1 //===-- SIFixSGPRLiveRanges.cpp - Fix SGPR live ranges ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 /// \file SALU instructions ignore the execution mask, so we need to modify the
11 /// live ranges of the registers they define in some cases.
13 /// The main case we need to handle is when a def is used in one side of a
14 /// branch and not another. For example:
25 /// Here we need the register allocator to avoid assigning any of the defs
26 /// inside of the IF to the same register as %def. In traditional live
27 /// interval analysis %def is not live inside the IF branch, however, since
28 /// SALU instructions inside of IF will be executed even if the branch is not
29 /// taken, there is the chance that one of the instructions will overwrite the
30 /// value of %def, so the use in ELSE will see the wrong value.
32 /// The strategy we use for solving this is to add an extra use after the ENDIF:
44 /// Adding this use will make the def live throughout the IF branch, which is
48 #include "SIInstrInfo.h"
49 #include "SIRegisterInfo.h"
50 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
51 #include "llvm/CodeGen/LiveVariables.h"
52 #include "llvm/CodeGen/MachineFunctionPass.h"
53 #include "llvm/CodeGen/MachineInstrBuilder.h"
54 #include "llvm/CodeGen/MachinePostDominators.h"
55 #include "llvm/CodeGen/MachineRegisterInfo.h"
56 #include "llvm/Support/Debug.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include "llvm/Target/TargetMachine.h"
62 #define DEBUG_TYPE "si-fix-sgpr-live-ranges"
66 class SIFixSGPRLiveRanges : public MachineFunctionPass {
71 SIFixSGPRLiveRanges() : MachineFunctionPass(ID) {
72 initializeSIFixSGPRLiveRangesPass(*PassRegistry::getPassRegistry());
75 bool runOnMachineFunction(MachineFunction &MF) override;
77 const char *getPassName() const override {
78 return "SI Fix SGPR live ranges";
81 void getAnalysisUsage(AnalysisUsage &AU) const override {
82 AU.addRequired<LiveIntervals>();
83 AU.addRequired<MachinePostDominatorTree>();
86 //AU.addPreserved<SlotIndexes>(); // XXX - This might be OK
87 AU.addPreserved<LiveIntervals>();
89 MachineFunctionPass::getAnalysisUsage(AU);
93 } // End anonymous namespace.
95 INITIALIZE_PASS_BEGIN(SIFixSGPRLiveRanges, DEBUG_TYPE,
96 "SI Fix SGPR Live Ranges", false, false)
97 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
98 INITIALIZE_PASS_DEPENDENCY(LiveVariables)
99 INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree)
100 INITIALIZE_PASS_END(SIFixSGPRLiveRanges, DEBUG_TYPE,
101 "SI Fix SGPR Live Ranges", false, false)
103 char SIFixSGPRLiveRanges::ID = 0;
105 char &llvm::SIFixSGPRLiveRangesID = SIFixSGPRLiveRanges::ID;
107 FunctionPass *llvm::createSIFixSGPRLiveRangesPass() {
108 return new SIFixSGPRLiveRanges();
111 bool SIFixSGPRLiveRanges::runOnMachineFunction(MachineFunction &MF) {
112 MachineRegisterInfo &MRI = MF.getRegInfo();
113 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
114 const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>(
115 MF.getSubtarget().getRegisterInfo());
117 MachinePostDominatorTree *PDT = &getAnalysis<MachinePostDominatorTree>();
118 std::vector<std::pair<unsigned, LiveRange *>> SGPRLiveRanges;
120 LiveIntervals *LIS = &getAnalysis<LiveIntervals>();
121 LiveVariables *LV = getAnalysisIfAvailable<LiveVariables>();
123 // First pass, collect all live intervals for SGPRs
124 for (const MachineBasicBlock &MBB : MF) {
125 for (const MachineInstr &MI : MBB) {
126 for (const MachineOperand &MO : MI.defs()) {
129 unsigned Def = MO.getReg();
130 if (TargetRegisterInfo::isVirtualRegister(Def)) {
131 if (TRI->isSGPRClass(MRI.getRegClass(Def))) {
132 // Only consider defs that are live outs. We don't care about def /
133 // use within the same block.
134 LiveRange &LR = LIS->getInterval(Def);
135 if (LIS->isLiveOutOfMBB(LR, &MBB))
136 SGPRLiveRanges.push_back(std::make_pair(Def, &LR));
138 } else if (TRI->isSGPRClass(TRI->getPhysRegClass(Def))) {
139 SGPRLiveRanges.push_back(
140 std::make_pair(Def, &LIS->getRegUnit(Def)));
146 // Second pass fix the intervals
147 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
149 MachineBasicBlock &MBB = *BI;
150 if (MBB.succ_size() < 2)
153 // We have structured control flow, so the number of successors should be
155 assert(MBB.succ_size() == 2);
156 MachineBasicBlock *SuccA = *MBB.succ_begin();
157 MachineBasicBlock *SuccB = *(++MBB.succ_begin());
158 MachineBasicBlock *NCD = PDT->findNearestCommonDominator(SuccA, SuccB);
163 MachineBasicBlock::iterator NCDTerm = NCD->getFirstTerminator();
165 if (NCDTerm != NCD->end() && NCDTerm->getOpcode() == AMDGPU::SI_ELSE) {
166 assert(NCD->succ_size() == 2);
167 // We want to make sure we insert the Use after the ENDIF, not after
169 NCD = PDT->findNearestCommonDominator(*NCD->succ_begin(),
170 *(++NCD->succ_begin()));
173 for (std::pair<unsigned, LiveRange*> RegLR : SGPRLiveRanges) {
174 unsigned Reg = RegLR.first;
175 LiveRange *LR = RegLR.second;
177 // FIXME: We could be smarter here. If the register is Live-In to one
178 // block, but the other doesn't have any SGPR defs, then there won't be a
179 // conflict. Also, if the branch condition is uniform then there will be
181 bool LiveInToA = LIS->isLiveInToMBB(*LR, SuccA);
182 bool LiveInToB = LIS->isLiveInToMBB(*LR, SuccB);
184 if (!LiveInToA && !LiveInToB) {
185 DEBUG(dbgs() << PrintReg(Reg, TRI, 0)
186 << " is live into neither successor\n");
190 if (LiveInToA && LiveInToB) {
191 DEBUG(dbgs() << PrintReg(Reg, TRI, 0)
192 << " is live into both successors\n");
196 // This interval is live in to one successor, but not the other, so
197 // we need to update its range so it is live in to both.
198 DEBUG(dbgs() << "Possible SGPR conflict detected for "
199 << PrintReg(Reg, TRI, 0) << " in " << *LR
200 << " BB#" << SuccA->getNumber() << ", BB#"
201 << SuccB->getNumber()
202 << " with NCD = BB#" << NCD->getNumber() << '\n');
204 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
205 "Not expecting to extend live range of physreg");
207 // FIXME: Need to figure out how to update LiveRange here so this pass
208 // will be able to preserve LiveInterval analysis.
209 MachineInstr *NCDSGPRUse =
210 BuildMI(*NCD, NCD->getFirstNonPHI(), DebugLoc(),
211 TII->get(AMDGPU::SGPR_USE))
212 .addReg(Reg, RegState::Implicit);
214 SlotIndex SI = LIS->InsertMachineInstrInMaps(NCDSGPRUse);
215 LIS->extendToIndices(*LR, SI.getRegSlot());
218 // TODO: This won't work post-SSA
219 LV->HandleVirtRegUse(Reg, NCD, NCDSGPRUse);
222 DEBUG(NCDSGPRUse->dump());