1 //===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief The AMDGPU target machine contains all of the hardware specific
12 /// information needed to emit code for R600 and SI GPUs.
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUTargetMachine.h"
17 #include "AMDGPUHSATargetObjectFile.h"
19 #include "AMDGPUTargetTransformInfo.h"
20 #include "R600ISelLowering.h"
21 #include "R600InstrInfo.h"
22 #include "R600MachineScheduler.h"
23 #include "SIISelLowering.h"
24 #include "SIInstrInfo.h"
25 #include "llvm/Analysis/Passes.h"
26 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/Passes.h"
30 #include "llvm/IR/Verifier.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/IR/LegacyPassManager.h"
33 #include "llvm/Support/TargetRegistry.h"
34 #include "llvm/Support/raw_os_ostream.h"
35 #include "llvm/Transforms/IPO.h"
36 #include "llvm/Transforms/Scalar.h"
37 #include <llvm/CodeGen/Passes.h>
41 extern "C" void LLVMInitializeAMDGPUTarget() {
42 // Register the target
43 RegisterTargetMachine<R600TargetMachine> X(TheAMDGPUTarget);
44 RegisterTargetMachine<GCNTargetMachine> Y(TheGCNTarget);
46 PassRegistry *PR = PassRegistry::getPassRegistry();
47 initializeSIFixSGPRLiveRangesPass(*PR);
48 initializeSIFixControlFlowLiveIntervalsPass(*PR);
49 initializeSILoadStoreOptimizerPass(*PR);
52 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
53 if (TT.getOS() == Triple::AMDHSA)
54 return make_unique<AMDGPUHSATargetObjectFile>();
56 return make_unique<TargetLoweringObjectFileELF>();
59 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
60 return new ScheduleDAGMILive(C, make_unique<R600SchedStrategy>());
63 static MachineSchedRegistry
64 SchedCustomRegistry("r600", "Run R600's custom scheduler",
65 createR600MachineScheduler);
67 static std::string computeDataLayout(const Triple &TT) {
68 std::string Ret = "e-p:32:32";
70 if (TT.getArch() == Triple::amdgcn) {
71 // 32-bit private, local, and region pointers. 64-bit global and constant.
72 Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64";
75 Ret += "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256"
76 "-v512:512-v1024:1024-v2048:2048-n32:64";
81 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
82 StringRef CPU, StringRef FS,
83 TargetOptions Options, Reloc::Model RM,
85 CodeGenOpt::Level OptLevel)
86 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
88 TLOF(createTLOF(getTargetTriple())), Subtarget(TT, CPU, FS, *this),
90 setRequiresStructuredCFG(true);
94 AMDGPUTargetMachine::~AMDGPUTargetMachine() { }
96 //===----------------------------------------------------------------------===//
97 // R600 Target Machine (R600 -> Cayman)
98 //===----------------------------------------------------------------------===//
100 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
101 StringRef FS, StringRef CPU,
102 TargetOptions Options, Reloc::Model RM,
103 CodeModel::Model CM, CodeGenOpt::Level OL)
104 : AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {}
106 //===----------------------------------------------------------------------===//
107 // GCN Target Machine (SI+)
108 //===----------------------------------------------------------------------===//
110 GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
111 StringRef FS, StringRef CPU,
112 TargetOptions Options, Reloc::Model RM,
113 CodeModel::Model CM, CodeGenOpt::Level OL)
114 : AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {}
116 //===----------------------------------------------------------------------===//
118 //===----------------------------------------------------------------------===//
121 class AMDGPUPassConfig : public TargetPassConfig {
123 AMDGPUPassConfig(TargetMachine *TM, PassManagerBase &PM)
124 : TargetPassConfig(TM, PM) {
126 // Exceptions and StackMaps are not supported, so these passes will never do
128 disablePass(&StackMapLivenessID);
129 disablePass(&FuncletLayoutID);
132 AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
133 return getTM<AMDGPUTargetMachine>();
137 createMachineScheduler(MachineSchedContext *C) const override {
138 const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
139 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
140 return createR600MachineScheduler(C);
144 void addIRPasses() override;
145 void addCodeGenPrepare() override;
146 bool addPreISel() override;
147 bool addInstSelector() override;
148 bool addGCPasses() override;
151 class R600PassConfig : public AMDGPUPassConfig {
153 R600PassConfig(TargetMachine *TM, PassManagerBase &PM)
154 : AMDGPUPassConfig(TM, PM) { }
156 bool addPreISel() override;
157 void addPreRegAlloc() override;
158 void addPreSched2() override;
159 void addPreEmitPass() override;
162 class GCNPassConfig : public AMDGPUPassConfig {
164 GCNPassConfig(TargetMachine *TM, PassManagerBase &PM)
165 : AMDGPUPassConfig(TM, PM) { }
166 bool addPreISel() override;
167 bool addInstSelector() override;
168 void addFastRegAlloc(FunctionPass *RegAllocPass) override;
169 void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
170 void addPreRegAlloc() override;
171 void addPostRegAlloc() override;
172 void addPreSched2() override;
173 void addPreEmitPass() override;
176 } // End of anonymous namespace
178 TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
179 return TargetIRAnalysis([this](const Function &F) {
180 return TargetTransformInfo(
181 AMDGPUTTIImpl(this, F.getParent()->getDataLayout()));
185 void AMDGPUPassConfig::addIRPasses() {
186 // Function calls are not supported, so make sure we inline everything.
187 addPass(createAMDGPUAlwaysInlinePass());
188 addPass(createAlwaysInlinerPass());
189 // We need to add the barrier noop pass, otherwise adding the function
190 // inlining pass will cause all of the PassConfigs passes to be run
191 // one function at a time, which means if we have a nodule with two
192 // functions, then we will generate code for the first function
193 // without ever running any passes on the second.
194 addPass(createBarrierNoopPass());
195 // Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
196 addPass(createAMDGPUOpenCLImageTypeLoweringPass());
197 TargetPassConfig::addIRPasses();
200 void AMDGPUPassConfig::addCodeGenPrepare() {
201 const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
202 if (ST.isPromoteAllocaEnabled()) {
203 addPass(createAMDGPUPromoteAlloca(ST));
204 addPass(createSROAPass());
206 TargetPassConfig::addCodeGenPrepare();
210 AMDGPUPassConfig::addPreISel() {
211 const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
212 addPass(createFlattenCFGPass());
213 if (ST.IsIRStructurizerEnabled())
214 addPass(createStructurizeCFGPass());
218 bool AMDGPUPassConfig::addInstSelector() {
219 addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
223 bool AMDGPUPassConfig::addGCPasses() {
224 // Do nothing. GC is not supported.
228 //===----------------------------------------------------------------------===//
230 //===----------------------------------------------------------------------===//
232 bool R600PassConfig::addPreISel() {
233 AMDGPUPassConfig::addPreISel();
234 addPass(createR600TextureIntrinsicsReplacer());
238 void R600PassConfig::addPreRegAlloc() {
239 addPass(createR600VectorRegMerger(*TM));
242 void R600PassConfig::addPreSched2() {
243 const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
244 addPass(createR600EmitClauseMarkers(), false);
245 if (ST.isIfCvtEnabled())
246 addPass(&IfConverterID, false);
247 addPass(createR600ClauseMergePass(*TM), false);
250 void R600PassConfig::addPreEmitPass() {
251 addPass(createAMDGPUCFGStructurizerPass(), false);
252 addPass(createR600ExpandSpecialInstrsPass(*TM), false);
253 addPass(&FinalizeMachineBundlesID, false);
254 addPass(createR600Packetizer(*TM), false);
255 addPass(createR600ControlFlowFinalizer(*TM), false);
258 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
259 return new R600PassConfig(this, PM);
262 //===----------------------------------------------------------------------===//
264 //===----------------------------------------------------------------------===//
266 bool GCNPassConfig::addPreISel() {
267 AMDGPUPassConfig::addPreISel();
268 addPass(createSinkingPass());
269 addPass(createSITypeRewriter());
270 addPass(createSIAnnotateControlFlowPass());
274 bool GCNPassConfig::addInstSelector() {
275 AMDGPUPassConfig::addInstSelector();
276 addPass(createSILowerI1CopiesPass());
277 addPass(createSIFixSGPRCopiesPass(*TM));
278 addPass(createSIFoldOperandsPass());
282 void GCNPassConfig::addPreRegAlloc() {
283 const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
285 // This needs to be run directly before register allocation because
286 // earlier passes might recompute live intervals.
287 // TODO: handle CodeGenOpt::None; fast RA ignores spill weights set by the pass
288 if (getOptLevel() > CodeGenOpt::None) {
289 insertPass(&MachineSchedulerID, &SIFixControlFlowLiveIntervalsID);
292 if (getOptLevel() > CodeGenOpt::None && ST.loadStoreOptEnabled()) {
293 // Don't do this with no optimizations since it throws away debug info by
294 // merging nonadjacent loads.
296 // This should be run after scheduling, but before register allocation. It
297 // also need extra copies to the address operand to be eliminated.
298 insertPass(&MachineSchedulerID, &SILoadStoreOptimizerID);
299 insertPass(&MachineSchedulerID, &RegisterCoalescerID);
301 addPass(createSIShrinkInstructionsPass(), false);
304 void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
305 addPass(&SIFixSGPRLiveRangesID);
306 TargetPassConfig::addFastRegAlloc(RegAllocPass);
309 void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
310 // We want to run this after LiveVariables is computed to avoid computing them
312 // FIXME: We shouldn't disable the verifier here. r249087 introduced a failure
313 // that needs to be fixed.
314 insertPass(&LiveVariablesID, &SIFixSGPRLiveRangesID, /*VerifyAfter=*/false);
315 TargetPassConfig::addOptimizedRegAlloc(RegAllocPass);
318 void GCNPassConfig::addPostRegAlloc() {
319 addPass(createSIPrepareScratchRegs(), false);
320 addPass(createSIShrinkInstructionsPass(), false);
323 void GCNPassConfig::addPreSched2() {
326 void GCNPassConfig::addPreEmitPass() {
327 addPass(createSIInsertWaits(*TM), false);
328 addPass(createSILowerControlFlowPass(*TM), false);
331 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
332 return new GCNPassConfig(this, PM);