1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUDiagnosticInfoUnsupported.h"
19 #include "AMDGPUFrameLowering.h"
20 #include "AMDGPUIntrinsicInfo.h"
21 #include "AMDGPURegisterInfo.h"
22 #include "AMDGPUSubtarget.h"
23 #include "R600MachineFunctionInfo.h"
24 #include "SIMachineFunctionInfo.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/DataLayout.h"
34 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
35 CCValAssign::LocInfo LocInfo,
36 ISD::ArgFlagsTy ArgFlags, CCState &State) {
37 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
38 ArgFlags.getOrigAlign());
39 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
44 #include "AMDGPUGenCallingConv.inc"
46 // Find a larger type to do a load / store of a vector with.
47 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
48 unsigned StoreSize = VT.getStoreSizeInBits();
50 return EVT::getIntegerVT(Ctx, StoreSize);
52 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
53 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
56 // Type for a vector that will be loaded to.
57 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
58 unsigned StoreSize = VT.getStoreSizeInBits();
60 return EVT::getIntegerVT(Ctx, 32);
62 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
65 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,
66 const AMDGPUSubtarget &STI)
67 : TargetLowering(TM), Subtarget(&STI) {
68 setOperationAction(ISD::Constant, MVT::i32, Legal);
69 setOperationAction(ISD::Constant, MVT::i64, Legal);
70 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
71 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
73 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
74 setOperationAction(ISD::BRIND, MVT::Other, Expand);
76 // This is totally unsupported, just custom lower to produce an error.
77 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
79 // We need to custom lower some of the intrinsics
80 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
82 // Library functions. These default to Expand, but we have instructions
84 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
85 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
86 setOperationAction(ISD::FPOW, MVT::f32, Legal);
87 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
88 setOperationAction(ISD::FABS, MVT::f32, Legal);
89 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
90 setOperationAction(ISD::FRINT, MVT::f32, Legal);
91 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
92 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
93 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
95 setOperationAction(ISD::FROUND, MVT::f32, Custom);
96 setOperationAction(ISD::FROUND, MVT::f64, Custom);
98 setOperationAction(ISD::FREM, MVT::f32, Custom);
99 setOperationAction(ISD::FREM, MVT::f64, Custom);
101 // v_mad_f32 does not support denormals according to some sources.
102 if (!Subtarget->hasFP32Denormals())
103 setOperationAction(ISD::FMAD, MVT::f32, Legal);
105 // Expand to fneg + fadd.
106 setOperationAction(ISD::FSUB, MVT::f64, Expand);
108 // Lower floating point store/load to integer store/load to reduce the number
109 // of patterns in tablegen.
110 setOperationAction(ISD::STORE, MVT::f32, Promote);
111 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
113 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
114 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
116 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
117 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
119 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
120 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
122 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
123 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
125 setOperationAction(ISD::STORE, MVT::f64, Promote);
126 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
128 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
129 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
131 // Custom lowering of vector stores is required for local address space
133 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
135 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
136 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
137 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
139 // XXX: This can be change to Custom, once ExpandVectorStores can
140 // handle 64-bit stores.
141 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
143 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
146 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
147 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
150 setOperationAction(ISD::LOAD, MVT::f32, Promote);
151 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
153 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
154 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
156 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
157 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
159 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
160 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
162 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
163 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
165 setOperationAction(ISD::LOAD, MVT::f64, Promote);
166 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
168 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
169 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
171 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
172 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
173 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
174 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
175 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
176 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
177 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
178 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
179 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
180 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
182 // There are no 64-bit extloads. These should be done as a 32-bit extload and
183 // an extension to 64-bit.
184 for (MVT VT : MVT::integer_valuetypes()) {
185 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
186 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
187 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
190 for (MVT VT : MVT::integer_vector_valuetypes()) {
191 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
192 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
193 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
194 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
195 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
196 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
197 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
198 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
199 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
200 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
201 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
202 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
205 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
207 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
208 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
209 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
210 setOperationAction(ISD::FRINT, MVT::f64, Custom);
211 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
214 if (!Subtarget->hasBFI()) {
215 // fcopysign can be done in a single instruction with BFI.
216 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
217 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
220 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
222 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
223 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
225 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, MVT::v8f16, Expand);
227 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
228 setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
229 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
230 setLoadExtAction(ISD::EXTLOAD, MVT::v8f64, MVT::v8f16, Expand);
232 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
233 setTruncStoreAction(MVT::v2f32, MVT::v2f16, Expand);
234 setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand);
235 setTruncStoreAction(MVT::v8f32, MVT::v8f16, Expand);
237 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
238 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
240 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
241 for (MVT VT : ScalarIntVTs) {
242 setOperationAction(ISD::SREM, VT, Expand);
243 setOperationAction(ISD::SDIV, VT, Expand);
245 // GPU does not have divrem function for signed or unsigned.
246 setOperationAction(ISD::SDIVREM, VT, Custom);
247 setOperationAction(ISD::UDIVREM, VT, Custom);
249 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
250 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
251 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
253 setOperationAction(ISD::BSWAP, VT, Expand);
254 setOperationAction(ISD::CTTZ, VT, Expand);
255 setOperationAction(ISD::CTLZ, VT, Expand);
258 if (!Subtarget->hasBCNT(32))
259 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
261 if (!Subtarget->hasBCNT(64))
262 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
264 // The hardware supports 32-bit ROTR, but not ROTL.
265 setOperationAction(ISD::ROTL, MVT::i32, Expand);
266 setOperationAction(ISD::ROTL, MVT::i64, Expand);
267 setOperationAction(ISD::ROTR, MVT::i64, Expand);
269 setOperationAction(ISD::MUL, MVT::i64, Expand);
270 setOperationAction(ISD::MULHU, MVT::i64, Expand);
271 setOperationAction(ISD::MULHS, MVT::i64, Expand);
272 setOperationAction(ISD::UDIV, MVT::i32, Expand);
273 setOperationAction(ISD::UREM, MVT::i32, Expand);
274 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
275 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
276 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
277 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
278 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
280 setOperationAction(ISD::SMIN, MVT::i32, Legal);
281 setOperationAction(ISD::UMIN, MVT::i32, Legal);
282 setOperationAction(ISD::SMAX, MVT::i32, Legal);
283 setOperationAction(ISD::UMAX, MVT::i32, Legal);
285 if (Subtarget->hasFFBH())
286 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom);
288 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
290 if (!Subtarget->hasFFBL())
291 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
293 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
295 setOperationAction(ISD::CTLZ, MVT::i64, Custom);
296 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
298 static const MVT::SimpleValueType VectorIntTypes[] = {
299 MVT::v2i32, MVT::v4i32
302 for (MVT VT : VectorIntTypes) {
303 // Expand the following operations for the current type by default.
304 setOperationAction(ISD::ADD, VT, Expand);
305 setOperationAction(ISD::AND, VT, Expand);
306 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
307 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
308 setOperationAction(ISD::MUL, VT, Expand);
309 setOperationAction(ISD::OR, VT, Expand);
310 setOperationAction(ISD::SHL, VT, Expand);
311 setOperationAction(ISD::SRA, VT, Expand);
312 setOperationAction(ISD::SRL, VT, Expand);
313 setOperationAction(ISD::ROTL, VT, Expand);
314 setOperationAction(ISD::ROTR, VT, Expand);
315 setOperationAction(ISD::SUB, VT, Expand);
316 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
317 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
318 setOperationAction(ISD::SDIV, VT, Expand);
319 setOperationAction(ISD::UDIV, VT, Expand);
320 setOperationAction(ISD::SREM, VT, Expand);
321 setOperationAction(ISD::UREM, VT, Expand);
322 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
323 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
324 setOperationAction(ISD::SDIVREM, VT, Custom);
325 setOperationAction(ISD::UDIVREM, VT, Expand);
326 setOperationAction(ISD::ADDC, VT, Expand);
327 setOperationAction(ISD::SUBC, VT, Expand);
328 setOperationAction(ISD::ADDE, VT, Expand);
329 setOperationAction(ISD::SUBE, VT, Expand);
330 setOperationAction(ISD::SELECT, VT, Expand);
331 setOperationAction(ISD::VSELECT, VT, Expand);
332 setOperationAction(ISD::SELECT_CC, VT, Expand);
333 setOperationAction(ISD::XOR, VT, Expand);
334 setOperationAction(ISD::BSWAP, VT, Expand);
335 setOperationAction(ISD::CTPOP, VT, Expand);
336 setOperationAction(ISD::CTTZ, VT, Expand);
337 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
338 setOperationAction(ISD::CTLZ, VT, Expand);
339 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
340 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
343 static const MVT::SimpleValueType FloatVectorTypes[] = {
344 MVT::v2f32, MVT::v4f32
347 for (MVT VT : FloatVectorTypes) {
348 setOperationAction(ISD::FABS, VT, Expand);
349 setOperationAction(ISD::FMINNUM, VT, Expand);
350 setOperationAction(ISD::FMAXNUM, VT, Expand);
351 setOperationAction(ISD::FADD, VT, Expand);
352 setOperationAction(ISD::FCEIL, VT, Expand);
353 setOperationAction(ISD::FCOS, VT, Expand);
354 setOperationAction(ISD::FDIV, VT, Expand);
355 setOperationAction(ISD::FEXP2, VT, Expand);
356 setOperationAction(ISD::FLOG2, VT, Expand);
357 setOperationAction(ISD::FREM, VT, Expand);
358 setOperationAction(ISD::FPOW, VT, Expand);
359 setOperationAction(ISD::FFLOOR, VT, Expand);
360 setOperationAction(ISD::FTRUNC, VT, Expand);
361 setOperationAction(ISD::FMUL, VT, Expand);
362 setOperationAction(ISD::FMA, VT, Expand);
363 setOperationAction(ISD::FRINT, VT, Expand);
364 setOperationAction(ISD::FNEARBYINT, VT, Expand);
365 setOperationAction(ISD::FSQRT, VT, Expand);
366 setOperationAction(ISD::FSIN, VT, Expand);
367 setOperationAction(ISD::FSUB, VT, Expand);
368 setOperationAction(ISD::FNEG, VT, Expand);
369 setOperationAction(ISD::SELECT, VT, Expand);
370 setOperationAction(ISD::VSELECT, VT, Expand);
371 setOperationAction(ISD::SELECT_CC, VT, Expand);
372 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
373 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
376 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
377 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
379 setTargetDAGCombine(ISD::SHL);
380 setTargetDAGCombine(ISD::MUL);
381 setTargetDAGCombine(ISD::SELECT);
382 setTargetDAGCombine(ISD::SELECT_CC);
383 setTargetDAGCombine(ISD::STORE);
385 setTargetDAGCombine(ISD::FADD);
386 setTargetDAGCombine(ISD::FSUB);
388 setBooleanContents(ZeroOrNegativeOneBooleanContent);
389 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
391 setSchedulingPreference(Sched::RegPressure);
392 setJumpIsExpensive(true);
394 // SI at least has hardware support for floating point exceptions, but no way
395 // of using or handling them is implemented. They are also optional in OpenCL
397 setHasFloatingPointExceptions(false);
399 setSelectIsExpensive(false);
400 PredictableSelectIsExpensive = false;
402 setFsqrtIsCheap(true);
404 // We want to find all load dependencies for long chains of stores to enable
405 // merging into very wide vectors. The problem is with vectors with > 4
406 // elements. MergeConsecutiveStores will attempt to merge these because x8/x16
407 // vectors are a legal type, even though we have to split the loads
408 // usually. When we can more precisely specify load legality per address
409 // space, we should be able to make FindBetterChain/MergeConsecutiveStores
410 // smarter so that they can figure out what to do in 2 iterations without all
411 // N > 4 stores on the same chain.
412 GatherAllAliasesMaxDepth = 16;
414 // FIXME: Need to really handle these.
415 MaxStoresPerMemcpy = 4096;
416 MaxStoresPerMemmove = 4096;
417 MaxStoresPerMemset = 4096;
420 //===----------------------------------------------------------------------===//
421 // Target Information
422 //===----------------------------------------------------------------------===//
424 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
428 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
432 // The backend supports 32 and 64 bit floating point immediates.
433 // FIXME: Why are we reporting vectors of FP immediates as legal?
434 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
435 EVT ScalarVT = VT.getScalarType();
436 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
439 // We don't want to shrink f64 / f32 constants.
440 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
441 EVT ScalarVT = VT.getScalarType();
442 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
445 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
449 unsigned NewSize = NewVT.getStoreSizeInBits();
451 // If we are reducing to a 32-bit load, this is always better.
455 EVT OldVT = N->getValueType(0);
456 unsigned OldSize = OldVT.getStoreSizeInBits();
458 // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
459 // extloads, so doing one requires using a buffer_load. In cases where we
460 // still couldn't use a scalar load, using the wider load shouldn't really
463 // If the old size already had to be an extload, there's no harm in continuing
464 // to reduce the width.
465 return (OldSize < 32);
468 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
470 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
473 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
474 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
476 return ((LScalarSize <= CastScalarSize) ||
477 (CastScalarSize >= 32) ||
481 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
482 // profitable with the expansion for 64-bit since it's generally good to
484 // FIXME: These should really have the size as a parameter.
485 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
489 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
493 //===---------------------------------------------------------------------===//
495 //===---------------------------------------------------------------------===//
497 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
498 assert(VT.isFloatingPoint());
499 return VT == MVT::f32 || VT == MVT::f64;
502 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
503 assert(VT.isFloatingPoint());
504 return VT == MVT::f32 || VT == MVT::f64;
507 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,
513 bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {
514 // There are few operations which truly have vector input operands. Any vector
515 // operation is going to involve operations on each component, and a
516 // build_vector will be a copy per element, so it always makes sense to use a
517 // build_vector input in place of the extracted element to avoid a copy into a
520 // We should probably only do this if all users are extracts only, but this
521 // should be the common case.
525 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
526 // Truncate is just accessing a subregister.
527 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
530 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
531 // Truncate is just accessing a subregister.
532 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
533 (Dest->getPrimitiveSizeInBits() % 32 == 0);
536 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
537 unsigned SrcSize = Src->getScalarSizeInBits();
538 unsigned DestSize = Dest->getScalarSizeInBits();
540 return SrcSize == 32 && DestSize == 64;
543 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
544 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
545 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
546 // this will enable reducing 64-bit operations the 32-bit, which is always
548 return Src == MVT::i32 && Dest == MVT::i64;
551 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
552 return isZExtFree(Val.getValueType(), VT2);
555 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
556 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
557 // limited number of native 64-bit operations. Shrinking an operation to fit
558 // in a single 32-bit register should always be helpful. As currently used,
559 // this is much less general than the name suggests, and is only used in
560 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
561 // not profitable, and may actually be harmful.
562 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
565 //===---------------------------------------------------------------------===//
566 // TargetLowering Callbacks
567 //===---------------------------------------------------------------------===//
569 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
570 const SmallVectorImpl<ISD::InputArg> &Ins) const {
572 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
575 SDValue AMDGPUTargetLowering::LowerReturn(
577 CallingConv::ID CallConv,
579 const SmallVectorImpl<ISD::OutputArg> &Outs,
580 const SmallVectorImpl<SDValue> &OutVals,
581 SDLoc DL, SelectionDAG &DAG) const {
582 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
585 //===---------------------------------------------------------------------===//
586 // Target specific lowering
587 //===---------------------------------------------------------------------===//
589 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
590 SmallVectorImpl<SDValue> &InVals) const {
591 SDValue Callee = CLI.Callee;
592 SelectionDAG &DAG = CLI.DAG;
594 const Function &Fn = *DAG.getMachineFunction().getFunction();
596 StringRef FuncName("<unknown>");
598 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
599 FuncName = G->getSymbol();
600 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
601 FuncName = G->getGlobal()->getName();
603 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
604 DAG.getContext()->diagnose(NoCalls);
608 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
609 SelectionDAG &DAG) const {
610 const Function &Fn = *DAG.getMachineFunction().getFunction();
612 DiagnosticInfoUnsupported NoDynamicAlloca(Fn, "dynamic alloca");
613 DAG.getContext()->diagnose(NoDynamicAlloca);
617 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
618 SelectionDAG &DAG) const {
619 switch (Op.getOpcode()) {
621 Op.getNode()->dump();
622 llvm_unreachable("Custom lowering code for this"
623 "instruction is not implemented yet!");
625 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
626 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
627 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
628 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
629 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
630 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
631 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
632 case ISD::FREM: return LowerFREM(Op, DAG);
633 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
634 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
635 case ISD::FRINT: return LowerFRINT(Op, DAG);
636 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
637 case ISD::FROUND: return LowerFROUND(Op, DAG);
638 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
639 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
640 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
641 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
642 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
644 case ISD::CTLZ_ZERO_UNDEF:
645 return LowerCTLZ(Op, DAG);
646 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
651 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
652 SmallVectorImpl<SDValue> &Results,
653 SelectionDAG &DAG) const {
654 switch (N->getOpcode()) {
655 case ISD::SIGN_EXTEND_INREG:
656 // Different parts of legalization seem to interpret which type of
657 // sign_extend_inreg is the one to check for custom lowering. The extended
658 // from type is what really matters, but some places check for custom
659 // lowering of the result type. This results in trying to use
660 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
661 // nothing here and let the illegal result integer be handled normally.
664 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
668 Results.push_back(SDValue(Node, 0));
669 Results.push_back(SDValue(Node, 1));
670 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
672 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
676 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
677 if (Lowered.getNode())
678 Results.push_back(Lowered);
686 // FIXME: This implements accesses to initialized globals in the constant
687 // address space by copying them to private and accessing that. It does not
688 // properly handle illegal types or vectors. The private vector loads are not
689 // scalarized, and the illegal scalars hit an assertion. This technique will not
690 // work well with large initializers, and this should eventually be
691 // removed. Initialized globals should be placed into a data section that the
692 // runtime will load into a buffer before the kernel is executed. Uses of the
693 // global need to be replaced with a pointer loaded from an implicit kernel
694 // argument into this buffer holding the copy of the data, which will remove the
695 // need for any of this.
696 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
697 const GlobalValue *GV,
698 const SDValue &InitPtr,
700 SelectionDAG &DAG) const {
701 const DataLayout &TD = DAG.getDataLayout();
703 Type *InitTy = Init->getType();
705 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
706 EVT VT = EVT::getEVT(InitTy);
707 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
708 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, DL, VT), InitPtr,
709 MachinePointerInfo(UndefValue::get(PtrTy)), false,
710 false, TD.getPrefTypeAlignment(InitTy));
713 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
714 EVT VT = EVT::getEVT(CFP->getType());
715 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
716 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, DL, VT), InitPtr,
717 MachinePointerInfo(UndefValue::get(PtrTy)), false,
718 false, TD.getPrefTypeAlignment(CFP->getType()));
721 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
722 const StructLayout *SL = TD.getStructLayout(ST);
724 EVT PtrVT = InitPtr.getValueType();
725 SmallVector<SDValue, 8> Chains;
727 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
728 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), DL, PtrVT);
729 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
731 Constant *Elt = Init->getAggregateElement(I);
732 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
735 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
738 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
739 EVT PtrVT = InitPtr.getValueType();
741 unsigned NumElements;
742 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
743 NumElements = AT->getNumElements();
744 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
745 NumElements = VT->getNumElements();
747 llvm_unreachable("Unexpected type");
749 unsigned EltSize = TD.getTypeAllocSize(SeqTy->getElementType());
750 SmallVector<SDValue, 8> Chains;
751 for (unsigned i = 0; i < NumElements; ++i) {
752 SDValue Offset = DAG.getConstant(i * EltSize, DL, PtrVT);
753 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
755 Constant *Elt = Init->getAggregateElement(i);
756 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
759 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
762 if (isa<UndefValue>(Init)) {
763 EVT VT = EVT::getEVT(InitTy);
764 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
765 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
766 MachinePointerInfo(UndefValue::get(PtrTy)), false,
767 false, TD.getPrefTypeAlignment(InitTy));
771 llvm_unreachable("Unhandled constant initializer");
774 static bool hasDefinedInitializer(const GlobalValue *GV) {
775 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
776 if (!GVar || !GVar->hasInitializer())
779 if (isa<UndefValue>(GVar->getInitializer()))
785 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
787 SelectionDAG &DAG) const {
789 const DataLayout &DL = DAG.getDataLayout();
790 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
791 const GlobalValue *GV = G->getGlobal();
793 switch (G->getAddressSpace()) {
794 case AMDGPUAS::LOCAL_ADDRESS: {
795 // XXX: What does the value of G->getOffset() mean?
796 assert(G->getOffset() == 0 &&
797 "Do not know what to do with an non-zero offset");
799 // TODO: We could emit code to handle the initialization somewhere.
800 if (hasDefinedInitializer(GV))
804 if (MFI->LocalMemoryObjects.count(GV) == 0) {
805 uint64_t Size = DL.getTypeAllocSize(GV->getType()->getElementType());
806 Offset = MFI->LDSSize;
807 MFI->LocalMemoryObjects[GV] = Offset;
808 // XXX: Account for alignment?
809 MFI->LDSSize += Size;
811 Offset = MFI->LocalMemoryObjects[GV];
814 return DAG.getConstant(Offset, SDLoc(Op),
815 getPointerTy(DL, AMDGPUAS::LOCAL_ADDRESS));
817 case AMDGPUAS::CONSTANT_ADDRESS: {
818 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
819 Type *EltType = GV->getType()->getElementType();
820 unsigned Size = DL.getTypeAllocSize(EltType);
821 unsigned Alignment = DL.getPrefTypeAlignment(EltType);
823 MVT PrivPtrVT = getPointerTy(DL, AMDGPUAS::PRIVATE_ADDRESS);
824 MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
826 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
827 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
829 const GlobalVariable *Var = cast<GlobalVariable>(GV);
830 if (!Var->hasInitializer()) {
831 // This has no use, but bugpoint will hit it.
832 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
835 const Constant *Init = Var->getInitializer();
836 SmallVector<SDNode*, 8> WorkList;
838 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
839 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
840 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
842 WorkList.push_back(*I);
844 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
845 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
846 E = WorkList.end(); I != E; ++I) {
847 SmallVector<SDValue, 8> Ops;
848 Ops.push_back(Chain);
849 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
850 Ops.push_back((*I)->getOperand(i));
852 DAG.UpdateNodeOperands(*I, Ops);
854 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
858 const Function &Fn = *DAG.getMachineFunction().getFunction();
859 DiagnosticInfoUnsupported BadInit(Fn,
860 "initializer for address space");
861 DAG.getContext()->diagnose(BadInit);
865 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
866 SelectionDAG &DAG) const {
867 SmallVector<SDValue, 8> Args;
869 for (const SDUse &U : Op->ops())
870 DAG.ExtractVectorElements(U.get(), Args);
872 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
875 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
876 SelectionDAG &DAG) const {
878 SmallVector<SDValue, 8> Args;
879 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
880 EVT VT = Op.getValueType();
881 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
882 VT.getVectorNumElements());
884 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
887 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
888 SelectionDAG &DAG) const {
890 MachineFunction &MF = DAG.getMachineFunction();
891 const AMDGPUFrameLowering *TFL = Subtarget->getFrameLowering();
893 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
895 unsigned FrameIndex = FIN->getIndex();
896 unsigned IgnoredFrameReg;
898 TFL->getFrameIndexReference(MF, FrameIndex, IgnoredFrameReg);
899 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF), SDLoc(Op),
903 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
904 SelectionDAG &DAG) const {
905 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
907 EVT VT = Op.getValueType();
909 switch (IntrinsicID) {
911 case AMDGPUIntrinsic::AMDGPU_abs:
912 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
913 return LowerIntrinsicIABS(Op, DAG);
914 case AMDGPUIntrinsic::AMDGPU_lrp:
915 return LowerIntrinsicLRP(Op, DAG);
917 case AMDGPUIntrinsic::AMDGPU_clamp:
918 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
919 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
920 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
922 case Intrinsic::AMDGPU_div_scale: {
923 // 3rd parameter required to be a constant.
924 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
926 return DAG.getUNDEF(VT);
928 // Translate to the operands expected by the machine instruction. The
929 // first parameter must be the same as the first instruction.
930 SDValue Numerator = Op.getOperand(1);
931 SDValue Denominator = Op.getOperand(2);
933 // Note this order is opposite of the machine instruction's operations,
934 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
935 // intrinsic has the numerator as the first operand to match a normal
936 // division operation.
938 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
940 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
941 Denominator, Numerator);
944 case Intrinsic::AMDGPU_div_fmas:
945 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
946 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
949 case Intrinsic::AMDGPU_div_fixup:
950 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
951 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
953 case Intrinsic::AMDGPU_trig_preop:
954 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
955 Op.getOperand(1), Op.getOperand(2));
957 case Intrinsic::AMDGPU_rcp:
958 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
960 case Intrinsic::AMDGPU_rsq:
961 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
963 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
964 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
966 case Intrinsic::AMDGPU_rsq_clamped:
967 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
968 Type *Type = VT.getTypeForEVT(*DAG.getContext());
969 APFloat Max = APFloat::getLargest(Type->getFltSemantics());
970 APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
972 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
973 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
974 DAG.getConstantFP(Max, DL, VT));
975 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
976 DAG.getConstantFP(Min, DL, VT));
978 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
981 case Intrinsic::AMDGPU_ldexp:
982 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
985 case AMDGPUIntrinsic::AMDGPU_imax:
986 return DAG.getNode(ISD::SMAX, DL, VT, Op.getOperand(1),
988 case AMDGPUIntrinsic::AMDGPU_umax:
989 return DAG.getNode(ISD::UMAX, DL, VT, Op.getOperand(1),
991 case AMDGPUIntrinsic::AMDGPU_imin:
992 return DAG.getNode(ISD::SMIN, DL, VT, Op.getOperand(1),
994 case AMDGPUIntrinsic::AMDGPU_umin:
995 return DAG.getNode(ISD::UMIN, DL, VT, Op.getOperand(1),
998 case AMDGPUIntrinsic::AMDGPU_umul24:
999 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
1000 Op.getOperand(1), Op.getOperand(2));
1002 case AMDGPUIntrinsic::AMDGPU_imul24:
1003 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
1004 Op.getOperand(1), Op.getOperand(2));
1006 case AMDGPUIntrinsic::AMDGPU_umad24:
1007 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
1008 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
1010 case AMDGPUIntrinsic::AMDGPU_imad24:
1011 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
1012 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
1014 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
1015 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
1017 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
1018 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
1020 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
1021 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
1023 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
1024 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
1026 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
1027 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
1032 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
1033 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
1038 case AMDGPUIntrinsic::AMDGPU_bfi:
1039 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
1044 case AMDGPUIntrinsic::AMDGPU_bfm:
1045 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
1049 case Intrinsic::AMDGPU_class:
1050 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, VT,
1051 Op.getOperand(1), Op.getOperand(2));
1053 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
1054 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
1056 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
1057 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
1058 case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
1059 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
1060 case AMDGPUIntrinsic::AMDGPU_brev: // Legacy name
1061 return DAG.getNode(ISD::BITREVERSE, DL, VT, Op.getOperand(1));
1065 ///IABS(a) = SMAX(sub(0, a), a)
1066 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
1067 SelectionDAG &DAG) const {
1069 EVT VT = Op.getValueType();
1070 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1073 return DAG.getNode(ISD::SMAX, DL, VT, Neg, Op.getOperand(1));
1076 /// Linear Interpolation
1077 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
1078 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
1079 SelectionDAG &DAG) const {
1081 EVT VT = Op.getValueType();
1082 // TODO: Should this propagate fast-math-flags?
1083 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
1084 DAG.getConstantFP(1.0f, DL, MVT::f32),
1086 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
1088 return DAG.getNode(ISD::FADD, DL, VT,
1089 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
1093 /// \brief Generate Min/Max node
1094 SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(SDLoc DL,
1101 DAGCombinerInfo &DCI) const {
1102 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1105 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1108 SelectionDAG &DAG = DCI.DAG;
1109 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1118 case ISD::SETFALSE2:
1127 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1128 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1134 // Ordered. Assume ordered for undefined.
1136 // Only do this after legalization to avoid interfering with other combines
1137 // which might occur.
1138 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1139 !DCI.isCalledByLegalizer())
1142 // We need to permute the operands to get the correct NaN behavior. The
1143 // selected operand is the second one based on the failing compare with NaN,
1144 // so permute it based on the compare type the hardware uses.
1146 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1147 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1152 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1153 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1159 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1160 !DCI.isCalledByLegalizer())
1164 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1165 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1167 case ISD::SETCC_INVALID:
1168 llvm_unreachable("Invalid setcc condcode!");
1173 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
1174 SelectionDAG &DAG) const {
1175 LoadSDNode *Load = cast<LoadSDNode>(Op);
1176 EVT MemVT = Load->getMemoryVT();
1177 EVT MemEltVT = MemVT.getVectorElementType();
1179 EVT LoadVT = Op.getValueType();
1180 EVT EltVT = LoadVT.getVectorElementType();
1181 EVT PtrVT = Load->getBasePtr().getValueType();
1183 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1184 SmallVector<SDValue, 8> Loads;
1185 SmallVector<SDValue, 8> Chains;
1188 unsigned MemEltSize = MemEltVT.getStoreSize();
1189 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1191 for (unsigned i = 0; i < NumElts; ++i) {
1192 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1193 DAG.getConstant(i * MemEltSize, SL, PtrVT));
1196 = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1197 Load->getChain(), Ptr,
1198 SrcValue.getWithOffset(i * MemEltSize),
1199 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1200 Load->isInvariant(), Load->getAlignment());
1201 Loads.push_back(NewLoad.getValue(0));
1202 Chains.push_back(NewLoad.getValue(1));
1206 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1207 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1210 return DAG.getMergeValues(Ops, SL);
1213 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1214 SelectionDAG &DAG) const {
1215 EVT VT = Op.getValueType();
1217 // If this is a 2 element vector, we really want to scalarize and not create
1218 // weird 1 element vectors.
1219 if (VT.getVectorNumElements() == 2)
1220 return ScalarizeVectorLoad(Op, DAG);
1222 LoadSDNode *Load = cast<LoadSDNode>(Op);
1223 SDValue BasePtr = Load->getBasePtr();
1224 EVT PtrVT = BasePtr.getValueType();
1225 EVT MemVT = Load->getMemoryVT();
1228 const MachinePointerInfo &SrcValue = Load->getMemOperand()->getPointerInfo();
1231 EVT LoMemVT, HiMemVT;
1234 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1235 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1236 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1238 unsigned Size = LoMemVT.getStoreSize();
1239 unsigned BaseAlign = Load->getAlignment();
1240 unsigned HiAlign = MinAlign(BaseAlign, Size);
1243 = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1244 Load->getChain(), BasePtr,
1246 LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1247 Load->isInvariant(), BaseAlign);
1249 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1250 DAG.getConstant(Size, SL, PtrVT));
1253 = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1254 Load->getChain(), HiPtr,
1255 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1256 HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1257 Load->isInvariant(), HiAlign);
1260 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1261 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1262 LoLoad.getValue(1), HiLoad.getValue(1))
1265 return DAG.getMergeValues(Ops, SL);
1268 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1269 SelectionDAG &DAG) const {
1270 StoreSDNode *Store = cast<StoreSDNode>(Op);
1271 EVT MemVT = Store->getMemoryVT();
1272 unsigned MemBits = MemVT.getSizeInBits();
1274 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1275 // truncating store into an i32 store.
1276 // XXX: We could also handle optimize other vector bitwidths.
1277 if (!MemVT.isVector() || MemBits > 32) {
1282 SDValue Value = Store->getValue();
1283 EVT VT = Value.getValueType();
1284 EVT ElemVT = VT.getVectorElementType();
1285 SDValue Ptr = Store->getBasePtr();
1286 EVT MemEltVT = MemVT.getVectorElementType();
1287 unsigned MemEltBits = MemEltVT.getSizeInBits();
1288 unsigned MemNumElements = MemVT.getVectorNumElements();
1289 unsigned PackedSize = MemVT.getStoreSizeInBits();
1290 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, DL, MVT::i32);
1292 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1294 SDValue PackedValue;
1295 for (unsigned i = 0; i < MemNumElements; ++i) {
1296 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1297 DAG.getConstant(i, DL, MVT::i32));
1298 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1299 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1301 SDValue Shift = DAG.getConstant(MemEltBits * i, DL, MVT::i32);
1302 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1307 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1311 if (PackedSize < 32) {
1312 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1313 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1314 Store->getMemOperand()->getPointerInfo(),
1316 Store->isNonTemporal(), Store->isVolatile(),
1317 Store->getAlignment());
1320 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1321 Store->getMemOperand()->getPointerInfo(),
1322 Store->isVolatile(), Store->isNonTemporal(),
1323 Store->getAlignment());
1326 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
1327 SelectionDAG &DAG) const {
1328 StoreSDNode *Store = cast<StoreSDNode>(Op);
1329 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1330 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1331 EVT PtrVT = Store->getBasePtr().getValueType();
1332 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1335 SmallVector<SDValue, 8> Chains;
1337 unsigned EltSize = MemEltVT.getStoreSize();
1338 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1340 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1341 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1343 DAG.getConstant(i, SL, MVT::i32));
1345 SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), SL, PtrVT);
1346 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
1348 DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1349 SrcValue.getWithOffset(i * EltSize),
1350 MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
1351 Store->getAlignment());
1352 Chains.push_back(NewStore);
1355 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1358 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1359 SelectionDAG &DAG) const {
1360 StoreSDNode *Store = cast<StoreSDNode>(Op);
1361 SDValue Val = Store->getValue();
1362 EVT VT = Val.getValueType();
1364 // If this is a 2 element vector, we really want to scalarize and not create
1365 // weird 1 element vectors.
1366 if (VT.getVectorNumElements() == 2)
1367 return ScalarizeVectorStore(Op, DAG);
1369 EVT MemVT = Store->getMemoryVT();
1370 SDValue Chain = Store->getChain();
1371 SDValue BasePtr = Store->getBasePtr();
1375 EVT LoMemVT, HiMemVT;
1378 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1379 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1380 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1382 EVT PtrVT = BasePtr.getValueType();
1383 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1384 DAG.getConstant(LoMemVT.getStoreSize(), SL,
1387 const MachinePointerInfo &SrcValue = Store->getMemOperand()->getPointerInfo();
1388 unsigned BaseAlign = Store->getAlignment();
1389 unsigned Size = LoMemVT.getStoreSize();
1390 unsigned HiAlign = MinAlign(BaseAlign, Size);
1393 = DAG.getTruncStore(Chain, SL, Lo,
1397 Store->isNonTemporal(),
1398 Store->isVolatile(),
1401 = DAG.getTruncStore(Chain, SL, Hi,
1403 SrcValue.getWithOffset(Size),
1405 Store->isNonTemporal(),
1406 Store->isVolatile(),
1409 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1413 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1415 LoadSDNode *Load = cast<LoadSDNode>(Op);
1416 ISD::LoadExtType ExtType = Load->getExtensionType();
1417 EVT VT = Op.getValueType();
1418 EVT MemVT = Load->getMemoryVT();
1420 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1421 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1422 // FIXME: Copied from PPC
1423 // First, load into 32 bits, then truncate to 1 bit.
1425 SDValue Chain = Load->getChain();
1426 SDValue BasePtr = Load->getBasePtr();
1427 MachineMemOperand *MMO = Load->getMemOperand();
1429 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1430 BasePtr, MVT::i8, MMO);
1433 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1437 return DAG.getMergeValues(Ops, DL);
1440 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1441 Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1442 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1445 // <SI && AS=PRIVATE && EXTLOAD && size < 32bit,
1446 // register (2-)byte extract.
1448 // Get Register holding the target.
1449 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1450 DAG.getConstant(2, DL, MVT::i32));
1451 // Load the Register.
1452 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1453 Load->getChain(), Ptr,
1454 DAG.getTargetConstant(0, DL, MVT::i32),
1457 // Get offset within the register.
1458 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1460 DAG.getConstant(0x3, DL, MVT::i32));
1462 // Bit offset of target byte (byteIdx * 8).
1463 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1464 DAG.getConstant(3, DL, MVT::i32));
1466 // Shift to the right.
1467 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1469 // Eliminate the upper bits by setting them to ...
1470 EVT MemEltVT = MemVT.getScalarType();
1473 if (ExtType == ISD::SEXTLOAD) {
1474 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1477 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1481 return DAG.getMergeValues(Ops, DL);
1486 DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1490 return DAG.getMergeValues(Ops, DL);
1493 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1495 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1496 if (Result.getNode()) {
1500 StoreSDNode *Store = cast<StoreSDNode>(Op);
1501 SDValue Chain = Store->getChain();
1502 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1503 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1504 Store->getValue().getValueType().isVector()) {
1505 return SplitVectorStore(Op, DAG);
1508 EVT MemVT = Store->getMemoryVT();
1509 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1510 MemVT.bitsLT(MVT::i32)) {
1512 if (Store->getMemoryVT() == MVT::i8) {
1514 } else if (Store->getMemoryVT() == MVT::i16) {
1517 SDValue BasePtr = Store->getBasePtr();
1518 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1519 DAG.getConstant(2, DL, MVT::i32));
1520 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1522 DAG.getTargetConstant(0, DL, MVT::i32));
1524 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1525 DAG.getConstant(0x3, DL, MVT::i32));
1527 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1528 DAG.getConstant(3, DL, MVT::i32));
1530 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1533 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1535 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1536 MaskedValue, ShiftAmt);
1538 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32,
1539 DAG.getConstant(Mask, DL, MVT::i32),
1541 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1542 DAG.getConstant(0xffffffff, DL, MVT::i32));
1543 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1545 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1546 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1548 DAG.getTargetConstant(0, DL, MVT::i32));
1553 // This is a shortcut for integer division because we have fast i32<->f32
1554 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1555 // float is enough to accurately represent up to a 24-bit integer.
1556 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
1558 EVT VT = Op.getValueType();
1559 SDValue LHS = Op.getOperand(0);
1560 SDValue RHS = Op.getOperand(1);
1561 MVT IntVT = MVT::i32;
1562 MVT FltVT = MVT::f32;
1564 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1565 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1567 if (VT.isVector()) {
1568 unsigned NElts = VT.getVectorNumElements();
1569 IntVT = MVT::getVectorVT(MVT::i32, NElts);
1570 FltVT = MVT::getVectorVT(MVT::f32, NElts);
1573 unsigned BitSize = VT.getScalarType().getSizeInBits();
1575 SDValue jq = DAG.getConstant(1, DL, IntVT);
1578 // char|short jq = ia ^ ib;
1579 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1581 // jq = jq >> (bitsize - 2)
1582 jq = DAG.getNode(ISD::SRA, DL, VT, jq,
1583 DAG.getConstant(BitSize - 2, DL, VT));
1586 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));
1589 jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1592 // int ia = (int)LHS;
1594 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
1596 // int ib, (int)RHS;
1598 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
1600 // float fa = (float)ia;
1601 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1603 // float fb = (float)ib;
1604 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1606 // TODO: Should this propagate fast-math-flags?
1607 // float fq = native_divide(fa, fb);
1608 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1609 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1612 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1614 // float fqneg = -fq;
1615 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1617 // float fr = mad(fqneg, fb, fa);
1618 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1619 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1621 // int iq = (int)fq;
1622 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1625 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1628 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1630 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
1632 // int cv = fr >= fb;
1633 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1635 // jq = (cv ? jq : 0);
1636 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));
1638 // dst = trunc/extend to legal type
1639 iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
1642 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1644 // Rem needs compensation, it's easier to recompute it
1645 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1646 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1652 return DAG.getMergeValues(Res, DL);
1655 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1657 SmallVectorImpl<SDValue> &Results) const {
1658 assert(Op.getValueType() == MVT::i64);
1661 EVT VT = Op.getValueType();
1662 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1664 SDValue one = DAG.getConstant(1, DL, HalfVT);
1665 SDValue zero = DAG.getConstant(0, DL, HalfVT);
1668 SDValue LHS = Op.getOperand(0);
1669 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
1670 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
1672 SDValue RHS = Op.getOperand(1);
1673 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
1674 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
1676 if (VT == MVT::i64 &&
1677 DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
1678 DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) {
1680 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1683 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(0), zero);
1684 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(1), zero);
1685 Results.push_back(DIV);
1686 Results.push_back(REM);
1690 // Get Speculative values
1691 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1692 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1694 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
1695 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, zero);
1697 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
1698 SDValue DIV_Lo = zero;
1700 const unsigned halfBitWidth = HalfVT.getSizeInBits();
1702 for (unsigned i = 0; i < halfBitWidth; ++i) {
1703 const unsigned bitPos = halfBitWidth - i - 1;
1704 SDValue POS = DAG.getConstant(bitPos, DL, HalfVT);
1705 // Get value of high bit
1706 SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1707 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
1708 HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
1711 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));
1713 REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
1715 SDValue BIT = DAG.getConstant(1 << bitPos, DL, HalfVT);
1716 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
1718 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1721 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1722 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1725 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
1726 Results.push_back(DIV);
1727 Results.push_back(REM);
1730 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1731 SelectionDAG &DAG) const {
1733 EVT VT = Op.getValueType();
1735 if (VT == MVT::i64) {
1736 SmallVector<SDValue, 2> Results;
1737 LowerUDIVREM64(Op, DAG, Results);
1738 return DAG.getMergeValues(Results, DL);
1741 SDValue Num = Op.getOperand(0);
1742 SDValue Den = Op.getOperand(1);
1744 if (VT == MVT::i32) {
1745 if (DAG.MaskedValueIsZero(Num, APInt::getHighBitsSet(32, 8)) &&
1746 DAG.MaskedValueIsZero(Den, APInt::getHighBitsSet(32, 8))) {
1747 // TODO: We technically could do this for i64, but shouldn't that just be
1748 // handled by something generally reducing 64-bit division on 32-bit
1749 // values to 32-bit?
1750 return LowerDIVREM24(Op, DAG, false);
1754 // RCP = URECIP(Den) = 2^32 / Den + e
1755 // e is rounding error.
1756 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1758 // RCP_LO = mul(RCP, Den) */
1759 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1761 // RCP_HI = mulhu (RCP, Den) */
1762 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1764 // NEG_RCP_LO = -RCP_LO
1765 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
1768 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1769 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1772 // Calculate the rounding error from the URECIP instruction
1773 // E = mulhu(ABS_RCP_LO, RCP)
1774 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1776 // RCP_A_E = RCP + E
1777 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1779 // RCP_S_E = RCP - E
1780 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1782 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1783 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, DL, VT),
1786 // Quotient = mulhu(Tmp0, Num)
1787 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1789 // Num_S_Remainder = Quotient * Den
1790 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1792 // Remainder = Num - Num_S_Remainder
1793 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1795 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1796 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1797 DAG.getConstant(-1, DL, VT),
1798 DAG.getConstant(0, DL, VT),
1800 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1801 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1803 DAG.getConstant(-1, DL, VT),
1804 DAG.getConstant(0, DL, VT),
1806 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1807 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1810 // Calculate Division result:
1812 // Quotient_A_One = Quotient + 1
1813 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1814 DAG.getConstant(1, DL, VT));
1816 // Quotient_S_One = Quotient - 1
1817 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1818 DAG.getConstant(1, DL, VT));
1820 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1821 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1822 Quotient, Quotient_A_One, ISD::SETEQ);
1824 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1825 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1826 Quotient_S_One, Div, ISD::SETEQ);
1828 // Calculate Rem result:
1830 // Remainder_S_Den = Remainder - Den
1831 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1833 // Remainder_A_Den = Remainder + Den
1834 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1836 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1837 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, DL, VT),
1838 Remainder, Remainder_S_Den, ISD::SETEQ);
1840 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1841 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, DL, VT),
1842 Remainder_A_Den, Rem, ISD::SETEQ);
1847 return DAG.getMergeValues(Ops, DL);
1850 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1851 SelectionDAG &DAG) const {
1853 EVT VT = Op.getValueType();
1855 SDValue LHS = Op.getOperand(0);
1856 SDValue RHS = Op.getOperand(1);
1858 SDValue Zero = DAG.getConstant(0, DL, VT);
1859 SDValue NegOne = DAG.getConstant(-1, DL, VT);
1861 if (VT == MVT::i32 &&
1862 DAG.ComputeNumSignBits(LHS) > 8 &&
1863 DAG.ComputeNumSignBits(RHS) > 8) {
1864 return LowerDIVREM24(Op, DAG, true);
1866 if (VT == MVT::i64 &&
1867 DAG.ComputeNumSignBits(LHS) > 32 &&
1868 DAG.ComputeNumSignBits(RHS) > 32) {
1869 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1872 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1873 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1874 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1877 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
1878 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
1880 return DAG.getMergeValues(Res, DL);
1883 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1884 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1885 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1886 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1888 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1889 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1891 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1892 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1894 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1895 SDValue Rem = Div.getValue(1);
1897 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1898 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1900 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1901 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1907 return DAG.getMergeValues(Res, DL);
1910 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1911 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1913 EVT VT = Op.getValueType();
1914 SDValue X = Op.getOperand(0);
1915 SDValue Y = Op.getOperand(1);
1917 // TODO: Should this propagate fast-math-flags?
1919 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1920 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1921 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1923 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1926 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1928 SDValue Src = Op.getOperand(0);
1930 // result = trunc(src)
1931 // if (src > 0.0 && src != result)
1934 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1936 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
1937 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
1940 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
1942 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1943 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1944 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1946 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1947 // TODO: Should this propagate fast-math-flags?
1948 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1951 static SDValue extractF64Exponent(SDValue Hi, SDLoc SL, SelectionDAG &DAG) {
1952 const unsigned FractBits = 52;
1953 const unsigned ExpBits = 11;
1955 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1957 DAG.getConstant(FractBits - 32, SL, MVT::i32),
1958 DAG.getConstant(ExpBits, SL, MVT::i32));
1959 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1960 DAG.getConstant(1023, SL, MVT::i32));
1965 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1967 SDValue Src = Op.getOperand(0);
1969 assert(Op.getValueType() == MVT::f64);
1971 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
1972 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
1974 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1976 // Extract the upper half, since this is where we will find the sign and
1978 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1980 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
1982 const unsigned FractBits = 52;
1984 // Extract the sign bit.
1985 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, SL, MVT::i32);
1986 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1988 // Extend back to to 64-bits.
1989 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1991 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1993 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1994 const SDValue FractMask
1995 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, SL, MVT::i64);
1997 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1998 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1999 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
2002 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
2004 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, SL, MVT::i32);
2006 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2007 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2009 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
2010 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
2012 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
2015 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
2017 SDValue Src = Op.getOperand(0);
2019 assert(Op.getValueType() == MVT::f64);
2021 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
2022 SDValue C1 = DAG.getConstantFP(C1Val, SL, MVT::f64);
2023 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
2025 // TODO: Should this propagate fast-math-flags?
2027 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
2028 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
2030 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
2032 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
2033 SDValue C2 = DAG.getConstantFP(C2Val, SL, MVT::f64);
2036 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2037 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
2039 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
2042 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
2043 // FNEARBYINT and FRINT are the same, except in their handling of FP
2044 // exceptions. Those aren't really meaningful for us, and OpenCL only has
2045 // rint, so just treat them as equivalent.
2046 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
2049 // XXX - May require not supporting f32 denormals?
2050 SDValue AMDGPUTargetLowering::LowerFROUND32(SDValue Op, SelectionDAG &DAG) const {
2052 SDValue X = Op.getOperand(0);
2054 SDValue T = DAG.getNode(ISD::FTRUNC, SL, MVT::f32, X);
2056 // TODO: Should this propagate fast-math-flags?
2058 SDValue Diff = DAG.getNode(ISD::FSUB, SL, MVT::f32, X, T);
2060 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, MVT::f32, Diff);
2062 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f32);
2063 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
2064 const SDValue Half = DAG.getConstantFP(0.5, SL, MVT::f32);
2066 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f32, One, X);
2069 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
2071 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
2073 SDValue Sel = DAG.getNode(ISD::SELECT, SL, MVT::f32, Cmp, SignOne, Zero);
2075 return DAG.getNode(ISD::FADD, SL, MVT::f32, T, Sel);
2078 SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {
2080 SDValue X = Op.getOperand(0);
2082 SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
2084 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2085 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2086 const SDValue NegOne = DAG.getConstant(-1, SL, MVT::i32);
2087 const SDValue FiftyOne = DAG.getConstant(51, SL, MVT::i32);
2089 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i32);
2091 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
2093 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);
2095 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2097 const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), SL,
2100 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
2101 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
2102 DAG.getConstant(INT64_C(0x0008000000000000), SL,
2106 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
2107 SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
2108 DAG.getConstant(0, SL, MVT::i64), Tmp0,
2111 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
2112 D, DAG.getConstant(0, SL, MVT::i64));
2113 SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
2115 K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
2116 K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);
2118 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2119 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2120 SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ);
2122 SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
2124 DAG.getConstantFP(1.0, SL, MVT::f64),
2125 DAG.getConstantFP(0.0, SL, MVT::f64));
2127 SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
2129 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
2130 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
2135 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
2136 EVT VT = Op.getValueType();
2139 return LowerFROUND32(Op, DAG);
2142 return LowerFROUND64(Op, DAG);
2144 llvm_unreachable("unhandled type");
2147 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2149 SDValue Src = Op.getOperand(0);
2151 // result = trunc(src);
2152 // if (src < 0.0 && src != result)
2155 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2157 const SDValue Zero = DAG.getConstantFP(0.0, SL, MVT::f64);
2158 const SDValue NegOne = DAG.getConstantFP(-1.0, SL, MVT::f64);
2161 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f64);
2163 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2164 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2165 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2167 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2168 // TODO: Should this propagate fast-math-flags?
2169 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2172 SDValue AMDGPUTargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
2174 SDValue Src = Op.getOperand(0);
2175 bool ZeroUndef = Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF;
2177 if (ZeroUndef && Src.getValueType() == MVT::i32)
2178 return DAG.getNode(AMDGPUISD::FFBH_U32, SL, MVT::i32, Src);
2180 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2182 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2183 const SDValue One = DAG.getConstant(1, SL, MVT::i32);
2185 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);
2186 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);
2188 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(),
2189 *DAG.getContext(), MVT::i32);
2191 SDValue Hi0 = DAG.getSetCC(SL, SetCCVT, Hi, Zero, ISD::SETEQ);
2193 SDValue CtlzLo = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i32, Lo);
2194 SDValue CtlzHi = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i32, Hi);
2196 const SDValue Bits32 = DAG.getConstant(32, SL, MVT::i32);
2197 SDValue Add = DAG.getNode(ISD::ADD, SL, MVT::i32, CtlzLo, Bits32);
2199 // ctlz(x) = hi_32(x) == 0 ? ctlz(lo_32(x)) + 32 : ctlz(hi_32(x))
2200 SDValue NewCtlz = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0, Add, CtlzHi);
2203 // Test if the full 64-bit input is zero.
2205 // FIXME: DAG combines turn what should be an s_and_b64 into a v_or_b32,
2206 // which we probably don't want.
2207 SDValue Lo0 = DAG.getSetCC(SL, SetCCVT, Lo, Zero, ISD::SETEQ);
2208 SDValue SrcIsZero = DAG.getNode(ISD::AND, SL, SetCCVT, Lo0, Hi0);
2210 // TODO: If i64 setcc is half rate, it can result in 1 fewer instruction
2211 // with the same cycles, otherwise it is slower.
2212 // SDValue SrcIsZero = DAG.getSetCC(SL, SetCCVT, Src,
2213 // DAG.getConstant(0, SL, MVT::i64), ISD::SETEQ);
2215 const SDValue Bits32 = DAG.getConstant(64, SL, MVT::i32);
2217 // The instruction returns -1 for 0 input, but the defined intrinsic
2218 // behavior is to return the number of bits.
2219 NewCtlz = DAG.getNode(ISD::SELECT, SL, MVT::i32,
2220 SrcIsZero, Bits32, NewCtlz);
2223 return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewCtlz);
2226 SDValue AMDGPUTargetLowering::LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG,
2227 bool Signed) const {
2231 // uint lz = clz(u);
2232 // uint e = (u != 0) ? 127U + 63U - lz : 0;
2233 // u = (u << lz) & 0x7fffffffffffffffUL;
2234 // ulong t = u & 0xffffffffffUL;
2235 // uint v = (e << 23) | (uint)(u >> 40);
2236 // uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
2237 // return as_float(v + r);
2242 // long s = l >> 63;
2243 // float r = cul2f((l + s) ^ s);
2244 // return s ? -r : r;
2248 SDValue Src = Op.getOperand(0);
2253 const SDValue SignBit = DAG.getConstant(63, SL, MVT::i64);
2254 S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit);
2256 SDValue LPlusS = DAG.getNode(ISD::ADD, SL, MVT::i64, L, S);
2257 L = DAG.getNode(ISD::XOR, SL, MVT::i64, LPlusS, S);
2260 EVT SetCCVT = getSetCCResultType(DAG.getDataLayout(),
2261 *DAG.getContext(), MVT::f32);
2264 SDValue ZeroI32 = DAG.getConstant(0, SL, MVT::i32);
2265 SDValue ZeroI64 = DAG.getConstant(0, SL, MVT::i64);
2266 SDValue LZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i64, L);
2267 LZ = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LZ);
2269 SDValue K = DAG.getConstant(127U + 63U, SL, MVT::i32);
2270 SDValue E = DAG.getSelect(SL, MVT::i32,
2271 DAG.getSetCC(SL, SetCCVT, L, ZeroI64, ISD::SETNE),
2272 DAG.getNode(ISD::SUB, SL, MVT::i32, K, LZ),
2275 SDValue U = DAG.getNode(ISD::AND, SL, MVT::i64,
2276 DAG.getNode(ISD::SHL, SL, MVT::i64, L, LZ),
2277 DAG.getConstant((-1ULL) >> 1, SL, MVT::i64));
2279 SDValue T = DAG.getNode(ISD::AND, SL, MVT::i64, U,
2280 DAG.getConstant(0xffffffffffULL, SL, MVT::i64));
2282 SDValue UShl = DAG.getNode(ISD::SRL, SL, MVT::i64,
2283 U, DAG.getConstant(40, SL, MVT::i64));
2285 SDValue V = DAG.getNode(ISD::OR, SL, MVT::i32,
2286 DAG.getNode(ISD::SHL, SL, MVT::i32, E, DAG.getConstant(23, SL, MVT::i32)),
2287 DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, UShl));
2289 SDValue C = DAG.getConstant(0x8000000000ULL, SL, MVT::i64);
2290 SDValue RCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETUGT);
2291 SDValue TCmp = DAG.getSetCC(SL, SetCCVT, T, C, ISD::SETEQ);
2293 SDValue One = DAG.getConstant(1, SL, MVT::i32);
2295 SDValue VTrunc1 = DAG.getNode(ISD::AND, SL, MVT::i32, V, One);
2297 SDValue R = DAG.getSelect(SL, MVT::i32,
2300 DAG.getSelect(SL, MVT::i32, TCmp, VTrunc1, ZeroI32));
2301 R = DAG.getNode(ISD::ADD, SL, MVT::i32, V, R);
2302 R = DAG.getNode(ISD::BITCAST, SL, MVT::f32, R);
2307 SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R);
2308 return DAG.getSelect(SL, MVT::f32, DAG.getSExtOrTrunc(S, SL, SetCCVT), RNeg, R);
2311 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2312 bool Signed) const {
2314 SDValue Src = Op.getOperand(0);
2316 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2318 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2319 DAG.getConstant(0, SL, MVT::i32));
2320 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2321 DAG.getConstant(1, SL, MVT::i32));
2323 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2326 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2328 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2329 DAG.getConstant(32, SL, MVT::i32));
2330 // TODO: Should this propagate fast-math-flags?
2331 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2334 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2335 SelectionDAG &DAG) const {
2336 assert(Op.getOperand(0).getValueType() == MVT::i64 &&
2337 "operation should be legal");
2339 EVT DestVT = Op.getValueType();
2340 if (DestVT == MVT::f64)
2341 return LowerINT_TO_FP64(Op, DAG, false);
2343 if (DestVT == MVT::f32)
2344 return LowerINT_TO_FP32(Op, DAG, false);
2349 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2350 SelectionDAG &DAG) const {
2351 assert(Op.getOperand(0).getValueType() == MVT::i64 &&
2352 "operation should be legal");
2354 EVT DestVT = Op.getValueType();
2355 if (DestVT == MVT::f32)
2356 return LowerINT_TO_FP32(Op, DAG, true);
2358 if (DestVT == MVT::f64)
2359 return LowerINT_TO_FP64(Op, DAG, true);
2364 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2365 bool Signed) const {
2368 SDValue Src = Op.getOperand(0);
2370 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2372 SDValue K0 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), SL,
2374 SDValue K1 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), SL,
2376 // TODO: Should this propagate fast-math-flags?
2377 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2379 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2382 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2384 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2385 MVT::i32, FloorMul);
2386 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2388 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi);
2390 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2393 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2394 SelectionDAG &DAG) const {
2395 SDValue Src = Op.getOperand(0);
2397 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2398 return LowerFP64_TO_INT(Op, DAG, true);
2403 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2404 SelectionDAG &DAG) const {
2405 SDValue Src = Op.getOperand(0);
2407 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2408 return LowerFP64_TO_INT(Op, DAG, false);
2413 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2414 SelectionDAG &DAG) const {
2415 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2416 MVT VT = Op.getSimpleValueType();
2417 MVT ScalarVT = VT.getScalarType();
2422 SDValue Src = Op.getOperand(0);
2425 // TODO: Don't scalarize on Evergreen?
2426 unsigned NElts = VT.getVectorNumElements();
2427 SmallVector<SDValue, 8> Args;
2428 DAG.ExtractVectorElements(Src, Args, 0, NElts);
2430 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2431 for (unsigned I = 0; I < NElts; ++I)
2432 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2434 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
2437 //===----------------------------------------------------------------------===//
2438 // Custom DAG optimizations
2439 //===----------------------------------------------------------------------===//
2441 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2442 APInt KnownZero, KnownOne;
2443 EVT VT = Op.getValueType();
2444 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2446 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
2449 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2450 EVT VT = Op.getValueType();
2452 // In order for this to be a signed 24-bit value, bit 23, must
2454 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2455 // as unsigned 24-bit values.
2456 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
2459 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
2461 SelectionDAG &DAG = DCI.DAG;
2462 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2463 EVT VT = Op.getValueType();
2465 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
2466 APInt KnownZero, KnownOne;
2467 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
2468 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
2469 DCI.CommitTargetLoweringOpt(TLO);
2472 template <typename IntTy>
2473 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
2474 uint32_t Offset, uint32_t Width, SDLoc DL) {
2475 if (Width + Offset < 32) {
2476 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2477 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2478 return DAG.getConstant(Result, DL, MVT::i32);
2481 return DAG.getConstant(Src0 >> Offset, DL, MVT::i32);
2484 static bool usesAllNormalStores(SDNode *LoadVal) {
2485 for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
2486 if (!ISD::isNormalStore(*I))
2493 // If we have a copy of an illegal type, replace it with a load / store of an
2494 // equivalently sized legal type. This avoids intermediate bit pack / unpack
2495 // instructions emitted when handling extloads and truncstores. Ideally we could
2496 // recognize the pack / unpack pattern to eliminate it.
2497 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2498 DAGCombinerInfo &DCI) const {
2499 if (!DCI.isBeforeLegalize())
2502 StoreSDNode *SN = cast<StoreSDNode>(N);
2503 SDValue Value = SN->getValue();
2504 EVT VT = Value.getValueType();
2506 if (isTypeLegal(VT) || SN->isVolatile() ||
2507 !ISD::isNormalLoad(Value.getNode()) || VT.getSizeInBits() < 8)
2510 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
2511 if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
2514 EVT MemVT = LoadVal->getMemoryVT();
2517 SelectionDAG &DAG = DCI.DAG;
2518 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
2520 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
2522 LoadVal->getChain(),
2523 LoadVal->getBasePtr(),
2524 LoadVal->getOffset(),
2526 LoadVal->getMemOperand());
2528 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
2529 DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
2531 return DAG.getStore(SN->getChain(), SL, NewLoad,
2532 SN->getBasePtr(), SN->getMemOperand());
2535 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
2536 DAGCombinerInfo &DCI) const {
2537 if (N->getValueType(0) != MVT::i64)
2540 // i64 (shl x, 32) -> (build_pair 0, x)
2542 // Doing this with moves theoretically helps MI optimizations that understand
2543 // copies. 2 v_mov_b32_e32 will have the same code size / cycle count as
2544 // v_lshl_b64. In the SALU case, I think this is slightly worse since it
2545 // doubles the code size and I'm unsure about cycle count.
2546 const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
2547 if (!RHS || RHS->getZExtValue() != 32)
2550 SDValue LHS = N->getOperand(0);
2553 SelectionDAG &DAG = DCI.DAG;
2555 // Extract low 32-bits.
2556 SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);
2558 const SDValue Zero = DAG.getConstant(0, SL, MVT::i32);
2559 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64, Zero, Lo);
2562 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2563 DAGCombinerInfo &DCI) const {
2564 EVT VT = N->getValueType(0);
2566 if (VT.isVector() || VT.getSizeInBits() > 32)
2569 SelectionDAG &DAG = DCI.DAG;
2572 SDValue N0 = N->getOperand(0);
2573 SDValue N1 = N->getOperand(1);
2576 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2577 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2578 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2579 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
2580 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2581 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2582 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2583 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
2588 // We need to use sext even for MUL_U24, because MUL_U24 is used
2589 // for signed multiply of 8 and 16-bit types.
2590 return DAG.getSExtOrTrunc(Mul, DL, VT);
2593 static bool isNegativeOne(SDValue Val) {
2594 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val))
2595 return C->isAllOnesValue();
2599 static bool isCtlzOpc(unsigned Opc) {
2600 return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF;
2603 // Get FFBH node if the incoming op may have been type legalized from a smaller
2605 // Need to match pre-legalized type because the generic legalization inserts the
2606 // add/sub between the select and compare.
2607 static SDValue getFFBH_U32(const TargetLowering &TLI,
2608 SelectionDAG &DAG, SDLoc SL, SDValue Op) {
2609 EVT VT = Op.getValueType();
2610 EVT LegalVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2611 if (LegalVT != MVT::i32)
2615 Op = DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i32, Op);
2617 SDValue FFBH = DAG.getNode(AMDGPUISD::FFBH_U32, SL, MVT::i32, Op);
2619 FFBH = DAG.getNode(ISD::TRUNCATE, SL, VT, FFBH);
2624 // The native instructions return -1 on 0 input. Optimize out a select that
2625 // produces -1 on 0.
2627 // TODO: If zero is not undef, we could also do this if the output is compared
2628 // against the bitwidth.
2630 // TODO: Should probably combine against FFBH_U32 instead of ctlz directly.
2631 SDValue AMDGPUTargetLowering::performCtlzCombine(SDLoc SL,
2635 DAGCombinerInfo &DCI) const {
2636 ConstantSDNode *CmpRhs = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2637 if (!CmpRhs || !CmpRhs->isNullValue())
2640 SelectionDAG &DAG = DCI.DAG;
2641 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
2642 SDValue CmpLHS = Cond.getOperand(0);
2644 // select (setcc x, 0, eq), -1, (ctlz_zero_undef x) -> ffbh_u32 x
2645 if (CCOpcode == ISD::SETEQ &&
2646 isCtlzOpc(RHS.getOpcode()) &&
2647 RHS.getOperand(0) == CmpLHS &&
2648 isNegativeOne(LHS)) {
2649 return getFFBH_U32(*this, DAG, SL, CmpLHS);
2652 // select (setcc x, 0, ne), (ctlz_zero_undef x), -1 -> ffbh_u32 x
2653 if (CCOpcode == ISD::SETNE &&
2654 isCtlzOpc(LHS.getOpcode()) &&
2655 LHS.getOperand(0) == CmpLHS &&
2656 isNegativeOne(RHS)) {
2657 return getFFBH_U32(*this, DAG, SL, CmpLHS);
2663 SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
2664 DAGCombinerInfo &DCI) const {
2665 SDValue Cond = N->getOperand(0);
2666 if (Cond.getOpcode() != ISD::SETCC)
2669 EVT VT = N->getValueType(0);
2670 SDValue LHS = Cond.getOperand(0);
2671 SDValue RHS = Cond.getOperand(1);
2672 SDValue CC = Cond.getOperand(2);
2674 SDValue True = N->getOperand(1);
2675 SDValue False = N->getOperand(2);
2677 if (VT == MVT::f32 && Cond.hasOneUse())
2678 return CombineFMinMaxLegacy(SDLoc(N), VT, LHS, RHS, True, False, CC, DCI);
2680 // There's no reason to not do this if the condition has other uses.
2681 return performCtlzCombine(SDLoc(N), Cond, True, False, DCI);
2684 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2685 DAGCombinerInfo &DCI) const {
2686 SelectionDAG &DAG = DCI.DAG;
2689 switch(N->getOpcode()) {
2693 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2696 return performShlCombine(N, DCI);
2699 return performMulCombine(N, DCI);
2700 case AMDGPUISD::MUL_I24:
2701 case AMDGPUISD::MUL_U24: {
2702 SDValue N0 = N->getOperand(0);
2703 SDValue N1 = N->getOperand(1);
2704 simplifyI24(N0, DCI);
2705 simplifyI24(N1, DCI);
2709 return performSelectCombine(N, DCI);
2710 case AMDGPUISD::BFE_I32:
2711 case AMDGPUISD::BFE_U32: {
2712 assert(!N->getValueType(0).isVector() &&
2713 "Vector handling of BFE not implemented");
2714 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2718 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2720 return DAG.getConstant(0, DL, MVT::i32);
2722 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2726 SDValue BitsFrom = N->getOperand(0);
2727 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2729 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2731 if (OffsetVal == 0) {
2732 // This is already sign / zero extended, so try to fold away extra BFEs.
2733 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2735 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2736 if (OpSignBits >= SignBits)
2739 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2741 // This is a sign_extend_inreg. Replace it to take advantage of existing
2742 // DAG Combines. If not eliminated, we will match back to BFE during
2745 // TODO: The sext_inreg of extended types ends, although we can could
2746 // handle them in a single BFE.
2747 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2748 DAG.getValueType(SmallVT));
2751 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2754 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
2756 return constantFoldBFE<int32_t>(DAG,
2757 CVal->getSExtValue(),
2763 return constantFoldBFE<uint32_t>(DAG,
2764 CVal->getZExtValue(),
2770 if ((OffsetVal + WidthVal) >= 32) {
2771 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32);
2772 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2773 BitsFrom, ShiftVal);
2776 if (BitsFrom.hasOneUse()) {
2777 APInt Demanded = APInt::getBitsSet(32,
2779 OffsetVal + WidthVal);
2781 APInt KnownZero, KnownOne;
2782 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2783 !DCI.isBeforeLegalizeOps());
2784 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2785 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2786 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
2787 KnownZero, KnownOne, TLO)) {
2788 DCI.CommitTargetLoweringOpt(TLO);
2796 return performStoreCombine(N, DCI);
2801 //===----------------------------------------------------------------------===//
2803 //===----------------------------------------------------------------------===//
2805 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2808 const SmallVectorImpl<ISD::InputArg> &Ins,
2809 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2811 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2812 if (Ins[i].ArgVT == Ins[i].VT) {
2813 OrigIns.push_back(Ins[i]);
2818 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2819 // Vector has been split into scalars.
2820 VT = Ins[i].ArgVT.getVectorElementType();
2821 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2822 Ins[i].ArgVT.getVectorElementType() !=
2823 Ins[i].VT.getVectorElementType()) {
2824 // Vector elements have been promoted
2827 // Vector has been spilt into smaller vectors.
2831 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2832 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2833 OrigIns.push_back(Arg);
2837 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2838 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2839 return CFP->isExactlyValue(1.0);
2841 return isAllOnesConstant(Op);
2844 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2845 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2846 return CFP->getValueAPF().isZero();
2848 return isNullConstant(Op);
2851 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2852 const TargetRegisterClass *RC,
2853 unsigned Reg, EVT VT) const {
2854 MachineFunction &MF = DAG.getMachineFunction();
2855 MachineRegisterInfo &MRI = MF.getRegInfo();
2856 unsigned VirtualRegister;
2857 if (!MRI.isLiveIn(Reg)) {
2858 VirtualRegister = MRI.createVirtualRegister(RC);
2859 MRI.addLiveIn(Reg, VirtualRegister);
2861 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2863 return DAG.getRegister(VirtualRegister, VT);
2866 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
2867 const AMDGPUMachineFunction *MFI, const ImplicitParameter Param) const {
2868 uint64_t ArgOffset = MFI->ABIArgOffset;
2873 return ArgOffset + 4;
2875 llvm_unreachable("unexpected implicit parameter type");
2878 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2880 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2881 switch ((AMDGPUISD::NodeType)Opcode) {
2882 case AMDGPUISD::FIRST_NUMBER: break;
2884 NODE_NAME_CASE(CALL);
2885 NODE_NAME_CASE(UMUL);
2886 NODE_NAME_CASE(RET_FLAG);
2887 NODE_NAME_CASE(BRANCH_COND);
2890 NODE_NAME_CASE(DWORDADDR)
2891 NODE_NAME_CASE(FRACT)
2892 NODE_NAME_CASE(CLAMP)
2893 NODE_NAME_CASE(COS_HW)
2894 NODE_NAME_CASE(SIN_HW)
2895 NODE_NAME_CASE(FMAX_LEGACY)
2896 NODE_NAME_CASE(FMIN_LEGACY)
2897 NODE_NAME_CASE(FMAX3)
2898 NODE_NAME_CASE(SMAX3)
2899 NODE_NAME_CASE(UMAX3)
2900 NODE_NAME_CASE(FMIN3)
2901 NODE_NAME_CASE(SMIN3)
2902 NODE_NAME_CASE(UMIN3)
2903 NODE_NAME_CASE(URECIP)
2904 NODE_NAME_CASE(DIV_SCALE)
2905 NODE_NAME_CASE(DIV_FMAS)
2906 NODE_NAME_CASE(DIV_FIXUP)
2907 NODE_NAME_CASE(TRIG_PREOP)
2910 NODE_NAME_CASE(RSQ_LEGACY)
2911 NODE_NAME_CASE(RSQ_CLAMPED)
2912 NODE_NAME_CASE(LDEXP)
2913 NODE_NAME_CASE(FP_CLASS)
2914 NODE_NAME_CASE(DOT4)
2915 NODE_NAME_CASE(CARRY)
2916 NODE_NAME_CASE(BORROW)
2917 NODE_NAME_CASE(BFE_U32)
2918 NODE_NAME_CASE(BFE_I32)
2921 NODE_NAME_CASE(FFBH_U32)
2922 NODE_NAME_CASE(MUL_U24)
2923 NODE_NAME_CASE(MUL_I24)
2924 NODE_NAME_CASE(MAD_U24)
2925 NODE_NAME_CASE(MAD_I24)
2926 NODE_NAME_CASE(TEXTURE_FETCH)
2927 NODE_NAME_CASE(EXPORT)
2928 NODE_NAME_CASE(CONST_ADDRESS)
2929 NODE_NAME_CASE(REGISTER_LOAD)
2930 NODE_NAME_CASE(REGISTER_STORE)
2931 NODE_NAME_CASE(LOAD_CONSTANT)
2932 NODE_NAME_CASE(LOAD_INPUT)
2933 NODE_NAME_CASE(SAMPLE)
2934 NODE_NAME_CASE(SAMPLEB)
2935 NODE_NAME_CASE(SAMPLED)
2936 NODE_NAME_CASE(SAMPLEL)
2937 NODE_NAME_CASE(CVT_F32_UBYTE0)
2938 NODE_NAME_CASE(CVT_F32_UBYTE1)
2939 NODE_NAME_CASE(CVT_F32_UBYTE2)
2940 NODE_NAME_CASE(CVT_F32_UBYTE3)
2941 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2942 NODE_NAME_CASE(CONST_DATA_PTR)
2943 case AMDGPUISD::FIRST_MEM_OPCODE_NUMBER: break;
2944 NODE_NAME_CASE(SENDMSG)
2945 NODE_NAME_CASE(INTERP_MOV)
2946 NODE_NAME_CASE(INTERP_P1)
2947 NODE_NAME_CASE(INTERP_P2)
2948 NODE_NAME_CASE(STORE_MSKOR)
2949 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2950 case AMDGPUISD::LAST_AMDGPU_ISD_NUMBER: break;
2955 SDValue AMDGPUTargetLowering::getRsqrtEstimate(SDValue Operand,
2956 DAGCombinerInfo &DCI,
2957 unsigned &RefinementSteps,
2958 bool &UseOneConstNR) const {
2959 SelectionDAG &DAG = DCI.DAG;
2960 EVT VT = Operand.getValueType();
2962 if (VT == MVT::f32) {
2963 RefinementSteps = 0;
2964 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
2967 // TODO: There is also f64 rsq instruction, but the documentation is less
2968 // clear on its precision.
2973 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
2974 DAGCombinerInfo &DCI,
2975 unsigned &RefinementSteps) const {
2976 SelectionDAG &DAG = DCI.DAG;
2977 EVT VT = Operand.getValueType();
2979 if (VT == MVT::f32) {
2980 // Reciprocal, < 1 ulp error.
2982 // This reciprocal approximation converges to < 0.5 ulp error with one
2983 // newton rhapson performed with two fused multiple adds (FMAs).
2985 RefinementSteps = 0;
2986 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);
2989 // TODO: There is also f64 rcp instruction, but the documentation is less
2990 // clear on its precision.
2995 static void computeKnownBitsForMinMax(const SDValue Op0,
2999 const SelectionDAG &DAG,
3001 APInt Op0Zero, Op0One;
3002 APInt Op1Zero, Op1One;
3003 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
3004 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
3006 KnownZero = Op0Zero & Op1Zero;
3007 KnownOne = Op0One & Op1One;
3010 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
3014 const SelectionDAG &DAG,
3015 unsigned Depth) const {
3017 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
3021 unsigned Opc = Op.getOpcode();
3026 case ISD::INTRINSIC_WO_CHAIN: {
3027 // FIXME: The intrinsic should just use the node.
3028 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
3029 case AMDGPUIntrinsic::AMDGPU_imax:
3030 case AMDGPUIntrinsic::AMDGPU_umax:
3031 case AMDGPUIntrinsic::AMDGPU_imin:
3032 case AMDGPUIntrinsic::AMDGPU_umin:
3033 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
3034 KnownZero, KnownOne, DAG, Depth);
3042 case AMDGPUISD::CARRY:
3043 case AMDGPUISD::BORROW: {
3044 KnownZero = APInt::getHighBitsSet(32, 31);
3048 case AMDGPUISD::BFE_I32:
3049 case AMDGPUISD::BFE_U32: {
3050 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
3054 unsigned BitWidth = 32;
3055 uint32_t Width = CWidth->getZExtValue() & 0x1f;
3057 if (Opc == AMDGPUISD::BFE_U32)
3058 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
3065 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
3067 const SelectionDAG &DAG,
3068 unsigned Depth) const {
3069 switch (Op.getOpcode()) {
3070 case AMDGPUISD::BFE_I32: {
3071 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
3075 unsigned SignBits = 32 - Width->getZExtValue() + 1;
3076 if (!isNullConstant(Op.getOperand(1)))
3079 // TODO: Could probably figure something out with non-0 offsets.
3080 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
3081 return std::max(SignBits, Op0SignBits);
3084 case AMDGPUISD::BFE_U32: {
3085 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
3086 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;
3089 case AMDGPUISD::CARRY:
3090 case AMDGPUISD::BORROW: