1 //===-- AArch64BaseInfo.cpp - AArch64 Base encoding information------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides basic encoding and assembly information for AArch64.
12 //===----------------------------------------------------------------------===//
13 #include "AArch64BaseInfo.h"
14 #include "llvm/ADT/APFloat.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/MC/SubtargetFeature.h"
18 #include "llvm/Support/Regex.h"
22 StringRef AArch64NamedImmMapper::toString(uint32_t Value, bool &Valid) const {
23 for (unsigned i = 0; i < NumPairs; ++i) {
24 if (Pairs[i].Value == Value) {
34 uint32_t AArch64NamedImmMapper::fromString(StringRef Name, bool &Valid) const {
35 std::string LowerCaseName = Name.lower();
36 for (unsigned i = 0; i < NumPairs; ++i) {
37 if (Pairs[i].Name == LowerCaseName) {
39 return Pairs[i].Value;
47 bool AArch64NamedImmMapper::validImm(uint32_t Value) const {
48 return Value < TooBigImm;
51 const AArch64NamedImmMapper::Mapping AArch64AT::ATMapper::ATPairs[] = {
66 AArch64AT::ATMapper::ATMapper()
67 : AArch64NamedImmMapper(ATPairs, 0) {}
69 const AArch64NamedImmMapper::Mapping AArch64DB::DBarrierMapper::DBarrierPairs[] = {
84 AArch64DB::DBarrierMapper::DBarrierMapper()
85 : AArch64NamedImmMapper(DBarrierPairs, 16u) {}
87 const AArch64NamedImmMapper::Mapping AArch64DC::DCMapper::DCPairs[] = {
98 AArch64DC::DCMapper::DCMapper()
99 : AArch64NamedImmMapper(DCPairs, 0) {}
101 const AArch64NamedImmMapper::Mapping AArch64IC::ICMapper::ICPairs[] = {
102 {"ialluis", IALLUIS},
107 AArch64IC::ICMapper::ICMapper()
108 : AArch64NamedImmMapper(ICPairs, 0) {}
110 const AArch64NamedImmMapper::Mapping AArch64ISB::ISBMapper::ISBPairs[] = {
114 AArch64ISB::ISBMapper::ISBMapper()
115 : AArch64NamedImmMapper(ISBPairs, 16) {}
117 const AArch64NamedImmMapper::Mapping AArch64PRFM::PRFMMapper::PRFMPairs[] = {
118 {"pldl1keep", PLDL1KEEP},
119 {"pldl1strm", PLDL1STRM},
120 {"pldl2keep", PLDL2KEEP},
121 {"pldl2strm", PLDL2STRM},
122 {"pldl3keep", PLDL3KEEP},
123 {"pldl3strm", PLDL3STRM},
124 {"plil1keep", PLIL1KEEP},
125 {"plil1strm", PLIL1STRM},
126 {"plil2keep", PLIL2KEEP},
127 {"plil2strm", PLIL2STRM},
128 {"plil3keep", PLIL3KEEP},
129 {"plil3strm", PLIL3STRM},
130 {"pstl1keep", PSTL1KEEP},
131 {"pstl1strm", PSTL1STRM},
132 {"pstl2keep", PSTL2KEEP},
133 {"pstl2strm", PSTL2STRM},
134 {"pstl3keep", PSTL3KEEP},
135 {"pstl3strm", PSTL3STRM}
138 AArch64PRFM::PRFMMapper::PRFMMapper()
139 : AArch64NamedImmMapper(PRFMPairs, 32) {}
141 const AArch64NamedImmMapper::Mapping AArch64PState::PStateMapper::PStatePairs[] = {
143 {"daifset", DAIFSet},
147 AArch64PState::PStateMapper::PStateMapper()
148 : AArch64NamedImmMapper(PStatePairs, 0) {}
150 const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSPairs[] = {
151 {"mdccsr_el0", MDCCSR_EL0},
152 {"dbgdtrrx_el0", DBGDTRRX_EL0},
153 {"mdrar_el1", MDRAR_EL1},
154 {"oslsr_el1", OSLSR_EL1},
155 {"dbgauthstatus_el1", DBGAUTHSTATUS_EL1},
156 {"pmceid0_el0", PMCEID0_EL0},
157 {"pmceid1_el0", PMCEID1_EL0},
158 {"midr_el1", MIDR_EL1},
159 {"ccsidr_el1", CCSIDR_EL1},
160 {"clidr_el1", CLIDR_EL1},
161 {"ctr_el0", CTR_EL0},
162 {"mpidr_el1", MPIDR_EL1},
163 {"revidr_el1", REVIDR_EL1},
164 {"aidr_el1", AIDR_EL1},
165 {"dczid_el0", DCZID_EL0},
166 {"id_pfr0_el1", ID_PFR0_EL1},
167 {"id_pfr1_el1", ID_PFR1_EL1},
168 {"id_dfr0_el1", ID_DFR0_EL1},
169 {"id_afr0_el1", ID_AFR0_EL1},
170 {"id_mmfr0_el1", ID_MMFR0_EL1},
171 {"id_mmfr1_el1", ID_MMFR1_EL1},
172 {"id_mmfr2_el1", ID_MMFR2_EL1},
173 {"id_mmfr3_el1", ID_MMFR3_EL1},
174 {"id_isar0_el1", ID_ISAR0_EL1},
175 {"id_isar1_el1", ID_ISAR1_EL1},
176 {"id_isar2_el1", ID_ISAR2_EL1},
177 {"id_isar3_el1", ID_ISAR3_EL1},
178 {"id_isar4_el1", ID_ISAR4_EL1},
179 {"id_isar5_el1", ID_ISAR5_EL1},
180 {"id_aa64pfr0_el1", ID_A64PFR0_EL1},
181 {"id_aa64pfr1_el1", ID_A64PFR1_EL1},
182 {"id_aa64dfr0_el1", ID_A64DFR0_EL1},
183 {"id_aa64dfr1_el1", ID_A64DFR1_EL1},
184 {"id_aa64afr0_el1", ID_A64AFR0_EL1},
185 {"id_aa64afr1_el1", ID_A64AFR1_EL1},
186 {"id_aa64isar0_el1", ID_A64ISAR0_EL1},
187 {"id_aa64isar1_el1", ID_A64ISAR1_EL1},
188 {"id_aa64mmfr0_el1", ID_A64MMFR0_EL1},
189 {"id_aa64mmfr1_el1", ID_A64MMFR1_EL1},
190 {"mvfr0_el1", MVFR0_EL1},
191 {"mvfr1_el1", MVFR1_EL1},
192 {"mvfr2_el1", MVFR2_EL1},
193 {"rvbar_el1", RVBAR_EL1},
194 {"rvbar_el2", RVBAR_EL2},
195 {"rvbar_el3", RVBAR_EL3},
196 {"isr_el1", ISR_EL1},
197 {"cntpct_el0", CNTPCT_EL0},
198 {"cntvct_el0", CNTVCT_EL0},
201 {"trcstatr", TRCSTATR},
202 {"trcidr8", TRCIDR8},
203 {"trcidr9", TRCIDR9},
204 {"trcidr10", TRCIDR10},
205 {"trcidr11", TRCIDR11},
206 {"trcidr12", TRCIDR12},
207 {"trcidr13", TRCIDR13},
208 {"trcidr0", TRCIDR0},
209 {"trcidr1", TRCIDR1},
210 {"trcidr2", TRCIDR2},
211 {"trcidr3", TRCIDR3},
212 {"trcidr4", TRCIDR4},
213 {"trcidr5", TRCIDR5},
214 {"trcidr6", TRCIDR6},
215 {"trcidr7", TRCIDR7},
216 {"trcoslsr", TRCOSLSR},
217 {"trcpdsr", TRCPDSR},
218 {"trcdevaff0", TRCDEVAFF0},
219 {"trcdevaff1", TRCDEVAFF1},
221 {"trcauthstatus", TRCAUTHSTATUS},
222 {"trcdevarch", TRCDEVARCH},
223 {"trcdevid", TRCDEVID},
224 {"trcdevtype", TRCDEVTYPE},
225 {"trcpidr4", TRCPIDR4},
226 {"trcpidr5", TRCPIDR5},
227 {"trcpidr6", TRCPIDR6},
228 {"trcpidr7", TRCPIDR7},
229 {"trcpidr0", TRCPIDR0},
230 {"trcpidr1", TRCPIDR1},
231 {"trcpidr2", TRCPIDR2},
232 {"trcpidr3", TRCPIDR3},
233 {"trccidr0", TRCCIDR0},
234 {"trccidr1", TRCCIDR1},
235 {"trccidr2", TRCCIDR2},
236 {"trccidr3", TRCCIDR3},
239 {"icc_iar1_el1", ICC_IAR1_EL1},
240 {"icc_iar0_el1", ICC_IAR0_EL1},
241 {"icc_hppir1_el1", ICC_HPPIR1_EL1},
242 {"icc_hppir0_el1", ICC_HPPIR0_EL1},
243 {"icc_rpr_el1", ICC_RPR_EL1},
244 {"ich_vtr_el2", ICH_VTR_EL2},
245 {"ich_eisr_el2", ICH_EISR_EL2},
246 {"ich_elsr_el2", ICH_ELSR_EL2}
249 AArch64SysReg::MRSMapper::MRSMapper(const FeatureBitset &FeatureBits)
250 : SysRegMapper(FeatureBits) {
251 InstPairs = &MRSPairs[0];
252 NumInstPairs = llvm::array_lengthof(MRSPairs);
255 const AArch64NamedImmMapper::Mapping AArch64SysReg::MSRMapper::MSRPairs[] = {
256 {"dbgdtrtx_el0", DBGDTRTX_EL0},
257 {"oslar_el1", OSLAR_EL1},
258 {"pmswinc_el0", PMSWINC_EL0},
261 {"trcoslar", TRCOSLAR},
265 {"icc_eoir1_el1", ICC_EOIR1_EL1},
266 {"icc_eoir0_el1", ICC_EOIR0_EL1},
267 {"icc_dir_el1", ICC_DIR_EL1},
268 {"icc_sgi1r_el1", ICC_SGI1R_EL1},
269 {"icc_asgi1r_el1", ICC_ASGI1R_EL1},
270 {"icc_sgi0r_el1", ICC_SGI0R_EL1}
273 AArch64SysReg::MSRMapper::MSRMapper(const FeatureBitset &FeatureBits)
274 : SysRegMapper(FeatureBits) {
275 InstPairs = &MSRPairs[0];
276 NumInstPairs = llvm::array_lengthof(MSRPairs);
280 const AArch64NamedImmMapper::Mapping AArch64SysReg::SysRegMapper::SysRegPairs[] = {
281 {"osdtrrx_el1", OSDTRRX_EL1},
282 {"osdtrtx_el1", OSDTRTX_EL1},
283 {"teecr32_el1", TEECR32_EL1},
284 {"mdccint_el1", MDCCINT_EL1},
285 {"mdscr_el1", MDSCR_EL1},
286 {"dbgdtr_el0", DBGDTR_EL0},
287 {"oseccr_el1", OSECCR_EL1},
288 {"dbgvcr32_el2", DBGVCR32_EL2},
289 {"dbgbvr0_el1", DBGBVR0_EL1},
290 {"dbgbvr1_el1", DBGBVR1_EL1},
291 {"dbgbvr2_el1", DBGBVR2_EL1},
292 {"dbgbvr3_el1", DBGBVR3_EL1},
293 {"dbgbvr4_el1", DBGBVR4_EL1},
294 {"dbgbvr5_el1", DBGBVR5_EL1},
295 {"dbgbvr6_el1", DBGBVR6_EL1},
296 {"dbgbvr7_el1", DBGBVR7_EL1},
297 {"dbgbvr8_el1", DBGBVR8_EL1},
298 {"dbgbvr9_el1", DBGBVR9_EL1},
299 {"dbgbvr10_el1", DBGBVR10_EL1},
300 {"dbgbvr11_el1", DBGBVR11_EL1},
301 {"dbgbvr12_el1", DBGBVR12_EL1},
302 {"dbgbvr13_el1", DBGBVR13_EL1},
303 {"dbgbvr14_el1", DBGBVR14_EL1},
304 {"dbgbvr15_el1", DBGBVR15_EL1},
305 {"dbgbcr0_el1", DBGBCR0_EL1},
306 {"dbgbcr1_el1", DBGBCR1_EL1},
307 {"dbgbcr2_el1", DBGBCR2_EL1},
308 {"dbgbcr3_el1", DBGBCR3_EL1},
309 {"dbgbcr4_el1", DBGBCR4_EL1},
310 {"dbgbcr5_el1", DBGBCR5_EL1},
311 {"dbgbcr6_el1", DBGBCR6_EL1},
312 {"dbgbcr7_el1", DBGBCR7_EL1},
313 {"dbgbcr8_el1", DBGBCR8_EL1},
314 {"dbgbcr9_el1", DBGBCR9_EL1},
315 {"dbgbcr10_el1", DBGBCR10_EL1},
316 {"dbgbcr11_el1", DBGBCR11_EL1},
317 {"dbgbcr12_el1", DBGBCR12_EL1},
318 {"dbgbcr13_el1", DBGBCR13_EL1},
319 {"dbgbcr14_el1", DBGBCR14_EL1},
320 {"dbgbcr15_el1", DBGBCR15_EL1},
321 {"dbgwvr0_el1", DBGWVR0_EL1},
322 {"dbgwvr1_el1", DBGWVR1_EL1},
323 {"dbgwvr2_el1", DBGWVR2_EL1},
324 {"dbgwvr3_el1", DBGWVR3_EL1},
325 {"dbgwvr4_el1", DBGWVR4_EL1},
326 {"dbgwvr5_el1", DBGWVR5_EL1},
327 {"dbgwvr6_el1", DBGWVR6_EL1},
328 {"dbgwvr7_el1", DBGWVR7_EL1},
329 {"dbgwvr8_el1", DBGWVR8_EL1},
330 {"dbgwvr9_el1", DBGWVR9_EL1},
331 {"dbgwvr10_el1", DBGWVR10_EL1},
332 {"dbgwvr11_el1", DBGWVR11_EL1},
333 {"dbgwvr12_el1", DBGWVR12_EL1},
334 {"dbgwvr13_el1", DBGWVR13_EL1},
335 {"dbgwvr14_el1", DBGWVR14_EL1},
336 {"dbgwvr15_el1", DBGWVR15_EL1},
337 {"dbgwcr0_el1", DBGWCR0_EL1},
338 {"dbgwcr1_el1", DBGWCR1_EL1},
339 {"dbgwcr2_el1", DBGWCR2_EL1},
340 {"dbgwcr3_el1", DBGWCR3_EL1},
341 {"dbgwcr4_el1", DBGWCR4_EL1},
342 {"dbgwcr5_el1", DBGWCR5_EL1},
343 {"dbgwcr6_el1", DBGWCR6_EL1},
344 {"dbgwcr7_el1", DBGWCR7_EL1},
345 {"dbgwcr8_el1", DBGWCR8_EL1},
346 {"dbgwcr9_el1", DBGWCR9_EL1},
347 {"dbgwcr10_el1", DBGWCR10_EL1},
348 {"dbgwcr11_el1", DBGWCR11_EL1},
349 {"dbgwcr12_el1", DBGWCR12_EL1},
350 {"dbgwcr13_el1", DBGWCR13_EL1},
351 {"dbgwcr14_el1", DBGWCR14_EL1},
352 {"dbgwcr15_el1", DBGWCR15_EL1},
353 {"teehbr32_el1", TEEHBR32_EL1},
354 {"osdlr_el1", OSDLR_EL1},
355 {"dbgprcr_el1", DBGPRCR_EL1},
356 {"dbgclaimset_el1", DBGCLAIMSET_EL1},
357 {"dbgclaimclr_el1", DBGCLAIMCLR_EL1},
358 {"csselr_el1", CSSELR_EL1},
359 {"vpidr_el2", VPIDR_EL2},
360 {"vmpidr_el2", VMPIDR_EL2},
361 {"sctlr_el1", SCTLR_EL1},
362 {"sctlr_el2", SCTLR_EL2},
363 {"sctlr_el3", SCTLR_EL3},
364 {"actlr_el1", ACTLR_EL1},
365 {"actlr_el2", ACTLR_EL2},
366 {"actlr_el3", ACTLR_EL3},
367 {"cpacr_el1", CPACR_EL1},
368 {"hcr_el2", HCR_EL2},
369 {"scr_el3", SCR_EL3},
370 {"mdcr_el2", MDCR_EL2},
371 {"sder32_el3", SDER32_EL3},
372 {"cptr_el2", CPTR_EL2},
373 {"cptr_el3", CPTR_EL3},
374 {"hstr_el2", HSTR_EL2},
375 {"hacr_el2", HACR_EL2},
376 {"mdcr_el3", MDCR_EL3},
377 {"ttbr0_el1", TTBR0_EL1},
378 {"ttbr0_el2", TTBR0_EL2},
379 {"ttbr0_el3", TTBR0_EL3},
380 {"ttbr1_el1", TTBR1_EL1},
381 {"tcr_el1", TCR_EL1},
382 {"tcr_el2", TCR_EL2},
383 {"tcr_el3", TCR_EL3},
384 {"vttbr_el2", VTTBR_EL2},
385 {"vtcr_el2", VTCR_EL2},
386 {"dacr32_el2", DACR32_EL2},
387 {"spsr_el1", SPSR_EL1},
388 {"spsr_el2", SPSR_EL2},
389 {"spsr_el3", SPSR_EL3},
390 {"elr_el1", ELR_EL1},
391 {"elr_el2", ELR_EL2},
392 {"elr_el3", ELR_EL3},
399 {"currentel", CurrentEL},
400 {"spsr_irq", SPSR_irq},
401 {"spsr_abt", SPSR_abt},
402 {"spsr_und", SPSR_und},
403 {"spsr_fiq", SPSR_fiq},
406 {"dspsr_el0", DSPSR_EL0},
407 {"dlr_el0", DLR_EL0},
408 {"ifsr32_el2", IFSR32_EL2},
409 {"afsr0_el1", AFSR0_EL1},
410 {"afsr0_el2", AFSR0_EL2},
411 {"afsr0_el3", AFSR0_EL3},
412 {"afsr1_el1", AFSR1_EL1},
413 {"afsr1_el2", AFSR1_EL2},
414 {"afsr1_el3", AFSR1_EL3},
415 {"esr_el1", ESR_EL1},
416 {"esr_el2", ESR_EL2},
417 {"esr_el3", ESR_EL3},
418 {"fpexc32_el2", FPEXC32_EL2},
419 {"far_el1", FAR_EL1},
420 {"far_el2", FAR_EL2},
421 {"far_el3", FAR_EL3},
422 {"hpfar_el2", HPFAR_EL2},
423 {"par_el1", PAR_EL1},
424 {"pmcr_el0", PMCR_EL0},
425 {"pmcntenset_el0", PMCNTENSET_EL0},
426 {"pmcntenclr_el0", PMCNTENCLR_EL0},
427 {"pmovsclr_el0", PMOVSCLR_EL0},
428 {"pmselr_el0", PMSELR_EL0},
429 {"pmccntr_el0", PMCCNTR_EL0},
430 {"pmxevtyper_el0", PMXEVTYPER_EL0},
431 {"pmxevcntr_el0", PMXEVCNTR_EL0},
432 {"pmuserenr_el0", PMUSERENR_EL0},
433 {"pmintenset_el1", PMINTENSET_EL1},
434 {"pmintenclr_el1", PMINTENCLR_EL1},
435 {"pmovsset_el0", PMOVSSET_EL0},
436 {"mair_el1", MAIR_EL1},
437 {"mair_el2", MAIR_EL2},
438 {"mair_el3", MAIR_EL3},
439 {"amair_el1", AMAIR_EL1},
440 {"amair_el2", AMAIR_EL2},
441 {"amair_el3", AMAIR_EL3},
442 {"vbar_el1", VBAR_EL1},
443 {"vbar_el2", VBAR_EL2},
444 {"vbar_el3", VBAR_EL3},
445 {"rmr_el1", RMR_EL1},
446 {"rmr_el2", RMR_EL2},
447 {"rmr_el3", RMR_EL3},
448 {"contextidr_el1", CONTEXTIDR_EL1},
449 {"tpidr_el0", TPIDR_EL0},
450 {"tpidr_el2", TPIDR_EL2},
451 {"tpidr_el3", TPIDR_EL3},
452 {"tpidrro_el0", TPIDRRO_EL0},
453 {"tpidr_el1", TPIDR_EL1},
454 {"cntfrq_el0", CNTFRQ_EL0},
455 {"cntvoff_el2", CNTVOFF_EL2},
456 {"cntkctl_el1", CNTKCTL_EL1},
457 {"cnthctl_el2", CNTHCTL_EL2},
458 {"cntp_tval_el0", CNTP_TVAL_EL0},
459 {"cnthp_tval_el2", CNTHP_TVAL_EL2},
460 {"cntps_tval_el1", CNTPS_TVAL_EL1},
461 {"cntp_ctl_el0", CNTP_CTL_EL0},
462 {"cnthp_ctl_el2", CNTHP_CTL_EL2},
463 {"cntps_ctl_el1", CNTPS_CTL_EL1},
464 {"cntp_cval_el0", CNTP_CVAL_EL0},
465 {"cnthp_cval_el2", CNTHP_CVAL_EL2},
466 {"cntps_cval_el1", CNTPS_CVAL_EL1},
467 {"cntv_tval_el0", CNTV_TVAL_EL0},
468 {"cntv_ctl_el0", CNTV_CTL_EL0},
469 {"cntv_cval_el0", CNTV_CVAL_EL0},
470 {"pmevcntr0_el0", PMEVCNTR0_EL0},
471 {"pmevcntr1_el0", PMEVCNTR1_EL0},
472 {"pmevcntr2_el0", PMEVCNTR2_EL0},
473 {"pmevcntr3_el0", PMEVCNTR3_EL0},
474 {"pmevcntr4_el0", PMEVCNTR4_EL0},
475 {"pmevcntr5_el0", PMEVCNTR5_EL0},
476 {"pmevcntr6_el0", PMEVCNTR6_EL0},
477 {"pmevcntr7_el0", PMEVCNTR7_EL0},
478 {"pmevcntr8_el0", PMEVCNTR8_EL0},
479 {"pmevcntr9_el0", PMEVCNTR9_EL0},
480 {"pmevcntr10_el0", PMEVCNTR10_EL0},
481 {"pmevcntr11_el0", PMEVCNTR11_EL0},
482 {"pmevcntr12_el0", PMEVCNTR12_EL0},
483 {"pmevcntr13_el0", PMEVCNTR13_EL0},
484 {"pmevcntr14_el0", PMEVCNTR14_EL0},
485 {"pmevcntr15_el0", PMEVCNTR15_EL0},
486 {"pmevcntr16_el0", PMEVCNTR16_EL0},
487 {"pmevcntr17_el0", PMEVCNTR17_EL0},
488 {"pmevcntr18_el0", PMEVCNTR18_EL0},
489 {"pmevcntr19_el0", PMEVCNTR19_EL0},
490 {"pmevcntr20_el0", PMEVCNTR20_EL0},
491 {"pmevcntr21_el0", PMEVCNTR21_EL0},
492 {"pmevcntr22_el0", PMEVCNTR22_EL0},
493 {"pmevcntr23_el0", PMEVCNTR23_EL0},
494 {"pmevcntr24_el0", PMEVCNTR24_EL0},
495 {"pmevcntr25_el0", PMEVCNTR25_EL0},
496 {"pmevcntr26_el0", PMEVCNTR26_EL0},
497 {"pmevcntr27_el0", PMEVCNTR27_EL0},
498 {"pmevcntr28_el0", PMEVCNTR28_EL0},
499 {"pmevcntr29_el0", PMEVCNTR29_EL0},
500 {"pmevcntr30_el0", PMEVCNTR30_EL0},
501 {"pmccfiltr_el0", PMCCFILTR_EL0},
502 {"pmevtyper0_el0", PMEVTYPER0_EL0},
503 {"pmevtyper1_el0", PMEVTYPER1_EL0},
504 {"pmevtyper2_el0", PMEVTYPER2_EL0},
505 {"pmevtyper3_el0", PMEVTYPER3_EL0},
506 {"pmevtyper4_el0", PMEVTYPER4_EL0},
507 {"pmevtyper5_el0", PMEVTYPER5_EL0},
508 {"pmevtyper6_el0", PMEVTYPER6_EL0},
509 {"pmevtyper7_el0", PMEVTYPER7_EL0},
510 {"pmevtyper8_el0", PMEVTYPER8_EL0},
511 {"pmevtyper9_el0", PMEVTYPER9_EL0},
512 {"pmevtyper10_el0", PMEVTYPER10_EL0},
513 {"pmevtyper11_el0", PMEVTYPER11_EL0},
514 {"pmevtyper12_el0", PMEVTYPER12_EL0},
515 {"pmevtyper13_el0", PMEVTYPER13_EL0},
516 {"pmevtyper14_el0", PMEVTYPER14_EL0},
517 {"pmevtyper15_el0", PMEVTYPER15_EL0},
518 {"pmevtyper16_el0", PMEVTYPER16_EL0},
519 {"pmevtyper17_el0", PMEVTYPER17_EL0},
520 {"pmevtyper18_el0", PMEVTYPER18_EL0},
521 {"pmevtyper19_el0", PMEVTYPER19_EL0},
522 {"pmevtyper20_el0", PMEVTYPER20_EL0},
523 {"pmevtyper21_el0", PMEVTYPER21_EL0},
524 {"pmevtyper22_el0", PMEVTYPER22_EL0},
525 {"pmevtyper23_el0", PMEVTYPER23_EL0},
526 {"pmevtyper24_el0", PMEVTYPER24_EL0},
527 {"pmevtyper25_el0", PMEVTYPER25_EL0},
528 {"pmevtyper26_el0", PMEVTYPER26_EL0},
529 {"pmevtyper27_el0", PMEVTYPER27_EL0},
530 {"pmevtyper28_el0", PMEVTYPER28_EL0},
531 {"pmevtyper29_el0", PMEVTYPER29_EL0},
532 {"pmevtyper30_el0", PMEVTYPER30_EL0},
535 {"trcprgctlr", TRCPRGCTLR},
536 {"trcprocselr", TRCPROCSELR},
537 {"trcconfigr", TRCCONFIGR},
538 {"trcauxctlr", TRCAUXCTLR},
539 {"trceventctl0r", TRCEVENTCTL0R},
540 {"trceventctl1r", TRCEVENTCTL1R},
541 {"trcstallctlr", TRCSTALLCTLR},
542 {"trctsctlr", TRCTSCTLR},
543 {"trcsyncpr", TRCSYNCPR},
544 {"trcccctlr", TRCCCCTLR},
545 {"trcbbctlr", TRCBBCTLR},
546 {"trctraceidr", TRCTRACEIDR},
547 {"trcqctlr", TRCQCTLR},
548 {"trcvictlr", TRCVICTLR},
549 {"trcviiectlr", TRCVIIECTLR},
550 {"trcvissctlr", TRCVISSCTLR},
551 {"trcvipcssctlr", TRCVIPCSSCTLR},
552 {"trcvdctlr", TRCVDCTLR},
553 {"trcvdsacctlr", TRCVDSACCTLR},
554 {"trcvdarcctlr", TRCVDARCCTLR},
555 {"trcseqevr0", TRCSEQEVR0},
556 {"trcseqevr1", TRCSEQEVR1},
557 {"trcseqevr2", TRCSEQEVR2},
558 {"trcseqrstevr", TRCSEQRSTEVR},
559 {"trcseqstr", TRCSEQSTR},
560 {"trcextinselr", TRCEXTINSELR},
561 {"trccntrldvr0", TRCCNTRLDVR0},
562 {"trccntrldvr1", TRCCNTRLDVR1},
563 {"trccntrldvr2", TRCCNTRLDVR2},
564 {"trccntrldvr3", TRCCNTRLDVR3},
565 {"trccntctlr0", TRCCNTCTLR0},
566 {"trccntctlr1", TRCCNTCTLR1},
567 {"trccntctlr2", TRCCNTCTLR2},
568 {"trccntctlr3", TRCCNTCTLR3},
569 {"trccntvr0", TRCCNTVR0},
570 {"trccntvr1", TRCCNTVR1},
571 {"trccntvr2", TRCCNTVR2},
572 {"trccntvr3", TRCCNTVR3},
573 {"trcimspec0", TRCIMSPEC0},
574 {"trcimspec1", TRCIMSPEC1},
575 {"trcimspec2", TRCIMSPEC2},
576 {"trcimspec3", TRCIMSPEC3},
577 {"trcimspec4", TRCIMSPEC4},
578 {"trcimspec5", TRCIMSPEC5},
579 {"trcimspec6", TRCIMSPEC6},
580 {"trcimspec7", TRCIMSPEC7},
581 {"trcrsctlr2", TRCRSCTLR2},
582 {"trcrsctlr3", TRCRSCTLR3},
583 {"trcrsctlr4", TRCRSCTLR4},
584 {"trcrsctlr5", TRCRSCTLR5},
585 {"trcrsctlr6", TRCRSCTLR6},
586 {"trcrsctlr7", TRCRSCTLR7},
587 {"trcrsctlr8", TRCRSCTLR8},
588 {"trcrsctlr9", TRCRSCTLR9},
589 {"trcrsctlr10", TRCRSCTLR10},
590 {"trcrsctlr11", TRCRSCTLR11},
591 {"trcrsctlr12", TRCRSCTLR12},
592 {"trcrsctlr13", TRCRSCTLR13},
593 {"trcrsctlr14", TRCRSCTLR14},
594 {"trcrsctlr15", TRCRSCTLR15},
595 {"trcrsctlr16", TRCRSCTLR16},
596 {"trcrsctlr17", TRCRSCTLR17},
597 {"trcrsctlr18", TRCRSCTLR18},
598 {"trcrsctlr19", TRCRSCTLR19},
599 {"trcrsctlr20", TRCRSCTLR20},
600 {"trcrsctlr21", TRCRSCTLR21},
601 {"trcrsctlr22", TRCRSCTLR22},
602 {"trcrsctlr23", TRCRSCTLR23},
603 {"trcrsctlr24", TRCRSCTLR24},
604 {"trcrsctlr25", TRCRSCTLR25},
605 {"trcrsctlr26", TRCRSCTLR26},
606 {"trcrsctlr27", TRCRSCTLR27},
607 {"trcrsctlr28", TRCRSCTLR28},
608 {"trcrsctlr29", TRCRSCTLR29},
609 {"trcrsctlr30", TRCRSCTLR30},
610 {"trcrsctlr31", TRCRSCTLR31},
611 {"trcssccr0", TRCSSCCR0},
612 {"trcssccr1", TRCSSCCR1},
613 {"trcssccr2", TRCSSCCR2},
614 {"trcssccr3", TRCSSCCR3},
615 {"trcssccr4", TRCSSCCR4},
616 {"trcssccr5", TRCSSCCR5},
617 {"trcssccr6", TRCSSCCR6},
618 {"trcssccr7", TRCSSCCR7},
619 {"trcsscsr0", TRCSSCSR0},
620 {"trcsscsr1", TRCSSCSR1},
621 {"trcsscsr2", TRCSSCSR2},
622 {"trcsscsr3", TRCSSCSR3},
623 {"trcsscsr4", TRCSSCSR4},
624 {"trcsscsr5", TRCSSCSR5},
625 {"trcsscsr6", TRCSSCSR6},
626 {"trcsscsr7", TRCSSCSR7},
627 {"trcsspcicr0", TRCSSPCICR0},
628 {"trcsspcicr1", TRCSSPCICR1},
629 {"trcsspcicr2", TRCSSPCICR2},
630 {"trcsspcicr3", TRCSSPCICR3},
631 {"trcsspcicr4", TRCSSPCICR4},
632 {"trcsspcicr5", TRCSSPCICR5},
633 {"trcsspcicr6", TRCSSPCICR6},
634 {"trcsspcicr7", TRCSSPCICR7},
635 {"trcpdcr", TRCPDCR},
636 {"trcacvr0", TRCACVR0},
637 {"trcacvr1", TRCACVR1},
638 {"trcacvr2", TRCACVR2},
639 {"trcacvr3", TRCACVR3},
640 {"trcacvr4", TRCACVR4},
641 {"trcacvr5", TRCACVR5},
642 {"trcacvr6", TRCACVR6},
643 {"trcacvr7", TRCACVR7},
644 {"trcacvr8", TRCACVR8},
645 {"trcacvr9", TRCACVR9},
646 {"trcacvr10", TRCACVR10},
647 {"trcacvr11", TRCACVR11},
648 {"trcacvr12", TRCACVR12},
649 {"trcacvr13", TRCACVR13},
650 {"trcacvr14", TRCACVR14},
651 {"trcacvr15", TRCACVR15},
652 {"trcacatr0", TRCACATR0},
653 {"trcacatr1", TRCACATR1},
654 {"trcacatr2", TRCACATR2},
655 {"trcacatr3", TRCACATR3},
656 {"trcacatr4", TRCACATR4},
657 {"trcacatr5", TRCACATR5},
658 {"trcacatr6", TRCACATR6},
659 {"trcacatr7", TRCACATR7},
660 {"trcacatr8", TRCACATR8},
661 {"trcacatr9", TRCACATR9},
662 {"trcacatr10", TRCACATR10},
663 {"trcacatr11", TRCACATR11},
664 {"trcacatr12", TRCACATR12},
665 {"trcacatr13", TRCACATR13},
666 {"trcacatr14", TRCACATR14},
667 {"trcacatr15", TRCACATR15},
668 {"trcdvcvr0", TRCDVCVR0},
669 {"trcdvcvr1", TRCDVCVR1},
670 {"trcdvcvr2", TRCDVCVR2},
671 {"trcdvcvr3", TRCDVCVR3},
672 {"trcdvcvr4", TRCDVCVR4},
673 {"trcdvcvr5", TRCDVCVR5},
674 {"trcdvcvr6", TRCDVCVR6},
675 {"trcdvcvr7", TRCDVCVR7},
676 {"trcdvcmr0", TRCDVCMR0},
677 {"trcdvcmr1", TRCDVCMR1},
678 {"trcdvcmr2", TRCDVCMR2},
679 {"trcdvcmr3", TRCDVCMR3},
680 {"trcdvcmr4", TRCDVCMR4},
681 {"trcdvcmr5", TRCDVCMR5},
682 {"trcdvcmr6", TRCDVCMR6},
683 {"trcdvcmr7", TRCDVCMR7},
684 {"trccidcvr0", TRCCIDCVR0},
685 {"trccidcvr1", TRCCIDCVR1},
686 {"trccidcvr2", TRCCIDCVR2},
687 {"trccidcvr3", TRCCIDCVR3},
688 {"trccidcvr4", TRCCIDCVR4},
689 {"trccidcvr5", TRCCIDCVR5},
690 {"trccidcvr6", TRCCIDCVR6},
691 {"trccidcvr7", TRCCIDCVR7},
692 {"trcvmidcvr0", TRCVMIDCVR0},
693 {"trcvmidcvr1", TRCVMIDCVR1},
694 {"trcvmidcvr2", TRCVMIDCVR2},
695 {"trcvmidcvr3", TRCVMIDCVR3},
696 {"trcvmidcvr4", TRCVMIDCVR4},
697 {"trcvmidcvr5", TRCVMIDCVR5},
698 {"trcvmidcvr6", TRCVMIDCVR6},
699 {"trcvmidcvr7", TRCVMIDCVR7},
700 {"trccidcctlr0", TRCCIDCCTLR0},
701 {"trccidcctlr1", TRCCIDCCTLR1},
702 {"trcvmidcctlr0", TRCVMIDCCTLR0},
703 {"trcvmidcctlr1", TRCVMIDCCTLR1},
704 {"trcitctrl", TRCITCTRL},
705 {"trcclaimset", TRCCLAIMSET},
706 {"trcclaimclr", TRCCLAIMCLR},
709 {"icc_bpr1_el1", ICC_BPR1_EL1},
710 {"icc_bpr0_el1", ICC_BPR0_EL1},
711 {"icc_pmr_el1", ICC_PMR_EL1},
712 {"icc_ctlr_el1", ICC_CTLR_EL1},
713 {"icc_ctlr_el3", ICC_CTLR_EL3},
714 {"icc_sre_el1", ICC_SRE_EL1},
715 {"icc_sre_el2", ICC_SRE_EL2},
716 {"icc_sre_el3", ICC_SRE_EL3},
717 {"icc_igrpen0_el1", ICC_IGRPEN0_EL1},
718 {"icc_igrpen1_el1", ICC_IGRPEN1_EL1},
719 {"icc_igrpen1_el3", ICC_IGRPEN1_EL3},
720 {"icc_seien_el1", ICC_SEIEN_EL1},
721 {"icc_ap0r0_el1", ICC_AP0R0_EL1},
722 {"icc_ap0r1_el1", ICC_AP0R1_EL1},
723 {"icc_ap0r2_el1", ICC_AP0R2_EL1},
724 {"icc_ap0r3_el1", ICC_AP0R3_EL1},
725 {"icc_ap1r0_el1", ICC_AP1R0_EL1},
726 {"icc_ap1r1_el1", ICC_AP1R1_EL1},
727 {"icc_ap1r2_el1", ICC_AP1R2_EL1},
728 {"icc_ap1r3_el1", ICC_AP1R3_EL1},
729 {"ich_ap0r0_el2", ICH_AP0R0_EL2},
730 {"ich_ap0r1_el2", ICH_AP0R1_EL2},
731 {"ich_ap0r2_el2", ICH_AP0R2_EL2},
732 {"ich_ap0r3_el2", ICH_AP0R3_EL2},
733 {"ich_ap1r0_el2", ICH_AP1R0_EL2},
734 {"ich_ap1r1_el2", ICH_AP1R1_EL2},
735 {"ich_ap1r2_el2", ICH_AP1R2_EL2},
736 {"ich_ap1r3_el2", ICH_AP1R3_EL2},
737 {"ich_hcr_el2", ICH_HCR_EL2},
738 {"ich_misr_el2", ICH_MISR_EL2},
739 {"ich_vmcr_el2", ICH_VMCR_EL2},
740 {"ich_vseir_el2", ICH_VSEIR_EL2},
741 {"ich_lr0_el2", ICH_LR0_EL2},
742 {"ich_lr1_el2", ICH_LR1_EL2},
743 {"ich_lr2_el2", ICH_LR2_EL2},
744 {"ich_lr3_el2", ICH_LR3_EL2},
745 {"ich_lr4_el2", ICH_LR4_EL2},
746 {"ich_lr5_el2", ICH_LR5_EL2},
747 {"ich_lr6_el2", ICH_LR6_EL2},
748 {"ich_lr7_el2", ICH_LR7_EL2},
749 {"ich_lr8_el2", ICH_LR8_EL2},
750 {"ich_lr9_el2", ICH_LR9_EL2},
751 {"ich_lr10_el2", ICH_LR10_EL2},
752 {"ich_lr11_el2", ICH_LR11_EL2},
753 {"ich_lr12_el2", ICH_LR12_EL2},
754 {"ich_lr13_el2", ICH_LR13_EL2},
755 {"ich_lr14_el2", ICH_LR14_EL2},
756 {"ich_lr15_el2", ICH_LR15_EL2}
759 const AArch64NamedImmMapper::Mapping
760 AArch64SysReg::SysRegMapper::CycloneSysRegPairs[] = {
761 {"cpm_ioacc_ctl_el3", CPM_IOACC_CTL_EL3}
765 AArch64SysReg::SysRegMapper::fromString(StringRef Name, bool &Valid) const {
766 std::string NameLower = Name.lower();
768 // First search the registers shared by all
769 for (unsigned i = 0; i < array_lengthof(SysRegPairs); ++i) {
770 if (SysRegPairs[i].Name == NameLower) {
772 return SysRegPairs[i].Value;
776 // Next search for target specific registers
777 if (FeatureBits[AArch64::ProcCyclone]) {
778 for (unsigned i = 0; i < array_lengthof(CycloneSysRegPairs); ++i) {
779 if (CycloneSysRegPairs[i].Name == NameLower) {
781 return CycloneSysRegPairs[i].Value;
786 // Now try the instruction-specific registers (either read-only or
788 for (unsigned i = 0; i < NumInstPairs; ++i) {
789 if (InstPairs[i].Name == NameLower) {
791 return InstPairs[i].Value;
795 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
796 Regex GenericRegPattern("^s([0-3])_([0-7])_c([0-9]|1[0-5])_c([0-9]|1[0-5])_([0-7])$");
798 SmallVector<StringRef, 5> Ops;
799 if (!GenericRegPattern.match(NameLower, &Ops)) {
804 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
806 Ops[1].getAsInteger(10, Op0);
807 Ops[2].getAsInteger(10, Op1);
808 Ops[3].getAsInteger(10, CRn);
809 Ops[4].getAsInteger(10, CRm);
810 Ops[5].getAsInteger(10, Op2);
811 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
818 AArch64SysReg::SysRegMapper::toString(uint32_t Bits) const {
819 // First search the registers shared by all
820 for (unsigned i = 0; i < array_lengthof(SysRegPairs); ++i) {
821 if (SysRegPairs[i].Value == Bits) {
822 return SysRegPairs[i].Name;
826 // Next search for target specific registers
827 if (FeatureBits[AArch64::ProcCyclone]) {
828 for (unsigned i = 0; i < array_lengthof(CycloneSysRegPairs); ++i) {
829 if (CycloneSysRegPairs[i].Value == Bits) {
830 return CycloneSysRegPairs[i].Name;
835 // Now try the instruction-specific registers (either read-only or
837 for (unsigned i = 0; i < NumInstPairs; ++i) {
838 if (InstPairs[i].Value == Bits) {
839 return InstPairs[i].Name;
843 assert(Bits < 0x10000);
844 uint32_t Op0 = (Bits >> 14) & 0x3;
845 uint32_t Op1 = (Bits >> 11) & 0x7;
846 uint32_t CRn = (Bits >> 7) & 0xf;
847 uint32_t CRm = (Bits >> 3) & 0xf;
848 uint32_t Op2 = Bits & 0x7;
850 return "s" + utostr(Op0)+ "_" + utostr(Op1) + "_c" + utostr(CRn)
851 + "_c" + utostr(CRm) + "_" + utostr(Op2);
854 const AArch64NamedImmMapper::Mapping AArch64TLBI::TLBIMapper::TLBIPairs[] = {
855 {"ipas2e1is", IPAS2E1IS},
856 {"ipas2le1is", IPAS2LE1IS},
857 {"vmalle1is", VMALLE1IS},
858 {"alle2is", ALLE2IS},
859 {"alle3is", ALLE3IS},
863 {"aside1is", ASIDE1IS},
864 {"vaae1is", VAAE1IS},
865 {"alle1is", ALLE1IS},
866 {"vale1is", VALE1IS},
867 {"vale2is", VALE2IS},
868 {"vale3is", VALE3IS},
869 {"vmalls12e1is", VMALLS12E1IS},
870 {"vaale1is", VAALE1IS},
871 {"ipas2e1", IPAS2E1},
872 {"ipas2le1", IPAS2LE1},
873 {"vmalle1", VMALLE1},
885 {"vmalls12e1", VMALLS12E1},
889 AArch64TLBI::TLBIMapper::TLBIMapper()
890 : AArch64NamedImmMapper(TLBIPairs, 0) {}