1 //==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an AArch64 MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64InstPrinter.h"
15 #include "MCTargetDesc/AArch64AddressingModes.h"
16 #include "Utils/AArch64BaseInfo.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/Format.h"
23 #include "llvm/Support/raw_ostream.h"
26 #define DEBUG_TYPE "asm-printer"
28 #define GET_INSTRUCTION_NAME
29 #define PRINT_ALIAS_INSTR
30 #include "AArch64GenAsmWriter.inc"
31 #define GET_INSTRUCTION_NAME
32 #define PRINT_ALIAS_INSTR
33 #include "AArch64GenAsmWriter1.inc"
35 AArch64InstPrinter::AArch64InstPrinter(const MCAsmInfo &MAI,
36 const MCInstrInfo &MII,
37 const MCRegisterInfo &MRI,
38 const MCSubtargetInfo &STI)
39 : MCInstPrinter(MAI, MII, MRI) {
40 // Initialize the set of available features.
41 setAvailableFeatures(STI.getFeatureBits());
44 AArch64AppleInstPrinter::AArch64AppleInstPrinter(const MCAsmInfo &MAI,
45 const MCInstrInfo &MII,
46 const MCRegisterInfo &MRI,
47 const MCSubtargetInfo &STI)
48 : AArch64InstPrinter(MAI, MII, MRI, STI) {}
50 void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
51 // This is for .cfi directives.
52 OS << getRegisterName(RegNo);
55 void AArch64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
57 const MCSubtargetInfo &STI) {
58 // Check for special encodings and print the canonical alias instead.
60 unsigned Opcode = MI->getOpcode();
62 if (Opcode == AArch64::SYSxt)
63 if (printSysAlias(MI, O)) {
64 printAnnotation(O, Annot);
68 // SBFM/UBFM should print to a nicer aliased form if possible.
69 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri ||
70 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) {
71 const MCOperand &Op0 = MI->getOperand(0);
72 const MCOperand &Op1 = MI->getOperand(1);
73 const MCOperand &Op2 = MI->getOperand(2);
74 const MCOperand &Op3 = MI->getOperand(3);
76 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri);
77 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri);
78 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
79 const char *AsmMnemonic = nullptr;
81 switch (Op3.getImm()) {
97 // *xtw is only valid for signed 64-bit operations.
98 if (Is64Bit && IsSigned)
104 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
105 << ", " << getRegisterName(getWRegFromXReg(Op1.getReg()));
106 printAnnotation(O, Annot);
111 // All immediate shifts are aliases, implemented using the Bitfield
112 // instruction. In all cases the immediate shift amount shift must be in
113 // the range 0 to (reg.size -1).
114 if (Op2.isImm() && Op3.isImm()) {
115 const char *AsmMnemonic = nullptr;
117 int64_t immr = Op2.getImm();
118 int64_t imms = Op3.getImm();
119 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
122 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f &&
123 ((imms + 1 == immr))) {
126 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) {
129 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) {
132 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) {
135 } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) {
140 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
141 << ", " << getRegisterName(Op1.getReg()) << ", #" << shift;
142 printAnnotation(O, Annot);
147 // SBFIZ/UBFIZ aliases
148 if (Op2.getImm() > Op3.getImm()) {
149 O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t'
150 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
151 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
152 printAnnotation(O, Annot);
156 // Otherwise SBFX/UBFX is the preferred form
157 O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t'
158 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
159 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
160 printAnnotation(O, Annot);
164 if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) {
165 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
166 const MCOperand &Op2 = MI->getOperand(2);
167 int ImmR = MI->getOperand(3).getImm();
168 int ImmS = MI->getOperand(4).getImm();
172 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32;
173 int LSB = (BitWidth - ImmR) % BitWidth;
174 int Width = ImmS + 1;
175 O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", "
176 << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width;
177 printAnnotation(O, Annot);
182 int Width = ImmS - ImmR + 1;
183 // Otherwise BFXIL the preferred form
185 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg())
186 << ", #" << LSB << ", #" << Width;
187 printAnnotation(O, Annot);
191 // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift
192 // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be
194 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi ||
195 Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) &&
196 MI->getOperand(1).isExpr()) {
197 if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi)
202 O << getRegisterName(MI->getOperand(0).getReg()) << ", #"
203 << *MI->getOperand(1).getExpr();
207 if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) &&
208 MI->getOperand(2).isExpr()) {
209 O << "\tmovk\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
210 << *MI->getOperand(2).getExpr();
214 if (!printAliasInstr(MI, STI, O))
215 printInstruction(MI, STI, O);
217 printAnnotation(O, Annot);
220 static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout,
223 case AArch64::TBXv8i8One:
224 case AArch64::TBXv8i8Two:
225 case AArch64::TBXv8i8Three:
226 case AArch64::TBXv8i8Four:
230 case AArch64::TBLv8i8One:
231 case AArch64::TBLv8i8Two:
232 case AArch64::TBLv8i8Three:
233 case AArch64::TBLv8i8Four:
237 case AArch64::TBXv16i8One:
238 case AArch64::TBXv16i8Two:
239 case AArch64::TBXv16i8Three:
240 case AArch64::TBXv16i8Four:
244 case AArch64::TBLv16i8One:
245 case AArch64::TBLv16i8Two:
246 case AArch64::TBLv16i8Three:
247 case AArch64::TBLv16i8Four:
256 struct LdStNInstrDesc {
258 const char *Mnemonic;
265 static LdStNInstrDesc LdStNInstInfo[] = {
266 { AArch64::LD1i8, "ld1", ".b", 1, true, 0 },
267 { AArch64::LD1i16, "ld1", ".h", 1, true, 0 },
268 { AArch64::LD1i32, "ld1", ".s", 1, true, 0 },
269 { AArch64::LD1i64, "ld1", ".d", 1, true, 0 },
270 { AArch64::LD1i8_POST, "ld1", ".b", 2, true, 1 },
271 { AArch64::LD1i16_POST, "ld1", ".h", 2, true, 2 },
272 { AArch64::LD1i32_POST, "ld1", ".s", 2, true, 4 },
273 { AArch64::LD1i64_POST, "ld1", ".d", 2, true, 8 },
274 { AArch64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 },
275 { AArch64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 },
276 { AArch64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 },
277 { AArch64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 },
278 { AArch64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 },
279 { AArch64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 },
280 { AArch64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 },
281 { AArch64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 },
282 { AArch64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 },
283 { AArch64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 },
284 { AArch64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 },
285 { AArch64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 },
286 { AArch64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 },
287 { AArch64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 },
288 { AArch64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 },
289 { AArch64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 },
290 { AArch64::LD1Onev16b, "ld1", ".16b", 0, false, 0 },
291 { AArch64::LD1Onev8h, "ld1", ".8h", 0, false, 0 },
292 { AArch64::LD1Onev4s, "ld1", ".4s", 0, false, 0 },
293 { AArch64::LD1Onev2d, "ld1", ".2d", 0, false, 0 },
294 { AArch64::LD1Onev8b, "ld1", ".8b", 0, false, 0 },
295 { AArch64::LD1Onev4h, "ld1", ".4h", 0, false, 0 },
296 { AArch64::LD1Onev2s, "ld1", ".2s", 0, false, 0 },
297 { AArch64::LD1Onev1d, "ld1", ".1d", 0, false, 0 },
298 { AArch64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 },
299 { AArch64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 },
300 { AArch64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 },
301 { AArch64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 },
302 { AArch64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 },
303 { AArch64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 },
304 { AArch64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 },
305 { AArch64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 },
306 { AArch64::LD1Twov16b, "ld1", ".16b", 0, false, 0 },
307 { AArch64::LD1Twov8h, "ld1", ".8h", 0, false, 0 },
308 { AArch64::LD1Twov4s, "ld1", ".4s", 0, false, 0 },
309 { AArch64::LD1Twov2d, "ld1", ".2d", 0, false, 0 },
310 { AArch64::LD1Twov8b, "ld1", ".8b", 0, false, 0 },
311 { AArch64::LD1Twov4h, "ld1", ".4h", 0, false, 0 },
312 { AArch64::LD1Twov2s, "ld1", ".2s", 0, false, 0 },
313 { AArch64::LD1Twov1d, "ld1", ".1d", 0, false, 0 },
314 { AArch64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 },
315 { AArch64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 },
316 { AArch64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 },
317 { AArch64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 },
318 { AArch64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 },
319 { AArch64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 },
320 { AArch64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 },
321 { AArch64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 },
322 { AArch64::LD1Threev16b, "ld1", ".16b", 0, false, 0 },
323 { AArch64::LD1Threev8h, "ld1", ".8h", 0, false, 0 },
324 { AArch64::LD1Threev4s, "ld1", ".4s", 0, false, 0 },
325 { AArch64::LD1Threev2d, "ld1", ".2d", 0, false, 0 },
326 { AArch64::LD1Threev8b, "ld1", ".8b", 0, false, 0 },
327 { AArch64::LD1Threev4h, "ld1", ".4h", 0, false, 0 },
328 { AArch64::LD1Threev2s, "ld1", ".2s", 0, false, 0 },
329 { AArch64::LD1Threev1d, "ld1", ".1d", 0, false, 0 },
330 { AArch64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 },
331 { AArch64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 },
332 { AArch64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 },
333 { AArch64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 },
334 { AArch64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 },
335 { AArch64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 },
336 { AArch64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 },
337 { AArch64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 },
338 { AArch64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 },
339 { AArch64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 },
340 { AArch64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 },
341 { AArch64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 },
342 { AArch64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 },
343 { AArch64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 },
344 { AArch64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 },
345 { AArch64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 },
346 { AArch64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 },
347 { AArch64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 },
348 { AArch64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 },
349 { AArch64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 },
350 { AArch64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 },
351 { AArch64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 },
352 { AArch64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 },
353 { AArch64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 },
354 { AArch64::LD2i8, "ld2", ".b", 1, true, 0 },
355 { AArch64::LD2i16, "ld2", ".h", 1, true, 0 },
356 { AArch64::LD2i32, "ld2", ".s", 1, true, 0 },
357 { AArch64::LD2i64, "ld2", ".d", 1, true, 0 },
358 { AArch64::LD2i8_POST, "ld2", ".b", 2, true, 2 },
359 { AArch64::LD2i16_POST, "ld2", ".h", 2, true, 4 },
360 { AArch64::LD2i32_POST, "ld2", ".s", 2, true, 8 },
361 { AArch64::LD2i64_POST, "ld2", ".d", 2, true, 16 },
362 { AArch64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 },
363 { AArch64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 },
364 { AArch64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 },
365 { AArch64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 },
366 { AArch64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 },
367 { AArch64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 },
368 { AArch64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 },
369 { AArch64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 },
370 { AArch64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 },
371 { AArch64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 },
372 { AArch64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 },
373 { AArch64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 },
374 { AArch64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 },
375 { AArch64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 },
376 { AArch64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 },
377 { AArch64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 },
378 { AArch64::LD2Twov16b, "ld2", ".16b", 0, false, 0 },
379 { AArch64::LD2Twov8h, "ld2", ".8h", 0, false, 0 },
380 { AArch64::LD2Twov4s, "ld2", ".4s", 0, false, 0 },
381 { AArch64::LD2Twov2d, "ld2", ".2d", 0, false, 0 },
382 { AArch64::LD2Twov8b, "ld2", ".8b", 0, false, 0 },
383 { AArch64::LD2Twov4h, "ld2", ".4h", 0, false, 0 },
384 { AArch64::LD2Twov2s, "ld2", ".2s", 0, false, 0 },
385 { AArch64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 },
386 { AArch64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 },
387 { AArch64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 },
388 { AArch64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 },
389 { AArch64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 },
390 { AArch64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 },
391 { AArch64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 },
392 { AArch64::LD3i8, "ld3", ".b", 1, true, 0 },
393 { AArch64::LD3i16, "ld3", ".h", 1, true, 0 },
394 { AArch64::LD3i32, "ld3", ".s", 1, true, 0 },
395 { AArch64::LD3i64, "ld3", ".d", 1, true, 0 },
396 { AArch64::LD3i8_POST, "ld3", ".b", 2, true, 3 },
397 { AArch64::LD3i16_POST, "ld3", ".h", 2, true, 6 },
398 { AArch64::LD3i32_POST, "ld3", ".s", 2, true, 12 },
399 { AArch64::LD3i64_POST, "ld3", ".d", 2, true, 24 },
400 { AArch64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 },
401 { AArch64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 },
402 { AArch64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 },
403 { AArch64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 },
404 { AArch64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 },
405 { AArch64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 },
406 { AArch64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 },
407 { AArch64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 },
408 { AArch64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 },
409 { AArch64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 },
410 { AArch64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 },
411 { AArch64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 },
412 { AArch64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 },
413 { AArch64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 },
414 { AArch64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 },
415 { AArch64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 },
416 { AArch64::LD3Threev16b, "ld3", ".16b", 0, false, 0 },
417 { AArch64::LD3Threev8h, "ld3", ".8h", 0, false, 0 },
418 { AArch64::LD3Threev4s, "ld3", ".4s", 0, false, 0 },
419 { AArch64::LD3Threev2d, "ld3", ".2d", 0, false, 0 },
420 { AArch64::LD3Threev8b, "ld3", ".8b", 0, false, 0 },
421 { AArch64::LD3Threev4h, "ld3", ".4h", 0, false, 0 },
422 { AArch64::LD3Threev2s, "ld3", ".2s", 0, false, 0 },
423 { AArch64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 },
424 { AArch64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 },
425 { AArch64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 },
426 { AArch64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 },
427 { AArch64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 },
428 { AArch64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 },
429 { AArch64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 },
430 { AArch64::LD4i8, "ld4", ".b", 1, true, 0 },
431 { AArch64::LD4i16, "ld4", ".h", 1, true, 0 },
432 { AArch64::LD4i32, "ld4", ".s", 1, true, 0 },
433 { AArch64::LD4i64, "ld4", ".d", 1, true, 0 },
434 { AArch64::LD4i8_POST, "ld4", ".b", 2, true, 4 },
435 { AArch64::LD4i16_POST, "ld4", ".h", 2, true, 8 },
436 { AArch64::LD4i32_POST, "ld4", ".s", 2, true, 16 },
437 { AArch64::LD4i64_POST, "ld4", ".d", 2, true, 32 },
438 { AArch64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 },
439 { AArch64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 },
440 { AArch64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 },
441 { AArch64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 },
442 { AArch64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 },
443 { AArch64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 },
444 { AArch64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 },
445 { AArch64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 },
446 { AArch64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 },
447 { AArch64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 },
448 { AArch64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 },
449 { AArch64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 },
450 { AArch64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 },
451 { AArch64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 },
452 { AArch64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 },
453 { AArch64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 },
454 { AArch64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 },
455 { AArch64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 },
456 { AArch64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 },
457 { AArch64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 },
458 { AArch64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 },
459 { AArch64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 },
460 { AArch64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 },
461 { AArch64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 },
462 { AArch64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 },
463 { AArch64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 },
464 { AArch64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 },
465 { AArch64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 },
466 { AArch64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 },
467 { AArch64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 },
468 { AArch64::ST1i8, "st1", ".b", 0, true, 0 },
469 { AArch64::ST1i16, "st1", ".h", 0, true, 0 },
470 { AArch64::ST1i32, "st1", ".s", 0, true, 0 },
471 { AArch64::ST1i64, "st1", ".d", 0, true, 0 },
472 { AArch64::ST1i8_POST, "st1", ".b", 1, true, 1 },
473 { AArch64::ST1i16_POST, "st1", ".h", 1, true, 2 },
474 { AArch64::ST1i32_POST, "st1", ".s", 1, true, 4 },
475 { AArch64::ST1i64_POST, "st1", ".d", 1, true, 8 },
476 { AArch64::ST1Onev16b, "st1", ".16b", 0, false, 0 },
477 { AArch64::ST1Onev8h, "st1", ".8h", 0, false, 0 },
478 { AArch64::ST1Onev4s, "st1", ".4s", 0, false, 0 },
479 { AArch64::ST1Onev2d, "st1", ".2d", 0, false, 0 },
480 { AArch64::ST1Onev8b, "st1", ".8b", 0, false, 0 },
481 { AArch64::ST1Onev4h, "st1", ".4h", 0, false, 0 },
482 { AArch64::ST1Onev2s, "st1", ".2s", 0, false, 0 },
483 { AArch64::ST1Onev1d, "st1", ".1d", 0, false, 0 },
484 { AArch64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 },
485 { AArch64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 },
486 { AArch64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 },
487 { AArch64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 },
488 { AArch64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 },
489 { AArch64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 },
490 { AArch64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 },
491 { AArch64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 },
492 { AArch64::ST1Twov16b, "st1", ".16b", 0, false, 0 },
493 { AArch64::ST1Twov8h, "st1", ".8h", 0, false, 0 },
494 { AArch64::ST1Twov4s, "st1", ".4s", 0, false, 0 },
495 { AArch64::ST1Twov2d, "st1", ".2d", 0, false, 0 },
496 { AArch64::ST1Twov8b, "st1", ".8b", 0, false, 0 },
497 { AArch64::ST1Twov4h, "st1", ".4h", 0, false, 0 },
498 { AArch64::ST1Twov2s, "st1", ".2s", 0, false, 0 },
499 { AArch64::ST1Twov1d, "st1", ".1d", 0, false, 0 },
500 { AArch64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 },
501 { AArch64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 },
502 { AArch64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 },
503 { AArch64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 },
504 { AArch64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 },
505 { AArch64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 },
506 { AArch64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 },
507 { AArch64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 },
508 { AArch64::ST1Threev16b, "st1", ".16b", 0, false, 0 },
509 { AArch64::ST1Threev8h, "st1", ".8h", 0, false, 0 },
510 { AArch64::ST1Threev4s, "st1", ".4s", 0, false, 0 },
511 { AArch64::ST1Threev2d, "st1", ".2d", 0, false, 0 },
512 { AArch64::ST1Threev8b, "st1", ".8b", 0, false, 0 },
513 { AArch64::ST1Threev4h, "st1", ".4h", 0, false, 0 },
514 { AArch64::ST1Threev2s, "st1", ".2s", 0, false, 0 },
515 { AArch64::ST1Threev1d, "st1", ".1d", 0, false, 0 },
516 { AArch64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 },
517 { AArch64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 },
518 { AArch64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 },
519 { AArch64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 },
520 { AArch64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 },
521 { AArch64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 },
522 { AArch64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 },
523 { AArch64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 },
524 { AArch64::ST1Fourv16b, "st1", ".16b", 0, false, 0 },
525 { AArch64::ST1Fourv8h, "st1", ".8h", 0, false, 0 },
526 { AArch64::ST1Fourv4s, "st1", ".4s", 0, false, 0 },
527 { AArch64::ST1Fourv2d, "st1", ".2d", 0, false, 0 },
528 { AArch64::ST1Fourv8b, "st1", ".8b", 0, false, 0 },
529 { AArch64::ST1Fourv4h, "st1", ".4h", 0, false, 0 },
530 { AArch64::ST1Fourv2s, "st1", ".2s", 0, false, 0 },
531 { AArch64::ST1Fourv1d, "st1", ".1d", 0, false, 0 },
532 { AArch64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 },
533 { AArch64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 },
534 { AArch64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 },
535 { AArch64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 },
536 { AArch64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 },
537 { AArch64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 },
538 { AArch64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 },
539 { AArch64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 },
540 { AArch64::ST2i8, "st2", ".b", 0, true, 0 },
541 { AArch64::ST2i16, "st2", ".h", 0, true, 0 },
542 { AArch64::ST2i32, "st2", ".s", 0, true, 0 },
543 { AArch64::ST2i64, "st2", ".d", 0, true, 0 },
544 { AArch64::ST2i8_POST, "st2", ".b", 1, true, 2 },
545 { AArch64::ST2i16_POST, "st2", ".h", 1, true, 4 },
546 { AArch64::ST2i32_POST, "st2", ".s", 1, true, 8 },
547 { AArch64::ST2i64_POST, "st2", ".d", 1, true, 16 },
548 { AArch64::ST2Twov16b, "st2", ".16b", 0, false, 0 },
549 { AArch64::ST2Twov8h, "st2", ".8h", 0, false, 0 },
550 { AArch64::ST2Twov4s, "st2", ".4s", 0, false, 0 },
551 { AArch64::ST2Twov2d, "st2", ".2d", 0, false, 0 },
552 { AArch64::ST2Twov8b, "st2", ".8b", 0, false, 0 },
553 { AArch64::ST2Twov4h, "st2", ".4h", 0, false, 0 },
554 { AArch64::ST2Twov2s, "st2", ".2s", 0, false, 0 },
555 { AArch64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 },
556 { AArch64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 },
557 { AArch64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 },
558 { AArch64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 },
559 { AArch64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 },
560 { AArch64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 },
561 { AArch64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 },
562 { AArch64::ST3i8, "st3", ".b", 0, true, 0 },
563 { AArch64::ST3i16, "st3", ".h", 0, true, 0 },
564 { AArch64::ST3i32, "st3", ".s", 0, true, 0 },
565 { AArch64::ST3i64, "st3", ".d", 0, true, 0 },
566 { AArch64::ST3i8_POST, "st3", ".b", 1, true, 3 },
567 { AArch64::ST3i16_POST, "st3", ".h", 1, true, 6 },
568 { AArch64::ST3i32_POST, "st3", ".s", 1, true, 12 },
569 { AArch64::ST3i64_POST, "st3", ".d", 1, true, 24 },
570 { AArch64::ST3Threev16b, "st3", ".16b", 0, false, 0 },
571 { AArch64::ST3Threev8h, "st3", ".8h", 0, false, 0 },
572 { AArch64::ST3Threev4s, "st3", ".4s", 0, false, 0 },
573 { AArch64::ST3Threev2d, "st3", ".2d", 0, false, 0 },
574 { AArch64::ST3Threev8b, "st3", ".8b", 0, false, 0 },
575 { AArch64::ST3Threev4h, "st3", ".4h", 0, false, 0 },
576 { AArch64::ST3Threev2s, "st3", ".2s", 0, false, 0 },
577 { AArch64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 },
578 { AArch64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 },
579 { AArch64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 },
580 { AArch64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 },
581 { AArch64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 },
582 { AArch64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 },
583 { AArch64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 },
584 { AArch64::ST4i8, "st4", ".b", 0, true, 0 },
585 { AArch64::ST4i16, "st4", ".h", 0, true, 0 },
586 { AArch64::ST4i32, "st4", ".s", 0, true, 0 },
587 { AArch64::ST4i64, "st4", ".d", 0, true, 0 },
588 { AArch64::ST4i8_POST, "st4", ".b", 1, true, 4 },
589 { AArch64::ST4i16_POST, "st4", ".h", 1, true, 8 },
590 { AArch64::ST4i32_POST, "st4", ".s", 1, true, 16 },
591 { AArch64::ST4i64_POST, "st4", ".d", 1, true, 32 },
592 { AArch64::ST4Fourv16b, "st4", ".16b", 0, false, 0 },
593 { AArch64::ST4Fourv8h, "st4", ".8h", 0, false, 0 },
594 { AArch64::ST4Fourv4s, "st4", ".4s", 0, false, 0 },
595 { AArch64::ST4Fourv2d, "st4", ".2d", 0, false, 0 },
596 { AArch64::ST4Fourv8b, "st4", ".8b", 0, false, 0 },
597 { AArch64::ST4Fourv4h, "st4", ".4h", 0, false, 0 },
598 { AArch64::ST4Fourv2s, "st4", ".2s", 0, false, 0 },
599 { AArch64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 },
600 { AArch64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 },
601 { AArch64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 },
602 { AArch64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 },
603 { AArch64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 },
604 { AArch64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 },
605 { AArch64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 },
608 static LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) {
610 for (Idx = 0; Idx != array_lengthof(LdStNInstInfo); ++Idx)
611 if (LdStNInstInfo[Idx].Opcode == Opcode)
612 return &LdStNInstInfo[Idx];
617 void AArch64AppleInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
619 const MCSubtargetInfo &STI) {
620 unsigned Opcode = MI->getOpcode();
621 StringRef Layout, Mnemonic;
624 if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
625 O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t'
626 << getRegisterName(MI->getOperand(0).getReg(), AArch64::vreg) << ", ";
628 unsigned ListOpNum = IsTbx ? 2 : 1;
629 printVectorList(MI, ListOpNum, STI, O, "");
632 << getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
633 printAnnotation(O, Annot);
637 if (LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) {
638 O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t';
640 // Now onto the operands: first a vector list with possible lane
641 // specifier. E.g. { v0 }[2]
642 int OpNum = LdStDesc->ListOperand;
643 printVectorList(MI, OpNum++, STI, O, "");
645 if (LdStDesc->HasLane)
646 O << '[' << MI->getOperand(OpNum++).getImm() << ']';
648 // Next the address: [xN]
649 unsigned AddrReg = MI->getOperand(OpNum++).getReg();
650 O << ", [" << getRegisterName(AddrReg) << ']';
652 // Finally, there might be a post-indexed offset.
653 if (LdStDesc->NaturalOffset != 0) {
654 unsigned Reg = MI->getOperand(OpNum++).getReg();
655 if (Reg != AArch64::XZR)
656 O << ", " << getRegisterName(Reg);
658 assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?");
659 O << ", #" << LdStDesc->NaturalOffset;
663 printAnnotation(O, Annot);
667 AArch64InstPrinter::printInst(MI, O, Annot, STI);
670 bool AArch64InstPrinter::printSysAlias(const MCInst *MI, raw_ostream &O) {
672 unsigned Opcode = MI->getOpcode();
673 assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!");
676 const char *Asm = nullptr;
677 const MCOperand &Op1 = MI->getOperand(0);
678 const MCOperand &Cn = MI->getOperand(1);
679 const MCOperand &Cm = MI->getOperand(2);
680 const MCOperand &Op2 = MI->getOperand(3);
682 unsigned Op1Val = Op1.getImm();
683 unsigned CnVal = Cn.getImm();
684 unsigned CmVal = Cm.getImm();
685 unsigned Op2Val = Op2.getImm();
694 if (Op1Val == 0 && Op2Val == 0)
698 if (Op1Val == 0 && Op2Val == 0)
700 else if (Op1Val == 3 && Op2Val == 1)
706 if (Op1Val == 3 && Op2Val == 1)
710 if (Op1Val == 0 && Op2Val == 1)
712 if (Op1Val == 0 && Op2Val == 2)
716 if (Op1Val == 3 && Op2Val == 1)
718 else if (Op1Val == 0 && Op2Val == 2)
722 if (Op1Val == 3 && Op2Val == 1)
726 if (Op1Val == 3 && Op2Val == 1)
728 else if (Op1Val == 0 && Op2Val == 2)
741 case 0: Asm = "at\ts1e1r"; break;
742 case 1: Asm = "at\ts1e1w"; break;
743 case 2: Asm = "at\ts1e0r"; break;
744 case 3: Asm = "at\ts1e0w"; break;
751 case 0: Asm = "at\ts1e2r"; break;
752 case 1: Asm = "at\ts1e2w"; break;
753 case 4: Asm = "at\ts12e1r"; break;
754 case 5: Asm = "at\ts12e1w"; break;
755 case 6: Asm = "at\ts12e0r"; break;
756 case 7: Asm = "at\ts12e0w"; break;
763 case 0: Asm = "at\ts1e3r"; break;
764 case 1: Asm = "at\ts1e3w"; break;
770 } else if (CnVal == 8) {
783 case 0: Asm = "tlbi\tvmalle1is"; break;
784 case 1: Asm = "tlbi\tvae1is"; break;
785 case 2: Asm = "tlbi\taside1is"; break;
786 case 3: Asm = "tlbi\tvaae1is"; break;
787 case 5: Asm = "tlbi\tvale1is"; break;
788 case 7: Asm = "tlbi\tvaale1is"; break;
795 case 0: Asm = "tlbi\talle2is"; break;
796 case 1: Asm = "tlbi\tvae2is"; break;
797 case 4: Asm = "tlbi\talle1is"; break;
798 case 5: Asm = "tlbi\tvale2is"; break;
799 case 6: Asm = "tlbi\tvmalls12e1is"; break;
806 case 0: Asm = "tlbi\talle3is"; break;
807 case 1: Asm = "tlbi\tvae3is"; break;
808 case 5: Asm = "tlbi\tvale3is"; break;
821 case 1: Asm = "tlbi\tipas2e1is"; break;
822 case 5: Asm = "tlbi\tipas2le1is"; break;
835 case 1: Asm = "tlbi\tipas2e1"; break;
836 case 5: Asm = "tlbi\tipas2le1"; break;
849 case 0: Asm = "tlbi\tvmalle1"; break;
850 case 1: Asm = "tlbi\tvae1"; break;
851 case 2: Asm = "tlbi\taside1"; break;
852 case 3: Asm = "tlbi\tvaae1"; break;
853 case 5: Asm = "tlbi\tvale1"; break;
854 case 7: Asm = "tlbi\tvaale1"; break;
861 case 0: Asm = "tlbi\talle2"; break;
862 case 1: Asm = "tlbi\tvae2"; break;
863 case 4: Asm = "tlbi\talle1"; break;
864 case 5: Asm = "tlbi\tvale2"; break;
865 case 6: Asm = "tlbi\tvmalls12e1"; break;
872 case 0: Asm = "tlbi\talle3"; break;
873 case 1: Asm = "tlbi\tvae3"; break;
874 case 5: Asm = "tlbi\tvale3"; break;
883 unsigned Reg = MI->getOperand(4).getReg();
886 if (StringRef(Asm).lower().find("all") == StringRef::npos)
887 O << ", " << getRegisterName(Reg);
890 return Asm != nullptr;
893 void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
894 const MCSubtargetInfo &STI,
896 const MCOperand &Op = MI->getOperand(OpNo);
898 unsigned Reg = Op.getReg();
899 O << getRegisterName(Reg);
900 } else if (Op.isImm()) {
901 O << '#' << Op.getImm();
903 assert(Op.isExpr() && "unknown operand kind in printOperand");
908 void AArch64InstPrinter::printHexImm(const MCInst *MI, unsigned OpNo,
909 const MCSubtargetInfo &STI,
911 const MCOperand &Op = MI->getOperand(OpNo);
912 O << format("#%#llx", Op.getImm());
915 void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
916 unsigned Imm, raw_ostream &O) {
917 const MCOperand &Op = MI->getOperand(OpNo);
919 unsigned Reg = Op.getReg();
920 if (Reg == AArch64::XZR)
923 O << getRegisterName(Reg);
925 llvm_unreachable("unknown operand kind in printPostIncOperand64");
928 void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
929 const MCSubtargetInfo &STI,
931 const MCOperand &Op = MI->getOperand(OpNo);
932 assert(Op.isReg() && "Non-register vreg operand!");
933 unsigned Reg = Op.getReg();
934 O << getRegisterName(Reg, AArch64::vreg);
937 void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo,
938 const MCSubtargetInfo &STI,
940 const MCOperand &Op = MI->getOperand(OpNo);
941 assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
942 O << "c" << Op.getImm();
945 void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
946 const MCSubtargetInfo &STI,
948 const MCOperand &MO = MI->getOperand(OpNum);
950 unsigned Val = (MO.getImm() & 0xfff);
951 assert(Val == MO.getImm() && "Add/sub immediate out of range!");
953 AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
956 printShifter(MI, OpNum + 1, STI, O);
959 *CommentStream << '=' << (Val << Shift) << '\n';
961 assert(MO.isExpr() && "Unexpected operand type!");
963 printShifter(MI, OpNum + 1, STI, O);
967 void AArch64InstPrinter::printLogicalImm32(const MCInst *MI, unsigned OpNum,
968 const MCSubtargetInfo &STI,
970 uint64_t Val = MI->getOperand(OpNum).getImm();
972 O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 32));
975 void AArch64InstPrinter::printLogicalImm64(const MCInst *MI, unsigned OpNum,
976 const MCSubtargetInfo &STI,
978 uint64_t Val = MI->getOperand(OpNum).getImm();
980 O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 64));
983 void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
984 const MCSubtargetInfo &STI,
986 unsigned Val = MI->getOperand(OpNum).getImm();
987 // LSL #0 should not be printed.
988 if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL &&
989 AArch64_AM::getShiftValue(Val) == 0)
991 O << ", " << AArch64_AM::getShiftExtendName(AArch64_AM::getShiftType(Val))
992 << " #" << AArch64_AM::getShiftValue(Val);
995 void AArch64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum,
996 const MCSubtargetInfo &STI,
998 O << getRegisterName(MI->getOperand(OpNum).getReg());
999 printShifter(MI, OpNum + 1, STI, O);
1002 void AArch64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum,
1003 const MCSubtargetInfo &STI,
1005 O << getRegisterName(MI->getOperand(OpNum).getReg());
1006 printArithExtend(MI, OpNum + 1, STI, O);
1009 void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
1010 const MCSubtargetInfo &STI,
1012 unsigned Val = MI->getOperand(OpNum).getImm();
1013 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val);
1014 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val);
1016 // If the destination or first source register operand is [W]SP, print
1017 // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
1019 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) {
1020 unsigned Dest = MI->getOperand(0).getReg();
1021 unsigned Src1 = MI->getOperand(1).getReg();
1022 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
1023 ExtType == AArch64_AM::UXTX) ||
1024 ((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
1025 ExtType == AArch64_AM::UXTW) ) {
1027 O << ", lsl #" << ShiftVal;
1031 O << ", " << AArch64_AM::getShiftExtendName(ExtType);
1033 O << " #" << ShiftVal;
1036 void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
1037 raw_ostream &O, char SrcRegKind,
1039 unsigned SignExtend = MI->getOperand(OpNum).getImm();
1040 unsigned DoShift = MI->getOperand(OpNum + 1).getImm();
1042 // sxtw, sxtx, uxtw or lsl (== uxtx)
1043 bool IsLSL = !SignExtend && SrcRegKind == 'x';
1047 O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind;
1049 if (DoShift || IsLSL)
1050 O << " #" << Log2_32(Width / 8);
1053 void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
1054 const MCSubtargetInfo &STI,
1056 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
1057 O << AArch64CC::getCondCodeName(CC);
1060 void AArch64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
1061 const MCSubtargetInfo &STI,
1063 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm();
1064 O << AArch64CC::getCondCodeName(AArch64CC::getInvertedCondCode(CC));
1067 void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
1068 const MCSubtargetInfo &STI,
1070 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']';
1074 void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
1075 const MCSubtargetInfo &STI,
1077 O << '#' << Scale * MI->getOperand(OpNum).getImm();
1080 void AArch64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum,
1081 unsigned Scale, raw_ostream &O) {
1082 const MCOperand MO = MI->getOperand(OpNum);
1084 O << "#" << (MO.getImm() * Scale);
1086 assert(MO.isExpr() && "Unexpected operand type!");
1091 void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
1092 unsigned Scale, raw_ostream &O) {
1093 const MCOperand MO1 = MI->getOperand(OpNum + 1);
1094 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg());
1096 O << ", #" << (MO1.getImm() * Scale);
1098 assert(MO1.isExpr() && "Unexpected operand type!");
1099 O << ", " << *MO1.getExpr();
1104 void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
1105 const MCSubtargetInfo &STI,
1107 unsigned prfop = MI->getOperand(OpNum).getImm();
1109 StringRef Name = AArch64PRFM::PRFMMapper().toString(prfop, Valid);
1116 void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1117 const MCSubtargetInfo &STI,
1119 const MCOperand &MO = MI->getOperand(OpNum);
1121 MO.isFPImm() ? MO.getFPImm() : AArch64_AM::getFPImmFloat(MO.getImm());
1123 // 8 decimal places are enough to perfectly represent permitted floats.
1124 O << format("#%.8f", FPImm);
1127 static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
1131 llvm_unreachable("Vector register expected!");
1132 case AArch64::Q0: Reg = AArch64::Q1; break;
1133 case AArch64::Q1: Reg = AArch64::Q2; break;
1134 case AArch64::Q2: Reg = AArch64::Q3; break;
1135 case AArch64::Q3: Reg = AArch64::Q4; break;
1136 case AArch64::Q4: Reg = AArch64::Q5; break;
1137 case AArch64::Q5: Reg = AArch64::Q6; break;
1138 case AArch64::Q6: Reg = AArch64::Q7; break;
1139 case AArch64::Q7: Reg = AArch64::Q8; break;
1140 case AArch64::Q8: Reg = AArch64::Q9; break;
1141 case AArch64::Q9: Reg = AArch64::Q10; break;
1142 case AArch64::Q10: Reg = AArch64::Q11; break;
1143 case AArch64::Q11: Reg = AArch64::Q12; break;
1144 case AArch64::Q12: Reg = AArch64::Q13; break;
1145 case AArch64::Q13: Reg = AArch64::Q14; break;
1146 case AArch64::Q14: Reg = AArch64::Q15; break;
1147 case AArch64::Q15: Reg = AArch64::Q16; break;
1148 case AArch64::Q16: Reg = AArch64::Q17; break;
1149 case AArch64::Q17: Reg = AArch64::Q18; break;
1150 case AArch64::Q18: Reg = AArch64::Q19; break;
1151 case AArch64::Q19: Reg = AArch64::Q20; break;
1152 case AArch64::Q20: Reg = AArch64::Q21; break;
1153 case AArch64::Q21: Reg = AArch64::Q22; break;
1154 case AArch64::Q22: Reg = AArch64::Q23; break;
1155 case AArch64::Q23: Reg = AArch64::Q24; break;
1156 case AArch64::Q24: Reg = AArch64::Q25; break;
1157 case AArch64::Q25: Reg = AArch64::Q26; break;
1158 case AArch64::Q26: Reg = AArch64::Q27; break;
1159 case AArch64::Q27: Reg = AArch64::Q28; break;
1160 case AArch64::Q28: Reg = AArch64::Q29; break;
1161 case AArch64::Q29: Reg = AArch64::Q30; break;
1162 case AArch64::Q30: Reg = AArch64::Q31; break;
1163 // Vector lists can wrap around.
1172 void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
1173 const MCSubtargetInfo &STI,
1175 StringRef LayoutSuffix) {
1176 unsigned Reg = MI->getOperand(OpNum).getReg();
1180 // Work out how many registers there are in the list (if there is an actual
1182 unsigned NumRegs = 1;
1183 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
1184 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg))
1186 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
1187 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))
1189 else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||
1190 MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg))
1193 // Now forget about the list and find out what the first register is.
1194 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
1196 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
1199 // If it's a D-reg, we need to promote it to the equivalent Q-reg before
1200 // printing (otherwise getRegisterName fails).
1201 if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
1202 const MCRegisterClass &FPR128RC =
1203 MRI.getRegClass(AArch64::FPR128RegClassID);
1204 Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
1207 for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
1208 O << getRegisterName(Reg, AArch64::vreg) << LayoutSuffix;
1209 if (i + 1 != NumRegs)
1217 AArch64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI,
1219 const MCSubtargetInfo &STI,
1221 printVectorList(MI, OpNum, STI, O, "");
1224 template <unsigned NumLanes, char LaneKind>
1225 void AArch64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum,
1226 const MCSubtargetInfo &STI,
1228 std::string Suffix(".");
1230 Suffix += itostr(NumLanes) + LaneKind;
1234 printVectorList(MI, OpNum, STI, O, Suffix);
1237 void AArch64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1238 const MCSubtargetInfo &STI,
1240 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1243 void AArch64InstPrinter::printAlignedLabel(const MCInst *MI, unsigned OpNum,
1244 const MCSubtargetInfo &STI,
1246 const MCOperand &Op = MI->getOperand(OpNum);
1248 // If the label has already been resolved to an immediate offset (say, when
1249 // we're running the disassembler), just print the immediate.
1251 O << "#" << (Op.getImm() * 4);
1255 // If the branch target is simply an address then print it in hex.
1256 const MCConstantExpr *BranchTarget =
1257 dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr());
1259 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
1261 O.write_hex(Address);
1263 // Otherwise, just print the expression.
1264 O << *MI->getOperand(OpNum).getExpr();
1268 void AArch64InstPrinter::printAdrpLabel(const MCInst *MI, unsigned OpNum,
1269 const MCSubtargetInfo &STI,
1271 const MCOperand &Op = MI->getOperand(OpNum);
1273 // If the label has already been resolved to an immediate offset (say, when
1274 // we're running the disassembler), just print the immediate.
1276 O << "#" << (Op.getImm() * (1 << 12));
1280 // Otherwise, just print the expression.
1281 O << *MI->getOperand(OpNum).getExpr();
1284 void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
1285 const MCSubtargetInfo &STI,
1287 unsigned Val = MI->getOperand(OpNo).getImm();
1288 unsigned Opcode = MI->getOpcode();
1292 if (Opcode == AArch64::ISB)
1293 Name = AArch64ISB::ISBMapper().toString(Val, Valid);
1295 Name = AArch64DB::DBarrierMapper().toString(Val, Valid);
1302 void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
1303 const MCSubtargetInfo &STI,
1305 unsigned Val = MI->getOperand(OpNo).getImm();
1307 auto Mapper = AArch64SysReg::MRSMapper();
1308 std::string Name = Mapper.toString(Val, getAvailableFeatures());
1310 O << StringRef(Name).upper();
1313 void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
1314 const MCSubtargetInfo &STI,
1316 unsigned Val = MI->getOperand(OpNo).getImm();
1318 auto Mapper = AArch64SysReg::MSRMapper();
1319 std::string Name = Mapper.toString(Val, getAvailableFeatures());
1321 O << StringRef(Name).upper();
1324 void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
1325 const MCSubtargetInfo &STI,
1327 unsigned Val = MI->getOperand(OpNo).getImm();
1330 StringRef Name = AArch64PState::PStateMapper().toString(Val, Valid);
1332 O << StringRef(Name.str()).upper();
1337 void AArch64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo,
1338 const MCSubtargetInfo &STI,
1340 unsigned RawVal = MI->getOperand(OpNo).getImm();
1341 uint64_t Val = AArch64_AM::decodeAdvSIMDModImmType10(RawVal);
1342 O << format("#%#016llx", Val);