1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the functions necessary to decode AArch64 instruction
11 // bitpatterns into MCInsts (with the help of TableGenerated information from
12 // the instruction definitions).
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "arm-disassembler"
19 #include "AArch64RegisterInfo.h"
20 #include "AArch64Subtarget.h"
21 #include "Utils/AArch64BaseInfo.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstrDesc.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCContext.h"
26 #include "llvm/MC/MCDisassembler.h"
27 #include "llvm/MC/MCFixedLenDisassembler.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MemoryObject.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include "llvm/Support/raw_ostream.h"
36 typedef MCDisassembler::DecodeStatus DecodeStatus;
39 /// AArch64 disassembler for all AArch64 platforms.
40 class AArch64Disassembler : public MCDisassembler {
41 OwningPtr<const MCRegisterInfo> RegInfo;
43 /// Initializes the disassembler.
45 AArch64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info)
46 : MCDisassembler(STI), RegInfo(Info) {
49 ~AArch64Disassembler() {}
51 /// See MCDisassembler.
52 DecodeStatus getInstruction(MCInst &instr,
54 const MemoryObject ®ion,
57 raw_ostream &cStream) const;
59 const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
64 // Forward-declarations used in the auto-generated files.
65 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
66 uint64_t Address, const void *Decoder);
68 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
69 uint64_t Address, const void *Decoder);
71 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
72 uint64_t Address, const void *Decoder);
74 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
75 uint64_t Address, const void *Decoder);
77 static DecodeStatus DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
78 uint64_t Address, const void *Decoder);
79 static DecodeStatus DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
80 uint64_t Address, const void *Decoder);
81 static DecodeStatus DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
82 uint64_t Address, const void *Decoder);
83 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
84 uint64_t Address, const void *Decoder);
85 static DecodeStatus DecodeFPR64LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
86 uint64_t Address, const void *Decoder);
87 static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
88 unsigned RegNo, uint64_t Address,
90 static DecodeStatus DecodeFPR128LoRegisterClass(llvm::MCInst &Inst,
91 unsigned RegNo, uint64_t Address,
94 static DecodeStatus DecodeGPR64noxzrRegisterClass(llvm::MCInst &Inst,
99 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
101 const void *Decoder);
102 static DecodeStatus DecodeQPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
104 const void *Decoder);
105 static DecodeStatus DecodeDTripleRegisterClass(llvm::MCInst &Inst,
106 unsigned RegNo, uint64_t Address,
107 const void *Decoder);
108 static DecodeStatus DecodeQTripleRegisterClass(llvm::MCInst &Inst,
109 unsigned RegNo, uint64_t Address,
110 const void *Decoder);
111 static DecodeStatus DecodeDQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
113 const void *Decoder);
114 static DecodeStatus DecodeQQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
116 const void *Decoder);
118 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
121 const void *Decoder);
124 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
127 const void *Decoder);
129 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
132 const void *Decoder);
134 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
137 const void *Decoder);
139 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val,
140 uint64_t Address, const void *Decoder);
141 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val,
143 const void *Decoder);
144 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val,
146 const void *Decoder);
147 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val,
149 const void *Decoder);
151 static DecodeStatus DecodeShiftLeftImm8(MCInst &Inst, unsigned Val,
152 uint64_t Address, const void *Decoder);
153 static DecodeStatus DecodeShiftLeftImm16(MCInst &Inst, unsigned Val,
155 const void *Decoder);
156 static DecodeStatus DecodeShiftLeftImm32(MCInst &Inst, unsigned Val,
158 const void *Decoder);
159 static DecodeStatus DecodeShiftLeftImm64(MCInst &Inst, unsigned Val,
161 const void *Decoder);
163 template<int RegWidth>
164 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
167 const void *Decoder);
169 template<int RegWidth>
170 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
173 const void *Decoder);
175 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
176 unsigned ShiftAmount,
178 const void *Decoder);
179 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf>
181 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount,
182 uint64_t Address, const void *Decoder);
184 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
185 unsigned ShiftAmount,
187 const void *Decoder);
188 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
190 const void *Decoder);
192 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
194 const void *Decoder);
196 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
199 const void *Decoder);
201 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
204 const void *Decoder);
206 template<typename SomeNamedImmMapper>
207 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
210 const void *Decoder);
213 DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper,
214 llvm::MCInst &Inst, unsigned Val,
215 uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
220 const void *Decoder);
222 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
225 const void *Decoder);
228 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
231 const void *Decoder);
233 static DecodeStatus DecodeVLDSTPostInstruction(MCInst &Inst, unsigned Val,
235 const void *Decoder);
237 static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn,
239 const void *Decoder);
241 static bool Check(DecodeStatus &Out, DecodeStatus In);
243 #include "AArch64GenDisassemblerTables.inc"
244 #include "AArch64GenInstrInfo.inc"
246 static bool Check(DecodeStatus &Out, DecodeStatus In) {
248 case MCDisassembler::Success:
249 // Out stays the same.
251 case MCDisassembler::SoftFail:
254 case MCDisassembler::Fail:
258 llvm_unreachable("Invalid DecodeStatus!");
261 DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
262 const MemoryObject &Region,
265 raw_ostream &cs) const {
270 // We want to read exactly 4 bytes of data.
271 if (Region.readBytes(Address, 4, bytes) == -1) {
273 return MCDisassembler::Fail;
276 // Encoded as a small-endian 32-bit word in the stream.
277 uint32_t insn = (bytes[3] << 24) |
282 // Calling the auto-generated decoder function.
283 DecodeStatus result = decodeInstruction(DecoderTableA6432, MI, insn, Address,
285 if (result != MCDisassembler::Fail) {
292 return MCDisassembler::Fail;
295 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
296 const AArch64Disassembler *Dis = static_cast<const AArch64Disassembler*>(D);
297 return Dis->getRegInfo()->getRegClass(RC).getRegister(RegNo);
300 static DecodeStatus DecodeGPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
301 uint64_t Address, const void *Decoder) {
303 return MCDisassembler::Fail;
305 uint16_t Register = getReg(Decoder, AArch64::GPR64RegClassID, RegNo);
306 Inst.addOperand(MCOperand::CreateReg(Register));
307 return MCDisassembler::Success;
311 DecodeGPR64xspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
312 uint64_t Address, const void *Decoder) {
314 return MCDisassembler::Fail;
316 uint16_t Register = getReg(Decoder, AArch64::GPR64xspRegClassID, RegNo);
317 Inst.addOperand(MCOperand::CreateReg(Register));
318 return MCDisassembler::Success;
321 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
323 const void *Decoder) {
325 return MCDisassembler::Fail;
327 uint16_t Register = getReg(Decoder, AArch64::GPR32RegClassID, RegNo);
328 Inst.addOperand(MCOperand::CreateReg(Register));
329 return MCDisassembler::Success;
333 DecodeGPR32wspRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
334 uint64_t Address, const void *Decoder) {
336 return MCDisassembler::Fail;
338 uint16_t Register = getReg(Decoder, AArch64::GPR32wspRegClassID, RegNo);
339 Inst.addOperand(MCOperand::CreateReg(Register));
340 return MCDisassembler::Success;
344 DecodeFPR8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
345 uint64_t Address, const void *Decoder) {
347 return MCDisassembler::Fail;
349 uint16_t Register = getReg(Decoder, AArch64::FPR8RegClassID, RegNo);
350 Inst.addOperand(MCOperand::CreateReg(Register));
351 return MCDisassembler::Success;
355 DecodeFPR16RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
356 uint64_t Address, const void *Decoder) {
358 return MCDisassembler::Fail;
360 uint16_t Register = getReg(Decoder, AArch64::FPR16RegClassID, RegNo);
361 Inst.addOperand(MCOperand::CreateReg(Register));
362 return MCDisassembler::Success;
367 DecodeFPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
368 uint64_t Address, const void *Decoder) {
370 return MCDisassembler::Fail;
372 uint16_t Register = getReg(Decoder, AArch64::FPR32RegClassID, RegNo);
373 Inst.addOperand(MCOperand::CreateReg(Register));
374 return MCDisassembler::Success;
378 DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
379 uint64_t Address, const void *Decoder) {
381 return MCDisassembler::Fail;
383 uint16_t Register = getReg(Decoder, AArch64::FPR64RegClassID, RegNo);
384 Inst.addOperand(MCOperand::CreateReg(Register));
385 return MCDisassembler::Success;
389 DecodeFPR64LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
390 uint64_t Address, const void *Decoder) {
392 return MCDisassembler::Fail;
394 return DecodeFPR64RegisterClass(Inst, RegNo, Address, Decoder);
398 DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
399 uint64_t Address, const void *Decoder) {
401 return MCDisassembler::Fail;
403 uint16_t Register = getReg(Decoder, AArch64::FPR128RegClassID, RegNo);
404 Inst.addOperand(MCOperand::CreateReg(Register));
405 return MCDisassembler::Success;
409 DecodeFPR128LoRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
410 uint64_t Address, const void *Decoder) {
412 return MCDisassembler::Fail;
414 return DecodeFPR128RegisterClass(Inst, RegNo, Address, Decoder);
417 static DecodeStatus DecodeGPR64noxzrRegisterClass(llvm::MCInst &Inst,
420 const void *Decoder) {
422 return MCDisassembler::Fail;
424 uint16_t Register = getReg(Decoder, AArch64::GPR64noxzrRegClassID, RegNo);
425 Inst.addOperand(MCOperand::CreateReg(Register));
426 return MCDisassembler::Success;
429 static DecodeStatus DecodeRegisterClassByID(llvm::MCInst &Inst, unsigned RegNo,
431 const void *Decoder) {
433 return MCDisassembler::Fail;
435 uint16_t Register = getReg(Decoder, RegID, RegNo);
436 Inst.addOperand(MCOperand::CreateReg(Register));
437 return MCDisassembler::Success;
440 static DecodeStatus DecodeDPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
442 const void *Decoder) {
443 return DecodeRegisterClassByID(Inst, RegNo, AArch64::DPairRegClassID,
447 static DecodeStatus DecodeQPairRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
449 const void *Decoder) {
450 return DecodeRegisterClassByID(Inst, RegNo, AArch64::QPairRegClassID,
454 static DecodeStatus DecodeDTripleRegisterClass(llvm::MCInst &Inst,
455 unsigned RegNo, uint64_t Address,
456 const void *Decoder) {
457 return DecodeRegisterClassByID(Inst, RegNo, AArch64::DTripleRegClassID,
461 static DecodeStatus DecodeQTripleRegisterClass(llvm::MCInst &Inst,
462 unsigned RegNo, uint64_t Address,
463 const void *Decoder) {
464 return DecodeRegisterClassByID(Inst, RegNo, AArch64::QTripleRegClassID,
468 static DecodeStatus DecodeDQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
470 const void *Decoder) {
471 return DecodeRegisterClassByID(Inst, RegNo, AArch64::DQuadRegClassID,
475 static DecodeStatus DecodeQQuadRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
477 const void *Decoder) {
478 return DecodeRegisterClassByID(Inst, RegNo, AArch64::QQuadRegClassID,
482 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
485 const void *Decoder) {
486 // Option{1} must be 1. OptionHiS is made up of {Option{2}, Option{1},
487 // S}. Hence we want to check bit 1.
488 if (!(OptionHiS & 2))
489 return MCDisassembler::Fail;
491 Inst.addOperand(MCOperand::CreateImm(OptionHiS));
492 return MCDisassembler::Success;
495 static DecodeStatus DecodeBitfield32ImmOperand(llvm::MCInst &Inst,
498 const void *Decoder) {
499 // In the 32-bit variant, bit 6 must be zero. I.e. the immediate must be
502 return MCDisassembler::Fail;
504 Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
505 return MCDisassembler::Success;
508 static DecodeStatus DecodeCVT32FixedPosOperand(llvm::MCInst &Inst,
511 const void *Decoder) {
512 // 1 <= Imm <= 32. Encoded as 64 - Imm so: 63 >= Encoded >= 32.
514 return MCDisassembler::Fail;
516 Inst.addOperand(MCOperand::CreateImm(Imm6Bits));
517 return MCDisassembler::Success;
520 static DecodeStatus DecodeFPZeroOperand(llvm::MCInst &Inst,
523 const void *Decoder) {
524 // Any bits are valid in the instruction (they're architecturally ignored),
525 // but a code generator should insert 0.
526 Inst.addOperand(MCOperand::CreateImm(0));
527 return MCDisassembler::Success;
530 static DecodeStatus DecodeShiftRightImm8(MCInst &Inst, unsigned Val,
532 const void *Decoder) {
533 Inst.addOperand(MCOperand::CreateImm(8 - Val));
534 return MCDisassembler::Success;
537 static DecodeStatus DecodeShiftRightImm16(MCInst &Inst, unsigned Val,
539 const void *Decoder) {
540 Inst.addOperand(MCOperand::CreateImm(16 - Val));
541 return MCDisassembler::Success;
544 static DecodeStatus DecodeShiftRightImm32(MCInst &Inst, unsigned Val,
546 const void *Decoder) {
547 Inst.addOperand(MCOperand::CreateImm(32 - Val));
548 return MCDisassembler::Success;
551 static DecodeStatus DecodeShiftRightImm64(MCInst &Inst, unsigned Val,
553 const void *Decoder) {
554 Inst.addOperand(MCOperand::CreateImm(64 - Val));
555 return MCDisassembler::Success;
558 static DecodeStatus DecodeShiftLeftImm8(MCInst &Inst, unsigned Val,
560 const void *Decoder) {
562 return MCDisassembler::Fail;
564 Inst.addOperand(MCOperand::CreateImm(Val));
565 return MCDisassembler::Success;
568 static DecodeStatus DecodeShiftLeftImm16(MCInst &Inst, unsigned Val,
570 const void *Decoder) {
572 return MCDisassembler::Fail;
574 Inst.addOperand(MCOperand::CreateImm(Val));
575 return MCDisassembler::Success;
578 static DecodeStatus DecodeShiftLeftImm32(MCInst &Inst, unsigned Val,
580 const void *Decoder) {
582 return MCDisassembler::Fail;
584 Inst.addOperand(MCOperand::CreateImm(Val));
585 return MCDisassembler::Success;
588 static DecodeStatus DecodeShiftLeftImm64(MCInst &Inst, unsigned Val,
590 const void *Decoder) {
592 return MCDisassembler::Fail;
594 Inst.addOperand(MCOperand::CreateImm(Val));
595 return MCDisassembler::Success;
598 template<int RegWidth>
599 static DecodeStatus DecodeMoveWideImmOperand(llvm::MCInst &Inst,
602 const void *Decoder) {
603 unsigned Imm16 = FullImm & 0xffff;
604 unsigned Shift = FullImm >> 16;
606 if (RegWidth == 32 && Shift > 1) return MCDisassembler::Fail;
608 Inst.addOperand(MCOperand::CreateImm(Imm16));
609 Inst.addOperand(MCOperand::CreateImm(Shift));
610 return MCDisassembler::Success;
613 template<int RegWidth>
614 static DecodeStatus DecodeLogicalImmOperand(llvm::MCInst &Inst,
617 const void *Decoder) {
619 if (!A64Imms::isLogicalImmBits(RegWidth, Bits, Imm))
620 return MCDisassembler::Fail;
622 Inst.addOperand(MCOperand::CreateImm(Bits));
623 return MCDisassembler::Success;
627 static DecodeStatus DecodeRegExtendOperand(llvm::MCInst &Inst,
628 unsigned ShiftAmount,
630 const void *Decoder) {
631 // Only values 0-4 are valid for this 3-bit field
633 return MCDisassembler::Fail;
635 Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
636 return MCDisassembler::Success;
639 static DecodeStatus Decode32BitShiftOperand(llvm::MCInst &Inst,
640 unsigned ShiftAmount,
642 const void *Decoder) {
643 // Only values below 32 are valid for a 32-bit register
644 if (ShiftAmount > 31)
645 return MCDisassembler::Fail;
647 Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
648 return MCDisassembler::Success;
651 static DecodeStatus DecodeBitfieldInstruction(llvm::MCInst &Inst, unsigned Insn,
653 const void *Decoder) {
654 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
655 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
656 unsigned ImmS = fieldFromInstruction(Insn, 10, 6);
657 unsigned ImmR = fieldFromInstruction(Insn, 16, 6);
658 unsigned SF = fieldFromInstruction(Insn, 31, 1);
660 // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise
661 // out assertions that it thinks should never be hit.
662 enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc;
663 Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2);
666 // ImmR and ImmS must be between 0 and 31 for 32-bit instructions.
667 if (ImmR > 31 || ImmS > 31)
668 return MCDisassembler::Fail;
672 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
673 // BFM MCInsts use Rd as a source too.
674 if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
675 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
677 DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
678 // BFM MCInsts use Rd as a source too.
679 if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder);
680 DecodeGPR32RegisterClass(Inst, Rn, Address, Decoder);
683 // ASR and LSR have more specific patterns so they won't get here:
684 assert(!(ImmS == 31 && !SF && Opc != BFM)
685 && "shift should have used auto decode");
686 assert(!(ImmS == 63 && SF && Opc != BFM)
687 && "shift should have used auto decode");
689 // Extension instructions similarly:
690 if (Opc == SBFM && ImmR == 0) {
691 assert((ImmS != 7 && ImmS != 15) && "extension got here");
692 assert((ImmS != 31 || SF == 0) && "extension got here");
693 } else if (Opc == UBFM && ImmR == 0) {
694 assert((SF != 0 || (ImmS != 7 && ImmS != 15)) && "extension got here");
698 // It might be a LSL instruction, which actually takes the shift amount
699 // itself as an MCInst operand.
700 if (SF && (ImmS + 1) % 64 == ImmR) {
701 Inst.setOpcode(AArch64::LSLxxi);
702 Inst.addOperand(MCOperand::CreateImm(63 - ImmS));
703 return MCDisassembler::Success;
704 } else if (!SF && (ImmS + 1) % 32 == ImmR) {
705 Inst.setOpcode(AArch64::LSLwwi);
706 Inst.addOperand(MCOperand::CreateImm(31 - ImmS));
707 return MCDisassembler::Success;
711 // Otherwise it's definitely either an extract or an insert depending on which
712 // of ImmR or ImmS is larger.
713 unsigned ExtractOp, InsertOp;
715 default: llvm_unreachable("unexpected instruction trying to decode bitfield");
717 ExtractOp = SF ? AArch64::SBFXxxii : AArch64::SBFXwwii;
718 InsertOp = SF ? AArch64::SBFIZxxii : AArch64::SBFIZwwii;
721 ExtractOp = SF ? AArch64::BFXILxxii : AArch64::BFXILwwii;
722 InsertOp = SF ? AArch64::BFIxxii : AArch64::BFIwwii;
725 ExtractOp = SF ? AArch64::UBFXxxii : AArch64::UBFXwwii;
726 InsertOp = SF ? AArch64::UBFIZxxii : AArch64::UBFIZwwii;
730 // Otherwise it's a boring insert or extract
731 Inst.addOperand(MCOperand::CreateImm(ImmR));
732 Inst.addOperand(MCOperand::CreateImm(ImmS));
736 Inst.setOpcode(InsertOp);
738 Inst.setOpcode(ExtractOp);
740 return MCDisassembler::Success;
743 static DecodeStatus DecodeFMOVLaneInstruction(llvm::MCInst &Inst, unsigned Insn,
745 const void *Decoder) {
746 // This decoder exists to add the dummy Lane operand to the MCInst, which must
747 // be 1 in assembly but has no other real manifestation.
748 unsigned Rd = fieldFromInstruction(Insn, 0, 5);
749 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
750 unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
753 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
754 DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
756 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
757 DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
761 Inst.addOperand(MCOperand::CreateImm(1));
763 return MCDisassembler::Success;
767 static DecodeStatus DecodeLDSTPairInstruction(llvm::MCInst &Inst,
770 const void *Decoder) {
771 DecodeStatus Result = MCDisassembler::Success;
772 unsigned Rt = fieldFromInstruction(Insn, 0, 5);
773 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
774 unsigned Rt2 = fieldFromInstruction(Insn, 10, 5);
775 unsigned SImm7 = fieldFromInstruction(Insn, 15, 7);
776 unsigned L = fieldFromInstruction(Insn, 22, 1);
777 unsigned V = fieldFromInstruction(Insn, 26, 1);
778 unsigned Opc = fieldFromInstruction(Insn, 30, 2);
780 // Not an official name, but it turns out that bit 23 distinguishes indexed
781 // from non-indexed operations.
782 unsigned Indexed = fieldFromInstruction(Insn, 23, 1);
784 if (Indexed && L == 0) {
785 // The MCInst for an indexed store has an out operand and 4 ins:
786 // Rn_wb, Rt, Rt2, Rn, Imm
787 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
790 // You shouldn't load to the same register twice in an instruction...
792 Result = MCDisassembler::SoftFail;
794 // ... or do any operation that writes-back to a transfer register. But note
795 // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
796 if (Indexed && V == 0 && Rn != 31 && (Rt == Rn || Rt2 == Rn))
797 Result = MCDisassembler::SoftFail;
799 // Exactly how we decode the MCInst's registers depends on the Opc and V
800 // fields of the instruction. These also obviously determine the size of the
801 // operation so we can fill in that information while we're at it.
803 // The instruction operates on the FP/SIMD registers
805 default: return MCDisassembler::Fail;
807 DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
808 DecodeFPR32RegisterClass(Inst, Rt2, Address, Decoder);
811 DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
812 DecodeFPR64RegisterClass(Inst, Rt2, Address, Decoder);
815 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
816 DecodeFPR128RegisterClass(Inst, Rt2, Address, Decoder);
821 default: return MCDisassembler::Fail;
823 DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
824 DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder);
827 assert(L && "unexpected \"store signed\" attempt");
828 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
829 DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
832 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
833 DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder);
838 if (Indexed && L == 1) {
839 // The MCInst for an indexed load has 3 out operands and an 3 ins:
840 // Rt, Rt2, Rn_wb, Rt2, Rn, Imm
841 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
845 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
846 Inst.addOperand(MCOperand::CreateImm(SImm7));
851 static DecodeStatus DecodeLoadPairExclusiveInstruction(llvm::MCInst &Inst,
854 const void *Decoder) {
855 unsigned Rt = fieldFromInstruction(Val, 0, 5);
856 unsigned Rn = fieldFromInstruction(Val, 5, 5);
857 unsigned Rt2 = fieldFromInstruction(Val, 10, 5);
858 unsigned MemSize = fieldFromInstruction(Val, 30, 2);
860 DecodeStatus S = MCDisassembler::Success;
861 if (Rt == Rt2) S = MCDisassembler::SoftFail;
865 if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder)))
866 return MCDisassembler::Fail;
867 if (!Check(S, DecodeGPR32RegisterClass(Inst, Rt2, Address, Decoder)))
868 return MCDisassembler::Fail;
871 if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder)))
872 return MCDisassembler::Fail;
873 if (!Check(S, DecodeGPR64RegisterClass(Inst, Rt2, Address, Decoder)))
874 return MCDisassembler::Fail;
877 llvm_unreachable("Invalid MemSize in DecodeLoadPairExclusiveInstruction");
880 if (!Check(S, DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder)))
881 return MCDisassembler::Fail;
886 template<typename SomeNamedImmMapper>
887 static DecodeStatus DecodeNamedImmOperand(llvm::MCInst &Inst,
890 const void *Decoder) {
891 SomeNamedImmMapper Mapper;
893 Mapper.toString(Val, ValidNamed);
894 if (ValidNamed || Mapper.validImm(Val)) {
895 Inst.addOperand(MCOperand::CreateImm(Val));
896 return MCDisassembler::Success;
899 return MCDisassembler::Fail;
902 static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &Mapper,
906 const void *Decoder) {
908 Mapper.toString(Val, ValidNamed);
910 Inst.addOperand(MCOperand::CreateImm(Val));
912 return ValidNamed ? MCDisassembler::Success : MCDisassembler::Fail;
915 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
918 const void *Decoder) {
919 return DecodeSysRegOperand(A64SysReg::MRSMapper(), Inst, Val, Address,
923 static DecodeStatus DecodeMSROperand(llvm::MCInst &Inst,
926 const void *Decoder) {
927 return DecodeSysRegOperand(A64SysReg::MSRMapper(), Inst, Val, Address,
931 static DecodeStatus DecodeSingleIndexedInstruction(llvm::MCInst &Inst,
934 const void *Decoder) {
935 unsigned Rt = fieldFromInstruction(Insn, 0, 5);
936 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
937 unsigned Imm9 = fieldFromInstruction(Insn, 12, 9);
939 unsigned Opc = fieldFromInstruction(Insn, 22, 2);
940 unsigned V = fieldFromInstruction(Insn, 26, 1);
941 unsigned Size = fieldFromInstruction(Insn, 30, 2);
943 if (Opc == 0 || (V == 1 && Opc == 2)) {
944 // It's a store, the MCInst gets: Rn_wb, Rt, Rn, Imm
945 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
948 if (V == 0 && (Opc == 2 || Size == 3)) {
949 DecodeGPR64RegisterClass(Inst, Rt, Address, Decoder);
951 DecodeGPR32RegisterClass(Inst, Rt, Address, Decoder);
952 } else if (V == 1 && (Opc & 2)) {
953 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
957 DecodeFPR8RegisterClass(Inst, Rt, Address, Decoder);
960 DecodeFPR16RegisterClass(Inst, Rt, Address, Decoder);
963 DecodeFPR32RegisterClass(Inst, Rt, Address, Decoder);
966 DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
971 if (Opc != 0 && (V != 1 || Opc != 2)) {
972 // It's a load, the MCInst gets: Rt, Rn_wb, Rn, Imm
973 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
976 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
978 Inst.addOperand(MCOperand::CreateImm(Imm9));
980 // N.b. The official documentation says undpredictable if Rt == Rn, but this
981 // takes place at the architectural rather than encoding level:
983 // "STR xzr, [sp], #4" is perfectly valid.
984 if (V == 0 && Rt == Rn && Rn != 31)
985 return MCDisassembler::SoftFail;
987 return MCDisassembler::Success;
990 static MCDisassembler *createAArch64Disassembler(const Target &T,
991 const MCSubtargetInfo &STI) {
992 return new AArch64Disassembler(STI, T.createMCRegInfo(""));
995 extern "C" void LLVMInitializeAArch64Disassembler() {
996 TargetRegistry::RegisterMCDisassembler(TheAArch64Target,
997 createAArch64Disassembler);
1000 template <A64SE::ShiftExtSpecifiers Ext, bool IsHalf>
1002 DecodeNeonMovImmShiftOperand(llvm::MCInst &Inst, unsigned ShiftAmount,
1003 uint64_t Address, const void *Decoder) {
1005 if (Ext == A64SE::LSL)
1007 else if (Ext != A64SE::MSL)
1008 return MCDisassembler::Fail;
1010 // MSL and LSLH accepts encoded shift amount 0 or 1.
1011 if ((!IsLSL || (IsLSL && IsHalf)) && ShiftAmount != 0 && ShiftAmount != 1)
1012 return MCDisassembler::Fail;
1014 // LSL accepts encoded shift amount 0, 1, 2 or 3.
1015 if (IsLSL && ShiftAmount > 3)
1016 return MCDisassembler::Fail;
1018 Inst.addOperand(MCOperand::CreateImm(ShiftAmount));
1019 return MCDisassembler::Success;
1022 // Decode post-index vector load/store instructions.
1023 // This is necessary as we need to decode Rm: if Rm == 0b11111, the last
1024 // operand is an immediate equal the the length of vector list in bytes,
1025 // or Rm is decoded to a GPR64noxzr register.
1026 static DecodeStatus DecodeVLDSTPostInstruction(MCInst &Inst, unsigned Insn,
1028 const void *Decoder) {
1029 unsigned Rt = fieldFromInstruction(Insn, 0, 5);
1030 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
1031 unsigned Rm = fieldFromInstruction(Insn, 16, 5);
1032 unsigned Opcode = fieldFromInstruction(Insn, 12, 4);
1033 unsigned IsLoad = fieldFromInstruction(Insn, 22, 1);
1034 // 0 for 64bit vector list, 1 for 128bit vector list
1035 unsigned Is128BitVec = fieldFromInstruction(Insn, 30, 1);
1040 case 2: // ld1/st1 with 4 vectors
1043 case 6: // ld1/st1 with 3 vectors
1045 case 7: // ld1/st1 with 1 vector
1048 case 10: // ld1/st1 with 2 vectors
1051 llvm_unreachable("Invalid opcode for post-index load/store instructions");
1054 // Decode vector list of 1/2/3/4 vectors for load instructions.
1058 Is128BitVec ? DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder)
1059 : DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
1062 Is128BitVec ? DecodeQPairRegisterClass(Inst, Rt, Address, Decoder)
1063 : DecodeDPairRegisterClass(Inst, Rt, Address, Decoder);
1066 Is128BitVec ? DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder)
1067 : DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder);
1070 Is128BitVec ? DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder)
1071 : DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder);
1076 // Decode write back register, which is equal to Rn.
1077 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
1078 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
1080 if (Rm == 31) // If Rm is 0x11111, add the vector list length in byte
1081 Inst.addOperand(MCOperand::CreateImm(NumVecs * (Is128BitVec ? 16 : 8)));
1083 DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder);
1085 // Decode vector list of 1/2/3/4 vectors for load instructions.
1089 Is128BitVec ? DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder)
1090 : DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
1093 Is128BitVec ? DecodeQPairRegisterClass(Inst, Rt, Address, Decoder)
1094 : DecodeDPairRegisterClass(Inst, Rt, Address, Decoder);
1097 Is128BitVec ? DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder)
1098 : DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder);
1101 Is128BitVec ? DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder)
1102 : DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder);
1107 return MCDisassembler::Success;
1110 // Decode post-index vector load/store lane instructions.
1111 // This is necessary as we need to decode Rm: if Rm == 0b11111, the last
1112 // operand is an immediate equal the the length of the changed bytes,
1113 // or Rm is decoded to a GPR64noxzr register.
1114 static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst &Inst, unsigned Insn,
1116 const void *Decoder) {
1117 bool Is64bitVec = false;
1118 bool IsLoadDup = false;
1119 bool IsLoad = false;
1120 // The total number of bytes transferred.
1121 // TransferBytes = NumVecs * OneLaneBytes
1122 unsigned TransferBytes = 0;
1123 unsigned NumVecs = 0;
1124 unsigned Opc = Inst.getOpcode();
1126 case AArch64::LD1R_WB_8B_fixed: case AArch64::LD1R_WB_8B_register:
1127 case AArch64::LD1R_WB_4H_fixed: case AArch64::LD1R_WB_4H_register:
1128 case AArch64::LD1R_WB_2S_fixed: case AArch64::LD1R_WB_2S_register:
1129 case AArch64::LD1R_WB_1D_fixed: case AArch64::LD1R_WB_1D_register: {
1131 case AArch64::LD1R_WB_8B_fixed: case AArch64::LD1R_WB_8B_register:
1132 TransferBytes = 1; break;
1133 case AArch64::LD1R_WB_4H_fixed: case AArch64::LD1R_WB_4H_register:
1134 TransferBytes = 2; break;
1135 case AArch64::LD1R_WB_2S_fixed: case AArch64::LD1R_WB_2S_register:
1136 TransferBytes = 4; break;
1137 case AArch64::LD1R_WB_1D_fixed: case AArch64::LD1R_WB_1D_register:
1138 TransferBytes = 8; break;
1146 case AArch64::LD1R_WB_16B_fixed: case AArch64::LD1R_WB_16B_register:
1147 case AArch64::LD1R_WB_8H_fixed: case AArch64::LD1R_WB_8H_register:
1148 case AArch64::LD1R_WB_4S_fixed: case AArch64::LD1R_WB_4S_register:
1149 case AArch64::LD1R_WB_2D_fixed: case AArch64::LD1R_WB_2D_register: {
1151 case AArch64::LD1R_WB_16B_fixed: case AArch64::LD1R_WB_16B_register:
1152 TransferBytes = 1; break;
1153 case AArch64::LD1R_WB_8H_fixed: case AArch64::LD1R_WB_8H_register:
1154 TransferBytes = 2; break;
1155 case AArch64::LD1R_WB_4S_fixed: case AArch64::LD1R_WB_4S_register:
1156 TransferBytes = 4; break;
1157 case AArch64::LD1R_WB_2D_fixed: case AArch64::LD1R_WB_2D_register:
1158 TransferBytes = 8; break;
1165 case AArch64::LD2R_WB_8B_fixed: case AArch64::LD2R_WB_8B_register:
1166 case AArch64::LD2R_WB_4H_fixed: case AArch64::LD2R_WB_4H_register:
1167 case AArch64::LD2R_WB_2S_fixed: case AArch64::LD2R_WB_2S_register:
1168 case AArch64::LD2R_WB_1D_fixed: case AArch64::LD2R_WB_1D_register: {
1170 case AArch64::LD2R_WB_8B_fixed: case AArch64::LD2R_WB_8B_register:
1171 TransferBytes = 2; break;
1172 case AArch64::LD2R_WB_4H_fixed: case AArch64::LD2R_WB_4H_register:
1173 TransferBytes = 4; break;
1174 case AArch64::LD2R_WB_2S_fixed: case AArch64::LD2R_WB_2S_register:
1175 TransferBytes = 8; break;
1176 case AArch64::LD2R_WB_1D_fixed: case AArch64::LD2R_WB_1D_register:
1177 TransferBytes = 16; break;
1185 case AArch64::LD2R_WB_16B_fixed: case AArch64::LD2R_WB_16B_register:
1186 case AArch64::LD2R_WB_8H_fixed: case AArch64::LD2R_WB_8H_register:
1187 case AArch64::LD2R_WB_4S_fixed: case AArch64::LD2R_WB_4S_register:
1188 case AArch64::LD2R_WB_2D_fixed: case AArch64::LD2R_WB_2D_register: {
1190 case AArch64::LD2R_WB_16B_fixed: case AArch64::LD2R_WB_16B_register:
1191 TransferBytes = 2; break;
1192 case AArch64::LD2R_WB_8H_fixed: case AArch64::LD2R_WB_8H_register:
1193 TransferBytes = 4; break;
1194 case AArch64::LD2R_WB_4S_fixed: case AArch64::LD2R_WB_4S_register:
1195 TransferBytes = 8; break;
1196 case AArch64::LD2R_WB_2D_fixed: case AArch64::LD2R_WB_2D_register:
1197 TransferBytes = 16; break;
1204 case AArch64::LD3R_WB_8B_fixed: case AArch64::LD3R_WB_8B_register:
1205 case AArch64::LD3R_WB_4H_fixed: case AArch64::LD3R_WB_4H_register:
1206 case AArch64::LD3R_WB_2S_fixed: case AArch64::LD3R_WB_2S_register:
1207 case AArch64::LD3R_WB_1D_fixed: case AArch64::LD3R_WB_1D_register: {
1209 case AArch64::LD3R_WB_8B_fixed: case AArch64::LD3R_WB_8B_register:
1210 TransferBytes = 3; break;
1211 case AArch64::LD3R_WB_4H_fixed: case AArch64::LD3R_WB_4H_register:
1212 TransferBytes = 6; break;
1213 case AArch64::LD3R_WB_2S_fixed: case AArch64::LD3R_WB_2S_register:
1214 TransferBytes = 12; break;
1215 case AArch64::LD3R_WB_1D_fixed: case AArch64::LD3R_WB_1D_register:
1216 TransferBytes = 24; break;
1224 case AArch64::LD3R_WB_16B_fixed: case AArch64::LD3R_WB_16B_register:
1225 case AArch64::LD3R_WB_4S_fixed: case AArch64::LD3R_WB_8H_register:
1226 case AArch64::LD3R_WB_8H_fixed: case AArch64::LD3R_WB_4S_register:
1227 case AArch64::LD3R_WB_2D_fixed: case AArch64::LD3R_WB_2D_register: {
1229 case AArch64::LD3R_WB_16B_fixed: case AArch64::LD3R_WB_16B_register:
1230 TransferBytes = 3; break;
1231 case AArch64::LD3R_WB_8H_fixed: case AArch64::LD3R_WB_8H_register:
1232 TransferBytes = 6; break;
1233 case AArch64::LD3R_WB_4S_fixed: case AArch64::LD3R_WB_4S_register:
1234 TransferBytes = 12; break;
1235 case AArch64::LD3R_WB_2D_fixed: case AArch64::LD3R_WB_2D_register:
1236 TransferBytes = 24; break;
1243 case AArch64::LD4R_WB_8B_fixed: case AArch64::LD4R_WB_8B_register:
1244 case AArch64::LD4R_WB_4H_fixed: case AArch64::LD4R_WB_4H_register:
1245 case AArch64::LD4R_WB_2S_fixed: case AArch64::LD4R_WB_2S_register:
1246 case AArch64::LD4R_WB_1D_fixed: case AArch64::LD4R_WB_1D_register: {
1248 case AArch64::LD4R_WB_8B_fixed: case AArch64::LD4R_WB_8B_register:
1249 TransferBytes = 4; break;
1250 case AArch64::LD4R_WB_4H_fixed: case AArch64::LD4R_WB_4H_register:
1251 TransferBytes = 8; break;
1252 case AArch64::LD4R_WB_2S_fixed: case AArch64::LD4R_WB_2S_register:
1253 TransferBytes = 16; break;
1254 case AArch64::LD4R_WB_1D_fixed: case AArch64::LD4R_WB_1D_register:
1255 TransferBytes = 32; break;
1263 case AArch64::LD4R_WB_16B_fixed: case AArch64::LD4R_WB_16B_register:
1264 case AArch64::LD4R_WB_4S_fixed: case AArch64::LD4R_WB_8H_register:
1265 case AArch64::LD4R_WB_8H_fixed: case AArch64::LD4R_WB_4S_register:
1266 case AArch64::LD4R_WB_2D_fixed: case AArch64::LD4R_WB_2D_register: {
1268 case AArch64::LD4R_WB_16B_fixed: case AArch64::LD4R_WB_16B_register:
1269 TransferBytes = 4; break;
1270 case AArch64::LD4R_WB_8H_fixed: case AArch64::LD4R_WB_8H_register:
1271 TransferBytes = 8; break;
1272 case AArch64::LD4R_WB_4S_fixed: case AArch64::LD4R_WB_4S_register:
1273 TransferBytes = 16; break;
1274 case AArch64::LD4R_WB_2D_fixed: case AArch64::LD4R_WB_2D_register:
1275 TransferBytes = 32; break;
1282 case AArch64::LD1LN_WB_B_fixed: case AArch64::LD1LN_WB_B_register:
1283 case AArch64::LD1LN_WB_H_fixed: case AArch64::LD1LN_WB_H_register:
1284 case AArch64::LD1LN_WB_S_fixed: case AArch64::LD1LN_WB_S_register:
1285 case AArch64::LD1LN_WB_D_fixed: case AArch64::LD1LN_WB_D_register: {
1287 case AArch64::LD1LN_WB_B_fixed: case AArch64::LD1LN_WB_B_register:
1288 TransferBytes = 1; break;
1289 case AArch64::LD1LN_WB_H_fixed: case AArch64::LD1LN_WB_H_register:
1290 TransferBytes = 2; break;
1291 case AArch64::LD1LN_WB_S_fixed: case AArch64::LD1LN_WB_S_register:
1292 TransferBytes = 4; break;
1293 case AArch64::LD1LN_WB_D_fixed: case AArch64::LD1LN_WB_D_register:
1294 TransferBytes = 8; break;
1301 case AArch64::LD2LN_WB_B_fixed: case AArch64::LD2LN_WB_B_register:
1302 case AArch64::LD2LN_WB_H_fixed: case AArch64::LD2LN_WB_H_register:
1303 case AArch64::LD2LN_WB_S_fixed: case AArch64::LD2LN_WB_S_register:
1304 case AArch64::LD2LN_WB_D_fixed: case AArch64::LD2LN_WB_D_register: {
1306 case AArch64::LD2LN_WB_B_fixed: case AArch64::LD2LN_WB_B_register:
1307 TransferBytes = 2; break;
1308 case AArch64::LD2LN_WB_H_fixed: case AArch64::LD2LN_WB_H_register:
1309 TransferBytes = 4; break;
1310 case AArch64::LD2LN_WB_S_fixed: case AArch64::LD2LN_WB_S_register:
1311 TransferBytes = 8; break;
1312 case AArch64::LD2LN_WB_D_fixed: case AArch64::LD2LN_WB_D_register:
1313 TransferBytes = 16; break;
1320 case AArch64::LD3LN_WB_B_fixed: case AArch64::LD3LN_WB_B_register:
1321 case AArch64::LD3LN_WB_H_fixed: case AArch64::LD3LN_WB_H_register:
1322 case AArch64::LD3LN_WB_S_fixed: case AArch64::LD3LN_WB_S_register:
1323 case AArch64::LD3LN_WB_D_fixed: case AArch64::LD3LN_WB_D_register: {
1325 case AArch64::LD3LN_WB_B_fixed: case AArch64::LD3LN_WB_B_register:
1326 TransferBytes = 3; break;
1327 case AArch64::LD3LN_WB_H_fixed: case AArch64::LD3LN_WB_H_register:
1328 TransferBytes = 6; break;
1329 case AArch64::LD3LN_WB_S_fixed: case AArch64::LD3LN_WB_S_register:
1330 TransferBytes = 12; break;
1331 case AArch64::LD3LN_WB_D_fixed: case AArch64::LD3LN_WB_D_register:
1332 TransferBytes = 24; break;
1339 case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register:
1340 case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register:
1341 case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register:
1342 case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register: {
1344 case AArch64::LD4LN_WB_B_fixed: case AArch64::LD4LN_WB_B_register:
1345 TransferBytes = 4; break;
1346 case AArch64::LD4LN_WB_H_fixed: case AArch64::LD4LN_WB_H_register:
1347 TransferBytes = 8; break;
1348 case AArch64::LD4LN_WB_S_fixed: case AArch64::LD4LN_WB_S_register:
1349 TransferBytes = 16; break;
1350 case AArch64::LD4LN_WB_D_fixed: case AArch64::LD4LN_WB_D_register:
1351 TransferBytes = 32; break;
1358 case AArch64::ST1LN_WB_B_fixed: case AArch64::ST1LN_WB_B_register:
1359 case AArch64::ST1LN_WB_H_fixed: case AArch64::ST1LN_WB_H_register:
1360 case AArch64::ST1LN_WB_S_fixed: case AArch64::ST1LN_WB_S_register:
1361 case AArch64::ST1LN_WB_D_fixed: case AArch64::ST1LN_WB_D_register: {
1363 case AArch64::ST1LN_WB_B_fixed: case AArch64::ST1LN_WB_B_register:
1364 TransferBytes = 1; break;
1365 case AArch64::ST1LN_WB_H_fixed: case AArch64::ST1LN_WB_H_register:
1366 TransferBytes = 2; break;
1367 case AArch64::ST1LN_WB_S_fixed: case AArch64::ST1LN_WB_S_register:
1368 TransferBytes = 4; break;
1369 case AArch64::ST1LN_WB_D_fixed: case AArch64::ST1LN_WB_D_register:
1370 TransferBytes = 8; break;
1376 case AArch64::ST2LN_WB_B_fixed: case AArch64::ST2LN_WB_B_register:
1377 case AArch64::ST2LN_WB_H_fixed: case AArch64::ST2LN_WB_H_register:
1378 case AArch64::ST2LN_WB_S_fixed: case AArch64::ST2LN_WB_S_register:
1379 case AArch64::ST2LN_WB_D_fixed: case AArch64::ST2LN_WB_D_register: {
1381 case AArch64::ST2LN_WB_B_fixed: case AArch64::ST2LN_WB_B_register:
1382 TransferBytes = 2; break;
1383 case AArch64::ST2LN_WB_H_fixed: case AArch64::ST2LN_WB_H_register:
1384 TransferBytes = 4; break;
1385 case AArch64::ST2LN_WB_S_fixed: case AArch64::ST2LN_WB_S_register:
1386 TransferBytes = 8; break;
1387 case AArch64::ST2LN_WB_D_fixed: case AArch64::ST2LN_WB_D_register:
1388 TransferBytes = 16; break;
1394 case AArch64::ST3LN_WB_B_fixed: case AArch64::ST3LN_WB_B_register:
1395 case AArch64::ST3LN_WB_H_fixed: case AArch64::ST3LN_WB_H_register:
1396 case AArch64::ST3LN_WB_S_fixed: case AArch64::ST3LN_WB_S_register:
1397 case AArch64::ST3LN_WB_D_fixed: case AArch64::ST3LN_WB_D_register: {
1399 case AArch64::ST3LN_WB_B_fixed: case AArch64::ST3LN_WB_B_register:
1400 TransferBytes = 3; break;
1401 case AArch64::ST3LN_WB_H_fixed: case AArch64::ST3LN_WB_H_register:
1402 TransferBytes = 6; break;
1403 case AArch64::ST3LN_WB_S_fixed: case AArch64::ST3LN_WB_S_register:
1404 TransferBytes = 12; break;
1405 case AArch64::ST3LN_WB_D_fixed: case AArch64::ST3LN_WB_D_register:
1406 TransferBytes = 24; break;
1412 case AArch64::ST4LN_WB_B_fixed: case AArch64::ST4LN_WB_B_register:
1413 case AArch64::ST4LN_WB_H_fixed: case AArch64::ST4LN_WB_H_register:
1414 case AArch64::ST4LN_WB_S_fixed: case AArch64::ST4LN_WB_S_register:
1415 case AArch64::ST4LN_WB_D_fixed: case AArch64::ST4LN_WB_D_register: {
1417 case AArch64::ST4LN_WB_B_fixed: case AArch64::ST4LN_WB_B_register:
1418 TransferBytes = 4; break;
1419 case AArch64::ST4LN_WB_H_fixed: case AArch64::ST4LN_WB_H_register:
1420 TransferBytes = 8; break;
1421 case AArch64::ST4LN_WB_S_fixed: case AArch64::ST4LN_WB_S_register:
1422 TransferBytes = 16; break;
1423 case AArch64::ST4LN_WB_D_fixed: case AArch64::ST4LN_WB_D_register:
1424 TransferBytes = 32; break;
1431 return MCDisassembler::Fail;
1432 } // End of switch (Opc)
1434 unsigned Rt = fieldFromInstruction(Insn, 0, 5);
1435 unsigned Rn = fieldFromInstruction(Insn, 5, 5);
1436 unsigned Rm = fieldFromInstruction(Insn, 16, 5);
1438 // Decode post-index of load duplicate lane
1442 Is64bitVec ? DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder)
1443 : DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
1446 Is64bitVec ? DecodeDPairRegisterClass(Inst, Rt, Address, Decoder)
1447 : DecodeQPairRegisterClass(Inst, Rt, Address, Decoder);
1450 Is64bitVec ? DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder)
1451 : DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder);
1454 Is64bitVec ? DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder)
1455 : DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder);
1458 // Decode write back register, which is equal to Rn.
1459 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
1460 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
1462 if (Rm == 31) // If Rm is 0x11111, add the number of transferred bytes
1463 Inst.addOperand(MCOperand::CreateImm(TransferBytes));
1465 DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder);
1467 return MCDisassembler::Success;
1470 // Decode post-index of load/store lane
1471 // Loads have a vector list as output.
1475 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
1478 DecodeQPairRegisterClass(Inst, Rt, Address, Decoder);
1481 DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder);
1484 DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder);
1488 // Decode write back register, which is equal to Rn.
1489 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
1490 DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
1492 if (Rm == 31) // If Rm is 0x11111, add the number of transferred bytes
1493 Inst.addOperand(MCOperand::CreateImm(TransferBytes));
1495 DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder);
1497 // Decode the source vector list.
1500 DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
1503 DecodeQPairRegisterClass(Inst, Rt, Address, Decoder);
1506 DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder);
1509 DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder);
1513 unsigned Q = fieldFromInstruction(Insn, 30, 1);
1514 unsigned S = fieldFromInstruction(Insn, 10, 3);
1516 // Calculate the number of lanes by number of vectors and transfered bytes.
1517 // NumLanes = 16 bytes / bytes of each lane
1518 unsigned NumLanes = 16 / (TransferBytes / NumVecs);
1520 case 16: // A vector has 16 lanes, each lane is 1 bytes.
1521 lane = (Q << 3) | S;
1524 lane = (Q << 2) | (S >> 1);
1527 lane = (Q << 1) | (S >> 2);
1533 Inst.addOperand(MCOperand::CreateImm(lane));
1535 return MCDisassembler::Success;