1 //==- AArch64AsmParser.cpp - Parse AArch64 assembly to MCInst instructions -==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the (GNU-style) assembly parser for the AArch64
13 //===----------------------------------------------------------------------===//
16 #include "MCTargetDesc/AArch64MCTargetDesc.h"
17 #include "MCTargetDesc/AArch64MCExpr.h"
18 #include "Utils/AArch64BaseInfo.h"
19 #include "llvm/ADT/APFloat.h"
20 #include "llvm/ADT/APInt.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
26 #include "llvm/MC/MCTargetAsmParser.h"
27 #include "llvm/MC/MCExpr.h"
28 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/MC/MCStreamer.h"
30 #include "llvm/MC/MCParser/MCAsmLexer.h"
31 #include "llvm/MC/MCParser/MCAsmParser.h"
32 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Support/TargetRegistry.h"
43 class AArch64AsmParser : public MCTargetAsmParser {
47 #define GET_ASSEMBLER_HEADER
48 #include "AArch64GenAsmMatcher.inc"
51 enum AArch64MatchResultTy {
52 Match_FirstAArch64 = FIRST_TARGET_MATCH_RESULT_TY,
53 #define GET_OPERAND_DIAGNOSTIC_TYPES
54 #include "AArch64GenAsmMatcher.inc"
57 AArch64AsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
58 const MCInstrInfo &MII)
59 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
60 MCAsmParserExtension::Initialize(_Parser);
62 // Initialize the set of available features.
63 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
66 // These are the public interface of the MCTargetAsmParser
67 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
68 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
70 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
72 bool ParseDirective(AsmToken DirectiveID);
73 bool ParseDirectiveTLSDescCall(SMLoc L);
74 bool ParseDirectiveWord(unsigned Size, SMLoc L);
76 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
77 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
78 MCStreamer&Out, unsigned &ErrorInfo,
79 bool MatchingInlineAsm);
81 // The rest of the sub-parsers have more freedom over interface: they return
82 // an OperandMatchResultTy because it's less ambiguous than true/false or
83 // -1/0/1 even if it is more verbose
85 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
88 OperandMatchResultTy ParseImmediate(const MCExpr *&ExprVal);
90 OperandMatchResultTy ParseRelocPrefix(AArch64MCExpr::VariantKind &RefKind);
93 ParseNEONLane(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
97 ParseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
101 ParseImmWithLSLOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
104 ParseCondCodeOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
107 ParseCRxOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
110 ParseFPImmOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
112 template<typename SomeNamedImmMapper> OperandMatchResultTy
113 ParseNamedImmOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
114 return ParseNamedImmOperand(SomeNamedImmMapper(), Operands);
118 ParseNamedImmOperand(const NamedImmMapper &Mapper,
119 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
122 ParseLSXAddressOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
125 ParseShiftExtend(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
128 ParseSysRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
130 bool TryParseVector(uint32_t &RegNum, SMLoc &RegEndLoc, StringRef &Layout,
133 OperandMatchResultTy ParseVectorList(SmallVectorImpl<MCParsedAsmOperand *> &);
135 bool validateInstruction(MCInst &Inst,
136 const SmallVectorImpl<MCParsedAsmOperand*> &Operands);
138 /// Scan the next token (which had better be an identifier) and determine
139 /// whether it represents a general-purpose or vector register. It returns
140 /// true if an identifier was found and populates its reference arguments. It
141 /// does not consume the token.
143 IdentifyRegister(unsigned &RegNum, SMLoc &RegEndLoc, StringRef &LayoutSpec,
144 SMLoc &LayoutLoc) const;
152 /// Instances of this class represent a parsed AArch64 machine instruction.
153 class AArch64Operand : public MCParsedAsmOperand {
156 k_ImmWithLSL, // #uimm {, LSL #amt }
157 k_CondCode, // eq/ne/...
158 k_FPImmediate, // Limited-precision floating-point imm
159 k_Immediate, // Including expressions referencing symbols
162 k_VectorList, // A sequential list of 1 to 4 registers.
163 k_SysReg, // The register operand of MRS and MSR instructions
164 k_Token, // The mnemonic; other raw tokens the auto-generated
165 k_WrappedRegister // Load/store exclusive permit a wrapped register.
168 SMLoc StartLoc, EndLoc;
170 struct ImmWithLSLOp {
172 unsigned ShiftAmount;
177 A64CC::CondCodes Code;
192 struct ShiftExtendOp {
193 A64SE::ShiftExtSpecifiers ShiftType;
198 // A vector register list is a sequential list of 1 to 4 registers.
199 struct VectorListOp {
202 A64Layout::VectorLayout Layout;
216 struct ImmWithLSLOp ImmWithLSL;
217 struct CondCodeOp CondCode;
218 struct FPImmOp FPImm;
221 struct ShiftExtendOp ShiftExtend;
222 struct VectorListOp VectorList;
223 struct SysRegOp SysReg;
227 AArch64Operand(KindTy K, SMLoc S, SMLoc E)
228 : MCParsedAsmOperand(), Kind(K), StartLoc(S), EndLoc(E) {}
231 AArch64Operand(const AArch64Operand &o) : MCParsedAsmOperand() {
234 SMLoc getStartLoc() const { return StartLoc; }
235 SMLoc getEndLoc() const { return EndLoc; }
236 void print(raw_ostream&) const;
239 StringRef getToken() const {
240 assert(Kind == k_Token && "Invalid access!");
241 return StringRef(Tok.Data, Tok.Length);
244 unsigned getReg() const {
245 assert((Kind == k_Register || Kind == k_WrappedRegister)
246 && "Invalid access!");
250 const MCExpr *getImm() const {
251 assert(Kind == k_Immediate && "Invalid access!");
255 A64CC::CondCodes getCondCode() const {
256 assert(Kind == k_CondCode && "Invalid access!");
257 return CondCode.Code;
260 static bool isNonConstantExpr(const MCExpr *E,
261 AArch64MCExpr::VariantKind &Variant) {
262 if (const AArch64MCExpr *A64E = dyn_cast<AArch64MCExpr>(E)) {
263 Variant = A64E->getKind();
265 } else if (!isa<MCConstantExpr>(E)) {
266 Variant = AArch64MCExpr::VK_AARCH64_None;
273 bool isCondCode() const { return Kind == k_CondCode; }
274 bool isToken() const { return Kind == k_Token; }
275 bool isReg() const { return Kind == k_Register; }
276 bool isImm() const { return Kind == k_Immediate; }
277 bool isMem() const { return false; }
278 bool isFPImm() const { return Kind == k_FPImmediate; }
279 bool isShiftOrExtend() const { return Kind == k_ShiftExtend; }
280 bool isSysReg() const { return Kind == k_SysReg; }
281 bool isImmWithLSL() const { return Kind == k_ImmWithLSL; }
282 bool isWrappedReg() const { return Kind == k_WrappedRegister; }
284 bool isAddSubImmLSL0() const {
285 if (!isImmWithLSL()) return false;
286 if (ImmWithLSL.ShiftAmount != 0) return false;
288 AArch64MCExpr::VariantKind Variant;
289 if (isNonConstantExpr(ImmWithLSL.Val, Variant)) {
290 return Variant == AArch64MCExpr::VK_AARCH64_LO12
291 || Variant == AArch64MCExpr::VK_AARCH64_DTPREL_LO12
292 || Variant == AArch64MCExpr::VK_AARCH64_DTPREL_LO12_NC
293 || Variant == AArch64MCExpr::VK_AARCH64_TPREL_LO12
294 || Variant == AArch64MCExpr::VK_AARCH64_TPREL_LO12_NC
295 || Variant == AArch64MCExpr::VK_AARCH64_TLSDESC_LO12;
298 // Otherwise it should be a real immediate in range:
299 const MCConstantExpr *CE = cast<MCConstantExpr>(ImmWithLSL.Val);
300 return CE->getValue() >= 0 && CE->getValue() <= 0xfff;
303 bool isAddSubImmLSL12() const {
304 if (!isImmWithLSL()) return false;
305 if (ImmWithLSL.ShiftAmount != 12) return false;
307 AArch64MCExpr::VariantKind Variant;
308 if (isNonConstantExpr(ImmWithLSL.Val, Variant)) {
309 return Variant == AArch64MCExpr::VK_AARCH64_DTPREL_HI12
310 || Variant == AArch64MCExpr::VK_AARCH64_TPREL_HI12;
313 // Otherwise it should be a real immediate in range:
314 const MCConstantExpr *CE = cast<MCConstantExpr>(ImmWithLSL.Val);
315 return CE->getValue() >= 0 && CE->getValue() <= 0xfff;
318 template<unsigned MemSize, unsigned RmSize> bool isAddrRegExtend() const {
319 if (!isShiftOrExtend()) return false;
321 A64SE::ShiftExtSpecifiers Ext = ShiftExtend.ShiftType;
322 if (RmSize == 32 && !(Ext == A64SE::UXTW || Ext == A64SE::SXTW))
325 if (RmSize == 64 && !(Ext == A64SE::LSL || Ext == A64SE::SXTX))
328 return ShiftExtend.Amount == Log2_32(MemSize) || ShiftExtend.Amount == 0;
331 bool isAdrpLabel() const {
332 if (!isImm()) return false;
334 AArch64MCExpr::VariantKind Variant;
335 if (isNonConstantExpr(getImm(), Variant)) {
336 return Variant == AArch64MCExpr::VK_AARCH64_None
337 || Variant == AArch64MCExpr::VK_AARCH64_GOT
338 || Variant == AArch64MCExpr::VK_AARCH64_GOTTPREL
339 || Variant == AArch64MCExpr::VK_AARCH64_TLSDESC;
342 return isLabel<21, 4096>();
345 template<unsigned RegWidth> bool isBitfieldWidth() const {
346 if (!isImm()) return false;
348 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
349 if (!CE) return false;
351 return CE->getValue() >= 1 && CE->getValue() <= RegWidth;
354 template<int RegWidth>
355 bool isCVTFixedPos() const {
356 if (!isImm()) return false;
358 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
359 if (!CE) return false;
361 return CE->getValue() >= 1 && CE->getValue() <= RegWidth;
364 bool isFMOVImm() const {
365 if (!isFPImm()) return false;
367 APFloat RealVal(FPImm.Val);
369 return A64Imms::isFPImm(RealVal, ImmVal);
372 bool isFPZero() const {
373 if (!isFPImm()) return false;
375 APFloat RealVal(FPImm.Val);
376 return RealVal.isPosZero();
379 template<unsigned field_width, unsigned scale>
380 bool isLabel() const {
381 if (!isImm()) return false;
383 if (dyn_cast<MCSymbolRefExpr>(Imm.Val)) {
385 } else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
386 int64_t Val = CE->getValue();
387 int64_t Min = - (scale * (1LL << (field_width - 1)));
388 int64_t Max = scale * ((1LL << (field_width - 1)) - 1);
389 return (Val % scale) == 0 && Val >= Min && Val <= Max;
392 // N.b. this disallows explicit relocation specifications via an
393 // AArch64MCExpr. Users needing that behaviour
397 bool isLane1() const {
398 if (!isImm()) return false;
400 // Because it's come through custom assembly parsing, it must always be a
401 // constant expression.
402 return cast<MCConstantExpr>(getImm())->getValue() == 1;
405 bool isLoadLitLabel() const {
406 if (!isImm()) return false;
408 AArch64MCExpr::VariantKind Variant;
409 if (isNonConstantExpr(getImm(), Variant)) {
410 return Variant == AArch64MCExpr::VK_AARCH64_None
411 || Variant == AArch64MCExpr::VK_AARCH64_GOTTPREL;
414 return isLabel<19, 4>();
417 template<unsigned RegWidth> bool isLogicalImm() const {
418 if (!isImm()) return false;
420 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
421 if (!CE) return false;
424 return A64Imms::isLogicalImm(RegWidth, CE->getValue(), Bits);
427 template<unsigned RegWidth> bool isLogicalImmMOV() const {
428 if (!isLogicalImm<RegWidth>()) return false;
430 const MCConstantExpr *CE = cast<MCConstantExpr>(Imm.Val);
432 // The move alias for ORR is only valid if the immediate cannot be
433 // represented with a move (immediate) instruction; they take priority.
435 return !A64Imms::isMOVZImm(RegWidth, CE->getValue(), UImm16, Shift)
436 && !A64Imms::isMOVNImm(RegWidth, CE->getValue(), UImm16, Shift);
439 template<int MemSize>
440 bool isOffsetUImm12() const {
441 if (!isImm()) return false;
443 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
445 // Assume they know what they're doing for now if they've given us a
446 // non-constant expression. In principle we could check for ridiculous
447 // things that can't possibly work or relocations that would almost
448 // certainly break resulting code.
452 int64_t Val = CE->getValue();
454 // Must be a multiple of the access size in bytes.
455 if ((Val & (MemSize - 1)) != 0) return false;
457 // Must be 12-bit unsigned
458 return Val >= 0 && Val <= 0xfff * MemSize;
461 template<A64SE::ShiftExtSpecifiers SHKind, bool is64Bit>
462 bool isShift() const {
463 if (!isShiftOrExtend()) return false;
465 if (ShiftExtend.ShiftType != SHKind)
468 return is64Bit ? ShiftExtend.Amount <= 63 : ShiftExtend.Amount <= 31;
471 bool isMOVN32Imm() const {
472 static const AArch64MCExpr::VariantKind PermittedModifiers[] = {
473 AArch64MCExpr::VK_AARCH64_SABS_G0,
474 AArch64MCExpr::VK_AARCH64_SABS_G1,
475 AArch64MCExpr::VK_AARCH64_DTPREL_G1,
476 AArch64MCExpr::VK_AARCH64_DTPREL_G0,
477 AArch64MCExpr::VK_AARCH64_GOTTPREL_G1,
478 AArch64MCExpr::VK_AARCH64_TPREL_G1,
479 AArch64MCExpr::VK_AARCH64_TPREL_G0,
481 const unsigned NumModifiers = llvm::array_lengthof(PermittedModifiers);
483 return isMoveWideImm(32, PermittedModifiers, NumModifiers);
486 bool isMOVN64Imm() const {
487 static const AArch64MCExpr::VariantKind PermittedModifiers[] = {
488 AArch64MCExpr::VK_AARCH64_SABS_G0,
489 AArch64MCExpr::VK_AARCH64_SABS_G1,
490 AArch64MCExpr::VK_AARCH64_SABS_G2,
491 AArch64MCExpr::VK_AARCH64_DTPREL_G2,
492 AArch64MCExpr::VK_AARCH64_DTPREL_G1,
493 AArch64MCExpr::VK_AARCH64_DTPREL_G0,
494 AArch64MCExpr::VK_AARCH64_GOTTPREL_G1,
495 AArch64MCExpr::VK_AARCH64_TPREL_G2,
496 AArch64MCExpr::VK_AARCH64_TPREL_G1,
497 AArch64MCExpr::VK_AARCH64_TPREL_G0,
499 const unsigned NumModifiers = llvm::array_lengthof(PermittedModifiers);
501 return isMoveWideImm(64, PermittedModifiers, NumModifiers);
505 bool isMOVZ32Imm() const {
506 static const AArch64MCExpr::VariantKind PermittedModifiers[] = {
507 AArch64MCExpr::VK_AARCH64_ABS_G0,
508 AArch64MCExpr::VK_AARCH64_ABS_G1,
509 AArch64MCExpr::VK_AARCH64_SABS_G0,
510 AArch64MCExpr::VK_AARCH64_SABS_G1,
511 AArch64MCExpr::VK_AARCH64_DTPREL_G1,
512 AArch64MCExpr::VK_AARCH64_DTPREL_G0,
513 AArch64MCExpr::VK_AARCH64_GOTTPREL_G1,
514 AArch64MCExpr::VK_AARCH64_TPREL_G1,
515 AArch64MCExpr::VK_AARCH64_TPREL_G0,
517 const unsigned NumModifiers = llvm::array_lengthof(PermittedModifiers);
519 return isMoveWideImm(32, PermittedModifiers, NumModifiers);
522 bool isMOVZ64Imm() const {
523 static const AArch64MCExpr::VariantKind PermittedModifiers[] = {
524 AArch64MCExpr::VK_AARCH64_ABS_G0,
525 AArch64MCExpr::VK_AARCH64_ABS_G1,
526 AArch64MCExpr::VK_AARCH64_ABS_G2,
527 AArch64MCExpr::VK_AARCH64_ABS_G3,
528 AArch64MCExpr::VK_AARCH64_SABS_G0,
529 AArch64MCExpr::VK_AARCH64_SABS_G1,
530 AArch64MCExpr::VK_AARCH64_SABS_G2,
531 AArch64MCExpr::VK_AARCH64_DTPREL_G2,
532 AArch64MCExpr::VK_AARCH64_DTPREL_G1,
533 AArch64MCExpr::VK_AARCH64_DTPREL_G0,
534 AArch64MCExpr::VK_AARCH64_GOTTPREL_G1,
535 AArch64MCExpr::VK_AARCH64_TPREL_G2,
536 AArch64MCExpr::VK_AARCH64_TPREL_G1,
537 AArch64MCExpr::VK_AARCH64_TPREL_G0,
539 const unsigned NumModifiers = llvm::array_lengthof(PermittedModifiers);
541 return isMoveWideImm(64, PermittedModifiers, NumModifiers);
544 bool isMOVK32Imm() const {
545 static const AArch64MCExpr::VariantKind PermittedModifiers[] = {
546 AArch64MCExpr::VK_AARCH64_ABS_G0_NC,
547 AArch64MCExpr::VK_AARCH64_ABS_G1_NC,
548 AArch64MCExpr::VK_AARCH64_DTPREL_G1_NC,
549 AArch64MCExpr::VK_AARCH64_DTPREL_G0_NC,
550 AArch64MCExpr::VK_AARCH64_GOTTPREL_G0_NC,
551 AArch64MCExpr::VK_AARCH64_TPREL_G1_NC,
552 AArch64MCExpr::VK_AARCH64_TPREL_G0_NC,
554 const unsigned NumModifiers = llvm::array_lengthof(PermittedModifiers);
556 return isMoveWideImm(32, PermittedModifiers, NumModifiers);
559 bool isMOVK64Imm() const {
560 static const AArch64MCExpr::VariantKind PermittedModifiers[] = {
561 AArch64MCExpr::VK_AARCH64_ABS_G0_NC,
562 AArch64MCExpr::VK_AARCH64_ABS_G1_NC,
563 AArch64MCExpr::VK_AARCH64_ABS_G2_NC,
564 AArch64MCExpr::VK_AARCH64_ABS_G3,
565 AArch64MCExpr::VK_AARCH64_DTPREL_G1_NC,
566 AArch64MCExpr::VK_AARCH64_DTPREL_G0_NC,
567 AArch64MCExpr::VK_AARCH64_GOTTPREL_G0_NC,
568 AArch64MCExpr::VK_AARCH64_TPREL_G1_NC,
569 AArch64MCExpr::VK_AARCH64_TPREL_G0_NC,
571 const unsigned NumModifiers = llvm::array_lengthof(PermittedModifiers);
573 return isMoveWideImm(64, PermittedModifiers, NumModifiers);
576 bool isMoveWideImm(unsigned RegWidth,
577 const AArch64MCExpr::VariantKind *PermittedModifiers,
578 unsigned NumModifiers) const {
579 if (!isImmWithLSL()) return false;
581 if (ImmWithLSL.ShiftAmount % 16 != 0) return false;
582 if (ImmWithLSL.ShiftAmount >= RegWidth) return false;
584 AArch64MCExpr::VariantKind Modifier;
585 if (isNonConstantExpr(ImmWithLSL.Val, Modifier)) {
586 // E.g. "#:abs_g0:sym, lsl #16" makes no sense.
587 if (!ImmWithLSL.ImplicitAmount) return false;
589 for (unsigned i = 0; i < NumModifiers; ++i)
590 if (PermittedModifiers[i] == Modifier) return true;
595 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmWithLSL.Val);
596 return CE && CE->getValue() >= 0 && CE->getValue() <= 0xffff;
599 template<int RegWidth, bool (*isValidImm)(int, uint64_t, int&, int&)>
600 bool isMoveWideMovAlias() const {
601 if (!isImm()) return false;
603 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
604 if (!CE) return false;
607 uint64_t Value = CE->getValue();
609 // If this is a 32-bit instruction then all bits above 32 should be the
610 // same: either of these is fine because signed/unsigned values should be
612 if (RegWidth == 32) {
613 if ((Value >> 32) != 0 && (Value >> 32) != 0xffffffff)
616 Value &= 0xffffffffULL;
619 return isValidImm(RegWidth, Value, UImm16, Shift);
622 bool isMSRWithReg() const {
623 if (!isSysReg()) return false;
625 bool IsKnownRegister;
626 StringRef Name(SysReg.Data, SysReg.Length);
627 A64SysReg::MSRMapper().fromString(Name, IsKnownRegister);
629 return IsKnownRegister;
632 bool isMSRPState() const {
633 if (!isSysReg()) return false;
635 bool IsKnownRegister;
636 StringRef Name(SysReg.Data, SysReg.Length);
637 A64PState::PStateMapper().fromString(Name, IsKnownRegister);
639 return IsKnownRegister;
643 if (!isSysReg()) return false;
645 // First check against specific MSR-only (write-only) registers
646 bool IsKnownRegister;
647 StringRef Name(SysReg.Data, SysReg.Length);
648 A64SysReg::MRSMapper().fromString(Name, IsKnownRegister);
650 return IsKnownRegister;
653 bool isPRFM() const {
654 if (!isImm()) return false;
656 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
661 return CE->getValue() >= 0 && CE->getValue() <= 31;
664 template<A64SE::ShiftExtSpecifiers SHKind> bool isRegExtend() const {
665 if (!isShiftOrExtend()) return false;
667 if (ShiftExtend.ShiftType != SHKind)
670 return ShiftExtend.Amount <= 4;
673 bool isRegExtendLSL() const {
674 if (!isShiftOrExtend()) return false;
676 if (ShiftExtend.ShiftType != A64SE::LSL)
679 return !ShiftExtend.ImplicitAmount && ShiftExtend.Amount <= 4;
682 // if 0 < value <= w, return true
683 bool isShrFixedWidth(int w) const {
686 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
689 int64_t Value = CE->getValue();
690 return Value > 0 && Value <= w;
693 bool isShrImm8() const { return isShrFixedWidth(8); }
695 bool isShrImm16() const { return isShrFixedWidth(16); }
697 bool isShrImm32() const { return isShrFixedWidth(32); }
699 bool isShrImm64() const { return isShrFixedWidth(64); }
701 // if 0 <= value < w, return true
702 bool isShlFixedWidth(int w) const {
705 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
708 int64_t Value = CE->getValue();
709 return Value >= 0 && Value < w;
712 bool isShlImm8() const { return isShlFixedWidth(8); }
714 bool isShlImm16() const { return isShlFixedWidth(16); }
716 bool isShlImm32() const { return isShlFixedWidth(32); }
718 bool isShlImm64() const { return isShlFixedWidth(64); }
720 bool isNeonMovImmShiftLSL() const {
721 if (!isShiftOrExtend())
724 if (ShiftExtend.ShiftType != A64SE::LSL)
727 // Valid shift amount is 0, 8, 16 and 24.
728 return ShiftExtend.Amount % 8 == 0 && ShiftExtend.Amount <= 24;
731 bool isNeonMovImmShiftLSLH() const {
732 if (!isShiftOrExtend())
735 if (ShiftExtend.ShiftType != A64SE::LSL)
738 // Valid shift amount is 0 and 8.
739 return ShiftExtend.Amount == 0 || ShiftExtend.Amount == 8;
742 bool isNeonMovImmShiftMSL() const {
743 if (!isShiftOrExtend())
746 if (ShiftExtend.ShiftType != A64SE::MSL)
749 // Valid shift amount is 8 and 16.
750 return ShiftExtend.Amount == 8 || ShiftExtend.Amount == 16;
753 template <A64Layout::VectorLayout Layout, unsigned Count>
754 bool isVectorList() const {
755 return Kind == k_VectorList && VectorList.Layout == Layout &&
756 VectorList.Count == Count;
759 template <int MemSize> bool isSImm7Scaled() const {
763 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
764 if (!CE) return false;
766 int64_t Val = CE->getValue();
767 if (Val % MemSize != 0) return false;
771 return Val >= -64 && Val < 64;
774 template<int BitWidth>
775 bool isSImm() const {
776 if (!isImm()) return false;
778 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
779 if (!CE) return false;
781 return CE->getValue() >= -(1LL << (BitWidth - 1))
782 && CE->getValue() < (1LL << (BitWidth - 1));
785 template<int bitWidth>
786 bool isUImm() const {
787 if (!isImm()) return false;
789 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
790 if (!CE) return false;
792 return CE->getValue() >= 0 && CE->getValue() < (1LL << bitWidth);
795 bool isUImm() const {
796 if (!isImm()) return false;
798 return isa<MCConstantExpr>(getImm());
801 bool isNeonUImm64Mask() const {
805 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
809 uint64_t Value = CE->getValue();
811 // i64 value with each byte being either 0x00 or 0xff.
812 for (unsigned i = 0; i < 8; ++i, Value >>= 8)
813 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff)
818 static AArch64Operand *CreateImmWithLSL(const MCExpr *Val,
819 unsigned ShiftAmount,
822 AArch64Operand *Op = new AArch64Operand(k_ImmWithLSL, S, E);
823 Op->ImmWithLSL.Val = Val;
824 Op->ImmWithLSL.ShiftAmount = ShiftAmount;
825 Op->ImmWithLSL.ImplicitAmount = ImplicitAmount;
829 static AArch64Operand *CreateCondCode(A64CC::CondCodes Code,
831 AArch64Operand *Op = new AArch64Operand(k_CondCode, S, E);
832 Op->CondCode.Code = Code;
836 static AArch64Operand *CreateFPImm(double Val,
838 AArch64Operand *Op = new AArch64Operand(k_FPImmediate, S, E);
843 static AArch64Operand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
844 AArch64Operand *Op = new AArch64Operand(k_Immediate, S, E);
849 static AArch64Operand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
850 AArch64Operand *Op = new AArch64Operand(k_Register, S, E);
851 Op->Reg.RegNum = RegNum;
855 static AArch64Operand *CreateWrappedReg(unsigned RegNum, SMLoc S, SMLoc E) {
856 AArch64Operand *Op = new AArch64Operand(k_WrappedRegister, S, E);
857 Op->Reg.RegNum = RegNum;
861 static AArch64Operand *CreateShiftExtend(A64SE::ShiftExtSpecifiers ShiftTyp,
865 AArch64Operand *Op = new AArch64Operand(k_ShiftExtend, S, E);
866 Op->ShiftExtend.ShiftType = ShiftTyp;
867 Op->ShiftExtend.Amount = Amount;
868 Op->ShiftExtend.ImplicitAmount = ImplicitAmount;
872 static AArch64Operand *CreateSysReg(StringRef Str, SMLoc S) {
873 AArch64Operand *Op = new AArch64Operand(k_SysReg, S, S);
874 Op->Tok.Data = Str.data();
875 Op->Tok.Length = Str.size();
879 static AArch64Operand *CreateVectorList(unsigned RegNum, unsigned Count,
880 A64Layout::VectorLayout Layout,
882 AArch64Operand *Op = new AArch64Operand(k_VectorList, S, E);
883 Op->VectorList.RegNum = RegNum;
884 Op->VectorList.Count = Count;
885 Op->VectorList.Layout = Layout;
891 static AArch64Operand *CreateToken(StringRef Str, SMLoc S) {
892 AArch64Operand *Op = new AArch64Operand(k_Token, S, S);
893 Op->Tok.Data = Str.data();
894 Op->Tok.Length = Str.size();
899 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
900 // Add as immediates when possible.
901 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
902 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
904 Inst.addOperand(MCOperand::CreateExpr(Expr));
907 template<unsigned RegWidth>
908 void addBFILSBOperands(MCInst &Inst, unsigned N) const {
909 assert(N == 1 && "Invalid number of operands!");
910 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
911 unsigned EncodedVal = (RegWidth - CE->getValue()) % RegWidth;
912 Inst.addOperand(MCOperand::CreateImm(EncodedVal));
915 void addBFIWidthOperands(MCInst &Inst, unsigned N) const {
916 assert(N == 1 && "Invalid number of operands!");
917 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
918 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
921 void addBFXWidthOperands(MCInst &Inst, unsigned N) const {
922 assert(N == 1 && "Invalid number of operands!");
924 uint64_t LSB = Inst.getOperand(Inst.getNumOperands()-1).getImm();
925 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
927 Inst.addOperand(MCOperand::CreateImm(LSB + CE->getValue() - 1));
930 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
931 assert(N == 1 && "Invalid number of operands!");
932 Inst.addOperand(MCOperand::CreateImm(getCondCode()));
935 void addCVTFixedPosOperands(MCInst &Inst, unsigned N) const {
936 assert(N == 1 && "Invalid number of operands!");
938 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
939 Inst.addOperand(MCOperand::CreateImm(64 - CE->getValue()));
942 void addFMOVImmOperands(MCInst &Inst, unsigned N) const {
943 assert(N == 1 && "Invalid number of operands!");
945 APFloat RealVal(FPImm.Val);
947 A64Imms::isFPImm(RealVal, ImmVal);
949 Inst.addOperand(MCOperand::CreateImm(ImmVal));
952 void addFPZeroOperands(MCInst &Inst, unsigned N) const {
953 assert(N == 1 && "Invalid number of operands");
954 Inst.addOperand(MCOperand::CreateImm(0));
957 void addInvCondCodeOperands(MCInst &Inst, unsigned N) const {
958 assert(N == 1 && "Invalid number of operands!");
959 unsigned Encoded = A64InvertCondCode(getCondCode());
960 Inst.addOperand(MCOperand::CreateImm(Encoded));
963 void addRegOperands(MCInst &Inst, unsigned N) const {
964 assert(N == 1 && "Invalid number of operands!");
965 Inst.addOperand(MCOperand::CreateReg(getReg()));
968 void addImmOperands(MCInst &Inst, unsigned N) const {
969 assert(N == 1 && "Invalid number of operands!");
970 addExpr(Inst, getImm());
973 template<int MemSize>
974 void addSImm7ScaledOperands(MCInst &Inst, unsigned N) const {
975 assert(N == 1 && "Invalid number of operands!");
977 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
978 uint64_t Val = CE->getValue() / MemSize;
979 Inst.addOperand(MCOperand::CreateImm(Val & 0x7f));
982 template<int BitWidth>
983 void addSImmOperands(MCInst &Inst, unsigned N) const {
984 assert(N == 1 && "Invalid number of operands!");
986 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
987 uint64_t Val = CE->getValue();
988 Inst.addOperand(MCOperand::CreateImm(Val & ((1ULL << BitWidth) - 1)));
991 void addImmWithLSLOperands(MCInst &Inst, unsigned N) const {
992 assert (N == 1 && "Invalid number of operands!");
994 addExpr(Inst, ImmWithLSL.Val);
997 template<unsigned field_width, unsigned scale>
998 void addLabelOperands(MCInst &Inst, unsigned N) const {
999 assert(N == 1 && "Invalid number of operands!");
1001 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
1004 addExpr(Inst, Imm.Val);
1008 int64_t Val = CE->getValue();
1009 assert(Val % scale == 0 && "Unaligned immediate in instruction");
1012 Inst.addOperand(MCOperand::CreateImm(Val & ((1LL << field_width) - 1)));
1015 template<int MemSize>
1016 void addOffsetUImm12Operands(MCInst &Inst, unsigned N) const {
1017 assert(N == 1 && "Invalid number of operands!");
1019 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1020 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / MemSize));
1022 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1026 template<unsigned RegWidth>
1027 void addLogicalImmOperands(MCInst &Inst, unsigned N) const {
1028 assert(N == 1 && "Invalid number of operands");
1029 const MCConstantExpr *CE = cast<MCConstantExpr>(Imm.Val);
1032 A64Imms::isLogicalImm(RegWidth, CE->getValue(), Bits);
1034 Inst.addOperand(MCOperand::CreateImm(Bits));
1037 void addMRSOperands(MCInst &Inst, unsigned N) const {
1038 assert(N == 1 && "Invalid number of operands!");
1041 StringRef Name(SysReg.Data, SysReg.Length);
1042 uint32_t Bits = A64SysReg::MRSMapper().fromString(Name, Valid);
1044 Inst.addOperand(MCOperand::CreateImm(Bits));
1047 void addMSRWithRegOperands(MCInst &Inst, unsigned N) const {
1048 assert(N == 1 && "Invalid number of operands!");
1051 StringRef Name(SysReg.Data, SysReg.Length);
1052 uint32_t Bits = A64SysReg::MSRMapper().fromString(Name, Valid);
1054 Inst.addOperand(MCOperand::CreateImm(Bits));
1057 void addMSRPStateOperands(MCInst &Inst, unsigned N) const {
1058 assert(N == 1 && "Invalid number of operands!");
1061 StringRef Name(SysReg.Data, SysReg.Length);
1062 uint32_t Bits = A64PState::PStateMapper().fromString(Name, Valid);
1064 Inst.addOperand(MCOperand::CreateImm(Bits));
1067 void addMoveWideImmOperands(MCInst &Inst, unsigned N) const {
1068 assert(N == 2 && "Invalid number of operands!");
1070 addExpr(Inst, ImmWithLSL.Val);
1072 AArch64MCExpr::VariantKind Variant;
1073 if (!isNonConstantExpr(ImmWithLSL.Val, Variant)) {
1074 Inst.addOperand(MCOperand::CreateImm(ImmWithLSL.ShiftAmount / 16));
1078 // We know it's relocated
1080 case AArch64MCExpr::VK_AARCH64_ABS_G0:
1081 case AArch64MCExpr::VK_AARCH64_ABS_G0_NC:
1082 case AArch64MCExpr::VK_AARCH64_SABS_G0:
1083 case AArch64MCExpr::VK_AARCH64_DTPREL_G0:
1084 case AArch64MCExpr::VK_AARCH64_DTPREL_G0_NC:
1085 case AArch64MCExpr::VK_AARCH64_GOTTPREL_G0_NC:
1086 case AArch64MCExpr::VK_AARCH64_TPREL_G0:
1087 case AArch64MCExpr::VK_AARCH64_TPREL_G0_NC:
1088 Inst.addOperand(MCOperand::CreateImm(0));
1090 case AArch64MCExpr::VK_AARCH64_ABS_G1:
1091 case AArch64MCExpr::VK_AARCH64_ABS_G1_NC:
1092 case AArch64MCExpr::VK_AARCH64_SABS_G1:
1093 case AArch64MCExpr::VK_AARCH64_DTPREL_G1:
1094 case AArch64MCExpr::VK_AARCH64_DTPREL_G1_NC:
1095 case AArch64MCExpr::VK_AARCH64_GOTTPREL_G1:
1096 case AArch64MCExpr::VK_AARCH64_TPREL_G1:
1097 case AArch64MCExpr::VK_AARCH64_TPREL_G1_NC:
1098 Inst.addOperand(MCOperand::CreateImm(1));
1100 case AArch64MCExpr::VK_AARCH64_ABS_G2:
1101 case AArch64MCExpr::VK_AARCH64_ABS_G2_NC:
1102 case AArch64MCExpr::VK_AARCH64_SABS_G2:
1103 case AArch64MCExpr::VK_AARCH64_DTPREL_G2:
1104 case AArch64MCExpr::VK_AARCH64_TPREL_G2:
1105 Inst.addOperand(MCOperand::CreateImm(2));
1107 case AArch64MCExpr::VK_AARCH64_ABS_G3:
1108 Inst.addOperand(MCOperand::CreateImm(3));
1110 default: llvm_unreachable("Inappropriate move wide relocation");
1114 template<int RegWidth, bool isValidImm(int, uint64_t, int&, int&)>
1115 void addMoveWideMovAliasOperands(MCInst &Inst, unsigned N) const {
1116 assert(N == 2 && "Invalid number of operands!");
1119 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
1120 uint64_t Value = CE->getValue();
1122 if (RegWidth == 32) {
1123 Value &= 0xffffffffULL;
1126 bool Valid = isValidImm(RegWidth, Value, UImm16, Shift);
1128 assert(Valid && "Invalid immediates should have been weeded out by now");
1130 Inst.addOperand(MCOperand::CreateImm(UImm16));
1131 Inst.addOperand(MCOperand::CreateImm(Shift));
1134 void addPRFMOperands(MCInst &Inst, unsigned N) const {
1135 assert(N == 1 && "Invalid number of operands!");
1137 const MCConstantExpr *CE = cast<MCConstantExpr>(getImm());
1138 assert(CE->getValue() >= 0 && CE->getValue() <= 31
1139 && "PRFM operand should be 5-bits");
1141 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1144 // For Add-sub (extended register) operands.
1145 void addRegExtendOperands(MCInst &Inst, unsigned N) const {
1146 assert(N == 1 && "Invalid number of operands!");
1148 Inst.addOperand(MCOperand::CreateImm(ShiftExtend.Amount));
1151 // For Vector Immediates shifted imm operands.
1152 void addNeonMovImmShiftLSLOperands(MCInst &Inst, unsigned N) const {
1153 assert(N == 1 && "Invalid number of operands!");
1155 if (ShiftExtend.Amount % 8 != 0 || ShiftExtend.Amount > 24)
1156 llvm_unreachable("Invalid shift amount for vector immediate inst.");
1158 // Encode LSL shift amount 0, 8, 16, 24 as 0, 1, 2, 3.
1159 int64_t Imm = ShiftExtend.Amount / 8;
1160 Inst.addOperand(MCOperand::CreateImm(Imm));
1163 void addNeonMovImmShiftLSLHOperands(MCInst &Inst, unsigned N) const {
1164 assert(N == 1 && "Invalid number of operands!");
1166 if (ShiftExtend.Amount != 0 && ShiftExtend.Amount != 8)
1167 llvm_unreachable("Invalid shift amount for vector immediate inst.");
1169 // Encode LSLH shift amount 0, 8 as 0, 1.
1170 int64_t Imm = ShiftExtend.Amount / 8;
1171 Inst.addOperand(MCOperand::CreateImm(Imm));
1174 void addNeonMovImmShiftMSLOperands(MCInst &Inst, unsigned N) const {
1175 assert(N == 1 && "Invalid number of operands!");
1177 if (ShiftExtend.Amount != 8 && ShiftExtend.Amount != 16)
1178 llvm_unreachable("Invalid shift amount for vector immediate inst.");
1180 // Encode MSL shift amount 8, 16 as 0, 1.
1181 int64_t Imm = ShiftExtend.Amount / 8 - 1;
1182 Inst.addOperand(MCOperand::CreateImm(Imm));
1185 // For the extend in load-store (register offset) instructions.
1186 template<unsigned MemSize>
1187 void addAddrRegExtendOperands(MCInst &Inst, unsigned N) const {
1188 addAddrRegExtendOperands(Inst, N, MemSize);
1191 void addAddrRegExtendOperands(MCInst &Inst, unsigned N,
1192 unsigned MemSize) const {
1193 assert(N == 1 && "Invalid number of operands!");
1195 // First bit of Option is set in instruction classes, the high two bits are
1197 unsigned OptionHi = 0;
1198 switch (ShiftExtend.ShiftType) {
1208 llvm_unreachable("Invalid extend type for register offset");
1212 if (MemSize == 1 && !ShiftExtend.ImplicitAmount)
1214 else if (MemSize != 1 && ShiftExtend.Amount != 0)
1217 Inst.addOperand(MCOperand::CreateImm((OptionHi << 1) | S));
1219 void addShiftOperands(MCInst &Inst, unsigned N) const {
1220 assert(N == 1 && "Invalid number of operands!");
1222 Inst.addOperand(MCOperand::CreateImm(ShiftExtend.Amount));
1225 void addNeonUImm64MaskOperands(MCInst &Inst, unsigned N) const {
1226 assert(N == 1 && "Invalid number of operands!");
1228 // A bit from each byte in the constant forms the encoded immediate
1229 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1230 uint64_t Value = CE->getValue();
1233 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
1234 Imm |= (Value & 1) << i;
1236 Inst.addOperand(MCOperand::CreateImm(Imm));
1239 void addVectorListOperands(MCInst &Inst, unsigned N) const {
1240 assert(N == 1 && "Invalid number of operands!");
1241 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1245 } // end anonymous namespace.
1247 AArch64AsmParser::OperandMatchResultTy
1248 AArch64AsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1249 StringRef Mnemonic) {
1251 // See if the operand has a custom parser
1252 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1254 // It could either succeed, fail or just not care.
1255 if (ResTy != MatchOperand_NoMatch)
1258 switch (getLexer().getKind()) {
1260 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1261 return MatchOperand_ParseFail;
1262 case AsmToken::Identifier: {
1263 // It might be in the LSL/UXTB family ...
1264 OperandMatchResultTy GotShift = ParseShiftExtend(Operands);
1266 // We can only continue if no tokens were eaten.
1267 if (GotShift != MatchOperand_NoMatch)
1270 // ... or it might be a register ...
1271 uint32_t NumLanes = 0;
1272 OperandMatchResultTy GotReg = ParseRegister(Operands, NumLanes);
1273 assert(GotReg != MatchOperand_ParseFail
1274 && "register parsing shouldn't partially succeed");
1276 if (GotReg == MatchOperand_Success) {
1277 if (Parser.getTok().is(AsmToken::LBrac))
1278 return ParseNEONLane(Operands, NumLanes);
1280 return MatchOperand_Success;
1282 // ... or it might be a symbolish thing
1285 case AsmToken::LParen: // E.g. (strcmp-4)
1286 case AsmToken::Integer: // 1f, 2b labels
1287 case AsmToken::String: // quoted labels
1288 case AsmToken::Dot: // . is Current location
1289 case AsmToken::Dollar: // $ is PC
1290 case AsmToken::Colon: {
1291 SMLoc StartLoc = Parser.getTok().getLoc();
1293 const MCExpr *ImmVal = 0;
1295 if (ParseImmediate(ImmVal) != MatchOperand_Success)
1296 return MatchOperand_ParseFail;
1298 EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1299 Operands.push_back(AArch64Operand::CreateImm(ImmVal, StartLoc, EndLoc));
1300 return MatchOperand_Success;
1302 case AsmToken::Hash: { // Immediates
1303 SMLoc StartLoc = Parser.getTok().getLoc();
1305 const MCExpr *ImmVal = 0;
1308 if (ParseImmediate(ImmVal) != MatchOperand_Success)
1309 return MatchOperand_ParseFail;
1311 EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1312 Operands.push_back(AArch64Operand::CreateImm(ImmVal, StartLoc, EndLoc));
1313 return MatchOperand_Success;
1315 case AsmToken::LBrac: {
1316 SMLoc Loc = Parser.getTok().getLoc();
1317 Operands.push_back(AArch64Operand::CreateToken("[", Loc));
1318 Parser.Lex(); // Eat '['
1320 // There's no comma after a '[', so we can parse the next operand
1322 return ParseOperand(Operands, Mnemonic);
1324 // The following will likely be useful later, but not in very early cases
1325 case AsmToken::LCurly: // SIMD vector list is not parsed here
1326 llvm_unreachable("Don't know how to deal with '{' in operand");
1327 return MatchOperand_ParseFail;
1331 AArch64AsmParser::OperandMatchResultTy
1332 AArch64AsmParser::ParseImmediate(const MCExpr *&ExprVal) {
1333 if (getLexer().is(AsmToken::Colon)) {
1334 AArch64MCExpr::VariantKind RefKind;
1336 OperandMatchResultTy ResTy = ParseRelocPrefix(RefKind);
1337 if (ResTy != MatchOperand_Success)
1340 const MCExpr *SubExprVal;
1341 if (getParser().parseExpression(SubExprVal))
1342 return MatchOperand_ParseFail;
1344 ExprVal = AArch64MCExpr::Create(RefKind, SubExprVal, getContext());
1345 return MatchOperand_Success;
1348 // No weird AArch64MCExpr prefix
1349 return getParser().parseExpression(ExprVal)
1350 ? MatchOperand_ParseFail : MatchOperand_Success;
1353 // A lane attached to a NEON register. "[N]", which should yield three tokens:
1354 // '[', N, ']'. A hash is not allowed to precede the immediate here.
1355 AArch64AsmParser::OperandMatchResultTy
1356 AArch64AsmParser::ParseNEONLane(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1357 uint32_t NumLanes) {
1358 SMLoc Loc = Parser.getTok().getLoc();
1360 assert(Parser.getTok().is(AsmToken::LBrac) && "inappropriate operand");
1361 Operands.push_back(AArch64Operand::CreateToken("[", Loc));
1362 Parser.Lex(); // Eat '['
1364 if (Parser.getTok().isNot(AsmToken::Integer)) {
1365 Error(Parser.getTok().getLoc(), "expected lane number");
1366 return MatchOperand_ParseFail;
1369 if (Parser.getTok().getIntVal() >= NumLanes) {
1370 Error(Parser.getTok().getLoc(), "lane number incompatible with layout");
1371 return MatchOperand_ParseFail;
1374 const MCExpr *Lane = MCConstantExpr::Create(Parser.getTok().getIntVal(),
1376 SMLoc S = Parser.getTok().getLoc();
1377 Parser.Lex(); // Eat actual lane
1378 SMLoc E = Parser.getTok().getLoc();
1379 Operands.push_back(AArch64Operand::CreateImm(Lane, S, E));
1382 if (Parser.getTok().isNot(AsmToken::RBrac)) {
1383 Error(Parser.getTok().getLoc(), "expected ']' after lane");
1384 return MatchOperand_ParseFail;
1387 Operands.push_back(AArch64Operand::CreateToken("]", Loc));
1388 Parser.Lex(); // Eat ']'
1390 return MatchOperand_Success;
1393 AArch64AsmParser::OperandMatchResultTy
1394 AArch64AsmParser::ParseRelocPrefix(AArch64MCExpr::VariantKind &RefKind) {
1395 assert(getLexer().is(AsmToken::Colon) && "expected a ':'");
1398 if (getLexer().isNot(AsmToken::Identifier)) {
1399 Error(Parser.getTok().getLoc(),
1400 "expected relocation specifier in operand after ':'");
1401 return MatchOperand_ParseFail;
1404 std::string LowerCase = Parser.getTok().getIdentifier().lower();
1405 RefKind = StringSwitch<AArch64MCExpr::VariantKind>(LowerCase)
1406 .Case("got", AArch64MCExpr::VK_AARCH64_GOT)
1407 .Case("got_lo12", AArch64MCExpr::VK_AARCH64_GOT_LO12)
1408 .Case("lo12", AArch64MCExpr::VK_AARCH64_LO12)
1409 .Case("abs_g0", AArch64MCExpr::VK_AARCH64_ABS_G0)
1410 .Case("abs_g0_nc", AArch64MCExpr::VK_AARCH64_ABS_G0_NC)
1411 .Case("abs_g1", AArch64MCExpr::VK_AARCH64_ABS_G1)
1412 .Case("abs_g1_nc", AArch64MCExpr::VK_AARCH64_ABS_G1_NC)
1413 .Case("abs_g2", AArch64MCExpr::VK_AARCH64_ABS_G2)
1414 .Case("abs_g2_nc", AArch64MCExpr::VK_AARCH64_ABS_G2_NC)
1415 .Case("abs_g3", AArch64MCExpr::VK_AARCH64_ABS_G3)
1416 .Case("abs_g0_s", AArch64MCExpr::VK_AARCH64_SABS_G0)
1417 .Case("abs_g1_s", AArch64MCExpr::VK_AARCH64_SABS_G1)
1418 .Case("abs_g2_s", AArch64MCExpr::VK_AARCH64_SABS_G2)
1419 .Case("dtprel_g2", AArch64MCExpr::VK_AARCH64_DTPREL_G2)
1420 .Case("dtprel_g1", AArch64MCExpr::VK_AARCH64_DTPREL_G1)
1421 .Case("dtprel_g1_nc", AArch64MCExpr::VK_AARCH64_DTPREL_G1_NC)
1422 .Case("dtprel_g0", AArch64MCExpr::VK_AARCH64_DTPREL_G0)
1423 .Case("dtprel_g0_nc", AArch64MCExpr::VK_AARCH64_DTPREL_G0_NC)
1424 .Case("dtprel_hi12", AArch64MCExpr::VK_AARCH64_DTPREL_HI12)
1425 .Case("dtprel_lo12", AArch64MCExpr::VK_AARCH64_DTPREL_LO12)
1426 .Case("dtprel_lo12_nc", AArch64MCExpr::VK_AARCH64_DTPREL_LO12_NC)
1427 .Case("gottprel_g1", AArch64MCExpr::VK_AARCH64_GOTTPREL_G1)
1428 .Case("gottprel_g0_nc", AArch64MCExpr::VK_AARCH64_GOTTPREL_G0_NC)
1429 .Case("gottprel", AArch64MCExpr::VK_AARCH64_GOTTPREL)
1430 .Case("gottprel_lo12", AArch64MCExpr::VK_AARCH64_GOTTPREL_LO12)
1431 .Case("tprel_g2", AArch64MCExpr::VK_AARCH64_TPREL_G2)
1432 .Case("tprel_g1", AArch64MCExpr::VK_AARCH64_TPREL_G1)
1433 .Case("tprel_g1_nc", AArch64MCExpr::VK_AARCH64_TPREL_G1_NC)
1434 .Case("tprel_g0", AArch64MCExpr::VK_AARCH64_TPREL_G0)
1435 .Case("tprel_g0_nc", AArch64MCExpr::VK_AARCH64_TPREL_G0_NC)
1436 .Case("tprel_hi12", AArch64MCExpr::VK_AARCH64_TPREL_HI12)
1437 .Case("tprel_lo12", AArch64MCExpr::VK_AARCH64_TPREL_LO12)
1438 .Case("tprel_lo12_nc", AArch64MCExpr::VK_AARCH64_TPREL_LO12_NC)
1439 .Case("tlsdesc", AArch64MCExpr::VK_AARCH64_TLSDESC)
1440 .Case("tlsdesc_lo12", AArch64MCExpr::VK_AARCH64_TLSDESC_LO12)
1441 .Default(AArch64MCExpr::VK_AARCH64_None);
1443 if (RefKind == AArch64MCExpr::VK_AARCH64_None) {
1444 Error(Parser.getTok().getLoc(),
1445 "expected relocation specifier in operand after ':'");
1446 return MatchOperand_ParseFail;
1448 Parser.Lex(); // Eat identifier
1450 if (getLexer().isNot(AsmToken::Colon)) {
1451 Error(Parser.getTok().getLoc(),
1452 "expected ':' after relocation specifier");
1453 return MatchOperand_ParseFail;
1456 return MatchOperand_Success;
1459 AArch64AsmParser::OperandMatchResultTy
1460 AArch64AsmParser::ParseImmWithLSLOperand(
1461 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1462 // FIXME?: I want to live in a world where immediates must start with
1463 // #. Please don't dash my hopes (well, do if you have a good reason).
1464 if (Parser.getTok().isNot(AsmToken::Hash)) return MatchOperand_NoMatch;
1466 SMLoc S = Parser.getTok().getLoc();
1467 Parser.Lex(); // Eat '#'
1470 if (ParseImmediate(Imm) != MatchOperand_Success)
1471 return MatchOperand_ParseFail;
1472 else if (Parser.getTok().isNot(AsmToken::Comma)) {
1473 SMLoc E = Parser.getTok().getLoc();
1474 Operands.push_back(AArch64Operand::CreateImmWithLSL(Imm, 0, true, S, E));
1475 return MatchOperand_Success;
1481 // The optional operand must be "lsl #N" where N is non-negative.
1482 if (Parser.getTok().is(AsmToken::Identifier)
1483 && Parser.getTok().getIdentifier().lower() == "lsl") {
1486 if (Parser.getTok().is(AsmToken::Hash)) {
1489 if (Parser.getTok().isNot(AsmToken::Integer)) {
1490 Error(Parser.getTok().getLoc(), "only 'lsl #+N' valid after immediate");
1491 return MatchOperand_ParseFail;
1496 int64_t ShiftAmount = Parser.getTok().getIntVal();
1498 if (ShiftAmount < 0) {
1499 Error(Parser.getTok().getLoc(), "positive shift amount required");
1500 return MatchOperand_ParseFail;
1502 Parser.Lex(); // Eat the number
1504 SMLoc E = Parser.getTok().getLoc();
1505 Operands.push_back(AArch64Operand::CreateImmWithLSL(Imm, ShiftAmount,
1507 return MatchOperand_Success;
1511 AArch64AsmParser::OperandMatchResultTy
1512 AArch64AsmParser::ParseCondCodeOperand(
1513 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1514 if (Parser.getTok().isNot(AsmToken::Identifier))
1515 return MatchOperand_NoMatch;
1517 StringRef Tok = Parser.getTok().getIdentifier();
1518 A64CC::CondCodes CondCode = A64StringToCondCode(Tok);
1520 if (CondCode == A64CC::Invalid)
1521 return MatchOperand_NoMatch;
1523 SMLoc S = Parser.getTok().getLoc();
1524 Parser.Lex(); // Eat condition code
1525 SMLoc E = Parser.getTok().getLoc();
1527 Operands.push_back(AArch64Operand::CreateCondCode(CondCode, S, E));
1528 return MatchOperand_Success;
1531 AArch64AsmParser::OperandMatchResultTy
1532 AArch64AsmParser::ParseCRxOperand(
1533 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1534 SMLoc S = Parser.getTok().getLoc();
1535 if (Parser.getTok().isNot(AsmToken::Identifier)) {
1536 Error(S, "Expected cN operand where 0 <= N <= 15");
1537 return MatchOperand_ParseFail;
1540 std::string LowerTok = Parser.getTok().getIdentifier().lower();
1541 StringRef Tok(LowerTok);
1542 if (Tok[0] != 'c') {
1543 Error(S, "Expected cN operand where 0 <= N <= 15");
1544 return MatchOperand_ParseFail;
1548 bool BadNum = Tok.drop_front().getAsInteger(10, CRNum);
1549 if (BadNum || CRNum > 15) {
1550 Error(S, "Expected cN operand where 0 <= N <= 15");
1551 return MatchOperand_ParseFail;
1554 const MCExpr *CRImm = MCConstantExpr::Create(CRNum, getContext());
1557 SMLoc E = Parser.getTok().getLoc();
1559 Operands.push_back(AArch64Operand::CreateImm(CRImm, S, E));
1560 return MatchOperand_Success;
1563 AArch64AsmParser::OperandMatchResultTy
1564 AArch64AsmParser::ParseFPImmOperand(
1565 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1567 // FIXME?: I want to live in a world where immediates must start with
1568 // #. Please don't dash my hopes (well, do if you have a good reason).
1569 if (Parser.getTok().isNot(AsmToken::Hash)) return MatchOperand_NoMatch;
1571 SMLoc S = Parser.getTok().getLoc();
1572 Parser.Lex(); // Eat '#'
1574 bool Negative = false;
1575 if (Parser.getTok().is(AsmToken::Minus)) {
1577 Parser.Lex(); // Eat '-'
1578 } else if (Parser.getTok().is(AsmToken::Plus)) {
1579 Parser.Lex(); // Eat '+'
1582 if (Parser.getTok().isNot(AsmToken::Real)) {
1583 Error(S, "Expected floating-point immediate");
1584 return MatchOperand_ParseFail;
1587 APFloat RealVal(APFloat::IEEEdouble, Parser.getTok().getString());
1588 if (Negative) RealVal.changeSign();
1589 double DblVal = RealVal.convertToDouble();
1591 Parser.Lex(); // Eat real number
1592 SMLoc E = Parser.getTok().getLoc();
1594 Operands.push_back(AArch64Operand::CreateFPImm(DblVal, S, E));
1595 return MatchOperand_Success;
1599 // Automatically generated
1600 static unsigned MatchRegisterName(StringRef Name);
1603 AArch64AsmParser::IdentifyRegister(unsigned &RegNum, SMLoc &RegEndLoc,
1605 SMLoc &LayoutLoc) const {
1606 const AsmToken &Tok = Parser.getTok();
1608 if (Tok.isNot(AsmToken::Identifier))
1611 std::string LowerReg = Tok.getString().lower();
1612 size_t DotPos = LowerReg.find('.');
1614 bool IsVec128 = false;
1615 SMLoc S = Tok.getLoc();
1616 RegEndLoc = SMLoc::getFromPointer(S.getPointer() + DotPos);
1618 if (DotPos == std::string::npos) {
1619 Layout = StringRef();
1621 // Everything afterwards needs to be a literal token, expected to be
1622 // '.2d','.b' etc for vector registers.
1624 // This StringSwitch validates the input and (perhaps more importantly)
1625 // gives us a permanent string to use in the token (a pointer into LowerReg
1626 // would go out of scope when we return).
1627 LayoutLoc = SMLoc::getFromPointer(S.getPointer() + DotPos + 1);
1628 std::string LayoutText = LowerReg.substr(DotPos, StringRef::npos);
1630 // See if it's a 128-bit layout first.
1631 Layout = StringSwitch<const char *>(LayoutText)
1632 .Case(".d", ".d").Case(".2d", ".2d")
1633 .Case(".s", ".s").Case(".4s", ".4s")
1634 .Case(".h", ".h").Case(".8h", ".8h")
1635 .Case(".b", ".b").Case(".16b", ".16b")
1638 if (Layout.size() != 0)
1641 Layout = StringSwitch<const char *>(LayoutText)
1649 if (Layout.size() == 0) {
1650 // If we've still not pinned it down the register is malformed.
1655 RegNum = MatchRegisterName(LowerReg.substr(0, DotPos));
1656 if (RegNum == AArch64::NoRegister) {
1657 RegNum = StringSwitch<unsigned>(LowerReg.substr(0, DotPos))
1658 .Case("ip0", AArch64::X16)
1659 .Case("ip1", AArch64::X17)
1660 .Case("fp", AArch64::X29)
1661 .Case("lr", AArch64::X30)
1662 .Case("v0", IsVec128 ? AArch64::Q0 : AArch64::D0)
1663 .Case("v1", IsVec128 ? AArch64::Q1 : AArch64::D1)
1664 .Case("v2", IsVec128 ? AArch64::Q2 : AArch64::D2)
1665 .Case("v3", IsVec128 ? AArch64::Q3 : AArch64::D3)
1666 .Case("v4", IsVec128 ? AArch64::Q4 : AArch64::D4)
1667 .Case("v5", IsVec128 ? AArch64::Q5 : AArch64::D5)
1668 .Case("v6", IsVec128 ? AArch64::Q6 : AArch64::D6)
1669 .Case("v7", IsVec128 ? AArch64::Q7 : AArch64::D7)
1670 .Case("v8", IsVec128 ? AArch64::Q8 : AArch64::D8)
1671 .Case("v9", IsVec128 ? AArch64::Q9 : AArch64::D9)
1672 .Case("v10", IsVec128 ? AArch64::Q10 : AArch64::D10)
1673 .Case("v11", IsVec128 ? AArch64::Q11 : AArch64::D11)
1674 .Case("v12", IsVec128 ? AArch64::Q12 : AArch64::D12)
1675 .Case("v13", IsVec128 ? AArch64::Q13 : AArch64::D13)
1676 .Case("v14", IsVec128 ? AArch64::Q14 : AArch64::D14)
1677 .Case("v15", IsVec128 ? AArch64::Q15 : AArch64::D15)
1678 .Case("v16", IsVec128 ? AArch64::Q16 : AArch64::D16)
1679 .Case("v17", IsVec128 ? AArch64::Q17 : AArch64::D17)
1680 .Case("v18", IsVec128 ? AArch64::Q18 : AArch64::D18)
1681 .Case("v19", IsVec128 ? AArch64::Q19 : AArch64::D19)
1682 .Case("v20", IsVec128 ? AArch64::Q20 : AArch64::D20)
1683 .Case("v21", IsVec128 ? AArch64::Q21 : AArch64::D21)
1684 .Case("v22", IsVec128 ? AArch64::Q22 : AArch64::D22)
1685 .Case("v23", IsVec128 ? AArch64::Q23 : AArch64::D23)
1686 .Case("v24", IsVec128 ? AArch64::Q24 : AArch64::D24)
1687 .Case("v25", IsVec128 ? AArch64::Q25 : AArch64::D25)
1688 .Case("v26", IsVec128 ? AArch64::Q26 : AArch64::D26)
1689 .Case("v27", IsVec128 ? AArch64::Q27 : AArch64::D27)
1690 .Case("v28", IsVec128 ? AArch64::Q28 : AArch64::D28)
1691 .Case("v29", IsVec128 ? AArch64::Q29 : AArch64::D29)
1692 .Case("v30", IsVec128 ? AArch64::Q30 : AArch64::D30)
1693 .Case("v31", IsVec128 ? AArch64::Q31 : AArch64::D31)
1694 .Default(AArch64::NoRegister);
1696 if (RegNum == AArch64::NoRegister)
1702 AArch64AsmParser::OperandMatchResultTy
1703 AArch64AsmParser::ParseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1704 uint32_t &NumLanes) {
1707 SMLoc RegEndLoc, LayoutLoc;
1708 SMLoc S = Parser.getTok().getLoc();
1710 if (!IdentifyRegister(RegNum, RegEndLoc, Layout, LayoutLoc))
1711 return MatchOperand_NoMatch;
1713 Operands.push_back(AArch64Operand::CreateReg(RegNum, S, RegEndLoc));
1715 if (Layout.size() != 0) {
1716 unsigned long long TmpLanes = 0;
1717 llvm::getAsUnsignedInteger(Layout.substr(1), 10, TmpLanes);
1718 if (TmpLanes != 0) {
1719 NumLanes = TmpLanes;
1721 // If the number of lanes isn't specified explicitly, a valid instruction
1722 // will have an element specifier and be capable of acting on the entire
1724 switch (Layout.back()) {
1725 default: llvm_unreachable("Invalid layout specifier");
1726 case 'b': NumLanes = 16; break;
1727 case 'h': NumLanes = 8; break;
1728 case 's': NumLanes = 4; break;
1729 case 'd': NumLanes = 2; break;
1733 Operands.push_back(AArch64Operand::CreateToken(Layout, LayoutLoc));
1737 return MatchOperand_Success;
1741 AArch64AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
1743 // This callback is used for things like DWARF frame directives in
1744 // assembly. They don't care about things like NEON layouts or lanes, they
1745 // just want to be able to produce the DWARF register number.
1746 StringRef LayoutSpec;
1747 SMLoc RegEndLoc, LayoutLoc;
1748 StartLoc = Parser.getTok().getLoc();
1750 if (!IdentifyRegister(RegNo, RegEndLoc, LayoutSpec, LayoutLoc))
1754 EndLoc = Parser.getTok().getLoc();
1759 AArch64AsmParser::OperandMatchResultTy
1760 AArch64AsmParser::ParseNamedImmOperand(const NamedImmMapper &Mapper,
1761 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1762 // Since these operands occur in very limited circumstances, without
1763 // alternatives, we actually signal an error if there is no match. If relaxing
1764 // this, beware of unintended consequences: an immediate will be accepted
1765 // during matching, no matter how it gets into the AArch64Operand.
1766 const AsmToken &Tok = Parser.getTok();
1767 SMLoc S = Tok.getLoc();
1769 if (Tok.is(AsmToken::Identifier)) {
1771 uint32_t Code = Mapper.fromString(Tok.getString().lower(), ValidName);
1774 Error(S, "operand specifier not recognised");
1775 return MatchOperand_ParseFail;
1778 Parser.Lex(); // We're done with the identifier. Eat it
1780 SMLoc E = Parser.getTok().getLoc();
1781 const MCExpr *Imm = MCConstantExpr::Create(Code, getContext());
1782 Operands.push_back(AArch64Operand::CreateImm(Imm, S, E));
1783 return MatchOperand_Success;
1784 } else if (Tok.is(AsmToken::Hash)) {
1787 const MCExpr *ImmVal;
1788 if (ParseImmediate(ImmVal) != MatchOperand_Success)
1789 return MatchOperand_ParseFail;
1791 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
1792 if (!CE || CE->getValue() < 0 || !Mapper.validImm(CE->getValue())) {
1793 Error(S, "Invalid immediate for instruction");
1794 return MatchOperand_ParseFail;
1797 SMLoc E = Parser.getTok().getLoc();
1798 Operands.push_back(AArch64Operand::CreateImm(ImmVal, S, E));
1799 return MatchOperand_Success;
1802 Error(S, "unexpected operand for instruction");
1803 return MatchOperand_ParseFail;
1806 AArch64AsmParser::OperandMatchResultTy
1807 AArch64AsmParser::ParseSysRegOperand(
1808 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1809 const AsmToken &Tok = Parser.getTok();
1811 // Any MSR/MRS operand will be an identifier, and we want to store it as some
1812 // kind of string: SPSel is valid for two different forms of MSR with two
1813 // different encodings. There's no collision at the moment, but the potential
1815 if (!Tok.is(AsmToken::Identifier)) {
1816 return MatchOperand_NoMatch;
1819 SMLoc S = Tok.getLoc();
1820 Operands.push_back(AArch64Operand::CreateSysReg(Tok.getString(), S));
1821 Parser.Lex(); // Eat identifier
1823 return MatchOperand_Success;
1826 AArch64AsmParser::OperandMatchResultTy
1827 AArch64AsmParser::ParseLSXAddressOperand(
1828 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1829 SMLoc S = Parser.getTok().getLoc();
1832 SMLoc RegEndLoc, LayoutLoc;
1834 if(!IdentifyRegister(RegNum, RegEndLoc, Layout, LayoutLoc)
1835 || !AArch64MCRegisterClasses[AArch64::GPR64xspRegClassID].contains(RegNum)
1836 || Layout.size() != 0) {
1837 // Check Layout.size because we don't want to let "x3.4s" or similar
1839 return MatchOperand_NoMatch;
1841 Parser.Lex(); // Eat register
1843 if (Parser.getTok().is(AsmToken::RBrac)) {
1845 SMLoc E = Parser.getTok().getLoc();
1846 Operands.push_back(AArch64Operand::CreateWrappedReg(RegNum, S, E));
1847 return MatchOperand_Success;
1850 // Otherwise, only ", #0" is valid
1852 if (Parser.getTok().isNot(AsmToken::Comma)) {
1853 Error(Parser.getTok().getLoc(), "expected ',' or ']' after register");
1854 return MatchOperand_ParseFail;
1856 Parser.Lex(); // Eat ','
1858 if (Parser.getTok().isNot(AsmToken::Hash)) {
1859 Error(Parser.getTok().getLoc(), "expected '#0'");
1860 return MatchOperand_ParseFail;
1862 Parser.Lex(); // Eat '#'
1864 if (Parser.getTok().isNot(AsmToken::Integer)
1865 || Parser.getTok().getIntVal() != 0 ) {
1866 Error(Parser.getTok().getLoc(), "expected '#0'");
1867 return MatchOperand_ParseFail;
1869 Parser.Lex(); // Eat '0'
1871 SMLoc E = Parser.getTok().getLoc();
1872 Operands.push_back(AArch64Operand::CreateWrappedReg(RegNum, S, E));
1873 return MatchOperand_Success;
1876 AArch64AsmParser::OperandMatchResultTy
1877 AArch64AsmParser::ParseShiftExtend(
1878 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1879 StringRef IDVal = Parser.getTok().getIdentifier();
1880 std::string LowerID = IDVal.lower();
1882 A64SE::ShiftExtSpecifiers Spec =
1883 StringSwitch<A64SE::ShiftExtSpecifiers>(LowerID)
1884 .Case("lsl", A64SE::LSL)
1885 .Case("msl", A64SE::MSL)
1886 .Case("lsr", A64SE::LSR)
1887 .Case("asr", A64SE::ASR)
1888 .Case("ror", A64SE::ROR)
1889 .Case("uxtb", A64SE::UXTB)
1890 .Case("uxth", A64SE::UXTH)
1891 .Case("uxtw", A64SE::UXTW)
1892 .Case("uxtx", A64SE::UXTX)
1893 .Case("sxtb", A64SE::SXTB)
1894 .Case("sxth", A64SE::SXTH)
1895 .Case("sxtw", A64SE::SXTW)
1896 .Case("sxtx", A64SE::SXTX)
1897 .Default(A64SE::Invalid);
1899 if (Spec == A64SE::Invalid)
1900 return MatchOperand_NoMatch;
1904 S = Parser.getTok().getLoc();
1907 if (Spec != A64SE::LSL && Spec != A64SE::LSR && Spec != A64SE::ASR &&
1908 Spec != A64SE::ROR && Spec != A64SE::MSL) {
1909 // The shift amount can be omitted for the extending versions, but not real
1911 // add x0, x0, x0, uxtb
1912 // is valid, and equivalent to
1913 // add x0, x0, x0, uxtb #0
1915 if (Parser.getTok().is(AsmToken::Comma) ||
1916 Parser.getTok().is(AsmToken::EndOfStatement) ||
1917 Parser.getTok().is(AsmToken::RBrac)) {
1918 Operands.push_back(AArch64Operand::CreateShiftExtend(Spec, 0, true,
1920 return MatchOperand_Success;
1924 // Eat # at beginning of immediate
1925 if (!Parser.getTok().is(AsmToken::Hash)) {
1926 Error(Parser.getTok().getLoc(),
1927 "expected #imm after shift specifier");
1928 return MatchOperand_ParseFail;
1932 // Make sure we do actually have a number
1933 if (!Parser.getTok().is(AsmToken::Integer)) {
1934 Error(Parser.getTok().getLoc(),
1935 "expected integer shift amount");
1936 return MatchOperand_ParseFail;
1938 unsigned Amount = Parser.getTok().getIntVal();
1940 E = Parser.getTok().getLoc();
1942 Operands.push_back(AArch64Operand::CreateShiftExtend(Spec, Amount, false,
1945 return MatchOperand_Success;
1948 /// Try to parse a vector register token, If it is a vector register,
1949 /// the token is eaten and return true. Otherwise return false.
1950 bool AArch64AsmParser::TryParseVector(uint32_t &RegNum, SMLoc &RegEndLoc,
1951 StringRef &Layout, SMLoc &LayoutLoc) {
1952 bool IsVector = true;
1954 if (!IdentifyRegister(RegNum, RegEndLoc, Layout, LayoutLoc))
1957 if (!AArch64MCRegisterClasses[AArch64::FPR64RegClassID].contains(RegNum) &&
1958 !AArch64MCRegisterClasses[AArch64::FPR128RegClassID].contains(RegNum))
1961 if (Layout.size() == 0)
1965 Error(Parser.getTok().getLoc(), "expected vector type register");
1967 Parser.Lex(); // Eat this token.
1972 // A vector list contains 1-4 consecutive registers.
1973 // Now there are two kinds of vector list when number of vector > 1:
1974 // (1) {Vn.layout, Vn+1.layout, ... , Vm.layout}
1975 // (2) {Vn.layout - Vm.layout}
1976 AArch64AsmParser::OperandMatchResultTy AArch64AsmParser::ParseVectorList(
1977 SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
1978 if (Parser.getTok().isNot(AsmToken::LCurly)) {
1979 Error(Parser.getTok().getLoc(), "'{' expected");
1980 return MatchOperand_ParseFail;
1982 SMLoc SLoc = Parser.getTok().getLoc();
1983 Parser.Lex(); // Eat '{' token.
1985 unsigned Reg, Count = 1;
1986 StringRef LayoutStr;
1987 SMLoc RegEndLoc, LayoutLoc;
1988 if (!TryParseVector(Reg, RegEndLoc, LayoutStr, LayoutLoc))
1989 return MatchOperand_ParseFail;
1991 if (Parser.getTok().is(AsmToken::Minus)) {
1992 Parser.Lex(); // Eat the minus.
1995 StringRef LayoutStr2;
1996 SMLoc RegEndLoc2, LayoutLoc2;
1997 SMLoc RegLoc2 = Parser.getTok().getLoc();
1999 if (!TryParseVector(Reg2, RegEndLoc2, LayoutStr2, LayoutLoc2))
2000 return MatchOperand_ParseFail;
2001 unsigned Space = (Reg < Reg2) ? (Reg2 - Reg) : (Reg2 + 32 - Reg);
2003 if (LayoutStr != LayoutStr2) {
2004 Error(LayoutLoc2, "expected the same vector layout");
2005 return MatchOperand_ParseFail;
2007 if (Space == 0 || Space > 3) {
2008 Error(RegLoc2, "invalid number of vectors");
2009 return MatchOperand_ParseFail;
2014 unsigned LastReg = Reg;
2015 while (Parser.getTok().is(AsmToken::Comma)) {
2016 Parser.Lex(); // Eat the comma.
2018 StringRef LayoutStr2;
2019 SMLoc RegEndLoc2, LayoutLoc2;
2020 SMLoc RegLoc2 = Parser.getTok().getLoc();
2022 if (!TryParseVector(Reg2, RegEndLoc2, LayoutStr2, LayoutLoc2))
2023 return MatchOperand_ParseFail;
2024 unsigned Space = (LastReg < Reg2) ? (Reg2 - LastReg)
2025 : (Reg2 + 32 - LastReg);
2028 // The space between two vectors should be 1. And they should have the same layout.
2029 // Total count shouldn't be great than 4
2031 Error(RegLoc2, "invalid space between two vectors");
2032 return MatchOperand_ParseFail;
2034 if (LayoutStr != LayoutStr2) {
2035 Error(LayoutLoc2, "expected the same vector layout");
2036 return MatchOperand_ParseFail;
2039 Error(RegLoc2, "invalid number of vectors");
2040 return MatchOperand_ParseFail;
2047 if (Parser.getTok().isNot(AsmToken::RCurly)) {
2048 Error(Parser.getTok().getLoc(), "'}' expected");
2049 return MatchOperand_ParseFail;
2051 SMLoc ELoc = Parser.getTok().getLoc();
2052 Parser.Lex(); // Eat '}' token.
2054 A64Layout::VectorLayout Layout = A64StringToVectorLayout(LayoutStr);
2055 if (Count > 1) { // If count > 1, create vector list using super register.
2056 bool IsVec64 = (Layout < A64Layout::_16B) ? true : false;
2057 static unsigned SupRegIDs[3][2] = {
2058 { AArch64::QPairRegClassID, AArch64::DPairRegClassID },
2059 { AArch64::QTripleRegClassID, AArch64::DTripleRegClassID },
2060 { AArch64::QQuadRegClassID, AArch64::DQuadRegClassID }
2062 unsigned SupRegID = SupRegIDs[Count - 2][static_cast<int>(IsVec64)];
2063 unsigned Sub0 = IsVec64 ? AArch64::dsub_0 : AArch64::qsub_0;
2064 const MCRegisterInfo *MRI = getContext().getRegisterInfo();
2065 Reg = MRI->getMatchingSuperReg(Reg, Sub0,
2066 &AArch64MCRegisterClasses[SupRegID]);
2069 AArch64Operand::CreateVectorList(Reg, Count, Layout, SLoc, ELoc));
2071 return MatchOperand_Success;
2074 // FIXME: We would really like to be able to tablegen'erate this.
2075 bool AArch64AsmParser::
2076 validateInstruction(MCInst &Inst,
2077 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2078 switch (Inst.getOpcode()) {
2079 case AArch64::BFIwwii:
2080 case AArch64::BFIxxii:
2081 case AArch64::SBFIZwwii:
2082 case AArch64::SBFIZxxii:
2083 case AArch64::UBFIZwwii:
2084 case AArch64::UBFIZxxii: {
2085 unsigned ImmOps = Inst.getNumOperands() - 2;
2086 int64_t ImmR = Inst.getOperand(ImmOps).getImm();
2087 int64_t ImmS = Inst.getOperand(ImmOps+1).getImm();
2089 if (ImmR != 0 && ImmS >= ImmR) {
2090 return Error(Operands[4]->getStartLoc(),
2091 "requested insert overflows register");
2095 case AArch64::BFXILwwii:
2096 case AArch64::BFXILxxii:
2097 case AArch64::SBFXwwii:
2098 case AArch64::SBFXxxii:
2099 case AArch64::UBFXwwii:
2100 case AArch64::UBFXxxii: {
2101 unsigned ImmOps = Inst.getNumOperands() - 2;
2102 int64_t ImmR = Inst.getOperand(ImmOps).getImm();
2103 int64_t ImmS = Inst.getOperand(ImmOps+1).getImm();
2104 int64_t RegWidth = 0;
2105 switch (Inst.getOpcode()) {
2106 case AArch64::SBFXxxii: case AArch64::UBFXxxii: case AArch64::BFXILxxii:
2109 case AArch64::SBFXwwii: case AArch64::UBFXwwii: case AArch64::BFXILwwii:
2114 if (ImmS >= RegWidth || ImmS < ImmR) {
2115 return Error(Operands[4]->getStartLoc(),
2116 "requested extract overflows register");
2120 case AArch64::ICix: {
2121 int64_t ImmVal = Inst.getOperand(0).getImm();
2122 A64IC::ICValues ICOp = static_cast<A64IC::ICValues>(ImmVal);
2123 if (!A64IC::NeedsRegister(ICOp)) {
2124 return Error(Operands[1]->getStartLoc(),
2125 "specified IC op does not use a register");
2129 case AArch64::ICi: {
2130 int64_t ImmVal = Inst.getOperand(0).getImm();
2131 A64IC::ICValues ICOp = static_cast<A64IC::ICValues>(ImmVal);
2132 if (A64IC::NeedsRegister(ICOp)) {
2133 return Error(Operands[1]->getStartLoc(),
2134 "specified IC op requires a register");
2138 case AArch64::TLBIix: {
2139 int64_t ImmVal = Inst.getOperand(0).getImm();
2140 A64TLBI::TLBIValues TLBIOp = static_cast<A64TLBI::TLBIValues>(ImmVal);
2141 if (!A64TLBI::NeedsRegister(TLBIOp)) {
2142 return Error(Operands[1]->getStartLoc(),
2143 "specified TLBI op does not use a register");
2147 case AArch64::TLBIi: {
2148 int64_t ImmVal = Inst.getOperand(0).getImm();
2149 A64TLBI::TLBIValues TLBIOp = static_cast<A64TLBI::TLBIValues>(ImmVal);
2150 if (A64TLBI::NeedsRegister(TLBIOp)) {
2151 return Error(Operands[1]->getStartLoc(),
2152 "specified TLBI op requires a register");
2162 // Parses the instruction *together with* all operands, appending each parsed
2163 // operand to the "Operands" list
2164 bool AArch64AsmParser::ParseInstruction(ParseInstructionInfo &Info,
2165 StringRef Name, SMLoc NameLoc,
2166 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2167 size_t CondCodePos = Name.find('.');
2169 StringRef Mnemonic = Name.substr(0, CondCodePos);
2170 Operands.push_back(AArch64Operand::CreateToken(Mnemonic, NameLoc));
2172 if (CondCodePos != StringRef::npos) {
2173 // We have a condition code
2174 SMLoc S = SMLoc::getFromPointer(NameLoc.getPointer() + CondCodePos + 1);
2175 StringRef CondStr = Name.substr(CondCodePos + 1, StringRef::npos);
2176 A64CC::CondCodes Code;
2178 Code = A64StringToCondCode(CondStr);
2180 if (Code == A64CC::Invalid) {
2181 Error(S, "invalid condition code");
2182 Parser.eatToEndOfStatement();
2186 SMLoc DotL = SMLoc::getFromPointer(NameLoc.getPointer() + CondCodePos);
2188 Operands.push_back(AArch64Operand::CreateToken(".", DotL));
2189 SMLoc E = SMLoc::getFromPointer(NameLoc.getPointer() + CondCodePos + 3);
2190 Operands.push_back(AArch64Operand::CreateCondCode(Code, S, E));
2193 // Now we parse the operands of this instruction
2194 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2195 // Read the first operand.
2196 if (ParseOperand(Operands, Mnemonic)) {
2197 Parser.eatToEndOfStatement();
2201 while (getLexer().is(AsmToken::Comma)) {
2202 Parser.Lex(); // Eat the comma.
2204 // Parse and remember the operand.
2205 if (ParseOperand(Operands, Mnemonic)) {
2206 Parser.eatToEndOfStatement();
2211 // After successfully parsing some operands there are two special cases to
2212 // consider (i.e. notional operands not separated by commas). Both are due
2213 // to memory specifiers:
2214 // + An RBrac will end an address for load/store/prefetch
2215 // + An '!' will indicate a pre-indexed operation.
2217 // It's someone else's responsibility to make sure these tokens are sane
2218 // in the given context!
2219 if (Parser.getTok().is(AsmToken::RBrac)) {
2220 SMLoc Loc = Parser.getTok().getLoc();
2221 Operands.push_back(AArch64Operand::CreateToken("]", Loc));
2225 if (Parser.getTok().is(AsmToken::Exclaim)) {
2226 SMLoc Loc = Parser.getTok().getLoc();
2227 Operands.push_back(AArch64Operand::CreateToken("!", Loc));
2233 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2234 SMLoc Loc = getLexer().getLoc();
2235 Parser.eatToEndOfStatement();
2236 return Error(Loc, "expected comma before next operand");
2239 // Eat the EndOfStatement
2245 bool AArch64AsmParser::ParseDirective(AsmToken DirectiveID) {
2246 StringRef IDVal = DirectiveID.getIdentifier();
2247 if (IDVal == ".hword")
2248 return ParseDirectiveWord(2, DirectiveID.getLoc());
2249 else if (IDVal == ".word")
2250 return ParseDirectiveWord(4, DirectiveID.getLoc());
2251 else if (IDVal == ".xword")
2252 return ParseDirectiveWord(8, DirectiveID.getLoc());
2253 else if (IDVal == ".tlsdesccall")
2254 return ParseDirectiveTLSDescCall(DirectiveID.getLoc());
2259 /// parseDirectiveWord
2260 /// ::= .word [ expression (, expression)* ]
2261 bool AArch64AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
2262 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2264 const MCExpr *Value;
2265 if (getParser().parseExpression(Value))
2268 getParser().getStreamer().EmitValue(Value, Size);
2270 if (getLexer().is(AsmToken::EndOfStatement))
2273 // FIXME: Improve diagnostic.
2274 if (getLexer().isNot(AsmToken::Comma))
2275 return Error(L, "unexpected token in directive");
2284 // parseDirectiveTLSDescCall:
2285 // ::= .tlsdesccall symbol
2286 bool AArch64AsmParser::ParseDirectiveTLSDescCall(SMLoc L) {
2288 if (getParser().parseIdentifier(Name))
2289 return Error(L, "expected symbol after directive");
2291 MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
2292 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::Create(Sym, getContext());
2295 Inst.setOpcode(AArch64::TLSDESCCALL);
2296 Inst.addOperand(MCOperand::CreateExpr(Expr));
2298 getParser().getStreamer().EmitInstruction(Inst);
2303 bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
2304 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2305 MCStreamer &Out, unsigned &ErrorInfo,
2306 bool MatchingInlineAsm) {
2308 unsigned MatchResult;
2309 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
2312 if (ErrorInfo != ~0U && ErrorInfo >= Operands.size())
2313 return Error(IDLoc, "too few operands for instruction");
2315 switch (MatchResult) {
2318 if (validateInstruction(Inst, Operands))
2321 Out.EmitInstruction(Inst);
2323 case Match_MissingFeature:
2324 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
2326 case Match_InvalidOperand: {
2327 SMLoc ErrorLoc = IDLoc;
2328 if (ErrorInfo != ~0U) {
2329 ErrorLoc = ((AArch64Operand*)Operands[ErrorInfo])->getStartLoc();
2330 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
2333 return Error(ErrorLoc, "invalid operand for instruction");
2335 case Match_MnemonicFail:
2336 return Error(IDLoc, "invalid instruction");
2338 case Match_AddSubRegExtendSmall:
2339 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2340 "expected '[su]xt[bhw]' or 'lsl' with optional integer in range [0, 4]");
2341 case Match_AddSubRegExtendLarge:
2342 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2343 "expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]");
2344 case Match_AddSubRegShift32:
2345 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2346 "expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]");
2347 case Match_AddSubRegShift64:
2348 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2349 "expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 63]");
2350 case Match_AddSubSecondSource:
2351 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2352 "expected compatible register, symbol or integer in range [0, 4095]");
2353 case Match_CVTFixedPos32:
2354 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2355 "expected integer in range [1, 32]");
2356 case Match_CVTFixedPos64:
2357 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2358 "expected integer in range [1, 64]");
2359 case Match_CondCode:
2360 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2361 "expected AArch64 condition code");
2363 // Any situation which allows a nontrivial floating-point constant also
2364 // allows a register.
2365 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2366 "expected compatible register or floating-point constant");
2368 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2369 "expected floating-point constant #0.0 or invalid register type");
2371 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2372 "expected label or encodable integer pc offset");
2374 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2375 "expected lane specifier '[1]'");
2376 case Match_LoadStoreExtend32_1:
2377 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2378 "expected 'uxtw' or 'sxtw' with optional shift of #0");
2379 case Match_LoadStoreExtend32_2:
2380 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2381 "expected 'uxtw' or 'sxtw' with optional shift of #0 or #1");
2382 case Match_LoadStoreExtend32_4:
2383 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2384 "expected 'uxtw' or 'sxtw' with optional shift of #0 or #2");
2385 case Match_LoadStoreExtend32_8:
2386 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2387 "expected 'uxtw' or 'sxtw' with optional shift of #0 or #3");
2388 case Match_LoadStoreExtend32_16:
2389 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2390 "expected 'lsl' or 'sxtw' with optional shift of #0 or #4");
2391 case Match_LoadStoreExtend64_1:
2392 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2393 "expected 'lsl' or 'sxtx' with optional shift of #0");
2394 case Match_LoadStoreExtend64_2:
2395 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2396 "expected 'lsl' or 'sxtx' with optional shift of #0 or #1");
2397 case Match_LoadStoreExtend64_4:
2398 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2399 "expected 'lsl' or 'sxtx' with optional shift of #0 or #2");
2400 case Match_LoadStoreExtend64_8:
2401 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2402 "expected 'lsl' or 'sxtx' with optional shift of #0 or #3");
2403 case Match_LoadStoreExtend64_16:
2404 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2405 "expected 'lsl' or 'sxtx' with optional shift of #0 or #4");
2406 case Match_LoadStoreSImm7_4:
2407 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2408 "expected integer multiple of 4 in range [-256, 252]");
2409 case Match_LoadStoreSImm7_8:
2410 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2411 "expected integer multiple of 8 in range [-512, 508]");
2412 case Match_LoadStoreSImm7_16:
2413 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2414 "expected integer multiple of 16 in range [-1024, 1016]");
2415 case Match_LoadStoreSImm9:
2416 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2417 "expected integer in range [-256, 255]");
2418 case Match_LoadStoreUImm12_1:
2419 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2420 "expected symbolic reference or integer in range [0, 4095]");
2421 case Match_LoadStoreUImm12_2:
2422 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2423 "expected symbolic reference or integer in range [0, 8190]");
2424 case Match_LoadStoreUImm12_4:
2425 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2426 "expected symbolic reference or integer in range [0, 16380]");
2427 case Match_LoadStoreUImm12_8:
2428 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2429 "expected symbolic reference or integer in range [0, 32760]");
2430 case Match_LoadStoreUImm12_16:
2431 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2432 "expected symbolic reference or integer in range [0, 65520]");
2433 case Match_LogicalSecondSource:
2434 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2435 "expected compatible register or logical immediate");
2436 case Match_MOVWUImm16:
2437 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2438 "expected relocated symbol or integer in range [0, 65535]");
2440 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2441 "expected readable system register");
2443 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2444 "expected writable system register or pstate");
2445 case Match_NamedImm_at:
2446 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2447 "expected symbolic 'at' operand: s1e[0-3][rw] or s12e[01][rw]");
2448 case Match_NamedImm_dbarrier:
2449 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2450 "expected integer in range [0, 15] or symbolic barrier operand");
2451 case Match_NamedImm_dc:
2452 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2453 "expected symbolic 'dc' operand");
2454 case Match_NamedImm_ic:
2455 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2456 "expected 'ic' operand: 'ialluis', 'iallu' or 'ivau'");
2457 case Match_NamedImm_isb:
2458 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2459 "expected integer in range [0, 15] or 'sy'");
2460 case Match_NamedImm_prefetch:
2461 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2462 "expected prefetch hint: p(ld|st|i)l[123](strm|keep)");
2463 case Match_NamedImm_tlbi:
2464 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2465 "expected translation buffer invalidation operand");
2467 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2468 "expected integer in range [0, 65535]");
2470 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2471 "expected integer in range [0, 7]");
2473 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2474 "expected integer in range [0, 15]");
2476 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2477 "expected integer in range [0, 31]");
2479 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2480 "expected integer in range [0, 63]");
2482 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2483 "expected integer in range [0, 127]");
2485 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2486 "expected integer in range [<lsb>, 31]");
2488 return Error(((AArch64Operand*)Operands[ErrorInfo])->getStartLoc(),
2489 "expected integer in range [<lsb>, 63]");
2491 return Error(((AArch64Operand *)Operands[ErrorInfo])->getStartLoc(),
2492 "expected integer in range [1, 8]");
2493 case Match_ShrImm16:
2494 return Error(((AArch64Operand *)Operands[ErrorInfo])->getStartLoc(),
2495 "expected integer in range [1, 16]");
2496 case Match_ShrImm32:
2497 return Error(((AArch64Operand *)Operands[ErrorInfo])->getStartLoc(),
2498 "expected integer in range [1, 32]");
2499 case Match_ShrImm64:
2500 return Error(((AArch64Operand *)Operands[ErrorInfo])->getStartLoc(),
2501 "expected integer in range [1, 64]");
2503 return Error(((AArch64Operand *)Operands[ErrorInfo])->getStartLoc(),
2504 "expected integer in range [0, 7]");
2505 case Match_ShlImm16:
2506 return Error(((AArch64Operand *)Operands[ErrorInfo])->getStartLoc(),
2507 "expected integer in range [0, 15]");
2508 case Match_ShlImm32:
2509 return Error(((AArch64Operand *)Operands[ErrorInfo])->getStartLoc(),
2510 "expected integer in range [0, 31]");
2511 case Match_ShlImm64:
2512 return Error(((AArch64Operand *)Operands[ErrorInfo])->getStartLoc(),
2513 "expected integer in range [0, 63]");
2516 llvm_unreachable("Implement any new match types added!");
2520 void AArch64Operand::print(raw_ostream &OS) const {
2523 OS << "<CondCode: " << CondCode.Code << ">";
2526 OS << "<fpimm: " << FPImm.Val << ">";
2529 OS << "<immwithlsl: imm=" << ImmWithLSL.Val
2530 << ", shift=" << ImmWithLSL.ShiftAmount << ">";
2533 getImm()->print(OS);
2536 OS << "<register " << getReg() << '>';
2539 OS << '\'' << getToken() << '\'';
2542 OS << "<shift: type=" << ShiftExtend.ShiftType
2543 << ", amount=" << ShiftExtend.Amount << ">";
2546 StringRef Name(SysReg.Data, SysReg.Length);
2547 OS << "<sysreg: " << Name << '>';
2551 llvm_unreachable("No idea how to print this kind of operand");
2556 void AArch64Operand::dump() const {
2561 /// Force static initialization.
2562 extern "C" void LLVMInitializeAArch64AsmParser() {
2563 RegisterMCAsmParser<AArch64AsmParser> X(TheAArch64Target);
2566 #define GET_REGISTER_MATCHER
2567 #define GET_MATCHER_IMPLEMENTATION
2568 #include "AArch64GenAsmMatcher.inc"