1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the AArch64 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef AArch64SUBTARGET_H
15 #define AArch64SUBTARGET_H
17 #include "AArch64InstrInfo.h"
18 #include "AArch64FrameLowering.h"
19 #include "AArch64RegisterInfo.h"
20 #include "AArch64SelectionDAGInfo.h"
21 #include "llvm/IR/DataLayout.h"
22 #include "llvm/Target/TargetSubtargetInfo.h"
25 #define GET_SUBTARGETINFO_HEADER
26 #include "AArch64GenSubtargetInfo.inc"
32 class AArch64Subtarget : public AArch64GenSubtargetInfo {
34 enum ARMProcFamilyEnum {Others, CortexA53, CortexA57, Cyclone};
36 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
37 ARMProcFamilyEnum ARMProcFamily;
44 // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
45 bool HasZeroCycleRegMove;
47 // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
48 bool HasZeroCycleZeroing;
50 /// CPUString - String name of used CPU.
51 std::string CPUString;
53 /// TargetTriple - What processor and OS we're targeting.
57 AArch64FrameLowering FrameLowering;
58 AArch64InstrInfo InstrInfo;
59 AArch64SelectionDAGInfo TSInfo;
62 /// This constructor initializes the data members to match that
63 /// of the specified triple.
64 AArch64Subtarget(const std::string &TT, const std::string &CPU,
65 const std::string &FS, bool LittleEndian);
67 const AArch64SelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; }
68 const AArch64FrameLowering *getFrameLowering() const {
69 return &FrameLowering;
71 const AArch64InstrInfo *getInstrInfo() const { return &InstrInfo; }
72 const DataLayout *getDataLayout() const { return &DL; }
73 bool enableMachineScheduler() const override { return true; }
75 bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
77 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
79 bool hasFPARMv8() const { return HasFPARMv8; }
80 bool hasNEON() const { return HasNEON; }
81 bool hasCrypto() const { return HasCrypto; }
82 bool hasCRC() const { return HasCRC; }
84 bool isLittleEndian() const { return DL.isLittleEndian(); }
86 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
88 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
90 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
92 bool isCyclone() const { return CPUString == "cyclone"; }
94 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
95 /// that still makes it profitable to inline the call.
96 unsigned getMaxInlineSizeThreshold() const { return 64; }
98 /// ParseSubtargetFeatures - Parses features string setting specified
99 /// subtarget options. Definition of function is auto generated by tblgen.
100 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
102 /// ClassifyGlobalReference - Find the target operand flags that describe
103 /// how a global value should be referenced for the current subtarget.
104 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
105 const TargetMachine &TM) const;
107 /// This function returns the name of a function which has an interface
108 /// like the non-standard bzero function, if such a function exists on
109 /// the current subtarget and it is considered prefereable over
110 /// memset with zero passed as the second argument. Otherwise it
112 const char *getBZeroEntry() const;
114 void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin,
116 unsigned NumRegionInstrs) const override;
118 bool enableEarlyIfConversion() const override;
120 } // End llvm namespace
122 #endif // AArch64SUBTARGET_H