1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the AArch64 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
17 #include "AArch64FrameLowering.h"
18 #include "AArch64ISelLowering.h"
19 #include "AArch64InstrInfo.h"
20 #include "AArch64RegisterInfo.h"
21 #include "AArch64SelectionDAGInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
26 #define GET_SUBTARGETINFO_HEADER
27 #include "AArch64GenSubtargetInfo.inc"
34 class AArch64Subtarget : public AArch64GenSubtargetInfo {
36 enum ARMProcFamilyEnum {Others, CortexA53, CortexA57, Cyclone};
38 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
39 ARMProcFamilyEnum ARMProcFamily;
51 // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
52 bool HasZeroCycleRegMove;
54 // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
55 bool HasZeroCycleZeroing;
57 // StrictAlign - Disallow unaligned memory accesses.
60 // ReserveX18 - X18 is not available as a general purpose register.
65 /// CPUString - String name of used CPU.
66 std::string CPUString;
68 /// TargetTriple - What processor and OS we're targeting.
71 AArch64FrameLowering FrameLowering;
72 AArch64InstrInfo InstrInfo;
73 AArch64SelectionDAGInfo TSInfo;
74 AArch64TargetLowering TLInfo;
76 /// initializeSubtargetDependencies - Initializes using CPUString and the
77 /// passed in feature string so that we can use initializer lists for
78 /// subtarget initialization.
79 AArch64Subtarget &initializeSubtargetDependencies(StringRef FS);
82 /// This constructor initializes the data members to match that
83 /// of the specified triple.
84 AArch64Subtarget(const Triple &TT, const std::string &CPU,
85 const std::string &FS, const TargetMachine &TM,
88 const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
91 const AArch64FrameLowering *getFrameLowering() const override {
92 return &FrameLowering;
94 const AArch64TargetLowering *getTargetLowering() const override {
97 const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
98 const AArch64RegisterInfo *getRegisterInfo() const override {
99 return &getInstrInfo()->getRegisterInfo();
101 const Triple &getTargetTriple() const { return TargetTriple; }
102 bool enableMachineScheduler() const override { return true; }
103 bool enablePostRAScheduler() const override {
104 return isCortexA53() || isCortexA57();
107 bool hasV8_1aOps() const { return HasV8_1aOps; }
108 bool hasV8_2aOps() const { return HasV8_2aOps; }
110 bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
112 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
114 bool requiresStrictAlign() const { return StrictAlign; }
116 bool isX18Reserved() const { return ReserveX18; }
117 bool hasFPARMv8() const { return HasFPARMv8; }
118 bool hasNEON() const { return HasNEON; }
119 bool hasCrypto() const { return HasCrypto; }
120 bool hasCRC() const { return HasCRC; }
121 /// CPU has TBI (top byte of addresses is ignored during HW address
122 /// translation) and OS enables it.
123 bool supportsAddressTopByteIgnored() const;
125 bool hasPerfMon() const { return HasPerfMon; }
126 bool hasFullFP16() const { return HasFullFP16; }
128 bool isLittleEndian() const { return IsLittle; }
130 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
131 bool isTargetIOS() const { return TargetTriple.isiOS(); }
132 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
133 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
134 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
136 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
137 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
138 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
140 bool isCyclone() const { return CPUString == "cyclone"; }
141 bool isCortexA57() const { return CPUString == "cortex-a57"; }
142 bool isCortexA53() const { return CPUString == "cortex-a53"; }
144 bool useAA() const override { return isCortexA53(); }
146 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
147 /// that still makes it profitable to inline the call.
148 unsigned getMaxInlineSizeThreshold() const { return 64; }
150 /// ParseSubtargetFeatures - Parses features string setting specified
151 /// subtarget options. Definition of function is auto generated by tblgen.
152 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
154 /// ClassifyGlobalReference - Find the target operand flags that describe
155 /// how a global value should be referenced for the current subtarget.
156 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
157 const TargetMachine &TM) const;
159 /// This function returns the name of a function which has an interface
160 /// like the non-standard bzero function, if such a function exists on
161 /// the current subtarget and it is considered prefereable over
162 /// memset with zero passed as the second argument. Otherwise it
164 const char *getBZeroEntry() const;
166 void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin,
168 unsigned NumRegionInstrs) const override;
170 bool enableEarlyIfConversion() const override;
172 std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
174 } // End llvm namespace