1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the AArch64 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
17 #include "AArch64FrameLowering.h"
18 #include "AArch64ISelLowering.h"
19 #include "AArch64InstrInfo.h"
20 #include "AArch64RegisterInfo.h"
21 #include "AArch64SelectionDAGInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
26 #define GET_SUBTARGETINFO_HEADER
27 #include "AArch64GenSubtargetInfo.inc"
34 class AArch64Subtarget : public AArch64GenSubtargetInfo {
36 enum ARMProcFamilyEnum {Others, CortexA53, CortexA57, Cyclone};
38 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
39 ARMProcFamilyEnum ARMProcFamily;
52 // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
53 bool HasZeroCycleRegMove;
55 // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
56 bool HasZeroCycleZeroing;
58 // StrictAlign - Disallow unaligned memory accesses.
61 // ReserveX18 - X18 is not available as a general purpose register.
66 /// CPUString - String name of used CPU.
67 std::string CPUString;
69 /// TargetTriple - What processor and OS we're targeting.
72 AArch64FrameLowering FrameLowering;
73 AArch64InstrInfo InstrInfo;
74 AArch64SelectionDAGInfo TSInfo;
75 AArch64TargetLowering TLInfo;
77 /// initializeSubtargetDependencies - Initializes using CPUString and the
78 /// passed in feature string so that we can use initializer lists for
79 /// subtarget initialization.
80 AArch64Subtarget &initializeSubtargetDependencies(StringRef FS);
83 /// This constructor initializes the data members to match that
84 /// of the specified triple.
85 AArch64Subtarget(const Triple &TT, const std::string &CPU,
86 const std::string &FS, const TargetMachine &TM,
89 const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
92 const AArch64FrameLowering *getFrameLowering() const override {
93 return &FrameLowering;
95 const AArch64TargetLowering *getTargetLowering() const override {
98 const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
99 const AArch64RegisterInfo *getRegisterInfo() const override {
100 return &getInstrInfo()->getRegisterInfo();
102 const Triple &getTargetTriple() const { return TargetTriple; }
103 bool enableMachineScheduler() const override { return true; }
104 bool enablePostRAScheduler() const override {
105 return isCortexA53() || isCortexA57();
108 bool hasV8_1aOps() const { return HasV8_1aOps; }
109 bool hasV8_2aOps() const { return HasV8_2aOps; }
111 bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
113 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
115 bool requiresStrictAlign() const { return StrictAlign; }
117 bool isX18Reserved() const { return ReserveX18; }
118 bool hasFPARMv8() const { return HasFPARMv8; }
119 bool hasNEON() const { return HasNEON; }
120 bool hasCrypto() const { return HasCrypto; }
121 bool hasCRC() const { return HasCRC; }
122 /// CPU has TBI (top byte of addresses is ignored during HW address
123 /// translation) and OS enables it.
124 bool supportsAddressTopByteIgnored() const;
126 bool hasPerfMon() const { return HasPerfMon; }
127 bool hasFullFP16() const { return HasFullFP16; }
128 bool hasSPE() const { return HasSPE; }
130 bool isLittleEndian() const { return IsLittle; }
132 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
133 bool isTargetIOS() const { return TargetTriple.isiOS(); }
134 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
135 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
136 bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
138 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
139 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
140 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
142 bool isCyclone() const { return CPUString == "cyclone"; }
143 bool isCortexA57() const { return CPUString == "cortex-a57"; }
144 bool isCortexA53() const { return CPUString == "cortex-a53"; }
146 bool useAA() const override { return isCortexA53(); }
148 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
149 /// that still makes it profitable to inline the call.
150 unsigned getMaxInlineSizeThreshold() const { return 64; }
152 /// ParseSubtargetFeatures - Parses features string setting specified
153 /// subtarget options. Definition of function is auto generated by tblgen.
154 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
156 /// ClassifyGlobalReference - Find the target operand flags that describe
157 /// how a global value should be referenced for the current subtarget.
158 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
159 const TargetMachine &TM) const;
161 /// This function returns the name of a function which has an interface
162 /// like the non-standard bzero function, if such a function exists on
163 /// the current subtarget and it is considered prefereable over
164 /// memset with zero passed as the second argument. Otherwise it
166 const char *getBZeroEntry() const;
168 void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin,
170 unsigned NumRegionInstrs) const override;
172 bool enableEarlyIfConversion() const override;
174 std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
176 } // End llvm namespace