1 //===-- AArch64InstrNEON.td - NEON support for AArch64 -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the AArch64 NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
17 def Neon_bsl : SDNode<"AArch64ISD::NEON_BSL", SDTypeProfile<1, 3,
18 [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
19 SDTCisSameAs<0, 3>]>>;
21 // (outs Result), (ins Imm, OpCmode)
22 def SDT_Neon_movi : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
24 def Neon_movi : SDNode<"AArch64ISD::NEON_MOVIMM", SDT_Neon_movi>;
26 def Neon_mvni : SDNode<"AArch64ISD::NEON_MVNIMM", SDT_Neon_movi>;
28 // (outs Result), (ins Imm)
29 def Neon_fmovi : SDNode<"AArch64ISD::NEON_FMOVIMM", SDTypeProfile<1, 1,
30 [SDTCisVec<0>, SDTCisVT<1, i32>]>>;
32 // (outs Result), (ins LHS, RHS, CondCode)
33 def Neon_cmp : SDNode<"AArch64ISD::NEON_CMP", SDTypeProfile<1, 3,
34 [SDTCisVec<0>, SDTCisSameAs<1, 2>]>>;
36 // (outs Result), (ins LHS, 0/0.0 constant, CondCode)
37 def Neon_cmpz : SDNode<"AArch64ISD::NEON_CMPZ", SDTypeProfile<1, 3,
38 [SDTCisVec<0>, SDTCisVec<1>]>>;
40 // (outs Result), (ins LHS, RHS)
41 def Neon_tst : SDNode<"AArch64ISD::NEON_TST", SDTypeProfile<1, 2,
42 [SDTCisVec<0>, SDTCisSameAs<1, 2>]>>;
44 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
46 def Neon_sqrshlImm : SDNode<"AArch64ISD::NEON_QSHLs", SDTARMVSH>;
47 def Neon_uqrshlImm : SDNode<"AArch64ISD::NEON_QSHLu", SDTARMVSH>;
49 def SDTPERMUTE : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
51 def Neon_uzp1 : SDNode<"AArch64ISD::NEON_UZP1", SDTPERMUTE>;
52 def Neon_uzp2 : SDNode<"AArch64ISD::NEON_UZP2", SDTPERMUTE>;
53 def Neon_zip1 : SDNode<"AArch64ISD::NEON_ZIP1", SDTPERMUTE>;
54 def Neon_zip2 : SDNode<"AArch64ISD::NEON_ZIP2", SDTPERMUTE>;
55 def Neon_trn1 : SDNode<"AArch64ISD::NEON_TRN1", SDTPERMUTE>;
56 def Neon_trn2 : SDNode<"AArch64ISD::NEON_TRN2", SDTPERMUTE>;
58 def SDTVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
59 def Neon_rev64 : SDNode<"AArch64ISD::NEON_REV64", SDTVSHUF>;
60 def Neon_rev32 : SDNode<"AArch64ISD::NEON_REV32", SDTVSHUF>;
61 def Neon_rev16 : SDNode<"AArch64ISD::NEON_REV16", SDTVSHUF>;
62 def Neon_vdup : SDNode<"AArch64ISD::NEON_VDUP", SDTypeProfile<1, 1,
64 def Neon_vduplane : SDNode<"AArch64ISD::NEON_VDUPLANE", SDTypeProfile<1, 2,
65 [SDTCisVec<0>, SDTCisVec<1>, SDTCisVT<2, i64>]>>;
66 def Neon_vextract : SDNode<"AArch64ISD::NEON_VEXTRACT", SDTypeProfile<1, 3,
67 [SDTCisVec<0>, SDTCisSameAs<0, 1>,
68 SDTCisSameAs<0, 2>, SDTCisVT<3, i64>]>>;
70 def SDT_assertext : SDTypeProfile<1, 1,
71 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
72 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
73 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
75 //===----------------------------------------------------------------------===//
77 //===----------------------------------------------------------------------===//
79 multiclass NeonI_3VSame_B_sizes<bit u, bits<2> size, bits<5> opcode,
80 string asmop, SDPatternOperator opnode8B,
81 SDPatternOperator opnode16B,
83 let isCommutable = Commutable in {
84 def _8B : NeonI_3VSame<0b0, u, size, opcode,
85 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
86 asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
87 [(set (v8i8 VPR64:$Rd),
88 (v8i8 (opnode8B (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
91 def _16B : NeonI_3VSame<0b1, u, size, opcode,
92 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
93 asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
94 [(set (v16i8 VPR128:$Rd),
95 (v16i8 (opnode16B (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
101 multiclass NeonI_3VSame_HS_sizes<bit u, bits<5> opcode,
102 string asmop, SDPatternOperator opnode,
103 bit Commutable = 0> {
104 let isCommutable = Commutable in {
105 def _4H : NeonI_3VSame<0b0, u, 0b01, opcode,
106 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
107 asmop # "\t$Rd.4h, $Rn.4h, $Rm.4h",
108 [(set (v4i16 VPR64:$Rd),
109 (v4i16 (opnode (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))))],
112 def _8H : NeonI_3VSame<0b1, u, 0b01, opcode,
113 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
114 asmop # "\t$Rd.8h, $Rn.8h, $Rm.8h",
115 [(set (v8i16 VPR128:$Rd),
116 (v8i16 (opnode (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))))],
119 def _2S : NeonI_3VSame<0b0, u, 0b10, opcode,
120 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
121 asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
122 [(set (v2i32 VPR64:$Rd),
123 (v2i32 (opnode (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))))],
126 def _4S : NeonI_3VSame<0b1, u, 0b10, opcode,
127 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
128 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
129 [(set (v4i32 VPR128:$Rd),
130 (v4i32 (opnode (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))))],
134 multiclass NeonI_3VSame_BHS_sizes<bit u, bits<5> opcode,
135 string asmop, SDPatternOperator opnode,
137 : NeonI_3VSame_HS_sizes<u, opcode, asmop, opnode, Commutable> {
138 let isCommutable = Commutable in {
139 def _8B : NeonI_3VSame<0b0, u, 0b00, opcode,
140 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
141 asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
142 [(set (v8i8 VPR64:$Rd),
143 (v8i8 (opnode (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
146 def _16B : NeonI_3VSame<0b1, u, 0b00, opcode,
147 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
148 asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
149 [(set (v16i8 VPR128:$Rd),
150 (v16i8 (opnode (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
155 multiclass NeonI_3VSame_BHSD_sizes<bit u, bits<5> opcode,
156 string asmop, SDPatternOperator opnode,
158 : NeonI_3VSame_BHS_sizes<u, opcode, asmop, opnode, Commutable> {
159 let isCommutable = Commutable in {
160 def _2D : NeonI_3VSame<0b1, u, 0b11, opcode,
161 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
162 asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
163 [(set (v2i64 VPR128:$Rd),
164 (v2i64 (opnode (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))))],
169 // Multiclass NeonI_3VSame_SD_sizes: Operand types are floating point types,
170 // but Result types can be integer or floating point types.
171 multiclass NeonI_3VSame_SD_sizes<bit u, bit size, bits<5> opcode,
172 string asmop, SDPatternOperator opnode2S,
173 SDPatternOperator opnode4S,
174 SDPatternOperator opnode2D,
175 ValueType ResTy2S, ValueType ResTy4S,
176 ValueType ResTy2D, bit Commutable = 0> {
177 let isCommutable = Commutable in {
178 def _2S : NeonI_3VSame<0b0, u, {size, 0b0}, opcode,
179 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
180 asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
181 [(set (ResTy2S VPR64:$Rd),
182 (ResTy2S (opnode2S (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
185 def _4S : NeonI_3VSame<0b1, u, {size, 0b0}, opcode,
186 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
187 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
188 [(set (ResTy4S VPR128:$Rd),
189 (ResTy4S (opnode4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
192 def _2D : NeonI_3VSame<0b1, u, {size, 0b1}, opcode,
193 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
194 asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
195 [(set (ResTy2D VPR128:$Rd),
196 (ResTy2D (opnode2D (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))))],
201 //===----------------------------------------------------------------------===//
202 // Instruction Definitions
203 //===----------------------------------------------------------------------===//
205 // Vector Arithmetic Instructions
207 // Vector Add (Integer and Floating-Point)
209 defm ADDvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b10000, "add", add, 1>;
210 defm FADDvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11010, "fadd", fadd, fadd, fadd,
211 v2f32, v4f32, v2f64, 1>;
213 // Vector Sub (Integer and Floating-Point)
215 defm SUBvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10000, "sub", sub, 0>;
216 defm FSUBvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11010, "fsub", fsub, fsub, fsub,
217 v2f32, v4f32, v2f64, 0>;
219 // Vector Multiply (Integer and Floating-Point)
221 defm MULvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10011, "mul", mul, 1>;
222 defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul, fmul, fmul,
223 v2f32, v4f32, v2f64, 1>;
225 // Vector Multiply (Polynomial)
227 defm PMULvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b10011, "pmul",
228 int_arm_neon_vmulp, int_arm_neon_vmulp, 1>;
230 // Vector Multiply-accumulate and Multiply-subtract (Integer)
232 // class NeonI_3VSame_Constraint_impl: NeonI_3VSame with no data type and
233 // two operands constraints.
234 class NeonI_3VSame_Constraint_impl<string asmop, string asmlane,
235 RegisterOperand VPRC, ValueType OpTy, bit q, bit u, bits<2> size,
236 bits<5> opcode, SDPatternOperator opnode>
237 : NeonI_3VSame<q, u, size, opcode,
238 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, VPRC:$Rm),
239 asmop # "\t$Rd" # asmlane # ", $Rn" # asmlane # ", $Rm" # asmlane,
240 [(set (OpTy VPRC:$Rd),
241 (OpTy (opnode (OpTy VPRC:$src), (OpTy VPRC:$Rn), (OpTy VPRC:$Rm))))],
243 let Constraints = "$src = $Rd";
246 def Neon_mla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
247 (add node:$Ra, (mul node:$Rn, node:$Rm))>;
249 def Neon_mls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
250 (sub node:$Ra, (mul node:$Rn, node:$Rm))>;
253 def MLAvvv_8B: NeonI_3VSame_Constraint_impl<"mla", ".8b", VPR64, v8i8,
254 0b0, 0b0, 0b00, 0b10010, Neon_mla>;
255 def MLAvvv_16B: NeonI_3VSame_Constraint_impl<"mla", ".16b", VPR128, v16i8,
256 0b1, 0b0, 0b00, 0b10010, Neon_mla>;
257 def MLAvvv_4H: NeonI_3VSame_Constraint_impl<"mla", ".4h", VPR64, v4i16,
258 0b0, 0b0, 0b01, 0b10010, Neon_mla>;
259 def MLAvvv_8H: NeonI_3VSame_Constraint_impl<"mla", ".8h", VPR128, v8i16,
260 0b1, 0b0, 0b01, 0b10010, Neon_mla>;
261 def MLAvvv_2S: NeonI_3VSame_Constraint_impl<"mla", ".2s", VPR64, v2i32,
262 0b0, 0b0, 0b10, 0b10010, Neon_mla>;
263 def MLAvvv_4S: NeonI_3VSame_Constraint_impl<"mla", ".4s", VPR128, v4i32,
264 0b1, 0b0, 0b10, 0b10010, Neon_mla>;
266 def MLSvvv_8B: NeonI_3VSame_Constraint_impl<"mls", ".8b", VPR64, v8i8,
267 0b0, 0b1, 0b00, 0b10010, Neon_mls>;
268 def MLSvvv_16B: NeonI_3VSame_Constraint_impl<"mls", ".16b", VPR128, v16i8,
269 0b1, 0b1, 0b00, 0b10010, Neon_mls>;
270 def MLSvvv_4H: NeonI_3VSame_Constraint_impl<"mls", ".4h", VPR64, v4i16,
271 0b0, 0b1, 0b01, 0b10010, Neon_mls>;
272 def MLSvvv_8H: NeonI_3VSame_Constraint_impl<"mls", ".8h", VPR128, v8i16,
273 0b1, 0b1, 0b01, 0b10010, Neon_mls>;
274 def MLSvvv_2S: NeonI_3VSame_Constraint_impl<"mls", ".2s", VPR64, v2i32,
275 0b0, 0b1, 0b10, 0b10010, Neon_mls>;
276 def MLSvvv_4S: NeonI_3VSame_Constraint_impl<"mls", ".4s", VPR128, v4i32,
277 0b1, 0b1, 0b10, 0b10010, Neon_mls>;
279 // Vector Multiply-accumulate and Multiply-subtract (Floating Point)
281 def Neon_fmla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
282 (fadd node:$Ra, (fmul node:$Rn, node:$Rm))>;
284 def Neon_fmls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
285 (fsub node:$Ra, (fmul node:$Rn, node:$Rm))>;
287 let Predicates = [HasNEON, UseFusedMAC] in {
288 def FMLAvvv_2S: NeonI_3VSame_Constraint_impl<"fmla", ".2s", VPR64, v2f32,
289 0b0, 0b0, 0b00, 0b11001, Neon_fmla>;
290 def FMLAvvv_4S: NeonI_3VSame_Constraint_impl<"fmla", ".4s", VPR128, v4f32,
291 0b1, 0b0, 0b00, 0b11001, Neon_fmla>;
292 def FMLAvvv_2D: NeonI_3VSame_Constraint_impl<"fmla", ".2d", VPR128, v2f64,
293 0b1, 0b0, 0b01, 0b11001, Neon_fmla>;
295 def FMLSvvv_2S: NeonI_3VSame_Constraint_impl<"fmls", ".2s", VPR64, v2f32,
296 0b0, 0b0, 0b10, 0b11001, Neon_fmls>;
297 def FMLSvvv_4S: NeonI_3VSame_Constraint_impl<"fmls", ".4s", VPR128, v4f32,
298 0b1, 0b0, 0b10, 0b11001, Neon_fmls>;
299 def FMLSvvv_2D: NeonI_3VSame_Constraint_impl<"fmls", ".2d", VPR128, v2f64,
300 0b1, 0b0, 0b11, 0b11001, Neon_fmls>;
303 // We're also allowed to match the fma instruction regardless of compile
305 def : Pat<(v2f32 (fma VPR64:$Rn, VPR64:$Rm, VPR64:$Ra)),
306 (FMLAvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
307 def : Pat<(v4f32 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
308 (FMLAvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
309 def : Pat<(v2f64 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
310 (FMLAvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
312 def : Pat<(v2f32 (fma (fneg VPR64:$Rn), VPR64:$Rm, VPR64:$Ra)),
313 (FMLSvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
314 def : Pat<(v4f32 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
315 (FMLSvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
316 def : Pat<(v2f64 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
317 (FMLSvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
319 // Vector Divide (Floating-Point)
321 defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv, fdiv, fdiv,
322 v2f32, v4f32, v2f64, 0>;
324 // Vector Bitwise Operations
326 // Vector Bitwise AND
328 defm ANDvvv : NeonI_3VSame_B_sizes<0b0, 0b00, 0b00011, "and", and, and, 1>;
330 // Vector Bitwise Exclusive OR
332 defm EORvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b00011, "eor", xor, xor, 1>;
336 defm ORRvvv : NeonI_3VSame_B_sizes<0b0, 0b10, 0b00011, "orr", or, or, 1>;
338 // ORR disassembled as MOV if Vn==Vm
340 // Vector Move - register
341 // Alias for ORR if Vn=Vm.
342 // FIXME: This is actually the preferred syntax but TableGen can't deal with
343 // custom printing of aliases.
344 def : NeonInstAlias<"mov $Rd.8b, $Rn.8b",
345 (ORRvvv_8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rn), 0>;
346 def : NeonInstAlias<"mov $Rd.16b, $Rn.16b",
347 (ORRvvv_16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rn), 0>;
349 // The MOVI instruction takes two immediate operands. The first is the
350 // immediate encoding, while the second is the cmode. A cmode of 14, or
351 // 0b1110, produces a MOVI operation, rather than a MVNI, ORR, or BIC.
352 def Neon_AllZero : PatFrag<(ops), (Neon_movi (i32 0), (i32 14))>;
353 def Neon_AllOne : PatFrag<(ops), (Neon_movi (i32 255), (i32 14))>;
355 def Neon_not8B : PatFrag<(ops node:$in),
356 (xor node:$in, (bitconvert (v8i8 Neon_AllOne)))>;
357 def Neon_not16B : PatFrag<(ops node:$in),
358 (xor node:$in, (bitconvert (v16i8 Neon_AllOne)))>;
360 def Neon_orn8B : PatFrag<(ops node:$Rn, node:$Rm),
361 (or node:$Rn, (Neon_not8B node:$Rm))>;
363 def Neon_orn16B : PatFrag<(ops node:$Rn, node:$Rm),
364 (or node:$Rn, (Neon_not16B node:$Rm))>;
366 def Neon_bic8B : PatFrag<(ops node:$Rn, node:$Rm),
367 (and node:$Rn, (Neon_not8B node:$Rm))>;
369 def Neon_bic16B : PatFrag<(ops node:$Rn, node:$Rm),
370 (and node:$Rn, (Neon_not16B node:$Rm))>;
373 // Vector Bitwise OR NOT - register
375 defm ORNvvv : NeonI_3VSame_B_sizes<0b0, 0b11, 0b00011, "orn",
376 Neon_orn8B, Neon_orn16B, 0>;
378 // Vector Bitwise Bit Clear (AND NOT) - register
380 defm BICvvv : NeonI_3VSame_B_sizes<0b0, 0b01, 0b00011, "bic",
381 Neon_bic8B, Neon_bic16B, 0>;
383 multiclass Neon_bitwise2V_patterns<SDPatternOperator opnode8B,
384 SDPatternOperator opnode16B,
386 Instruction INST16B> {
387 def : Pat<(v2i32 (opnode8B VPR64:$Rn, VPR64:$Rm)),
388 (INST8B VPR64:$Rn, VPR64:$Rm)>;
389 def : Pat<(v4i16 (opnode8B VPR64:$Rn, VPR64:$Rm)),
390 (INST8B VPR64:$Rn, VPR64:$Rm)>;
391 def : Pat<(v1i64 (opnode8B VPR64:$Rn, VPR64:$Rm)),
392 (INST8B VPR64:$Rn, VPR64:$Rm)>;
393 def : Pat<(v4i32 (opnode16B VPR128:$Rn, VPR128:$Rm)),
394 (INST16B VPR128:$Rn, VPR128:$Rm)>;
395 def : Pat<(v8i16 (opnode16B VPR128:$Rn, VPR128:$Rm)),
396 (INST16B VPR128:$Rn, VPR128:$Rm)>;
397 def : Pat<(v2i64 (opnode16B VPR128:$Rn, VPR128:$Rm)),
398 (INST16B VPR128:$Rn, VPR128:$Rm)>;
401 // Additional patterns for bitwise instructions AND, EOR, ORR, BIC, ORN
402 defm : Neon_bitwise2V_patterns<and, and, ANDvvv_8B, ANDvvv_16B>;
403 defm : Neon_bitwise2V_patterns<or, or, ORRvvv_8B, ORRvvv_16B>;
404 defm : Neon_bitwise2V_patterns<xor, xor, EORvvv_8B, EORvvv_16B>;
405 defm : Neon_bitwise2V_patterns<Neon_bic8B, Neon_bic16B, BICvvv_8B, BICvvv_16B>;
406 defm : Neon_bitwise2V_patterns<Neon_orn8B, Neon_orn16B, ORNvvv_8B, ORNvvv_16B>;
408 // Vector Bitwise Select
409 def BSLvvv_8B : NeonI_3VSame_Constraint_impl<"bsl", ".8b", VPR64, v8i8,
410 0b0, 0b1, 0b01, 0b00011, Neon_bsl>;
412 def BSLvvv_16B : NeonI_3VSame_Constraint_impl<"bsl", ".16b", VPR128, v16i8,
413 0b1, 0b1, 0b01, 0b00011, Neon_bsl>;
415 multiclass Neon_bitwise3V_patterns<SDPatternOperator opnode,
417 Instruction INST16B> {
418 // Disassociate type from instruction definition
419 def : Pat<(v2i32 (opnode VPR64:$src,VPR64:$Rn, VPR64:$Rm)),
420 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
421 def : Pat<(v4i16 (opnode VPR64:$src, VPR64:$Rn, VPR64:$Rm)),
422 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
423 def : Pat<(v1i64 (opnode VPR64:$src, VPR64:$Rn, VPR64:$Rm)),
424 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
425 def : Pat<(v4i32 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
426 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
427 def : Pat<(v8i16 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
428 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
429 def : Pat<(v2i64 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
430 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
432 // Allow to match BSL instruction pattern with non-constant operand
433 def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
434 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
435 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
436 def : Pat<(v4i16 (or (and VPR64:$Rn, VPR64:$Rd),
437 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
438 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
439 def : Pat<(v2i32 (or (and VPR64:$Rn, VPR64:$Rd),
440 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
441 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
442 def : Pat<(v1i64 (or (and VPR64:$Rn, VPR64:$Rd),
443 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
444 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
445 def : Pat<(v16i8 (or (and VPR128:$Rn, VPR128:$Rd),
446 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
447 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
448 def : Pat<(v8i16 (or (and VPR128:$Rn, VPR128:$Rd),
449 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
450 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
451 def : Pat<(v4i32 (or (and VPR128:$Rn, VPR128:$Rd),
452 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
453 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
454 def : Pat<(v2i64 (or (and VPR128:$Rn, VPR128:$Rd),
455 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
456 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
458 // Allow to match llvm.arm.* intrinsics.
459 def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 VPR64:$src),
460 (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
461 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
462 def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 VPR64:$src),
463 (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
464 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
465 def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 VPR64:$src),
466 (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
467 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
468 def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 VPR64:$src),
469 (v1i64 VPR64:$Rn), (v1i64 VPR64:$Rm))),
470 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
471 def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 VPR64:$src),
472 (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
473 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
474 def : Pat<(v1f64 (int_arm_neon_vbsl (v1f64 VPR64:$src),
475 (v1f64 VPR64:$Rn), (v1f64 VPR64:$Rm))),
476 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
477 def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 VPR128:$src),
478 (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
479 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
480 def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 VPR128:$src),
481 (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
482 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
483 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 VPR128:$src),
484 (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
485 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
486 def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 VPR128:$src),
487 (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
488 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
489 def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 VPR128:$src),
490 (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
491 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
492 def : Pat<(v2f64 (int_arm_neon_vbsl (v2f64 VPR128:$src),
493 (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
494 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
497 // Additional patterns for bitwise instruction BSL
498 defm: Neon_bitwise3V_patterns<Neon_bsl, BSLvvv_8B, BSLvvv_16B>;
500 def Neon_NoBSLop : PatFrag<(ops node:$src, node:$Rn, node:$Rm),
501 (Neon_bsl node:$src, node:$Rn, node:$Rm),
502 [{ (void)N; return false; }]>;
504 // Vector Bitwise Insert if True
506 def BITvvv_8B : NeonI_3VSame_Constraint_impl<"bit", ".8b", VPR64, v8i8,
507 0b0, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
508 def BITvvv_16B : NeonI_3VSame_Constraint_impl<"bit", ".16b", VPR128, v16i8,
509 0b1, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
511 // Vector Bitwise Insert if False
513 def BIFvvv_8B : NeonI_3VSame_Constraint_impl<"bif", ".8b", VPR64, v8i8,
514 0b0, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
515 def BIFvvv_16B : NeonI_3VSame_Constraint_impl<"bif", ".16b", VPR128, v16i8,
516 0b1, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
518 // Vector Absolute Difference and Accumulate (Signed, Unsigned)
520 def Neon_uaba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
521 (add node:$Ra, (int_arm_neon_vabdu node:$Rn, node:$Rm))>;
522 def Neon_saba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
523 (add node:$Ra, (int_arm_neon_vabds node:$Rn, node:$Rm))>;
525 // Vector Absolute Difference and Accumulate (Unsigned)
526 def UABAvvv_8B : NeonI_3VSame_Constraint_impl<"uaba", ".8b", VPR64, v8i8,
527 0b0, 0b1, 0b00, 0b01111, Neon_uaba>;
528 def UABAvvv_16B : NeonI_3VSame_Constraint_impl<"uaba", ".16b", VPR128, v16i8,
529 0b1, 0b1, 0b00, 0b01111, Neon_uaba>;
530 def UABAvvv_4H : NeonI_3VSame_Constraint_impl<"uaba", ".4h", VPR64, v4i16,
531 0b0, 0b1, 0b01, 0b01111, Neon_uaba>;
532 def UABAvvv_8H : NeonI_3VSame_Constraint_impl<"uaba", ".8h", VPR128, v8i16,
533 0b1, 0b1, 0b01, 0b01111, Neon_uaba>;
534 def UABAvvv_2S : NeonI_3VSame_Constraint_impl<"uaba", ".2s", VPR64, v2i32,
535 0b0, 0b1, 0b10, 0b01111, Neon_uaba>;
536 def UABAvvv_4S : NeonI_3VSame_Constraint_impl<"uaba", ".4s", VPR128, v4i32,
537 0b1, 0b1, 0b10, 0b01111, Neon_uaba>;
539 // Vector Absolute Difference and Accumulate (Signed)
540 def SABAvvv_8B : NeonI_3VSame_Constraint_impl<"saba", ".8b", VPR64, v8i8,
541 0b0, 0b0, 0b00, 0b01111, Neon_saba>;
542 def SABAvvv_16B : NeonI_3VSame_Constraint_impl<"saba", ".16b", VPR128, v16i8,
543 0b1, 0b0, 0b00, 0b01111, Neon_saba>;
544 def SABAvvv_4H : NeonI_3VSame_Constraint_impl<"saba", ".4h", VPR64, v4i16,
545 0b0, 0b0, 0b01, 0b01111, Neon_saba>;
546 def SABAvvv_8H : NeonI_3VSame_Constraint_impl<"saba", ".8h", VPR128, v8i16,
547 0b1, 0b0, 0b01, 0b01111, Neon_saba>;
548 def SABAvvv_2S : NeonI_3VSame_Constraint_impl<"saba", ".2s", VPR64, v2i32,
549 0b0, 0b0, 0b10, 0b01111, Neon_saba>;
550 def SABAvvv_4S : NeonI_3VSame_Constraint_impl<"saba", ".4s", VPR128, v4i32,
551 0b1, 0b0, 0b10, 0b01111, Neon_saba>;
554 // Vector Absolute Difference (Signed, Unsigned)
555 defm UABDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01110, "uabd", int_arm_neon_vabdu, 0>;
556 defm SABDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01110, "sabd", int_arm_neon_vabds, 0>;
558 // Vector Absolute Difference (Floating Point)
559 defm FABDvvv: NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11010, "fabd",
560 int_arm_neon_vabds, int_arm_neon_vabds,
561 int_arm_neon_vabds, v2f32, v4f32, v2f64, 0>;
563 // Vector Reciprocal Step (Floating Point)
564 defm FRECPSvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11111, "frecps",
565 int_arm_neon_vrecps, int_arm_neon_vrecps,
567 v2f32, v4f32, v2f64, 0>;
569 // Vector Reciprocal Square Root Step (Floating Point)
570 defm FRSQRTSvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11111, "frsqrts",
571 int_arm_neon_vrsqrts,
572 int_arm_neon_vrsqrts,
573 int_arm_neon_vrsqrts,
574 v2f32, v4f32, v2f64, 0>;
576 // Vector Comparisons
578 def Neon_cmeq : PatFrag<(ops node:$lhs, node:$rhs),
579 (Neon_cmp node:$lhs, node:$rhs, SETEQ)>;
580 def Neon_cmphs : PatFrag<(ops node:$lhs, node:$rhs),
581 (Neon_cmp node:$lhs, node:$rhs, SETUGE)>;
582 def Neon_cmge : PatFrag<(ops node:$lhs, node:$rhs),
583 (Neon_cmp node:$lhs, node:$rhs, SETGE)>;
584 def Neon_cmhi : PatFrag<(ops node:$lhs, node:$rhs),
585 (Neon_cmp node:$lhs, node:$rhs, SETUGT)>;
586 def Neon_cmgt : PatFrag<(ops node:$lhs, node:$rhs),
587 (Neon_cmp node:$lhs, node:$rhs, SETGT)>;
589 // NeonI_compare_aliases class: swaps register operands to implement
590 // comparison aliases, e.g., CMLE is alias for CMGE with operands reversed.
591 class NeonI_compare_aliases<string asmop, string asmlane,
592 Instruction inst, RegisterOperand VPRC>
593 : NeonInstAlias<asmop # "\t$Rd" # asmlane #", $Rn" # asmlane #
595 (inst VPRC:$Rd, VPRC:$Rm, VPRC:$Rn), 0b0>;
597 // Vector Comparisons (Integer)
599 // Vector Compare Mask Equal (Integer)
600 let isCommutable =1 in {
601 defm CMEQvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10001, "cmeq", Neon_cmeq, 0>;
604 // Vector Compare Mask Higher or Same (Unsigned Integer)
605 defm CMHSvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00111, "cmhs", Neon_cmphs, 0>;
607 // Vector Compare Mask Greater Than or Equal (Integer)
608 defm CMGEvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00111, "cmge", Neon_cmge, 0>;
610 // Vector Compare Mask Higher (Unsigned Integer)
611 defm CMHIvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00110, "cmhi", Neon_cmhi, 0>;
613 // Vector Compare Mask Greater Than (Integer)
614 defm CMGTvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00110, "cmgt", Neon_cmgt, 0>;
616 // Vector Compare Mask Bitwise Test (Integer)
617 defm CMTSTvvv: NeonI_3VSame_BHSD_sizes<0b0, 0b10001, "cmtst", Neon_tst, 0>;
619 // Vector Compare Mask Less or Same (Unsigned Integer)
620 // CMLS is alias for CMHS with operands reversed.
621 def CMLSvvv_8B : NeonI_compare_aliases<"cmls", ".8b", CMHSvvv_8B, VPR64>;
622 def CMLSvvv_16B : NeonI_compare_aliases<"cmls", ".16b", CMHSvvv_16B, VPR128>;
623 def CMLSvvv_4H : NeonI_compare_aliases<"cmls", ".4h", CMHSvvv_4H, VPR64>;
624 def CMLSvvv_8H : NeonI_compare_aliases<"cmls", ".8h", CMHSvvv_8H, VPR128>;
625 def CMLSvvv_2S : NeonI_compare_aliases<"cmls", ".2s", CMHSvvv_2S, VPR64>;
626 def CMLSvvv_4S : NeonI_compare_aliases<"cmls", ".4s", CMHSvvv_4S, VPR128>;
627 def CMLSvvv_2D : NeonI_compare_aliases<"cmls", ".2d", CMHSvvv_2D, VPR128>;
629 // Vector Compare Mask Less Than or Equal (Integer)
630 // CMLE is alias for CMGE with operands reversed.
631 def CMLEvvv_8B : NeonI_compare_aliases<"cmle", ".8b", CMGEvvv_8B, VPR64>;
632 def CMLEvvv_16B : NeonI_compare_aliases<"cmle", ".16b", CMGEvvv_16B, VPR128>;
633 def CMLEvvv_4H : NeonI_compare_aliases<"cmle", ".4h", CMGEvvv_4H, VPR64>;
634 def CMLEvvv_8H : NeonI_compare_aliases<"cmle", ".8h", CMGEvvv_8H, VPR128>;
635 def CMLEvvv_2S : NeonI_compare_aliases<"cmle", ".2s", CMGEvvv_2S, VPR64>;
636 def CMLEvvv_4S : NeonI_compare_aliases<"cmle", ".4s", CMGEvvv_4S, VPR128>;
637 def CMLEvvv_2D : NeonI_compare_aliases<"cmle", ".2d", CMGEvvv_2D, VPR128>;
639 // Vector Compare Mask Lower (Unsigned Integer)
640 // CMLO is alias for CMHI with operands reversed.
641 def CMLOvvv_8B : NeonI_compare_aliases<"cmlo", ".8b", CMHIvvv_8B, VPR64>;
642 def CMLOvvv_16B : NeonI_compare_aliases<"cmlo", ".16b", CMHIvvv_16B, VPR128>;
643 def CMLOvvv_4H : NeonI_compare_aliases<"cmlo", ".4h", CMHIvvv_4H, VPR64>;
644 def CMLOvvv_8H : NeonI_compare_aliases<"cmlo", ".8h", CMHIvvv_8H, VPR128>;
645 def CMLOvvv_2S : NeonI_compare_aliases<"cmlo", ".2s", CMHIvvv_2S, VPR64>;
646 def CMLOvvv_4S : NeonI_compare_aliases<"cmlo", ".4s", CMHIvvv_4S, VPR128>;
647 def CMLOvvv_2D : NeonI_compare_aliases<"cmlo", ".2d", CMHIvvv_2D, VPR128>;
649 // Vector Compare Mask Less Than (Integer)
650 // CMLT is alias for CMGT with operands reversed.
651 def CMLTvvv_8B : NeonI_compare_aliases<"cmlt", ".8b", CMGTvvv_8B, VPR64>;
652 def CMLTvvv_16B : NeonI_compare_aliases<"cmlt", ".16b", CMGTvvv_16B, VPR128>;
653 def CMLTvvv_4H : NeonI_compare_aliases<"cmlt", ".4h", CMGTvvv_4H, VPR64>;
654 def CMLTvvv_8H : NeonI_compare_aliases<"cmlt", ".8h", CMGTvvv_8H, VPR128>;
655 def CMLTvvv_2S : NeonI_compare_aliases<"cmlt", ".2s", CMGTvvv_2S, VPR64>;
656 def CMLTvvv_4S : NeonI_compare_aliases<"cmlt", ".4s", CMGTvvv_4S, VPR128>;
657 def CMLTvvv_2D : NeonI_compare_aliases<"cmlt", ".2d", CMGTvvv_2D, VPR128>;
660 def neon_uimm0_asmoperand : AsmOperandClass
663 let PredicateMethod = "isUImm<0>";
664 let RenderMethod = "addImmOperands";
667 def neon_uimm0 : Operand<i32>, ImmLeaf<i32, [{return Imm == 0;}]> {
668 let ParserMatchClass = neon_uimm0_asmoperand;
669 let PrintMethod = "printNeonUImm0Operand";
673 multiclass NeonI_cmpz_sizes<bit u, bits<5> opcode, string asmop, CondCode CC>
675 def _8B : NeonI_2VMisc<0b0, u, 0b00, opcode,
676 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
677 asmop # "\t$Rd.8b, $Rn.8b, $Imm",
678 [(set (v8i8 VPR64:$Rd),
679 (v8i8 (Neon_cmpz (v8i8 VPR64:$Rn), (i32 imm:$Imm), CC)))],
682 def _16B : NeonI_2VMisc<0b1, u, 0b00, opcode,
683 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
684 asmop # "\t$Rd.16b, $Rn.16b, $Imm",
685 [(set (v16i8 VPR128:$Rd),
686 (v16i8 (Neon_cmpz (v16i8 VPR128:$Rn), (i32 imm:$Imm), CC)))],
689 def _4H : NeonI_2VMisc<0b0, u, 0b01, opcode,
690 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
691 asmop # "\t$Rd.4h, $Rn.4h, $Imm",
692 [(set (v4i16 VPR64:$Rd),
693 (v4i16 (Neon_cmpz (v4i16 VPR64:$Rn), (i32 imm:$Imm), CC)))],
696 def _8H : NeonI_2VMisc<0b1, u, 0b01, opcode,
697 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
698 asmop # "\t$Rd.8h, $Rn.8h, $Imm",
699 [(set (v8i16 VPR128:$Rd),
700 (v8i16 (Neon_cmpz (v8i16 VPR128:$Rn), (i32 imm:$Imm), CC)))],
703 def _2S : NeonI_2VMisc<0b0, u, 0b10, opcode,
704 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
705 asmop # "\t$Rd.2s, $Rn.2s, $Imm",
706 [(set (v2i32 VPR64:$Rd),
707 (v2i32 (Neon_cmpz (v2i32 VPR64:$Rn), (i32 imm:$Imm), CC)))],
710 def _4S : NeonI_2VMisc<0b1, u, 0b10, opcode,
711 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
712 asmop # "\t$Rd.4s, $Rn.4s, $Imm",
713 [(set (v4i32 VPR128:$Rd),
714 (v4i32 (Neon_cmpz (v4i32 VPR128:$Rn), (i32 imm:$Imm), CC)))],
717 def _2D : NeonI_2VMisc<0b1, u, 0b11, opcode,
718 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
719 asmop # "\t$Rd.2d, $Rn.2d, $Imm",
720 [(set (v2i64 VPR128:$Rd),
721 (v2i64 (Neon_cmpz (v2i64 VPR128:$Rn), (i32 imm:$Imm), CC)))],
725 // Vector Compare Mask Equal to Zero (Integer)
726 defm CMEQvvi : NeonI_cmpz_sizes<0b0, 0b01001, "cmeq", SETEQ>;
728 // Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
729 defm CMGEvvi : NeonI_cmpz_sizes<0b1, 0b01000, "cmge", SETGE>;
731 // Vector Compare Mask Greater Than Zero (Signed Integer)
732 defm CMGTvvi : NeonI_cmpz_sizes<0b0, 0b01000, "cmgt", SETGT>;
734 // Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
735 defm CMLEvvi : NeonI_cmpz_sizes<0b1, 0b01001, "cmle", SETLE>;
737 // Vector Compare Mask Less Than Zero (Signed Integer)
738 defm CMLTvvi : NeonI_cmpz_sizes<0b0, 0b01010, "cmlt", SETLT>;
740 // Vector Comparisons (Floating Point)
742 // Vector Compare Mask Equal (Floating Point)
743 let isCommutable =1 in {
744 defm FCMEQvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11100, "fcmeq", Neon_cmeq,
745 Neon_cmeq, Neon_cmeq,
746 v2i32, v4i32, v2i64, 0>;
749 // Vector Compare Mask Greater Than Or Equal (Floating Point)
750 defm FCMGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11100, "fcmge", Neon_cmge,
751 Neon_cmge, Neon_cmge,
752 v2i32, v4i32, v2i64, 0>;
754 // Vector Compare Mask Greater Than (Floating Point)
755 defm FCMGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11100, "fcmgt", Neon_cmgt,
756 Neon_cmgt, Neon_cmgt,
757 v2i32, v4i32, v2i64, 0>;
759 // Vector Compare Mask Less Than Or Equal (Floating Point)
760 // FCMLE is alias for FCMGE with operands reversed.
761 def FCMLEvvv_2S : NeonI_compare_aliases<"fcmle", ".2s", FCMGEvvv_2S, VPR64>;
762 def FCMLEvvv_4S : NeonI_compare_aliases<"fcmle", ".4s", FCMGEvvv_4S, VPR128>;
763 def FCMLEvvv_2D : NeonI_compare_aliases<"fcmle", ".2d", FCMGEvvv_2D, VPR128>;
765 // Vector Compare Mask Less Than (Floating Point)
766 // FCMLT is alias for FCMGT with operands reversed.
767 def FCMLTvvv_2S : NeonI_compare_aliases<"fcmlt", ".2s", FCMGTvvv_2S, VPR64>;
768 def FCMLTvvv_4S : NeonI_compare_aliases<"fcmlt", ".4s", FCMGTvvv_4S, VPR128>;
769 def FCMLTvvv_2D : NeonI_compare_aliases<"fcmlt", ".2d", FCMGTvvv_2D, VPR128>;
772 multiclass NeonI_fpcmpz_sizes<bit u, bit size, bits<5> opcode,
773 string asmop, CondCode CC>
775 def _2S : NeonI_2VMisc<0b0, u, {size, 0b0}, opcode,
776 (outs VPR64:$Rd), (ins VPR64:$Rn, fpz32:$FPImm),
777 asmop # "\t$Rd.2s, $Rn.2s, $FPImm",
778 [(set (v2i32 VPR64:$Rd),
779 (v2i32 (Neon_cmpz (v2f32 VPR64:$Rn), (f32 fpimm:$FPImm), CC)))],
782 def _4S : NeonI_2VMisc<0b1, u, {size, 0b0}, opcode,
783 (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
784 asmop # "\t$Rd.4s, $Rn.4s, $FPImm",
785 [(set (v4i32 VPR128:$Rd),
786 (v4i32 (Neon_cmpz (v4f32 VPR128:$Rn), (f32 fpimm:$FPImm), CC)))],
789 def _2D : NeonI_2VMisc<0b1, u, {size, 0b1}, opcode,
790 (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
791 asmop # "\t$Rd.2d, $Rn.2d, $FPImm",
792 [(set (v2i64 VPR128:$Rd),
793 (v2i64 (Neon_cmpz (v2f64 VPR128:$Rn), (f32 fpimm:$FPImm), CC)))],
797 // Vector Compare Mask Equal to Zero (Floating Point)
798 defm FCMEQvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01101, "fcmeq", SETEQ>;
800 // Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
801 defm FCMGEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01100, "fcmge", SETGE>;
803 // Vector Compare Mask Greater Than Zero (Floating Point)
804 defm FCMGTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01100, "fcmgt", SETGT>;
806 // Vector Compare Mask Less Than or Equal To Zero (Floating Point)
807 defm FCMLEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01101, "fcmle", SETLE>;
809 // Vector Compare Mask Less Than Zero (Floating Point)
810 defm FCMLTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01110, "fcmlt", SETLT>;
812 // Vector Absolute Comparisons (Floating Point)
814 // Vector Absolute Compare Mask Greater Than Or Equal (Floating Point)
815 defm FACGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11101, "facge",
816 int_arm_neon_vacged, int_arm_neon_vacgeq,
817 int_aarch64_neon_vacgeq,
818 v2i32, v4i32, v2i64, 0>;
820 // Vector Absolute Compare Mask Greater Than (Floating Point)
821 defm FACGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11101, "facgt",
822 int_arm_neon_vacgtd, int_arm_neon_vacgtq,
823 int_aarch64_neon_vacgtq,
824 v2i32, v4i32, v2i64, 0>;
826 // Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
827 // FACLE is alias for FACGE with operands reversed.
828 def FACLEvvv_2S : NeonI_compare_aliases<"facle", ".2s", FACGEvvv_2S, VPR64>;
829 def FACLEvvv_4S : NeonI_compare_aliases<"facle", ".4s", FACGEvvv_4S, VPR128>;
830 def FACLEvvv_2D : NeonI_compare_aliases<"facle", ".2d", FACGEvvv_2D, VPR128>;
832 // Vector Absolute Compare Mask Less Than (Floating Point)
833 // FACLT is alias for FACGT with operands reversed.
834 def FACLTvvv_2S : NeonI_compare_aliases<"faclt", ".2s", FACGTvvv_2S, VPR64>;
835 def FACLTvvv_4S : NeonI_compare_aliases<"faclt", ".4s", FACGTvvv_4S, VPR128>;
836 def FACLTvvv_2D : NeonI_compare_aliases<"faclt", ".2d", FACGTvvv_2D, VPR128>;
838 // Vector halving add (Integer Signed, Unsigned)
839 defm SHADDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00000, "shadd",
840 int_arm_neon_vhadds, 1>;
841 defm UHADDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00000, "uhadd",
842 int_arm_neon_vhaddu, 1>;
844 // Vector halving sub (Integer Signed, Unsigned)
845 defm SHSUBvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00100, "shsub",
846 int_arm_neon_vhsubs, 0>;
847 defm UHSUBvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00100, "uhsub",
848 int_arm_neon_vhsubu, 0>;
850 // Vector rouding halving add (Integer Signed, Unsigned)
851 defm SRHADDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00010, "srhadd",
852 int_arm_neon_vrhadds, 1>;
853 defm URHADDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00010, "urhadd",
854 int_arm_neon_vrhaddu, 1>;
856 // Vector Saturating add (Integer Signed, Unsigned)
857 defm SQADDvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00001, "sqadd",
858 int_arm_neon_vqadds, 1>;
859 defm UQADDvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00001, "uqadd",
860 int_arm_neon_vqaddu, 1>;
862 // Vector Saturating sub (Integer Signed, Unsigned)
863 defm SQSUBvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00101, "sqsub",
864 int_arm_neon_vqsubs, 1>;
865 defm UQSUBvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00101, "uqsub",
866 int_arm_neon_vqsubu, 1>;
868 // Vector Shift Left (Signed and Unsigned Integer)
869 defm SSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01000, "sshl",
870 int_arm_neon_vshifts, 1>;
871 defm USHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01000, "ushl",
872 int_arm_neon_vshiftu, 1>;
874 // Vector Saturating Shift Left (Signed and Unsigned Integer)
875 defm SQSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01001, "sqshl",
876 int_arm_neon_vqshifts, 1>;
877 defm UQSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01001, "uqshl",
878 int_arm_neon_vqshiftu, 1>;
880 // Vector Rouding Shift Left (Signed and Unsigned Integer)
881 defm SRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01010, "srshl",
882 int_arm_neon_vrshifts, 1>;
883 defm URSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01010, "urshl",
884 int_arm_neon_vrshiftu, 1>;
886 // Vector Saturating Rouding Shift Left (Signed and Unsigned Integer)
887 defm SQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01011, "sqrshl",
888 int_arm_neon_vqrshifts, 1>;
889 defm UQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01011, "uqrshl",
890 int_arm_neon_vqrshiftu, 1>;
892 // Vector Maximum (Signed and Unsigned Integer)
893 defm SMAXvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01100, "smax", int_arm_neon_vmaxs, 1>;
894 defm UMAXvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01100, "umax", int_arm_neon_vmaxu, 1>;
896 // Vector Minimum (Signed and Unsigned Integer)
897 defm SMINvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01101, "smin", int_arm_neon_vmins, 1>;
898 defm UMINvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01101, "umin", int_arm_neon_vminu, 1>;
900 // Vector Maximum (Floating Point)
901 defm FMAXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11110, "fmax",
902 int_arm_neon_vmaxs, int_arm_neon_vmaxs,
903 int_arm_neon_vmaxs, v2f32, v4f32, v2f64, 1>;
905 // Vector Minimum (Floating Point)
906 defm FMINvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11110, "fmin",
907 int_arm_neon_vmins, int_arm_neon_vmins,
908 int_arm_neon_vmins, v2f32, v4f32, v2f64, 1>;
910 // Vector maxNum (Floating Point) - prefer a number over a quiet NaN)
911 defm FMAXNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11000, "fmaxnm",
912 int_aarch64_neon_vmaxnm,
913 int_aarch64_neon_vmaxnm,
914 int_aarch64_neon_vmaxnm,
915 v2f32, v4f32, v2f64, 1>;
917 // Vector minNum (Floating Point) - prefer a number over a quiet NaN)
918 defm FMINNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11000, "fminnm",
919 int_aarch64_neon_vminnm,
920 int_aarch64_neon_vminnm,
921 int_aarch64_neon_vminnm,
922 v2f32, v4f32, v2f64, 1>;
924 // Vector Maximum Pairwise (Signed and Unsigned Integer)
925 defm SMAXPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10100, "smaxp", int_arm_neon_vpmaxs, 1>;
926 defm UMAXPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10100, "umaxp", int_arm_neon_vpmaxu, 1>;
928 // Vector Minimum Pairwise (Signed and Unsigned Integer)
929 defm SMINPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10101, "sminp", int_arm_neon_vpmins, 1>;
930 defm UMINPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10101, "uminp", int_arm_neon_vpminu, 1>;
932 // Vector Maximum Pairwise (Floating Point)
933 defm FMAXPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11110, "fmaxp",
934 int_arm_neon_vpmaxs, int_arm_neon_vpmaxs,
935 int_arm_neon_vpmaxs, v2f32, v4f32, v2f64, 1>;
937 // Vector Minimum Pairwise (Floating Point)
938 defm FMINPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11110, "fminp",
939 int_arm_neon_vpmins, int_arm_neon_vpmins,
940 int_arm_neon_vpmins, v2f32, v4f32, v2f64, 1>;
942 // Vector maxNum Pairwise (Floating Point) - prefer a number over a quiet NaN)
943 defm FMAXNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11000, "fmaxnmp",
944 int_aarch64_neon_vpmaxnm,
945 int_aarch64_neon_vpmaxnm,
946 int_aarch64_neon_vpmaxnm,
947 v2f32, v4f32, v2f64, 1>;
949 // Vector minNum Pairwise (Floating Point) - prefer a number over a quiet NaN)
950 defm FMINNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11000, "fminnmp",
951 int_aarch64_neon_vpminnm,
952 int_aarch64_neon_vpminnm,
953 int_aarch64_neon_vpminnm,
954 v2f32, v4f32, v2f64, 1>;
956 // Vector Addition Pairwise (Integer)
957 defm ADDP : NeonI_3VSame_BHSD_sizes<0b0, 0b10111, "addp", int_arm_neon_vpadd, 1>;
959 // Vector Addition Pairwise (Floating Point)
960 defm FADDP : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11010, "faddp",
964 v2f32, v4f32, v2f64, 1>;
966 // Vector Saturating Doubling Multiply High
967 defm SQDMULHvvv : NeonI_3VSame_HS_sizes<0b0, 0b10110, "sqdmulh",
968 int_arm_neon_vqdmulh, 1>;
970 // Vector Saturating Rouding Doubling Multiply High
971 defm SQRDMULHvvv : NeonI_3VSame_HS_sizes<0b1, 0b10110, "sqrdmulh",
972 int_arm_neon_vqrdmulh, 1>;
974 // Vector Multiply Extended (Floating Point)
975 defm FMULXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11011, "fmulx",
976 int_aarch64_neon_vmulx,
977 int_aarch64_neon_vmulx,
978 int_aarch64_neon_vmulx,
979 v2f32, v4f32, v2f64, 1>;
981 // Patterns to match llvm.aarch64.* intrinsic for
982 // ADDP, SMINP, UMINP, SMAXP, UMAXP having i32 as output
983 class Neon_VectorPair_v2i32_pattern<SDPatternOperator opnode, Instruction INST>
984 : Pat<(v1i32 (opnode (v2i32 VPR64:$Rn))),
986 (v2i32 (INST (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rn))),
989 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_sminv, SMINPvvv_2S>;
990 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_uminv, UMINPvvv_2S>;
991 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_smaxv, SMAXPvvv_2S>;
992 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_umaxv, UMAXPvvv_2S>;
993 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_vaddv, ADDP_2S>;
995 // Vector Immediate Instructions
997 multiclass neon_mov_imm_shift_asmoperands<string PREFIX>
999 def _asmoperand : AsmOperandClass
1001 let Name = "NeonMovImmShift" # PREFIX;
1002 let RenderMethod = "addNeonMovImmShift" # PREFIX # "Operands";
1003 let PredicateMethod = "isNeonMovImmShift" # PREFIX;
1007 // Definition of vector immediates shift operands
1009 // The selectable use-cases extract the shift operation
1010 // information from the OpCmode fields encoded in the immediate.
1011 def neon_mod_shift_imm_XFORM : SDNodeXForm<imm, [{
1012 uint64_t OpCmode = N->getZExtValue();
1014 unsigned ShiftOnesIn;
1016 A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1017 if (!HasShift) return SDValue();
1018 return CurDAG->getTargetConstant(ShiftImm, MVT::i32);
1021 // Vector immediates shift operands which accept LSL and MSL
1022 // shift operators with shift value in the range of 0, 8, 16, 24 (LSL),
1023 // or 0, 8 (LSLH) or 8, 16 (MSL).
1024 defm neon_mov_imm_LSL : neon_mov_imm_shift_asmoperands<"LSL">;
1025 defm neon_mov_imm_MSL : neon_mov_imm_shift_asmoperands<"MSL">;
1026 // LSLH restricts shift amount to 0, 8 out of 0, 8, 16, 24
1027 defm neon_mov_imm_LSLH : neon_mov_imm_shift_asmoperands<"LSLH">;
1029 multiclass neon_mov_imm_shift_operands<string PREFIX,
1030 string HALF, string ISHALF, code pred>
1032 def _operand : Operand<i32>, ImmLeaf<i32, pred, neon_mod_shift_imm_XFORM>
1035 "printNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1037 "DecodeNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1038 let ParserMatchClass =
1039 !cast<AsmOperandClass>("neon_mov_imm_" # PREFIX # HALF # "_asmoperand");
1043 defm neon_mov_imm_LSL : neon_mov_imm_shift_operands<"LSL", "", "false", [{
1045 unsigned ShiftOnesIn;
1047 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1048 return (HasShift && !ShiftOnesIn);
1051 defm neon_mov_imm_MSL : neon_mov_imm_shift_operands<"MSL", "", "false", [{
1053 unsigned ShiftOnesIn;
1055 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1056 return (HasShift && ShiftOnesIn);
1059 defm neon_mov_imm_LSLH : neon_mov_imm_shift_operands<"LSL", "H", "true", [{
1061 unsigned ShiftOnesIn;
1063 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1064 return (HasShift && !ShiftOnesIn);
1067 def neon_uimm1_asmoperand : AsmOperandClass
1070 let PredicateMethod = "isUImm<1>";
1071 let RenderMethod = "addImmOperands";
1074 def neon_uimm2_asmoperand : AsmOperandClass
1077 let PredicateMethod = "isUImm<2>";
1078 let RenderMethod = "addImmOperands";
1081 def neon_uimm8_asmoperand : AsmOperandClass
1084 let PredicateMethod = "isUImm<8>";
1085 let RenderMethod = "addImmOperands";
1088 def neon_uimm8 : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1089 let ParserMatchClass = neon_uimm8_asmoperand;
1090 let PrintMethod = "printUImmHexOperand";
1093 def neon_uimm64_mask_asmoperand : AsmOperandClass
1095 let Name = "NeonUImm64Mask";
1096 let PredicateMethod = "isNeonUImm64Mask";
1097 let RenderMethod = "addNeonUImm64MaskOperands";
1100 // MCOperand for 64-bit bytemask with each byte having only the
1101 // value 0x00 and 0xff is encoded as an unsigned 8-bit value
1102 def neon_uimm64_mask : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1103 let ParserMatchClass = neon_uimm64_mask_asmoperand;
1104 let PrintMethod = "printNeonUImm64MaskOperand";
1107 multiclass NeonI_mov_imm_lsl_sizes<string asmop, bit op,
1108 SDPatternOperator opnode>
1110 // shift zeros, per word
1111 def _2S : NeonI_1VModImm<0b0, op,
1113 (ins neon_uimm8:$Imm,
1114 neon_mov_imm_LSL_operand:$Simm),
1115 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1116 [(set (v2i32 VPR64:$Rd),
1117 (v2i32 (opnode (timm:$Imm),
1118 (neon_mov_imm_LSL_operand:$Simm))))],
1121 let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1124 def _4S : NeonI_1VModImm<0b1, op,
1126 (ins neon_uimm8:$Imm,
1127 neon_mov_imm_LSL_operand:$Simm),
1128 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1129 [(set (v4i32 VPR128:$Rd),
1130 (v4i32 (opnode (timm:$Imm),
1131 (neon_mov_imm_LSL_operand:$Simm))))],
1134 let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1137 // shift zeros, per halfword
1138 def _4H : NeonI_1VModImm<0b0, op,
1140 (ins neon_uimm8:$Imm,
1141 neon_mov_imm_LSLH_operand:$Simm),
1142 !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1143 [(set (v4i16 VPR64:$Rd),
1144 (v4i16 (opnode (timm:$Imm),
1145 (neon_mov_imm_LSLH_operand:$Simm))))],
1148 let cmode = {0b1, 0b0, Simm, 0b0};
1151 def _8H : NeonI_1VModImm<0b1, op,
1153 (ins neon_uimm8:$Imm,
1154 neon_mov_imm_LSLH_operand:$Simm),
1155 !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1156 [(set (v8i16 VPR128:$Rd),
1157 (v8i16 (opnode (timm:$Imm),
1158 (neon_mov_imm_LSLH_operand:$Simm))))],
1161 let cmode = {0b1, 0b0, Simm, 0b0};
1165 multiclass NeonI_mov_imm_with_constraint_lsl_sizes<string asmop, bit op,
1166 SDPatternOperator opnode,
1167 SDPatternOperator neonopnode>
1169 let Constraints = "$src = $Rd" in {
1170 // shift zeros, per word
1171 def _2S : NeonI_1VModImm<0b0, op,
1173 (ins VPR64:$src, neon_uimm8:$Imm,
1174 neon_mov_imm_LSL_operand:$Simm),
1175 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1176 [(set (v2i32 VPR64:$Rd),
1177 (v2i32 (opnode (v2i32 VPR64:$src),
1178 (v2i32 (bitconvert (v2i32 (neonopnode timm:$Imm,
1179 neon_mov_imm_LSL_operand:$Simm)))))))],
1182 let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1185 def _4S : NeonI_1VModImm<0b1, op,
1187 (ins VPR128:$src, neon_uimm8:$Imm,
1188 neon_mov_imm_LSL_operand:$Simm),
1189 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1190 [(set (v4i32 VPR128:$Rd),
1191 (v4i32 (opnode (v4i32 VPR128:$src),
1192 (v4i32 (bitconvert (v4i32 (neonopnode timm:$Imm,
1193 neon_mov_imm_LSL_operand:$Simm)))))))],
1196 let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1199 // shift zeros, per halfword
1200 def _4H : NeonI_1VModImm<0b0, op,
1202 (ins VPR64:$src, neon_uimm8:$Imm,
1203 neon_mov_imm_LSLH_operand:$Simm),
1204 !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1205 [(set (v4i16 VPR64:$Rd),
1206 (v4i16 (opnode (v4i16 VPR64:$src),
1207 (v4i16 (bitconvert (v4i16 (neonopnode timm:$Imm,
1208 neon_mov_imm_LSL_operand:$Simm)))))))],
1211 let cmode = {0b1, 0b0, Simm, 0b1};
1214 def _8H : NeonI_1VModImm<0b1, op,
1216 (ins VPR128:$src, neon_uimm8:$Imm,
1217 neon_mov_imm_LSLH_operand:$Simm),
1218 !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1219 [(set (v8i16 VPR128:$Rd),
1220 (v8i16 (opnode (v8i16 VPR128:$src),
1221 (v8i16 (bitconvert (v8i16 (neonopnode timm:$Imm,
1222 neon_mov_imm_LSL_operand:$Simm)))))))],
1225 let cmode = {0b1, 0b0, Simm, 0b1};
1230 multiclass NeonI_mov_imm_msl_sizes<string asmop, bit op,
1231 SDPatternOperator opnode>
1233 // shift ones, per word
1234 def _2S : NeonI_1VModImm<0b0, op,
1236 (ins neon_uimm8:$Imm,
1237 neon_mov_imm_MSL_operand:$Simm),
1238 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1239 [(set (v2i32 VPR64:$Rd),
1240 (v2i32 (opnode (timm:$Imm),
1241 (neon_mov_imm_MSL_operand:$Simm))))],
1244 let cmode = {0b1, 0b1, 0b0, Simm};
1247 def _4S : NeonI_1VModImm<0b1, op,
1249 (ins neon_uimm8:$Imm,
1250 neon_mov_imm_MSL_operand:$Simm),
1251 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1252 [(set (v4i32 VPR128:$Rd),
1253 (v4i32 (opnode (timm:$Imm),
1254 (neon_mov_imm_MSL_operand:$Simm))))],
1257 let cmode = {0b1, 0b1, 0b0, Simm};
1261 // Vector Move Immediate Shifted
1262 let isReMaterializable = 1 in {
1263 defm MOVIvi_lsl : NeonI_mov_imm_lsl_sizes<"movi", 0b0, Neon_movi>;
1266 // Vector Move Inverted Immediate Shifted
1267 let isReMaterializable = 1 in {
1268 defm MVNIvi_lsl : NeonI_mov_imm_lsl_sizes<"mvni", 0b1, Neon_mvni>;
1271 // Vector Bitwise Bit Clear (AND NOT) - immediate
1272 let isReMaterializable = 1 in {
1273 defm BICvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"bic", 0b1,
1277 // Vector Bitwise OR - immedidate
1279 let isReMaterializable = 1 in {
1280 defm ORRvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"orr", 0b0,
1284 // Additional patterns for Vector Bitwise Bit Clear (AND NOT) - immedidate
1285 // LowerBUILD_VECTOR favors lowering MOVI over MVNI.
1286 // BIC immediate instructions selection requires additional patterns to
1287 // transform Neon_movi operands into BIC immediate operands
1289 def neon_mov_imm_LSLH_transform_XFORM : SDNodeXForm<imm, [{
1290 uint64_t OpCmode = N->getZExtValue();
1292 unsigned ShiftOnesIn;
1293 (void)A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1294 // LSLH restricts shift amount to 0, 8 which are encoded as 0 and 1
1295 // Transform encoded shift amount 0 to 1 and 1 to 0.
1296 return CurDAG->getTargetConstant(!ShiftImm, MVT::i32);
1299 def neon_mov_imm_LSLH_transform_operand
1302 unsigned ShiftOnesIn;
1304 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1305 return (HasShift && !ShiftOnesIn); }],
1306 neon_mov_imm_LSLH_transform_XFORM>;
1308 // Transform (and A, (4h Neon_movi 0xff)) -> BIC 4h (A, 0x00, LSL 8)
1309 // Transform (and A, (4h Neon_movi 0xff LSL #8)) -> BIC 4h (A, 0x00)
1310 def : Pat<(v4i16 (and VPR64:$src,
1311 (v4i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1312 (BICvi_lsl_4H VPR64:$src, 0,
1313 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1315 // Transform (and A, (8h Neon_movi 8h 0xff)) -> BIC 8h (A, 0x00, LSL 8)
1316 // Transform (and A, (8h Neon_movi 0xff LSL #8)) -> BIC 8h (A, 0x00)
1317 def : Pat<(v8i16 (and VPR128:$src,
1318 (v8i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1319 (BICvi_lsl_8H VPR128:$src, 0,
1320 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1323 multiclass Neon_bitwiseVi_patterns<SDPatternOperator opnode,
1324 SDPatternOperator neonopnode,
1326 Instruction INST8H> {
1327 def : Pat<(v8i8 (opnode VPR64:$src,
1328 (bitconvert(v4i16 (neonopnode timm:$Imm,
1329 neon_mov_imm_LSLH_operand:$Simm))))),
1330 (INST4H VPR64:$src, neon_uimm8:$Imm,
1331 neon_mov_imm_LSLH_operand:$Simm)>;
1332 def : Pat<(v1i64 (opnode VPR64:$src,
1333 (bitconvert(v4i16 (neonopnode timm:$Imm,
1334 neon_mov_imm_LSLH_operand:$Simm))))),
1335 (INST4H VPR64:$src, neon_uimm8:$Imm,
1336 neon_mov_imm_LSLH_operand:$Simm)>;
1338 def : Pat<(v16i8 (opnode VPR128:$src,
1339 (bitconvert(v8i16 (neonopnode timm:$Imm,
1340 neon_mov_imm_LSLH_operand:$Simm))))),
1341 (INST8H VPR128:$src, neon_uimm8:$Imm,
1342 neon_mov_imm_LSLH_operand:$Simm)>;
1343 def : Pat<(v4i32 (opnode VPR128:$src,
1344 (bitconvert(v8i16 (neonopnode timm:$Imm,
1345 neon_mov_imm_LSLH_operand:$Simm))))),
1346 (INST8H VPR128:$src, neon_uimm8:$Imm,
1347 neon_mov_imm_LSLH_operand:$Simm)>;
1348 def : Pat<(v2i64 (opnode VPR128:$src,
1349 (bitconvert(v8i16 (neonopnode timm:$Imm,
1350 neon_mov_imm_LSLH_operand:$Simm))))),
1351 (INST8H VPR128:$src, neon_uimm8:$Imm,
1352 neon_mov_imm_LSLH_operand:$Simm)>;
1355 // Additional patterns for Vector Vector Bitwise Bit Clear (AND NOT) - immediate
1356 defm : Neon_bitwiseVi_patterns<or, Neon_mvni, BICvi_lsl_4H, BICvi_lsl_8H>;
1358 // Additional patterns for Vector Bitwise OR - immedidate
1359 defm : Neon_bitwiseVi_patterns<or, Neon_movi, ORRvi_lsl_4H, ORRvi_lsl_8H>;
1362 // Vector Move Immediate Masked
1363 let isReMaterializable = 1 in {
1364 defm MOVIvi_msl : NeonI_mov_imm_msl_sizes<"movi", 0b0, Neon_movi>;
1367 // Vector Move Inverted Immediate Masked
1368 let isReMaterializable = 1 in {
1369 defm MVNIvi_msl : NeonI_mov_imm_msl_sizes<"mvni", 0b1, Neon_mvni>;
1372 class NeonI_mov_imm_lsl_aliases<string asmop, string asmlane,
1373 Instruction inst, RegisterOperand VPRC>
1374 : NeonInstAlias<!strconcat(asmop, "\t$Rd," # asmlane # ", $Imm"),
1375 (inst VPRC:$Rd, neon_uimm8:$Imm, 0), 0b0>;
1377 // Aliases for Vector Move Immediate Shifted
1378 def : NeonI_mov_imm_lsl_aliases<"movi", ".2s", MOVIvi_lsl_2S, VPR64>;
1379 def : NeonI_mov_imm_lsl_aliases<"movi", ".4s", MOVIvi_lsl_4S, VPR128>;
1380 def : NeonI_mov_imm_lsl_aliases<"movi", ".4h", MOVIvi_lsl_4H, VPR64>;
1381 def : NeonI_mov_imm_lsl_aliases<"movi", ".8h", MOVIvi_lsl_8H, VPR128>;
1383 // Aliases for Vector Move Inverted Immediate Shifted
1384 def : NeonI_mov_imm_lsl_aliases<"mvni", ".2s", MVNIvi_lsl_2S, VPR64>;
1385 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4s", MVNIvi_lsl_4S, VPR128>;
1386 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4h", MVNIvi_lsl_4H, VPR64>;
1387 def : NeonI_mov_imm_lsl_aliases<"mvni", ".8h", MVNIvi_lsl_8H, VPR128>;
1389 // Aliases for Vector Bitwise Bit Clear (AND NOT) - immediate
1390 def : NeonI_mov_imm_lsl_aliases<"bic", ".2s", BICvi_lsl_2S, VPR64>;
1391 def : NeonI_mov_imm_lsl_aliases<"bic", ".4s", BICvi_lsl_4S, VPR128>;
1392 def : NeonI_mov_imm_lsl_aliases<"bic", ".4h", BICvi_lsl_4H, VPR64>;
1393 def : NeonI_mov_imm_lsl_aliases<"bic", ".8h", BICvi_lsl_8H, VPR128>;
1395 // Aliases for Vector Bitwise OR - immedidate
1396 def : NeonI_mov_imm_lsl_aliases<"orr", ".2s", ORRvi_lsl_2S, VPR64>;
1397 def : NeonI_mov_imm_lsl_aliases<"orr", ".4s", ORRvi_lsl_4S, VPR128>;
1398 def : NeonI_mov_imm_lsl_aliases<"orr", ".4h", ORRvi_lsl_4H, VPR64>;
1399 def : NeonI_mov_imm_lsl_aliases<"orr", ".8h", ORRvi_lsl_8H, VPR128>;
1401 // Vector Move Immediate - per byte
1402 let isReMaterializable = 1 in {
1403 def MOVIvi_8B : NeonI_1VModImm<0b0, 0b0,
1404 (outs VPR64:$Rd), (ins neon_uimm8:$Imm),
1405 "movi\t$Rd.8b, $Imm",
1406 [(set (v8i8 VPR64:$Rd),
1407 (v8i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1412 def MOVIvi_16B : NeonI_1VModImm<0b1, 0b0,
1413 (outs VPR128:$Rd), (ins neon_uimm8:$Imm),
1414 "movi\t$Rd.16b, $Imm",
1415 [(set (v16i8 VPR128:$Rd),
1416 (v16i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1422 // Vector Move Immediate - bytemask, per double word
1423 let isReMaterializable = 1 in {
1424 def MOVIvi_2D : NeonI_1VModImm<0b1, 0b1,
1425 (outs VPR128:$Rd), (ins neon_uimm64_mask:$Imm),
1426 "movi\t $Rd.2d, $Imm",
1427 [(set (v2i64 VPR128:$Rd),
1428 (v2i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1434 // Vector Move Immediate - bytemask, one doubleword
1436 let isReMaterializable = 1 in {
1437 def MOVIdi : NeonI_1VModImm<0b0, 0b1,
1438 (outs FPR64:$Rd), (ins neon_uimm64_mask:$Imm),
1440 [(set (v1i64 FPR64:$Rd),
1441 (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1447 // Vector Floating Point Move Immediate
1449 class NeonI_FMOV_impl<string asmlane, RegisterOperand VPRC, ValueType OpTy,
1450 Operand immOpType, bit q, bit op>
1451 : NeonI_1VModImm<q, op,
1452 (outs VPRC:$Rd), (ins immOpType:$Imm),
1453 "fmov\t$Rd" # asmlane # ", $Imm",
1454 [(set (OpTy VPRC:$Rd),
1455 (OpTy (Neon_fmovi (timm:$Imm))))],
1460 let isReMaterializable = 1 in {
1461 def FMOVvi_2S : NeonI_FMOV_impl<".2s", VPR64, v2f32, fmov32_operand, 0b0, 0b0>;
1462 def FMOVvi_4S : NeonI_FMOV_impl<".4s", VPR128, v4f32, fmov32_operand, 0b1, 0b0>;
1463 def FMOVvi_2D : NeonI_FMOV_impl<".2d", VPR128, v2f64, fmov64_operand, 0b1, 0b1>;
1466 // Vector Shift (Immediate)
1467 // Immediate in [0, 63]
1468 def imm0_63 : Operand<i32> {
1469 let ParserMatchClass = uimm6_asmoperand;
1472 // Shift Right/Left Immediate - The immh:immb field of these shifts are encoded
1476 // 8 immh:immb<6:3> = '0001xxx', <imm> is encoded in immh:immb<2:0>
1477 // 16 immh:immb<6:4> = '001xxxx', <imm> is encoded in immh:immb<3:0>
1478 // 32 immh:immb<6:5> = '01xxxxx', <imm> is encoded in immh:immb<4:0>
1479 // 64 immh:immb<6> = '1xxxxxx', <imm> is encoded in immh:immb<5:0>
1481 // The shift right immediate amount, in the range 1 to element bits, is computed
1482 // as Offset - UInt(immh:immb). The shift left immediate amount, in the range 0
1483 // to element bits - 1, is computed as UInt(immh:immb) - Offset.
1485 class shr_imm_asmoperands<string OFFSET> : AsmOperandClass {
1486 let Name = "ShrImm" # OFFSET;
1487 let RenderMethod = "addImmOperands";
1488 let DiagnosticType = "ShrImm" # OFFSET;
1491 class shr_imm<string OFFSET> : Operand<i32> {
1492 let EncoderMethod = "getShiftRightImm" # OFFSET;
1493 let DecoderMethod = "DecodeShiftRightImm" # OFFSET;
1494 let ParserMatchClass =
1495 !cast<AsmOperandClass>("shr_imm" # OFFSET # "_asmoperand");
1498 def shr_imm8_asmoperand : shr_imm_asmoperands<"8">;
1499 def shr_imm16_asmoperand : shr_imm_asmoperands<"16">;
1500 def shr_imm32_asmoperand : shr_imm_asmoperands<"32">;
1501 def shr_imm64_asmoperand : shr_imm_asmoperands<"64">;
1503 def shr_imm8 : shr_imm<"8">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 8;}]>;
1504 def shr_imm16 : shr_imm<"16">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 16;}]>;
1505 def shr_imm32 : shr_imm<"32">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 32;}]>;
1506 def shr_imm64 : shr_imm<"64">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 64;}]>;
1508 class shl_imm_asmoperands<string OFFSET> : AsmOperandClass {
1509 let Name = "ShlImm" # OFFSET;
1510 let RenderMethod = "addImmOperands";
1511 let DiagnosticType = "ShlImm" # OFFSET;
1514 class shl_imm<string OFFSET> : Operand<i32> {
1515 let EncoderMethod = "getShiftLeftImm" # OFFSET;
1516 let DecoderMethod = "DecodeShiftLeftImm" # OFFSET;
1517 let ParserMatchClass =
1518 !cast<AsmOperandClass>("shl_imm" # OFFSET # "_asmoperand");
1521 def shl_imm8_asmoperand : shl_imm_asmoperands<"8">;
1522 def shl_imm16_asmoperand : shl_imm_asmoperands<"16">;
1523 def shl_imm32_asmoperand : shl_imm_asmoperands<"32">;
1524 def shl_imm64_asmoperand : shl_imm_asmoperands<"64">;
1526 def shl_imm8 : shl_imm<"8">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 8;}]>;
1527 def shl_imm16 : shl_imm<"16">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 16;}]>;
1528 def shl_imm32 : shl_imm<"32">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 32;}]>;
1529 def shl_imm64 : shl_imm<"64">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 64;}]>;
1531 class N2VShift<bit q, bit u, bits<5> opcode, string asmop, string T,
1532 RegisterOperand VPRC, ValueType Ty, Operand ImmTy, SDNode OpNode>
1533 : NeonI_2VShiftImm<q, u, opcode,
1534 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1535 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1536 [(set (Ty VPRC:$Rd),
1537 (Ty (OpNode (Ty VPRC:$Rn),
1538 (Ty (Neon_vdup (i32 ImmTy:$Imm))))))],
1541 multiclass NeonI_N2VShL<bit u, bits<5> opcode, string asmop> {
1542 // 64-bit vector types.
1543 def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8, shl> {
1544 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1547 def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16, shl> {
1548 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1551 def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32, shl> {
1552 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1555 // 128-bit vector types.
1556 def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8, shl> {
1557 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1560 def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16, shl> {
1561 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1564 def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32, shl> {
1565 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1568 def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64, shl> {
1569 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
1573 multiclass NeonI_N2VShR<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1574 def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1576 let Inst{22-19} = 0b0001;
1579 def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1581 let Inst{22-20} = 0b001;
1584 def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1586 let Inst{22-21} = 0b01;
1589 def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1591 let Inst{22-19} = 0b0001;
1594 def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1596 let Inst{22-20} = 0b001;
1599 def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1601 let Inst{22-21} = 0b01;
1604 def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1611 defm SHLvvi : NeonI_N2VShL<0b0, 0b01010, "shl">;
1614 defm SSHRvvi : NeonI_N2VShR<0b0, 0b00000, "sshr", sra>;
1615 defm USHRvvi : NeonI_N2VShR<0b1, 0b00000, "ushr", srl>;
1617 def Neon_High16B : PatFrag<(ops node:$in),
1618 (extract_subvector (v16i8 node:$in), (iPTR 8))>;
1619 def Neon_High8H : PatFrag<(ops node:$in),
1620 (extract_subvector (v8i16 node:$in), (iPTR 4))>;
1621 def Neon_High4S : PatFrag<(ops node:$in),
1622 (extract_subvector (v4i32 node:$in), (iPTR 2))>;
1623 def Neon_High2D : PatFrag<(ops node:$in),
1624 (extract_subvector (v2i64 node:$in), (iPTR 1))>;
1625 def Neon_High4float : PatFrag<(ops node:$in),
1626 (extract_subvector (v4f32 node:$in), (iPTR 2))>;
1627 def Neon_High2double : PatFrag<(ops node:$in),
1628 (extract_subvector (v2f64 node:$in), (iPTR 1))>;
1630 def Neon_Low16B : PatFrag<(ops node:$in),
1631 (v8i8 (extract_subvector (v16i8 node:$in),
1633 def Neon_Low8H : PatFrag<(ops node:$in),
1634 (v4i16 (extract_subvector (v8i16 node:$in),
1636 def Neon_Low4S : PatFrag<(ops node:$in),
1637 (v2i32 (extract_subvector (v4i32 node:$in),
1639 def Neon_Low2D : PatFrag<(ops node:$in),
1640 (v1i64 (extract_subvector (v2i64 node:$in),
1642 def Neon_Low4float : PatFrag<(ops node:$in),
1643 (v2f32 (extract_subvector (v4f32 node:$in),
1645 def Neon_Low2double : PatFrag<(ops node:$in),
1646 (v1f64 (extract_subvector (v2f64 node:$in),
1649 class N2VShiftLong<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1650 string SrcT, ValueType DestTy, ValueType SrcTy,
1651 Operand ImmTy, SDPatternOperator ExtOp>
1652 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1653 (ins VPR64:$Rn, ImmTy:$Imm),
1654 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1655 [(set (DestTy VPR128:$Rd),
1657 (DestTy (ExtOp (SrcTy VPR64:$Rn))),
1658 (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1661 class N2VShiftLongHigh<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1662 string SrcT, ValueType DestTy, ValueType SrcTy,
1663 int StartIndex, Operand ImmTy,
1664 SDPatternOperator ExtOp, PatFrag getTop>
1665 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1666 (ins VPR128:$Rn, ImmTy:$Imm),
1667 asmop # "2\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1668 [(set (DestTy VPR128:$Rd),
1671 (SrcTy (getTop VPR128:$Rn)))),
1672 (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1675 multiclass NeonI_N2VShLL<string prefix, bit u, bits<5> opcode, string asmop,
1677 // 64-bit vector types.
1678 def _8B : N2VShiftLong<0b0, u, opcode, asmop, "8h", "8b", v8i16, v8i8,
1680 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1683 def _4H : N2VShiftLong<0b0, u, opcode, asmop, "4s", "4h", v4i32, v4i16,
1685 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1688 def _2S : N2VShiftLong<0b0, u, opcode, asmop, "2d", "2s", v2i64, v2i32,
1690 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1693 // 128-bit vector types
1694 def _16B : N2VShiftLongHigh<0b1, u, opcode, asmop, "8h", "16b", v8i16, v8i8,
1695 8, shl_imm8, ExtOp, Neon_High16B> {
1696 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1699 def _8H : N2VShiftLongHigh<0b1, u, opcode, asmop, "4s", "8h", v4i32, v4i16,
1700 4, shl_imm16, ExtOp, Neon_High8H> {
1701 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1704 def _4S : N2VShiftLongHigh<0b1, u, opcode, asmop, "2d", "4s", v2i64, v2i32,
1705 2, shl_imm32, ExtOp, Neon_High4S> {
1706 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1709 // Use other patterns to match when the immediate is 0.
1710 def : Pat<(v8i16 (ExtOp (v8i8 VPR64:$Rn))),
1711 (!cast<Instruction>(prefix # "_8B") VPR64:$Rn, 0)>;
1713 def : Pat<(v4i32 (ExtOp (v4i16 VPR64:$Rn))),
1714 (!cast<Instruction>(prefix # "_4H") VPR64:$Rn, 0)>;
1716 def : Pat<(v2i64 (ExtOp (v2i32 VPR64:$Rn))),
1717 (!cast<Instruction>(prefix # "_2S") VPR64:$Rn, 0)>;
1719 def : Pat<(v8i16 (ExtOp (v8i8 (Neon_High16B VPR128:$Rn)))),
1720 (!cast<Instruction>(prefix # "_16B") VPR128:$Rn, 0)>;
1722 def : Pat<(v4i32 (ExtOp (v4i16 (Neon_High8H VPR128:$Rn)))),
1723 (!cast<Instruction>(prefix # "_8H") VPR128:$Rn, 0)>;
1725 def : Pat<(v2i64 (ExtOp (v2i32 (Neon_High4S VPR128:$Rn)))),
1726 (!cast<Instruction>(prefix # "_4S") VPR128:$Rn, 0)>;
1730 defm SSHLLvvi : NeonI_N2VShLL<"SSHLLvvi", 0b0, 0b10100, "sshll", sext>;
1731 defm USHLLvvi : NeonI_N2VShLL<"USHLLvvi", 0b1, 0b10100, "ushll", zext>;
1733 // Rounding/Saturating shift
1734 class N2VShift_RQ<bit q, bit u, bits<5> opcode, string asmop, string T,
1735 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1736 SDPatternOperator OpNode>
1737 : NeonI_2VShiftImm<q, u, opcode,
1738 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1739 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1740 [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$Rn),
1741 (i32 ImmTy:$Imm))))],
1744 // shift right (vector by immediate)
1745 multiclass NeonI_N2VShR_RQ<bit u, bits<5> opcode, string asmop,
1746 SDPatternOperator OpNode> {
1747 def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1749 let Inst{22-19} = 0b0001;
1752 def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1754 let Inst{22-20} = 0b001;
1757 def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1759 let Inst{22-21} = 0b01;
1762 def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1764 let Inst{22-19} = 0b0001;
1767 def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1769 let Inst{22-20} = 0b001;
1772 def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1774 let Inst{22-21} = 0b01;
1777 def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1783 multiclass NeonI_N2VShL_Q<bit u, bits<5> opcode, string asmop,
1784 SDPatternOperator OpNode> {
1785 // 64-bit vector types.
1786 def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
1788 let Inst{22-19} = 0b0001;
1791 def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
1793 let Inst{22-20} = 0b001;
1796 def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
1798 let Inst{22-21} = 0b01;
1801 // 128-bit vector types.
1802 def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
1804 let Inst{22-19} = 0b0001;
1807 def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
1809 let Inst{22-20} = 0b001;
1812 def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
1814 let Inst{22-21} = 0b01;
1817 def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
1823 // Rounding shift right
1824 defm SRSHRvvi : NeonI_N2VShR_RQ<0b0, 0b00100, "srshr",
1825 int_aarch64_neon_vsrshr>;
1826 defm URSHRvvi : NeonI_N2VShR_RQ<0b1, 0b00100, "urshr",
1827 int_aarch64_neon_vurshr>;
1829 // Saturating shift left unsigned
1830 defm SQSHLUvvi : NeonI_N2VShL_Q<0b1, 0b01100, "sqshlu", int_aarch64_neon_vsqshlu>;
1832 // Saturating shift left
1833 defm SQSHLvvi : NeonI_N2VShL_Q<0b0, 0b01110, "sqshl", Neon_sqrshlImm>;
1834 defm UQSHLvvi : NeonI_N2VShL_Q<0b1, 0b01110, "uqshl", Neon_uqrshlImm>;
1836 class N2VShiftAdd<bit q, bit u, bits<5> opcode, string asmop, string T,
1837 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1839 : NeonI_2VShiftImm<q, u, opcode,
1840 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1841 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1842 [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1843 (Ty (OpNode (Ty VPRC:$Rn),
1844 (Ty (Neon_vdup (i32 ImmTy:$Imm))))))))],
1846 let Constraints = "$src = $Rd";
1849 // Shift Right accumulate
1850 multiclass NeonI_N2VShRAdd<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1851 def _8B : N2VShiftAdd<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1853 let Inst{22-19} = 0b0001;
1856 def _4H : N2VShiftAdd<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1858 let Inst{22-20} = 0b001;
1861 def _2S : N2VShiftAdd<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1863 let Inst{22-21} = 0b01;
1866 def _16B : N2VShiftAdd<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1868 let Inst{22-19} = 0b0001;
1871 def _8H : N2VShiftAdd<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1873 let Inst{22-20} = 0b001;
1876 def _4S : N2VShiftAdd<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1878 let Inst{22-21} = 0b01;
1881 def _2D : N2VShiftAdd<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1887 // Shift right and accumulate
1888 defm SSRAvvi : NeonI_N2VShRAdd<0, 0b00010, "ssra", sra>;
1889 defm USRAvvi : NeonI_N2VShRAdd<1, 0b00010, "usra", srl>;
1891 // Rounding shift accumulate
1892 class N2VShiftAdd_R<bit q, bit u, bits<5> opcode, string asmop, string T,
1893 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1894 SDPatternOperator OpNode>
1895 : NeonI_2VShiftImm<q, u, opcode,
1896 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1897 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1898 [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1899 (Ty (OpNode (Ty VPRC:$Rn), (i32 ImmTy:$Imm))))))],
1901 let Constraints = "$src = $Rd";
1904 multiclass NeonI_N2VShRAdd_R<bit u, bits<5> opcode, string asmop,
1905 SDPatternOperator OpNode> {
1906 def _8B : N2VShiftAdd_R<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1908 let Inst{22-19} = 0b0001;
1911 def _4H : N2VShiftAdd_R<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1913 let Inst{22-20} = 0b001;
1916 def _2S : N2VShiftAdd_R<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1918 let Inst{22-21} = 0b01;
1921 def _16B : N2VShiftAdd_R<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1923 let Inst{22-19} = 0b0001;
1926 def _8H : N2VShiftAdd_R<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1928 let Inst{22-20} = 0b001;
1931 def _4S : N2VShiftAdd_R<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1933 let Inst{22-21} = 0b01;
1936 def _2D : N2VShiftAdd_R<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1942 // Rounding shift right and accumulate
1943 defm SRSRAvvi : NeonI_N2VShRAdd_R<0, 0b00110, "srsra", int_aarch64_neon_vsrshr>;
1944 defm URSRAvvi : NeonI_N2VShRAdd_R<1, 0b00110, "ursra", int_aarch64_neon_vurshr>;
1946 // Shift insert by immediate
1947 class N2VShiftIns<bit q, bit u, bits<5> opcode, string asmop, string T,
1948 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1949 SDPatternOperator OpNode>
1950 : NeonI_2VShiftImm<q, u, opcode,
1951 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1952 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1953 [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$src), (Ty VPRC:$Rn),
1954 (i32 ImmTy:$Imm))))],
1956 let Constraints = "$src = $Rd";
1959 // shift left insert (vector by immediate)
1960 multiclass NeonI_N2VShLIns<bit u, bits<5> opcode, string asmop> {
1961 def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
1962 int_aarch64_neon_vsli> {
1963 let Inst{22-19} = 0b0001;
1966 def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
1967 int_aarch64_neon_vsli> {
1968 let Inst{22-20} = 0b001;
1971 def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
1972 int_aarch64_neon_vsli> {
1973 let Inst{22-21} = 0b01;
1976 // 128-bit vector types
1977 def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
1978 int_aarch64_neon_vsli> {
1979 let Inst{22-19} = 0b0001;
1982 def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
1983 int_aarch64_neon_vsli> {
1984 let Inst{22-20} = 0b001;
1987 def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
1988 int_aarch64_neon_vsli> {
1989 let Inst{22-21} = 0b01;
1992 def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
1993 int_aarch64_neon_vsli> {
1998 // shift right insert (vector by immediate)
1999 multiclass NeonI_N2VShRIns<bit u, bits<5> opcode, string asmop> {
2000 // 64-bit vector types.
2001 def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
2002 int_aarch64_neon_vsri> {
2003 let Inst{22-19} = 0b0001;
2006 def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
2007 int_aarch64_neon_vsri> {
2008 let Inst{22-20} = 0b001;
2011 def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
2012 int_aarch64_neon_vsri> {
2013 let Inst{22-21} = 0b01;
2016 // 128-bit vector types
2017 def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2018 int_aarch64_neon_vsri> {
2019 let Inst{22-19} = 0b0001;
2022 def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2023 int_aarch64_neon_vsri> {
2024 let Inst{22-20} = 0b001;
2027 def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2028 int_aarch64_neon_vsri> {
2029 let Inst{22-21} = 0b01;
2032 def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2033 int_aarch64_neon_vsri> {
2038 // Shift left and insert
2039 defm SLIvvi : NeonI_N2VShLIns<0b1, 0b01010, "sli">;
2041 // Shift right and insert
2042 defm SRIvvi : NeonI_N2VShRIns<0b1, 0b01000, "sri">;
2044 class N2VShR_Narrow<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2045 string SrcT, Operand ImmTy>
2046 : NeonI_2VShiftImm<q, u, opcode,
2047 (outs VPR64:$Rd), (ins VPR128:$Rn, ImmTy:$Imm),
2048 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2051 class N2VShR_Narrow_Hi<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2052 string SrcT, Operand ImmTy>
2053 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
2054 (ins VPR128:$src, VPR128:$Rn, ImmTy:$Imm),
2055 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2057 let Constraints = "$src = $Rd";
2060 // left long shift by immediate
2061 multiclass NeonI_N2VShR_Narrow<bit u, bits<5> opcode, string asmop> {
2062 def _8B : N2VShR_Narrow<0b0, u, opcode, asmop, "8b", "8h", shr_imm8> {
2063 let Inst{22-19} = 0b0001;
2066 def _4H : N2VShR_Narrow<0b0, u, opcode, asmop, "4h", "4s", shr_imm16> {
2067 let Inst{22-20} = 0b001;
2070 def _2S : N2VShR_Narrow<0b0, u, opcode, asmop, "2s", "2d", shr_imm32> {
2071 let Inst{22-21} = 0b01;
2074 // Shift Narrow High
2075 def _16B : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "16b", "8h",
2077 let Inst{22-19} = 0b0001;
2080 def _8H : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "8h", "4s",
2082 let Inst{22-20} = 0b001;
2085 def _4S : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "4s", "2d",
2087 let Inst{22-21} = 0b01;
2091 // Shift right narrow
2092 defm SHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10000, "shrn">;
2094 // Shift right narrow (prefix Q is saturating, prefix R is rounding)
2095 defm QSHRUNvvi :NeonI_N2VShR_Narrow<0b1, 0b10000, "sqshrun">;
2096 defm RSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10001, "rshrn">;
2097 defm QRSHRUNvvi : NeonI_N2VShR_Narrow<0b1, 0b10001, "sqrshrun">;
2098 defm SQSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10010, "sqshrn">;
2099 defm UQSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10010, "uqshrn">;
2100 defm SQRSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10011, "sqrshrn">;
2101 defm UQRSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10011, "uqrshrn">;
2103 def Neon_combine_2D : PatFrag<(ops node:$Rm, node:$Rn),
2104 (v2i64 (concat_vectors (v1i64 node:$Rm),
2105 (v1i64 node:$Rn)))>;
2106 def Neon_combine_8H : PatFrag<(ops node:$Rm, node:$Rn),
2107 (v8i16 (concat_vectors (v4i16 node:$Rm),
2108 (v4i16 node:$Rn)))>;
2109 def Neon_combine_4S : PatFrag<(ops node:$Rm, node:$Rn),
2110 (v4i32 (concat_vectors (v2i32 node:$Rm),
2111 (v2i32 node:$Rn)))>;
2112 def Neon_combine_4f : PatFrag<(ops node:$Rm, node:$Rn),
2113 (v4f32 (concat_vectors (v2f32 node:$Rm),
2114 (v2f32 node:$Rn)))>;
2115 def Neon_combine_2d : PatFrag<(ops node:$Rm, node:$Rn),
2116 (v2f64 (concat_vectors (v1f64 node:$Rm),
2117 (v1f64 node:$Rn)))>;
2119 def Neon_lshrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2120 (v8i16 (srl (v8i16 node:$lhs),
2121 (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2122 def Neon_lshrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2123 (v4i32 (srl (v4i32 node:$lhs),
2124 (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2125 def Neon_lshrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2126 (v2i64 (srl (v2i64 node:$lhs),
2127 (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2128 def Neon_ashrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2129 (v8i16 (sra (v8i16 node:$lhs),
2130 (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2131 def Neon_ashrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2132 (v4i32 (sra (v4i32 node:$lhs),
2133 (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2134 def Neon_ashrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2135 (v2i64 (sra (v2i64 node:$lhs),
2136 (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2138 // Normal shift right narrow is matched by IR (srl/sra, trunc, concat_vectors)
2139 multiclass Neon_shiftNarrow_patterns<string shr> {
2140 def : Pat<(v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H") VPR128:$Rn,
2141 (i32 shr_imm8:$Imm)))),
2142 (SHRNvvi_8B VPR128:$Rn, imm:$Imm)>;
2143 def : Pat<(v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S") VPR128:$Rn,
2144 (i32 shr_imm16:$Imm)))),
2145 (SHRNvvi_4H VPR128:$Rn, imm:$Imm)>;
2146 def : Pat<(v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D") VPR128:$Rn,
2147 (i32 shr_imm32:$Imm)))),
2148 (SHRNvvi_2S VPR128:$Rn, imm:$Imm)>;
2150 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2151 (v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H")
2152 VPR128:$Rn, (i32 shr_imm8:$Imm))))))),
2153 (SHRNvvi_16B (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
2154 VPR128:$Rn, imm:$Imm)>;
2155 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2156 (v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S")
2157 VPR128:$Rn, (i32 shr_imm16:$Imm))))))),
2158 (SHRNvvi_8H (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2159 VPR128:$Rn, imm:$Imm)>;
2160 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2161 (v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D")
2162 VPR128:$Rn, (i32 shr_imm32:$Imm))))))),
2163 (SHRNvvi_4S (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2164 VPR128:$Rn, imm:$Imm)>;
2167 multiclass Neon_shiftNarrow_QR_patterns<SDPatternOperator op, string prefix> {
2168 def : Pat<(v8i8 (op (v8i16 VPR128:$Rn), shr_imm8:$Imm)),
2169 (!cast<Instruction>(prefix # "_8B") VPR128:$Rn, imm:$Imm)>;
2170 def : Pat<(v4i16 (op (v4i32 VPR128:$Rn), shr_imm16:$Imm)),
2171 (!cast<Instruction>(prefix # "_4H") VPR128:$Rn, imm:$Imm)>;
2172 def : Pat<(v2i32 (op (v2i64 VPR128:$Rn), shr_imm32:$Imm)),
2173 (!cast<Instruction>(prefix # "_2S") VPR128:$Rn, imm:$Imm)>;
2175 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2176 (v1i64 (bitconvert (v8i8
2177 (op (v8i16 VPR128:$Rn), shr_imm8:$Imm))))),
2178 (!cast<Instruction>(prefix # "_16B")
2179 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2180 VPR128:$Rn, imm:$Imm)>;
2181 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2182 (v1i64 (bitconvert (v4i16
2183 (op (v4i32 VPR128:$Rn), shr_imm16:$Imm))))),
2184 (!cast<Instruction>(prefix # "_8H")
2185 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2186 VPR128:$Rn, imm:$Imm)>;
2187 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2188 (v1i64 (bitconvert (v2i32
2189 (op (v2i64 VPR128:$Rn), shr_imm32:$Imm))))),
2190 (!cast<Instruction>(prefix # "_4S")
2191 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2192 VPR128:$Rn, imm:$Imm)>;
2195 defm : Neon_shiftNarrow_patterns<"lshr">;
2196 defm : Neon_shiftNarrow_patterns<"ashr">;
2198 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrun, "QSHRUNvvi">;
2199 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vrshrn, "RSHRNvvi">;
2200 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrun, "QRSHRUNvvi">;
2201 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrn, "SQSHRNvvi">;
2202 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqshrn, "UQSHRNvvi">;
2203 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrn, "SQRSHRNvvi">;
2204 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqrshrn, "UQRSHRNvvi">;
2206 // Convert fix-point and float-pointing
2207 class N2VCvt_Fx<bit q, bit u, bits<5> opcode, string asmop, string T,
2208 RegisterOperand VPRC, ValueType DestTy, ValueType SrcTy,
2209 Operand ImmTy, SDPatternOperator IntOp>
2210 : NeonI_2VShiftImm<q, u, opcode,
2211 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
2212 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2213 [(set (DestTy VPRC:$Rd), (DestTy (IntOp (SrcTy VPRC:$Rn),
2214 (i32 ImmTy:$Imm))))],
2217 multiclass NeonI_N2VCvt_Fx2fp<bit u, bits<5> opcode, string asmop,
2218 SDPatternOperator IntOp> {
2219 def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2f32, v2i32,
2221 let Inst{22-21} = 0b01;
2224 def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4f32, v4i32,
2226 let Inst{22-21} = 0b01;
2229 def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2f64, v2i64,
2235 multiclass NeonI_N2VCvt_Fp2fx<bit u, bits<5> opcode, string asmop,
2236 SDPatternOperator IntOp> {
2237 def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2i32, v2f32,
2239 let Inst{22-21} = 0b01;
2242 def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4i32, v4f32,
2244 let Inst{22-21} = 0b01;
2247 def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2i64, v2f64,
2253 // Convert fixed-point to floating-point
2254 defm VCVTxs2f : NeonI_N2VCvt_Fx2fp<0, 0b11100, "scvtf",
2255 int_arm_neon_vcvtfxs2fp>;
2256 defm VCVTxu2f : NeonI_N2VCvt_Fx2fp<1, 0b11100, "ucvtf",
2257 int_arm_neon_vcvtfxu2fp>;
2259 // Convert floating-point to fixed-point
2260 defm VCVTf2xs : NeonI_N2VCvt_Fp2fx<0, 0b11111, "fcvtzs",
2261 int_arm_neon_vcvtfp2fxs>;
2262 defm VCVTf2xu : NeonI_N2VCvt_Fp2fx<1, 0b11111, "fcvtzu",
2263 int_arm_neon_vcvtfp2fxu>;
2265 multiclass Neon_sshll2_0<SDNode ext>
2267 def _v8i8 : PatFrag<(ops node:$Rn),
2268 (v8i16 (ext (v8i8 (Neon_High16B node:$Rn))))>;
2269 def _v4i16 : PatFrag<(ops node:$Rn),
2270 (v4i32 (ext (v4i16 (Neon_High8H node:$Rn))))>;
2271 def _v2i32 : PatFrag<(ops node:$Rn),
2272 (v2i64 (ext (v2i32 (Neon_High4S node:$Rn))))>;
2275 defm NI_sext_high : Neon_sshll2_0<sext>;
2276 defm NI_zext_high : Neon_sshll2_0<zext>;
2279 //===----------------------------------------------------------------------===//
2280 // Multiclasses for NeonI_Across
2281 //===----------------------------------------------------------------------===//
2285 multiclass NeonI_2VAcross_1<bit u, bits<5> opcode,
2286 string asmop, SDPatternOperator opnode>
2288 def _1h8b: NeonI_2VAcross<0b0, u, 0b00, opcode,
2289 (outs FPR16:$Rd), (ins VPR64:$Rn),
2290 asmop # "\t$Rd, $Rn.8b",
2291 [(set (v1i16 FPR16:$Rd),
2292 (v1i16 (opnode (v8i8 VPR64:$Rn))))],
2295 def _1h16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2296 (outs FPR16:$Rd), (ins VPR128:$Rn),
2297 asmop # "\t$Rd, $Rn.16b",
2298 [(set (v1i16 FPR16:$Rd),
2299 (v1i16 (opnode (v16i8 VPR128:$Rn))))],
2302 def _1s4h: NeonI_2VAcross<0b0, u, 0b01, opcode,
2303 (outs FPR32:$Rd), (ins VPR64:$Rn),
2304 asmop # "\t$Rd, $Rn.4h",
2305 [(set (v1i32 FPR32:$Rd),
2306 (v1i32 (opnode (v4i16 VPR64:$Rn))))],
2309 def _1s8h: NeonI_2VAcross<0b1, u, 0b01, opcode,
2310 (outs FPR32:$Rd), (ins VPR128:$Rn),
2311 asmop # "\t$Rd, $Rn.8h",
2312 [(set (v1i32 FPR32:$Rd),
2313 (v1i32 (opnode (v8i16 VPR128:$Rn))))],
2316 // _1d2s doesn't exist!
2318 def _1d4s: NeonI_2VAcross<0b1, u, 0b10, opcode,
2319 (outs FPR64:$Rd), (ins VPR128:$Rn),
2320 asmop # "\t$Rd, $Rn.4s",
2321 [(set (v1i64 FPR64:$Rd),
2322 (v1i64 (opnode (v4i32 VPR128:$Rn))))],
2326 defm SADDLV : NeonI_2VAcross_1<0b0, 0b00011, "saddlv", int_aarch64_neon_saddlv>;
2327 defm UADDLV : NeonI_2VAcross_1<0b1, 0b00011, "uaddlv", int_aarch64_neon_uaddlv>;
2331 multiclass NeonI_2VAcross_2<bit u, bits<5> opcode,
2332 string asmop, SDPatternOperator opnode>
2334 def _1b8b: NeonI_2VAcross<0b0, u, 0b00, opcode,
2335 (outs FPR8:$Rd), (ins VPR64:$Rn),
2336 asmop # "\t$Rd, $Rn.8b",
2337 [(set (v1i8 FPR8:$Rd),
2338 (v1i8 (opnode (v8i8 VPR64:$Rn))))],
2341 def _1b16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2342 (outs FPR8:$Rd), (ins VPR128:$Rn),
2343 asmop # "\t$Rd, $Rn.16b",
2344 [(set (v1i8 FPR8:$Rd),
2345 (v1i8 (opnode (v16i8 VPR128:$Rn))))],
2348 def _1h4h: NeonI_2VAcross<0b0, u, 0b01, opcode,
2349 (outs FPR16:$Rd), (ins VPR64:$Rn),
2350 asmop # "\t$Rd, $Rn.4h",
2351 [(set (v1i16 FPR16:$Rd),
2352 (v1i16 (opnode (v4i16 VPR64:$Rn))))],
2355 def _1h8h: NeonI_2VAcross<0b1, u, 0b01, opcode,
2356 (outs FPR16:$Rd), (ins VPR128:$Rn),
2357 asmop # "\t$Rd, $Rn.8h",
2358 [(set (v1i16 FPR16:$Rd),
2359 (v1i16 (opnode (v8i16 VPR128:$Rn))))],
2362 // _1s2s doesn't exist!
2364 def _1s4s: NeonI_2VAcross<0b1, u, 0b10, opcode,
2365 (outs FPR32:$Rd), (ins VPR128:$Rn),
2366 asmop # "\t$Rd, $Rn.4s",
2367 [(set (v1i32 FPR32:$Rd),
2368 (v1i32 (opnode (v4i32 VPR128:$Rn))))],
2372 defm SMAXV : NeonI_2VAcross_2<0b0, 0b01010, "smaxv", int_aarch64_neon_smaxv>;
2373 defm UMAXV : NeonI_2VAcross_2<0b1, 0b01010, "umaxv", int_aarch64_neon_umaxv>;
2375 defm SMINV : NeonI_2VAcross_2<0b0, 0b11010, "sminv", int_aarch64_neon_sminv>;
2376 defm UMINV : NeonI_2VAcross_2<0b1, 0b11010, "uminv", int_aarch64_neon_uminv>;
2378 defm ADDV : NeonI_2VAcross_2<0b0, 0b11011, "addv", int_aarch64_neon_vaddv>;
2382 multiclass NeonI_2VAcross_3<bit u, bits<5> opcode, bits<2> size,
2383 string asmop, SDPatternOperator opnode> {
2384 def _1s4s: NeonI_2VAcross<0b1, u, size, opcode,
2385 (outs FPR32:$Rd), (ins VPR128:$Rn),
2386 asmop # "\t$Rd, $Rn.4s",
2387 [(set (v1f32 FPR32:$Rd),
2388 (v1f32 (opnode (v4f32 VPR128:$Rn))))],
2392 defm FMAXNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b00, "fmaxnmv",
2393 int_aarch64_neon_vmaxnmv>;
2394 defm FMINNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b10, "fminnmv",
2395 int_aarch64_neon_vminnmv>;
2397 defm FMAXV : NeonI_2VAcross_3<0b1, 0b01111, 0b00, "fmaxv",
2398 int_aarch64_neon_vmaxv>;
2399 defm FMINV : NeonI_2VAcross_3<0b1, 0b01111, 0b10, "fminv",
2400 int_aarch64_neon_vminv>;
2402 // The followings are for instruction class (Perm)
2404 class NeonI_Permute<bit q, bits<2> size, bits<3> opcode,
2405 string asmop, RegisterOperand OpVPR, string OpS,
2406 SDPatternOperator opnode, ValueType Ty>
2407 : NeonI_Perm<q, size, opcode,
2408 (outs OpVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2409 asmop # "\t$Rd." # OpS # ", $Rn." # OpS # ", $Rm." # OpS,
2410 [(set (Ty OpVPR:$Rd),
2411 (Ty (opnode (Ty OpVPR:$Rn), (Ty OpVPR:$Rm))))],
2414 multiclass NeonI_Perm_pat<bits<3> opcode, string asmop,
2415 SDPatternOperator opnode> {
2416 def _8b : NeonI_Permute<0b0, 0b00, opcode, asmop,
2417 VPR64, "8b", opnode, v8i8>;
2418 def _16b : NeonI_Permute<0b1, 0b00, opcode, asmop,
2419 VPR128, "16b",opnode, v16i8>;
2420 def _4h : NeonI_Permute<0b0, 0b01, opcode, asmop,
2421 VPR64, "4h", opnode, v4i16>;
2422 def _8h : NeonI_Permute<0b1, 0b01, opcode, asmop,
2423 VPR128, "8h", opnode, v8i16>;
2424 def _2s : NeonI_Permute<0b0, 0b10, opcode, asmop,
2425 VPR64, "2s", opnode, v2i32>;
2426 def _4s : NeonI_Permute<0b1, 0b10, opcode, asmop,
2427 VPR128, "4s", opnode, v4i32>;
2428 def _2d : NeonI_Permute<0b1, 0b11, opcode, asmop,
2429 VPR128, "2d", opnode, v2i64>;
2432 defm UZP1vvv : NeonI_Perm_pat<0b001, "uzp1", Neon_uzp1>;
2433 defm TRN1vvv : NeonI_Perm_pat<0b010, "trn1", Neon_trn1>;
2434 defm ZIP1vvv : NeonI_Perm_pat<0b011, "zip1", Neon_zip1>;
2435 defm UZP2vvv : NeonI_Perm_pat<0b101, "uzp2", Neon_uzp2>;
2436 defm TRN2vvv : NeonI_Perm_pat<0b110, "trn2", Neon_trn2>;
2437 defm ZIP2vvv : NeonI_Perm_pat<0b111, "zip2", Neon_zip2>;
2439 multiclass NeonI_Perm_float_pat<string INS, SDPatternOperator opnode> {
2440 def : Pat<(v2f32 (opnode (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
2441 (!cast<Instruction>(INS # "_2s") VPR64:$Rn, VPR64:$Rm)>;
2443 def : Pat<(v4f32 (opnode (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
2444 (!cast<Instruction>(INS # "_4s") VPR128:$Rn, VPR128:$Rm)>;
2446 def : Pat<(v2f64 (opnode (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
2447 (!cast<Instruction>(INS # "_2d") VPR128:$Rn, VPR128:$Rm)>;
2450 defm : NeonI_Perm_float_pat<"UZP1vvv", Neon_uzp1>;
2451 defm : NeonI_Perm_float_pat<"UZP2vvv", Neon_uzp2>;
2452 defm : NeonI_Perm_float_pat<"ZIP1vvv", Neon_zip1>;
2453 defm : NeonI_Perm_float_pat<"ZIP2vvv", Neon_zip2>;
2454 defm : NeonI_Perm_float_pat<"TRN1vvv", Neon_trn1>;
2455 defm : NeonI_Perm_float_pat<"TRN2vvv", Neon_trn2>;
2457 // The followings are for instruction class (3V Diff)
2459 // normal long/long2 pattern
2460 class NeonI_3VDL<bit q, bit u, bits<2> size, bits<4> opcode,
2461 string asmop, string ResS, string OpS,
2462 SDPatternOperator opnode, SDPatternOperator ext,
2463 RegisterOperand OpVPR,
2464 ValueType ResTy, ValueType OpTy>
2465 : NeonI_3VDiff<q, u, size, opcode,
2466 (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2467 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2468 [(set (ResTy VPR128:$Rd),
2469 (ResTy (opnode (ResTy (ext (OpTy OpVPR:$Rn))),
2470 (ResTy (ext (OpTy OpVPR:$Rm))))))],
2473 multiclass NeonI_3VDL_s<bit u, bits<4> opcode,
2474 string asmop, SDPatternOperator opnode,
2475 bit Commutable = 0> {
2476 let isCommutable = Commutable in {
2477 def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2478 opnode, sext, VPR64, v8i16, v8i8>;
2479 def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2480 opnode, sext, VPR64, v4i32, v4i16>;
2481 def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2482 opnode, sext, VPR64, v2i64, v2i32>;
2486 multiclass NeonI_3VDL2_s<bit u, bits<4> opcode, string asmop,
2487 SDPatternOperator opnode, bit Commutable = 0> {
2488 let isCommutable = Commutable in {
2489 def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2490 opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2491 def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2492 opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2493 def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2494 opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2498 multiclass NeonI_3VDL_u<bit u, bits<4> opcode, string asmop,
2499 SDPatternOperator opnode, bit Commutable = 0> {
2500 let isCommutable = Commutable in {
2501 def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2502 opnode, zext, VPR64, v8i16, v8i8>;
2503 def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2504 opnode, zext, VPR64, v4i32, v4i16>;
2505 def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2506 opnode, zext, VPR64, v2i64, v2i32>;
2510 multiclass NeonI_3VDL2_u<bit u, bits<4> opcode, string asmop,
2511 SDPatternOperator opnode, bit Commutable = 0> {
2512 let isCommutable = Commutable in {
2513 def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2514 opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2515 def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2516 opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2517 def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2518 opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2522 defm SADDLvvv : NeonI_3VDL_s<0b0, 0b0000, "saddl", add, 1>;
2523 defm UADDLvvv : NeonI_3VDL_u<0b1, 0b0000, "uaddl", add, 1>;
2525 defm SADDL2vvv : NeonI_3VDL2_s<0b0, 0b0000, "saddl2", add, 1>;
2526 defm UADDL2vvv : NeonI_3VDL2_u<0b1, 0b0000, "uaddl2", add, 1>;
2528 defm SSUBLvvv : NeonI_3VDL_s<0b0, 0b0010, "ssubl", sub, 0>;
2529 defm USUBLvvv : NeonI_3VDL_u<0b1, 0b0010, "usubl", sub, 0>;
2531 defm SSUBL2vvv : NeonI_3VDL2_s<0b0, 0b0010, "ssubl2", sub, 0>;
2532 defm USUBL2vvv : NeonI_3VDL2_u<0b1, 0b0010, "usubl2", sub, 0>;
2534 // normal wide/wide2 pattern
2535 class NeonI_3VDW<bit q, bit u, bits<2> size, bits<4> opcode,
2536 string asmop, string ResS, string OpS,
2537 SDPatternOperator opnode, SDPatternOperator ext,
2538 RegisterOperand OpVPR,
2539 ValueType ResTy, ValueType OpTy>
2540 : NeonI_3VDiff<q, u, size, opcode,
2541 (outs VPR128:$Rd), (ins VPR128:$Rn, OpVPR:$Rm),
2542 asmop # "\t$Rd." # ResS # ", $Rn." # ResS # ", $Rm." # OpS,
2543 [(set (ResTy VPR128:$Rd),
2544 (ResTy (opnode (ResTy VPR128:$Rn),
2545 (ResTy (ext (OpTy OpVPR:$Rm))))))],
2548 multiclass NeonI_3VDW_s<bit u, bits<4> opcode, string asmop,
2549 SDPatternOperator opnode> {
2550 def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2551 opnode, sext, VPR64, v8i16, v8i8>;
2552 def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2553 opnode, sext, VPR64, v4i32, v4i16>;
2554 def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2555 opnode, sext, VPR64, v2i64, v2i32>;
2558 defm SADDWvvv : NeonI_3VDW_s<0b0, 0b0001, "saddw", add>;
2559 defm SSUBWvvv : NeonI_3VDW_s<0b0, 0b0011, "ssubw", sub>;
2561 multiclass NeonI_3VDW2_s<bit u, bits<4> opcode, string asmop,
2562 SDPatternOperator opnode> {
2563 def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2564 opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2565 def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2566 opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2567 def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2568 opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2571 defm SADDW2vvv : NeonI_3VDW2_s<0b0, 0b0001, "saddw2", add>;
2572 defm SSUBW2vvv : NeonI_3VDW2_s<0b0, 0b0011, "ssubw2", sub>;
2574 multiclass NeonI_3VDW_u<bit u, bits<4> opcode, string asmop,
2575 SDPatternOperator opnode> {
2576 def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2577 opnode, zext, VPR64, v8i16, v8i8>;
2578 def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2579 opnode, zext, VPR64, v4i32, v4i16>;
2580 def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2581 opnode, zext, VPR64, v2i64, v2i32>;
2584 defm UADDWvvv : NeonI_3VDW_u<0b1, 0b0001, "uaddw", add>;
2585 defm USUBWvvv : NeonI_3VDW_u<0b1, 0b0011, "usubw", sub>;
2587 multiclass NeonI_3VDW2_u<bit u, bits<4> opcode, string asmop,
2588 SDPatternOperator opnode> {
2589 def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2590 opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2591 def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2592 opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2593 def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2594 opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2597 defm UADDW2vvv : NeonI_3VDW2_u<0b1, 0b0001, "uaddw2", add>;
2598 defm USUBW2vvv : NeonI_3VDW2_u<0b1, 0b0011, "usubw2", sub>;
2600 // Get the high half part of the vector element.
2601 multiclass NeonI_get_high {
2602 def _8h : PatFrag<(ops node:$Rn),
2603 (v8i8 (trunc (v8i16 (srl (v8i16 node:$Rn),
2604 (v8i16 (Neon_vdup (i32 8)))))))>;
2605 def _4s : PatFrag<(ops node:$Rn),
2606 (v4i16 (trunc (v4i32 (srl (v4i32 node:$Rn),
2607 (v4i32 (Neon_vdup (i32 16)))))))>;
2608 def _2d : PatFrag<(ops node:$Rn),
2609 (v2i32 (trunc (v2i64 (srl (v2i64 node:$Rn),
2610 (v2i64 (Neon_vdup (i32 32)))))))>;
2613 defm NI_get_hi : NeonI_get_high;
2615 // pattern for addhn/subhn with 2 operands
2616 class NeonI_3VDN_addhn_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2617 string asmop, string ResS, string OpS,
2618 SDPatternOperator opnode, SDPatternOperator get_hi,
2619 ValueType ResTy, ValueType OpTy>
2620 : NeonI_3VDiff<q, u, size, opcode,
2621 (outs VPR64:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2622 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2623 [(set (ResTy VPR64:$Rd),
2625 (OpTy (opnode (OpTy VPR128:$Rn),
2626 (OpTy VPR128:$Rm))))))],
2629 multiclass NeonI_3VDN_addhn_2Op<bit u, bits<4> opcode, string asmop,
2630 SDPatternOperator opnode, bit Commutable = 0> {
2631 let isCommutable = Commutable in {
2632 def _8b8h : NeonI_3VDN_addhn_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2633 opnode, NI_get_hi_8h, v8i8, v8i16>;
2634 def _4h4s : NeonI_3VDN_addhn_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2635 opnode, NI_get_hi_4s, v4i16, v4i32>;
2636 def _2s2d : NeonI_3VDN_addhn_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2637 opnode, NI_get_hi_2d, v2i32, v2i64>;
2641 defm ADDHNvvv : NeonI_3VDN_addhn_2Op<0b0, 0b0100, "addhn", add, 1>;
2642 defm SUBHNvvv : NeonI_3VDN_addhn_2Op<0b0, 0b0110, "subhn", sub, 0>;
2644 // pattern for operation with 2 operands
2645 class NeonI_3VD_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2646 string asmop, string ResS, string OpS,
2647 SDPatternOperator opnode,
2648 RegisterOperand ResVPR, RegisterOperand OpVPR,
2649 ValueType ResTy, ValueType OpTy>
2650 : NeonI_3VDiff<q, u, size, opcode,
2651 (outs ResVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2652 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2653 [(set (ResTy ResVPR:$Rd),
2654 (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))],
2657 // normal narrow pattern
2658 multiclass NeonI_3VDN_2Op<bit u, bits<4> opcode, string asmop,
2659 SDPatternOperator opnode, bit Commutable = 0> {
2660 let isCommutable = Commutable in {
2661 def _8b8h : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2662 opnode, VPR64, VPR128, v8i8, v8i16>;
2663 def _4h4s : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2664 opnode, VPR64, VPR128, v4i16, v4i32>;
2665 def _2s2d : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2666 opnode, VPR64, VPR128, v2i32, v2i64>;
2670 defm RADDHNvvv : NeonI_3VDN_2Op<0b1, 0b0100, "raddhn", int_arm_neon_vraddhn, 1>;
2671 defm RSUBHNvvv : NeonI_3VDN_2Op<0b1, 0b0110, "rsubhn", int_arm_neon_vrsubhn, 0>;
2673 // pattern for acle intrinsic with 3 operands
2674 class NeonI_3VDN_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2675 string asmop, string ResS, string OpS>
2676 : NeonI_3VDiff<q, u, size, opcode,
2677 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
2678 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2680 let Constraints = "$src = $Rd";
2681 let neverHasSideEffects = 1;
2684 multiclass NeonI_3VDN_3Op_v1<bit u, bits<4> opcode, string asmop> {
2685 def _16b8h : NeonI_3VDN_3Op<0b1, u, 0b00, opcode, asmop, "16b", "8h">;
2686 def _8h4s : NeonI_3VDN_3Op<0b1, u, 0b01, opcode, asmop, "8h", "4s">;
2687 def _4s2d : NeonI_3VDN_3Op<0b1, u, 0b10, opcode, asmop, "4s", "2d">;
2690 defm ADDHN2vvv : NeonI_3VDN_3Op_v1<0b0, 0b0100, "addhn2">;
2691 defm SUBHN2vvv : NeonI_3VDN_3Op_v1<0b0, 0b0110, "subhn2">;
2693 defm RADDHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0100, "raddhn2">;
2694 defm RSUBHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0110, "rsubhn2">;
2696 // Patterns have to be separate because there's a SUBREG_TO_REG in the output
2698 class NarrowHighHalfPat<Instruction INST, ValueType DstTy, ValueType SrcTy,
2699 SDPatternOperator coreop>
2700 : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2701 (v1i64 (bitconvert (DstTy (coreop (SrcTy VPR128:$Rn),
2702 (SrcTy VPR128:$Rm)))))),
2703 (INST (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2704 VPR128:$Rn, VPR128:$Rm)>;
2707 def : NarrowHighHalfPat<ADDHN2vvv_16b8h, v8i8, v8i16,
2708 BinOpFrag<(NI_get_hi_8h (add node:$LHS, node:$RHS))>>;
2709 def : NarrowHighHalfPat<ADDHN2vvv_8h4s, v4i16, v4i32,
2710 BinOpFrag<(NI_get_hi_4s (add node:$LHS, node:$RHS))>>;
2711 def : NarrowHighHalfPat<ADDHN2vvv_4s2d, v2i32, v2i64,
2712 BinOpFrag<(NI_get_hi_2d (add node:$LHS, node:$RHS))>>;
2715 def : NarrowHighHalfPat<SUBHN2vvv_16b8h, v8i8, v8i16,
2716 BinOpFrag<(NI_get_hi_8h (sub node:$LHS, node:$RHS))>>;
2717 def : NarrowHighHalfPat<SUBHN2vvv_8h4s, v4i16, v4i32,
2718 BinOpFrag<(NI_get_hi_4s (sub node:$LHS, node:$RHS))>>;
2719 def : NarrowHighHalfPat<SUBHN2vvv_4s2d, v2i32, v2i64,
2720 BinOpFrag<(NI_get_hi_2d (sub node:$LHS, node:$RHS))>>;
2723 def : NarrowHighHalfPat<RADDHN2vvv_16b8h, v8i8, v8i16, int_arm_neon_vraddhn>;
2724 def : NarrowHighHalfPat<RADDHN2vvv_8h4s, v4i16, v4i32, int_arm_neon_vraddhn>;
2725 def : NarrowHighHalfPat<RADDHN2vvv_4s2d, v2i32, v2i64, int_arm_neon_vraddhn>;
2728 def : NarrowHighHalfPat<RSUBHN2vvv_16b8h, v8i8, v8i16, int_arm_neon_vrsubhn>;
2729 def : NarrowHighHalfPat<RSUBHN2vvv_8h4s, v4i16, v4i32, int_arm_neon_vrsubhn>;
2730 def : NarrowHighHalfPat<RSUBHN2vvv_4s2d, v2i32, v2i64, int_arm_neon_vrsubhn>;
2732 // pattern that need to extend result
2733 class NeonI_3VDL_Ext<bit q, bit u, bits<2> size, bits<4> opcode,
2734 string asmop, string ResS, string OpS,
2735 SDPatternOperator opnode,
2736 RegisterOperand OpVPR,
2737 ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2738 : NeonI_3VDiff<q, u, size, opcode,
2739 (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2740 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2741 [(set (ResTy VPR128:$Rd),
2742 (ResTy (zext (OpSTy (opnode (OpTy OpVPR:$Rn),
2743 (OpTy OpVPR:$Rm))))))],
2746 multiclass NeonI_3VDL_zext<bit u, bits<4> opcode, string asmop,
2747 SDPatternOperator opnode, bit Commutable = 0> {
2748 let isCommutable = Commutable in {
2749 def _8h8b : NeonI_3VDL_Ext<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2750 opnode, VPR64, v8i16, v8i8, v8i8>;
2751 def _4s4h : NeonI_3VDL_Ext<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2752 opnode, VPR64, v4i32, v4i16, v4i16>;
2753 def _2d2s : NeonI_3VDL_Ext<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2754 opnode, VPR64, v2i64, v2i32, v2i32>;
2758 defm SABDLvvv : NeonI_3VDL_zext<0b0, 0b0111, "sabdl", int_arm_neon_vabds, 1>;
2759 defm UABDLvvv : NeonI_3VDL_zext<0b1, 0b0111, "uabdl", int_arm_neon_vabdu, 1>;
2761 multiclass NeonI_Op_High<SDPatternOperator op> {
2762 def _16B : PatFrag<(ops node:$Rn, node:$Rm),
2763 (op (v8i8 (Neon_High16B node:$Rn)),
2764 (v8i8 (Neon_High16B node:$Rm)))>;
2765 def _8H : PatFrag<(ops node:$Rn, node:$Rm),
2766 (op (v4i16 (Neon_High8H node:$Rn)),
2767 (v4i16 (Neon_High8H node:$Rm)))>;
2768 def _4S : PatFrag<(ops node:$Rn, node:$Rm),
2769 (op (v2i32 (Neon_High4S node:$Rn)),
2770 (v2i32 (Neon_High4S node:$Rm)))>;
2773 defm NI_sabdl_hi : NeonI_Op_High<int_arm_neon_vabds>;
2774 defm NI_uabdl_hi : NeonI_Op_High<int_arm_neon_vabdu>;
2775 defm NI_smull_hi : NeonI_Op_High<int_arm_neon_vmulls>;
2776 defm NI_umull_hi : NeonI_Op_High<int_arm_neon_vmullu>;
2777 defm NI_qdmull_hi : NeonI_Op_High<int_arm_neon_vqdmull>;
2778 defm NI_pmull_hi : NeonI_Op_High<int_arm_neon_vmullp>;
2780 multiclass NeonI_3VDL_Abd_u<bit u, bits<4> opcode, string asmop, string opnode,
2781 bit Commutable = 0> {
2782 let isCommutable = Commutable in {
2783 def _8h8b : NeonI_3VDL_Ext<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2784 !cast<PatFrag>(opnode # "_16B"),
2785 VPR128, v8i16, v16i8, v8i8>;
2786 def _4s4h : NeonI_3VDL_Ext<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2787 !cast<PatFrag>(opnode # "_8H"),
2788 VPR128, v4i32, v8i16, v4i16>;
2789 def _2d2s : NeonI_3VDL_Ext<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2790 !cast<PatFrag>(opnode # "_4S"),
2791 VPR128, v2i64, v4i32, v2i32>;
2795 defm SABDL2vvv : NeonI_3VDL_Abd_u<0b0, 0b0111, "sabdl2", "NI_sabdl_hi", 1>;
2796 defm UABDL2vvv : NeonI_3VDL_Abd_u<0b1, 0b0111, "uabdl2", "NI_uabdl_hi", 1>;
2798 // For pattern that need two operators being chained.
2799 class NeonI_3VDL_Aba<bit q, bit u, bits<2> size, bits<4> opcode,
2800 string asmop, string ResS, string OpS,
2801 SDPatternOperator opnode, SDPatternOperator subop,
2802 RegisterOperand OpVPR,
2803 ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2804 : NeonI_3VDiff<q, u, size, opcode,
2805 (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2806 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2807 [(set (ResTy VPR128:$Rd),
2809 (ResTy VPR128:$src),
2810 (ResTy (zext (OpSTy (subop (OpTy OpVPR:$Rn),
2811 (OpTy OpVPR:$Rm))))))))],
2813 let Constraints = "$src = $Rd";
2816 multiclass NeonI_3VDL_Aba_v1<bit u, bits<4> opcode, string asmop,
2817 SDPatternOperator opnode, SDPatternOperator subop>{
2818 def _8h8b : NeonI_3VDL_Aba<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2819 opnode, subop, VPR64, v8i16, v8i8, v8i8>;
2820 def _4s4h : NeonI_3VDL_Aba<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2821 opnode, subop, VPR64, v4i32, v4i16, v4i16>;
2822 def _2d2s : NeonI_3VDL_Aba<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2823 opnode, subop, VPR64, v2i64, v2i32, v2i32>;
2826 defm SABALvvv : NeonI_3VDL_Aba_v1<0b0, 0b0101, "sabal",
2827 add, int_arm_neon_vabds>;
2828 defm UABALvvv : NeonI_3VDL_Aba_v1<0b1, 0b0101, "uabal",
2829 add, int_arm_neon_vabdu>;
2831 multiclass NeonI_3VDL2_Aba_v1<bit u, bits<4> opcode, string asmop,
2832 SDPatternOperator opnode, string subop> {
2833 def _8h8b : NeonI_3VDL_Aba<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2834 opnode, !cast<PatFrag>(subop # "_16B"),
2835 VPR128, v8i16, v16i8, v8i8>;
2836 def _4s4h : NeonI_3VDL_Aba<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2837 opnode, !cast<PatFrag>(subop # "_8H"),
2838 VPR128, v4i32, v8i16, v4i16>;
2839 def _2d2s : NeonI_3VDL_Aba<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2840 opnode, !cast<PatFrag>(subop # "_4S"),
2841 VPR128, v2i64, v4i32, v2i32>;
2844 defm SABAL2vvv : NeonI_3VDL2_Aba_v1<0b0, 0b0101, "sabal2", add,
2846 defm UABAL2vvv : NeonI_3VDL2_Aba_v1<0b1, 0b0101, "uabal2", add,
2849 // Long pattern with 2 operands
2850 multiclass NeonI_3VDL_2Op<bit u, bits<4> opcode, string asmop,
2851 SDPatternOperator opnode, bit Commutable = 0> {
2852 let isCommutable = Commutable in {
2853 def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2854 opnode, VPR128, VPR64, v8i16, v8i8>;
2855 def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2856 opnode, VPR128, VPR64, v4i32, v4i16>;
2857 def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2858 opnode, VPR128, VPR64, v2i64, v2i32>;
2862 defm SMULLvvv : NeonI_3VDL_2Op<0b0, 0b1100, "smull", int_arm_neon_vmulls, 1>;
2863 defm UMULLvvv : NeonI_3VDL_2Op<0b1, 0b1100, "umull", int_arm_neon_vmullu, 1>;
2865 class NeonI_3VDL2_2Op_mull<bit q, bit u, bits<2> size, bits<4> opcode,
2866 string asmop, string ResS, string OpS,
2867 SDPatternOperator opnode,
2868 ValueType ResTy, ValueType OpTy>
2869 : NeonI_3VDiff<q, u, size, opcode,
2870 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2871 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2872 [(set (ResTy VPR128:$Rd),
2873 (ResTy (opnode (OpTy VPR128:$Rn), (OpTy VPR128:$Rm))))],
2876 multiclass NeonI_3VDL2_2Op_mull_v1<bit u, bits<4> opcode, string asmop,
2877 string opnode, bit Commutable = 0> {
2878 let isCommutable = Commutable in {
2879 def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2880 !cast<PatFrag>(opnode # "_16B"),
2882 def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2883 !cast<PatFrag>(opnode # "_8H"),
2885 def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2886 !cast<PatFrag>(opnode # "_4S"),
2891 defm SMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b0, 0b1100, "smull2",
2893 defm UMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b1, 0b1100, "umull2",
2896 // Long pattern with 3 operands
2897 class NeonI_3VDL_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2898 string asmop, string ResS, string OpS,
2899 SDPatternOperator opnode,
2900 ValueType ResTy, ValueType OpTy>
2901 : NeonI_3VDiff<q, u, size, opcode,
2902 (outs VPR128:$Rd), (ins VPR128:$src, VPR64:$Rn, VPR64:$Rm),
2903 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2904 [(set (ResTy VPR128:$Rd),
2906 (ResTy VPR128:$src),
2907 (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))))],
2909 let Constraints = "$src = $Rd";
2912 multiclass NeonI_3VDL_3Op_v1<bit u, bits<4> opcode, string asmop,
2913 SDPatternOperator opnode> {
2914 def _8h8b : NeonI_3VDL_3Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2915 opnode, v8i16, v8i8>;
2916 def _4s4h : NeonI_3VDL_3Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2917 opnode, v4i32, v4i16>;
2918 def _2d2s : NeonI_3VDL_3Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2919 opnode, v2i64, v2i32>;
2922 def Neon_smlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2924 (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
2926 def Neon_umlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2928 (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
2930 def Neon_smlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2932 (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
2934 def Neon_umlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2936 (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
2938 defm SMLALvvv : NeonI_3VDL_3Op_v1<0b0, 0b1000, "smlal", Neon_smlal>;
2939 defm UMLALvvv : NeonI_3VDL_3Op_v1<0b1, 0b1000, "umlal", Neon_umlal>;
2941 defm SMLSLvvv : NeonI_3VDL_3Op_v1<0b0, 0b1010, "smlsl", Neon_smlsl>;
2942 defm UMLSLvvv : NeonI_3VDL_3Op_v1<0b1, 0b1010, "umlsl", Neon_umlsl>;
2944 class NeonI_3VDL2_3Op_mlas<bit q, bit u, bits<2> size, bits<4> opcode,
2945 string asmop, string ResS, string OpS,
2946 SDPatternOperator subop, SDPatternOperator opnode,
2947 RegisterOperand OpVPR,
2948 ValueType ResTy, ValueType OpTy>
2949 : NeonI_3VDiff<q, u, size, opcode,
2950 (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2951 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2952 [(set (ResTy VPR128:$Rd),
2954 (ResTy VPR128:$src),
2955 (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))))],
2957 let Constraints = "$src = $Rd";
2960 multiclass NeonI_3VDL2_3Op_mlas_v1<bit u, bits<4> opcode, string asmop,
2961 SDPatternOperator subop, string opnode> {
2962 def _8h16b : NeonI_3VDL2_3Op_mlas<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2963 subop, !cast<PatFrag>(opnode # "_16B"),
2964 VPR128, v8i16, v16i8>;
2965 def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2966 subop, !cast<PatFrag>(opnode # "_8H"),
2967 VPR128, v4i32, v8i16>;
2968 def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2969 subop, !cast<PatFrag>(opnode # "_4S"),
2970 VPR128, v2i64, v4i32>;
2973 defm SMLAL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1000, "smlal2",
2974 add, "NI_smull_hi">;
2975 defm UMLAL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1000, "umlal2",
2976 add, "NI_umull_hi">;
2978 defm SMLSL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1010, "smlsl2",
2979 sub, "NI_smull_hi">;
2980 defm UMLSL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1010, "umlsl2",
2981 sub, "NI_umull_hi">;
2983 multiclass NeonI_3VDL_qdmlal_3Op_v2<bit u, bits<4> opcode, string asmop,
2984 SDPatternOperator opnode> {
2985 def _4s4h : NeonI_3VDL2_3Op_mlas<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2986 opnode, int_arm_neon_vqdmull,
2987 VPR64, v4i32, v4i16>;
2988 def _2d2s : NeonI_3VDL2_3Op_mlas<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2989 opnode, int_arm_neon_vqdmull,
2990 VPR64, v2i64, v2i32>;
2993 defm SQDMLALvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1001, "sqdmlal",
2994 int_arm_neon_vqadds>;
2995 defm SQDMLSLvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1011, "sqdmlsl",
2996 int_arm_neon_vqsubs>;
2998 multiclass NeonI_3VDL_v2<bit u, bits<4> opcode, string asmop,
2999 SDPatternOperator opnode, bit Commutable = 0> {
3000 let isCommutable = Commutable in {
3001 def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3002 opnode, VPR128, VPR64, v4i32, v4i16>;
3003 def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3004 opnode, VPR128, VPR64, v2i64, v2i32>;
3008 defm SQDMULLvvv : NeonI_3VDL_v2<0b0, 0b1101, "sqdmull",
3009 int_arm_neon_vqdmull, 1>;
3011 multiclass NeonI_3VDL2_2Op_mull_v2<bit u, bits<4> opcode, string asmop,
3012 string opnode, bit Commutable = 0> {
3013 let isCommutable = Commutable in {
3014 def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3015 !cast<PatFrag>(opnode # "_8H"),
3017 def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3018 !cast<PatFrag>(opnode # "_4S"),
3023 defm SQDMULL2vvv : NeonI_3VDL2_2Op_mull_v2<0b0, 0b1101, "sqdmull2",
3026 multiclass NeonI_3VDL2_3Op_qdmlal_v2<bit u, bits<4> opcode, string asmop,
3027 SDPatternOperator opnode> {
3028 def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3029 opnode, NI_qdmull_hi_8H,
3030 VPR128, v4i32, v8i16>;
3031 def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3032 opnode, NI_qdmull_hi_4S,
3033 VPR128, v2i64, v4i32>;
3036 defm SQDMLAL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1001, "sqdmlal2",
3037 int_arm_neon_vqadds>;
3038 defm SQDMLSL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1011, "sqdmlsl2",
3039 int_arm_neon_vqsubs>;
3041 multiclass NeonI_3VDL_v3<bit u, bits<4> opcode, string asmop,
3042 SDPatternOperator opnode, bit Commutable = 0> {
3043 let isCommutable = Commutable in {
3044 def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3045 opnode, VPR128, VPR64, v8i16, v8i8>;
3047 def _1q1d : NeonI_3VDiff<0b0, u, 0b11, opcode,
3048 (outs VPR128:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
3049 asmop # "\t$Rd.1q, $Rn.1d, $Rm.1d",
3054 defm PMULLvvv : NeonI_3VDL_v3<0b0, 0b1110, "pmull", int_arm_neon_vmullp, 1>;
3056 multiclass NeonI_3VDL2_2Op_mull_v3<bit u, bits<4> opcode, string asmop,
3057 string opnode, bit Commutable = 0> {
3058 let isCommutable = Commutable in {
3059 def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3060 !cast<PatFrag>(opnode # "_16B"),
3063 def _1q2d : NeonI_3VDiff<0b1, u, 0b11, opcode,
3064 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3065 asmop # "\t$Rd.1q, $Rn.2d, $Rm.2d",
3070 defm PMULL2vvv : NeonI_3VDL2_2Op_mull_v3<0b0, 0b1110, "pmull2", "NI_pmull_hi",
3073 // End of implementation for instruction class (3V Diff)
3075 // The followings are vector load/store multiple N-element structure
3076 // (class SIMD lselem).
3078 // ld1: load multiple 1-element structure to 1/2/3/4 registers.
3079 // ld2/ld3/ld4: load multiple N-element structure to N registers (N = 2, 3, 4).
3080 // The structure consists of a sequence of sets of N values.
3081 // The first element of the structure is placed in the first lane
3082 // of the first first vector, the second element in the first lane
3083 // of the second vector, and so on.
3084 // E.g. LD1_3V_2S will load 32-bit elements {A, B, C, D, E, F} sequentially into
3085 // the three 64-bit vectors list {BA, DC, FE}.
3086 // E.g. LD3_2S will load 32-bit elements {A, B, C, D, E, F} into the three
3087 // 64-bit vectors list {DA, EB, FC}.
3088 // Store instructions store multiple structure to N registers like load.
3091 class NeonI_LDVList<bit q, bits<4> opcode, bits<2> size,
3092 RegisterOperand VecList, string asmop>
3093 : NeonI_LdStMult<q, 1, opcode, size,
3094 (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3095 asmop # "\t$Rt, [$Rn]",
3099 let neverHasSideEffects = 1;
3102 multiclass LDVList_BHSD<bits<4> opcode, string List, string asmop> {
3103 def _8B : NeonI_LDVList<0, opcode, 0b00,
3104 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3106 def _4H : NeonI_LDVList<0, opcode, 0b01,
3107 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3109 def _2S : NeonI_LDVList<0, opcode, 0b10,
3110 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3112 def _16B : NeonI_LDVList<1, opcode, 0b00,
3113 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3115 def _8H : NeonI_LDVList<1, opcode, 0b01,
3116 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3118 def _4S : NeonI_LDVList<1, opcode, 0b10,
3119 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3121 def _2D : NeonI_LDVList<1, opcode, 0b11,
3122 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3125 // Load multiple N-element structure to N consecutive registers (N = 1,2,3,4)
3126 defm LD1 : LDVList_BHSD<0b0111, "VOne", "ld1">;
3127 def LD1_1D : NeonI_LDVList<0, 0b0111, 0b11, VOne1D_operand, "ld1">;
3129 defm LD2 : LDVList_BHSD<0b1000, "VPair", "ld2">;
3131 defm LD3 : LDVList_BHSD<0b0100, "VTriple", "ld3">;
3133 defm LD4 : LDVList_BHSD<0b0000, "VQuad", "ld4">;
3135 // Load multiple 1-element structure to N consecutive registers (N = 2,3,4)
3136 defm LD1x2 : LDVList_BHSD<0b1010, "VPair", "ld1">;
3137 def LD1x2_1D : NeonI_LDVList<0, 0b1010, 0b11, VPair1D_operand, "ld1">;
3139 defm LD1x3 : LDVList_BHSD<0b0110, "VTriple", "ld1">;
3140 def LD1x3_1D : NeonI_LDVList<0, 0b0110, 0b11, VTriple1D_operand, "ld1">;
3142 defm LD1x4 : LDVList_BHSD<0b0010, "VQuad", "ld1">;
3143 def LD1x4_1D : NeonI_LDVList<0, 0b0010, 0b11, VQuad1D_operand, "ld1">;
3145 class NeonI_STVList<bit q, bits<4> opcode, bits<2> size,
3146 RegisterOperand VecList, string asmop>
3147 : NeonI_LdStMult<q, 0, opcode, size,
3148 (outs), (ins GPR64xsp:$Rn, VecList:$Rt),
3149 asmop # "\t$Rt, [$Rn]",
3153 let neverHasSideEffects = 1;
3156 multiclass STVList_BHSD<bits<4> opcode, string List, string asmop> {
3157 def _8B : NeonI_STVList<0, opcode, 0b00,
3158 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3160 def _4H : NeonI_STVList<0, opcode, 0b01,
3161 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3163 def _2S : NeonI_STVList<0, opcode, 0b10,
3164 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3166 def _16B : NeonI_STVList<1, opcode, 0b00,
3167 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3169 def _8H : NeonI_STVList<1, opcode, 0b01,
3170 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3172 def _4S : NeonI_STVList<1, opcode, 0b10,
3173 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3175 def _2D : NeonI_STVList<1, opcode, 0b11,
3176 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3179 // Store multiple N-element structures from N registers (N = 1,2,3,4)
3180 defm ST1 : STVList_BHSD<0b0111, "VOne", "st1">;
3181 def ST1_1D : NeonI_STVList<0, 0b0111, 0b11, VOne1D_operand, "st1">;
3183 defm ST2 : STVList_BHSD<0b1000, "VPair", "st2">;
3185 defm ST3 : STVList_BHSD<0b0100, "VTriple", "st3">;
3187 defm ST4 : STVList_BHSD<0b0000, "VQuad", "st4">;
3189 // Store multiple 1-element structures from N consecutive registers (N = 2,3,4)
3190 defm ST1x2 : STVList_BHSD<0b1010, "VPair", "st1">;
3191 def ST1x2_1D : NeonI_STVList<0, 0b1010, 0b11, VPair1D_operand, "st1">;
3193 defm ST1x3 : STVList_BHSD<0b0110, "VTriple", "st1">;
3194 def ST1x3_1D : NeonI_STVList<0, 0b0110, 0b11, VTriple1D_operand, "st1">;
3196 defm ST1x4 : STVList_BHSD<0b0010, "VQuad", "st1">;
3197 def ST1x4_1D : NeonI_STVList<0, 0b0010, 0b11, VQuad1D_operand, "st1">;
3199 def : Pat<(v2f64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3200 def : Pat<(v2i64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3202 def : Pat<(v4f32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3203 def : Pat<(v4i32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3205 def : Pat<(v8i16 (load GPR64xsp:$addr)), (LD1_8H GPR64xsp:$addr)>;
3206 def : Pat<(v16i8 (load GPR64xsp:$addr)), (LD1_16B GPR64xsp:$addr)>;
3208 def : Pat<(v1f64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3209 def : Pat<(v1i64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3211 def : Pat<(v2f32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3212 def : Pat<(v2i32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3214 def : Pat<(v4i16 (load GPR64xsp:$addr)), (LD1_4H GPR64xsp:$addr)>;
3215 def : Pat<(v8i8 (load GPR64xsp:$addr)), (LD1_8B GPR64xsp:$addr)>;
3217 def : Pat<(store (v2i64 VPR128:$value), GPR64xsp:$addr),
3218 (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3219 def : Pat<(store (v2f64 VPR128:$value), GPR64xsp:$addr),
3220 (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3222 def : Pat<(store (v4i32 VPR128:$value), GPR64xsp:$addr),
3223 (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3224 def : Pat<(store (v4f32 VPR128:$value), GPR64xsp:$addr),
3225 (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3227 def : Pat<(store (v8i16 VPR128:$value), GPR64xsp:$addr),
3228 (ST1_8H GPR64xsp:$addr, VPR128:$value)>;
3229 def : Pat<(store (v16i8 VPR128:$value), GPR64xsp:$addr),
3230 (ST1_16B GPR64xsp:$addr, VPR128:$value)>;
3232 def : Pat<(store (v1i64 VPR64:$value), GPR64xsp:$addr),
3233 (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3234 def : Pat<(store (v1f64 VPR64:$value), GPR64xsp:$addr),
3235 (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3237 def : Pat<(store (v2i32 VPR64:$value), GPR64xsp:$addr),
3238 (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3239 def : Pat<(store (v2f32 VPR64:$value), GPR64xsp:$addr),
3240 (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3242 def : Pat<(store (v4i16 VPR64:$value), GPR64xsp:$addr),
3243 (ST1_4H GPR64xsp:$addr, VPR64:$value)>;
3244 def : Pat<(store (v8i8 VPR64:$value), GPR64xsp:$addr),
3245 (ST1_8B GPR64xsp:$addr, VPR64:$value)>;
3247 // End of vector load/store multiple N-element structure(class SIMD lselem)
3249 // The followings are post-index vector load/store multiple N-element
3250 // structure(class SIMD lselem-post)
3251 def exact1_asmoperand : AsmOperandClass {
3252 let Name = "Exact1";
3253 let PredicateMethod = "isExactImm<1>";
3254 let RenderMethod = "addImmOperands";
3256 def uimm_exact1 : Operand<i32>, ImmLeaf<i32, [{return Imm == 1;}]> {
3257 let ParserMatchClass = exact1_asmoperand;
3260 def exact2_asmoperand : AsmOperandClass {
3261 let Name = "Exact2";
3262 let PredicateMethod = "isExactImm<2>";
3263 let RenderMethod = "addImmOperands";
3265 def uimm_exact2 : Operand<i32>, ImmLeaf<i32, [{return Imm == 2;}]> {
3266 let ParserMatchClass = exact2_asmoperand;
3269 def exact3_asmoperand : AsmOperandClass {
3270 let Name = "Exact3";
3271 let PredicateMethod = "isExactImm<3>";
3272 let RenderMethod = "addImmOperands";
3274 def uimm_exact3 : Operand<i32>, ImmLeaf<i32, [{return Imm == 3;}]> {
3275 let ParserMatchClass = exact3_asmoperand;
3278 def exact4_asmoperand : AsmOperandClass {
3279 let Name = "Exact4";
3280 let PredicateMethod = "isExactImm<4>";
3281 let RenderMethod = "addImmOperands";
3283 def uimm_exact4 : Operand<i32>, ImmLeaf<i32, [{return Imm == 4;}]> {
3284 let ParserMatchClass = exact4_asmoperand;
3287 def exact6_asmoperand : AsmOperandClass {
3288 let Name = "Exact6";
3289 let PredicateMethod = "isExactImm<6>";
3290 let RenderMethod = "addImmOperands";
3292 def uimm_exact6 : Operand<i32>, ImmLeaf<i32, [{return Imm == 6;}]> {
3293 let ParserMatchClass = exact6_asmoperand;
3296 def exact8_asmoperand : AsmOperandClass {
3297 let Name = "Exact8";
3298 let PredicateMethod = "isExactImm<8>";
3299 let RenderMethod = "addImmOperands";
3301 def uimm_exact8 : Operand<i32>, ImmLeaf<i32, [{return Imm == 8;}]> {
3302 let ParserMatchClass = exact8_asmoperand;
3305 def exact12_asmoperand : AsmOperandClass {
3306 let Name = "Exact12";
3307 let PredicateMethod = "isExactImm<12>";
3308 let RenderMethod = "addImmOperands";
3310 def uimm_exact12 : Operand<i32>, ImmLeaf<i32, [{return Imm == 12;}]> {
3311 let ParserMatchClass = exact12_asmoperand;
3314 def exact16_asmoperand : AsmOperandClass {
3315 let Name = "Exact16";
3316 let PredicateMethod = "isExactImm<16>";
3317 let RenderMethod = "addImmOperands";
3319 def uimm_exact16 : Operand<i32>, ImmLeaf<i32, [{return Imm == 16;}]> {
3320 let ParserMatchClass = exact16_asmoperand;
3323 def exact24_asmoperand : AsmOperandClass {
3324 let Name = "Exact24";
3325 let PredicateMethod = "isExactImm<24>";
3326 let RenderMethod = "addImmOperands";
3328 def uimm_exact24 : Operand<i32>, ImmLeaf<i32, [{return Imm == 24;}]> {
3329 let ParserMatchClass = exact24_asmoperand;
3332 def exact32_asmoperand : AsmOperandClass {
3333 let Name = "Exact32";
3334 let PredicateMethod = "isExactImm<32>";
3335 let RenderMethod = "addImmOperands";
3337 def uimm_exact32 : Operand<i32>, ImmLeaf<i32, [{return Imm == 32;}]> {
3338 let ParserMatchClass = exact32_asmoperand;
3341 def exact48_asmoperand : AsmOperandClass {
3342 let Name = "Exact48";
3343 let PredicateMethod = "isExactImm<48>";
3344 let RenderMethod = "addImmOperands";
3346 def uimm_exact48 : Operand<i32>, ImmLeaf<i32, [{return Imm == 48;}]> {
3347 let ParserMatchClass = exact48_asmoperand;
3350 def exact64_asmoperand : AsmOperandClass {
3351 let Name = "Exact64";
3352 let PredicateMethod = "isExactImm<64>";
3353 let RenderMethod = "addImmOperands";
3355 def uimm_exact64 : Operand<i32>, ImmLeaf<i32, [{return Imm == 64;}]> {
3356 let ParserMatchClass = exact64_asmoperand;
3359 multiclass NeonI_LDWB_VList<bit q, bits<4> opcode, bits<2> size,
3360 RegisterOperand VecList, Operand ImmTy,
3362 let Constraints = "$Rn = $wb", mayLoad = 1, neverHasSideEffects = 1,
3363 DecoderMethod = "DecodeVLDSTPostInstruction" in {
3364 def _fixed : NeonI_LdStMult_Post<q, 1, opcode, size,
3365 (outs VecList:$Rt, GPR64xsp:$wb),
3366 (ins GPR64xsp:$Rn, ImmTy:$amt),
3367 asmop # "\t$Rt, [$Rn], $amt",
3373 def _register : NeonI_LdStMult_Post<q, 1, opcode, size,
3374 (outs VecList:$Rt, GPR64xsp:$wb),
3375 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3376 asmop # "\t$Rt, [$Rn], $Rm",
3382 multiclass LDWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3383 Operand ImmTy2, string asmop> {
3384 defm _8B : NeonI_LDWB_VList<0, opcode, 0b00,
3385 !cast<RegisterOperand>(List # "8B_operand"),
3388 defm _4H : NeonI_LDWB_VList<0, opcode, 0b01,
3389 !cast<RegisterOperand>(List # "4H_operand"),
3392 defm _2S : NeonI_LDWB_VList<0, opcode, 0b10,
3393 !cast<RegisterOperand>(List # "2S_operand"),
3396 defm _16B : NeonI_LDWB_VList<1, opcode, 0b00,
3397 !cast<RegisterOperand>(List # "16B_operand"),
3400 defm _8H : NeonI_LDWB_VList<1, opcode, 0b01,
3401 !cast<RegisterOperand>(List # "8H_operand"),
3404 defm _4S : NeonI_LDWB_VList<1, opcode, 0b10,
3405 !cast<RegisterOperand>(List # "4S_operand"),
3408 defm _2D : NeonI_LDWB_VList<1, opcode, 0b11,
3409 !cast<RegisterOperand>(List # "2D_operand"),
3413 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3414 defm LD1WB : LDWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "ld1">;
3415 defm LD1WB_1D : NeonI_LDWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3418 defm LD2WB : LDWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "ld2">;
3420 defm LD3WB : LDWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3423 defm LD4WB : LDWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "ld4">;
3425 // Post-index load multiple 1-element structures from N consecutive registers
3427 defm LD1x2WB : LDWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3429 defm LD1x2WB_1D : NeonI_LDWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3430 uimm_exact16, "ld1">;
3432 defm LD1x3WB : LDWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3434 defm LD1x3WB_1D : NeonI_LDWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3435 uimm_exact24, "ld1">;
3437 defm LD1x4WB : LDWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3439 defm LD1x4WB_1D : NeonI_LDWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3440 uimm_exact32, "ld1">;
3442 multiclass NeonI_STWB_VList<bit q, bits<4> opcode, bits<2> size,
3443 RegisterOperand VecList, Operand ImmTy,
3445 let Constraints = "$Rn = $wb", mayStore = 1, neverHasSideEffects = 1,
3446 DecoderMethod = "DecodeVLDSTPostInstruction" in {
3447 def _fixed : NeonI_LdStMult_Post<q, 0, opcode, size,
3448 (outs GPR64xsp:$wb),
3449 (ins GPR64xsp:$Rn, ImmTy:$amt, VecList:$Rt),
3450 asmop # "\t$Rt, [$Rn], $amt",
3456 def _register : NeonI_LdStMult_Post<q, 0, opcode, size,
3457 (outs GPR64xsp:$wb),
3458 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VecList:$Rt),
3459 asmop # "\t$Rt, [$Rn], $Rm",
3465 multiclass STWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3466 Operand ImmTy2, string asmop> {
3467 defm _8B : NeonI_STWB_VList<0, opcode, 0b00,
3468 !cast<RegisterOperand>(List # "8B_operand"), ImmTy, asmop>;
3470 defm _4H : NeonI_STWB_VList<0, opcode, 0b01,
3471 !cast<RegisterOperand>(List # "4H_operand"),
3474 defm _2S : NeonI_STWB_VList<0, opcode, 0b10,
3475 !cast<RegisterOperand>(List # "2S_operand"),
3478 defm _16B : NeonI_STWB_VList<1, opcode, 0b00,
3479 !cast<RegisterOperand>(List # "16B_operand"),
3482 defm _8H : NeonI_STWB_VList<1, opcode, 0b01,
3483 !cast<RegisterOperand>(List # "8H_operand"),
3486 defm _4S : NeonI_STWB_VList<1, opcode, 0b10,
3487 !cast<RegisterOperand>(List # "4S_operand"),
3490 defm _2D : NeonI_STWB_VList<1, opcode, 0b11,
3491 !cast<RegisterOperand>(List # "2D_operand"),
3495 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3496 defm ST1WB : STWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "st1">;
3497 defm ST1WB_1D : NeonI_STWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3500 defm ST2WB : STWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "st2">;
3502 defm ST3WB : STWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3505 defm ST4WB : STWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "st4">;
3507 // Post-index load multiple 1-element structures from N consecutive registers
3509 defm ST1x2WB : STWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3511 defm ST1x2WB_1D : NeonI_STWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3512 uimm_exact16, "st1">;
3514 defm ST1x3WB : STWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3516 defm ST1x3WB_1D : NeonI_STWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3517 uimm_exact24, "st1">;
3519 defm ST1x4WB : STWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3521 defm ST1x4WB_1D : NeonI_STWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3522 uimm_exact32, "st1">;
3524 // End of post-index vector load/store multiple N-element structure
3525 // (class SIMD lselem-post)
3527 // The followings are vector load/store single N-element structure
3528 // (class SIMD lsone).
3529 def neon_uimm0_bare : Operand<i64>,
3530 ImmLeaf<i64, [{return Imm == 0;}]> {
3531 let ParserMatchClass = neon_uimm0_asmoperand;
3532 let PrintMethod = "printUImmBareOperand";
3535 def neon_uimm1_bare : Operand<i64>,
3536 ImmLeaf<i64, [{return Imm < 2;}]> {
3537 let ParserMatchClass = neon_uimm1_asmoperand;
3538 let PrintMethod = "printUImmBareOperand";
3541 def neon_uimm2_bare : Operand<i64>,
3542 ImmLeaf<i64, [{return Imm < 4;}]> {
3543 let ParserMatchClass = neon_uimm2_asmoperand;
3544 let PrintMethod = "printUImmBareOperand";
3547 def neon_uimm3_bare : Operand<i64>,
3548 ImmLeaf<i64, [{return Imm < 8;}]> {
3549 let ParserMatchClass = uimm3_asmoperand;
3550 let PrintMethod = "printUImmBareOperand";
3553 def neon_uimm4_bare : Operand<i64>,
3554 ImmLeaf<i64, [{return Imm < 16;}]> {
3555 let ParserMatchClass = uimm4_asmoperand;
3556 let PrintMethod = "printUImmBareOperand";
3559 class NeonI_LDN_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3560 RegisterOperand VecList, string asmop>
3561 : NeonI_LdOne_Dup<q, r, opcode, size,
3562 (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3563 asmop # "\t$Rt, [$Rn]",
3567 let neverHasSideEffects = 1;
3570 multiclass LDN_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop> {
3571 def _8B : NeonI_LDN_Dup<0, r, opcode, 0b00,
3572 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3574 def _4H : NeonI_LDN_Dup<0, r, opcode, 0b01,
3575 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3577 def _2S : NeonI_LDN_Dup<0, r, opcode, 0b10,
3578 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3580 def _1D : NeonI_LDN_Dup<0, r, opcode, 0b11,
3581 !cast<RegisterOperand>(List # "1D_operand"), asmop>;
3583 def _16B : NeonI_LDN_Dup<1, r, opcode, 0b00,
3584 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3586 def _8H : NeonI_LDN_Dup<1, r, opcode, 0b01,
3587 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3589 def _4S : NeonI_LDN_Dup<1, r, opcode, 0b10,
3590 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3592 def _2D : NeonI_LDN_Dup<1, r, opcode, 0b11,
3593 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3596 // Load single 1-element structure to all lanes of 1 register
3597 defm LD1R : LDN_Dup_BHSD<0b0, 0b110, "VOne", "ld1r">;
3599 // Load single N-element structure to all lanes of N consecutive
3600 // registers (N = 2,3,4)
3601 defm LD2R : LDN_Dup_BHSD<0b1, 0b110, "VPair", "ld2r">;
3602 defm LD3R : LDN_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r">;
3603 defm LD4R : LDN_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r">;
3606 class LD1R_pattern <ValueType VTy, ValueType DTy, PatFrag LoadOp,
3608 : Pat<(VTy (Neon_vdup (DTy (LoadOp GPR64xsp:$Rn)))),
3609 (VTy (INST GPR64xsp:$Rn))>;
3611 // Match all LD1R instructions
3612 def : LD1R_pattern<v8i8, i32, extloadi8, LD1R_8B>;
3614 def : LD1R_pattern<v16i8, i32, extloadi8, LD1R_16B>;
3616 def : LD1R_pattern<v4i16, i32, extloadi16, LD1R_4H>;
3618 def : LD1R_pattern<v8i16, i32, extloadi16, LD1R_8H>;
3620 def : LD1R_pattern<v2i32, i32, load, LD1R_2S>;
3621 def : LD1R_pattern<v2f32, f32, load, LD1R_2S>;
3623 def : LD1R_pattern<v4i32, i32, load, LD1R_4S>;
3624 def : LD1R_pattern<v4f32, f32, load, LD1R_4S>;
3626 def : LD1R_pattern<v1i64, i64, load, LD1R_1D>;
3627 def : LD1R_pattern<v1f64, f64, load, LD1R_1D>;
3629 def : LD1R_pattern<v2i64, i64, load, LD1R_2D>;
3630 def : LD1R_pattern<v2f64, f64, load, LD1R_2D>;
3633 multiclass VectorList_Bare_BHSD<string PREFIX, int Count,
3634 RegisterClass RegList> {
3635 defm B : VectorList_operands<PREFIX, "B", Count, RegList>;
3636 defm H : VectorList_operands<PREFIX, "H", Count, RegList>;
3637 defm S : VectorList_operands<PREFIX, "S", Count, RegList>;
3638 defm D : VectorList_operands<PREFIX, "D", Count, RegList>;
3641 // Special vector list operand of 128-bit vectors with bare layout.
3642 // i.e. only show ".b", ".h", ".s", ".d"
3643 defm VOne : VectorList_Bare_BHSD<"VOne", 1, FPR128>;
3644 defm VPair : VectorList_Bare_BHSD<"VPair", 2, QPair>;
3645 defm VTriple : VectorList_Bare_BHSD<"VTriple", 3, QTriple>;
3646 defm VQuad : VectorList_Bare_BHSD<"VQuad", 4, QQuad>;
3648 class NeonI_LDN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3649 Operand ImmOp, string asmop>
3650 : NeonI_LdStOne_Lane<1, r, op2_1, op0,
3652 (ins GPR64xsp:$Rn, VList:$src, ImmOp:$lane),
3653 asmop # "\t$Rt[$lane], [$Rn]",
3657 let neverHasSideEffects = 1;
3658 let hasExtraDefRegAllocReq = 1;
3659 let Constraints = "$src = $Rt";
3662 multiclass LDN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3663 def _B : NeonI_LDN_Lane<r, 0b00, op0,
3664 !cast<RegisterOperand>(List # "B_operand"),
3665 neon_uimm4_bare, asmop> {
3666 let Inst{12-10} = lane{2-0};
3667 let Inst{30} = lane{3};
3670 def _H : NeonI_LDN_Lane<r, 0b01, op0,
3671 !cast<RegisterOperand>(List # "H_operand"),
3672 neon_uimm3_bare, asmop> {
3673 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3674 let Inst{30} = lane{2};
3677 def _S : NeonI_LDN_Lane<r, 0b10, op0,
3678 !cast<RegisterOperand>(List # "S_operand"),
3679 neon_uimm2_bare, asmop> {
3680 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3681 let Inst{30} = lane{1};
3684 def _D : NeonI_LDN_Lane<r, 0b10, op0,
3685 !cast<RegisterOperand>(List # "D_operand"),
3686 neon_uimm1_bare, asmop> {
3687 let Inst{12-10} = 0b001;
3688 let Inst{30} = lane{0};
3692 // Load single 1-element structure to one lane of 1 register.
3693 defm LD1LN : LDN_Lane_BHSD<0b0, 0b0, "VOne", "ld1">;
3695 // Load single N-element structure to one lane of N consecutive registers
3697 defm LD2LN : LDN_Lane_BHSD<0b1, 0b0, "VPair", "ld2">;
3698 defm LD3LN : LDN_Lane_BHSD<0b0, 0b1, "VTriple", "ld3">;
3699 defm LD4LN : LDN_Lane_BHSD<0b1, 0b1, "VQuad", "ld4">;
3701 multiclass LD1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3702 Operand ImmOp, Operand ImmOp2, PatFrag LoadOp,
3704 def : Pat<(VTy (vector_insert (VTy VPR64:$src),
3705 (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp:$lane))),
3706 (VTy (EXTRACT_SUBREG
3708 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
3712 def : Pat<(VTy2 (vector_insert (VTy2 VPR128:$src),
3713 (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp2:$lane))),
3714 (VTy2 (INST GPR64xsp:$Rn, VPR128:$src, ImmOp2:$lane))>;
3717 // Match all LD1LN instructions
3718 defm : LD1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3719 extloadi8, LD1LN_B>;
3721 defm : LD1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3722 extloadi16, LD1LN_H>;
3724 defm : LD1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3726 defm : LD1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3729 defm : LD1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3731 defm : LD1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3734 class NeonI_STN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3735 Operand ImmOp, string asmop>
3736 : NeonI_LdStOne_Lane<0, r, op2_1, op0,
3737 (outs), (ins GPR64xsp:$Rn, VList:$Rt, ImmOp:$lane),
3738 asmop # "\t$Rt[$lane], [$Rn]",
3742 let neverHasSideEffects = 1;
3743 let hasExtraDefRegAllocReq = 1;
3746 multiclass STN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3747 def _B : NeonI_STN_Lane<r, 0b00, op0,
3748 !cast<RegisterOperand>(List # "B_operand"),
3749 neon_uimm4_bare, asmop> {
3750 let Inst{12-10} = lane{2-0};
3751 let Inst{30} = lane{3};
3754 def _H : NeonI_STN_Lane<r, 0b01, op0,
3755 !cast<RegisterOperand>(List # "H_operand"),
3756 neon_uimm3_bare, asmop> {
3757 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3758 let Inst{30} = lane{2};
3761 def _S : NeonI_STN_Lane<r, 0b10, op0,
3762 !cast<RegisterOperand>(List # "S_operand"),
3763 neon_uimm2_bare, asmop> {
3764 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3765 let Inst{30} = lane{1};
3768 def _D : NeonI_STN_Lane<r, 0b10, op0,
3769 !cast<RegisterOperand>(List # "D_operand"),
3770 neon_uimm1_bare, asmop>{
3771 let Inst{12-10} = 0b001;
3772 let Inst{30} = lane{0};
3776 // Store single 1-element structure from one lane of 1 register.
3777 defm ST1LN : STN_Lane_BHSD<0b0, 0b0, "VOne", "st1">;
3779 // Store single N-element structure from one lane of N consecutive registers
3781 defm ST2LN : STN_Lane_BHSD<0b1, 0b0, "VPair", "st2">;
3782 defm ST3LN : STN_Lane_BHSD<0b0, 0b1, "VTriple", "st3">;
3783 defm ST4LN : STN_Lane_BHSD<0b1, 0b1, "VQuad", "st4">;
3785 multiclass ST1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3786 Operand ImmOp, Operand ImmOp2, PatFrag StoreOp,
3788 def : Pat<(StoreOp (DTy (vector_extract (VTy VPR64:$Rt), ImmOp:$lane)),
3791 (SUBREG_TO_REG (i64 0), VPR64:$Rt, sub_64),
3794 def : Pat<(StoreOp (DTy (vector_extract (VTy2 VPR128:$Rt), ImmOp2:$lane)),
3796 (INST GPR64xsp:$Rn, VPR128:$Rt, ImmOp2:$lane)>;
3799 // Match all ST1LN instructions
3800 defm : ST1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3801 truncstorei8, ST1LN_B>;
3803 defm : ST1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3804 truncstorei16, ST1LN_H>;
3806 defm : ST1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3808 defm : ST1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3811 defm : ST1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3813 defm : ST1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3816 // End of vector load/store single N-element structure (class SIMD lsone).
3819 // The following are post-index load/store single N-element instructions
3820 // (class SIMD lsone-post)
3822 multiclass NeonI_LDN_WB_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3823 RegisterOperand VecList, Operand ImmTy,
3825 let mayLoad = 1, neverHasSideEffects = 1, Constraints = "$wb = $Rn",
3826 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
3827 def _fixed : NeonI_LdOne_Dup_Post<q, r, opcode, size,
3828 (outs VecList:$Rt, GPR64xsp:$wb),
3829 (ins GPR64xsp:$Rn, ImmTy:$amt),
3830 asmop # "\t$Rt, [$Rn], $amt",
3836 def _register : NeonI_LdOne_Dup_Post<q, r, opcode, size,
3837 (outs VecList:$Rt, GPR64xsp:$wb),
3838 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3839 asmop # "\t$Rt, [$Rn], $Rm",
3845 multiclass LDWB_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop,
3846 Operand uimm_b, Operand uimm_h,
3847 Operand uimm_s, Operand uimm_d> {
3848 defm _8B : NeonI_LDN_WB_Dup<0, r, opcode, 0b00,
3849 !cast<RegisterOperand>(List # "8B_operand"),
3852 defm _4H : NeonI_LDN_WB_Dup<0, r, opcode, 0b01,
3853 !cast<RegisterOperand>(List # "4H_operand"),
3856 defm _2S : NeonI_LDN_WB_Dup<0, r, opcode, 0b10,
3857 !cast<RegisterOperand>(List # "2S_operand"),
3860 defm _1D : NeonI_LDN_WB_Dup<0, r, opcode, 0b11,
3861 !cast<RegisterOperand>(List # "1D_operand"),
3864 defm _16B : NeonI_LDN_WB_Dup<1, r, opcode, 0b00,
3865 !cast<RegisterOperand>(List # "16B_operand"),
3868 defm _8H : NeonI_LDN_WB_Dup<1, r, opcode, 0b01,
3869 !cast<RegisterOperand>(List # "8H_operand"),
3872 defm _4S : NeonI_LDN_WB_Dup<1, r, opcode, 0b10,
3873 !cast<RegisterOperand>(List # "4S_operand"),
3876 defm _2D : NeonI_LDN_WB_Dup<1, r, opcode, 0b11,
3877 !cast<RegisterOperand>(List # "2D_operand"),
3881 // Post-index load single 1-element structure to all lanes of 1 register
3882 defm LD1R_WB : LDWB_Dup_BHSD<0b0, 0b110, "VOne", "ld1r", uimm_exact1,
3883 uimm_exact2, uimm_exact4, uimm_exact8>;
3885 // Post-index load single N-element structure to all lanes of N consecutive
3886 // registers (N = 2,3,4)
3887 defm LD2R_WB : LDWB_Dup_BHSD<0b1, 0b110, "VPair", "ld2r", uimm_exact2,
3888 uimm_exact4, uimm_exact8, uimm_exact16>;
3889 defm LD3R_WB : LDWB_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r", uimm_exact3,
3890 uimm_exact6, uimm_exact12, uimm_exact24>;
3891 defm LD4R_WB : LDWB_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r", uimm_exact4,
3892 uimm_exact8, uimm_exact16, uimm_exact32>;
3894 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
3895 Constraints = "$Rn = $wb, $Rt = $src",
3896 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
3897 class LDN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3898 Operand ImmTy, Operand ImmOp, string asmop>
3899 : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
3900 (outs VList:$Rt, GPR64xsp:$wb),
3901 (ins GPR64xsp:$Rn, ImmTy:$amt,
3902 VList:$src, ImmOp:$lane),
3903 asmop # "\t$Rt[$lane], [$Rn], $amt",
3909 class LDN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3910 Operand ImmTy, Operand ImmOp, string asmop>
3911 : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
3912 (outs VList:$Rt, GPR64xsp:$wb),
3913 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm,
3914 VList:$src, ImmOp:$lane),
3915 asmop # "\t$Rt[$lane], [$Rn], $Rm",
3920 multiclass LD_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
3921 Operand uimm_b, Operand uimm_h,
3922 Operand uimm_s, Operand uimm_d> {
3923 def _B_fixed : LDN_WBFx_Lane<r, 0b00, op0,
3924 !cast<RegisterOperand>(List # "B_operand"),
3925 uimm_b, neon_uimm4_bare, asmop> {
3926 let Inst{12-10} = lane{2-0};
3927 let Inst{30} = lane{3};
3930 def _B_register : LDN_WBReg_Lane<r, 0b00, op0,
3931 !cast<RegisterOperand>(List # "B_operand"),
3932 uimm_b, neon_uimm4_bare, asmop> {
3933 let Inst{12-10} = lane{2-0};
3934 let Inst{30} = lane{3};
3937 def _H_fixed : LDN_WBFx_Lane<r, 0b01, op0,
3938 !cast<RegisterOperand>(List # "H_operand"),
3939 uimm_h, neon_uimm3_bare, asmop> {
3940 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3941 let Inst{30} = lane{2};
3944 def _H_register : LDN_WBReg_Lane<r, 0b01, op0,
3945 !cast<RegisterOperand>(List # "H_operand"),
3946 uimm_h, neon_uimm3_bare, asmop> {
3947 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3948 let Inst{30} = lane{2};
3951 def _S_fixed : LDN_WBFx_Lane<r, 0b10, op0,
3952 !cast<RegisterOperand>(List # "S_operand"),
3953 uimm_s, neon_uimm2_bare, asmop> {
3954 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3955 let Inst{30} = lane{1};
3958 def _S_register : LDN_WBReg_Lane<r, 0b10, op0,
3959 !cast<RegisterOperand>(List # "S_operand"),
3960 uimm_s, neon_uimm2_bare, asmop> {
3961 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3962 let Inst{30} = lane{1};
3965 def _D_fixed : LDN_WBFx_Lane<r, 0b10, op0,
3966 !cast<RegisterOperand>(List # "D_operand"),
3967 uimm_d, neon_uimm1_bare, asmop> {
3968 let Inst{12-10} = 0b001;
3969 let Inst{30} = lane{0};
3972 def _D_register : LDN_WBReg_Lane<r, 0b10, op0,
3973 !cast<RegisterOperand>(List # "D_operand"),
3974 uimm_d, neon_uimm1_bare, asmop> {
3975 let Inst{12-10} = 0b001;
3976 let Inst{30} = lane{0};
3980 // Post-index load single 1-element structure to one lane of 1 register.
3981 defm LD1LN_WB : LD_Lane_WB_BHSD<0b0, 0b0, "VOne", "ld1", uimm_exact1,
3982 uimm_exact2, uimm_exact4, uimm_exact8>;
3984 // Post-index load single N-element structure to one lane of N consecutive
3987 defm LD2LN_WB : LD_Lane_WB_BHSD<0b1, 0b0, "VPair", "ld2", uimm_exact2,
3988 uimm_exact4, uimm_exact8, uimm_exact16>;
3989 defm LD3LN_WB : LD_Lane_WB_BHSD<0b0, 0b1, "VTriple", "ld3", uimm_exact3,
3990 uimm_exact6, uimm_exact12, uimm_exact24>;
3991 defm LD4LN_WB : LD_Lane_WB_BHSD<0b1, 0b1, "VQuad", "ld4", uimm_exact4,
3992 uimm_exact8, uimm_exact16, uimm_exact32>;
3994 let mayStore = 1, neverHasSideEffects = 1,
3995 hasExtraDefRegAllocReq = 1, Constraints = "$Rn = $wb",
3996 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
3997 class STN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3998 Operand ImmTy, Operand ImmOp, string asmop>
3999 : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4000 (outs GPR64xsp:$wb),
4001 (ins GPR64xsp:$Rn, ImmTy:$amt,
4002 VList:$Rt, ImmOp:$lane),
4003 asmop # "\t$Rt[$lane], [$Rn], $amt",
4009 class STN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4010 Operand ImmTy, Operand ImmOp, string asmop>
4011 : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4012 (outs GPR64xsp:$wb),
4013 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VList:$Rt,
4015 asmop # "\t$Rt[$lane], [$Rn], $Rm",
4020 multiclass ST_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4021 Operand uimm_b, Operand uimm_h,
4022 Operand uimm_s, Operand uimm_d> {
4023 def _B_fixed : STN_WBFx_Lane<r, 0b00, op0,
4024 !cast<RegisterOperand>(List # "B_operand"),
4025 uimm_b, neon_uimm4_bare, asmop> {
4026 let Inst{12-10} = lane{2-0};
4027 let Inst{30} = lane{3};
4030 def _B_register : STN_WBReg_Lane<r, 0b00, op0,
4031 !cast<RegisterOperand>(List # "B_operand"),
4032 uimm_b, neon_uimm4_bare, asmop> {
4033 let Inst{12-10} = lane{2-0};
4034 let Inst{30} = lane{3};
4037 def _H_fixed : STN_WBFx_Lane<r, 0b01, op0,
4038 !cast<RegisterOperand>(List # "H_operand"),
4039 uimm_h, neon_uimm3_bare, asmop> {
4040 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4041 let Inst{30} = lane{2};
4044 def _H_register : STN_WBReg_Lane<r, 0b01, op0,
4045 !cast<RegisterOperand>(List # "H_operand"),
4046 uimm_h, neon_uimm3_bare, asmop> {
4047 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4048 let Inst{30} = lane{2};
4051 def _S_fixed : STN_WBFx_Lane<r, 0b10, op0,
4052 !cast<RegisterOperand>(List # "S_operand"),
4053 uimm_s, neon_uimm2_bare, asmop> {
4054 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4055 let Inst{30} = lane{1};
4058 def _S_register : STN_WBReg_Lane<r, 0b10, op0,
4059 !cast<RegisterOperand>(List # "S_operand"),
4060 uimm_s, neon_uimm2_bare, asmop> {
4061 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4062 let Inst{30} = lane{1};
4065 def _D_fixed : STN_WBFx_Lane<r, 0b10, op0,
4066 !cast<RegisterOperand>(List # "D_operand"),
4067 uimm_d, neon_uimm1_bare, asmop> {
4068 let Inst{12-10} = 0b001;
4069 let Inst{30} = lane{0};
4072 def _D_register : STN_WBReg_Lane<r, 0b10, op0,
4073 !cast<RegisterOperand>(List # "D_operand"),
4074 uimm_d, neon_uimm1_bare, asmop> {
4075 let Inst{12-10} = 0b001;
4076 let Inst{30} = lane{0};
4080 // Post-index store single 1-element structure from one lane of 1 register.
4081 defm ST1LN_WB : ST_Lane_WB_BHSD<0b0, 0b0, "VOne", "st1", uimm_exact1,
4082 uimm_exact2, uimm_exact4, uimm_exact8>;
4084 // Post-index store single N-element structure from one lane of N consecutive
4085 // registers (N = 2,3,4)
4086 defm ST2LN_WB : ST_Lane_WB_BHSD<0b1, 0b0, "VPair", "st2", uimm_exact2,
4087 uimm_exact4, uimm_exact8, uimm_exact16>;
4088 defm ST3LN_WB : ST_Lane_WB_BHSD<0b0, 0b1, "VTriple", "st3", uimm_exact3,
4089 uimm_exact6, uimm_exact12, uimm_exact24>;
4090 defm ST4LN_WB : ST_Lane_WB_BHSD<0b1, 0b1, "VQuad", "st4", uimm_exact4,
4091 uimm_exact8, uimm_exact16, uimm_exact32>;
4093 // End of post-index load/store single N-element instructions
4094 // (class SIMD lsone-post)
4096 // Neon Scalar instructions implementation
4097 // Scalar Three Same
4099 class NeonI_Scalar3Same_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4101 : NeonI_Scalar3Same<u, size, opcode,
4102 (outs FPRC:$Rd), (ins FPRC:$Rn, FPRC:$Rm),
4103 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4107 class NeonI_Scalar3Same_D_size<bit u, bits<5> opcode, string asmop>
4108 : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4110 multiclass NeonI_Scalar3Same_HS_sizes<bit u, bits<5> opcode, string asmop,
4111 bit Commutable = 0> {
4112 let isCommutable = Commutable in {
4113 def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4114 def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4118 multiclass NeonI_Scalar3Same_SD_sizes<bit u, bit size_high, bits<5> opcode,
4119 string asmop, bit Commutable = 0> {
4120 let isCommutable = Commutable in {
4121 def sss : NeonI_Scalar3Same_size<u, {size_high, 0b0}, opcode, asmop, FPR32>;
4122 def ddd : NeonI_Scalar3Same_size<u, {size_high, 0b1}, opcode, asmop, FPR64>;
4126 multiclass NeonI_Scalar3Same_BHSD_sizes<bit u, bits<5> opcode,
4127 string asmop, bit Commutable = 0> {
4128 let isCommutable = Commutable in {
4129 def bbb : NeonI_Scalar3Same_size<u, 0b00, opcode, asmop, FPR8>;
4130 def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4131 def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4132 def ddd : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4136 multiclass Neon_Scalar3Same_D_size_patterns<SDPatternOperator opnode,
4137 Instruction INSTD> {
4138 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4139 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4142 multiclass Neon_Scalar3Same_BHSD_size_patterns<SDPatternOperator opnode,
4147 : Neon_Scalar3Same_D_size_patterns<opnode, INSTD> {
4148 def: Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (v1i8 FPR8:$Rm))),
4149 (INSTB FPR8:$Rn, FPR8:$Rm)>;
4151 def: Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4152 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4154 def: Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4155 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4158 class Neon_Scalar3Same_cmp_D_size_patterns<SDPatternOperator opnode,
4160 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4161 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4163 multiclass Neon_Scalar3Same_HS_size_patterns<SDPatternOperator opnode,
4165 Instruction INSTS> {
4166 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4167 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4168 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4169 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4172 multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
4174 Instruction INSTD> {
4175 def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
4176 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4177 def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
4178 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4181 multiclass Neon_Scalar3Same_cmp_SD_size_patterns<SDPatternOperator opnode,
4183 Instruction INSTD> {
4184 def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
4185 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4186 def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
4187 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4190 class Neon_Scalar3Same_cmp_V1_D_size_patterns<CondCode CC,
4192 : Pat<(v1i64 (Neon_cmp (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm), CC)),
4193 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4195 // Scalar Three Different
4197 class NeonI_Scalar3Diff_size<bit u, bits<2> size, bits<4> opcode, string asmop,
4198 RegisterClass FPRCD, RegisterClass FPRCS>
4199 : NeonI_Scalar3Diff<u, size, opcode,
4200 (outs FPRCD:$Rd), (ins FPRCS:$Rn, FPRCS:$Rm),
4201 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4205 multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> {
4206 def shh : NeonI_Scalar3Diff_size<u, 0b01, opcode, asmop, FPR32, FPR16>;
4207 def dss : NeonI_Scalar3Diff_size<u, 0b10, opcode, asmop, FPR64, FPR32>;
4210 multiclass NeonI_Scalar3Diff_ml_HS_size<bit u, bits<4> opcode, string asmop> {
4211 let Constraints = "$Src = $Rd" in {
4212 def shh : NeonI_Scalar3Diff<u, 0b01, opcode,
4213 (outs FPR32:$Rd), (ins FPR32:$Src, FPR16:$Rn, FPR16:$Rm),
4214 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4217 def dss : NeonI_Scalar3Diff<u, 0b10, opcode,
4218 (outs FPR64:$Rd), (ins FPR64:$Src, FPR32:$Rn, FPR32:$Rm),
4219 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4225 multiclass Neon_Scalar3Diff_HS_size_patterns<SDPatternOperator opnode,
4227 Instruction INSTS> {
4228 def : Pat<(v1i32 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4229 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4230 def : Pat<(v1i64 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4231 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4234 multiclass Neon_Scalar3Diff_ml_HS_size_patterns<SDPatternOperator opnode,
4236 Instruction INSTS> {
4237 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4238 (INSTH FPR32:$Src, FPR16:$Rn, FPR16:$Rm)>;
4239 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4240 (INSTS FPR64:$Src, FPR32:$Rn, FPR32:$Rm)>;
4243 // Scalar Two Registers Miscellaneous
4245 class NeonI_Scalar2SameMisc_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4246 RegisterClass FPRCD, RegisterClass FPRCS>
4247 : NeonI_Scalar2SameMisc<u, size, opcode,
4248 (outs FPRCD:$Rd), (ins FPRCS:$Rn),
4249 !strconcat(asmop, "\t$Rd, $Rn"),
4253 multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
4255 def ss : NeonI_Scalar2SameMisc_size<u, {size_high, 0b0}, opcode, asmop, FPR32,
4257 def dd : NeonI_Scalar2SameMisc_size<u, {size_high, 0b1}, opcode, asmop, FPR64,
4261 multiclass NeonI_Scalar2SameMisc_D_size<bit u, bits<5> opcode, string asmop> {
4262 def dd : NeonI_Scalar2SameMisc_size<u, 0b11, opcode, asmop, FPR64, FPR64>;
4265 multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>
4266 : NeonI_Scalar2SameMisc_D_size<u, opcode, asmop> {
4267 def bb : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR8>;
4268 def hh : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR16>;
4269 def ss : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR32>;
4272 class NeonI_Scalar2SameMisc_fcvtxn_D_size<bit u, bits<5> opcode, string asmop>
4273 : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR32, FPR64>;
4275 multiclass NeonI_Scalar2SameMisc_narrow_HSD_size<bit u, bits<5> opcode,
4277 def bh : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR16>;
4278 def hs : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR32>;
4279 def sd : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR64>;
4282 class NeonI_Scalar2SameMisc_accum_size<bit u, bits<2> size, bits<5> opcode,
4283 string asmop, RegisterClass FPRC>
4284 : NeonI_Scalar2SameMisc<u, size, opcode,
4285 (outs FPRC:$Rd), (ins FPRC:$Src, FPRC:$Rn),
4286 !strconcat(asmop, "\t$Rd, $Rn"),
4290 multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
4293 let Constraints = "$Src = $Rd" in {
4294 def bb : NeonI_Scalar2SameMisc_accum_size<u, 0b00, opcode, asmop, FPR8>;
4295 def hh : NeonI_Scalar2SameMisc_accum_size<u, 0b01, opcode, asmop, FPR16>;
4296 def ss : NeonI_Scalar2SameMisc_accum_size<u, 0b10, opcode, asmop, FPR32>;
4297 def dd : NeonI_Scalar2SameMisc_accum_size<u, 0b11, opcode, asmop, FPR64>;
4301 class Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<SDPatternOperator opnode,
4303 : Pat<(v1f32 (opnode (v1f64 FPR64:$Rn))),
4306 multiclass Neon_Scalar2SameMisc_fcvt_SD_size_patterns<SDPatternOperator opnode,
4308 Instruction INSTD> {
4309 def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn))),
4311 def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))),
4315 multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator Sopnode,
4316 SDPatternOperator Dopnode,
4318 Instruction INSTD> {
4319 def : Pat<(f32 (Sopnode (v1i32 FPR32:$Rn))),
4321 def : Pat<(f64 (Dopnode (v1i64 FPR64:$Rn))),
4325 multiclass Neon_Scalar2SameMisc_SD_size_patterns<SDPatternOperator opnode,
4327 Instruction INSTD> {
4328 def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn))),
4330 def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))),
4334 class NeonI_Scalar2SameMisc_cmpz_D_size<bit u, bits<5> opcode, string asmop>
4335 : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4336 (outs FPR64:$Rd), (ins FPR64:$Rn, neon_uimm0:$Imm),
4337 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4341 multiclass NeonI_Scalar2SameMisc_cmpz_SD_size<bit u, bits<5> opcode,
4343 def ssi : NeonI_Scalar2SameMisc<u, 0b10, opcode,
4344 (outs FPR32:$Rd), (ins FPR32:$Rn, fpz32:$FPImm),
4345 !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4348 def ddi : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4349 (outs FPR64:$Rd), (ins FPR64:$Rn, fpz32:$FPImm),
4350 !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4355 class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode,
4357 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4358 (v1i64 (bitconvert (v8i8 Neon_AllZero))))),
4359 (INSTD FPR64:$Rn, 0)>;
4361 class Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<CondCode CC,
4363 : Pat<(v1i64 (Neon_cmpz (v1i64 FPR64:$Rn),
4364 (i32 neon_uimm0:$Imm), CC)),
4365 (INSTD FPR64:$Rn, neon_uimm0:$Imm)>;
4367 multiclass Neon_Scalar2SameMisc_cmpz_SD_size_patterns<SDPatternOperator opnode,
4369 Instruction INSTD> {
4370 def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn),
4371 (v1f32 (scalar_to_vector (f32 fpz32:$FPImm))))),
4372 (INSTS FPR32:$Rn, fpz32:$FPImm)>;
4373 def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn),
4374 (v1f32 (scalar_to_vector (f32 fpz32:$FPImm))))),
4375 (INSTD FPR64:$Rn, fpz32:$FPImm)>;
4378 multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode,
4379 Instruction INSTD> {
4380 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))),
4384 multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
4389 : Neon_Scalar2SameMisc_D_size_patterns<opnode, INSTD> {
4390 def : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn))),
4392 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn))),
4394 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn))),
4398 multiclass Neon_Scalar2SameMisc_narrow_HSD_size_patterns<
4399 SDPatternOperator opnode,
4402 Instruction INSTD> {
4403 def : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn))),
4405 def : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn))),
4407 def : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn))),
4412 multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns<
4413 SDPatternOperator opnode,
4417 Instruction INSTD> {
4418 def : Pat<(v1i8 (opnode (v1i8 FPR8:$Src), (v1i8 FPR8:$Rn))),
4419 (INSTB FPR8:$Src, FPR8:$Rn)>;
4420 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Src), (v1i16 FPR16:$Rn))),
4421 (INSTH FPR16:$Src, FPR16:$Rn)>;
4422 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i32 FPR32:$Rn))),
4423 (INSTS FPR32:$Src, FPR32:$Rn)>;
4424 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn))),
4425 (INSTD FPR64:$Src, FPR64:$Rn)>;
4428 // Scalar Shift By Immediate
4430 class NeonI_ScalarShiftImm_size<bit u, bits<5> opcode, string asmop,
4431 RegisterClass FPRC, Operand ImmTy>
4432 : NeonI_ScalarShiftImm<u, opcode,
4433 (outs FPRC:$Rd), (ins FPRC:$Rn, ImmTy:$Imm),
4434 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4437 multiclass NeonI_ScalarShiftRightImm_D_size<bit u, bits<5> opcode,
4439 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4441 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4442 let Inst{21-16} = Imm;
4446 multiclass NeonI_ScalarShiftRightImm_BHSD_size<bit u, bits<5> opcode,
4448 : NeonI_ScalarShiftRightImm_D_size<u, opcode, asmop> {
4449 def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shr_imm8> {
4451 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4452 let Inst{18-16} = Imm;
4454 def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shr_imm16> {
4456 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4457 let Inst{19-16} = Imm;
4459 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4461 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4462 let Inst{20-16} = Imm;
4466 multiclass NeonI_ScalarShiftLeftImm_D_size<bit u, bits<5> opcode,
4468 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shl_imm64> {
4470 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4471 let Inst{21-16} = Imm;
4475 multiclass NeonI_ScalarShiftLeftImm_BHSD_size<bit u, bits<5> opcode,
4477 : NeonI_ScalarShiftLeftImm_D_size<u, opcode, asmop> {
4478 def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shl_imm8> {
4480 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4481 let Inst{18-16} = Imm;
4483 def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shl_imm16> {
4485 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4486 let Inst{19-16} = Imm;
4488 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shl_imm32> {
4490 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4491 let Inst{20-16} = Imm;
4495 class NeonI_ScalarShiftRightImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4496 : NeonI_ScalarShiftImm<u, opcode,
4498 (ins FPR64:$Src, FPR64:$Rn, shr_imm64:$Imm),
4499 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4502 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4503 let Inst{21-16} = Imm;
4504 let Constraints = "$Src = $Rd";
4507 class NeonI_ScalarShiftLeftImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4508 : NeonI_ScalarShiftImm<u, opcode,
4510 (ins FPR64:$Src, FPR64:$Rn, shl_imm64:$Imm),
4511 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4514 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4515 let Inst{21-16} = Imm;
4516 let Constraints = "$Src = $Rd";
4519 class NeonI_ScalarShiftImm_narrow_size<bit u, bits<5> opcode, string asmop,
4520 RegisterClass FPRCD, RegisterClass FPRCS,
4522 : NeonI_ScalarShiftImm<u, opcode,
4523 (outs FPRCD:$Rd), (ins FPRCS:$Rn, ImmTy:$Imm),
4524 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4527 multiclass NeonI_ScalarShiftImm_narrow_HSD_size<bit u, bits<5> opcode,
4529 def bhi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR8, FPR16,
4532 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4533 let Inst{18-16} = Imm;
4535 def hsi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR16, FPR32,
4538 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4539 let Inst{19-16} = Imm;
4541 def sdi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR32, FPR64,
4544 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4545 let Inst{20-16} = Imm;
4549 multiclass NeonI_ScalarShiftImm_cvt_SD_size<bit u, bits<5> opcode, string asmop> {
4550 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4552 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4553 let Inst{20-16} = Imm;
4555 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4557 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4558 let Inst{21-16} = Imm;
4562 multiclass Neon_ScalarShiftRImm_D_size_patterns<SDPatternOperator opnode,
4563 Instruction INSTD> {
4564 def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4565 (INSTD FPR64:$Rn, imm:$Imm)>;
4568 multiclass Neon_ScalarShiftLImm_D_size_patterns<SDPatternOperator opnode,
4569 Instruction INSTD> {
4570 def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shl_imm64:$Imm))),
4571 (INSTD FPR64:$Rn, imm:$Imm)>;
4574 class Neon_ScalarShiftImm_arm_D_size_patterns<SDPatternOperator opnode,
4576 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4577 (v1i64 (Neon_vdup (i32 shr_imm64:$Imm))))),
4578 (INSTD FPR64:$Rn, imm:$Imm)>;
4580 multiclass Neon_ScalarShiftLImm_BHSD_size_patterns<SDPatternOperator opnode,
4585 : Neon_ScalarShiftLImm_D_size_patterns<opnode, INSTD> {
4586 def bbi : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (i32 shl_imm8:$Imm))),
4587 (INSTB FPR8:$Rn, imm:$Imm)>;
4588 def hhi : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (i32 shl_imm16:$Imm))),
4589 (INSTH FPR16:$Rn, imm:$Imm)>;
4590 def ssi : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (i32 shl_imm32:$Imm))),
4591 (INSTS FPR32:$Rn, imm:$Imm)>;
4594 class Neon_ScalarShiftLImm_accum_D_size_patterns<SDPatternOperator opnode,
4596 : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4597 (i32 shl_imm64:$Imm))),
4598 (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4600 class Neon_ScalarShiftRImm_accum_D_size_patterns<SDPatternOperator opnode,
4602 : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4603 (i32 shr_imm64:$Imm))),
4604 (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4606 multiclass Neon_ScalarShiftImm_narrow_HSD_size_patterns<
4607 SDPatternOperator opnode,
4610 Instruction INSTD> {
4611 def bhi : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn), (i32 shr_imm16:$Imm))),
4612 (INSTH FPR16:$Rn, imm:$Imm)>;
4613 def hsi : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4614 (INSTS FPR32:$Rn, imm:$Imm)>;
4615 def sdi : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4616 (INSTD FPR64:$Rn, imm:$Imm)>;
4619 multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns<SDPatternOperator Sopnode,
4620 SDPatternOperator Dopnode,
4622 Instruction INSTD> {
4623 def ssi : Pat<(f32 (Sopnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4624 (INSTS FPR32:$Rn, imm:$Imm)>;
4625 def ddi : Pat<(f64 (Dopnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4626 (INSTD FPR64:$Rn, imm:$Imm)>;
4629 multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns<SDPatternOperator Sopnode,
4630 SDPatternOperator Dopnode,
4632 Instruction INSTD> {
4633 def ssi : Pat<(v1i32 (Sopnode (v1f32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4634 (INSTS FPR32:$Rn, imm:$Imm)>;
4635 def ddi : Pat<(v1i64 (Dopnode (v1f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4636 (INSTD FPR64:$Rn, imm:$Imm)>;
4639 // Scalar Signed Shift Right (Immediate)
4640 defm SSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00000, "sshr">;
4641 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrds_n, SSHRddi>;
4642 // Pattern to match llvm.arm.* intrinsic.
4643 def : Neon_ScalarShiftImm_arm_D_size_patterns<sra, SSHRddi>;
4645 // Scalar Unsigned Shift Right (Immediate)
4646 defm USHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00000, "ushr">;
4647 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrdu_n, USHRddi>;
4648 // Pattern to match llvm.arm.* intrinsic.
4649 def : Neon_ScalarShiftImm_arm_D_size_patterns<srl, USHRddi>;
4651 // Scalar Signed Rounding Shift Right (Immediate)
4652 defm SRSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00100, "srshr">;
4653 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vsrshr, SRSHRddi>;
4655 // Scalar Unigned Rounding Shift Right (Immediate)
4656 defm URSHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00100, "urshr">;
4657 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vurshr, URSHRddi>;
4659 // Scalar Signed Shift Right and Accumulate (Immediate)
4660 def SSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00010, "ssra">;
4661 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4662 <int_aarch64_neon_vsrads_n, SSRA>;
4664 // Scalar Unsigned Shift Right and Accumulate (Immediate)
4665 def USRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00010, "usra">;
4666 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4667 <int_aarch64_neon_vsradu_n, USRA>;
4669 // Scalar Signed Rounding Shift Right and Accumulate (Immediate)
4670 def SRSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00110, "srsra">;
4671 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4672 <int_aarch64_neon_vrsrads_n, SRSRA>;
4674 // Scalar Unsigned Rounding Shift Right and Accumulate (Immediate)
4675 def URSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00110, "ursra">;
4676 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4677 <int_aarch64_neon_vrsradu_n, URSRA>;
4679 // Scalar Shift Left (Immediate)
4680 defm SHL : NeonI_ScalarShiftLeftImm_D_size<0b0, 0b01010, "shl">;
4681 defm : Neon_ScalarShiftLImm_D_size_patterns<int_aarch64_neon_vshld_n, SHLddi>;
4682 // Pattern to match llvm.arm.* intrinsic.
4683 def : Neon_ScalarShiftImm_arm_D_size_patterns<shl, SHLddi>;
4685 // Signed Saturating Shift Left (Immediate)
4686 defm SQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b0, 0b01110, "sqshl">;
4687 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshls_n,
4689 SQSHLssi, SQSHLddi>;
4690 // Pattern to match llvm.arm.* intrinsic.
4691 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_sqrshlImm, SQSHLddi>;
4693 // Unsigned Saturating Shift Left (Immediate)
4694 defm UQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01110, "uqshl">;
4695 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshlu_n,
4697 UQSHLssi, UQSHLddi>;
4698 // Pattern to match llvm.arm.* intrinsic.
4699 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_uqrshlImm, UQSHLddi>;
4701 // Signed Saturating Shift Left Unsigned (Immediate)
4702 defm SQSHLU : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01100, "sqshlu">;
4703 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vsqshlu,
4704 SQSHLUbbi, SQSHLUhhi,
4705 SQSHLUssi, SQSHLUddi>;
4707 // Shift Right And Insert (Immediate)
4708 def SRI : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b01000, "sri">;
4709 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4710 <int_aarch64_neon_vsri, SRI>;
4712 // Shift Left And Insert (Immediate)
4713 def SLI : NeonI_ScalarShiftLeftImm_accum_D_size<0b1, 0b01010, "sli">;
4714 def : Neon_ScalarShiftLImm_accum_D_size_patterns
4715 <int_aarch64_neon_vsli, SLI>;
4717 // Signed Saturating Shift Right Narrow (Immediate)
4718 defm SQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10010, "sqshrn">;
4719 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrn,
4720 SQSHRNbhi, SQSHRNhsi,
4723 // Unsigned Saturating Shift Right Narrow (Immediate)
4724 defm UQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10010, "uqshrn">;
4725 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqshrn,
4726 UQSHRNbhi, UQSHRNhsi,
4729 // Signed Saturating Rounded Shift Right Narrow (Immediate)
4730 defm SQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10011, "sqrshrn">;
4731 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrn,
4732 SQRSHRNbhi, SQRSHRNhsi,
4735 // Unsigned Saturating Rounded Shift Right Narrow (Immediate)
4736 defm UQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10011, "uqrshrn">;
4737 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqrshrn,
4738 UQRSHRNbhi, UQRSHRNhsi,
4741 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
4742 defm SQSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10000, "sqshrun">;
4743 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrun,
4744 SQSHRUNbhi, SQSHRUNhsi,
4747 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
4748 defm SQRSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10001, "sqrshrun">;
4749 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrun,
4750 SQRSHRUNbhi, SQRSHRUNhsi,
4753 // Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
4754 defm SCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11100, "scvtf">;
4755 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtf32_n_s32,
4756 int_aarch64_neon_vcvtf64_n_s64,
4757 SCVTF_Nssi, SCVTF_Nddi>;
4759 // Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
4760 defm UCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11100, "ucvtf">;
4761 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtf32_n_u32,
4762 int_aarch64_neon_vcvtf64_n_u64,
4763 UCVTF_Nssi, UCVTF_Nddi>;
4765 // Scalar Floating-point Convert To Signed Fixed-point (Immediate)
4766 defm FCVTZS_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11111, "fcvtzs">;
4767 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvts_n_s32_f32,
4768 int_aarch64_neon_vcvtd_n_s64_f64,
4769 FCVTZS_Nssi, FCVTZS_Nddi>;
4771 // Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
4772 defm FCVTZU_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11111, "fcvtzu">;
4773 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvts_n_u32_f32,
4774 int_aarch64_neon_vcvtd_n_u64_f64,
4775 FCVTZU_Nssi, FCVTZU_Nddi>;
4777 // Patterns For Convert Instructions Between v1f64 and v1i64
4778 class Neon_ScalarShiftImm_cvtf_v1f64_pattern<SDPatternOperator opnode,
4780 : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4781 (INST FPR64:$Rn, imm:$Imm)>;
4783 class Neon_ScalarShiftImm_fcvt_v1f64_pattern<SDPatternOperator opnode,
4785 : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4786 (INST FPR64:$Rn, imm:$Imm)>;
4788 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxs2fp,
4791 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxu2fp,
4794 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxs,
4797 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxu,
4800 // Scalar Integer Add
4801 let isCommutable = 1 in {
4802 def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
4805 // Scalar Integer Sub
4806 def SUBddd : NeonI_Scalar3Same_D_size<0b1, 0b10000, "sub">;
4808 // Pattern for Scalar Integer Add and Sub with D register only
4809 defm : Neon_Scalar3Same_D_size_patterns<add, ADDddd>;
4810 defm : Neon_Scalar3Same_D_size_patterns<sub, SUBddd>;
4812 // Patterns to match llvm.aarch64.* intrinsic for Scalar Add, Sub
4813 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vaddds, ADDddd>;
4814 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vadddu, ADDddd>;
4815 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubds, SUBddd>;
4816 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubdu, SUBddd>;
4818 // Scalar Integer Saturating Add (Signed, Unsigned)
4819 defm SQADD : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00001, "sqadd", 1>;
4820 defm UQADD : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00001, "uqadd", 1>;
4822 // Scalar Integer Saturating Sub (Signed, Unsigned)
4823 defm SQSUB : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00101, "sqsub", 0>;
4824 defm UQSUB : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00101, "uqsub", 0>;
4827 // Patterns to match llvm.aarch64.* intrinsic for
4828 // Scalar Integer Saturating Add, Sub (Signed, Unsigned)
4829 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqadds, SQADDbbb,
4830 SQADDhhh, SQADDsss, SQADDddd>;
4831 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqaddu, UQADDbbb,
4832 UQADDhhh, UQADDsss, UQADDddd>;
4833 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubs, SQSUBbbb,
4834 SQSUBhhh, SQSUBsss, SQSUBddd>;
4835 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubu, UQSUBbbb,
4836 UQSUBhhh, UQSUBsss, UQSUBddd>;
4838 // Scalar Integer Saturating Doubling Multiply Half High
4839 defm SQDMULH : NeonI_Scalar3Same_HS_sizes<0b0, 0b10110, "sqdmulh", 1>;
4841 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4842 defm SQRDMULH : NeonI_Scalar3Same_HS_sizes<0b1, 0b10110, "sqrdmulh", 1>;
4844 // Patterns to match llvm.arm.* intrinsic for
4845 // Scalar Integer Saturating Doubling Multiply Half High and
4846 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4847 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqdmulh, SQDMULHhhh,
4849 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqrdmulh, SQRDMULHhhh,
4852 // Scalar Floating-point Multiply Extended
4853 defm FMULX : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11011, "fmulx", 1>;
4855 // Scalar Floating-point Reciprocal Step
4856 defm FRECPS : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11111, "frecps", 0>;
4858 // Scalar Floating-point Reciprocal Square Root Step
4859 defm FRSQRTS : NeonI_Scalar3Same_SD_sizes<0b0, 0b1, 0b11111, "frsqrts", 0>;
4861 // Patterns to match llvm.arm.* intrinsic for
4862 // Scalar Floating-point Reciprocal Step and
4863 // Scalar Floating-point Reciprocal Square Root Step
4864 defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrecps, FRECPSsss,
4866 defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrsqrts, FRSQRTSsss,
4869 def : Pat<(v1f64 (fsqrt (v1f64 FPR64:$Rn))), (FSQRTdd FPR64:$Rn)>;
4871 // Patterns to match llvm.aarch64.* intrinsic for
4872 // Scalar Floating-point Multiply Extended,
4873 multiclass Neon_Scalar3Same_MULX_SD_size_patterns<SDPatternOperator opnode,
4875 Instruction INSTD> {
4876 def : Pat<(f32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
4877 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4878 def : Pat<(f64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
4879 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4882 defm : Neon_Scalar3Same_MULX_SD_size_patterns<int_aarch64_neon_vmulx,
4885 // Scalar Integer Shift Left (Signed, Unsigned)
4886 def SSHLddd : NeonI_Scalar3Same_D_size<0b0, 0b01000, "sshl">;
4887 def USHLddd : NeonI_Scalar3Same_D_size<0b1, 0b01000, "ushl">;
4889 // Patterns to match llvm.arm.* intrinsic for
4890 // Scalar Integer Shift Left (Signed, Unsigned)
4891 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshifts, SSHLddd>;
4892 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshiftu, USHLddd>;
4894 // Patterns to match llvm.aarch64.* intrinsic for
4895 // Scalar Integer Shift Left (Signed, Unsigned)
4896 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshlds, SSHLddd>;
4897 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshldu, USHLddd>;
4899 // Scalar Integer Saturating Shift Left (Signed, Unsigned)
4900 defm SQSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01001, "sqshl", 0>;
4901 defm UQSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01001, "uqshl", 0>;
4903 // Patterns to match llvm.aarch64.* intrinsic for
4904 // Scalar Integer Saturating Shift Letf (Signed, Unsigned)
4905 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshls, SQSHLbbb,
4906 SQSHLhhh, SQSHLsss, SQSHLddd>;
4907 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshlu, UQSHLbbb,
4908 UQSHLhhh, UQSHLsss, UQSHLddd>;
4910 // Patterns to match llvm.arm.* intrinsic for
4911 // Scalar Integer Saturating Shift Letf (Signed, Unsigned)
4912 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshifts, SQSHLddd>;
4913 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshiftu, UQSHLddd>;
4915 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4916 def SRSHLddd: NeonI_Scalar3Same_D_size<0b0, 0b01010, "srshl">;
4917 def URSHLddd: NeonI_Scalar3Same_D_size<0b1, 0b01010, "urshl">;
4919 // Patterns to match llvm.aarch64.* intrinsic for
4920 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4921 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshlds, SRSHLddd>;
4922 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshldu, URSHLddd>;
4924 // Patterns to match llvm.arm.* intrinsic for
4925 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4926 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshifts, SRSHLddd>;
4927 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshiftu, URSHLddd>;
4929 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4930 defm SQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01011, "sqrshl", 0>;
4931 defm UQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01011, "uqrshl", 0>;
4933 // Patterns to match llvm.aarch64.* intrinsic for
4934 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4935 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshls, SQRSHLbbb,
4936 SQRSHLhhh, SQRSHLsss, SQRSHLddd>;
4937 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb,
4938 UQRSHLhhh, UQRSHLsss, UQRSHLddd>;
4940 // Patterns to match llvm.arm.* intrinsic for
4941 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4942 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
4943 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
4945 // Signed Saturating Doubling Multiply-Add Long
4946 defm SQDMLAL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1001, "sqdmlal">;
4947 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlal,
4948 SQDMLALshh, SQDMLALdss>;
4950 // Signed Saturating Doubling Multiply-Subtract Long
4951 defm SQDMLSL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1011, "sqdmlsl">;
4952 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlsl,
4953 SQDMLSLshh, SQDMLSLdss>;
4955 // Signed Saturating Doubling Multiply Long
4956 defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">;
4957 defm : Neon_Scalar3Diff_HS_size_patterns<int_arm_neon_vqdmull,
4958 SQDMULLshh, SQDMULLdss>;
4960 // Scalar Signed Integer Convert To Floating-point
4961 defm SCVTF : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">;
4962 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_s32,
4963 int_aarch64_neon_vcvtf64_s64,
4966 // Scalar Unsigned Integer Convert To Floating-point
4967 defm UCVTF : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11101, "ucvtf">;
4968 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_u32,
4969 int_aarch64_neon_vcvtf64_u64,
4972 // Scalar Floating-point Converts
4973 def FCVTXN : NeonI_Scalar2SameMisc_fcvtxn_D_size<0b1, 0b10110, "fcvtxn">;
4974 def : Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<int_aarch64_neon_fcvtxn,
4977 defm FCVTNS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11010, "fcvtns">;
4978 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtns,
4979 FCVTNSss, FCVTNSdd>;
4981 defm FCVTNU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11010, "fcvtnu">;
4982 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtnu,
4983 FCVTNUss, FCVTNUdd>;
4985 defm FCVTMS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11011, "fcvtms">;
4986 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtms,
4987 FCVTMSss, FCVTMSdd>;
4989 defm FCVTMU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11011, "fcvtmu">;
4990 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtmu,
4991 FCVTMUss, FCVTMUdd>;
4993 defm FCVTAS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11100, "fcvtas">;
4994 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtas,
4995 FCVTASss, FCVTASdd>;
4997 defm FCVTAU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11100, "fcvtau">;
4998 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtau,
4999 FCVTAUss, FCVTAUdd>;
5001 defm FCVTPS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11010, "fcvtps">;
5002 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtps,
5003 FCVTPSss, FCVTPSdd>;
5005 defm FCVTPU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11010, "fcvtpu">;
5006 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtpu,
5007 FCVTPUss, FCVTPUdd>;
5009 defm FCVTZS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11011, "fcvtzs">;
5010 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzs,
5011 FCVTZSss, FCVTZSdd>;
5013 defm FCVTZU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11011, "fcvtzu">;
5014 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzu,
5015 FCVTZUss, FCVTZUdd>;
5017 // Patterns For Convert Instructions Between v1f64 and v1i64
5018 class Neon_Scalar2SameMisc_cvtf_v1f64_pattern<SDPatternOperator opnode,
5020 : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5022 class Neon_Scalar2SameMisc_fcvt_v1f64_pattern<SDPatternOperator opnode,
5024 : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5026 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<sint_to_fp, SCVTFdd>;
5027 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<uint_to_fp, UCVTFdd>;
5029 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_sint, FCVTZSdd>;
5030 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_uint, FCVTZUdd>;
5032 // Scalar Floating-point Reciprocal Estimate
5033 defm FRECPE : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11101, "frecpe">;
5034 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrecpe,
5035 FRECPEss, FRECPEdd>;
5037 // Scalar Floating-point Reciprocal Exponent
5038 defm FRECPX : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11111, "frecpx">;
5039 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpx,
5040 FRECPXss, FRECPXdd>;
5042 // Scalar Floating-point Reciprocal Square Root Estimate
5043 defm FRSQRTE: NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11101, "frsqrte">;
5044 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrsqrte,
5045 FRSQRTEss, FRSQRTEdd>;
5047 // Scalar Floating-point Round
5048 class Neon_ScalarFloatRound_pattern<SDPatternOperator opnode, Instruction INST>
5049 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5051 def : Neon_ScalarFloatRound_pattern<fceil, FRINTPdd>;
5052 def : Neon_ScalarFloatRound_pattern<ffloor, FRINTMdd>;
5053 def : Neon_ScalarFloatRound_pattern<ftrunc, FRINTZdd>;
5054 def : Neon_ScalarFloatRound_pattern<frint, FRINTXdd>;
5055 def : Neon_ScalarFloatRound_pattern<fnearbyint, FRINTIdd>;
5056 def : Neon_ScalarFloatRound_pattern<frnd, FRINTAdd>;
5057 def : Neon_ScalarFloatRound_pattern<int_aarch64_neon_frintn, FRINTNdd>;
5059 // Scalar Integer Compare
5061 // Scalar Compare Bitwise Equal
5062 def CMEQddd: NeonI_Scalar3Same_D_size<0b1, 0b10001, "cmeq">;
5063 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vceq, CMEQddd>;
5065 class Neon_Scalar3Same_cmp_D_size_v1_patterns<SDPatternOperator opnode,
5068 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm), CC)),
5069 (INSTD FPR64:$Rn, FPR64:$Rm)>;
5071 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMEQddd, SETEQ>;
5073 // Scalar Compare Signed Greather Than Or Equal
5074 def CMGEddd: NeonI_Scalar3Same_D_size<0b0, 0b00111, "cmge">;
5075 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcge, CMGEddd>;
5076 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGEddd, SETGE>;
5078 // Scalar Compare Unsigned Higher Or Same
5079 def CMHSddd: NeonI_Scalar3Same_D_size<0b1, 0b00111, "cmhs">;
5080 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchs, CMHSddd>;
5081 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHSddd, SETUGE>;
5083 // Scalar Compare Unsigned Higher
5084 def CMHIddd: NeonI_Scalar3Same_D_size<0b1, 0b00110, "cmhi">;
5085 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchi, CMHIddd>;
5086 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHIddd, SETUGT>;
5088 // Scalar Compare Signed Greater Than
5089 def CMGTddd: NeonI_Scalar3Same_D_size<0b0, 0b00110, "cmgt">;
5090 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcgt, CMGTddd>;
5091 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGTddd, SETGT>;
5093 // Scalar Compare Bitwise Test Bits
5094 def CMTSTddd: NeonI_Scalar3Same_D_size<0b0, 0b10001, "cmtst">;
5095 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vtstd, CMTSTddd>;
5096 def : Neon_Scalar3Same_cmp_D_size_patterns<Neon_tst, CMTSTddd>;
5098 // Scalar Compare Bitwise Equal To Zero
5099 def CMEQddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01001, "cmeq">;
5100 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vceq,
5102 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETEQ, CMEQddi>;
5104 // Scalar Compare Signed Greather Than Or Equal To Zero
5105 def CMGEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01000, "cmge">;
5106 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcge,
5108 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGE, CMGEddi>;
5110 // Scalar Compare Signed Greater Than Zero
5111 def CMGTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01000, "cmgt">;
5112 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcgt,
5114 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGT, CMGTddi>;
5116 // Scalar Compare Signed Less Than Or Equal To Zero
5117 def CMLEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01001, "cmle">;
5118 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vclez,
5120 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLE, CMLEddi>;
5122 // Scalar Compare Less Than Zero
5123 def CMLTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01010, "cmlt">;
5124 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcltz,
5126 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLT, CMLTddi>;
5128 // Scalar Floating-point Compare
5130 // Scalar Floating-point Compare Mask Equal
5131 defm FCMEQ: NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11100, "fcmeq">;
5132 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vceq,
5133 FCMEQsss, FCMEQddd>;
5134 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETEQ, FCMEQddd>;
5136 // Scalar Floating-point Compare Mask Equal To Zero
5137 defm FCMEQZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01101, "fcmeq">;
5138 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vceq,
5139 FCMEQZssi, FCMEQZddi>;
5140 def : Pat<(v1i64 (Neon_cmpz (v1f64 FPR64:$Rn), (f32 fpz32:$FPImm), SETEQ)),
5141 (FCMEQZddi FPR64:$Rn, fpz32:$FPImm)>;
5143 // Scalar Floating-point Compare Mask Greater Than Or Equal
5144 defm FCMGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11100, "fcmge">;
5145 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcge,
5146 FCMGEsss, FCMGEddd>;
5147 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGE, FCMGEddd>;
5149 // Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
5150 defm FCMGEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01100, "fcmge">;
5151 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcge,
5152 FCMGEZssi, FCMGEZddi>;
5154 // Scalar Floating-point Compare Mask Greather Than
5155 defm FCMGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11100, "fcmgt">;
5156 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcgt,
5157 FCMGTsss, FCMGTddd>;
5158 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGT, FCMGTddd>;
5160 // Scalar Floating-point Compare Mask Greather Than Zero
5161 defm FCMGTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01100, "fcmgt">;
5162 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcgt,
5163 FCMGTZssi, FCMGTZddi>;
5165 // Scalar Floating-point Compare Mask Less Than Or Equal To Zero
5166 defm FCMLEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01101, "fcmle">;
5167 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vclez,
5168 FCMLEZssi, FCMLEZddi>;
5170 // Scalar Floating-point Compare Mask Less Than Zero
5171 defm FCMLTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01110, "fcmlt">;
5172 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcltz,
5173 FCMLTZssi, FCMLTZddi>;
5175 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
5176 defm FACGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11101, "facge">;
5177 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcage,
5178 FACGEsss, FACGEddd>;
5180 // Scalar Floating-point Absolute Compare Mask Greater Than
5181 defm FACGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11101, "facgt">;
5182 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcagt,
5183 FACGTsss, FACGTddd>;
5185 // Scakar Floating-point Absolute Difference
5186 defm FABD: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11010, "fabd">;
5187 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vabd,
5190 // Scalar Absolute Value
5191 defm ABS : NeonI_Scalar2SameMisc_D_size<0b0, 0b01011, "abs">;
5192 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vabs, ABSdd>;
5194 // Scalar Signed Saturating Absolute Value
5195 defm SQABS : NeonI_Scalar2SameMisc_BHSD_size<0b0, 0b00111, "sqabs">;
5196 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqabs,
5197 SQABSbb, SQABShh, SQABSss, SQABSdd>;
5200 defm NEG : NeonI_Scalar2SameMisc_D_size<0b1, 0b01011, "neg">;
5201 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vneg, NEGdd>;
5203 // Scalar Signed Saturating Negate
5204 defm SQNEG : NeonI_Scalar2SameMisc_BHSD_size<0b1, 0b00111, "sqneg">;
5205 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqneg,
5206 SQNEGbb, SQNEGhh, SQNEGss, SQNEGdd>;
5208 // Scalar Signed Saturating Accumulated of Unsigned Value
5209 defm SUQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b0, 0b00011, "suqadd">;
5210 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vuqadd,
5212 SUQADDss, SUQADDdd>;
5214 // Scalar Unsigned Saturating Accumulated of Signed Value
5215 defm USQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b1, 0b00011, "usqadd">;
5216 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vsqadd,
5218 USQADDss, USQADDdd>;
5220 def : Pat<(v1i64 (int_aarch64_neon_suqadd (v1i64 FPR64:$Src),
5221 (v1i64 FPR64:$Rn))),
5222 (SUQADDdd FPR64:$Src, FPR64:$Rn)>;
5224 def : Pat<(v1i64 (int_aarch64_neon_usqadd (v1i64 FPR64:$Src),
5225 (v1i64 FPR64:$Rn))),
5226 (USQADDdd FPR64:$Src, FPR64:$Rn)>;
5228 def : Pat<(v1i64 (int_arm_neon_vabs (v1i64 FPR64:$Rn))),
5231 def : Pat<(v1i64 (int_arm_neon_vqabs (v1i64 FPR64:$Rn))),
5232 (SQABSdd FPR64:$Rn)>;
5234 def : Pat<(v1i64 (int_arm_neon_vqneg (v1i64 FPR64:$Rn))),
5235 (SQNEGdd FPR64:$Rn)>;
5237 def : Pat<(v1i64 (sub (v1i64 (bitconvert (v8i8 Neon_AllZero))),
5238 (v1i64 FPR64:$Rn))),
5241 // Scalar Signed Saturating Extract Unsigned Narrow
5242 defm SQXTUN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10010, "sqxtun">;
5243 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnsu,
5247 // Scalar Signed Saturating Extract Narrow
5248 defm SQXTN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b0, 0b10100, "sqxtn">;
5249 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovns,
5253 // Scalar Unsigned Saturating Extract Narrow
5254 defm UQXTN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10100, "uqxtn">;
5255 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnu,
5259 // Scalar Reduce Pairwise
5261 multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode,
5262 string asmop, bit Commutable = 0> {
5263 let isCommutable = Commutable in {
5264 def _D_2D : NeonI_ScalarPair<u, {size, 0b1}, opcode,
5265 (outs FPR64:$Rd), (ins VPR128:$Rn),
5266 !strconcat(asmop, "\t$Rd, $Rn.2d"),
5272 multiclass NeonI_ScalarPair_SD_sizes<bit u, bit size, bits<5> opcode,
5273 string asmop, bit Commutable = 0>
5274 : NeonI_ScalarPair_D_sizes<u, size, opcode, asmop, Commutable> {
5275 let isCommutable = Commutable in {
5276 def _S_2S : NeonI_ScalarPair<u, {size, 0b0}, opcode,
5277 (outs FPR32:$Rd), (ins VPR64:$Rn),
5278 !strconcat(asmop, "\t$Rd, $Rn.2s"),
5284 // Scalar Reduce Addition Pairwise (Integer) with
5285 // Pattern to match llvm.arm.* intrinsic
5286 defm ADDPvv : NeonI_ScalarPair_D_sizes<0b0, 0b1, 0b11011, "addp", 0>;
5288 // Pattern to match llvm.aarch64.* intrinsic for
5289 // Scalar Reduce Addition Pairwise (Integer)
5290 def : Pat<(v1i64 (int_aarch64_neon_vpadd (v2i64 VPR128:$Rn))),
5291 (ADDPvv_D_2D VPR128:$Rn)>;
5292 def : Pat<(v1i64 (int_aarch64_neon_vaddv (v2i64 VPR128:$Rn))),
5293 (ADDPvv_D_2D VPR128:$Rn)>;
5295 // Scalar Reduce Addition Pairwise (Floating Point)
5296 defm FADDPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01101, "faddp", 0>;
5298 // Scalar Reduce Maximum Pairwise (Floating Point)
5299 defm FMAXPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01111, "fmaxp", 0>;
5301 // Scalar Reduce Minimum Pairwise (Floating Point)
5302 defm FMINPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01111, "fminp", 0>;
5304 // Scalar Reduce maxNum Pairwise (Floating Point)
5305 defm FMAXNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01100, "fmaxnmp", 0>;
5307 // Scalar Reduce minNum Pairwise (Floating Point)
5308 defm FMINNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01100, "fminnmp", 0>;
5310 multiclass Neon_ScalarPair_SD_size_patterns<SDPatternOperator opnode,
5312 Instruction INSTD> {
5313 def : Pat<(v1f32 (opnode (v2f32 VPR64:$Rn))),
5315 def : Pat<(v1f64 (opnode (v2f64 VPR128:$Rn))),
5316 (INSTD VPR128:$Rn)>;
5319 // Patterns to match llvm.aarch64.* intrinsic for
5320 // Scalar Reduce Add, Max, Min, MaxiNum, MinNum Pairwise (Floating Point)
5321 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfadd,
5322 FADDPvv_S_2S, FADDPvv_D_2D>;
5324 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmax,
5325 FMAXPvv_S_2S, FMAXPvv_D_2D>;
5327 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmin,
5328 FMINPvv_S_2S, FMINPvv_D_2D>;
5330 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfmaxnm,
5331 FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
5333 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfminnm,
5334 FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
5336 def : Pat<(v1f32 (int_aarch64_neon_vpfadd (v4f32 VPR128:$Rn))),
5337 (FADDPvv_S_2S (v2f32
5339 (v4f32 (FADDP_4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rn))),
5342 // Scalar by element Arithmetic
5344 class NeonI_ScalarXIndexedElemArith<string asmop, bits<4> opcode,
5345 string rmlane, bit u, bit szhi, bit szlo,
5346 RegisterClass ResFPR, RegisterClass OpFPR,
5347 RegisterOperand OpVPR, Operand OpImm>
5348 : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5350 (ins OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5351 asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5358 class NeonI_ScalarXIndexedElemArith_Constraint_Impl<string asmop, bits<4> opcode,
5360 bit u, bit szhi, bit szlo,
5361 RegisterClass ResFPR,
5362 RegisterClass OpFPR,
5363 RegisterOperand OpVPR,
5365 : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5367 (ins ResFPR:$src, OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5368 asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5371 let Constraints = "$src = $Rd";
5376 // Scalar Floating Point multiply (scalar, by element)
5377 def FMULssv_4S : NeonI_ScalarXIndexedElemArith<"fmul",
5378 0b1001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5379 let Inst{11} = Imm{1}; // h
5380 let Inst{21} = Imm{0}; // l
5381 let Inst{20-16} = MRm;
5383 def FMULddv_2D : NeonI_ScalarXIndexedElemArith<"fmul",
5384 0b1001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5385 let Inst{11} = Imm{0}; // h
5386 let Inst{21} = 0b0; // l
5387 let Inst{20-16} = MRm;
5390 // Scalar Floating Point multiply extended (scalar, by element)
5391 def FMULXssv_4S : NeonI_ScalarXIndexedElemArith<"fmulx",
5392 0b1001, ".s", 0b1, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5393 let Inst{11} = Imm{1}; // h
5394 let Inst{21} = Imm{0}; // l
5395 let Inst{20-16} = MRm;
5397 def FMULXddv_2D : NeonI_ScalarXIndexedElemArith<"fmulx",
5398 0b1001, ".d", 0b1, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5399 let Inst{11} = Imm{0}; // h
5400 let Inst{21} = 0b0; // l
5401 let Inst{20-16} = MRm;
5404 multiclass Neon_ScalarXIndexedElem_MUL_MULX_Patterns<
5405 SDPatternOperator opnode,
5407 ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5408 ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5410 def : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5411 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)))),
5412 (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5414 def : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5415 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)))),
5416 (ResTy (INST (ResTy FPRC:$Rn),
5417 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5421 def : Pat<(ResTy (opnode
5422 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5424 (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5426 def : Pat<(ResTy (opnode
5427 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5429 (ResTy (INST (ResTy FPRC:$Rn),
5430 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5434 // Patterns for Scalar Floating Point multiply (scalar, by element)
5435 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULssv_4S,
5436 f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5437 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULddv_2D,
5438 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5440 // Patterns for Scalar Floating Point multiply extended (scalar, by element)
5441 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5442 FMULXssv_4S, f32, FPR32, v4f32, neon_uimm2_bare,
5443 v2f32, v4f32, neon_uimm1_bare>;
5444 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5445 FMULXddv_2D, f64, FPR64, v2f64, neon_uimm1_bare,
5446 v1f64, v2f64, neon_uimm0_bare>;
5449 // Scalar Floating Point fused multiply-add (scalar, by element)
5450 def FMLAssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5451 0b0001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5452 let Inst{11} = Imm{1}; // h
5453 let Inst{21} = Imm{0}; // l
5454 let Inst{20-16} = MRm;
5456 def FMLAddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5457 0b0001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5458 let Inst{11} = Imm{0}; // h
5459 let Inst{21} = 0b0; // l
5460 let Inst{20-16} = MRm;
5463 // Scalar Floating Point fused multiply-subtract (scalar, by element)
5464 def FMLSssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5465 0b0101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5466 let Inst{11} = Imm{1}; // h
5467 let Inst{21} = Imm{0}; // l
5468 let Inst{20-16} = MRm;
5470 def FMLSddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5471 0b0101, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5472 let Inst{11} = Imm{0}; // h
5473 let Inst{21} = 0b0; // l
5474 let Inst{20-16} = MRm;
5476 // We are allowed to match the fma instruction regardless of compile options.
5477 multiclass Neon_ScalarXIndexedElem_FMA_Patterns<
5478 Instruction FMLAI, Instruction FMLSI,
5479 ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5480 ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5482 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5483 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5485 (ResTy (FMLAI (ResTy FPRC:$Ra),
5486 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5488 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5489 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5491 (ResTy (FMLAI (ResTy FPRC:$Ra),
5493 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5496 // swapped fmla operands
5497 def : Pat<(ResTy (fma
5498 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5501 (ResTy (FMLAI (ResTy FPRC:$Ra),
5502 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5504 def : Pat<(ResTy (fma
5505 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5508 (ResTy (FMLAI (ResTy FPRC:$Ra),
5510 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5514 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5515 (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5517 (ResTy (FMLSI (ResTy FPRC:$Ra),
5518 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5520 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5521 (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5523 (ResTy (FMLSI (ResTy FPRC:$Ra),
5525 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5528 // swapped fmls operands
5529 def : Pat<(ResTy (fma
5530 (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5533 (ResTy (FMLSI (ResTy FPRC:$Ra),
5534 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5536 def : Pat<(ResTy (fma
5537 (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5540 (ResTy (FMLSI (ResTy FPRC:$Ra),
5542 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5546 // Scalar Floating Point fused multiply-add and
5547 // multiply-subtract (scalar, by element)
5548 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAssv_4S, FMLSssv_4S,
5549 f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5550 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5551 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5552 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5553 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5555 // Scalar Signed saturating doubling multiply long (scalar, by element)
5556 def SQDMULLshv_4H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5557 0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5558 let Inst{11} = 0b0; // h
5559 let Inst{21} = Imm{1}; // l
5560 let Inst{20} = Imm{0}; // m
5561 let Inst{19-16} = MRm{3-0};
5563 def SQDMULLshv_8H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5564 0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5565 let Inst{11} = Imm{2}; // h
5566 let Inst{21} = Imm{1}; // l
5567 let Inst{20} = Imm{0}; // m
5568 let Inst{19-16} = MRm{3-0};
5570 def SQDMULLdsv_2S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5571 0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5572 let Inst{11} = 0b0; // h
5573 let Inst{21} = Imm{0}; // l
5574 let Inst{20-16} = MRm;
5576 def SQDMULLdsv_4S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5577 0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5578 let Inst{11} = Imm{1}; // h
5579 let Inst{21} = Imm{0}; // l
5580 let Inst{20-16} = MRm;
5583 multiclass Neon_ScalarXIndexedElem_MUL_Patterns<
5584 SDPatternOperator opnode,
5586 ValueType ResTy, RegisterClass FPRC,
5587 ValueType OpVTy, ValueType OpTy,
5588 ValueType VecOpTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5590 def : Pat<(ResTy (opnode (OpVTy FPRC:$Rn),
5591 (OpVTy (scalar_to_vector
5592 (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))))),
5593 (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5596 def : Pat<(ResTy (opnode
5597 (OpVTy (scalar_to_vector
5598 (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))),
5600 (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5604 // Patterns for Scalar Signed saturating doubling
5605 // multiply long (scalar, by element)
5606 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5607 SQDMULLshv_4H, v1i32, FPR16, v1i16, i16, v4i16,
5608 i32, VPR64Lo, neon_uimm2_bare>;
5609 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5610 SQDMULLshv_8H, v1i32, FPR16, v1i16, i16, v8i16,
5611 i32, VPR128Lo, neon_uimm3_bare>;
5612 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5613 SQDMULLdsv_2S, v1i64, FPR32, v1i32, i32, v2i32,
5614 i32, VPR64Lo, neon_uimm1_bare>;
5615 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5616 SQDMULLdsv_4S, v1i64, FPR32, v1i32, i32, v4i32,
5617 i32, VPR128Lo, neon_uimm2_bare>;
5619 // Scalar Signed saturating doubling multiply-add long (scalar, by element)
5620 def SQDMLALshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5621 0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5622 let Inst{11} = 0b0; // h
5623 let Inst{21} = Imm{1}; // l
5624 let Inst{20} = Imm{0}; // m
5625 let Inst{19-16} = MRm{3-0};
5627 def SQDMLALshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5628 0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5629 let Inst{11} = Imm{2}; // h
5630 let Inst{21} = Imm{1}; // l
5631 let Inst{20} = Imm{0}; // m
5632 let Inst{19-16} = MRm{3-0};
5634 def SQDMLALdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5635 0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5636 let Inst{11} = 0b0; // h
5637 let Inst{21} = Imm{0}; // l
5638 let Inst{20-16} = MRm;
5640 def SQDMLALdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5641 0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5642 let Inst{11} = Imm{1}; // h
5643 let Inst{21} = Imm{0}; // l
5644 let Inst{20-16} = MRm;
5647 // Scalar Signed saturating doubling
5648 // multiply-subtract long (scalar, by element)
5649 def SQDMLSLshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5650 0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5651 let Inst{11} = 0b0; // h
5652 let Inst{21} = Imm{1}; // l
5653 let Inst{20} = Imm{0}; // m
5654 let Inst{19-16} = MRm{3-0};
5656 def SQDMLSLshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5657 0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5658 let Inst{11} = Imm{2}; // h
5659 let Inst{21} = Imm{1}; // l
5660 let Inst{20} = Imm{0}; // m
5661 let Inst{19-16} = MRm{3-0};
5663 def SQDMLSLdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5664 0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5665 let Inst{11} = 0b0; // h
5666 let Inst{21} = Imm{0}; // l
5667 let Inst{20-16} = MRm;
5669 def SQDMLSLdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5670 0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5671 let Inst{11} = Imm{1}; // h
5672 let Inst{21} = Imm{0}; // l
5673 let Inst{20-16} = MRm;
5676 multiclass Neon_ScalarXIndexedElem_MLAL_Patterns<
5677 SDPatternOperator opnode,
5678 SDPatternOperator coreopnode,
5680 ValueType ResTy, RegisterClass ResFPRC, RegisterClass FPRC,
5682 ValueType OpVTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5684 def : Pat<(ResTy (opnode
5685 (ResTy ResFPRC:$Ra),
5686 (ResTy (coreopnode (OpTy FPRC:$Rn),
5687 (OpTy (scalar_to_vector
5688 (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))))))),
5689 (ResTy (INST (ResTy ResFPRC:$Ra),
5690 (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5693 def : Pat<(ResTy (opnode
5694 (ResTy ResFPRC:$Ra),
5696 (OpTy (scalar_to_vector
5697 (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))),
5698 (OpTy FPRC:$Rn))))),
5699 (ResTy (INST (ResTy ResFPRC:$Ra),
5700 (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5703 // Patterns for Scalar Signed saturating
5704 // doubling multiply-add long (scalar, by element)
5705 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5706 int_arm_neon_vqdmull, SQDMLALshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5707 i32, VPR64Lo, neon_uimm2_bare>;
5708 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5709 int_arm_neon_vqdmull, SQDMLALshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5710 i32, VPR128Lo, neon_uimm3_bare>;
5711 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5712 int_arm_neon_vqdmull, SQDMLALdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5713 i32, VPR64Lo, neon_uimm1_bare>;
5714 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5715 int_arm_neon_vqdmull, SQDMLALdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5716 i32, VPR128Lo, neon_uimm2_bare>;
5718 // Patterns for Scalar Signed saturating
5719 // doubling multiply-sub long (scalar, by element)
5720 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5721 int_arm_neon_vqdmull, SQDMLSLshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5722 i32, VPR64Lo, neon_uimm2_bare>;
5723 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5724 int_arm_neon_vqdmull, SQDMLSLshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5725 i32, VPR128Lo, neon_uimm3_bare>;
5726 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5727 int_arm_neon_vqdmull, SQDMLSLdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5728 i32, VPR64Lo, neon_uimm1_bare>;
5729 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5730 int_arm_neon_vqdmull, SQDMLSLdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5731 i32, VPR128Lo, neon_uimm2_bare>;
5733 // Scalar general arithmetic operation
5734 class Neon_Scalar_GeneralMath2D_pattern<SDPatternOperator opnode,
5736 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5738 class Neon_Scalar_GeneralMath3D_pattern<SDPatternOperator opnode,
5740 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5741 (INST FPR64:$Rn, FPR64:$Rm)>;
5743 class Neon_Scalar_GeneralMath4D_pattern<SDPatternOperator opnode,
5745 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm),
5746 (v1f64 FPR64:$Ra))),
5747 (INST FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
5749 def : Neon_Scalar_GeneralMath3D_pattern<fadd, FADDddd>;
5750 def : Neon_Scalar_GeneralMath3D_pattern<fmul, FMULddd>;
5751 def : Neon_Scalar_GeneralMath3D_pattern<fsub, FSUBddd>;
5752 def : Neon_Scalar_GeneralMath3D_pattern<fdiv, FDIVddd>;
5753 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vabds, FABDddd>;
5754 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmaxs, FMAXddd>;
5755 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmins, FMINddd>;
5756 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vmaxnm, FMAXNMddd>;
5757 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vminnm, FMINNMddd>;
5759 def : Neon_Scalar_GeneralMath2D_pattern<fabs, FABSdd>;
5760 def : Neon_Scalar_GeneralMath2D_pattern<fneg, FNEGdd>;
5762 def : Neon_Scalar_GeneralMath4D_pattern<fma, FMADDdddd>;
5763 def : Neon_Scalar_GeneralMath4D_pattern<fmsub, FMSUBdddd>;
5765 // Scalar Signed saturating doubling multiply returning
5766 // high half (scalar, by element)
5767 def SQDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5768 0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5769 let Inst{11} = 0b0; // h
5770 let Inst{21} = Imm{1}; // l
5771 let Inst{20} = Imm{0}; // m
5772 let Inst{19-16} = MRm{3-0};
5774 def SQDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5775 0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5776 let Inst{11} = Imm{2}; // h
5777 let Inst{21} = Imm{1}; // l
5778 let Inst{20} = Imm{0}; // m
5779 let Inst{19-16} = MRm{3-0};
5781 def SQDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5782 0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5783 let Inst{11} = 0b0; // h
5784 let Inst{21} = Imm{0}; // l
5785 let Inst{20-16} = MRm;
5787 def SQDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5788 0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5789 let Inst{11} = Imm{1}; // h
5790 let Inst{21} = Imm{0}; // l
5791 let Inst{20-16} = MRm;
5794 // Patterns for Scalar Signed saturating doubling multiply returning
5795 // high half (scalar, by element)
5796 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5797 SQDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16,
5798 i32, VPR64Lo, neon_uimm2_bare>;
5799 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5800 SQDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16,
5801 i32, VPR128Lo, neon_uimm3_bare>;
5802 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5803 SQDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32,
5804 i32, VPR64Lo, neon_uimm1_bare>;
5805 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5806 SQDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32,
5807 i32, VPR128Lo, neon_uimm2_bare>;
5809 // Scalar Signed saturating rounding doubling multiply
5810 // returning high half (scalar, by element)
5811 def SQRDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5812 0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5813 let Inst{11} = 0b0; // h
5814 let Inst{21} = Imm{1}; // l
5815 let Inst{20} = Imm{0}; // m
5816 let Inst{19-16} = MRm{3-0};
5818 def SQRDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5819 0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5820 let Inst{11} = Imm{2}; // h
5821 let Inst{21} = Imm{1}; // l
5822 let Inst{20} = Imm{0}; // m
5823 let Inst{19-16} = MRm{3-0};
5825 def SQRDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5826 0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5827 let Inst{11} = 0b0; // h
5828 let Inst{21} = Imm{0}; // l
5829 let Inst{20-16} = MRm;
5831 def SQRDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5832 0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5833 let Inst{11} = Imm{1}; // h
5834 let Inst{21} = Imm{0}; // l
5835 let Inst{20-16} = MRm;
5838 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5839 SQRDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16, i32,
5840 VPR64Lo, neon_uimm2_bare>;
5841 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5842 SQRDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16, i32,
5843 VPR128Lo, neon_uimm3_bare>;
5844 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5845 SQRDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32, i32,
5846 VPR64Lo, neon_uimm1_bare>;
5847 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5848 SQRDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32, i32,
5849 VPR128Lo, neon_uimm2_bare>;
5851 // Scalar Copy - DUP element to scalar
5852 class NeonI_Scalar_DUP<string asmop, string asmlane,
5853 RegisterClass ResRC, RegisterOperand VPRC,
5855 : NeonI_ScalarCopy<(outs ResRC:$Rd), (ins VPRC:$Rn, OpImm:$Imm),
5856 asmop # "\t$Rd, $Rn." # asmlane # "[$Imm]",
5862 def DUPbv_B : NeonI_Scalar_DUP<"dup", "b", FPR8, VPR128, neon_uimm4_bare> {
5863 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
5865 def DUPhv_H : NeonI_Scalar_DUP<"dup", "h", FPR16, VPR128, neon_uimm3_bare> {
5866 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
5868 def DUPsv_S : NeonI_Scalar_DUP<"dup", "s", FPR32, VPR128, neon_uimm2_bare> {
5869 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
5871 def DUPdv_D : NeonI_Scalar_DUP<"dup", "d", FPR64, VPR128, neon_uimm1_bare> {
5872 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
5875 multiclass NeonI_Scalar_DUP_Elt_pattern<Instruction DUPI, ValueType ResTy,
5876 ValueType OpTy, Operand OpImm,
5877 ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5878 def : Pat<(ResTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
5879 (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5881 def : Pat<(ResTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
5883 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5887 // Patterns for vector extract of FP data using scalar DUP instructions
5888 defm : NeonI_Scalar_DUP_Elt_pattern<DUPsv_S, f32,
5889 v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5890 defm : NeonI_Scalar_DUP_Elt_pattern<DUPdv_D, f64,
5891 v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5893 multiclass NeonI_Scalar_DUP_Ext_Vec_pattern<Instruction DUPI,
5894 ValueType ResTy, ValueType OpTy,Operand OpLImm,
5895 ValueType NOpTy, ValueType ExTy, Operand OpNImm> {
5897 def : Pat<(ResTy (extract_subvector (OpTy VPR128:$Rn), OpLImm:$Imm)),
5898 (ResTy (DUPI VPR128:$Rn, OpLImm:$Imm))>;
5900 def : Pat<(ResTy (extract_subvector (NOpTy VPR64:$Rn), OpNImm:$Imm)),
5902 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5906 // Patterns for extract subvectors of v1ix data using scalar DUP instructions.
5907 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPbv_B, v1i8, v16i8, neon_uimm4_bare,
5908 v8i8, v16i8, neon_uimm3_bare>;
5909 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPhv_H, v1i16, v8i16, neon_uimm3_bare,
5910 v4i16, v8i16, neon_uimm2_bare>;
5911 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPsv_S, v1i32, v4i32, neon_uimm2_bare,
5912 v2i32, v4i32, neon_uimm1_bare>;
5914 multiclass NeonI_Scalar_DUP_Copy_pattern1<Instruction DUPI, ValueType ResTy,
5915 ValueType OpTy, ValueType ElemTy,
5916 Operand OpImm, ValueType OpNTy,
5917 ValueType ExTy, Operand OpNImm> {
5919 def : Pat<(ResTy (vector_insert (ResTy undef),
5920 (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
5921 (neon_uimm0_bare:$Imm))),
5922 (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5924 def : Pat<(ResTy (vector_insert (ResTy undef),
5925 (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
5928 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5932 multiclass NeonI_Scalar_DUP_Copy_pattern2<Instruction DUPI, ValueType ResTy,
5933 ValueType OpTy, ValueType ElemTy,
5934 Operand OpImm, ValueType OpNTy,
5935 ValueType ExTy, Operand OpNImm> {
5937 def : Pat<(ResTy (scalar_to_vector
5938 (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)))),
5939 (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5941 def : Pat<(ResTy (scalar_to_vector
5942 (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)))),
5944 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5948 // Patterns for vector copy to v1ix and v1fx vectors using scalar DUP
5950 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPdv_D,
5951 v1i64, v2i64, i64, neon_uimm1_bare,
5952 v1i64, v2i64, neon_uimm0_bare>;
5953 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPsv_S,
5954 v1i32, v4i32, i32, neon_uimm2_bare,
5955 v2i32, v4i32, neon_uimm1_bare>;
5956 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPhv_H,
5957 v1i16, v8i16, i32, neon_uimm3_bare,
5958 v4i16, v8i16, neon_uimm2_bare>;
5959 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPbv_B,
5960 v1i8, v16i8, i32, neon_uimm4_bare,
5961 v8i8, v16i8, neon_uimm3_bare>;
5962 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPdv_D,
5963 v1f64, v2f64, f64, neon_uimm1_bare,
5964 v1f64, v2f64, neon_uimm0_bare>;
5965 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPsv_S,
5966 v1f32, v4f32, f32, neon_uimm2_bare,
5967 v2f32, v4f32, neon_uimm1_bare>;
5968 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPdv_D,
5969 v1i64, v2i64, i64, neon_uimm1_bare,
5970 v1i64, v2i64, neon_uimm0_bare>;
5971 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPsv_S,
5972 v1i32, v4i32, i32, neon_uimm2_bare,
5973 v2i32, v4i32, neon_uimm1_bare>;
5974 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPhv_H,
5975 v1i16, v8i16, i32, neon_uimm3_bare,
5976 v4i16, v8i16, neon_uimm2_bare>;
5977 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPbv_B,
5978 v1i8, v16i8, i32, neon_uimm4_bare,
5979 v8i8, v16i8, neon_uimm3_bare>;
5980 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPdv_D,
5981 v1f64, v2f64, f64, neon_uimm1_bare,
5982 v1f64, v2f64, neon_uimm0_bare>;
5983 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPsv_S,
5984 v1f32, v4f32, f32, neon_uimm2_bare,
5985 v2f32, v4f32, neon_uimm1_bare>;
5987 multiclass NeonI_Scalar_DUP_alias<string asmop, string asmlane,
5988 Instruction DUPI, Operand OpImm,
5989 RegisterClass ResRC> {
5990 def : NeonInstAlias<!strconcat(asmop, "$Rd, $Rn" # asmlane # "[$Imm]"),
5991 (DUPI ResRC:$Rd, VPR128:$Rn, OpImm:$Imm), 0b0>;
5994 // Aliases for Scalar copy - DUP element (scalar)
5995 // FIXME: This is actually the preferred syntax but TableGen can't deal with
5996 // custom printing of aliases.
5997 defm : NeonI_Scalar_DUP_alias<"mov", ".b", DUPbv_B, neon_uimm4_bare, FPR8>;
5998 defm : NeonI_Scalar_DUP_alias<"mov", ".h", DUPhv_H, neon_uimm3_bare, FPR16>;
5999 defm : NeonI_Scalar_DUP_alias<"mov", ".s", DUPsv_S, neon_uimm2_bare, FPR32>;
6000 defm : NeonI_Scalar_DUP_alias<"mov", ".d", DUPdv_D, neon_uimm1_bare, FPR64>;
6002 multiclass NeonI_SDUP<PatFrag GetLow, PatFrag GetHigh, ValueType ResTy,
6004 def : Pat<(ResTy (GetLow VPR128:$Rn)),
6005 (ResTy (EXTRACT_SUBREG (OpTy VPR128:$Rn), sub_64))>;
6006 def : Pat<(ResTy (GetHigh VPR128:$Rn)),
6007 (ResTy (DUPdv_D (OpTy VPR128:$Rn), 1))>;
6010 defm : NeonI_SDUP<Neon_Low16B, Neon_High16B, v8i8, v16i8>;
6011 defm : NeonI_SDUP<Neon_Low8H, Neon_High8H, v4i16, v8i16>;
6012 defm : NeonI_SDUP<Neon_Low4S, Neon_High4S, v2i32, v4i32>;
6013 defm : NeonI_SDUP<Neon_Low2D, Neon_High2D, v1i64, v2i64>;
6014 defm : NeonI_SDUP<Neon_Low4float, Neon_High4float, v2f32, v4f32>;
6015 defm : NeonI_SDUP<Neon_Low2double, Neon_High2double, v1f64, v2f64>;
6017 //===----------------------------------------------------------------------===//
6018 // Non-Instruction Patterns
6019 //===----------------------------------------------------------------------===//
6021 // 64-bit vector bitcasts...
6023 def : Pat<(v1i64 (bitconvert (v8i8 VPR64:$src))), (v1i64 VPR64:$src)>;
6024 def : Pat<(v2f32 (bitconvert (v8i8 VPR64:$src))), (v2f32 VPR64:$src)>;
6025 def : Pat<(v2i32 (bitconvert (v8i8 VPR64:$src))), (v2i32 VPR64:$src)>;
6026 def : Pat<(v4i16 (bitconvert (v8i8 VPR64:$src))), (v4i16 VPR64:$src)>;
6028 def : Pat<(v1i64 (bitconvert (v4i16 VPR64:$src))), (v1i64 VPR64:$src)>;
6029 def : Pat<(v2i32 (bitconvert (v4i16 VPR64:$src))), (v2i32 VPR64:$src)>;
6030 def : Pat<(v2f32 (bitconvert (v4i16 VPR64:$src))), (v2f32 VPR64:$src)>;
6031 def : Pat<(v8i8 (bitconvert (v4i16 VPR64:$src))), (v8i8 VPR64:$src)>;
6033 def : Pat<(v1i64 (bitconvert (v2i32 VPR64:$src))), (v1i64 VPR64:$src)>;
6034 def : Pat<(v2f32 (bitconvert (v2i32 VPR64:$src))), (v2f32 VPR64:$src)>;
6035 def : Pat<(v4i16 (bitconvert (v2i32 VPR64:$src))), (v4i16 VPR64:$src)>;
6036 def : Pat<(v8i8 (bitconvert (v2i32 VPR64:$src))), (v8i8 VPR64:$src)>;
6038 def : Pat<(v1i64 (bitconvert (v2f32 VPR64:$src))), (v1i64 VPR64:$src)>;
6039 def : Pat<(v2i32 (bitconvert (v2f32 VPR64:$src))), (v2i32 VPR64:$src)>;
6040 def : Pat<(v4i16 (bitconvert (v2f32 VPR64:$src))), (v4i16 VPR64:$src)>;
6041 def : Pat<(v8i8 (bitconvert (v2f32 VPR64:$src))), (v8i8 VPR64:$src)>;
6043 def : Pat<(v2f32 (bitconvert (v1i64 VPR64:$src))), (v2f32 VPR64:$src)>;
6044 def : Pat<(v2i32 (bitconvert (v1i64 VPR64:$src))), (v2i32 VPR64:$src)>;
6045 def : Pat<(v4i16 (bitconvert (v1i64 VPR64:$src))), (v4i16 VPR64:$src)>;
6046 def : Pat<(v8i8 (bitconvert (v1i64 VPR64:$src))), (v8i8 VPR64:$src)>;
6048 // ..and 128-bit vector bitcasts...
6050 def : Pat<(v2f64 (bitconvert (v16i8 VPR128:$src))), (v2f64 VPR128:$src)>;
6051 def : Pat<(v2i64 (bitconvert (v16i8 VPR128:$src))), (v2i64 VPR128:$src)>;
6052 def : Pat<(v4f32 (bitconvert (v16i8 VPR128:$src))), (v4f32 VPR128:$src)>;
6053 def : Pat<(v4i32 (bitconvert (v16i8 VPR128:$src))), (v4i32 VPR128:$src)>;
6054 def : Pat<(v8i16 (bitconvert (v16i8 VPR128:$src))), (v8i16 VPR128:$src)>;
6056 def : Pat<(v2f64 (bitconvert (v8i16 VPR128:$src))), (v2f64 VPR128:$src)>;
6057 def : Pat<(v2i64 (bitconvert (v8i16 VPR128:$src))), (v2i64 VPR128:$src)>;
6058 def : Pat<(v4i32 (bitconvert (v8i16 VPR128:$src))), (v4i32 VPR128:$src)>;
6059 def : Pat<(v4f32 (bitconvert (v8i16 VPR128:$src))), (v4f32 VPR128:$src)>;
6060 def : Pat<(v16i8 (bitconvert (v8i16 VPR128:$src))), (v16i8 VPR128:$src)>;
6062 def : Pat<(v2f64 (bitconvert (v4i32 VPR128:$src))), (v2f64 VPR128:$src)>;
6063 def : Pat<(v2i64 (bitconvert (v4i32 VPR128:$src))), (v2i64 VPR128:$src)>;
6064 def : Pat<(v4f32 (bitconvert (v4i32 VPR128:$src))), (v4f32 VPR128:$src)>;
6065 def : Pat<(v8i16 (bitconvert (v4i32 VPR128:$src))), (v8i16 VPR128:$src)>;
6066 def : Pat<(v16i8 (bitconvert (v4i32 VPR128:$src))), (v16i8 VPR128:$src)>;
6068 def : Pat<(v2f64 (bitconvert (v4f32 VPR128:$src))), (v2f64 VPR128:$src)>;
6069 def : Pat<(v2i64 (bitconvert (v4f32 VPR128:$src))), (v2i64 VPR128:$src)>;
6070 def : Pat<(v4i32 (bitconvert (v4f32 VPR128:$src))), (v4i32 VPR128:$src)>;
6071 def : Pat<(v8i16 (bitconvert (v4f32 VPR128:$src))), (v8i16 VPR128:$src)>;
6072 def : Pat<(v16i8 (bitconvert (v4f32 VPR128:$src))), (v16i8 VPR128:$src)>;
6074 def : Pat<(v2f64 (bitconvert (v2i64 VPR128:$src))), (v2f64 VPR128:$src)>;
6075 def : Pat<(v4f32 (bitconvert (v2i64 VPR128:$src))), (v4f32 VPR128:$src)>;
6076 def : Pat<(v4i32 (bitconvert (v2i64 VPR128:$src))), (v4i32 VPR128:$src)>;
6077 def : Pat<(v8i16 (bitconvert (v2i64 VPR128:$src))), (v8i16 VPR128:$src)>;
6078 def : Pat<(v16i8 (bitconvert (v2i64 VPR128:$src))), (v16i8 VPR128:$src)>;
6080 def : Pat<(v2i64 (bitconvert (v2f64 VPR128:$src))), (v2i64 VPR128:$src)>;
6081 def : Pat<(v4f32 (bitconvert (v2f64 VPR128:$src))), (v4f32 VPR128:$src)>;
6082 def : Pat<(v4i32 (bitconvert (v2f64 VPR128:$src))), (v4i32 VPR128:$src)>;
6083 def : Pat<(v8i16 (bitconvert (v2f64 VPR128:$src))), (v8i16 VPR128:$src)>;
6084 def : Pat<(v16i8 (bitconvert (v2f64 VPR128:$src))), (v16i8 VPR128:$src)>;
6086 // ...and scalar bitcasts...
6087 def : Pat<(f16 (bitconvert (v1i16 FPR16:$src))), (f16 FPR16:$src)>;
6088 def : Pat<(f32 (bitconvert (v1i32 FPR32:$src))), (f32 FPR32:$src)>;
6089 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
6090 def : Pat<(f32 (bitconvert (v1f32 FPR32:$src))), (f32 FPR32:$src)>;
6091 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
6093 def : Pat<(i64 (bitconvert (v1i64 FPR64:$src))), (FMOVxd $src)>;
6094 def : Pat<(i64 (bitconvert (v1f64 FPR64:$src))), (FMOVxd $src)>;
6095 def : Pat<(i64 (bitconvert (v2i32 FPR64:$src))), (FMOVxd $src)>;
6096 def : Pat<(i64 (bitconvert (v2f32 FPR64:$src))), (FMOVxd $src)>;
6097 def : Pat<(i64 (bitconvert (v4i16 FPR64:$src))), (FMOVxd $src)>;
6098 def : Pat<(i64 (bitconvert (v8i8 FPR64:$src))), (FMOVxd $src)>;
6100 def : Pat<(i32 (bitconvert (v1i32 FPR32:$src))), (FMOVws $src)>;
6102 def : Pat<(v8i8 (bitconvert (v1i64 VPR64:$src))), (v8i8 VPR64:$src)>;
6103 def : Pat<(v4i16 (bitconvert (v1i64 VPR64:$src))), (v4i16 VPR64:$src)>;
6104 def : Pat<(v2i32 (bitconvert (v1i64 VPR64:$src))), (v2i32 VPR64:$src)>;
6106 def : Pat<(f64 (bitconvert (v8i8 VPR64:$src))), (f64 VPR64:$src)>;
6107 def : Pat<(f64 (bitconvert (v4i16 VPR64:$src))), (f64 VPR64:$src)>;
6108 def : Pat<(f64 (bitconvert (v2i32 VPR64:$src))), (f64 VPR64:$src)>;
6109 def : Pat<(f64 (bitconvert (v2f32 VPR64:$src))), (f64 VPR64:$src)>;
6110 def : Pat<(f64 (bitconvert (v1i64 VPR64:$src))), (f64 VPR64:$src)>;
6112 def : Pat<(f128 (bitconvert (v16i8 VPR128:$src))), (f128 VPR128:$src)>;
6113 def : Pat<(f128 (bitconvert (v8i16 VPR128:$src))), (f128 VPR128:$src)>;
6114 def : Pat<(f128 (bitconvert (v4i32 VPR128:$src))), (f128 VPR128:$src)>;
6115 def : Pat<(f128 (bitconvert (v2i64 VPR128:$src))), (f128 VPR128:$src)>;
6116 def : Pat<(f128 (bitconvert (v4f32 VPR128:$src))), (f128 VPR128:$src)>;
6117 def : Pat<(f128 (bitconvert (v2f64 VPR128:$src))), (f128 VPR128:$src)>;
6119 def : Pat<(v1i16 (bitconvert (f16 FPR16:$src))), (v1i16 FPR16:$src)>;
6120 def : Pat<(v1i32 (bitconvert (f32 FPR32:$src))), (v1i32 FPR32:$src)>;
6121 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
6122 def : Pat<(v1f32 (bitconvert (f32 FPR32:$src))), (v1f32 FPR32:$src)>;
6123 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
6125 def : Pat<(v1i64 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6126 def : Pat<(v1f64 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6127 def : Pat<(v2i32 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6128 def : Pat<(v2f32 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6129 def : Pat<(v4i16 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6130 def : Pat<(v8i8 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6132 def : Pat<(v1i32 (bitconvert (i32 GPR32:$src))), (FMOVsw $src)>;
6134 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
6135 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
6136 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
6137 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
6138 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
6140 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
6141 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
6142 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
6143 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
6144 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
6145 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
6147 // Scalar Three Same
6149 def neon_uimm3 : Operand<i64>,
6150 ImmLeaf<i64, [{return Imm < 8;}]> {
6151 let ParserMatchClass = uimm3_asmoperand;
6152 let PrintMethod = "printUImmHexOperand";
6155 def neon_uimm4 : Operand<i64>,
6156 ImmLeaf<i64, [{return Imm < 16;}]> {
6157 let ParserMatchClass = uimm4_asmoperand;
6158 let PrintMethod = "printUImmHexOperand";
6162 class NeonI_Extract<bit q, bits<2> op2, string asmop,
6163 string OpS, RegisterOperand OpVPR, Operand OpImm>
6164 : NeonI_BitExtract<q, op2, (outs OpVPR:$Rd),
6165 (ins OpVPR:$Rn, OpVPR:$Rm, OpImm:$Index),
6166 asmop # "\t$Rd." # OpS # ", $Rn." # OpS #
6167 ", $Rm." # OpS # ", $Index",
6173 def EXTvvvi_8b : NeonI_Extract<0b0, 0b00, "ext", "8b",
6174 VPR64, neon_uimm3> {
6175 let Inst{14-11} = {0b0, Index{2}, Index{1}, Index{0}};
6178 def EXTvvvi_16b: NeonI_Extract<0b1, 0b00, "ext", "16b",
6179 VPR128, neon_uimm4> {
6180 let Inst{14-11} = Index;
6183 class NI_Extract<ValueType OpTy, RegisterOperand OpVPR, Instruction INST,
6185 : Pat<(OpTy (Neon_vextract (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm),
6187 (INST OpVPR:$Rn, OpVPR:$Rm, OpImm:$Imm)>;
6189 def : NI_Extract<v8i8, VPR64, EXTvvvi_8b, neon_uimm3>;
6190 def : NI_Extract<v4i16, VPR64, EXTvvvi_8b, neon_uimm3>;
6191 def : NI_Extract<v2i32, VPR64, EXTvvvi_8b, neon_uimm3>;
6192 def : NI_Extract<v1i64, VPR64, EXTvvvi_8b, neon_uimm3>;
6193 def : NI_Extract<v2f32, VPR64, EXTvvvi_8b, neon_uimm3>;
6194 def : NI_Extract<v1f64, VPR64, EXTvvvi_8b, neon_uimm3>;
6195 def : NI_Extract<v16i8, VPR128, EXTvvvi_16b, neon_uimm4>;
6196 def : NI_Extract<v8i16, VPR128, EXTvvvi_16b, neon_uimm4>;
6197 def : NI_Extract<v4i32, VPR128, EXTvvvi_16b, neon_uimm4>;
6198 def : NI_Extract<v2i64, VPR128, EXTvvvi_16b, neon_uimm4>;
6199 def : NI_Extract<v4f32, VPR128, EXTvvvi_16b, neon_uimm4>;
6200 def : NI_Extract<v2f64, VPR128, EXTvvvi_16b, neon_uimm4>;
6203 class NI_TBL<bit q, bits<2> op2, bits<2> len, bit op,
6204 string asmop, string OpS, RegisterOperand OpVPR,
6205 RegisterOperand VecList>
6206 : NeonI_TBL<q, op2, len, op,
6207 (outs OpVPR:$Rd), (ins VecList:$Rn, OpVPR:$Rm),
6208 asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6212 // The vectors in look up table are always 16b
6213 multiclass NI_TBL_pat<bits<2> len, bit op, string asmop, string List> {
6214 def _8b : NI_TBL<0, 0b00, len, op, asmop, "8b", VPR64,
6215 !cast<RegisterOperand>(List # "16B_operand")>;
6217 def _16b : NI_TBL<1, 0b00, len, op, asmop, "16b", VPR128,
6218 !cast<RegisterOperand>(List # "16B_operand")>;
6221 defm TBL1 : NI_TBL_pat<0b00, 0b0, "tbl", "VOne">;
6222 defm TBL2 : NI_TBL_pat<0b01, 0b0, "tbl", "VPair">;
6223 defm TBL3 : NI_TBL_pat<0b10, 0b0, "tbl", "VTriple">;
6224 defm TBL4 : NI_TBL_pat<0b11, 0b0, "tbl", "VQuad">;
6226 // Table lookup extention
6227 class NI_TBX<bit q, bits<2> op2, bits<2> len, bit op,
6228 string asmop, string OpS, RegisterOperand OpVPR,
6229 RegisterOperand VecList>
6230 : NeonI_TBL<q, op2, len, op,
6231 (outs OpVPR:$Rd), (ins OpVPR:$src, VecList:$Rn, OpVPR:$Rm),
6232 asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6235 let Constraints = "$src = $Rd";
6238 // The vectors in look up table are always 16b
6239 multiclass NI_TBX_pat<bits<2> len, bit op, string asmop, string List> {
6240 def _8b : NI_TBX<0, 0b00, len, op, asmop, "8b", VPR64,
6241 !cast<RegisterOperand>(List # "16B_operand")>;
6243 def _16b : NI_TBX<1, 0b00, len, op, asmop, "16b", VPR128,
6244 !cast<RegisterOperand>(List # "16B_operand")>;
6247 defm TBX1 : NI_TBX_pat<0b00, 0b1, "tbx", "VOne">;
6248 defm TBX2 : NI_TBX_pat<0b01, 0b1, "tbx", "VPair">;
6249 defm TBX3 : NI_TBX_pat<0b10, 0b1, "tbx", "VTriple">;
6250 defm TBX4 : NI_TBX_pat<0b11, 0b1, "tbx", "VQuad">;
6252 class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
6253 RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
6254 : NeonI_copy<0b1, 0b0, 0b0011,
6255 (outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
6256 asmop # "\t$Rd." # Res # "[$Imm], $Rn",
6257 [(set (ResTy VPR128:$Rd),
6258 (ResTy (vector_insert
6259 (ResTy VPR128:$src),
6264 let Constraints = "$src = $Rd";
6267 //Insert element (vector, from main)
6268 def INSbw : NeonI_INS_main<"ins", "b", v16i8, GPR32, i32,
6270 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6272 def INShw : NeonI_INS_main<"ins", "h", v8i16, GPR32, i32,
6274 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6276 def INSsw : NeonI_INS_main<"ins", "s", v4i32, GPR32, i32,
6278 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6280 def INSdx : NeonI_INS_main<"ins", "d", v2i64, GPR64, i64,
6282 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6285 def : NeonInstAlias<"mov $Rd.b[$Imm], $Rn",
6286 (INSbw VPR128:$Rd, GPR32:$Rn, neon_uimm4_bare:$Imm), 0>;
6287 def : NeonInstAlias<"mov $Rd.h[$Imm], $Rn",
6288 (INShw VPR128:$Rd, GPR32:$Rn, neon_uimm3_bare:$Imm), 0>;
6289 def : NeonInstAlias<"mov $Rd.s[$Imm], $Rn",
6290 (INSsw VPR128:$Rd, GPR32:$Rn, neon_uimm2_bare:$Imm), 0>;
6291 def : NeonInstAlias<"mov $Rd.d[$Imm], $Rn",
6292 (INSdx VPR128:$Rd, GPR64:$Rn, neon_uimm1_bare:$Imm), 0>;
6294 class Neon_INS_main_pattern <ValueType ResTy,ValueType ExtResTy,
6295 RegisterClass OpGPR, ValueType OpTy,
6296 Operand OpImm, Instruction INS>
6297 : Pat<(ResTy (vector_insert
6301 (ResTy (EXTRACT_SUBREG
6302 (ExtResTy (INS (ExtResTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
6303 OpGPR:$Rn, OpImm:$Imm)), sub_64))>;
6305 def INSbw_pattern : Neon_INS_main_pattern<v8i8, v16i8, GPR32, i32,
6306 neon_uimm3_bare, INSbw>;
6307 def INShw_pattern : Neon_INS_main_pattern<v4i16, v8i16, GPR32, i32,
6308 neon_uimm2_bare, INShw>;
6309 def INSsw_pattern : Neon_INS_main_pattern<v2i32, v4i32, GPR32, i32,
6310 neon_uimm1_bare, INSsw>;
6311 def INSdx_pattern : Neon_INS_main_pattern<v1i64, v2i64, GPR64, i64,
6312 neon_uimm0_bare, INSdx>;
6314 class NeonI_INS_element<string asmop, string Res, Operand ResImm>
6315 : NeonI_insert<0b1, 0b1,
6316 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn,
6317 ResImm:$Immd, ResImm:$Immn),
6318 asmop # "\t$Rd." # Res # "[$Immd], $Rn." # Res # "[$Immn]",
6321 let Constraints = "$src = $Rd";
6326 //Insert element (vector, from element)
6327 def INSELb : NeonI_INS_element<"ins", "b", neon_uimm4_bare> {
6328 let Inst{20-16} = {Immd{3}, Immd{2}, Immd{1}, Immd{0}, 0b1};
6329 let Inst{14-11} = {Immn{3}, Immn{2}, Immn{1}, Immn{0}};
6331 def INSELh : NeonI_INS_element<"ins", "h", neon_uimm3_bare> {
6332 let Inst{20-16} = {Immd{2}, Immd{1}, Immd{0}, 0b1, 0b0};
6333 let Inst{14-11} = {Immn{2}, Immn{1}, Immn{0}, 0b0};
6334 // bit 11 is unspecified, but should be set to zero.
6336 def INSELs : NeonI_INS_element<"ins", "s", neon_uimm2_bare> {
6337 let Inst{20-16} = {Immd{1}, Immd{0}, 0b1, 0b0, 0b0};
6338 let Inst{14-11} = {Immn{1}, Immn{0}, 0b0, 0b0};
6339 // bits 11-12 are unspecified, but should be set to zero.
6341 def INSELd : NeonI_INS_element<"ins", "d", neon_uimm1_bare> {
6342 let Inst{20-16} = {Immd, 0b1, 0b0, 0b0, 0b0};
6343 let Inst{14-11} = {Immn{0}, 0b0, 0b0, 0b0};
6344 // bits 11-13 are unspecified, but should be set to zero.
6347 def : NeonInstAlias<"mov $Rd.b[$Immd], $Rn.b[$Immn]",
6348 (INSELb VPR128:$Rd, VPR128:$Rn,
6349 neon_uimm4_bare:$Immd, neon_uimm4_bare:$Immn), 0>;
6350 def : NeonInstAlias<"mov $Rd.h[$Immd], $Rn.h[$Immn]",
6351 (INSELh VPR128:$Rd, VPR128:$Rn,
6352 neon_uimm3_bare:$Immd, neon_uimm3_bare:$Immn), 0>;
6353 def : NeonInstAlias<"mov $Rd.s[$Immd], $Rn.s[$Immn]",
6354 (INSELs VPR128:$Rd, VPR128:$Rn,
6355 neon_uimm2_bare:$Immd, neon_uimm2_bare:$Immn), 0>;
6356 def : NeonInstAlias<"mov $Rd.d[$Immd], $Rn.d[$Immn]",
6357 (INSELd VPR128:$Rd, VPR128:$Rn,
6358 neon_uimm1_bare:$Immd, neon_uimm1_bare:$Immn), 0>;
6360 multiclass Neon_INS_elt_pattern<ValueType ResTy, ValueType NaTy,
6361 ValueType MidTy, Operand StImm, Operand NaImm,
6363 def : Pat<(ResTy (vector_insert
6364 (ResTy VPR128:$src),
6365 (MidTy (vector_extract
6369 (INS (ResTy VPR128:$src), (ResTy VPR128:$Rn),
6370 StImm:$Immd, StImm:$Immn)>;
6372 def : Pat <(ResTy (vector_insert
6373 (ResTy VPR128:$src),
6374 (MidTy (vector_extract
6378 (INS (ResTy VPR128:$src),
6379 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6380 StImm:$Immd, NaImm:$Immn)>;
6382 def : Pat <(NaTy (vector_insert
6384 (MidTy (vector_extract
6388 (NaTy (EXTRACT_SUBREG
6390 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6392 NaImm:$Immd, StImm:$Immn)),
6395 def : Pat <(NaTy (vector_insert
6397 (MidTy (vector_extract
6401 (NaTy (EXTRACT_SUBREG
6403 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6404 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6405 NaImm:$Immd, NaImm:$Immn)),
6409 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, neon_uimm2_bare,
6410 neon_uimm1_bare, INSELs>;
6411 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, neon_uimm1_bare,
6412 neon_uimm0_bare, INSELd>;
6413 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6414 neon_uimm3_bare, INSELb>;
6415 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6416 neon_uimm2_bare, INSELh>;
6417 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6418 neon_uimm1_bare, INSELs>;
6419 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, neon_uimm1_bare,
6420 neon_uimm0_bare, INSELd>;
6422 multiclass Neon_INS_elt_float_pattern<ValueType ResTy, ValueType NaTy,
6424 RegisterClass OpFPR, Operand ResImm,
6425 SubRegIndex SubIndex, Instruction INS> {
6426 def : Pat <(ResTy (vector_insert
6427 (ResTy VPR128:$src),
6430 (INS (ResTy VPR128:$src),
6431 (ResTy (SUBREG_TO_REG (i64 0), OpFPR:$Rn, SubIndex)),
6435 def : Pat <(NaTy (vector_insert
6439 (NaTy (EXTRACT_SUBREG
6441 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6442 (ResTy (SUBREG_TO_REG (i64 0), (MidTy OpFPR:$Rn), SubIndex)),
6448 defm : Neon_INS_elt_float_pattern<v4f32, v2f32, f32, FPR32, neon_uimm2_bare,
6450 defm : Neon_INS_elt_float_pattern<v2f64, v1f64, f64, FPR64, neon_uimm1_bare,
6453 class NeonI_SMOV<string asmop, string Res, bit Q,
6454 ValueType OpTy, ValueType eleTy,
6455 Operand OpImm, RegisterClass ResGPR, ValueType ResTy>
6456 : NeonI_copy<Q, 0b0, 0b0101,
6457 (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6458 asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6459 [(set (ResTy ResGPR:$Rd),
6461 (ResTy (vector_extract
6462 (OpTy VPR128:$Rn), (OpImm:$Imm))),
6468 //Signed integer move (main, from element)
6469 def SMOVwb : NeonI_SMOV<"smov", "b", 0b0, v16i8, i8, neon_uimm4_bare,
6471 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6473 def SMOVwh : NeonI_SMOV<"smov", "h", 0b0, v8i16, i16, neon_uimm3_bare,
6475 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6477 def SMOVxb : NeonI_SMOV<"smov", "b", 0b1, v16i8, i8, neon_uimm4_bare,
6479 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6481 def SMOVxh : NeonI_SMOV<"smov", "h", 0b1, v8i16, i16, neon_uimm3_bare,
6483 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6485 def SMOVxs : NeonI_SMOV<"smov", "s", 0b1, v4i32, i32, neon_uimm2_bare,
6487 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6490 multiclass Neon_SMOVx_pattern <ValueType StTy, ValueType NaTy,
6491 ValueType eleTy, Operand StImm, Operand NaImm,
6492 Instruction SMOVI> {
6493 def : Pat<(i64 (sext_inreg
6495 (i32 (vector_extract
6496 (StTy VPR128:$Rn), (StImm:$Imm))))),
6498 (SMOVI VPR128:$Rn, StImm:$Imm)>;
6500 def : Pat<(i64 (sext
6501 (i32 (vector_extract
6502 (StTy VPR128:$Rn), (StImm:$Imm))))),
6503 (SMOVI VPR128:$Rn, StImm:$Imm)>;
6505 def : Pat<(i64 (sext_inreg
6506 (i64 (vector_extract
6507 (NaTy VPR64:$Rn), (NaImm:$Imm))),
6509 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6512 def : Pat<(i64 (sext_inreg
6514 (i32 (vector_extract
6515 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6517 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6520 def : Pat<(i64 (sext
6521 (i32 (vector_extract
6522 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6523 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6527 defm : Neon_SMOVx_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6528 neon_uimm3_bare, SMOVxb>;
6529 defm : Neon_SMOVx_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6530 neon_uimm2_bare, SMOVxh>;
6531 defm : Neon_SMOVx_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6532 neon_uimm1_bare, SMOVxs>;
6534 class Neon_SMOVw_pattern <ValueType StTy, ValueType NaTy,
6535 ValueType eleTy, Operand StImm, Operand NaImm,
6537 : Pat<(i32 (sext_inreg
6538 (i32 (vector_extract
6539 (NaTy VPR64:$Rn), (NaImm:$Imm))),
6541 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6544 def : Neon_SMOVw_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6545 neon_uimm3_bare, SMOVwb>;
6546 def : Neon_SMOVw_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6547 neon_uimm2_bare, SMOVwh>;
6549 class NeonI_UMOV<string asmop, string Res, bit Q,
6550 ValueType OpTy, Operand OpImm,
6551 RegisterClass ResGPR, ValueType ResTy>
6552 : NeonI_copy<Q, 0b0, 0b0111,
6553 (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6554 asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6555 [(set (ResTy ResGPR:$Rd),
6556 (ResTy (vector_extract
6557 (OpTy VPR128:$Rn), (OpImm:$Imm))))],
6562 //Unsigned integer move (main, from element)
6563 def UMOVwb : NeonI_UMOV<"umov", "b", 0b0, v16i8, neon_uimm4_bare,
6565 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6567 def UMOVwh : NeonI_UMOV<"umov", "h", 0b0, v8i16, neon_uimm3_bare,
6569 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6571 def UMOVws : NeonI_UMOV<"umov", "s", 0b0, v4i32, neon_uimm2_bare,
6573 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6575 def UMOVxd : NeonI_UMOV<"umov", "d", 0b1, v2i64, neon_uimm1_bare,
6577 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6580 def : NeonInstAlias<"mov $Rd, $Rn.s[$Imm]",
6581 (UMOVws GPR32:$Rd, VPR128:$Rn, neon_uimm2_bare:$Imm), 0>;
6582 def : NeonInstAlias<"mov $Rd, $Rn.d[$Imm]",
6583 (UMOVxd GPR64:$Rd, VPR128:$Rn, neon_uimm1_bare:$Imm), 0>;
6585 class Neon_UMOV_pattern <ValueType StTy, ValueType NaTy, ValueType ResTy,
6586 Operand StImm, Operand NaImm,
6588 : Pat<(ResTy (vector_extract
6589 (NaTy VPR64:$Rn), NaImm:$Imm)),
6590 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6593 def : Neon_UMOV_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6594 neon_uimm3_bare, UMOVwb>;
6595 def : Neon_UMOV_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6596 neon_uimm2_bare, UMOVwh>;
6597 def : Neon_UMOV_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6598 neon_uimm1_bare, UMOVws>;
6601 (i32 (vector_extract
6602 (v16i8 VPR128:$Rn), (neon_uimm4_bare:$Imm))),
6604 (UMOVwb VPR128:$Rn, neon_uimm4_bare:$Imm)>;
6607 (i32 (vector_extract
6608 (v8i16 VPR128:$Rn), (neon_uimm3_bare:$Imm))),
6610 (UMOVwh VPR128:$Rn, neon_uimm3_bare:$Imm)>;
6612 def : Pat<(i64 (zext
6613 (i32 (vector_extract
6614 (v2i64 VPR128:$Rn), (neon_uimm1_bare:$Imm))))),
6615 (UMOVxd VPR128:$Rn, neon_uimm1_bare:$Imm)>;
6618 (i32 (vector_extract
6619 (v8i8 VPR64:$Rn), (neon_uimm3_bare:$Imm))),
6621 (UMOVwb (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6622 neon_uimm3_bare:$Imm)>;
6625 (i32 (vector_extract
6626 (v4i16 VPR64:$Rn), (neon_uimm2_bare:$Imm))),
6628 (UMOVwh (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6629 neon_uimm2_bare:$Imm)>;
6631 def : Pat<(i64 (zext
6632 (i32 (vector_extract
6633 (v1i64 VPR64:$Rn), (neon_uimm0_bare:$Imm))))),
6634 (UMOVxd (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6635 neon_uimm0_bare:$Imm)>;
6637 // Additional copy patterns for scalar types
6638 def : Pat<(i32 (vector_extract (v1i8 FPR8:$Rn), (i64 0))),
6640 (SUBREG_TO_REG (i64 0), FPR8:$Rn, sub_8)), (i64 0))>;
6642 def : Pat<(i32 (vector_extract (v1i16 FPR16:$Rn), (i64 0))),
6644 (SUBREG_TO_REG (i64 0), FPR16:$Rn, sub_16)), (i64 0))>;
6646 def : Pat<(i32 (vector_extract (v1i32 FPR32:$Rn), (i64 0))),
6647 (FMOVws FPR32:$Rn)>;
6649 def : Pat<(i64 (vector_extract (v1i64 FPR64:$Rn), (i64 0))),
6650 (FMOVxd FPR64:$Rn)>;
6652 def : Pat<(f64 (vector_extract (v1f64 FPR64:$Rn), (i64 0))),
6655 def : Pat<(f32 (vector_extract (v1f32 FPR32:$Rn), (i64 0))),
6658 def : Pat<(v1i8 (scalar_to_vector GPR32:$Rn)),
6659 (v1i8 (EXTRACT_SUBREG (v16i8
6660 (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
6663 def : Pat<(v1i16 (scalar_to_vector GPR32:$Rn)),
6664 (v1i16 (EXTRACT_SUBREG (v8i16
6665 (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
6668 def : Pat<(v1i32 (scalar_to_vector GPR32:$src)),
6671 def : Pat<(v1i64 (scalar_to_vector GPR64:$src)),
6674 def : Pat<(v1f32 (scalar_to_vector (f32 FPR32:$Rn))),
6676 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
6679 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
6682 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$src))),
6683 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
6684 (f64 FPR64:$src), sub_64)>;
6686 class NeonI_DUP_Elt<bit Q, string asmop, string rdlane, string rnlane,
6687 RegisterOperand ResVPR, Operand OpImm>
6688 : NeonI_copy<Q, 0b0, 0b0000, (outs ResVPR:$Rd),
6689 (ins VPR128:$Rn, OpImm:$Imm),
6690 asmop # "\t$Rd" # rdlane # ", $Rn" # rnlane # "[$Imm]",
6696 def DUPELT16b : NeonI_DUP_Elt<0b1, "dup", ".16b", ".b", VPR128,
6698 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6701 def DUPELT8h : NeonI_DUP_Elt<0b1, "dup", ".8h", ".h", VPR128,
6703 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6706 def DUPELT4s : NeonI_DUP_Elt<0b1, "dup", ".4s", ".s", VPR128,
6708 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6711 def DUPELT2d : NeonI_DUP_Elt<0b1, "dup", ".2d", ".d", VPR128,
6713 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6716 def DUPELT8b : NeonI_DUP_Elt<0b0, "dup", ".8b", ".b", VPR64,
6718 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6721 def DUPELT4h : NeonI_DUP_Elt<0b0, "dup", ".4h", ".h", VPR64,
6723 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6726 def DUPELT2s : NeonI_DUP_Elt<0b0, "dup", ".2s", ".s", VPR64,
6728 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6731 multiclass NeonI_DUP_Elt_pattern<Instruction DUPELT, ValueType ResTy,
6732 ValueType OpTy,ValueType NaTy,
6733 ValueType ExTy, Operand OpLImm,
6735 def : Pat<(ResTy (Neon_vduplane (OpTy VPR128:$Rn), OpLImm:$Imm)),
6736 (ResTy (DUPELT (OpTy VPR128:$Rn), OpLImm:$Imm))>;
6738 def : Pat<(ResTy (Neon_vduplane
6739 (NaTy VPR64:$Rn), OpNImm:$Imm)),
6741 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)), OpNImm:$Imm))>;
6743 defm : NeonI_DUP_Elt_pattern<DUPELT16b, v16i8, v16i8, v8i8, v16i8,
6744 neon_uimm4_bare, neon_uimm3_bare>;
6745 defm : NeonI_DUP_Elt_pattern<DUPELT8b, v8i8, v16i8, v8i8, v16i8,
6746 neon_uimm4_bare, neon_uimm3_bare>;
6747 defm : NeonI_DUP_Elt_pattern<DUPELT8h, v8i16, v8i16, v4i16, v8i16,
6748 neon_uimm3_bare, neon_uimm2_bare>;
6749 defm : NeonI_DUP_Elt_pattern<DUPELT4h, v4i16, v8i16, v4i16, v8i16,
6750 neon_uimm3_bare, neon_uimm2_bare>;
6751 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4i32, v4i32, v2i32, v4i32,
6752 neon_uimm2_bare, neon_uimm1_bare>;
6753 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2i32, v4i32, v2i32, v4i32,
6754 neon_uimm2_bare, neon_uimm1_bare>;
6755 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2i64, v2i64, v1i64, v2i64,
6756 neon_uimm1_bare, neon_uimm0_bare>;
6757 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4f32, v4f32, v2f32, v4f32,
6758 neon_uimm2_bare, neon_uimm1_bare>;
6759 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2f32, v4f32, v2f32, v4f32,
6760 neon_uimm2_bare, neon_uimm1_bare>;
6761 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2f64, v2f64, v1f64, v2f64,
6762 neon_uimm1_bare, neon_uimm0_bare>;
6764 def : Pat<(v2f32 (Neon_vdup (f32 FPR32:$Rn))),
6766 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
6768 def : Pat<(v4f32 (Neon_vdup (f32 FPR32:$Rn))),
6770 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
6772 def : Pat<(v2f64 (Neon_vdup (f64 FPR64:$Rn))),
6774 (SUBREG_TO_REG (i64 0), FPR64:$Rn, sub_64),
6777 class NeonI_DUP<bit Q, string asmop, string rdlane,
6778 RegisterOperand ResVPR, ValueType ResTy,
6779 RegisterClass OpGPR, ValueType OpTy>
6780 : NeonI_copy<Q, 0b0, 0b0001, (outs ResVPR:$Rd), (ins OpGPR:$Rn),
6781 asmop # "\t$Rd" # rdlane # ", $Rn",
6782 [(set (ResTy ResVPR:$Rd),
6783 (ResTy (Neon_vdup (OpTy OpGPR:$Rn))))],
6786 def DUP16b : NeonI_DUP<0b1, "dup", ".16b", VPR128, v16i8, GPR32, i32> {
6787 let Inst{20-16} = 0b00001;
6788 // bits 17-20 are unspecified, but should be set to zero.
6791 def DUP8h : NeonI_DUP<0b1, "dup", ".8h", VPR128, v8i16, GPR32, i32> {
6792 let Inst{20-16} = 0b00010;
6793 // bits 18-20 are unspecified, but should be set to zero.
6796 def DUP4s : NeonI_DUP<0b1, "dup", ".4s", VPR128, v4i32, GPR32, i32> {
6797 let Inst{20-16} = 0b00100;
6798 // bits 19-20 are unspecified, but should be set to zero.
6801 def DUP2d : NeonI_DUP<0b1, "dup", ".2d", VPR128, v2i64, GPR64, i64> {
6802 let Inst{20-16} = 0b01000;
6803 // bit 20 is unspecified, but should be set to zero.
6806 def DUP8b : NeonI_DUP<0b0, "dup", ".8b", VPR64, v8i8, GPR32, i32> {
6807 let Inst{20-16} = 0b00001;
6808 // bits 17-20 are unspecified, but should be set to zero.
6811 def DUP4h : NeonI_DUP<0b0, "dup", ".4h", VPR64, v4i16, GPR32, i32> {
6812 let Inst{20-16} = 0b00010;
6813 // bits 18-20 are unspecified, but should be set to zero.
6816 def DUP2s : NeonI_DUP<0b0, "dup", ".2s", VPR64, v2i32, GPR32, i32> {
6817 let Inst{20-16} = 0b00100;
6818 // bits 19-20 are unspecified, but should be set to zero.
6821 // patterns for CONCAT_VECTORS
6822 multiclass Concat_Vector_Pattern<ValueType ResTy, ValueType OpTy> {
6823 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), undef)),
6824 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)>;
6825 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))),
6827 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6828 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rm, sub_64)),
6831 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rn))),
6833 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6837 defm : Concat_Vector_Pattern<v16i8, v8i8>;
6838 defm : Concat_Vector_Pattern<v8i16, v4i16>;
6839 defm : Concat_Vector_Pattern<v4i32, v2i32>;
6840 defm : Concat_Vector_Pattern<v2i64, v1i64>;
6841 defm : Concat_Vector_Pattern<v4f32, v2f32>;
6842 defm : Concat_Vector_Pattern<v2f64, v1f64>;
6844 //patterns for EXTRACT_SUBVECTOR
6845 def : Pat<(v8i8 (extract_subvector (v16i8 VPR128:$Rn), (i64 0))),
6846 (v8i8 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6847 def : Pat<(v4i16 (extract_subvector (v8i16 VPR128:$Rn), (i64 0))),
6848 (v4i16 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6849 def : Pat<(v2i32 (extract_subvector (v4i32 VPR128:$Rn), (i64 0))),
6850 (v2i32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6851 def : Pat<(v1i64 (extract_subvector (v2i64 VPR128:$Rn), (i64 0))),
6852 (v1i64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6853 def : Pat<(v2f32 (extract_subvector (v4f32 VPR128:$Rn), (i64 0))),
6854 (v2f32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6855 def : Pat<(v1f64 (extract_subvector (v2f64 VPR128:$Rn), (i64 0))),
6856 (v1f64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6858 // The followings are for instruction class (3V Elem)
6862 class NI_2VE<bit q, bit u, bits<2> size, bits<4> opcode,
6863 string asmop, string ResS, string OpS, string EleOpS,
6864 Operand OpImm, RegisterOperand ResVPR,
6865 RegisterOperand OpVPR, RegisterOperand EleOpVPR>
6866 : NeonI_2VElem<q, u, size, opcode,
6867 (outs ResVPR:$Rd), (ins ResVPR:$src, OpVPR:$Rn,
6868 EleOpVPR:$Re, OpImm:$Index),
6869 asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
6870 ", $Re." # EleOpS # "[$Index]",
6876 let Constraints = "$src = $Rd";
6879 multiclass NI_2VE_v1<bit u, bits<4> opcode, string asmop> {
6880 // vector register class for element is always 128-bit to cover the max index
6881 def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6882 neon_uimm2_bare, VPR64, VPR64, VPR128> {
6883 let Inst{11} = {Index{1}};
6884 let Inst{21} = {Index{0}};
6885 let Inst{20-16} = Re;
6888 def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6889 neon_uimm2_bare, VPR128, VPR128, VPR128> {
6890 let Inst{11} = {Index{1}};
6891 let Inst{21} = {Index{0}};
6892 let Inst{20-16} = Re;
6895 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6896 def _4h8h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
6897 neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
6898 let Inst{11} = {Index{2}};
6899 let Inst{21} = {Index{1}};
6900 let Inst{20} = {Index{0}};
6901 let Inst{19-16} = Re{3-0};
6904 def _8h8h : NI_2VE<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
6905 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
6906 let Inst{11} = {Index{2}};
6907 let Inst{21} = {Index{1}};
6908 let Inst{20} = {Index{0}};
6909 let Inst{19-16} = Re{3-0};
6913 defm MLAvve : NI_2VE_v1<0b1, 0b0000, "mla">;
6914 defm MLSvve : NI_2VE_v1<0b1, 0b0100, "mls">;
6916 // Pattern for lane in 128-bit vector
6917 class NI_2VE_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6918 RegisterOperand ResVPR, RegisterOperand OpVPR,
6919 RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
6921 : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
6922 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6923 (INST ResVPR:$src, OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
6925 // Pattern for lane in 64-bit vector
6926 class NI_2VE_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6927 RegisterOperand ResVPR, RegisterOperand OpVPR,
6928 RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
6930 : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
6931 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6932 (INST ResVPR:$src, OpVPR:$Rn,
6933 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
6935 multiclass NI_2VE_v1_pat<string subop, SDPatternOperator op>
6937 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
6938 op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32>;
6940 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
6941 op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32>;
6943 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
6944 op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
6946 def : NI_2VE_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
6947 op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
6949 // Index can only be half of the max value for lane in 64-bit vector
6951 def : NI_2VE_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
6952 op, VPR64, VPR64, VPR64, v2i32, v2i32, v2i32>;
6954 def : NI_2VE_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
6955 op, VPR64, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
6958 defm MLA_lane_v1 : NI_2VE_v1_pat<"MLAvve", Neon_mla>;
6959 defm MLS_lane_v1 : NI_2VE_v1_pat<"MLSvve", Neon_mls>;
6961 class NI_2VE_2op<bit q, bit u, bits<2> size, bits<4> opcode,
6962 string asmop, string ResS, string OpS, string EleOpS,
6963 Operand OpImm, RegisterOperand ResVPR,
6964 RegisterOperand OpVPR, RegisterOperand EleOpVPR>
6965 : NeonI_2VElem<q, u, size, opcode,
6966 (outs ResVPR:$Rd), (ins OpVPR:$Rn,
6967 EleOpVPR:$Re, OpImm:$Index),
6968 asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
6969 ", $Re." # EleOpS # "[$Index]",
6976 multiclass NI_2VE_v1_2op<bit u, bits<4> opcode, string asmop> {
6977 // vector register class for element is always 128-bit to cover the max index
6978 def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6979 neon_uimm2_bare, VPR64, VPR64, VPR128> {
6980 let Inst{11} = {Index{1}};
6981 let Inst{21} = {Index{0}};
6982 let Inst{20-16} = Re;
6985 def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6986 neon_uimm2_bare, VPR128, VPR128, VPR128> {
6987 let Inst{11} = {Index{1}};
6988 let Inst{21} = {Index{0}};
6989 let Inst{20-16} = Re;
6992 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6993 def _4h8h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
6994 neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
6995 let Inst{11} = {Index{2}};
6996 let Inst{21} = {Index{1}};
6997 let Inst{20} = {Index{0}};
6998 let Inst{19-16} = Re{3-0};
7001 def _8h8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
7002 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7003 let Inst{11} = {Index{2}};
7004 let Inst{21} = {Index{1}};
7005 let Inst{20} = {Index{0}};
7006 let Inst{19-16} = Re{3-0};
7010 defm MULve : NI_2VE_v1_2op<0b0, 0b1000, "mul">;
7011 defm SQDMULHve : NI_2VE_v1_2op<0b0, 0b1100, "sqdmulh">;
7012 defm SQRDMULHve : NI_2VE_v1_2op<0b0, 0b1101, "sqrdmulh">;
7014 // Pattern for lane in 128-bit vector
7015 class NI_2VE_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7016 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7017 ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7018 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7019 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7020 (INST OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7022 // Pattern for lane in 64-bit vector
7023 class NI_2VE_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7024 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7025 ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7026 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7027 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7029 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7031 multiclass NI_2VE_mul_v1_pat<string subop, SDPatternOperator op> {
7032 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7033 op, VPR64, VPR128, v2i32, v2i32, v4i32>;
7035 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7036 op, VPR128, VPR128, v4i32, v4i32, v4i32>;
7038 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
7039 op, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
7041 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
7042 op, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
7044 // Index can only be half of the max value for lane in 64-bit vector
7046 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7047 op, VPR64, VPR64, v2i32, v2i32, v2i32>;
7049 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
7050 op, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
7053 defm MUL_lane_v1 : NI_2VE_mul_v1_pat<"MULve", mul>;
7054 defm SQDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQDMULHve", int_arm_neon_vqdmulh>;
7055 defm SQRDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQRDMULHve", int_arm_neon_vqrdmulh>;
7059 multiclass NI_2VE_v2_2op<bit u, bits<4> opcode, string asmop> {
7060 // vector register class for element is always 128-bit to cover the max index
7061 def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7062 neon_uimm2_bare, VPR64, VPR64, VPR128> {
7063 let Inst{11} = {Index{1}};
7064 let Inst{21} = {Index{0}};
7065 let Inst{20-16} = Re;
7068 def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7069 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7070 let Inst{11} = {Index{1}};
7071 let Inst{21} = {Index{0}};
7072 let Inst{20-16} = Re;
7075 // _1d2d doesn't exist!
7077 def _2d2d : NI_2VE_2op<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7078 neon_uimm1_bare, VPR128, VPR128, VPR128> {
7079 let Inst{11} = {Index{0}};
7081 let Inst{20-16} = Re;
7085 defm FMULve : NI_2VE_v2_2op<0b0, 0b1001, "fmul">;
7086 defm FMULXve : NI_2VE_v2_2op<0b1, 0b1001, "fmulx">;
7088 class NI_2VE_mul_lane_2d<Instruction INST, Operand OpImm, SDPatternOperator op,
7089 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7090 ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
7091 SDPatternOperator coreop>
7092 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7093 (OpTy (coreop (EleOpTy EleOpVPR:$Re), (EleOpTy EleOpVPR:$Re))))),
7095 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), 0)>;
7097 multiclass NI_2VE_mul_v2_pat<string subop, SDPatternOperator op> {
7098 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7099 op, VPR64, VPR128, v2f32, v2f32, v4f32>;
7101 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7102 op, VPR128, VPR128, v4f32, v4f32, v4f32>;
7104 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7105 op, VPR128, VPR128, v2f64, v2f64, v2f64>;
7107 // Index can only be half of the max value for lane in 64-bit vector
7109 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7110 op, VPR64, VPR64, v2f32, v2f32, v2f32>;
7112 def : NI_2VE_mul_lane_2d<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7113 op, VPR128, VPR64, v2f64, v2f64, v1f64,
7114 BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7117 defm FMUL_lane_v2 : NI_2VE_mul_v2_pat<"FMULve", fmul>;
7118 defm FMULX_lane_v2 : NI_2VE_mul_v2_pat<"FMULXve", int_aarch64_neon_vmulx>;
7120 def : Pat<(v2f32 (fmul (v2f32 (Neon_vdup (f32 FPR32:$Re))),
7121 (v2f32 VPR64:$Rn))),
7122 (FMULve_2s4s VPR64:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7124 def : Pat<(v4f32 (fmul (v4f32 (Neon_vdup (f32 FPR32:$Re))),
7125 (v4f32 VPR128:$Rn))),
7126 (FMULve_4s4s VPR128:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7128 def : Pat<(v2f64 (fmul (v2f64 (Neon_vdup (f64 FPR64:$Re))),
7129 (v2f64 VPR128:$Rn))),
7130 (FMULve_2d2d VPR128:$Rn, (SUBREG_TO_REG (i64 0), $Re, sub_64), 0)>;
7132 // The followings are patterns using fma
7133 // -ffp-contract=fast generates fma
7135 multiclass NI_2VE_v2<bit u, bits<4> opcode, string asmop> {
7136 // vector register class for element is always 128-bit to cover the max index
7137 def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7138 neon_uimm2_bare, VPR64, VPR64, VPR128> {
7139 let Inst{11} = {Index{1}};
7140 let Inst{21} = {Index{0}};
7141 let Inst{20-16} = Re;
7144 def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7145 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7146 let Inst{11} = {Index{1}};
7147 let Inst{21} = {Index{0}};
7148 let Inst{20-16} = Re;
7151 // _1d2d doesn't exist!
7153 def _2d2d : NI_2VE<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7154 neon_uimm1_bare, VPR128, VPR128, VPR128> {
7155 let Inst{11} = {Index{0}};
7157 let Inst{20-16} = Re;
7161 defm FMLAvve : NI_2VE_v2<0b0, 0b0001, "fmla">;
7162 defm FMLSvve : NI_2VE_v2<0b0, 0b0101, "fmls">;
7164 // Pattern for lane in 128-bit vector
7165 class NI_2VEswap_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7166 RegisterOperand ResVPR, RegisterOperand OpVPR,
7167 ValueType ResTy, ValueType OpTy,
7168 SDPatternOperator coreop>
7169 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7170 (ResTy ResVPR:$src), (ResTy ResVPR:$Rn))),
7171 (INST ResVPR:$src, ResVPR:$Rn, OpVPR:$Re, OpImm:$Index)>;
7173 // Pattern for lane 0
7174 class NI_2VEfma_lane0<Instruction INST, SDPatternOperator op,
7175 RegisterOperand ResVPR, ValueType ResTy>
7176 : Pat<(ResTy (op (ResTy ResVPR:$Rn),
7177 (ResTy (Neon_vdup (f32 FPR32:$Re))),
7178 (ResTy ResVPR:$src))),
7179 (INST ResVPR:$src, ResVPR:$Rn,
7180 (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7182 // Pattern for lane in 64-bit vector
7183 class NI_2VEswap_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7184 RegisterOperand ResVPR, RegisterOperand OpVPR,
7185 ValueType ResTy, ValueType OpTy,
7186 SDPatternOperator coreop>
7187 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7188 (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7189 (INST ResVPR:$src, ResVPR:$Rn,
7190 (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), OpImm:$Index)>;
7192 // Pattern for lane in 64-bit vector
7193 class NI_2VEswap_lane_2d2d<Instruction INST, Operand OpImm,
7194 SDPatternOperator op,
7195 RegisterOperand ResVPR, RegisterOperand OpVPR,
7196 ValueType ResTy, ValueType OpTy,
7197 SDPatternOperator coreop>
7198 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (OpTy OpVPR:$Re))),
7199 (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7200 (INST ResVPR:$src, ResVPR:$Rn,
7201 (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), 0)>;
7204 multiclass NI_2VE_fma_v2_pat<string subop, SDPatternOperator op> {
7205 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7206 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7207 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7209 def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_2s4s"),
7212 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7213 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7214 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7216 def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_4s4s"),
7219 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7220 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7221 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7223 // Index can only be half of the max value for lane in 64-bit vector
7225 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7226 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7227 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7229 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7230 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7231 BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7234 defm FMLA_lane_v2_s : NI_2VE_fma_v2_pat<"FMLAvve", fma>;
7236 // Pattern for lane 0
7237 class NI_2VEfms_lane0<Instruction INST, SDPatternOperator op,
7238 RegisterOperand ResVPR, ValueType ResTy>
7239 : Pat<(ResTy (op (ResTy (fneg ResVPR:$Rn)),
7240 (ResTy (Neon_vdup (f32 FPR32:$Re))),
7241 (ResTy ResVPR:$src))),
7242 (INST ResVPR:$src, ResVPR:$Rn,
7243 (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7245 multiclass NI_2VE_fms_v2_pat<string subop, SDPatternOperator op>
7247 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7248 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7249 BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7251 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7252 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7253 BinOpFrag<(Neon_vduplane
7254 (fneg node:$LHS), node:$RHS)>>;
7256 def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_2s4s"),
7259 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7260 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7261 BinOpFrag<(fneg (Neon_vduplane
7262 node:$LHS, node:$RHS))>>;
7264 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7265 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7266 BinOpFrag<(Neon_vduplane
7267 (fneg node:$LHS), node:$RHS)>>;
7269 def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_4s4s"),
7272 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7273 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7274 BinOpFrag<(fneg (Neon_vduplane
7275 node:$LHS, node:$RHS))>>;
7277 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7278 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7279 BinOpFrag<(Neon_vduplane
7280 (fneg node:$LHS), node:$RHS)>>;
7282 // Index can only be half of the max value for lane in 64-bit vector
7284 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7285 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7286 BinOpFrag<(fneg (Neon_vduplane
7287 node:$LHS, node:$RHS))>>;
7289 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7290 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7291 BinOpFrag<(Neon_vduplane
7292 (fneg node:$LHS), node:$RHS)>>;
7294 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7295 neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7296 BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7298 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7299 neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7300 BinOpFrag<(Neon_vduplane (fneg node:$LHS), node:$RHS)>>;
7302 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7303 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7304 BinOpFrag<(fneg (Neon_combine_2d
7305 node:$LHS, node:$RHS))>>;
7307 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7308 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7309 BinOpFrag<(Neon_combine_2d
7310 (fneg node:$LHS), (fneg node:$RHS))>>;
7313 defm FMLS_lane_v2_s : NI_2VE_fms_v2_pat<"FMLSvve", fma>;
7315 // Variant 3: Long type
7316 // E.g. SMLAL : 4S/4H/H (v0-v15), 2D/2S/S
7317 // SMLAL2: 4S/8H/H (v0-v15), 2D/4S/S
7319 multiclass NI_2VE_v3<bit u, bits<4> opcode, string asmop> {
7320 // vector register class for element is always 128-bit to cover the max index
7321 def _2d2s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7322 neon_uimm2_bare, VPR128, VPR64, VPR128> {
7323 let Inst{11} = {Index{1}};
7324 let Inst{21} = {Index{0}};
7325 let Inst{20-16} = Re;
7328 def _2d4s : NI_2VE<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7329 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7330 let Inst{11} = {Index{1}};
7331 let Inst{21} = {Index{0}};
7332 let Inst{20-16} = Re;
7335 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7336 def _4s8h : NI_2VE<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7337 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7338 let Inst{11} = {Index{2}};
7339 let Inst{21} = {Index{1}};
7340 let Inst{20} = {Index{0}};
7341 let Inst{19-16} = Re{3-0};
7344 def _4s4h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7345 neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7346 let Inst{11} = {Index{2}};
7347 let Inst{21} = {Index{1}};
7348 let Inst{20} = {Index{0}};
7349 let Inst{19-16} = Re{3-0};
7353 defm SMLALvve : NI_2VE_v3<0b0, 0b0010, "smlal">;
7354 defm UMLALvve : NI_2VE_v3<0b1, 0b0010, "umlal">;
7355 defm SMLSLvve : NI_2VE_v3<0b0, 0b0110, "smlsl">;
7356 defm UMLSLvve : NI_2VE_v3<0b1, 0b0110, "umlsl">;
7357 defm SQDMLALvve : NI_2VE_v3<0b0, 0b0011, "sqdmlal">;
7358 defm SQDMLSLvve : NI_2VE_v3<0b0, 0b0111, "sqdmlsl">;
7360 multiclass NI_2VE_v3_2op<bit u, bits<4> opcode, string asmop> {
7361 // vector register class for element is always 128-bit to cover the max index
7362 def _2d2s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7363 neon_uimm2_bare, VPR128, VPR64, VPR128> {
7364 let Inst{11} = {Index{1}};
7365 let Inst{21} = {Index{0}};
7366 let Inst{20-16} = Re;
7369 def _2d4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7370 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7371 let Inst{11} = {Index{1}};
7372 let Inst{21} = {Index{0}};
7373 let Inst{20-16} = Re;
7376 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7377 def _4s8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7378 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7379 let Inst{11} = {Index{2}};
7380 let Inst{21} = {Index{1}};
7381 let Inst{20} = {Index{0}};
7382 let Inst{19-16} = Re{3-0};
7385 def _4s4h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7386 neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7387 let Inst{11} = {Index{2}};
7388 let Inst{21} = {Index{1}};
7389 let Inst{20} = {Index{0}};
7390 let Inst{19-16} = Re{3-0};
7394 defm SMULLve : NI_2VE_v3_2op<0b0, 0b1010, "smull">;
7395 defm UMULLve : NI_2VE_v3_2op<0b1, 0b1010, "umull">;
7396 defm SQDMULLve : NI_2VE_v3_2op<0b0, 0b1011, "sqdmull">;
7398 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
7400 def : Pat<(v1f32 (scalar_to_vector (f32 FPR32:$src))),
7403 // Pattern for lane in 128-bit vector
7404 class NI_2VEL2_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7405 RegisterOperand EleOpVPR, ValueType ResTy,
7406 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7407 SDPatternOperator hiop>
7408 : Pat<(ResTy (op (ResTy VPR128:$src),
7409 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7410 (HalfOpTy (Neon_vduplane
7411 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7412 (INST VPR128:$src, VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7414 // Pattern for lane in 64-bit vector
7415 class NI_2VEL2_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7416 RegisterOperand EleOpVPR, ValueType ResTy,
7417 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7418 SDPatternOperator hiop>
7419 : Pat<(ResTy (op (ResTy VPR128:$src),
7420 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7421 (HalfOpTy (Neon_vduplane
7422 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7423 (INST VPR128:$src, VPR128:$Rn,
7424 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7426 class NI_2VEL2_lane0<Instruction INST, SDPatternOperator op,
7427 ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7428 SDPatternOperator hiop, Instruction DupInst>
7429 : Pat<(ResTy (op (ResTy VPR128:$src),
7430 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7431 (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7432 (INST VPR128:$src, VPR128:$Rn, (DupInst $Re), 0)>;
7434 multiclass NI_2VEL_v3_pat<string subop, SDPatternOperator op> {
7435 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7436 op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7438 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7439 op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32>;
7441 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7442 op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7444 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7445 op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7447 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7448 op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7450 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7451 op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7453 // Index can only be half of the max value for lane in 64-bit vector
7455 def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7456 op, VPR128, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7458 def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7459 op, VPR128, VPR64, VPR64, v2i64, v2i32, v2i32>;
7461 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7462 op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7464 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7465 op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7468 defm SMLAL_lane_v3 : NI_2VEL_v3_pat<"SMLALvve", Neon_smlal>;
7469 defm UMLAL_lane_v3 : NI_2VEL_v3_pat<"UMLALvve", Neon_umlal>;
7470 defm SMLSL_lane_v3 : NI_2VEL_v3_pat<"SMLSLvve", Neon_smlsl>;
7471 defm UMLSL_lane_v3 : NI_2VEL_v3_pat<"UMLSLvve", Neon_umlsl>;
7473 // Pattern for lane in 128-bit vector
7474 class NI_2VEL2_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7475 RegisterOperand EleOpVPR, ValueType ResTy,
7476 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7477 SDPatternOperator hiop>
7479 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7480 (HalfOpTy (Neon_vduplane
7481 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7482 (INST VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7484 // Pattern for lane in 64-bit vector
7485 class NI_2VEL2_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7486 RegisterOperand EleOpVPR, ValueType ResTy,
7487 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7488 SDPatternOperator hiop>
7490 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7491 (HalfOpTy (Neon_vduplane
7492 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7494 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7496 // Pattern for fixed lane 0
7497 class NI_2VEL2_mul_lane0<Instruction INST, SDPatternOperator op,
7498 ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7499 SDPatternOperator hiop, Instruction DupInst>
7501 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7502 (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7503 (INST VPR128:$Rn, (DupInst $Re), 0)>;
7505 multiclass NI_2VEL_mul_v3_pat<string subop, SDPatternOperator op> {
7506 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7507 op, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7509 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7510 op, VPR64, VPR128, v2i64, v2i32, v4i32>;
7512 def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7513 op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7515 def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7516 op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7518 def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_4s8h"),
7519 op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7521 def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_2d4s"),
7522 op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7524 // Index can only be half of the max value for lane in 64-bit vector
7526 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7527 op, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7529 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7530 op, VPR64, VPR64, v2i64, v2i32, v2i32>;
7532 def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7533 op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7535 def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7536 op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7539 defm SMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SMULLve", int_arm_neon_vmulls>;
7540 defm UMULL_lane_v3 : NI_2VEL_mul_v3_pat<"UMULLve", int_arm_neon_vmullu>;
7541 defm SQDMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SQDMULLve", int_arm_neon_vqdmull>;
7543 multiclass NI_qdma<SDPatternOperator op> {
7544 def _4s : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7546 (v4i32 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7548 def _2d : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7550 (v2i64 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7553 defm Neon_qdmlal : NI_qdma<int_arm_neon_vqadds>;
7554 defm Neon_qdmlsl : NI_qdma<int_arm_neon_vqsubs>;
7556 multiclass NI_2VEL_v3_qdma_pat<string subop, string op> {
7557 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7558 !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR128Lo,
7559 v4i32, v4i16, v8i16>;
7561 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7562 !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR128,
7563 v2i64, v2i32, v4i32>;
7565 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7566 !cast<PatFrag>(op # "_4s"), VPR128Lo,
7567 v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7569 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7570 !cast<PatFrag>(op # "_2d"), VPR128,
7571 v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7573 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7574 !cast<PatFrag>(op # "_4s"),
7575 v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7577 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7578 !cast<PatFrag>(op # "_2d"),
7579 v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7581 // Index can only be half of the max value for lane in 64-bit vector
7583 def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7584 !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR64Lo,
7585 v4i32, v4i16, v4i16>;
7587 def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7588 !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR64,
7589 v2i64, v2i32, v2i32>;
7591 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7592 !cast<PatFrag>(op # "_4s"), VPR64Lo,
7593 v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7595 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7596 !cast<PatFrag>(op # "_2d"), VPR64,
7597 v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7600 defm SQDMLAL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLALvve", "Neon_qdmlal">;
7601 defm SQDMLSL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLSLvve", "Neon_qdmlsl">;
7603 // End of implementation for instruction class (3V Elem)
7605 class NeonI_REV<string asmop, string Res, bits<2> size, bit Q, bit U,
7606 bits<5> opcode, RegisterOperand ResVPR, ValueType ResTy,
7607 SDPatternOperator Neon_Rev>
7608 : NeonI_2VMisc<Q, U, size, opcode,
7609 (outs ResVPR:$Rd), (ins ResVPR:$Rn),
7610 asmop # "\t$Rd." # Res # ", $Rn." # Res,
7611 [(set (ResTy ResVPR:$Rd),
7612 (ResTy (Neon_Rev (ResTy ResVPR:$Rn))))],
7615 def REV64_16b : NeonI_REV<"rev64", "16b", 0b00, 0b1, 0b0, 0b00000, VPR128,
7617 def REV64_8h : NeonI_REV<"rev64", "8h", 0b01, 0b1, 0b0, 0b00000, VPR128,
7619 def REV64_4s : NeonI_REV<"rev64", "4s", 0b10, 0b1, 0b0, 0b00000, VPR128,
7621 def REV64_8b : NeonI_REV<"rev64", "8b", 0b00, 0b0, 0b0, 0b00000, VPR64,
7623 def REV64_4h : NeonI_REV<"rev64", "4h", 0b01, 0b0, 0b0, 0b00000, VPR64,
7625 def REV64_2s : NeonI_REV<"rev64", "2s", 0b10, 0b0, 0b0, 0b00000, VPR64,
7628 def : Pat<(v4f32 (Neon_rev64 (v4f32 VPR128:$Rn))), (REV64_4s VPR128:$Rn)>;
7629 def : Pat<(v2f32 (Neon_rev64 (v2f32 VPR64:$Rn))), (REV64_2s VPR64:$Rn)>;
7631 def REV32_16b : NeonI_REV<"rev32", "16b", 0b00, 0b1, 0b1, 0b00000, VPR128,
7633 def REV32_8h : NeonI_REV<"rev32", "8h", 0b01, 0b1, 0b1, 0b00000, VPR128,
7635 def REV32_8b : NeonI_REV<"rev32", "8b", 0b00, 0b0, 0b1, 0b00000, VPR64,
7637 def REV32_4h : NeonI_REV<"rev32", "4h", 0b01, 0b0, 0b1, 0b00000, VPR64,
7640 def REV16_16b : NeonI_REV<"rev16", "16b", 0b00, 0b1, 0b0, 0b00001, VPR128,
7642 def REV16_8b : NeonI_REV<"rev16", "8b", 0b00, 0b0, 0b0, 0b00001, VPR64,
7645 multiclass NeonI_PairwiseAdd<string asmop, bit U, bits<5> opcode,
7646 SDPatternOperator Neon_Padd> {
7647 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7648 (outs VPR128:$Rd), (ins VPR128:$Rn),
7649 asmop # "\t$Rd.8h, $Rn.16b",
7650 [(set (v8i16 VPR128:$Rd),
7651 (v8i16 (Neon_Padd (v16i8 VPR128:$Rn))))],
7654 def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7655 (outs VPR64:$Rd), (ins VPR64:$Rn),
7656 asmop # "\t$Rd.4h, $Rn.8b",
7657 [(set (v4i16 VPR64:$Rd),
7658 (v4i16 (Neon_Padd (v8i8 VPR64:$Rn))))],
7661 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7662 (outs VPR128:$Rd), (ins VPR128:$Rn),
7663 asmop # "\t$Rd.4s, $Rn.8h",
7664 [(set (v4i32 VPR128:$Rd),
7665 (v4i32 (Neon_Padd (v8i16 VPR128:$Rn))))],
7668 def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7669 (outs VPR64:$Rd), (ins VPR64:$Rn),
7670 asmop # "\t$Rd.2s, $Rn.4h",
7671 [(set (v2i32 VPR64:$Rd),
7672 (v2i32 (Neon_Padd (v4i16 VPR64:$Rn))))],
7675 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7676 (outs VPR128:$Rd), (ins VPR128:$Rn),
7677 asmop # "\t$Rd.2d, $Rn.4s",
7678 [(set (v2i64 VPR128:$Rd),
7679 (v2i64 (Neon_Padd (v4i32 VPR128:$Rn))))],
7682 def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7683 (outs VPR64:$Rd), (ins VPR64:$Rn),
7684 asmop # "\t$Rd.1d, $Rn.2s",
7685 [(set (v1i64 VPR64:$Rd),
7686 (v1i64 (Neon_Padd (v2i32 VPR64:$Rn))))],
7690 defm SADDLP : NeonI_PairwiseAdd<"saddlp", 0b0, 0b00010,
7691 int_arm_neon_vpaddls>;
7692 defm UADDLP : NeonI_PairwiseAdd<"uaddlp", 0b1, 0b00010,
7693 int_arm_neon_vpaddlu>;
7695 def : Pat<(v1i64 (int_aarch64_neon_saddlv (v2i32 VPR64:$Rn))),
7697 def : Pat<(v1i64 (int_aarch64_neon_uaddlv (v2i32 VPR64:$Rn))),
7700 multiclass NeonI_PairwiseAddAcc<string asmop, bit U, bits<5> opcode,
7701 SDPatternOperator Neon_Padd> {
7702 let Constraints = "$src = $Rd" in {
7703 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7704 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7705 asmop # "\t$Rd.8h, $Rn.16b",
7706 [(set (v8i16 VPR128:$Rd),
7708 (v8i16 VPR128:$src), (v16i8 VPR128:$Rn))))],
7711 def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7712 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7713 asmop # "\t$Rd.4h, $Rn.8b",
7714 [(set (v4i16 VPR64:$Rd),
7716 (v4i16 VPR64:$src), (v8i8 VPR64:$Rn))))],
7719 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7720 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7721 asmop # "\t$Rd.4s, $Rn.8h",
7722 [(set (v4i32 VPR128:$Rd),
7724 (v4i32 VPR128:$src), (v8i16 VPR128:$Rn))))],
7727 def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7728 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7729 asmop # "\t$Rd.2s, $Rn.4h",
7730 [(set (v2i32 VPR64:$Rd),
7732 (v2i32 VPR64:$src), (v4i16 VPR64:$Rn))))],
7735 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7736 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7737 asmop # "\t$Rd.2d, $Rn.4s",
7738 [(set (v2i64 VPR128:$Rd),
7740 (v2i64 VPR128:$src), (v4i32 VPR128:$Rn))))],
7743 def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7744 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7745 asmop # "\t$Rd.1d, $Rn.2s",
7746 [(set (v1i64 VPR64:$Rd),
7748 (v1i64 VPR64:$src), (v2i32 VPR64:$Rn))))],
7753 defm SADALP : NeonI_PairwiseAddAcc<"sadalp", 0b0, 0b00110,
7754 int_arm_neon_vpadals>;
7755 defm UADALP : NeonI_PairwiseAddAcc<"uadalp", 0b1, 0b00110,
7756 int_arm_neon_vpadalu>;
7758 multiclass NeonI_2VMisc_BHSDsize_1Arg<string asmop, bit U, bits<5> opcode> {
7759 def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7760 (outs VPR128:$Rd), (ins VPR128:$Rn),
7761 asmop # "\t$Rd.16b, $Rn.16b",
7764 def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7765 (outs VPR128:$Rd), (ins VPR128:$Rn),
7766 asmop # "\t$Rd.8h, $Rn.8h",
7769 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7770 (outs VPR128:$Rd), (ins VPR128:$Rn),
7771 asmop # "\t$Rd.4s, $Rn.4s",
7774 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7775 (outs VPR128:$Rd), (ins VPR128:$Rn),
7776 asmop # "\t$Rd.2d, $Rn.2d",
7779 def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7780 (outs VPR64:$Rd), (ins VPR64:$Rn),
7781 asmop # "\t$Rd.8b, $Rn.8b",
7784 def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7785 (outs VPR64:$Rd), (ins VPR64:$Rn),
7786 asmop # "\t$Rd.4h, $Rn.4h",
7789 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7790 (outs VPR64:$Rd), (ins VPR64:$Rn),
7791 asmop # "\t$Rd.2s, $Rn.2s",
7795 defm SQABS : NeonI_2VMisc_BHSDsize_1Arg<"sqabs", 0b0, 0b00111>;
7796 defm SQNEG : NeonI_2VMisc_BHSDsize_1Arg<"sqneg", 0b1, 0b00111>;
7797 defm ABS : NeonI_2VMisc_BHSDsize_1Arg<"abs", 0b0, 0b01011>;
7798 defm NEG : NeonI_2VMisc_BHSDsize_1Arg<"neg", 0b1, 0b01011>;
7800 multiclass NeonI_2VMisc_BHSD_1Arg_Pattern<string Prefix,
7801 SDPatternOperator Neon_Op> {
7802 def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$Rn))),
7803 (v16i8 (!cast<Instruction>(Prefix # 16b) (v16i8 VPR128:$Rn)))>;
7805 def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$Rn))),
7806 (v8i16 (!cast<Instruction>(Prefix # 8h) (v8i16 VPR128:$Rn)))>;
7808 def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$Rn))),
7809 (v4i32 (!cast<Instruction>(Prefix # 4s) (v4i32 VPR128:$Rn)))>;
7811 def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$Rn))),
7812 (v2i64 (!cast<Instruction>(Prefix # 2d) (v2i64 VPR128:$Rn)))>;
7814 def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$Rn))),
7815 (v8i8 (!cast<Instruction>(Prefix # 8b) (v8i8 VPR64:$Rn)))>;
7817 def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$Rn))),
7818 (v4i16 (!cast<Instruction>(Prefix # 4h) (v4i16 VPR64:$Rn)))>;
7820 def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$Rn))),
7821 (v2i32 (!cast<Instruction>(Prefix # 2s) (v2i32 VPR64:$Rn)))>;
7824 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQABS", int_arm_neon_vqabs>;
7825 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQNEG", int_arm_neon_vqneg>;
7826 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"ABS", int_arm_neon_vabs>;
7828 def : Pat<(v16i8 (sub
7829 (v16i8 Neon_AllZero),
7830 (v16i8 VPR128:$Rn))),
7831 (v16i8 (NEG16b (v16i8 VPR128:$Rn)))>;
7832 def : Pat<(v8i8 (sub
7833 (v8i8 Neon_AllZero),
7835 (v8i8 (NEG8b (v8i8 VPR64:$Rn)))>;
7836 def : Pat<(v8i16 (sub
7837 (v8i16 (bitconvert (v16i8 Neon_AllZero))),
7838 (v8i16 VPR128:$Rn))),
7839 (v8i16 (NEG8h (v8i16 VPR128:$Rn)))>;
7840 def : Pat<(v4i16 (sub
7841 (v4i16 (bitconvert (v8i8 Neon_AllZero))),
7842 (v4i16 VPR64:$Rn))),
7843 (v4i16 (NEG4h (v4i16 VPR64:$Rn)))>;
7844 def : Pat<(v4i32 (sub
7845 (v4i32 (bitconvert (v16i8 Neon_AllZero))),
7846 (v4i32 VPR128:$Rn))),
7847 (v4i32 (NEG4s (v4i32 VPR128:$Rn)))>;
7848 def : Pat<(v2i32 (sub
7849 (v2i32 (bitconvert (v8i8 Neon_AllZero))),
7850 (v2i32 VPR64:$Rn))),
7851 (v2i32 (NEG2s (v2i32 VPR64:$Rn)))>;
7852 def : Pat<(v2i64 (sub
7853 (v2i64 (bitconvert (v16i8 Neon_AllZero))),
7854 (v2i64 VPR128:$Rn))),
7855 (v2i64 (NEG2d (v2i64 VPR128:$Rn)))>;
7857 multiclass NeonI_2VMisc_BHSDsize_2Args<string asmop, bit U, bits<5> opcode> {
7858 let Constraints = "$src = $Rd" in {
7859 def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7860 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7861 asmop # "\t$Rd.16b, $Rn.16b",
7864 def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7865 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7866 asmop # "\t$Rd.8h, $Rn.8h",
7869 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7870 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7871 asmop # "\t$Rd.4s, $Rn.4s",
7874 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7875 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7876 asmop # "\t$Rd.2d, $Rn.2d",
7879 def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7880 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7881 asmop # "\t$Rd.8b, $Rn.8b",
7884 def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7885 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7886 asmop # "\t$Rd.4h, $Rn.4h",
7889 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7890 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7891 asmop # "\t$Rd.2s, $Rn.2s",
7896 defm SUQADD : NeonI_2VMisc_BHSDsize_2Args<"suqadd", 0b0, 0b00011>;
7897 defm USQADD : NeonI_2VMisc_BHSDsize_2Args<"usqadd", 0b1, 0b00011>;
7899 multiclass NeonI_2VMisc_BHSD_2Args_Pattern<string Prefix,
7900 SDPatternOperator Neon_Op> {
7901 def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$src), (v16i8 VPR128:$Rn))),
7902 (v16i8 (!cast<Instruction>(Prefix # 16b)
7903 (v16i8 VPR128:$src), (v16i8 VPR128:$Rn)))>;
7905 def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$src), (v8i16 VPR128:$Rn))),
7906 (v8i16 (!cast<Instruction>(Prefix # 8h)
7907 (v8i16 VPR128:$src), (v8i16 VPR128:$Rn)))>;
7909 def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$src), (v4i32 VPR128:$Rn))),
7910 (v4i32 (!cast<Instruction>(Prefix # 4s)
7911 (v4i32 VPR128:$src), (v4i32 VPR128:$Rn)))>;
7913 def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$src), (v2i64 VPR128:$Rn))),
7914 (v2i64 (!cast<Instruction>(Prefix # 2d)
7915 (v2i64 VPR128:$src), (v2i64 VPR128:$Rn)))>;
7917 def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$src), (v8i8 VPR64:$Rn))),
7918 (v8i8 (!cast<Instruction>(Prefix # 8b)
7919 (v8i8 VPR64:$src), (v8i8 VPR64:$Rn)))>;
7921 def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$src), (v4i16 VPR64:$Rn))),
7922 (v4i16 (!cast<Instruction>(Prefix # 4h)
7923 (v4i16 VPR64:$src), (v4i16 VPR64:$Rn)))>;
7925 def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$src), (v2i32 VPR64:$Rn))),
7926 (v2i32 (!cast<Instruction>(Prefix # 2s)
7927 (v2i32 VPR64:$src), (v2i32 VPR64:$Rn)))>;
7930 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"SUQADD", int_aarch64_neon_suqadd>;
7931 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"USQADD", int_aarch64_neon_usqadd>;
7933 multiclass NeonI_2VMisc_BHSsizes<string asmop, bit U,
7934 SDPatternOperator Neon_Op> {
7935 def 16b : NeonI_2VMisc<0b1, U, 0b00, 0b00100,
7936 (outs VPR128:$Rd), (ins VPR128:$Rn),
7937 asmop # "\t$Rd.16b, $Rn.16b",
7938 [(set (v16i8 VPR128:$Rd),
7939 (v16i8 (Neon_Op (v16i8 VPR128:$Rn))))],
7942 def 8h : NeonI_2VMisc<0b1, U, 0b01, 0b00100,
7943 (outs VPR128:$Rd), (ins VPR128:$Rn),
7944 asmop # "\t$Rd.8h, $Rn.8h",
7945 [(set (v8i16 VPR128:$Rd),
7946 (v8i16 (Neon_Op (v8i16 VPR128:$Rn))))],
7949 def 4s : NeonI_2VMisc<0b1, U, 0b10, 0b00100,
7950 (outs VPR128:$Rd), (ins VPR128:$Rn),
7951 asmop # "\t$Rd.4s, $Rn.4s",
7952 [(set (v4i32 VPR128:$Rd),
7953 (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
7956 def 8b : NeonI_2VMisc<0b0, U, 0b00, 0b00100,
7957 (outs VPR64:$Rd), (ins VPR64:$Rn),
7958 asmop # "\t$Rd.8b, $Rn.8b",
7959 [(set (v8i8 VPR64:$Rd),
7960 (v8i8 (Neon_Op (v8i8 VPR64:$Rn))))],
7963 def 4h : NeonI_2VMisc<0b0, U, 0b01, 0b00100,
7964 (outs VPR64:$Rd), (ins VPR64:$Rn),
7965 asmop # "\t$Rd.4h, $Rn.4h",
7966 [(set (v4i16 VPR64:$Rd),
7967 (v4i16 (Neon_Op (v4i16 VPR64:$Rn))))],
7970 def 2s : NeonI_2VMisc<0b0, U, 0b10, 0b00100,
7971 (outs VPR64:$Rd), (ins VPR64:$Rn),
7972 asmop # "\t$Rd.2s, $Rn.2s",
7973 [(set (v2i32 VPR64:$Rd),
7974 (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
7978 defm CLS : NeonI_2VMisc_BHSsizes<"cls", 0b0, int_arm_neon_vcls>;
7979 defm CLZ : NeonI_2VMisc_BHSsizes<"clz", 0b1, ctlz>;
7981 multiclass NeonI_2VMisc_Bsize<string asmop, bit U, bits<2> size,
7983 def 16b : NeonI_2VMisc<0b1, U, size, Opcode,
7984 (outs VPR128:$Rd), (ins VPR128:$Rn),
7985 asmop # "\t$Rd.16b, $Rn.16b",
7988 def 8b : NeonI_2VMisc<0b0, U, size, Opcode,
7989 (outs VPR64:$Rd), (ins VPR64:$Rn),
7990 asmop # "\t$Rd.8b, $Rn.8b",
7994 defm CNT : NeonI_2VMisc_Bsize<"cnt", 0b0, 0b00, 0b00101>;
7995 defm NOT : NeonI_2VMisc_Bsize<"not", 0b1, 0b00, 0b00101>;
7996 defm RBIT : NeonI_2VMisc_Bsize<"rbit", 0b1, 0b01, 0b00101>;
7998 def : NeonInstAlias<"mvn $Rd.16b, $Rn.16b",
7999 (NOT16b VPR128:$Rd, VPR128:$Rn), 0>;
8000 def : NeonInstAlias<"mvn $Rd.8b, $Rn.8b",
8001 (NOT8b VPR64:$Rd, VPR64:$Rn), 0>;
8003 def : Pat<(v16i8 (ctpop (v16i8 VPR128:$Rn))),
8004 (v16i8 (CNT16b (v16i8 VPR128:$Rn)))>;
8005 def : Pat<(v8i8 (ctpop (v8i8 VPR64:$Rn))),
8006 (v8i8 (CNT8b (v8i8 VPR64:$Rn)))>;
8008 def : Pat<(v16i8 (xor
8010 (v16i8 Neon_AllOne))),
8011 (v16i8 (NOT16b (v16i8 VPR128:$Rn)))>;
8012 def : Pat<(v8i8 (xor
8014 (v8i8 Neon_AllOne))),
8015 (v8i8 (NOT8b (v8i8 VPR64:$Rn)))>;
8016 def : Pat<(v8i16 (xor
8018 (v8i16 (bitconvert (v16i8 Neon_AllOne))))),
8019 (NOT16b VPR128:$Rn)>;
8020 def : Pat<(v4i16 (xor
8022 (v4i16 (bitconvert (v8i8 Neon_AllOne))))),
8024 def : Pat<(v4i32 (xor
8026 (v4i32 (bitconvert (v16i8 Neon_AllOne))))),
8027 (NOT16b VPR128:$Rn)>;
8028 def : Pat<(v2i32 (xor
8030 (v2i32 (bitconvert (v8i8 Neon_AllOne))))),
8032 def : Pat<(v2i64 (xor
8034 (v2i64 (bitconvert (v16i8 Neon_AllOne))))),
8035 (NOT16b VPR128:$Rn)>;
8037 def : Pat<(v16i8 (int_aarch64_neon_rbit (v16i8 VPR128:$Rn))),
8038 (v16i8 (RBIT16b (v16i8 VPR128:$Rn)))>;
8039 def : Pat<(v8i8 (int_aarch64_neon_rbit (v8i8 VPR64:$Rn))),
8040 (v8i8 (RBIT8b (v8i8 VPR64:$Rn)))>;
8042 multiclass NeonI_2VMisc_SDsizes<string asmop, bit U, bits<5> opcode,
8043 SDPatternOperator Neon_Op> {
8044 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8045 (outs VPR128:$Rd), (ins VPR128:$Rn),
8046 asmop # "\t$Rd.4s, $Rn.4s",
8047 [(set (v4f32 VPR128:$Rd),
8048 (v4f32 (Neon_Op (v4f32 VPR128:$Rn))))],
8051 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
8052 (outs VPR128:$Rd), (ins VPR128:$Rn),
8053 asmop # "\t$Rd.2d, $Rn.2d",
8054 [(set (v2f64 VPR128:$Rd),
8055 (v2f64 (Neon_Op (v2f64 VPR128:$Rn))))],
8058 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8059 (outs VPR64:$Rd), (ins VPR64:$Rn),
8060 asmop # "\t$Rd.2s, $Rn.2s",
8061 [(set (v2f32 VPR64:$Rd),
8062 (v2f32 (Neon_Op (v2f32 VPR64:$Rn))))],
8066 defm FABS : NeonI_2VMisc_SDsizes<"fabs", 0b0, 0b01111, fabs>;
8067 defm FNEG : NeonI_2VMisc_SDsizes<"fneg", 0b1, 0b01111, fneg>;
8069 multiclass NeonI_2VMisc_HSD_Narrow<string asmop, bit U, bits<5> opcode> {
8070 def 8h8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
8071 (outs VPR64:$Rd), (ins VPR128:$Rn),
8072 asmop # "\t$Rd.8b, $Rn.8h",
8075 def 4s4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
8076 (outs VPR64:$Rd), (ins VPR128:$Rn),
8077 asmop # "\t$Rd.4h, $Rn.4s",
8080 def 2d2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8081 (outs VPR64:$Rd), (ins VPR128:$Rn),
8082 asmop # "\t$Rd.2s, $Rn.2d",
8085 let Constraints = "$Rd = $src" in {
8086 def 8h16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
8087 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8088 asmop # "2\t$Rd.16b, $Rn.8h",
8091 def 4s8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
8092 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8093 asmop # "2\t$Rd.8h, $Rn.4s",
8096 def 2d4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8097 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8098 asmop # "2\t$Rd.4s, $Rn.2d",
8103 defm XTN : NeonI_2VMisc_HSD_Narrow<"xtn", 0b0, 0b10010>;
8104 defm SQXTUN : NeonI_2VMisc_HSD_Narrow<"sqxtun", 0b1, 0b10010>;
8105 defm SQXTN : NeonI_2VMisc_HSD_Narrow<"sqxtn", 0b0, 0b10100>;
8106 defm UQXTN : NeonI_2VMisc_HSD_Narrow<"uqxtn", 0b1, 0b10100>;
8108 multiclass NeonI_2VMisc_Narrow_Patterns<string Prefix,
8109 SDPatternOperator Neon_Op> {
8110 def : Pat<(v8i8 (Neon_Op (v8i16 VPR128:$Rn))),
8111 (v8i8 (!cast<Instruction>(Prefix # 8h8b) (v8i16 VPR128:$Rn)))>;
8113 def : Pat<(v4i16 (Neon_Op (v4i32 VPR128:$Rn))),
8114 (v4i16 (!cast<Instruction>(Prefix # 4s4h) (v4i32 VPR128:$Rn)))>;
8116 def : Pat<(v2i32 (Neon_Op (v2i64 VPR128:$Rn))),
8117 (v2i32 (!cast<Instruction>(Prefix # 2d2s) (v2i64 VPR128:$Rn)))>;
8119 def : Pat<(v16i8 (concat_vectors
8121 (v8i8 (Neon_Op (v8i16 VPR128:$Rn))))),
8122 (!cast<Instruction>(Prefix # 8h16b)
8123 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8126 def : Pat<(v8i16 (concat_vectors
8128 (v4i16 (Neon_Op (v4i32 VPR128:$Rn))))),
8129 (!cast<Instruction>(Prefix # 4s8h)
8130 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8133 def : Pat<(v4i32 (concat_vectors
8135 (v2i32 (Neon_Op (v2i64 VPR128:$Rn))))),
8136 (!cast<Instruction>(Prefix # 2d4s)
8137 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8141 defm : NeonI_2VMisc_Narrow_Patterns<"XTN", trunc>;
8142 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTUN", int_arm_neon_vqmovnsu>;
8143 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTN", int_arm_neon_vqmovns>;
8144 defm : NeonI_2VMisc_Narrow_Patterns<"UQXTN", int_arm_neon_vqmovnu>;
8146 multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> {
8147 let DecoderMethod = "DecodeSHLLInstruction" in {
8148 def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8150 (ins VPR64:$Rn, uimm_exact8:$Imm),
8151 asmop # "\t$Rd.8h, $Rn.8b, $Imm",
8154 def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8156 (ins VPR64:$Rn, uimm_exact16:$Imm),
8157 asmop # "\t$Rd.4s, $Rn.4h, $Imm",
8160 def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
8162 (ins VPR64:$Rn, uimm_exact32:$Imm),
8163 asmop # "\t$Rd.2d, $Rn.2s, $Imm",
8166 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8168 (ins VPR128:$Rn, uimm_exact8:$Imm),
8169 asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
8172 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8174 (ins VPR128:$Rn, uimm_exact16:$Imm),
8175 asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
8178 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
8180 (ins VPR128:$Rn, uimm_exact32:$Imm),
8181 asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
8186 defm SHLL : NeonI_2VMisc_SHIFT<"shll", 0b1, 0b10011>;
8188 class NeonI_SHLL_Patterns<ValueType OpTy, ValueType DesTy,
8189 SDPatternOperator ExtOp, Operand Neon_Imm,
8192 (DesTy (ExtOp (OpTy VPR64:$Rn))),
8194 (i32 Neon_Imm:$Imm))))),
8195 (!cast<Instruction>("SHLL" # suffix) VPR64:$Rn, Neon_Imm:$Imm)>;
8197 class NeonI_SHLL_High_Patterns<ValueType OpTy, ValueType DesTy,
8198 SDPatternOperator ExtOp, Operand Neon_Imm,
8199 string suffix, PatFrag GetHigh>
8202 (OpTy (GetHigh VPR128:$Rn)))),
8204 (i32 Neon_Imm:$Imm))))),
8205 (!cast<Instruction>("SHLL" # suffix) VPR128:$Rn, Neon_Imm:$Imm)>;
8207 def : NeonI_SHLL_Patterns<v8i8, v8i16, zext, uimm_exact8, "8b8h">;
8208 def : NeonI_SHLL_Patterns<v8i8, v8i16, sext, uimm_exact8, "8b8h">;
8209 def : NeonI_SHLL_Patterns<v4i16, v4i32, zext, uimm_exact16, "4h4s">;
8210 def : NeonI_SHLL_Patterns<v4i16, v4i32, sext, uimm_exact16, "4h4s">;
8211 def : NeonI_SHLL_Patterns<v2i32, v2i64, zext, uimm_exact32, "2s2d">;
8212 def : NeonI_SHLL_Patterns<v2i32, v2i64, sext, uimm_exact32, "2s2d">;
8213 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, zext, uimm_exact8, "16b8h",
8215 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, sext, uimm_exact8, "16b8h",
8217 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, zext, uimm_exact16, "8h4s",
8219 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, sext, uimm_exact16, "8h4s",
8221 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, zext, uimm_exact32, "4s2d",
8223 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, sext, uimm_exact32, "4s2d",
8226 multiclass NeonI_2VMisc_SD_Narrow<string asmop, bit U, bits<5> opcode> {
8227 def 4s4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8228 (outs VPR64:$Rd), (ins VPR128:$Rn),
8229 asmop # "\t$Rd.4h, $Rn.4s",
8232 def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8233 (outs VPR64:$Rd), (ins VPR128:$Rn),
8234 asmop # "\t$Rd.2s, $Rn.2d",
8237 let Constraints = "$src = $Rd" in {
8238 def 4s8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8239 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8240 asmop # "2\t$Rd.8h, $Rn.4s",
8243 def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8244 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8245 asmop # "2\t$Rd.4s, $Rn.2d",
8250 defm FCVTN : NeonI_2VMisc_SD_Narrow<"fcvtn", 0b0, 0b10110>;
8252 multiclass NeonI_2VMisc_Narrow_Pattern<string prefix,
8253 SDPatternOperator f32_to_f16_Op,
8254 SDPatternOperator f64_to_f32_Op> {
8256 def : Pat<(v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))),
8257 (!cast<Instruction>(prefix # "4s4h") (v4f32 VPR128:$Rn))>;
8259 def : Pat<(v8i16 (concat_vectors
8261 (v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))))),
8262 (!cast<Instruction>(prefix # "4s8h")
8263 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8264 (v4f32 VPR128:$Rn))>;
8266 def : Pat<(v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))),
8267 (!cast<Instruction>(prefix # "2d2s") (v2f64 VPR128:$Rn))>;
8269 def : Pat<(v4f32 (concat_vectors
8271 (v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))))),
8272 (!cast<Instruction>(prefix # "2d4s")
8273 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8274 (v2f64 VPR128:$Rn))>;
8277 defm : NeonI_2VMisc_Narrow_Pattern<"FCVTN", int_arm_neon_vcvtfp2hf, fround>;
8279 multiclass NeonI_2VMisc_D_Narrow<string asmop, string prefix, bit U,
8281 def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8282 (outs VPR64:$Rd), (ins VPR128:$Rn),
8283 asmop # "\t$Rd.2s, $Rn.2d",
8286 def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8287 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8288 asmop # "2\t$Rd.4s, $Rn.2d",
8290 let Constraints = "$src = $Rd";
8293 def : Pat<(v2f32 (int_aarch64_neon_fcvtxn (v2f64 VPR128:$Rn))),
8294 (!cast<Instruction>(prefix # "2d2s") VPR128:$Rn)>;
8296 def : Pat<(v4f32 (concat_vectors
8298 (v2f32 (int_aarch64_neon_fcvtxn (v2f64 VPR128:$Rn))))),
8299 (!cast<Instruction>(prefix # "2d4s")
8300 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8304 defm FCVTXN : NeonI_2VMisc_D_Narrow<"fcvtxn","FCVTXN", 0b1, 0b10110>;
8306 def Neon_High4Float : PatFrag<(ops node:$in),
8307 (extract_subvector (v4f32 node:$in), (iPTR 2))>;
8309 multiclass NeonI_2VMisc_HS_Extend<string asmop, bit U, bits<5> opcode> {
8310 def 4h4s : NeonI_2VMisc<0b0, U, 0b00, opcode,
8311 (outs VPR128:$Rd), (ins VPR64:$Rn),
8312 asmop # "\t$Rd.4s, $Rn.4h",
8315 def 2s2d : NeonI_2VMisc<0b0, U, 0b01, opcode,
8316 (outs VPR128:$Rd), (ins VPR64:$Rn),
8317 asmop # "\t$Rd.2d, $Rn.2s",
8320 def 8h4s : NeonI_2VMisc<0b1, U, 0b00, opcode,
8321 (outs VPR128:$Rd), (ins VPR128:$Rn),
8322 asmop # "2\t$Rd.4s, $Rn.8h",
8325 def 4s2d : NeonI_2VMisc<0b1, U, 0b01, opcode,
8326 (outs VPR128:$Rd), (ins VPR128:$Rn),
8327 asmop # "2\t$Rd.2d, $Rn.4s",
8331 defm FCVTL : NeonI_2VMisc_HS_Extend<"fcvtl", 0b0, 0b10111>;
8333 multiclass NeonI_2VMisc_Extend_Pattern<string prefix> {
8334 def : Pat<(v4f32 (int_arm_neon_vcvthf2fp (v4i16 VPR64:$Rn))),
8335 (!cast<Instruction>(prefix # "4h4s") VPR64:$Rn)>;
8337 def : Pat<(v4f32 (int_arm_neon_vcvthf2fp
8339 (v8i16 VPR128:$Rn))))),
8340 (!cast<Instruction>(prefix # "8h4s") VPR128:$Rn)>;
8342 def : Pat<(v2f64 (fextend (v2f32 VPR64:$Rn))),
8343 (!cast<Instruction>(prefix # "2s2d") VPR64:$Rn)>;
8345 def : Pat<(v2f64 (fextend
8346 (v2f32 (Neon_High4Float
8347 (v4f32 VPR128:$Rn))))),
8348 (!cast<Instruction>(prefix # "4s2d") VPR128:$Rn)>;
8351 defm : NeonI_2VMisc_Extend_Pattern<"FCVTL">;
8353 multiclass NeonI_2VMisc_SD_Conv<string asmop, bit Size, bit U, bits<5> opcode,
8354 ValueType ResTy4s, ValueType OpTy4s,
8355 ValueType ResTy2d, ValueType OpTy2d,
8356 ValueType ResTy2s, ValueType OpTy2s,
8357 SDPatternOperator Neon_Op> {
8359 def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8360 (outs VPR128:$Rd), (ins VPR128:$Rn),
8361 asmop # "\t$Rd.4s, $Rn.4s",
8362 [(set (ResTy4s VPR128:$Rd),
8363 (ResTy4s (Neon_Op (OpTy4s VPR128:$Rn))))],
8366 def 2d : NeonI_2VMisc<0b1, U, {Size, 0b1}, opcode,
8367 (outs VPR128:$Rd), (ins VPR128:$Rn),
8368 asmop # "\t$Rd.2d, $Rn.2d",
8369 [(set (ResTy2d VPR128:$Rd),
8370 (ResTy2d (Neon_Op (OpTy2d VPR128:$Rn))))],
8373 def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8374 (outs VPR64:$Rd), (ins VPR64:$Rn),
8375 asmop # "\t$Rd.2s, $Rn.2s",
8376 [(set (ResTy2s VPR64:$Rd),
8377 (ResTy2s (Neon_Op (OpTy2s VPR64:$Rn))))],
8381 multiclass NeonI_2VMisc_fp_to_int<string asmop, bit Size, bit U,
8382 bits<5> opcode, SDPatternOperator Neon_Op> {
8383 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4i32, v4f32, v2i64,
8384 v2f64, v2i32, v2f32, Neon_Op>;
8387 defm FCVTNS : NeonI_2VMisc_fp_to_int<"fcvtns", 0b0, 0b0, 0b11010,
8388 int_aarch64_neon_fcvtns>;
8389 defm FCVTNU : NeonI_2VMisc_fp_to_int<"fcvtnu", 0b0, 0b1, 0b11010,
8390 int_aarch64_neon_fcvtnu>;
8391 defm FCVTPS : NeonI_2VMisc_fp_to_int<"fcvtps", 0b1, 0b0, 0b11010,
8392 int_aarch64_neon_fcvtps>;
8393 defm FCVTPU : NeonI_2VMisc_fp_to_int<"fcvtpu", 0b1, 0b1, 0b11010,
8394 int_aarch64_neon_fcvtpu>;
8395 defm FCVTMS : NeonI_2VMisc_fp_to_int<"fcvtms", 0b0, 0b0, 0b11011,
8396 int_aarch64_neon_fcvtms>;
8397 defm FCVTMU : NeonI_2VMisc_fp_to_int<"fcvtmu", 0b0, 0b1, 0b11011,
8398 int_aarch64_neon_fcvtmu>;
8399 defm FCVTZS : NeonI_2VMisc_fp_to_int<"fcvtzs", 0b1, 0b0, 0b11011, fp_to_sint>;
8400 defm FCVTZU : NeonI_2VMisc_fp_to_int<"fcvtzu", 0b1, 0b1, 0b11011, fp_to_uint>;
8401 defm FCVTAS : NeonI_2VMisc_fp_to_int<"fcvtas", 0b0, 0b0, 0b11100,
8402 int_aarch64_neon_fcvtas>;
8403 defm FCVTAU : NeonI_2VMisc_fp_to_int<"fcvtau", 0b0, 0b1, 0b11100,
8404 int_aarch64_neon_fcvtau>;
8406 multiclass NeonI_2VMisc_int_to_fp<string asmop, bit Size, bit U,
8407 bits<5> opcode, SDPatternOperator Neon_Op> {
8408 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4i32, v2f64,
8409 v2i64, v2f32, v2i32, Neon_Op>;
8412 defm SCVTF : NeonI_2VMisc_int_to_fp<"scvtf", 0b0, 0b0, 0b11101, sint_to_fp>;
8413 defm UCVTF : NeonI_2VMisc_int_to_fp<"ucvtf", 0b0, 0b1, 0b11101, uint_to_fp>;
8415 multiclass NeonI_2VMisc_fp_to_fp<string asmop, bit Size, bit U,
8416 bits<5> opcode, SDPatternOperator Neon_Op> {
8417 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4f32, v2f64,
8418 v2f64, v2f32, v2f32, Neon_Op>;
8421 defm FRINTN : NeonI_2VMisc_fp_to_fp<"frintn", 0b0, 0b0, 0b11000,
8422 int_aarch64_neon_frintn>;
8423 defm FRINTA : NeonI_2VMisc_fp_to_fp<"frinta", 0b0, 0b1, 0b11000, frnd>;
8424 defm FRINTP : NeonI_2VMisc_fp_to_fp<"frintp", 0b1, 0b0, 0b11000, fceil>;
8425 defm FRINTM : NeonI_2VMisc_fp_to_fp<"frintm", 0b0, 0b0, 0b11001, ffloor>;
8426 defm FRINTX : NeonI_2VMisc_fp_to_fp<"frintx", 0b0, 0b1, 0b11001, frint>;
8427 defm FRINTZ : NeonI_2VMisc_fp_to_fp<"frintz", 0b1, 0b0, 0b11001, ftrunc>;
8428 defm FRINTI : NeonI_2VMisc_fp_to_fp<"frinti", 0b1, 0b1, 0b11001, fnearbyint>;
8429 defm FRECPE : NeonI_2VMisc_fp_to_fp<"frecpe", 0b1, 0b0, 0b11101,
8430 int_arm_neon_vrecpe>;
8431 defm FRSQRTE : NeonI_2VMisc_fp_to_fp<"frsqrte", 0b1, 0b1, 0b11101,
8432 int_arm_neon_vrsqrte>;
8433 defm FSQRT : NeonI_2VMisc_fp_to_fp<"fsqrt", 0b1, 0b1, 0b11111, fsqrt>;
8435 multiclass NeonI_2VMisc_S_Conv<string asmop, bit Size, bit U,
8436 bits<5> opcode, SDPatternOperator Neon_Op> {
8437 def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8438 (outs VPR128:$Rd), (ins VPR128:$Rn),
8439 asmop # "\t$Rd.4s, $Rn.4s",
8440 [(set (v4i32 VPR128:$Rd),
8441 (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
8444 def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8445 (outs VPR64:$Rd), (ins VPR64:$Rn),
8446 asmop # "\t$Rd.2s, $Rn.2s",
8447 [(set (v2i32 VPR64:$Rd),
8448 (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8452 defm URECPE : NeonI_2VMisc_S_Conv<"urecpe", 0b1, 0b0, 0b11100,
8453 int_arm_neon_vrecpe>;
8454 defm URSQRTE : NeonI_2VMisc_S_Conv<"ursqrte", 0b1, 0b1, 0b11100,
8455 int_arm_neon_vrsqrte>;
8458 class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
8459 string asmop, SDPatternOperator opnode>
8460 : NeonI_Crypto_AES<size, opcode,
8461 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8462 asmop # "\t$Rd.16b, $Rn.16b",
8463 [(set (v16i8 VPR128:$Rd),
8464 (v16i8 (opnode (v16i8 VPR128:$src),
8465 (v16i8 VPR128:$Rn))))],
8467 let Constraints = "$src = $Rd";
8468 let Predicates = [HasNEON, HasCrypto];
8471 def AESE : NeonI_Cryptoaes_2v<0b00, 0b00100, "aese", int_arm_neon_aese>;
8472 def AESD : NeonI_Cryptoaes_2v<0b00, 0b00101, "aesd", int_arm_neon_aesd>;
8474 class NeonI_Cryptoaes<bits<2> size, bits<5> opcode,
8475 string asmop, SDPatternOperator opnode>
8476 : NeonI_Crypto_AES<size, opcode,
8477 (outs VPR128:$Rd), (ins VPR128:$Rn),
8478 asmop # "\t$Rd.16b, $Rn.16b",
8479 [(set (v16i8 VPR128:$Rd),
8480 (v16i8 (opnode (v16i8 VPR128:$Rn))))],
8483 def AESMC : NeonI_Cryptoaes<0b00, 0b00110, "aesmc", int_arm_neon_aesmc>;
8484 def AESIMC : NeonI_Cryptoaes<0b00, 0b00111, "aesimc", int_arm_neon_aesimc>;
8486 class NeonI_Cryptosha_vv<bits<2> size, bits<5> opcode,
8487 string asmop, SDPatternOperator opnode>
8488 : NeonI_Crypto_SHA<size, opcode,
8489 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8490 asmop # "\t$Rd.4s, $Rn.4s",
8491 [(set (v4i32 VPR128:$Rd),
8492 (v4i32 (opnode (v4i32 VPR128:$src),
8493 (v4i32 VPR128:$Rn))))],
8495 let Constraints = "$src = $Rd";
8496 let Predicates = [HasNEON, HasCrypto];
8499 def SHA1SU1 : NeonI_Cryptosha_vv<0b00, 0b00001, "sha1su1",
8500 int_arm_neon_sha1su1>;
8501 def SHA256SU0 : NeonI_Cryptosha_vv<0b00, 0b00010, "sha256su0",
8502 int_arm_neon_sha256su0>;
8504 class NeonI_Cryptosha_ss<bits<2> size, bits<5> opcode,
8505 string asmop, SDPatternOperator opnode>
8506 : NeonI_Crypto_SHA<size, opcode,
8507 (outs FPR32:$Rd), (ins FPR32:$Rn),
8508 asmop # "\t$Rd, $Rn",
8509 [(set (v1i32 FPR32:$Rd),
8510 (v1i32 (opnode (v1i32 FPR32:$Rn))))],
8512 let Predicates = [HasNEON, HasCrypto];
8515 def SHA1H : NeonI_Cryptosha_ss<0b00, 0b00000, "sha1h", int_arm_neon_sha1h>;
8517 class NeonI_Cryptosha3_vvv<bits<2> size, bits<3> opcode, string asmop,
8518 SDPatternOperator opnode>
8519 : NeonI_Crypto_3VSHA<size, opcode,
8521 (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
8522 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
8523 [(set (v4i32 VPR128:$Rd),
8524 (v4i32 (opnode (v4i32 VPR128:$src),
8526 (v4i32 VPR128:$Rm))))],
8528 let Constraints = "$src = $Rd";
8529 let Predicates = [HasNEON, HasCrypto];
8532 def SHA1SU0 : NeonI_Cryptosha3_vvv<0b00, 0b011, "sha1su0",
8533 int_arm_neon_sha1su0>;
8534 def SHA256SU1 : NeonI_Cryptosha3_vvv<0b00, 0b110, "sha256su1",
8535 int_arm_neon_sha256su1>;
8537 class NeonI_Cryptosha3_qqv<bits<2> size, bits<3> opcode, string asmop,
8538 SDPatternOperator opnode>
8539 : NeonI_Crypto_3VSHA<size, opcode,
8541 (ins FPR128:$src, FPR128:$Rn, VPR128:$Rm),
8542 asmop # "\t$Rd, $Rn, $Rm.4s",
8543 [(set (v4i32 FPR128:$Rd),
8544 (v4i32 (opnode (v4i32 FPR128:$src),
8546 (v4i32 VPR128:$Rm))))],
8548 let Constraints = "$src = $Rd";
8549 let Predicates = [HasNEON, HasCrypto];
8552 def SHA256H : NeonI_Cryptosha3_qqv<0b00, 0b100, "sha256h",
8553 int_arm_neon_sha256h>;
8554 def SHA256H2 : NeonI_Cryptosha3_qqv<0b00, 0b101, "sha256h2",
8555 int_arm_neon_sha256h2>;
8557 class NeonI_Cryptosha3_qsv<bits<2> size, bits<3> opcode, string asmop,
8558 SDPatternOperator opnode>
8559 : NeonI_Crypto_3VSHA<size, opcode,
8561 (ins FPR128:$src, FPR32:$Rn, VPR128:$Rm),
8562 asmop # "\t$Rd, $Rn, $Rm.4s",
8563 [(set (v4i32 FPR128:$Rd),
8564 (v4i32 (opnode (v4i32 FPR128:$src),
8566 (v4i32 VPR128:$Rm))))],
8568 let Constraints = "$src = $Rd";
8569 let Predicates = [HasNEON, HasCrypto];
8572 def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
8573 def SHA1P : NeonI_Cryptosha3_qsv<0b00, 0b001, "sha1p", int_aarch64_neon_sha1p>;
8574 def SHA1M : NeonI_Cryptosha3_qsv<0b00, 0b010, "sha1m", int_aarch64_neon_sha1m>;
8577 // Patterns for handling half-precision values
8580 // Convert f16 value coming in as i16 value to f32
8581 def : Pat<(f32 (f16_to_f32 (i32 (and (i32 GPR32:$Rn), 65535)))),
8582 (FCVTsh (EXTRACT_SUBREG (FMOVsw GPR32:$Rn), sub_16))>;
8583 def : Pat<(f32 (f16_to_f32 (i32 (assertzext GPR32:$Rn)))),
8584 (FCVTsh (EXTRACT_SUBREG (FMOVsw GPR32:$Rn), sub_16))>;
8586 def : Pat<(f32 (f16_to_f32 (i32 (assertzext (i32 (
8587 f32_to_f16 (f32 FPR32:$Rn))))))),
8590 // Patterns for vector extract of half-precision FP value in i16 storage type
8591 def : Pat<(f32 (f16_to_f32 ( i32 (and (i32 (vector_extract
8592 (v4i16 VPR64:$Rn), neon_uimm2_bare:$Imm)), 65535)))),
8593 (FCVTsh (f16 (DUPhv_H
8594 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8595 neon_uimm2_bare:$Imm)))>;
8597 def : Pat<(f32 (f16_to_f32 ( i32 (and (i32 (vector_extract
8598 (v8i16 VPR128:$Rn), neon_uimm3_bare:$Imm)), 65535)))),
8599 (FCVTsh (f16 (DUPhv_H (v8i16 VPR128:$Rn), neon_uimm3_bare:$Imm)))>;
8601 // Patterns for vector insert of half-precision FP value 0 in i16 storage type
8602 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8603 (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 0))))))),
8604 (neon_uimm3_bare:$Imm))),
8605 (v8i16 (INSELh (v8i16 VPR128:$Rn),
8606 (v8i16 (SUBREG_TO_REG (i64 0),
8607 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 WZR))), sub_16)),
8609 neon_uimm3_bare:$Imm, 0))>;
8611 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8612 (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 0))))))),
8613 (neon_uimm2_bare:$Imm))),
8614 (v4i16 (EXTRACT_SUBREG
8616 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8617 (v8i16 (SUBREG_TO_REG (i64 0),
8618 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 WZR))), sub_16)),
8620 neon_uimm2_bare:$Imm, 0)),
8623 // Patterns for vector insert of half-precision FP value in i16 storage type
8624 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8625 (i32 (assertsext (i32 (fp_to_sint
8626 (f32 (f16_to_f32 (i32 (and (i32 GPR32:$src), 65535)))))))),
8627 (neon_uimm3_bare:$Imm))),
8628 (v8i16 (INSELh (v8i16 VPR128:$Rn),
8629 (v8i16 (SUBREG_TO_REG (i64 0),
8630 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 GPR32:$src))), sub_16)),
8632 neon_uimm3_bare:$Imm, 0))>;
8634 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8635 (i32 (assertsext (i32 (fp_to_sint
8636 (f32 (f16_to_f32 (i32 (and (i32 GPR32:$src), 65535)))))))),
8637 (neon_uimm2_bare:$Imm))),
8638 (v4i16 (EXTRACT_SUBREG
8640 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8641 (v8i16 (SUBREG_TO_REG (i64 0),
8642 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 GPR32:$src))), sub_16)),
8644 neon_uimm2_bare:$Imm, 0)),
8647 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8648 (i32 (vector_extract (v8i16 VPR128:$src), neon_uimm3_bare:$Imm2)),
8649 (neon_uimm3_bare:$Imm1))),
8650 (v8i16 (INSELh (v8i16 VPR128:$Rn), (v8i16 VPR128:$src),
8651 neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2))>;
8653 // Patterns for vector copy of half-precision FP value in i16 storage type
8654 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8655 (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 (and (i32
8656 (vector_extract (v8i16 VPR128:$src), neon_uimm3_bare:$Imm2)),
8658 (neon_uimm3_bare:$Imm1))),
8659 (v8i16 (INSELh (v8i16 VPR128:$Rn), (v8i16 VPR128:$src),
8660 neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2))>;
8662 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8663 (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 (and (i32
8664 (vector_extract (v4i16 VPR64:$src), neon_uimm3_bare:$Imm2)),
8666 (neon_uimm3_bare:$Imm1))),
8667 (v4i16 (EXTRACT_SUBREG
8669 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8670 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
8671 neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2)),