lib/Target/AArch64/AArch64InstrNEON.td

   1 //===-- AArch64InstrNEON.td - NEON support for AArch64 -----*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the AArch64 NEON instruction set.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // NEON-specific DAG Nodes.
  16 //===----------------------------------------------------------------------===//
  17 def Neon_bsl       : SDNode<"AArch64ISD::NEON_BSL", SDTypeProfile<1, 3,
  18                       [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
  19                       SDTCisSameAs<0, 3>]>>;
  20
  21 // (outs Result), (ins Imm, OpCmode)
  22 def SDT_Neon_movi : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
  23
  24 def Neon_movi     : SDNode<"AArch64ISD::NEON_MOVIMM", SDT_Neon_movi>;
  25
  26 def Neon_mvni     : SDNode<"AArch64ISD::NEON_MVNIMM", SDT_Neon_movi>;
  27
  28 // (outs Result), (ins Imm)
  29 def Neon_fmovi : SDNode<"AArch64ISD::NEON_FMOVIMM", SDTypeProfile<1, 1,
  30                         [SDTCisVec<0>, SDTCisVT<1, i32>]>>;
  31
  32 // (outs Result), (ins LHS, RHS, CondCode)
  33 def Neon_cmp : SDNode<"AArch64ISD::NEON_CMP", SDTypeProfile<1, 3,
  34                  [SDTCisVec<0>,  SDTCisSameAs<1, 2>]>>;
  35
  36 // (outs Result), (ins LHS, 0/0.0 constant, CondCode)
  37 def Neon_cmpz : SDNode<"AArch64ISD::NEON_CMPZ", SDTypeProfile<1, 3,
  38                  [SDTCisVec<0>,  SDTCisVec<1>]>>;
  39
  40 // (outs Result), (ins LHS, RHS)
  41 def Neon_tst : SDNode<"AArch64ISD::NEON_TST", SDTypeProfile<1, 2,
  42                  [SDTCisVec<0>,  SDTCisSameAs<1, 2>]>>;
  43
  44 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  45                                      SDTCisVT<2, i32>]>;
  46 def Neon_sqrshlImm   : SDNode<"AArch64ISD::NEON_QSHLs", SDTARMVSH>;
  47 def Neon_uqrshlImm   : SDNode<"AArch64ISD::NEON_QSHLu", SDTARMVSH>;
  48
  49 def Neon_vdup : SDNode<"AArch64ISD::NEON_VDUP", SDTypeProfile<1, 1,
  50                        [SDTCisVec<0>]>>;
  51 def Neon_vduplane : SDNode<"AArch64ISD::NEON_VDUPLANE", SDTypeProfile<1, 2,
  52                            [SDTCisVec<0>, SDTCisVec<1>, SDTCisVT<2, i64>]>>;
  53
  54 //===----------------------------------------------------------------------===//
  55 // Multiclasses
  56 //===----------------------------------------------------------------------===//
  57
  58 multiclass NeonI_3VSame_B_sizes<bit u, bits<2> size,  bits<5> opcode,
  59                                 string asmop, SDPatternOperator opnode8B,
  60                                 SDPatternOperator opnode16B,
  61                                 bit Commutable = 0>
  62 {
  63   let isCommutable = Commutable in {
  64     def _8B :  NeonI_3VSame<0b0, u, size, opcode,
  65                (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
  66                asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
  67                [(set (v8i8 VPR64:$Rd),
  68                   (v8i8 (opnode8B (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
  69                NoItinerary>;
  70
  71     def _16B : NeonI_3VSame<0b1, u, size, opcode,
  72                (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
  73                asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
  74                [(set (v16i8 VPR128:$Rd),
  75                   (v16i8 (opnode16B (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
  76                NoItinerary>;
  77   }
  78
  79 }
  80
  81 multiclass NeonI_3VSame_HS_sizes<bit u, bits<5> opcode,
  82                                   string asmop, SDPatternOperator opnode,
  83                                   bit Commutable = 0>
  84 {
  85   let isCommutable = Commutable in {
  86     def _4H : NeonI_3VSame<0b0, u, 0b01, opcode,
  87               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
  88               asmop # "\t$Rd.4h, $Rn.4h, $Rm.4h",
  89               [(set (v4i16 VPR64:$Rd),
  90                  (v4i16 (opnode (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))))],
  91               NoItinerary>;
  92
  93     def _8H : NeonI_3VSame<0b1, u, 0b01, opcode,
  94               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
  95               asmop # "\t$Rd.8h, $Rn.8h, $Rm.8h",
  96               [(set (v8i16 VPR128:$Rd),
  97                  (v8i16 (opnode (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))))],
  98               NoItinerary>;
  99
 100     def _2S : NeonI_3VSame<0b0, u, 0b10, opcode,
 101               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 102               asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
 103               [(set (v2i32 VPR64:$Rd),
 104                  (v2i32 (opnode (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))))],
 105               NoItinerary>;
 106
 107     def _4S : NeonI_3VSame<0b1, u, 0b10, opcode,
 108               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 109               asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
 110               [(set (v4i32 VPR128:$Rd),
 111                  (v4i32 (opnode (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))))],
 112               NoItinerary>;
 113   }
 114 }
 115 multiclass NeonI_3VSame_BHS_sizes<bit u, bits<5> opcode,
 116                                   string asmop, SDPatternOperator opnode,
 117                                   bit Commutable = 0>
 118    : NeonI_3VSame_HS_sizes<u, opcode,  asmop, opnode, Commutable>
 119 {
 120   let isCommutable = Commutable in {
 121     def _8B :  NeonI_3VSame<0b0, u, 0b00, opcode,
 122                (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 123                asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
 124                [(set (v8i8 VPR64:$Rd),
 125                   (v8i8 (opnode (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
 126                NoItinerary>;
 127
 128     def _16B : NeonI_3VSame<0b1, u, 0b00, opcode,
 129                (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 130                asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
 131                [(set (v16i8 VPR128:$Rd),
 132                   (v16i8 (opnode (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
 133                NoItinerary>;
 134   }
 135 }
 136
 137 multiclass NeonI_3VSame_BHSD_sizes<bit u, bits<5> opcode,
 138                                    string asmop, SDPatternOperator opnode,
 139                                    bit Commutable = 0>
 140    : NeonI_3VSame_BHS_sizes<u, opcode,  asmop, opnode, Commutable>
 141 {
 142   let isCommutable = Commutable in {
 143     def _2D : NeonI_3VSame<0b1, u, 0b11, opcode,
 144               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 145               asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
 146               [(set (v2i64 VPR128:$Rd),
 147                  (v2i64 (opnode (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))))],
 148               NoItinerary>;
 149   }
 150 }
 151
 152 // Multiclass NeonI_3VSame_SD_sizes: Operand types are floating point types,
 153 // but Result types can be integer or floating point types.
 154 multiclass NeonI_3VSame_SD_sizes<bit u, bit size, bits<5> opcode,
 155                                  string asmop, SDPatternOperator opnode2S,
 156                                  SDPatternOperator opnode4S,
 157                                  SDPatternOperator opnode2D,
 158                                  ValueType ResTy2S, ValueType ResTy4S,
 159                                  ValueType ResTy2D, bit Commutable = 0>
 160 {
 161   let isCommutable = Commutable in {
 162     def _2S : NeonI_3VSame<0b0, u, {size, 0b0}, opcode,
 163               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 164               asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
 165               [(set (ResTy2S VPR64:$Rd),
 166                  (ResTy2S (opnode2S (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
 167               NoItinerary>;
 168
 169     def _4S : NeonI_3VSame<0b1, u, {size, 0b0}, opcode,
 170               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 171               asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
 172               [(set (ResTy4S VPR128:$Rd),
 173                  (ResTy4S (opnode4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
 174               NoItinerary>;
 175
 176     def _2D : NeonI_3VSame<0b1, u, {size, 0b1}, opcode,
 177               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 178               asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
 179               [(set (ResTy2D VPR128:$Rd),
 180                  (ResTy2D (opnode2D (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))))],
 181                NoItinerary>;
 182   }
 183 }
 184
 185 //===----------------------------------------------------------------------===//
 186 // Instruction Definitions
 187 //===----------------------------------------------------------------------===//
 188
 189 // Vector Arithmetic Instructions
 190
 191 // Vector Add (Integer and Floating-Point)
 192
 193 defm ADDvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b10000, "add", add, 1>;
 194 defm FADDvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11010, "fadd", fadd, fadd, fadd,
 195                                      v2f32, v4f32, v2f64, 1>;
 196
 197 // Vector Sub (Integer and Floating-Point)
 198
 199 defm SUBvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b10000, "sub", sub, 0>;
 200 defm FSUBvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11010, "fsub", fsub, fsub, fsub,
 201                                      v2f32, v4f32, v2f64, 0>;
 202
 203 // Vector Multiply (Integer and Floating-Point)
 204
 205 defm MULvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b10011, "mul", mul, 1>;
 206 defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul, fmul, fmul,
 207                                      v2f32, v4f32, v2f64, 1>;
 208
 209 // Vector Multiply (Polynomial)
 210
 211 defm PMULvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b10011, "pmul",
 212                                     int_arm_neon_vmulp, int_arm_neon_vmulp, 1>;
 213
 214 // Vector Multiply-accumulate and Multiply-subtract (Integer)
 215
 216 // class NeonI_3VSame_Constraint_impl: NeonI_3VSame with no data type and
 217 // two operands constraints.
 218 class NeonI_3VSame_Constraint_impl<string asmop, string asmlane,
 219   RegisterOperand VPRC, ValueType OpTy, bit q, bit u, bits<2> size,
 220   bits<5> opcode, SDPatternOperator opnode>
 221   : NeonI_3VSame<q, u, size, opcode,
 222     (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, VPRC:$Rm),
 223     asmop # "\t$Rd" # asmlane # ", $Rn" # asmlane # ", $Rm" # asmlane,
 224     [(set (OpTy VPRC:$Rd),
 225        (OpTy (opnode (OpTy VPRC:$src), (OpTy VPRC:$Rn), (OpTy VPRC:$Rm))))],
 226     NoItinerary> {
 227   let Constraints = "$src = $Rd";
 228 }
 229
 230 def Neon_mla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 231                        (add node:$Ra, (mul node:$Rn, node:$Rm))>;
 232
 233 def Neon_mls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 234                        (sub node:$Ra, (mul node:$Rn, node:$Rm))>;
 235
 236
 237 def MLAvvv_8B:  NeonI_3VSame_Constraint_impl<"mla", ".8b",  VPR64,  v8i8,
 238                                              0b0, 0b0, 0b00, 0b10010, Neon_mla>;
 239 def MLAvvv_16B: NeonI_3VSame_Constraint_impl<"mla", ".16b", VPR128, v16i8,
 240                                              0b1, 0b0, 0b00, 0b10010, Neon_mla>;
 241 def MLAvvv_4H:  NeonI_3VSame_Constraint_impl<"mla", ".4h",  VPR64,  v4i16,
 242                                              0b0, 0b0, 0b01, 0b10010, Neon_mla>;
 243 def MLAvvv_8H:  NeonI_3VSame_Constraint_impl<"mla", ".8h",  VPR128, v8i16,
 244                                              0b1, 0b0, 0b01, 0b10010, Neon_mla>;
 245 def MLAvvv_2S:  NeonI_3VSame_Constraint_impl<"mla", ".2s",  VPR64,  v2i32,
 246                                              0b0, 0b0, 0b10, 0b10010, Neon_mla>;
 247 def MLAvvv_4S:  NeonI_3VSame_Constraint_impl<"mla", ".4s",  VPR128, v4i32,
 248                                              0b1, 0b0, 0b10, 0b10010, Neon_mla>;
 249
 250 def MLSvvv_8B:  NeonI_3VSame_Constraint_impl<"mls", ".8b",  VPR64,  v8i8,
 251                                              0b0, 0b1, 0b00, 0b10010, Neon_mls>;
 252 def MLSvvv_16B: NeonI_3VSame_Constraint_impl<"mls", ".16b", VPR128, v16i8,
 253                                              0b1, 0b1, 0b00, 0b10010, Neon_mls>;
 254 def MLSvvv_4H:  NeonI_3VSame_Constraint_impl<"mls", ".4h",  VPR64,  v4i16,
 255                                              0b0, 0b1, 0b01, 0b10010, Neon_mls>;
 256 def MLSvvv_8H:  NeonI_3VSame_Constraint_impl<"mls", ".8h",  VPR128, v8i16,
 257                                              0b1, 0b1, 0b01, 0b10010, Neon_mls>;
 258 def MLSvvv_2S:  NeonI_3VSame_Constraint_impl<"mls", ".2s",  VPR64,  v2i32,
 259                                              0b0, 0b1, 0b10, 0b10010, Neon_mls>;
 260 def MLSvvv_4S:  NeonI_3VSame_Constraint_impl<"mls", ".4s",  VPR128, v4i32,
 261                                              0b1, 0b1, 0b10, 0b10010, Neon_mls>;
 262
 263 // Vector Multiply-accumulate and Multiply-subtract (Floating Point)
 264
 265 def Neon_fmla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 266                         (fadd node:$Ra, (fmul node:$Rn, node:$Rm))>;
 267
 268 def Neon_fmls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 269                         (fsub node:$Ra, (fmul node:$Rn, node:$Rm))>;
 270
 271 let Predicates = [HasNEON, UseFusedMAC] in {
 272 def FMLAvvv_2S: NeonI_3VSame_Constraint_impl<"fmla", ".2s",  VPR64,  v2f32,
 273                                              0b0, 0b0, 0b00, 0b11001, Neon_fmla>;
 274 def FMLAvvv_4S: NeonI_3VSame_Constraint_impl<"fmla", ".4s",  VPR128, v4f32,
 275                                              0b1, 0b0, 0b00, 0b11001, Neon_fmla>;
 276 def FMLAvvv_2D: NeonI_3VSame_Constraint_impl<"fmla", ".2d",  VPR128, v2f64,
 277                                              0b1, 0b0, 0b01, 0b11001, Neon_fmla>;
 278
 279 def FMLSvvv_2S: NeonI_3VSame_Constraint_impl<"fmls", ".2s",  VPR64,  v2f32,
 280                                               0b0, 0b0, 0b10, 0b11001, Neon_fmls>;
 281 def FMLSvvv_4S: NeonI_3VSame_Constraint_impl<"fmls", ".4s",  VPR128, v4f32,
 282                                              0b1, 0b0, 0b10, 0b11001, Neon_fmls>;
 283 def FMLSvvv_2D: NeonI_3VSame_Constraint_impl<"fmls", ".2d",  VPR128, v2f64,
 284                                              0b1, 0b0, 0b11, 0b11001, Neon_fmls>;
 285 }
 286
 287 // We're also allowed to match the fma instruction regardless of compile
 288 // options.
 289 def : Pat<(v2f32 (fma VPR64:$Rn, VPR64:$Rm, VPR64:$Ra)),
 290           (FMLAvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
 291 def : Pat<(v4f32 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
 292           (FMLAvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 293 def : Pat<(v2f64 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
 294           (FMLAvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 295
 296 def : Pat<(v2f32 (fma (fneg VPR64:$Rn), VPR64:$Rm, VPR64:$Ra)),
 297           (FMLSvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
 298 def : Pat<(v4f32 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
 299           (FMLSvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 300 def : Pat<(v2f64 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
 301           (FMLSvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 302
 303 // Vector Divide (Floating-Point)
 304
 305 defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv, fdiv, fdiv,
 306                                      v2f32, v4f32, v2f64, 0>;
 307
 308 // Vector Bitwise Operations
 309
 310 // Vector Bitwise AND
 311
 312 defm ANDvvv : NeonI_3VSame_B_sizes<0b0, 0b00, 0b00011, "and", and, and, 1>;
 313
 314 // Vector Bitwise Exclusive OR
 315
 316 defm EORvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b00011, "eor", xor, xor, 1>;
 317
 318 // Vector Bitwise OR
 319
 320 defm ORRvvv : NeonI_3VSame_B_sizes<0b0, 0b10, 0b00011, "orr", or, or, 1>;
 321
 322 // ORR disassembled as MOV if Vn==Vm
 323
 324 // Vector Move - register
 325 // Alias for ORR if Vn=Vm.
 326 // FIXME: This is actually the preferred syntax but TableGen can't deal with
 327 // custom printing of aliases.
 328 def : NeonInstAlias<"mov $Rd.8b, $Rn.8b",
 329                     (ORRvvv_8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rn), 0>;
 330 def : NeonInstAlias<"mov $Rd.16b, $Rn.16b",
 331                     (ORRvvv_16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rn), 0>;
 332
 333 def Neon_immAllOnes: PatLeaf<(Neon_movi (i32 timm), (i32 imm)), [{
 334   ConstantSDNode *ImmConstVal = cast<ConstantSDNode>(N->getOperand(0));
 335   ConstantSDNode *OpCmodeConstVal = cast<ConstantSDNode>(N->getOperand(1));
 336   unsigned EltBits;
 337   uint64_t EltVal = A64Imms::decodeNeonModImm(ImmConstVal->getZExtValue(),
 338     OpCmodeConstVal->getZExtValue(), EltBits);
 339   return (EltBits == 8 && EltVal == 0xff);
 340 }]>;
 341
 342 def Neon_immAllZeros: PatLeaf<(Neon_movi (i32 timm), (i32 imm)), [{
 343   ConstantSDNode *ImmConstVal = cast<ConstantSDNode>(N->getOperand(0));
 344   ConstantSDNode *OpCmodeConstVal = cast<ConstantSDNode>(N->getOperand(1));
 345   unsigned EltBits;
 346   uint64_t EltVal = A64Imms::decodeNeonModImm(ImmConstVal->getZExtValue(),
 347     OpCmodeConstVal->getZExtValue(), EltBits);
 348   return (EltBits == 8 && EltVal == 0x0);
 349 }]>;
 350
 351
 352 def Neon_not8B  : PatFrag<(ops node:$in),
 353                           (xor node:$in, (bitconvert (v8i8 Neon_immAllOnes)))>;
 354 def Neon_not16B : PatFrag<(ops node:$in),
 355                           (xor node:$in, (bitconvert (v16i8 Neon_immAllOnes)))>;
 356
 357 def Neon_orn8B : PatFrag<(ops node:$Rn, node:$Rm),
 358                          (or node:$Rn, (Neon_not8B node:$Rm))>;
 359
 360 def Neon_orn16B : PatFrag<(ops node:$Rn, node:$Rm),
 361                           (or node:$Rn, (Neon_not16B node:$Rm))>;
 362
 363 def Neon_bic8B : PatFrag<(ops node:$Rn, node:$Rm),
 364                          (and node:$Rn, (Neon_not8B node:$Rm))>;
 365
 366 def Neon_bic16B : PatFrag<(ops node:$Rn, node:$Rm),
 367                           (and node:$Rn, (Neon_not16B node:$Rm))>;
 368
 369
 370 // Vector Bitwise OR NOT - register
 371
 372 defm ORNvvv : NeonI_3VSame_B_sizes<0b0, 0b11, 0b00011, "orn",
 373                                    Neon_orn8B, Neon_orn16B, 0>;
 374
 375 // Vector Bitwise Bit Clear (AND NOT) - register
 376
 377 defm BICvvv : NeonI_3VSame_B_sizes<0b0, 0b01, 0b00011, "bic",
 378                                    Neon_bic8B, Neon_bic16B, 0>;
 379
 380 multiclass Neon_bitwise2V_patterns<SDPatternOperator opnode8B,
 381                                    SDPatternOperator opnode16B,
 382                                    Instruction INST8B,
 383                                    Instruction INST16B> {
 384   def : Pat<(v2i32 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 385             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 386   def : Pat<(v4i16 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 387             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 388   def : Pat<(v1i64 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 389             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 390   def : Pat<(v4i32 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 391             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 392   def : Pat<(v8i16 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 393             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 394   def : Pat<(v2i64 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 395             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 396 }
 397
 398 // Additional patterns for bitwise instructions AND, EOR, ORR, BIC, ORN
 399 defm : Neon_bitwise2V_patterns<and, and, ANDvvv_8B, ANDvvv_16B>;
 400 defm : Neon_bitwise2V_patterns<or,  or,  ORRvvv_8B, ORRvvv_16B>;
 401 defm : Neon_bitwise2V_patterns<xor, xor, EORvvv_8B, EORvvv_16B>;
 402 defm : Neon_bitwise2V_patterns<Neon_bic8B, Neon_bic16B, BICvvv_8B, BICvvv_16B>;
 403 defm : Neon_bitwise2V_patterns<Neon_orn8B, Neon_orn16B, ORNvvv_8B, ORNvvv_16B>;
 404
 405 //   Vector Bitwise Select
 406 def BSLvvv_8B  : NeonI_3VSame_Constraint_impl<"bsl", ".8b",  VPR64, v8i8,
 407                                               0b0, 0b1, 0b01, 0b00011, Neon_bsl>;
 408
 409 def BSLvvv_16B : NeonI_3VSame_Constraint_impl<"bsl", ".16b", VPR128, v16i8,
 410                                               0b1, 0b1, 0b01, 0b00011, Neon_bsl>;
 411
 412 multiclass Neon_bitwise3V_patterns<SDPatternOperator opnode,
 413                                    Instruction INST8B,
 414                                    Instruction INST16B> {
 415   // Disassociate type from instruction definition
 416   def : Pat<(v2i32 (opnode VPR64:$src,VPR64:$Rn, VPR64:$Rm)),
 417             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 418   def : Pat<(v4i16 (opnode VPR64:$src, VPR64:$Rn, VPR64:$Rm)),
 419             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 420   def : Pat<(v1i64 (opnode VPR64:$src, VPR64:$Rn, VPR64:$Rm)),
 421             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 422   def : Pat<(v4i32 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
 423             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 424   def : Pat<(v8i16 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
 425             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 426   def : Pat<(v2i64 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
 427             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 428
 429   // Allow to match BSL instruction pattern with non-constant operand
 430   def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
 431                     (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 432           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 433   def : Pat<(v4i16 (or (and VPR64:$Rn, VPR64:$Rd),
 434                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 435           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 436   def : Pat<(v2i32 (or (and VPR64:$Rn, VPR64:$Rd),
 437                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 438           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 439   def : Pat<(v1i64 (or (and VPR64:$Rn, VPR64:$Rd),
 440                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 441           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 442   def : Pat<(v16i8 (or (and VPR128:$Rn, VPR128:$Rd),
 443                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 444           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 445   def : Pat<(v8i16 (or (and VPR128:$Rn, VPR128:$Rd),
 446                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 447           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 448   def : Pat<(v4i32 (or (and VPR128:$Rn, VPR128:$Rd),
 449                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 450           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 451   def : Pat<(v2i64 (or (and VPR128:$Rn, VPR128:$Rd),
 452                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 453           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 454
 455   // Allow to match llvm.arm.* intrinsics.
 456   def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 VPR64:$src),
 457                     (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
 458             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 459   def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 VPR64:$src),
 460                     (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
 461             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 462   def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 VPR64:$src),
 463                     (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
 464             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 465   def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 VPR64:$src),
 466                     (v1i64 VPR64:$Rn), (v1i64 VPR64:$Rm))),
 467             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 468   def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 VPR64:$src),
 469                     (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
 470             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 471   def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 VPR128:$src),
 472                     (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
 473             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 474   def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 VPR128:$src),
 475                     (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
 476             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 477   def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 VPR128:$src),
 478                     (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
 479             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 480   def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 VPR128:$src),
 481                     (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
 482             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 483   def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 VPR128:$src),
 484                     (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
 485             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 486   def : Pat<(v2f64 (int_arm_neon_vbsl (v2f64 VPR128:$src),
 487                     (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
 488             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 489 }
 490
 491 // Additional patterns for bitwise instruction BSL
 492 defm: Neon_bitwise3V_patterns<Neon_bsl, BSLvvv_8B, BSLvvv_16B>;
 493
 494 def Neon_NoBSLop : PatFrag<(ops node:$src, node:$Rn, node:$Rm),
 495                            (Neon_bsl node:$src, node:$Rn, node:$Rm),
 496                            [{ (void)N; return false; }]>;
 497
 498 // Vector Bitwise Insert if True
 499
 500 def BITvvv_8B  : NeonI_3VSame_Constraint_impl<"bit", ".8b", VPR64,   v8i8,
 501                    0b0, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
 502 def BITvvv_16B : NeonI_3VSame_Constraint_impl<"bit", ".16b", VPR128, v16i8,
 503                    0b1, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
 504
 505 // Vector Bitwise Insert if False
 506
 507 def BIFvvv_8B  : NeonI_3VSame_Constraint_impl<"bif", ".8b", VPR64,  v8i8,
 508                                 0b0, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
 509 def BIFvvv_16B : NeonI_3VSame_Constraint_impl<"bif", ".16b", VPR128, v16i8,
 510                                 0b1, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
 511
 512 // Vector Absolute Difference and Accumulate (Signed, Unsigned)
 513
 514 def Neon_uaba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 515                        (add node:$Ra, (int_arm_neon_vabdu node:$Rn, node:$Rm))>;
 516 def Neon_saba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 517                        (add node:$Ra, (int_arm_neon_vabds node:$Rn, node:$Rm))>;
 518
 519 // Vector Absolute Difference and Accumulate (Unsigned)
 520 def UABAvvv_8B :  NeonI_3VSame_Constraint_impl<"uaba", ".8b",  VPR64,  v8i8,
 521                     0b0, 0b1, 0b00, 0b01111, Neon_uaba>;
 522 def UABAvvv_16B : NeonI_3VSame_Constraint_impl<"uaba", ".16b", VPR128, v16i8,
 523                     0b1, 0b1, 0b00, 0b01111, Neon_uaba>;
 524 def UABAvvv_4H :  NeonI_3VSame_Constraint_impl<"uaba", ".4h",  VPR64,  v4i16,
 525                     0b0, 0b1, 0b01, 0b01111, Neon_uaba>;
 526 def UABAvvv_8H :  NeonI_3VSame_Constraint_impl<"uaba", ".8h",  VPR128, v8i16,
 527                     0b1, 0b1, 0b01, 0b01111, Neon_uaba>;
 528 def UABAvvv_2S :  NeonI_3VSame_Constraint_impl<"uaba", ".2s",  VPR64,  v2i32,
 529                     0b0, 0b1, 0b10, 0b01111, Neon_uaba>;
 530 def UABAvvv_4S :  NeonI_3VSame_Constraint_impl<"uaba", ".4s",  VPR128, v4i32,
 531                     0b1, 0b1, 0b10, 0b01111, Neon_uaba>;
 532
 533 // Vector Absolute Difference and Accumulate (Signed)
 534 def SABAvvv_8B :  NeonI_3VSame_Constraint_impl<"saba", ".8b",  VPR64,  v8i8,
 535                     0b0, 0b0, 0b00, 0b01111, Neon_saba>;
 536 def SABAvvv_16B : NeonI_3VSame_Constraint_impl<"saba", ".16b", VPR128, v16i8,
 537                     0b1, 0b0, 0b00, 0b01111, Neon_saba>;
 538 def SABAvvv_4H :  NeonI_3VSame_Constraint_impl<"saba", ".4h",  VPR64,  v4i16,
 539                     0b0, 0b0, 0b01, 0b01111, Neon_saba>;
 540 def SABAvvv_8H :  NeonI_3VSame_Constraint_impl<"saba", ".8h",  VPR128, v8i16,
 541                     0b1, 0b0, 0b01, 0b01111, Neon_saba>;
 542 def SABAvvv_2S :  NeonI_3VSame_Constraint_impl<"saba", ".2s",  VPR64,  v2i32,
 543                     0b0, 0b0, 0b10, 0b01111, Neon_saba>;
 544 def SABAvvv_4S :  NeonI_3VSame_Constraint_impl<"saba", ".4s",  VPR128, v4i32,
 545                     0b1, 0b0, 0b10, 0b01111, Neon_saba>;
 546
 547
 548 // Vector Absolute Difference (Signed, Unsigned)
 549 defm UABDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01110, "uabd", int_arm_neon_vabdu, 0>;
 550 defm SABDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01110, "sabd", int_arm_neon_vabds, 0>;
 551
 552 // Vector Absolute Difference (Floating Point)
 553 defm FABDvvv: NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11010, "fabd",
 554                                     int_arm_neon_vabds, int_arm_neon_vabds,
 555                                     int_arm_neon_vabds, v2f32, v4f32, v2f64, 0>;
 556
 557 // Vector Reciprocal Step (Floating Point)
 558 defm FRECPSvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11111, "frecps",
 559                                        int_arm_neon_vrecps, int_arm_neon_vrecps,
 560                                        int_arm_neon_vrecps,
 561                                        v2f32, v4f32, v2f64, 0>;
 562
 563 // Vector Reciprocal Square Root Step (Floating Point)
 564 defm FRSQRTSvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11111, "frsqrts",
 565                                         int_arm_neon_vrsqrts,
 566                                         int_arm_neon_vrsqrts,
 567                                         int_arm_neon_vrsqrts,
 568                                         v2f32, v4f32, v2f64, 0>;
 569
 570 // Vector Comparisons
 571
 572 def Neon_cmeq : PatFrag<(ops node:$lhs, node:$rhs),
 573                         (Neon_cmp node:$lhs, node:$rhs, SETEQ)>;
 574 def Neon_cmphs : PatFrag<(ops node:$lhs, node:$rhs),
 575                          (Neon_cmp node:$lhs, node:$rhs, SETUGE)>;
 576 def Neon_cmge : PatFrag<(ops node:$lhs, node:$rhs),
 577                         (Neon_cmp node:$lhs, node:$rhs, SETGE)>;
 578 def Neon_cmhi : PatFrag<(ops node:$lhs, node:$rhs),
 579                         (Neon_cmp node:$lhs, node:$rhs, SETUGT)>;
 580 def Neon_cmgt : PatFrag<(ops node:$lhs, node:$rhs),
 581                         (Neon_cmp node:$lhs, node:$rhs, SETGT)>;
 582
 583 // NeonI_compare_aliases class: swaps register operands to implement
 584 // comparison aliases, e.g., CMLE is alias for CMGE with operands reversed.
 585 class NeonI_compare_aliases<string asmop, string asmlane,
 586                             Instruction inst, RegisterOperand VPRC>
 587   : NeonInstAlias<asmop # "\t$Rd" # asmlane #", $Rn" # asmlane #
 588                     ", $Rm" # asmlane,
 589                   (inst VPRC:$Rd, VPRC:$Rm, VPRC:$Rn), 0b0>;
 590
 591 // Vector Comparisons (Integer)
 592
 593 // Vector Compare Mask Equal (Integer)
 594 let isCommutable =1 in {
 595 defm CMEQvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10001, "cmeq", Neon_cmeq, 0>;
 596 }
 597
 598 // Vector Compare Mask Higher or Same (Unsigned Integer)
 599 defm CMHSvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00111, "cmhs", Neon_cmphs, 0>;
 600
 601 // Vector Compare Mask Greater Than or Equal (Integer)
 602 defm CMGEvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00111, "cmge", Neon_cmge, 0>;
 603
 604 // Vector Compare Mask Higher (Unsigned Integer)
 605 defm CMHIvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00110, "cmhi", Neon_cmhi, 0>;
 606
 607 // Vector Compare Mask Greater Than (Integer)
 608 defm CMGTvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00110, "cmgt", Neon_cmgt, 0>;
 609
 610 // Vector Compare Mask Bitwise Test (Integer)
 611 defm CMTSTvvv:  NeonI_3VSame_BHSD_sizes<0b0, 0b10001, "cmtst", Neon_tst, 0>;
 612
 613 // Vector Compare Mask Less or Same (Unsigned Integer)
 614 // CMLS is alias for CMHS with operands reversed.
 615 def CMLSvvv_8B  : NeonI_compare_aliases<"cmls", ".8b",  CMHSvvv_8B,  VPR64>;
 616 def CMLSvvv_16B : NeonI_compare_aliases<"cmls", ".16b", CMHSvvv_16B, VPR128>;
 617 def CMLSvvv_4H  : NeonI_compare_aliases<"cmls", ".4h",  CMHSvvv_4H,  VPR64>;
 618 def CMLSvvv_8H  : NeonI_compare_aliases<"cmls", ".8h",  CMHSvvv_8H,  VPR128>;
 619 def CMLSvvv_2S  : NeonI_compare_aliases<"cmls", ".2s",  CMHSvvv_2S,  VPR64>;
 620 def CMLSvvv_4S  : NeonI_compare_aliases<"cmls", ".4s",  CMHSvvv_4S,  VPR128>;
 621 def CMLSvvv_2D  : NeonI_compare_aliases<"cmls", ".2d",  CMHSvvv_2D,  VPR128>;
 622
 623 // Vector Compare Mask Less Than or Equal (Integer)
 624 // CMLE is alias for CMGE with operands reversed.
 625 def CMLEvvv_8B  : NeonI_compare_aliases<"cmle", ".8b",  CMGEvvv_8B,  VPR64>;
 626 def CMLEvvv_16B : NeonI_compare_aliases<"cmle", ".16b", CMGEvvv_16B, VPR128>;
 627 def CMLEvvv_4H  : NeonI_compare_aliases<"cmle", ".4h",  CMGEvvv_4H,  VPR64>;
 628 def CMLEvvv_8H  : NeonI_compare_aliases<"cmle", ".8h",  CMGEvvv_8H,  VPR128>;
 629 def CMLEvvv_2S  : NeonI_compare_aliases<"cmle", ".2s",  CMGEvvv_2S,  VPR64>;
 630 def CMLEvvv_4S  : NeonI_compare_aliases<"cmle", ".4s",  CMGEvvv_4S,  VPR128>;
 631 def CMLEvvv_2D  : NeonI_compare_aliases<"cmle", ".2d",  CMGEvvv_2D,  VPR128>;
 632
 633 // Vector Compare Mask Lower (Unsigned Integer)
 634 // CMLO is alias for CMHI with operands reversed.
 635 def CMLOvvv_8B  : NeonI_compare_aliases<"cmlo", ".8b",  CMHIvvv_8B,  VPR64>;
 636 def CMLOvvv_16B : NeonI_compare_aliases<"cmlo", ".16b", CMHIvvv_16B, VPR128>;
 637 def CMLOvvv_4H  : NeonI_compare_aliases<"cmlo", ".4h",  CMHIvvv_4H,  VPR64>;
 638 def CMLOvvv_8H  : NeonI_compare_aliases<"cmlo", ".8h",  CMHIvvv_8H,  VPR128>;
 639 def CMLOvvv_2S  : NeonI_compare_aliases<"cmlo", ".2s",  CMHIvvv_2S,  VPR64>;
 640 def CMLOvvv_4S  : NeonI_compare_aliases<"cmlo", ".4s",  CMHIvvv_4S,  VPR128>;
 641 def CMLOvvv_2D  : NeonI_compare_aliases<"cmlo", ".2d",  CMHIvvv_2D,  VPR128>;
 642
 643 // Vector Compare Mask Less Than (Integer)
 644 // CMLT is alias for CMGT with operands reversed.
 645 def CMLTvvv_8B  : NeonI_compare_aliases<"cmlt", ".8b",  CMGTvvv_8B,  VPR64>;
 646 def CMLTvvv_16B : NeonI_compare_aliases<"cmlt", ".16b", CMGTvvv_16B, VPR128>;
 647 def CMLTvvv_4H  : NeonI_compare_aliases<"cmlt", ".4h",  CMGTvvv_4H,  VPR64>;
 648 def CMLTvvv_8H  : NeonI_compare_aliases<"cmlt", ".8h",  CMGTvvv_8H,  VPR128>;
 649 def CMLTvvv_2S  : NeonI_compare_aliases<"cmlt", ".2s",  CMGTvvv_2S,  VPR64>;
 650 def CMLTvvv_4S  : NeonI_compare_aliases<"cmlt", ".4s",  CMGTvvv_4S,  VPR128>;
 651 def CMLTvvv_2D  : NeonI_compare_aliases<"cmlt", ".2d",  CMGTvvv_2D,  VPR128>;
 652
 653
 654 def neon_uimm0_asmoperand : AsmOperandClass
 655 {
 656   let Name = "UImm0";
 657   let PredicateMethod = "isUImm<0>";
 658   let RenderMethod = "addImmOperands";
 659 }
 660
 661 def neon_uimm0 : Operand<i32>, ImmLeaf<i32, [{return Imm == 0;}]> {
 662   let ParserMatchClass = neon_uimm0_asmoperand;
 663   let PrintMethod = "printNeonUImm0Operand";
 664
 665 }
 666
 667 multiclass NeonI_cmpz_sizes<bit u, bits<5> opcode, string asmop, CondCode CC>
 668 {
 669   def _8B :  NeonI_2VMisc<0b0, u, 0b00, opcode,
 670              (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 671              asmop # "\t$Rd.8b, $Rn.8b, $Imm",
 672              [(set (v8i8 VPR64:$Rd),
 673                 (v8i8 (Neon_cmpz (v8i8 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 674              NoItinerary>;
 675
 676   def _16B : NeonI_2VMisc<0b1, u, 0b00, opcode,
 677              (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 678              asmop # "\t$Rd.16b, $Rn.16b, $Imm",
 679              [(set (v16i8 VPR128:$Rd),
 680                 (v16i8 (Neon_cmpz (v16i8 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 681              NoItinerary>;
 682
 683   def _4H : NeonI_2VMisc<0b0, u, 0b01, opcode,
 684             (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 685             asmop # "\t$Rd.4h, $Rn.4h, $Imm",
 686             [(set (v4i16 VPR64:$Rd),
 687                (v4i16 (Neon_cmpz (v4i16 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 688             NoItinerary>;
 689
 690   def _8H : NeonI_2VMisc<0b1, u, 0b01, opcode,
 691             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 692             asmop # "\t$Rd.8h, $Rn.8h, $Imm",
 693             [(set (v8i16 VPR128:$Rd),
 694                (v8i16 (Neon_cmpz (v8i16 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 695             NoItinerary>;
 696
 697   def _2S : NeonI_2VMisc<0b0, u, 0b10, opcode,
 698             (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 699             asmop # "\t$Rd.2s, $Rn.2s, $Imm",
 700             [(set (v2i32 VPR64:$Rd),
 701                (v2i32 (Neon_cmpz (v2i32 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 702             NoItinerary>;
 703
 704   def _4S : NeonI_2VMisc<0b1, u, 0b10, opcode,
 705             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 706             asmop # "\t$Rd.4s, $Rn.4s, $Imm",
 707             [(set (v4i32 VPR128:$Rd),
 708                (v4i32 (Neon_cmpz (v4i32 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 709             NoItinerary>;
 710
 711   def _2D : NeonI_2VMisc<0b1, u, 0b11, opcode,
 712             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 713             asmop # "\t$Rd.2d, $Rn.2d, $Imm",
 714             [(set (v2i64 VPR128:$Rd),
 715                (v2i64 (Neon_cmpz (v2i64 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 716             NoItinerary>;
 717 }
 718
 719 // Vector Compare Mask Equal to Zero (Integer)
 720 defm CMEQvvi : NeonI_cmpz_sizes<0b0, 0b01001, "cmeq", SETEQ>;
 721
 722 // Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
 723 defm CMGEvvi : NeonI_cmpz_sizes<0b1, 0b01000, "cmge", SETGE>;
 724
 725 // Vector Compare Mask Greater Than Zero (Signed Integer)
 726 defm CMGTvvi : NeonI_cmpz_sizes<0b0, 0b01000, "cmgt", SETGT>;
 727
 728 // Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
 729 defm CMLEvvi : NeonI_cmpz_sizes<0b1, 0b01001, "cmle", SETLE>;
 730
 731 // Vector Compare Mask Less Than Zero (Signed Integer)
 732 defm CMLTvvi : NeonI_cmpz_sizes<0b0, 0b01010, "cmlt", SETLT>;
 733
 734 // Vector Comparisons (Floating Point)
 735
 736 // Vector Compare Mask Equal (Floating Point)
 737 let isCommutable =1 in {
 738 defm FCMEQvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11100, "fcmeq", Neon_cmeq,
 739                                       Neon_cmeq, Neon_cmeq,
 740                                       v2i32, v4i32, v2i64, 0>;
 741 }
 742
 743 // Vector Compare Mask Greater Than Or Equal (Floating Point)
 744 defm FCMGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11100, "fcmge", Neon_cmge,
 745                                       Neon_cmge, Neon_cmge,
 746                                       v2i32, v4i32, v2i64, 0>;
 747
 748 // Vector Compare Mask Greater Than (Floating Point)
 749 defm FCMGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11100, "fcmgt", Neon_cmgt,
 750                                       Neon_cmgt, Neon_cmgt,
 751                                       v2i32, v4i32, v2i64, 0>;
 752
 753 // Vector Compare Mask Less Than Or Equal (Floating Point)
 754 // FCMLE is alias for FCMGE with operands reversed.
 755 def FCMLEvvv_2S  : NeonI_compare_aliases<"fcmle", ".2s",  FCMGEvvv_2S,  VPR64>;
 756 def FCMLEvvv_4S  : NeonI_compare_aliases<"fcmle", ".4s",  FCMGEvvv_4S,  VPR128>;
 757 def FCMLEvvv_2D  : NeonI_compare_aliases<"fcmle", ".2d",  FCMGEvvv_2D,  VPR128>;
 758
 759 // Vector Compare Mask Less Than (Floating Point)
 760 // FCMLT is alias for FCMGT with operands reversed.
 761 def FCMLTvvv_2S  : NeonI_compare_aliases<"fcmlt", ".2s",  FCMGTvvv_2S,  VPR64>;
 762 def FCMLTvvv_4S  : NeonI_compare_aliases<"fcmlt", ".4s",  FCMGTvvv_4S,  VPR128>;
 763 def FCMLTvvv_2D  : NeonI_compare_aliases<"fcmlt", ".2d",  FCMGTvvv_2D,  VPR128>;
 764
 765
 766 multiclass NeonI_fpcmpz_sizes<bit u, bit size, bits<5> opcode,
 767                               string asmop, CondCode CC>
 768 {
 769   def _2S : NeonI_2VMisc<0b0, u, {size, 0b0}, opcode,
 770             (outs VPR64:$Rd), (ins VPR64:$Rn, fpz32:$FPImm),
 771             asmop # "\t$Rd.2s, $Rn.2s, $FPImm",
 772             [(set (v2i32 VPR64:$Rd),
 773                (v2i32 (Neon_cmpz (v2f32 VPR64:$Rn), (f32 fpimm:$FPImm), CC)))],
 774             NoItinerary>;
 775
 776   def _4S : NeonI_2VMisc<0b1, u, {size, 0b0}, opcode,
 777             (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
 778             asmop # "\t$Rd.4s, $Rn.4s, $FPImm",
 779             [(set (v4i32 VPR128:$Rd),
 780                (v4i32 (Neon_cmpz (v4f32 VPR128:$Rn), (f32 fpimm:$FPImm), CC)))],
 781             NoItinerary>;
 782
 783   def _2D : NeonI_2VMisc<0b1, u, {size, 0b1}, opcode,
 784             (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
 785             asmop # "\t$Rd.2d, $Rn.2d, $FPImm",
 786             [(set (v2i64 VPR128:$Rd),
 787                (v2i64 (Neon_cmpz (v2f64 VPR128:$Rn), (f32 fpimm:$FPImm), CC)))],
 788             NoItinerary>;
 789 }
 790
 791 // Vector Compare Mask Equal to Zero (Floating Point)
 792 defm FCMEQvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01101, "fcmeq", SETEQ>;
 793
 794 // Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
 795 defm FCMGEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01100, "fcmge", SETGE>;
 796
 797 // Vector Compare Mask Greater Than Zero (Floating Point)
 798 defm FCMGTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01100, "fcmgt", SETGT>;
 799
 800 // Vector Compare Mask Less Than or Equal To Zero (Floating Point)
 801 defm FCMLEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01101, "fcmle", SETLE>;
 802
 803 // Vector Compare Mask Less Than Zero (Floating Point)
 804 defm FCMLTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01110, "fcmlt", SETLT>;
 805
 806 // Vector Absolute Comparisons (Floating Point)
 807
 808 // Vector Absolute Compare Mask Greater Than Or Equal (Floating Point)
 809 defm FACGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11101, "facge",
 810                                       int_arm_neon_vacged, int_arm_neon_vacgeq,
 811                                       int_aarch64_neon_vacgeq,
 812                                       v2i32, v4i32, v2i64, 0>;
 813
 814 // Vector Absolute Compare Mask Greater Than (Floating Point)
 815 defm FACGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11101, "facgt",
 816                                       int_arm_neon_vacgtd, int_arm_neon_vacgtq,
 817                                       int_aarch64_neon_vacgtq,
 818                                       v2i32, v4i32, v2i64, 0>;
 819
 820 // Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
 821 // FACLE is alias for FACGE with operands reversed.
 822 def FACLEvvv_2S  : NeonI_compare_aliases<"facle", ".2s",  FACGEvvv_2S,  VPR64>;
 823 def FACLEvvv_4S  : NeonI_compare_aliases<"facle", ".4s",  FACGEvvv_4S,  VPR128>;
 824 def FACLEvvv_2D  : NeonI_compare_aliases<"facle", ".2d",  FACGEvvv_2D,  VPR128>;
 825
 826 // Vector Absolute Compare Mask Less Than (Floating Point)
 827 // FACLT is alias for FACGT with operands reversed.
 828 def FACLTvvv_2S  : NeonI_compare_aliases<"faclt", ".2s",  FACGTvvv_2S,  VPR64>;
 829 def FACLTvvv_4S  : NeonI_compare_aliases<"faclt", ".4s",  FACGTvvv_4S,  VPR128>;
 830 def FACLTvvv_2D  : NeonI_compare_aliases<"faclt", ".2d",  FACGTvvv_2D,  VPR128>;
 831
 832 // Vector halving add (Integer Signed, Unsigned)
 833 defm SHADDvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00000, "shadd",
 834                                         int_arm_neon_vhadds, 1>;
 835 defm UHADDvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00000, "uhadd",
 836                                         int_arm_neon_vhaddu, 1>;
 837
 838 // Vector halving sub (Integer Signed, Unsigned)
 839 defm SHSUBvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00100, "shsub",
 840                                         int_arm_neon_vhsubs, 0>;
 841 defm UHSUBvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00100, "uhsub",
 842                                         int_arm_neon_vhsubu, 0>;
 843
 844 // Vector rouding halving add (Integer Signed, Unsigned)
 845 defm SRHADDvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00010, "srhadd",
 846                                          int_arm_neon_vrhadds, 1>;
 847 defm URHADDvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00010, "urhadd",
 848                                          int_arm_neon_vrhaddu, 1>;
 849
 850 // Vector Saturating add (Integer Signed, Unsigned)
 851 defm SQADDvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b00001, "sqadd",
 852                    int_arm_neon_vqadds, 1>;
 853 defm UQADDvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b00001, "uqadd",
 854                    int_arm_neon_vqaddu, 1>;
 855
 856 // Vector Saturating sub (Integer Signed, Unsigned)
 857 defm SQSUBvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b00101, "sqsub",
 858                    int_arm_neon_vqsubs, 1>;
 859 defm UQSUBvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b00101, "uqsub",
 860                    int_arm_neon_vqsubu, 1>;
 861
 862 // Vector Shift Left (Signed and Unsigned Integer)
 863 defm SSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01000, "sshl",
 864                  int_arm_neon_vshifts, 1>;
 865 defm USHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01000, "ushl",
 866                  int_arm_neon_vshiftu, 1>;
 867
 868 // Vector Saturating Shift Left (Signed and Unsigned Integer)
 869 defm SQSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01001, "sqshl",
 870                   int_arm_neon_vqshifts, 1>;
 871 defm UQSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01001, "uqshl",
 872                   int_arm_neon_vqshiftu, 1>;
 873
 874 // Vector Rouding Shift Left (Signed and Unsigned Integer)
 875 defm SRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01010, "srshl",
 876                   int_arm_neon_vrshifts, 1>;
 877 defm URSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01010, "urshl",
 878                   int_arm_neon_vrshiftu, 1>;
 879
 880 // Vector Saturating Rouding Shift Left (Signed and Unsigned Integer)
 881 defm SQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01011, "sqrshl",
 882                    int_arm_neon_vqrshifts, 1>;
 883 defm UQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01011, "uqrshl",
 884                    int_arm_neon_vqrshiftu, 1>;
 885
 886 // Vector Maximum (Signed and Unsigned Integer)
 887 defm SMAXvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01100, "smax", int_arm_neon_vmaxs, 1>;
 888 defm UMAXvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01100, "umax", int_arm_neon_vmaxu, 1>;
 889
 890 // Vector Minimum (Signed and Unsigned Integer)
 891 defm SMINvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01101, "smin", int_arm_neon_vmins, 1>;
 892 defm UMINvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01101, "umin", int_arm_neon_vminu, 1>;
 893
 894 // Vector Maximum (Floating Point)
 895 defm FMAXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11110, "fmax",
 896                                      int_arm_neon_vmaxs, int_arm_neon_vmaxs,
 897                                      int_arm_neon_vmaxs, v2f32, v4f32, v2f64, 1>;
 898
 899 // Vector Minimum (Floating Point)
 900 defm FMINvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11110, "fmin",
 901                                      int_arm_neon_vmins, int_arm_neon_vmins,
 902                                      int_arm_neon_vmins, v2f32, v4f32, v2f64, 1>;
 903
 904 // Vector maxNum (Floating Point) -  prefer a number over a quiet NaN)
 905 defm FMAXNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11000, "fmaxnm",
 906                                        int_aarch64_neon_vmaxnm,
 907                                        int_aarch64_neon_vmaxnm,
 908                                        int_aarch64_neon_vmaxnm,
 909                                        v2f32, v4f32, v2f64, 1>;
 910
 911 // Vector minNum (Floating Point) - prefer a number over a quiet NaN)
 912 defm FMINNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11000, "fminnm",
 913                                        int_aarch64_neon_vminnm,
 914                                        int_aarch64_neon_vminnm,
 915                                        int_aarch64_neon_vminnm,
 916                                        v2f32, v4f32, v2f64, 1>;
 917
 918 // Vector Maximum Pairwise (Signed and Unsigned Integer)
 919 defm SMAXPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10100, "smaxp", int_arm_neon_vpmaxs, 1>;
 920 defm UMAXPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10100, "umaxp", int_arm_neon_vpmaxu, 1>;
 921
 922 // Vector Minimum Pairwise (Signed and Unsigned Integer)
 923 defm SMINPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10101, "sminp", int_arm_neon_vpmins, 1>;
 924 defm UMINPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10101, "uminp", int_arm_neon_vpminu, 1>;
 925
 926 // Vector Maximum Pairwise (Floating Point)
 927 defm FMAXPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11110, "fmaxp",
 928                                      int_arm_neon_vpmaxs, int_arm_neon_vpmaxs,
 929                                      int_arm_neon_vpmaxs, v2f32, v4f32, v2f64, 1>;
 930
 931 // Vector Minimum Pairwise (Floating Point)
 932 defm FMINPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11110, "fminp",
 933                                      int_arm_neon_vpmins, int_arm_neon_vpmins,
 934                                      int_arm_neon_vpmins, v2f32, v4f32, v2f64, 1>;
 935
 936 // Vector maxNum Pairwise (Floating Point) -  prefer a number over a quiet NaN)
 937 defm FMAXNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11000, "fmaxnmp",
 938                                        int_aarch64_neon_vpmaxnm,
 939                                        int_aarch64_neon_vpmaxnm,
 940                                        int_aarch64_neon_vpmaxnm,
 941                                        v2f32, v4f32, v2f64, 1>;
 942
 943 // Vector minNum Pairwise (Floating Point) -  prefer a number over a quiet NaN)
 944 defm FMINNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11000, "fminnmp",
 945                                        int_aarch64_neon_vpminnm,
 946                                        int_aarch64_neon_vpminnm,
 947                                        int_aarch64_neon_vpminnm,
 948                                        v2f32, v4f32, v2f64, 1>;
 949
 950 // Vector Addition Pairwise (Integer)
 951 defm ADDP : NeonI_3VSame_BHSD_sizes<0b0, 0b10111, "addp", int_arm_neon_vpadd, 1>;
 952
 953 // Vector Addition Pairwise (Floating Point)
 954 defm FADDP : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11010, "faddp",
 955                                        int_arm_neon_vpadd,
 956                                        int_arm_neon_vpadd,
 957                                        int_arm_neon_vpadd,
 958                                        v2f32, v4f32, v2f64, 1>;
 959
 960 // Vector Saturating Doubling Multiply High
 961 defm SQDMULHvvv : NeonI_3VSame_HS_sizes<0b0, 0b10110, "sqdmulh",
 962                     int_arm_neon_vqdmulh, 1>;
 963
 964 // Vector Saturating Rouding Doubling Multiply High
 965 defm SQRDMULHvvv : NeonI_3VSame_HS_sizes<0b1, 0b10110, "sqrdmulh",
 966                      int_arm_neon_vqrdmulh, 1>;
 967
 968 // Vector Multiply Extended (Floating Point)
 969 defm FMULXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11011, "fmulx",
 970                                       int_aarch64_neon_vmulx,
 971                                       int_aarch64_neon_vmulx,
 972                                       int_aarch64_neon_vmulx,
 973                                       v2f32, v4f32, v2f64, 1>;
 974
 975 // Vector Immediate Instructions
 976
 977 multiclass neon_mov_imm_shift_asmoperands<string PREFIX>
 978 {
 979   def _asmoperand : AsmOperandClass
 980     {
 981       let Name = "NeonMovImmShift" # PREFIX;
 982       let RenderMethod = "addNeonMovImmShift" # PREFIX # "Operands";
 983       let PredicateMethod = "isNeonMovImmShift" # PREFIX;
 984     }
 985 }
 986
 987 // Definition of vector immediates shift operands
 988
 989 // The selectable use-cases extract the shift operation
 990 // information from the OpCmode fields encoded in the immediate.
 991 def neon_mod_shift_imm_XFORM : SDNodeXForm<imm, [{
 992   uint64_t OpCmode = N->getZExtValue();
 993   unsigned ShiftImm;
 994   unsigned ShiftOnesIn;
 995   unsigned HasShift =
 996     A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
 997   if (!HasShift) return SDValue();
 998   return CurDAG->getTargetConstant(ShiftImm, MVT::i32);
 999 }]>;
1000
1001 // Vector immediates shift operands which accept LSL and MSL
1002 // shift operators with shift value in the range of 0, 8, 16, 24 (LSL),
1003 // or 0, 8 (LSLH) or 8, 16 (MSL).
1004 defm neon_mov_imm_LSL : neon_mov_imm_shift_asmoperands<"LSL">;
1005 defm neon_mov_imm_MSL : neon_mov_imm_shift_asmoperands<"MSL">;
1006 // LSLH restricts shift amount to  0, 8 out of 0, 8, 16, 24
1007 defm neon_mov_imm_LSLH : neon_mov_imm_shift_asmoperands<"LSLH">;
1008
1009 multiclass neon_mov_imm_shift_operands<string PREFIX,
1010                                        string HALF, string ISHALF, code pred>
1011 {
1012    def _operand : Operand<i32>, ImmLeaf<i32, pred, neon_mod_shift_imm_XFORM>
1013     {
1014       let PrintMethod =
1015         "printNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1016       let DecoderMethod =
1017         "DecodeNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1018       let ParserMatchClass =
1019         !cast<AsmOperandClass>("neon_mov_imm_" # PREFIX # HALF # "_asmoperand");
1020     }
1021 }
1022
1023 defm neon_mov_imm_LSL  : neon_mov_imm_shift_operands<"LSL", "", "false", [{
1024   unsigned ShiftImm;
1025   unsigned ShiftOnesIn;
1026   unsigned HasShift =
1027     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1028   return (HasShift && !ShiftOnesIn);
1029 }]>;
1030
1031 defm neon_mov_imm_MSL  : neon_mov_imm_shift_operands<"MSL", "", "false", [{
1032   unsigned ShiftImm;
1033   unsigned ShiftOnesIn;
1034   unsigned HasShift =
1035     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1036   return (HasShift && ShiftOnesIn);
1037 }]>;
1038
1039 defm neon_mov_imm_LSLH  : neon_mov_imm_shift_operands<"LSL", "H", "true", [{
1040   unsigned ShiftImm;
1041   unsigned ShiftOnesIn;
1042   unsigned HasShift =
1043     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1044   return (HasShift && !ShiftOnesIn);
1045 }]>;
1046
1047 def neon_uimm1_asmoperand : AsmOperandClass
1048 {
1049   let Name = "UImm1";
1050   let PredicateMethod = "isUImm<1>";
1051   let RenderMethod = "addImmOperands";
1052 }
1053
1054 def neon_uimm2_asmoperand : AsmOperandClass
1055 {
1056   let Name = "UImm2";
1057   let PredicateMethod = "isUImm<2>";
1058   let RenderMethod = "addImmOperands";
1059 }
1060
1061 def neon_uimm8_asmoperand : AsmOperandClass
1062 {
1063   let Name = "UImm8";
1064   let PredicateMethod = "isUImm<8>";
1065   let RenderMethod = "addImmOperands";
1066 }
1067
1068 def neon_uimm8 : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1069   let ParserMatchClass = neon_uimm8_asmoperand;
1070   let PrintMethod = "printNeonUImm8Operand";
1071 }
1072
1073 def neon_uimm64_mask_asmoperand : AsmOperandClass
1074 {
1075   let Name = "NeonUImm64Mask";
1076   let PredicateMethod = "isNeonUImm64Mask";
1077   let RenderMethod = "addNeonUImm64MaskOperands";
1078 }
1079
1080 // MCOperand for 64-bit bytemask with each byte having only the
1081 // value 0x00 and 0xff is encoded as an unsigned 8-bit value
1082 def neon_uimm64_mask : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1083   let ParserMatchClass = neon_uimm64_mask_asmoperand;
1084   let PrintMethod = "printNeonUImm64MaskOperand";
1085 }
1086
1087 multiclass NeonI_mov_imm_lsl_sizes<string asmop, bit op,
1088                                    SDPatternOperator opnode>
1089 {
1090     // shift zeros, per word
1091     def _2S  : NeonI_1VModImm<0b0, op,
1092                               (outs VPR64:$Rd),
1093                               (ins neon_uimm8:$Imm,
1094                                 neon_mov_imm_LSL_operand:$Simm),
1095                               !strconcat(asmop, " $Rd.2s, $Imm$Simm"),
1096                               [(set (v2i32 VPR64:$Rd),
1097                                  (v2i32 (opnode (timm:$Imm),
1098                                    (neon_mov_imm_LSL_operand:$Simm))))],
1099                               NoItinerary> {
1100        bits<2> Simm;
1101        let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1102      }
1103
1104     def _4S  : NeonI_1VModImm<0b1, op,
1105                               (outs VPR128:$Rd),
1106                               (ins neon_uimm8:$Imm,
1107                                 neon_mov_imm_LSL_operand:$Simm),
1108                               !strconcat(asmop, " $Rd.4s, $Imm$Simm"),
1109                               [(set (v4i32 VPR128:$Rd),
1110                                  (v4i32 (opnode (timm:$Imm),
1111                                    (neon_mov_imm_LSL_operand:$Simm))))],
1112                               NoItinerary> {
1113       bits<2> Simm;
1114       let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1115     }
1116
1117     // shift zeros, per halfword
1118     def _4H  : NeonI_1VModImm<0b0, op,
1119                               (outs VPR64:$Rd),
1120                               (ins neon_uimm8:$Imm,
1121                                 neon_mov_imm_LSLH_operand:$Simm),
1122                               !strconcat(asmop, " $Rd.4h, $Imm$Simm"),
1123                               [(set (v4i16 VPR64:$Rd),
1124                                  (v4i16 (opnode (timm:$Imm),
1125                                    (neon_mov_imm_LSLH_operand:$Simm))))],
1126                               NoItinerary> {
1127       bit  Simm;
1128       let cmode = {0b1, 0b0, Simm, 0b0};
1129     }
1130
1131     def _8H  : NeonI_1VModImm<0b1, op,
1132                               (outs VPR128:$Rd),
1133                               (ins neon_uimm8:$Imm,
1134                                 neon_mov_imm_LSLH_operand:$Simm),
1135                               !strconcat(asmop, " $Rd.8h, $Imm$Simm"),
1136                               [(set (v8i16 VPR128:$Rd),
1137                                  (v8i16 (opnode (timm:$Imm),
1138                                    (neon_mov_imm_LSLH_operand:$Simm))))],
1139                               NoItinerary> {
1140       bit Simm;
1141       let cmode = {0b1, 0b0, Simm, 0b0};
1142      }
1143 }
1144
1145 multiclass NeonI_mov_imm_with_constraint_lsl_sizes<string asmop, bit op,
1146                                                    SDPatternOperator opnode,
1147                                                    SDPatternOperator neonopnode>
1148 {
1149   let Constraints = "$src = $Rd" in {
1150     // shift zeros, per word
1151     def _2S  : NeonI_1VModImm<0b0, op,
1152                  (outs VPR64:$Rd),
1153                  (ins VPR64:$src, neon_uimm8:$Imm,
1154                    neon_mov_imm_LSL_operand:$Simm),
1155                  !strconcat(asmop, " $Rd.2s, $Imm$Simm"),
1156                  [(set (v2i32 VPR64:$Rd),
1157                     (v2i32 (opnode (v2i32 VPR64:$src),
1158                       (v2i32 (bitconvert (v2i32 (neonopnode timm:$Imm,
1159                         neon_mov_imm_LSL_operand:$Simm)))))))],
1160                  NoItinerary> {
1161       bits<2> Simm;
1162       let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1163     }
1164
1165     def _4S  : NeonI_1VModImm<0b1, op,
1166                  (outs VPR128:$Rd),
1167                  (ins VPR128:$src, neon_uimm8:$Imm,
1168                    neon_mov_imm_LSL_operand:$Simm),
1169                  !strconcat(asmop, " $Rd.4s, $Imm$Simm"),
1170                  [(set (v4i32 VPR128:$Rd),
1171                     (v4i32 (opnode (v4i32 VPR128:$src),
1172                       (v4i32 (bitconvert (v4i32 (neonopnode timm:$Imm,
1173                         neon_mov_imm_LSL_operand:$Simm)))))))],
1174                  NoItinerary> {
1175       bits<2> Simm;
1176       let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1177     }
1178
1179     // shift zeros, per halfword
1180     def _4H  : NeonI_1VModImm<0b0, op,
1181                  (outs VPR64:$Rd),
1182                  (ins VPR64:$src, neon_uimm8:$Imm,
1183                    neon_mov_imm_LSLH_operand:$Simm),
1184                  !strconcat(asmop, " $Rd.4h, $Imm$Simm"),
1185                  [(set (v4i16 VPR64:$Rd),
1186                     (v4i16 (opnode (v4i16 VPR64:$src),
1187                        (v4i16 (bitconvert (v4i16 (neonopnode timm:$Imm,
1188                           neon_mov_imm_LSL_operand:$Simm)))))))],
1189                  NoItinerary> {
1190       bit  Simm;
1191       let cmode = {0b1, 0b0, Simm, 0b1};
1192     }
1193
1194     def _8H  : NeonI_1VModImm<0b1, op,
1195                  (outs VPR128:$Rd),
1196                  (ins VPR128:$src, neon_uimm8:$Imm,
1197                    neon_mov_imm_LSLH_operand:$Simm),
1198                  !strconcat(asmop, " $Rd.8h, $Imm$Simm"),
1199                  [(set (v8i16 VPR128:$Rd),
1200                     (v8i16 (opnode (v8i16 VPR128:$src),
1201                       (v8i16 (bitconvert (v8i16 (neonopnode timm:$Imm,
1202                         neon_mov_imm_LSL_operand:$Simm)))))))],
1203                  NoItinerary> {
1204       bit Simm;
1205       let cmode = {0b1, 0b0, Simm, 0b1};
1206     }
1207   }
1208 }
1209
1210 multiclass NeonI_mov_imm_msl_sizes<string asmop, bit op,
1211                                    SDPatternOperator opnode>
1212 {
1213     // shift ones, per word
1214     def _2S  : NeonI_1VModImm<0b0, op,
1215                              (outs VPR64:$Rd),
1216                              (ins neon_uimm8:$Imm,
1217                                neon_mov_imm_MSL_operand:$Simm),
1218                              !strconcat(asmop, " $Rd.2s, $Imm$Simm"),
1219                               [(set (v2i32 VPR64:$Rd),
1220                                  (v2i32 (opnode (timm:$Imm),
1221                                    (neon_mov_imm_MSL_operand:$Simm))))],
1222                              NoItinerary> {
1223        bit Simm;
1224        let cmode = {0b1, 0b1, 0b0, Simm};
1225      }
1226
1227    def _4S  : NeonI_1VModImm<0b1, op,
1228                               (outs VPR128:$Rd),
1229                               (ins neon_uimm8:$Imm,
1230                                 neon_mov_imm_MSL_operand:$Simm),
1231                               !strconcat(asmop, " $Rd.4s, $Imm$Simm"),
1232                               [(set (v4i32 VPR128:$Rd),
1233                                  (v4i32 (opnode (timm:$Imm),
1234                                    (neon_mov_imm_MSL_operand:$Simm))))],
1235                               NoItinerary> {
1236      bit Simm;
1237      let cmode = {0b1, 0b1, 0b0, Simm};
1238    }
1239 }
1240
1241 // Vector Move Immediate Shifted
1242 let isReMaterializable = 1 in {
1243 defm MOVIvi_lsl : NeonI_mov_imm_lsl_sizes<"movi", 0b0, Neon_movi>;
1244 }
1245
1246 // Vector Move Inverted Immediate Shifted
1247 let isReMaterializable = 1 in {
1248 defm MVNIvi_lsl : NeonI_mov_imm_lsl_sizes<"mvni", 0b1, Neon_mvni>;
1249 }
1250
1251 // Vector Bitwise Bit Clear (AND NOT) - immediate
1252 let isReMaterializable = 1 in {
1253 defm BICvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"bic", 0b1,
1254                                                          and, Neon_mvni>;
1255 }
1256
1257 // Vector Bitwise OR - immedidate
1258
1259 let isReMaterializable = 1 in {
1260 defm ORRvi_lsl   : NeonI_mov_imm_with_constraint_lsl_sizes<"orr", 0b0,
1261                                                            or, Neon_movi>;
1262 }
1263
1264 // Additional patterns for Vector Bitwise Bit Clear (AND NOT) - immedidate
1265 // LowerBUILD_VECTOR favors lowering MOVI over MVNI.
1266 // BIC immediate instructions selection requires additional patterns to
1267 // transform Neon_movi operands into BIC immediate operands
1268
1269 def neon_mov_imm_LSLH_transform_XFORM : SDNodeXForm<imm, [{
1270   uint64_t OpCmode = N->getZExtValue();
1271   unsigned ShiftImm;
1272   unsigned ShiftOnesIn;
1273   (void)A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1274   // LSLH restricts shift amount to  0, 8 which are encoded as 0 and 1
1275   // Transform encoded shift amount 0 to 1 and 1 to 0.
1276   return CurDAG->getTargetConstant(!ShiftImm, MVT::i32);
1277 }]>;
1278
1279 def neon_mov_imm_LSLH_transform_operand
1280   : ImmLeaf<i32, [{
1281     unsigned ShiftImm;
1282     unsigned ShiftOnesIn;
1283     unsigned HasShift =
1284       A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1285     return (HasShift && !ShiftOnesIn); }],
1286   neon_mov_imm_LSLH_transform_XFORM>;
1287
1288 // Transform (and A, (4h Neon_movi 0xff)) -> BIC 4h (A, 0x00, LSL 8)
1289 // Transform (and A, (4h Neon_movi 0xff LSL #8)) -> BIC 4h (A, 0x00)
1290 def : Pat<(v4i16 (and VPR64:$src,
1291             (v4i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1292           (BICvi_lsl_4H VPR64:$src, 0,
1293             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1294
1295 // Transform (and A, (8h Neon_movi 8h 0xff)) -> BIC 8h (A, 0x00, LSL 8)
1296 // Transform (and A, (8h Neon_movi 0xff LSL #8)) -> BIC 8h (A, 0x00)
1297 def : Pat<(v8i16 (and VPR128:$src,
1298             (v8i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1299           (BICvi_lsl_8H VPR128:$src, 0,
1300             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1301
1302
1303 multiclass Neon_bitwiseVi_patterns<SDPatternOperator opnode,
1304                                    SDPatternOperator neonopnode,
1305                                    Instruction INST4H,
1306                                    Instruction INST8H> {
1307   def : Pat<(v8i8 (opnode VPR64:$src,
1308                     (bitconvert(v4i16 (neonopnode timm:$Imm,
1309                       neon_mov_imm_LSLH_operand:$Simm))))),
1310             (INST4H VPR64:$src, neon_uimm8:$Imm,
1311               neon_mov_imm_LSLH_operand:$Simm)>;
1312   def : Pat<(v1i64 (opnode VPR64:$src,
1313                   (bitconvert(v4i16 (neonopnode timm:$Imm,
1314                     neon_mov_imm_LSLH_operand:$Simm))))),
1315           (INST4H VPR64:$src, neon_uimm8:$Imm,
1316             neon_mov_imm_LSLH_operand:$Simm)>;
1317
1318   def : Pat<(v16i8 (opnode VPR128:$src,
1319                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1320                      neon_mov_imm_LSLH_operand:$Simm))))),
1321           (INST8H VPR128:$src, neon_uimm8:$Imm,
1322             neon_mov_imm_LSLH_operand:$Simm)>;
1323   def : Pat<(v4i32 (opnode VPR128:$src,
1324                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1325                      neon_mov_imm_LSLH_operand:$Simm))))),
1326           (INST8H VPR128:$src, neon_uimm8:$Imm,
1327             neon_mov_imm_LSLH_operand:$Simm)>;
1328   def : Pat<(v2i64 (opnode VPR128:$src,
1329                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1330                      neon_mov_imm_LSLH_operand:$Simm))))),
1331           (INST8H VPR128:$src, neon_uimm8:$Imm,
1332             neon_mov_imm_LSLH_operand:$Simm)>;
1333 }
1334
1335 // Additional patterns for Vector Vector Bitwise Bit Clear (AND NOT) - immediate
1336 defm : Neon_bitwiseVi_patterns<or, Neon_mvni, BICvi_lsl_4H, BICvi_lsl_8H>;
1337
1338 // Additional patterns for Vector Bitwise OR - immedidate
1339 defm : Neon_bitwiseVi_patterns<or, Neon_movi, ORRvi_lsl_4H, ORRvi_lsl_8H>;
1340
1341
1342 // Vector Move Immediate Masked
1343 let isReMaterializable = 1 in {
1344 defm MOVIvi_msl : NeonI_mov_imm_msl_sizes<"movi", 0b0, Neon_movi>;
1345 }
1346
1347 // Vector Move Inverted Immediate Masked
1348 let isReMaterializable = 1 in {
1349 defm MVNIvi_msl : NeonI_mov_imm_msl_sizes<"mvni", 0b1, Neon_mvni>;
1350 }
1351
1352 class NeonI_mov_imm_lsl_aliases<string asmop, string asmlane,
1353                                 Instruction inst, RegisterOperand VPRC>
1354   : NeonInstAlias<!strconcat(asmop, " $Rd," # asmlane # ", $Imm"),
1355                         (inst VPRC:$Rd, neon_uimm8:$Imm,  0), 0b0>;
1356
1357 // Aliases for Vector Move Immediate Shifted
1358 def : NeonI_mov_imm_lsl_aliases<"movi", ".2s", MOVIvi_lsl_2S, VPR64>;
1359 def : NeonI_mov_imm_lsl_aliases<"movi", ".4s", MOVIvi_lsl_4S, VPR128>;
1360 def : NeonI_mov_imm_lsl_aliases<"movi", ".4h", MOVIvi_lsl_4H, VPR64>;
1361 def : NeonI_mov_imm_lsl_aliases<"movi", ".8h", MOVIvi_lsl_8H, VPR128>;
1362
1363 // Aliases for Vector Move Inverted Immediate Shifted
1364 def : NeonI_mov_imm_lsl_aliases<"mvni", ".2s", MVNIvi_lsl_2S, VPR64>;
1365 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4s", MVNIvi_lsl_4S, VPR128>;
1366 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4h", MVNIvi_lsl_4H, VPR64>;
1367 def : NeonI_mov_imm_lsl_aliases<"mvni", ".8h", MVNIvi_lsl_8H, VPR128>;
1368
1369 // Aliases for Vector Bitwise Bit Clear (AND NOT) - immediate
1370 def : NeonI_mov_imm_lsl_aliases<"bic", ".2s", BICvi_lsl_2S, VPR64>;
1371 def : NeonI_mov_imm_lsl_aliases<"bic", ".4s", BICvi_lsl_4S, VPR128>;
1372 def : NeonI_mov_imm_lsl_aliases<"bic", ".4h", BICvi_lsl_4H, VPR64>;
1373 def : NeonI_mov_imm_lsl_aliases<"bic", ".8h", BICvi_lsl_8H, VPR128>;
1374
1375 // Aliases for Vector Bitwise OR - immedidate
1376 def : NeonI_mov_imm_lsl_aliases<"orr", ".2s", ORRvi_lsl_2S, VPR64>;
1377 def : NeonI_mov_imm_lsl_aliases<"orr", ".4s", ORRvi_lsl_4S, VPR128>;
1378 def : NeonI_mov_imm_lsl_aliases<"orr", ".4h", ORRvi_lsl_4H, VPR64>;
1379 def : NeonI_mov_imm_lsl_aliases<"orr", ".8h", ORRvi_lsl_8H, VPR128>;
1380
1381 //  Vector Move Immediate - per byte
1382 let isReMaterializable = 1 in {
1383 def MOVIvi_8B : NeonI_1VModImm<0b0, 0b0,
1384                                (outs VPR64:$Rd), (ins neon_uimm8:$Imm),
1385                                "movi\t$Rd.8b, $Imm",
1386                                [(set (v8i8 VPR64:$Rd),
1387                                   (v8i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1388                                 NoItinerary> {
1389   let cmode = 0b1110;
1390 }
1391
1392 def MOVIvi_16B : NeonI_1VModImm<0b1, 0b0,
1393                                 (outs VPR128:$Rd), (ins neon_uimm8:$Imm),
1394                                 "movi\t$Rd.16b, $Imm",
1395                                 [(set (v16i8 VPR128:$Rd),
1396                                    (v16i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1397                                  NoItinerary> {
1398   let cmode = 0b1110;
1399 }
1400 }
1401
1402 // Vector Move Immediate - bytemask, per double word
1403 let isReMaterializable = 1 in {
1404 def MOVIvi_2D : NeonI_1VModImm<0b1, 0b1,
1405                                (outs VPR128:$Rd), (ins neon_uimm64_mask:$Imm),
1406                                "movi\t $Rd.2d, $Imm",
1407                                [(set (v2i64 VPR128:$Rd),
1408                                   (v2i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1409                                NoItinerary> {
1410   let cmode = 0b1110;
1411 }
1412 }
1413
1414 // Vector Move Immediate - bytemask, one doubleword
1415
1416 let isReMaterializable = 1 in {
1417 def MOVIdi : NeonI_1VModImm<0b0, 0b1,
1418                            (outs FPR64:$Rd), (ins neon_uimm64_mask:$Imm),
1419                            "movi\t $Rd, $Imm",
1420                            [(set (f64 FPR64:$Rd),
1421                               (f64 (bitconvert
1422                                 (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))))],
1423                            NoItinerary> {
1424   let cmode = 0b1110;
1425 }
1426 }
1427
1428 // Vector Floating Point Move Immediate
1429
1430 class NeonI_FMOV_impl<string asmlane, RegisterOperand VPRC, ValueType OpTy,
1431                       Operand immOpType, bit q, bit op>
1432   : NeonI_1VModImm<q, op,
1433                    (outs VPRC:$Rd), (ins immOpType:$Imm),
1434                    "fmov\t$Rd" # asmlane # ", $Imm",
1435                    [(set (OpTy VPRC:$Rd),
1436                       (OpTy (Neon_fmovi (timm:$Imm))))],
1437                    NoItinerary> {
1438      let cmode = 0b1111;
1439    }
1440
1441 let isReMaterializable = 1 in {
1442 def FMOVvi_2S : NeonI_FMOV_impl<".2s", VPR64,  v2f32, fmov32_operand, 0b0, 0b0>;
1443 def FMOVvi_4S : NeonI_FMOV_impl<".4s", VPR128, v4f32, fmov32_operand, 0b1, 0b0>;
1444 def FMOVvi_2D : NeonI_FMOV_impl<".2d", VPR128, v2f64, fmov64_operand, 0b1, 0b1>;
1445 }
1446
1447 // Vector Shift (Immediate)
1448 // Immediate in [0, 63]
1449 def imm0_63 : Operand<i32> {
1450   let ParserMatchClass = uimm6_asmoperand;
1451 }
1452
1453 // Shift Right Immediate - A shift right immediate is encoded differently from
1454 // other shift immediates. The immh:immb field is encoded like so:
1455 //
1456 //    Offset    Encoding
1457 //     8        immh:immb<6:3> = '0001xxx', <imm> is encoded in immh:immb<2:0>
1458 //     16       immh:immb<6:4> = '001xxxx', <imm> is encoded in immh:immb<3:0>
1459 //     32       immh:immb<6:5> = '01xxxxx', <imm> is encoded in immh:immb<4:0>
1460 //     64       immh:immb<6>   = '1xxxxxx', <imm> is encoded in immh:immb<5:0>
1461 class shr_imm_asmoperands<string OFFSET> : AsmOperandClass {
1462   let Name = "ShrImm" # OFFSET;
1463   let RenderMethod = "addImmOperands";
1464   let DiagnosticType = "ShrImm" # OFFSET;
1465 }
1466
1467 class shr_imm<string OFFSET> : Operand<i32> {
1468   let EncoderMethod = "getShiftRightImm" # OFFSET;
1469   let DecoderMethod = "DecodeShiftRightImm" # OFFSET;
1470   let ParserMatchClass =
1471     !cast<AsmOperandClass>("shr_imm" # OFFSET # "_asmoperand");
1472 }
1473
1474 def shr_imm8_asmoperand : shr_imm_asmoperands<"8">;
1475 def shr_imm16_asmoperand : shr_imm_asmoperands<"16">;
1476 def shr_imm32_asmoperand : shr_imm_asmoperands<"32">;
1477 def shr_imm64_asmoperand : shr_imm_asmoperands<"64">;
1478
1479 def shr_imm8 : shr_imm<"8">;
1480 def shr_imm16 : shr_imm<"16">;
1481 def shr_imm32 : shr_imm<"32">;
1482 def shr_imm64 : shr_imm<"64">;
1483
1484 class N2VShift<bit q, bit u, bits<5> opcode, string asmop, string T,
1485                RegisterOperand VPRC, ValueType Ty, Operand ImmTy, SDNode OpNode>
1486   : NeonI_2VShiftImm<q, u, opcode,
1487                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1488                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1489                      [(set (Ty VPRC:$Rd),
1490                         (Ty (OpNode (Ty VPRC:$Rn),
1491                           (Ty (Neon_vdup (i32 imm:$Imm))))))],
1492                      NoItinerary>;
1493
1494 multiclass NeonI_N2VShL<bit u, bits<5> opcode, string asmop> {
1495   // 64-bit vector types.
1496   def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, uimm3, shl> {
1497     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1498   }
1499
1500   def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, uimm4, shl> {
1501     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1502   }
1503
1504   def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, uimm5, shl> {
1505     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1506   }
1507
1508   // 128-bit vector types.
1509   def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, uimm3, shl> {
1510     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1511   }
1512
1513   def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, uimm4, shl> {
1514     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1515   }
1516
1517   def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, uimm5, shl> {
1518     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1519   }
1520
1521   def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, imm0_63, shl> {
1522     let Inst{22} = 0b1;        // immh:immb = 1xxxxxx
1523   }
1524 }
1525
1526 multiclass NeonI_N2VShR<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1527   def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1528                      OpNode> {
1529     let Inst{22-19} = 0b0001;
1530   }
1531
1532   def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1533                      OpNode> {
1534     let Inst{22-20} = 0b001;
1535   }
1536
1537   def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1538                      OpNode> {
1539      let Inst{22-21} = 0b01;
1540   }
1541
1542   def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1543                       OpNode> {
1544                       let Inst{22-19} = 0b0001;
1545                     }
1546
1547   def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1548                      OpNode> {
1549                      let Inst{22-20} = 0b001;
1550                     }
1551
1552   def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1553                      OpNode> {
1554                       let Inst{22-21} = 0b01;
1555                     }
1556
1557   def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1558                      OpNode> {
1559                       let Inst{22} = 0b1;
1560                     }
1561 }
1562
1563 // Shift left
1564 defm SHLvvi : NeonI_N2VShL<0b0, 0b01010, "shl">;
1565
1566 // Shift right
1567 defm SSHRvvi : NeonI_N2VShR<0b0, 0b00000, "sshr", sra>;
1568 defm USHRvvi : NeonI_N2VShR<0b1, 0b00000, "ushr", srl>;
1569
1570 def Neon_High16B : PatFrag<(ops node:$in),
1571                            (extract_subvector (v16i8 node:$in), (iPTR 8))>;
1572 def Neon_High8H  : PatFrag<(ops node:$in),
1573                            (extract_subvector (v8i16 node:$in), (iPTR 4))>;
1574 def Neon_High4S  : PatFrag<(ops node:$in),
1575                            (extract_subvector (v4i32 node:$in), (iPTR 2))>;
1576
1577 def Neon_low8H : PatFrag<(ops node:$in),
1578                          (v4i16 (extract_subvector (v8i16 node:$in),
1579                                                    (iPTR 0)))>;
1580 def Neon_low4S : PatFrag<(ops node:$in),
1581                          (v2i32 (extract_subvector (v4i32 node:$in),
1582                                                    (iPTR 0)))>;
1583 def Neon_low4f : PatFrag<(ops node:$in),
1584                          (v2f32 (extract_subvector (v4f32 node:$in),
1585                                                    (iPTR 0)))>;
1586
1587 class N2VShiftLong<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1588                    string SrcT, ValueType DestTy, ValueType SrcTy,
1589                    Operand ImmTy, SDPatternOperator ExtOp>
1590   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1591                      (ins VPR64:$Rn, ImmTy:$Imm),
1592                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1593                      [(set (DestTy VPR128:$Rd),
1594                         (DestTy (shl
1595                           (DestTy (ExtOp (SrcTy VPR64:$Rn))),
1596                             (DestTy (Neon_vdup (i32 imm:$Imm))))))],
1597                      NoItinerary>;
1598
1599 class N2VShiftLongHigh<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1600                        string SrcT, ValueType DestTy, ValueType SrcTy,
1601                        int StartIndex, Operand ImmTy,
1602                        SDPatternOperator ExtOp, PatFrag getTop>
1603   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1604                      (ins VPR128:$Rn, ImmTy:$Imm),
1605                      asmop # "2\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1606                      [(set (DestTy VPR128:$Rd),
1607                         (DestTy (shl
1608                           (DestTy (ExtOp
1609                             (SrcTy (getTop VPR128:$Rn)))),
1610                               (DestTy (Neon_vdup (i32 imm:$Imm))))))],
1611                      NoItinerary>;
1612
1613 multiclass NeonI_N2VShLL<string prefix, bit u, bits<5> opcode, string asmop,
1614                          SDNode ExtOp> {
1615   // 64-bit vector types.
1616   def _8B : N2VShiftLong<0b0, u, opcode, asmop, "8h", "8b", v8i16, v8i8,
1617                          uimm3, ExtOp> {
1618     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1619   }
1620
1621   def _4H : N2VShiftLong<0b0, u, opcode, asmop, "4s", "4h", v4i32, v4i16,
1622                          uimm4, ExtOp> {
1623     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1624   }
1625
1626   def _2S : N2VShiftLong<0b0, u, opcode, asmop, "2d", "2s", v2i64, v2i32,
1627                          uimm5, ExtOp> {
1628     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1629   }
1630
1631   // 128-bit vector types
1632   def _16B : N2VShiftLongHigh<0b1, u, opcode, asmop, "8h", "16b",
1633                               v8i16, v8i8, 8, uimm3, ExtOp, Neon_High16B> {
1634     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1635   }
1636
1637   def _8H : N2VShiftLongHigh<0b1, u, opcode, asmop, "4s", "8h",
1638                              v4i32, v4i16, 4, uimm4, ExtOp, Neon_High8H> {
1639     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1640   }
1641
1642   def _4S : N2VShiftLongHigh<0b1, u, opcode, asmop, "2d", "4s",
1643                              v2i64, v2i32, 2, uimm5, ExtOp, Neon_High4S> {
1644     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1645   }
1646
1647   // Use other patterns to match when the immediate is 0.
1648   def : Pat<(v8i16 (ExtOp (v8i8 VPR64:$Rn))),
1649             (!cast<Instruction>(prefix # "_8B") VPR64:$Rn, 0)>;
1650
1651   def : Pat<(v4i32 (ExtOp (v4i16 VPR64:$Rn))),
1652             (!cast<Instruction>(prefix # "_4H") VPR64:$Rn, 0)>;
1653
1654   def : Pat<(v2i64 (ExtOp (v2i32 VPR64:$Rn))),
1655             (!cast<Instruction>(prefix # "_2S") VPR64:$Rn, 0)>;
1656
1657   def : Pat<(v8i16 (ExtOp (v8i8 (Neon_High16B VPR128:$Rn)))),
1658             (!cast<Instruction>(prefix # "_16B") VPR128:$Rn, 0)>;
1659
1660   def : Pat<(v4i32 (ExtOp (v4i16 (Neon_High8H VPR128:$Rn)))),
1661             (!cast<Instruction>(prefix # "_8H") VPR128:$Rn, 0)>;
1662
1663   def : Pat<(v2i64 (ExtOp (v2i32 (Neon_High4S VPR128:$Rn)))),
1664             (!cast<Instruction>(prefix # "_4S") VPR128:$Rn, 0)>;
1665 }
1666
1667 // Shift left long
1668 defm SSHLLvvi : NeonI_N2VShLL<"SSHLLvvi", 0b0, 0b10100, "sshll", sext>;
1669 defm USHLLvvi : NeonI_N2VShLL<"USHLLvvi", 0b1, 0b10100, "ushll", zext>;
1670
1671 // Rounding/Saturating shift
1672 class N2VShift_RQ<bit q, bit u, bits<5> opcode, string asmop, string T,
1673                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1674                   SDPatternOperator OpNode>
1675   : NeonI_2VShiftImm<q, u, opcode,
1676                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1677                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1678                      [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$Rn),
1679                         (i32 imm:$Imm))))],
1680                      NoItinerary>;
1681
1682 // shift right (vector by immediate)
1683 multiclass NeonI_N2VShR_RQ<bit u, bits<5> opcode, string asmop,
1684                            SDPatternOperator OpNode> {
1685   def _8B  : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1686                          OpNode> {
1687     let Inst{22-19} = 0b0001;
1688   }
1689
1690   def _4H  : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1691                          OpNode> {
1692     let Inst{22-20} = 0b001;
1693   }
1694
1695   def _2S  : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1696                          OpNode> {
1697     let Inst{22-21} = 0b01;
1698   }
1699
1700   def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1701                          OpNode> {
1702     let Inst{22-19} = 0b0001;
1703   }
1704
1705   def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1706                         OpNode> {
1707     let Inst{22-20} = 0b001;
1708   }
1709
1710   def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1711                         OpNode> {
1712     let Inst{22-21} = 0b01;
1713   }
1714
1715   def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1716                         OpNode> {
1717     let Inst{22} = 0b1;
1718   }
1719 }
1720
1721 multiclass NeonI_N2VShL_Q<bit u, bits<5> opcode, string asmop,
1722                           SDPatternOperator OpNode> {
1723   // 64-bit vector types.
1724   def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, uimm3,
1725                         OpNode> {
1726     let Inst{22-19} = 0b0001;
1727   }
1728
1729   def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, uimm4,
1730                         OpNode> {
1731     let Inst{22-20} = 0b001;
1732   }
1733
1734   def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, uimm5,
1735                         OpNode> {
1736     let Inst{22-21} = 0b01;
1737   }
1738
1739   // 128-bit vector types.
1740   def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, uimm3,
1741                          OpNode> {
1742     let Inst{22-19} = 0b0001;
1743   }
1744
1745   def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, uimm4,
1746                         OpNode> {
1747     let Inst{22-20} = 0b001;
1748   }
1749
1750   def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, uimm5,
1751                         OpNode> {
1752     let Inst{22-21} = 0b01;
1753   }
1754
1755   def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, imm0_63,
1756                         OpNode> {
1757     let Inst{22} = 0b1;
1758   }
1759 }
1760
1761 // Rounding shift right
1762 defm SRSHRvvi : NeonI_N2VShR_RQ<0b0, 0b00100, "srshr",
1763                                 int_aarch64_neon_vsrshr>;
1764 defm URSHRvvi : NeonI_N2VShR_RQ<0b1, 0b00100, "urshr",
1765                                 int_aarch64_neon_vurshr>;
1766
1767 // Saturating shift left unsigned
1768 defm SQSHLUvvi : NeonI_N2VShL_Q<0b1, 0b01100, "sqshlu", int_aarch64_neon_vsqshlu>;
1769
1770 // Saturating shift left
1771 defm SQSHLvvi : NeonI_N2VShL_Q<0b0, 0b01110, "sqshl", Neon_sqrshlImm>;
1772 defm UQSHLvvi : NeonI_N2VShL_Q<0b1, 0b01110, "uqshl", Neon_uqrshlImm>;
1773
1774 class N2VShiftAdd<bit q, bit u, bits<5> opcode, string asmop, string T,
1775                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1776                   SDNode OpNode>
1777   : NeonI_2VShiftImm<q, u, opcode,
1778            (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1779            asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1780            [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1781               (Ty (OpNode (Ty VPRC:$Rn),
1782                 (Ty (Neon_vdup (i32 imm:$Imm))))))))],
1783            NoItinerary> {
1784   let Constraints = "$src = $Rd";
1785 }
1786
1787 // Shift Right accumulate
1788 multiclass NeonI_N2VShRAdd<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1789   def _8B : N2VShiftAdd<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1790                         OpNode> {
1791     let Inst{22-19} = 0b0001;
1792   }
1793
1794   def _4H : N2VShiftAdd<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1795                         OpNode> {
1796     let Inst{22-20} = 0b001;
1797   }
1798
1799   def _2S : N2VShiftAdd<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1800                         OpNode> {
1801     let Inst{22-21} = 0b01;
1802   }
1803
1804   def _16B : N2VShiftAdd<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1805                          OpNode> {
1806     let Inst{22-19} = 0b0001;
1807   }
1808
1809   def _8H : N2VShiftAdd<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1810                         OpNode> {
1811     let Inst{22-20} = 0b001;
1812   }
1813
1814   def _4S : N2VShiftAdd<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1815                         OpNode> {
1816     let Inst{22-21} = 0b01;
1817   }
1818
1819   def _2D : N2VShiftAdd<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1820                         OpNode> {
1821     let Inst{22} = 0b1;
1822   }
1823 }
1824
1825 // Shift right and accumulate
1826 defm SSRAvvi    : NeonI_N2VShRAdd<0, 0b00010, "ssra", sra>;
1827 defm USRAvvi    : NeonI_N2VShRAdd<1, 0b00010, "usra", srl>;
1828
1829 // Rounding shift accumulate
1830 class N2VShiftAdd_R<bit q, bit u, bits<5> opcode, string asmop, string T,
1831                     RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1832                     SDPatternOperator OpNode>
1833   : NeonI_2VShiftImm<q, u, opcode,
1834                      (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1835                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1836                      [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1837                         (Ty (OpNode (Ty VPRC:$Rn), (i32 imm:$Imm))))))],
1838                      NoItinerary> {
1839   let Constraints = "$src = $Rd";
1840 }
1841
1842 multiclass NeonI_N2VShRAdd_R<bit u, bits<5> opcode, string asmop,
1843                              SDPatternOperator OpNode> {
1844   def _8B : N2VShiftAdd_R<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1845                           OpNode> {
1846     let Inst{22-19} = 0b0001;
1847   }
1848
1849   def _4H : N2VShiftAdd_R<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1850                           OpNode> {
1851     let Inst{22-20} = 0b001;
1852   }
1853
1854   def _2S : N2VShiftAdd_R<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1855                           OpNode> {
1856     let Inst{22-21} = 0b01;
1857   }
1858
1859   def _16B : N2VShiftAdd_R<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1860                            OpNode> {
1861     let Inst{22-19} = 0b0001;
1862   }
1863
1864   def _8H : N2VShiftAdd_R<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1865                           OpNode> {
1866     let Inst{22-20} = 0b001;
1867   }
1868
1869   def _4S : N2VShiftAdd_R<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1870                           OpNode> {
1871     let Inst{22-21} = 0b01;
1872   }
1873
1874   def _2D : N2VShiftAdd_R<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1875                           OpNode> {
1876     let Inst{22} = 0b1;
1877   }
1878 }
1879
1880 // Rounding shift right and accumulate
1881 defm SRSRAvvi : NeonI_N2VShRAdd_R<0, 0b00110, "srsra", int_aarch64_neon_vsrshr>;
1882 defm URSRAvvi : NeonI_N2VShRAdd_R<1, 0b00110, "ursra", int_aarch64_neon_vurshr>;
1883
1884 // Shift insert by immediate
1885 class N2VShiftIns<bit q, bit u, bits<5> opcode, string asmop, string T,
1886                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1887                   SDPatternOperator OpNode>
1888     : NeonI_2VShiftImm<q, u, opcode,
1889            (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1890            asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1891            [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$src), (Ty VPRC:$Rn),
1892              (i32 imm:$Imm))))],
1893            NoItinerary> {
1894   let Constraints = "$src = $Rd";
1895 }
1896
1897 // shift left insert (vector by immediate)
1898 multiclass NeonI_N2VShLIns<bit u, bits<5> opcode, string asmop> {
1899   def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, uimm3,
1900                         int_aarch64_neon_vsli> {
1901     let Inst{22-19} = 0b0001;
1902   }
1903
1904   def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, uimm4,
1905                         int_aarch64_neon_vsli> {
1906     let Inst{22-20} = 0b001;
1907   }
1908
1909   def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, uimm5,
1910                         int_aarch64_neon_vsli> {
1911     let Inst{22-21} = 0b01;
1912   }
1913
1914     // 128-bit vector types
1915   def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, uimm3,
1916                          int_aarch64_neon_vsli> {
1917     let Inst{22-19} = 0b0001;
1918   }
1919
1920   def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, uimm4,
1921                         int_aarch64_neon_vsli> {
1922     let Inst{22-20} = 0b001;
1923   }
1924
1925   def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, uimm5,
1926                         int_aarch64_neon_vsli> {
1927     let Inst{22-21} = 0b01;
1928   }
1929
1930   def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, imm0_63,
1931                         int_aarch64_neon_vsli> {
1932     let Inst{22} = 0b1;
1933   }
1934 }
1935
1936 // shift right insert (vector by immediate)
1937 multiclass NeonI_N2VShRIns<bit u, bits<5> opcode, string asmop> {
1938     // 64-bit vector types.
1939   def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1940                         int_aarch64_neon_vsri> {
1941     let Inst{22-19} = 0b0001;
1942   }
1943
1944   def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1945                         int_aarch64_neon_vsri> {
1946     let Inst{22-20} = 0b001;
1947   }
1948
1949   def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1950                         int_aarch64_neon_vsri> {
1951     let Inst{22-21} = 0b01;
1952   }
1953
1954     // 128-bit vector types
1955   def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1956                          int_aarch64_neon_vsri> {
1957     let Inst{22-19} = 0b0001;
1958   }
1959
1960   def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1961                         int_aarch64_neon_vsri> {
1962     let Inst{22-20} = 0b001;
1963   }
1964
1965   def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1966                         int_aarch64_neon_vsri> {
1967     let Inst{22-21} = 0b01;
1968   }
1969
1970   def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1971                         int_aarch64_neon_vsri> {
1972     let Inst{22} = 0b1;
1973   }
1974 }
1975
1976 // Shift left and insert
1977 defm SLIvvi   : NeonI_N2VShLIns<0b1, 0b01010, "sli">;
1978
1979 // Shift right and insert
1980 defm SRIvvi   : NeonI_N2VShRIns<0b1, 0b01000, "sri">;
1981
1982 class N2VShR_Narrow<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1983                     string SrcT, Operand ImmTy>
1984   : NeonI_2VShiftImm<q, u, opcode,
1985                      (outs VPR64:$Rd), (ins VPR128:$Rn, ImmTy:$Imm),
1986                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1987                      [], NoItinerary>;
1988
1989 class N2VShR_Narrow_Hi<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1990                        string SrcT, Operand ImmTy>
1991   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1992                      (ins VPR128:$src, VPR128:$Rn, ImmTy:$Imm),
1993                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1994                      [], NoItinerary> {
1995   let Constraints = "$src = $Rd";
1996 }
1997
1998 // left long shift by immediate
1999 multiclass NeonI_N2VShR_Narrow<bit u, bits<5> opcode, string asmop> {
2000   def _8B : N2VShR_Narrow<0b0, u, opcode, asmop, "8b", "8h", shr_imm8> {
2001     let Inst{22-19} = 0b0001;
2002   }
2003
2004   def _4H : N2VShR_Narrow<0b0, u, opcode, asmop, "4h", "4s", shr_imm16> {
2005     let Inst{22-20} = 0b001;
2006   }
2007
2008   def _2S : N2VShR_Narrow<0b0, u, opcode, asmop, "2s", "2d", shr_imm32> {
2009     let Inst{22-21} = 0b01;
2010   }
2011
2012   // Shift Narrow High
2013   def _16B : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "16b", "8h",
2014                               shr_imm8> {
2015     let Inst{22-19} = 0b0001;
2016   }
2017
2018   def _8H : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "8h", "4s",
2019                              shr_imm16> {
2020     let Inst{22-20} = 0b001;
2021   }
2022
2023   def _4S : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "4s", "2d",
2024                              shr_imm32> {
2025     let Inst{22-21} = 0b01;
2026   }
2027 }
2028
2029 // Shift right narrow
2030 defm SHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10000, "shrn">;
2031
2032 // Shift right narrow (prefix Q is saturating, prefix R is rounding)
2033 defm QSHRUNvvi :NeonI_N2VShR_Narrow<0b1, 0b10000, "sqshrun">;
2034 defm RSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10001, "rshrn">;
2035 defm QRSHRUNvvi : NeonI_N2VShR_Narrow<0b1, 0b10001, "sqrshrun">;
2036 defm SQSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10010, "sqshrn">;
2037 defm UQSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10010, "uqshrn">;
2038 defm SQRSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10011, "sqrshrn">;
2039 defm UQRSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10011, "uqrshrn">;
2040
2041 def Neon_combine_2D : PatFrag<(ops node:$Rm, node:$Rn),
2042                               (v2i64 (concat_vectors (v1i64 node:$Rm),
2043                                                      (v1i64 node:$Rn)))>;
2044 def Neon_combine_8H : PatFrag<(ops node:$Rm, node:$Rn),
2045                               (v8i16 (concat_vectors (v4i16 node:$Rm),
2046                                                      (v4i16 node:$Rn)))>;
2047 def Neon_combine_4S : PatFrag<(ops node:$Rm, node:$Rn),
2048                               (v4i32 (concat_vectors (v2i32 node:$Rm),
2049                                                      (v2i32 node:$Rn)))>;
2050 def Neon_combine_4f : PatFrag<(ops node:$Rm, node:$Rn),
2051                               (v4f32 (concat_vectors (v2f32 node:$Rm),
2052                                                      (v2f32 node:$Rn)))>;
2053 def Neon_combine_2d : PatFrag<(ops node:$Rm, node:$Rn),
2054                               (v2f64 (concat_vectors (v1f64 node:$Rm),
2055                                                      (v1f64 node:$Rn)))>;
2056
2057 def Neon_lshrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2058                              (v8i16 (srl (v8i16 node:$lhs),
2059                                (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2060 def Neon_lshrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2061                              (v4i32 (srl (v4i32 node:$lhs),
2062                                (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2063 def Neon_lshrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2064                              (v2i64 (srl (v2i64 node:$lhs),
2065                                (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2066 def Neon_ashrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2067                              (v8i16 (sra (v8i16 node:$lhs),
2068                                (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2069 def Neon_ashrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2070                              (v4i32 (sra (v4i32 node:$lhs),
2071                                (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2072 def Neon_ashrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2073                              (v2i64 (sra (v2i64 node:$lhs),
2074                                (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2075
2076 // Normal shift right narrow is matched by IR (srl/sra, trunc, concat_vectors)
2077 multiclass Neon_shiftNarrow_patterns<string shr> {
2078   def : Pat<(v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H") VPR128:$Rn,
2079               (i32 imm:$Imm)))),
2080             (SHRNvvi_8B VPR128:$Rn, imm:$Imm)>;
2081   def : Pat<(v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S") VPR128:$Rn,
2082               (i32 imm:$Imm)))),
2083             (SHRNvvi_4H VPR128:$Rn, imm:$Imm)>;
2084   def : Pat<(v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D") VPR128:$Rn,
2085               (i32 imm:$Imm)))),
2086             (SHRNvvi_2S VPR128:$Rn, imm:$Imm)>;
2087
2088   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2089               (v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H")
2090                 VPR128:$Rn, (i32 imm:$Imm))))))),
2091             (SHRNvvi_16B (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
2092                          VPR128:$Rn, imm:$Imm)>;
2093   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2094               (v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S")
2095                 VPR128:$Rn, (i32 imm:$Imm))))))),
2096             (SHRNvvi_8H (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2097                         VPR128:$Rn, imm:$Imm)>;
2098   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2099               (v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D")
2100                 VPR128:$Rn, (i32 imm:$Imm))))))),
2101             (SHRNvvi_4S (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2102                         VPR128:$Rn, imm:$Imm)>;
2103 }
2104
2105 multiclass Neon_shiftNarrow_QR_patterns<SDPatternOperator op, string prefix> {
2106   def : Pat<(v8i8 (op (v8i16 VPR128:$Rn), imm:$Imm)),
2107             (!cast<Instruction>(prefix # "_8B") VPR128:$Rn, imm:$Imm)>;
2108   def : Pat<(v4i16 (op (v4i32 VPR128:$Rn), imm:$Imm)),
2109             (!cast<Instruction>(prefix # "_4H") VPR128:$Rn, imm:$Imm)>;
2110   def : Pat<(v2i32 (op (v2i64 VPR128:$Rn), imm:$Imm)),
2111             (!cast<Instruction>(prefix # "_2S") VPR128:$Rn, imm:$Imm)>;
2112
2113   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2114                 (v1i64 (bitconvert (v8i8 (op (v8i16 VPR128:$Rn), imm:$Imm))))),
2115             (!cast<Instruction>(prefix # "_16B")
2116                 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2117                 VPR128:$Rn, imm:$Imm)>;
2118   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2119                 (v1i64 (bitconvert (v4i16 (op (v4i32 VPR128:$Rn), imm:$Imm))))),
2120             (!cast<Instruction>(prefix # "_8H")
2121                 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2122                 VPR128:$Rn, imm:$Imm)>;
2123   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2124                 (v1i64 (bitconvert (v2i32 (op (v2i64 VPR128:$Rn), imm:$Imm))))),
2125             (!cast<Instruction>(prefix # "_4S")
2126                   (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2127                   VPR128:$Rn, imm:$Imm)>;
2128 }
2129
2130 defm : Neon_shiftNarrow_patterns<"lshr">;
2131 defm : Neon_shiftNarrow_patterns<"ashr">;
2132
2133 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrun, "QSHRUNvvi">;
2134 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vrshrn, "RSHRNvvi">;
2135 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrun, "QRSHRUNvvi">;
2136 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrn, "SQSHRNvvi">;
2137 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqshrn, "UQSHRNvvi">;
2138 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrn, "SQRSHRNvvi">;
2139 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqrshrn, "UQRSHRNvvi">;
2140
2141 // Convert fix-point and float-pointing
2142 class N2VCvt_Fx<bit q, bit u, bits<5> opcode, string asmop, string T,
2143                 RegisterOperand VPRC, ValueType DestTy, ValueType SrcTy,
2144                 Operand ImmTy, SDPatternOperator IntOp>
2145   : NeonI_2VShiftImm<q, u, opcode,
2146                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
2147                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2148                      [(set (DestTy VPRC:$Rd), (DestTy (IntOp (SrcTy VPRC:$Rn),
2149                        (i32 imm:$Imm))))],
2150                      NoItinerary>;
2151
2152 multiclass NeonI_N2VCvt_Fx2fp<bit u, bits<5> opcode, string asmop,
2153                               SDPatternOperator IntOp> {
2154   def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2f32, v2i32,
2155                       shr_imm32, IntOp> {
2156     let Inst{22-21} = 0b01;
2157   }
2158
2159   def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4f32, v4i32,
2160                       shr_imm32, IntOp> {
2161     let Inst{22-21} = 0b01;
2162   }
2163
2164   def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2f64, v2i64,
2165                       shr_imm64, IntOp> {
2166     let Inst{22} = 0b1;
2167   }
2168 }
2169
2170 multiclass NeonI_N2VCvt_Fp2fx<bit u, bits<5> opcode, string asmop,
2171                               SDPatternOperator IntOp> {
2172   def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2i32, v2f32,
2173                       shr_imm32, IntOp> {
2174     let Inst{22-21} = 0b01;
2175   }
2176
2177   def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4i32, v4f32,
2178                       shr_imm32, IntOp> {
2179     let Inst{22-21} = 0b01;
2180   }
2181
2182   def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2i64, v2f64,
2183                       shr_imm64, IntOp> {
2184     let Inst{22} = 0b1;
2185   }
2186 }
2187
2188 // Convert fixed-point to floating-point
2189 defm VCVTxs2f : NeonI_N2VCvt_Fx2fp<0, 0b11100, "scvtf",
2190                                    int_arm_neon_vcvtfxs2fp>;
2191 defm VCVTxu2f : NeonI_N2VCvt_Fx2fp<1, 0b11100, "ucvtf",
2192                                    int_arm_neon_vcvtfxu2fp>;
2193
2194 // Convert floating-point to fixed-point
2195 defm VCVTf2xs : NeonI_N2VCvt_Fp2fx<0, 0b11111, "fcvtzs",
2196                                    int_arm_neon_vcvtfp2fxs>;
2197 defm VCVTf2xu : NeonI_N2VCvt_Fp2fx<1, 0b11111, "fcvtzu",
2198                                    int_arm_neon_vcvtfp2fxu>;
2199
2200 multiclass Neon_sshll2_0<SDNode ext>
2201 {
2202   def _v8i8  : PatFrag<(ops node:$Rn),
2203                        (v8i16 (ext (v8i8 (Neon_High16B node:$Rn))))>;
2204   def _v4i16 : PatFrag<(ops node:$Rn),
2205                        (v4i32 (ext (v4i16 (Neon_High8H node:$Rn))))>;
2206   def _v2i32 : PatFrag<(ops node:$Rn),
2207                        (v2i64 (ext (v2i32 (Neon_High4S node:$Rn))))>;
2208 }
2209
2210 defm NI_sext_high : Neon_sshll2_0<sext>;
2211 defm NI_zext_high : Neon_sshll2_0<zext>;
2212
2213
2214 //===----------------------------------------------------------------------===//
2215 // Multiclasses for NeonI_Across
2216 //===----------------------------------------------------------------------===//
2217
2218 // Variant 1
2219
2220 multiclass NeonI_2VAcross_1<bit u, bits<5> opcode,
2221                             string asmop, SDPatternOperator opnode>
2222 {
2223     def _1h8b:  NeonI_2VAcross<0b0, u, 0b00, opcode,
2224                 (outs FPR16:$Rd), (ins VPR64:$Rn),
2225                 asmop # "\t$Rd, $Rn.8b",
2226                 [(set (v1i16 FPR16:$Rd),
2227                     (v1i16 (opnode (v8i8 VPR64:$Rn))))],
2228                 NoItinerary>;
2229
2230     def _1h16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2231                 (outs FPR16:$Rd), (ins VPR128:$Rn),
2232                 asmop # "\t$Rd, $Rn.16b",
2233                 [(set (v1i16 FPR16:$Rd),
2234                     (v1i16 (opnode (v16i8 VPR128:$Rn))))],
2235                 NoItinerary>;
2236
2237     def _1s4h:  NeonI_2VAcross<0b0, u, 0b01, opcode,
2238                 (outs FPR32:$Rd), (ins VPR64:$Rn),
2239                 asmop # "\t$Rd, $Rn.4h",
2240                 [(set (v1i32 FPR32:$Rd),
2241                     (v1i32 (opnode (v4i16 VPR64:$Rn))))],
2242                 NoItinerary>;
2243
2244     def _1s8h:  NeonI_2VAcross<0b1, u, 0b01, opcode,
2245                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2246                 asmop # "\t$Rd, $Rn.8h",
2247                 [(set (v1i32 FPR32:$Rd),
2248                     (v1i32 (opnode (v8i16 VPR128:$Rn))))],
2249                 NoItinerary>;
2250
2251     // _1d2s doesn't exist!
2252
2253     def _1d4s:  NeonI_2VAcross<0b1, u, 0b10, opcode,
2254                 (outs FPR64:$Rd), (ins VPR128:$Rn),
2255                 asmop # "\t$Rd, $Rn.4s",
2256                 [(set (v1i64 FPR64:$Rd),
2257                     (v1i64 (opnode (v4i32 VPR128:$Rn))))],
2258                 NoItinerary>;
2259 }
2260
2261 defm SADDLV : NeonI_2VAcross_1<0b0, 0b00011, "saddlv", int_aarch64_neon_saddlv>;
2262 defm UADDLV : NeonI_2VAcross_1<0b1, 0b00011, "uaddlv", int_aarch64_neon_uaddlv>;
2263
2264 // Variant 2
2265
2266 multiclass NeonI_2VAcross_2<bit u, bits<5> opcode,
2267                             string asmop, SDPatternOperator opnode>
2268 {
2269     def _1b8b:  NeonI_2VAcross<0b0, u, 0b00, opcode,
2270                 (outs FPR8:$Rd), (ins VPR64:$Rn),
2271                 asmop # "\t$Rd, $Rn.8b",
2272                 [(set (v1i8 FPR8:$Rd),
2273                     (v1i8 (opnode (v8i8 VPR64:$Rn))))],
2274                 NoItinerary>;
2275
2276     def _1b16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2277                 (outs FPR8:$Rd), (ins VPR128:$Rn),
2278                 asmop # "\t$Rd, $Rn.16b",
2279                 [(set (v1i8 FPR8:$Rd),
2280                     (v1i8 (opnode (v16i8 VPR128:$Rn))))],
2281                 NoItinerary>;
2282
2283     def _1h4h:  NeonI_2VAcross<0b0, u, 0b01, opcode,
2284                 (outs FPR16:$Rd), (ins VPR64:$Rn),
2285                 asmop # "\t$Rd, $Rn.4h",
2286                 [(set (v1i16 FPR16:$Rd),
2287                     (v1i16 (opnode (v4i16 VPR64:$Rn))))],
2288                 NoItinerary>;
2289
2290     def _1h8h:  NeonI_2VAcross<0b1, u, 0b01, opcode,
2291                 (outs FPR16:$Rd), (ins VPR128:$Rn),
2292                 asmop # "\t$Rd, $Rn.8h",
2293                 [(set (v1i16 FPR16:$Rd),
2294                     (v1i16 (opnode (v8i16 VPR128:$Rn))))],
2295                 NoItinerary>;
2296
2297     // _1s2s doesn't exist!
2298
2299     def _1s4s:  NeonI_2VAcross<0b1, u, 0b10, opcode,
2300                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2301                 asmop # "\t$Rd, $Rn.4s",
2302                 [(set (v1i32 FPR32:$Rd),
2303                     (v1i32 (opnode (v4i32 VPR128:$Rn))))],
2304                 NoItinerary>;
2305 }
2306
2307 defm SMAXV : NeonI_2VAcross_2<0b0, 0b01010, "smaxv", int_aarch64_neon_smaxv>;
2308 defm UMAXV : NeonI_2VAcross_2<0b1, 0b01010, "umaxv", int_aarch64_neon_umaxv>;
2309
2310 defm SMINV : NeonI_2VAcross_2<0b0, 0b11010, "sminv", int_aarch64_neon_sminv>;
2311 defm UMINV : NeonI_2VAcross_2<0b1, 0b11010, "uminv", int_aarch64_neon_uminv>;
2312
2313 defm ADDV : NeonI_2VAcross_2<0b0, 0b11011, "addv", int_aarch64_neon_vaddv>;
2314
2315 // Variant 3
2316
2317 multiclass NeonI_2VAcross_3<bit u, bits<5> opcode, bits<2> size,
2318                             string asmop, SDPatternOperator opnode>
2319 {
2320     def _1s4s:  NeonI_2VAcross<0b1, u, size, opcode,
2321                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2322                 asmop # "\t$Rd, $Rn.4s",
2323                 [(set (v1f32 FPR32:$Rd),
2324                     (v1f32 (opnode (v4f32 VPR128:$Rn))))],
2325                 NoItinerary>;
2326 }
2327
2328 defm FMAXNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b00, "fmaxnmv",
2329                                 int_aarch64_neon_vmaxnmv>;
2330 defm FMINNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b10, "fminnmv",
2331                                 int_aarch64_neon_vminnmv>;
2332
2333 defm FMAXV : NeonI_2VAcross_3<0b1, 0b01111, 0b00, "fmaxv",
2334                               int_aarch64_neon_vmaxv>;
2335 defm FMINV : NeonI_2VAcross_3<0b1, 0b01111, 0b10, "fminv",
2336                               int_aarch64_neon_vminv>;
2337
2338 // The followings are for instruction class (3V Diff)
2339
2340 // normal long/long2 pattern
2341 class NeonI_3VDL<bit q, bit u, bits<2> size, bits<4> opcode,
2342                  string asmop, string ResS, string OpS,
2343                  SDPatternOperator opnode, SDPatternOperator ext,
2344                  RegisterOperand OpVPR,
2345                  ValueType ResTy, ValueType OpTy>
2346   : NeonI_3VDiff<q, u, size, opcode,
2347                  (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2348                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2349                  [(set (ResTy VPR128:$Rd),
2350                     (ResTy (opnode (ResTy (ext (OpTy OpVPR:$Rn))),
2351                                    (ResTy (ext (OpTy OpVPR:$Rm))))))],
2352                  NoItinerary>;
2353
2354 multiclass NeonI_3VDL_s<bit u, bits<4> opcode,
2355                         string asmop, SDPatternOperator opnode,
2356                         bit Commutable = 0>
2357 {
2358   let isCommutable = Commutable in {
2359     def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2360                            opnode, sext, VPR64, v8i16, v8i8>;
2361     def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2362                            opnode, sext, VPR64, v4i32, v4i16>;
2363     def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2364                            opnode, sext, VPR64, v2i64, v2i32>;
2365   }
2366 }
2367
2368 multiclass NeonI_3VDL2_s<bit u, bits<4> opcode,
2369                          string asmop, SDPatternOperator opnode,
2370                          bit Commutable = 0>
2371 {
2372   let isCommutable = Commutable in {
2373     def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2374                             opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2375     def _4s8h  : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2376                             opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2377     def _2d4s  : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2378                             opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2379   }
2380 }
2381
2382 multiclass NeonI_3VDL_u<bit u, bits<4> opcode,
2383                           string asmop, SDPatternOperator opnode,
2384                           bit Commutable = 0>
2385 {
2386   let isCommutable = Commutable in {
2387     def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2388                            opnode, zext, VPR64, v8i16, v8i8>;
2389     def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2390                            opnode, zext, VPR64, v4i32, v4i16>;
2391     def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2392                            opnode, zext, VPR64, v2i64, v2i32>;
2393   }
2394 }
2395
2396 multiclass NeonI_3VDL2_u<bit u, bits<4> opcode,
2397                            string asmop, SDPatternOperator opnode,
2398                            bit Commutable = 0>
2399 {
2400   let isCommutable = Commutable in {
2401     def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2402                             opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2403     def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2404                            opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2405     def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2406                            opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2407   }
2408 }
2409
2410 defm SADDLvvv :  NeonI_3VDL_s<0b0, 0b0000, "saddl", add, 1>;
2411 defm UADDLvvv :  NeonI_3VDL_u<0b1, 0b0000, "uaddl", add, 1>;
2412
2413 defm SADDL2vvv :  NeonI_3VDL2_s<0b0, 0b0000, "saddl2", add, 1>;
2414 defm UADDL2vvv :  NeonI_3VDL2_u<0b1, 0b0000, "uaddl2", add, 1>;
2415
2416 defm SSUBLvvv :  NeonI_3VDL_s<0b0, 0b0010, "ssubl", sub, 0>;
2417 defm USUBLvvv :  NeonI_3VDL_u<0b1, 0b0010, "usubl", sub, 0>;
2418
2419 defm SSUBL2vvv :  NeonI_3VDL2_s<0b0, 0b0010, "ssubl2", sub, 0>;
2420 defm USUBL2vvv :  NeonI_3VDL2_u<0b1, 0b0010, "usubl2", sub, 0>;
2421
2422 // normal wide/wide2 pattern
2423 class NeonI_3VDW<bit q, bit u, bits<2> size, bits<4> opcode,
2424                  string asmop, string ResS, string OpS,
2425                  SDPatternOperator opnode, SDPatternOperator ext,
2426                  RegisterOperand OpVPR,
2427                  ValueType ResTy, ValueType OpTy>
2428   : NeonI_3VDiff<q, u, size, opcode,
2429                  (outs VPR128:$Rd), (ins VPR128:$Rn, OpVPR:$Rm),
2430                  asmop # "\t$Rd." # ResS # ", $Rn." # ResS # ", $Rm." # OpS,
2431                  [(set (ResTy VPR128:$Rd),
2432                     (ResTy (opnode (ResTy VPR128:$Rn),
2433                                    (ResTy (ext (OpTy OpVPR:$Rm))))))],
2434                  NoItinerary>;
2435
2436 multiclass NeonI_3VDW_s<bit u, bits<4> opcode,
2437                         string asmop, SDPatternOperator opnode>
2438 {
2439   def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2440                          opnode, sext, VPR64, v8i16, v8i8>;
2441   def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2442                          opnode, sext, VPR64, v4i32, v4i16>;
2443   def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2444                          opnode, sext, VPR64, v2i64, v2i32>;
2445 }
2446
2447 defm SADDWvvv :  NeonI_3VDW_s<0b0, 0b0001, "saddw", add>;
2448 defm SSUBWvvv :  NeonI_3VDW_s<0b0, 0b0011, "ssubw", sub>;
2449
2450 multiclass NeonI_3VDW2_s<bit u, bits<4> opcode,
2451                          string asmop, SDPatternOperator opnode>
2452 {
2453   def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2454                           opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2455   def _4s8h  : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2456                           opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2457   def _2d4s  : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2458                           opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2459 }
2460
2461 defm SADDW2vvv :  NeonI_3VDW2_s<0b0, 0b0001, "saddw2", add>;
2462 defm SSUBW2vvv :  NeonI_3VDW2_s<0b0, 0b0011, "ssubw2", sub>;
2463
2464 multiclass NeonI_3VDW_u<bit u, bits<4> opcode,
2465                         string asmop, SDPatternOperator opnode>
2466 {
2467   def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2468                          opnode, zext, VPR64, v8i16, v8i8>;
2469   def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2470                          opnode, zext, VPR64, v4i32, v4i16>;
2471   def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2472                          opnode, zext, VPR64, v2i64, v2i32>;
2473 }
2474
2475 defm UADDWvvv :  NeonI_3VDW_u<0b1, 0b0001, "uaddw", add>;
2476 defm USUBWvvv :  NeonI_3VDW_u<0b1, 0b0011, "usubw", sub>;
2477
2478 multiclass NeonI_3VDW2_u<bit u, bits<4> opcode,
2479                            string asmop, SDPatternOperator opnode>
2480 {
2481   def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2482                           opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2483   def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2484                          opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2485   def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2486                          opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2487 }
2488
2489 defm UADDW2vvv :  NeonI_3VDW2_u<0b1, 0b0001, "uaddw2", add>;
2490 defm USUBW2vvv :  NeonI_3VDW2_u<0b1, 0b0011, "usubw2", sub>;
2491
2492 // Get the high half part of the vector element.
2493 multiclass NeonI_get_high
2494 {
2495   def _8h : PatFrag<(ops node:$Rn),
2496                     (v8i8 (trunc (v8i16 (srl (v8i16 node:$Rn),
2497                                              (v8i16 (Neon_vdup (i32 8)))))))>;
2498   def _4s : PatFrag<(ops node:$Rn),
2499                     (v4i16 (trunc (v4i32 (srl (v4i32 node:$Rn),
2500                                               (v4i32 (Neon_vdup (i32 16)))))))>;
2501   def _2d : PatFrag<(ops node:$Rn),
2502                     (v2i32 (trunc (v2i64 (srl (v2i64 node:$Rn),
2503                                               (v2i64 (Neon_vdup (i32 32)))))))>;
2504 }
2505
2506 defm NI_get_hi : NeonI_get_high;
2507
2508 // pattern for addhn/subhn with 2 operands
2509 class NeonI_3VDN_addhn_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2510                            string asmop, string ResS, string OpS,
2511                            SDPatternOperator opnode, SDPatternOperator get_hi,
2512                            ValueType ResTy, ValueType OpTy>
2513   : NeonI_3VDiff<q, u, size, opcode,
2514                  (outs VPR64:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2515                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2516                  [(set (ResTy VPR64:$Rd),
2517                     (ResTy (get_hi
2518                       (OpTy (opnode (OpTy VPR128:$Rn),
2519                                     (OpTy VPR128:$Rm))))))],
2520                  NoItinerary>;
2521
2522 multiclass NeonI_3VDN_addhn_2Op<bit u, bits<4> opcode,
2523                                 string asmop, SDPatternOperator opnode,
2524                                 bit Commutable = 0>
2525 {
2526   let isCommutable = Commutable in {
2527     def _8b8h : NeonI_3VDN_addhn_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2528                                      opnode, NI_get_hi_8h, v8i8, v8i16>;
2529     def _4h4s : NeonI_3VDN_addhn_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2530                                      opnode, NI_get_hi_4s, v4i16, v4i32>;
2531     def _2s2d : NeonI_3VDN_addhn_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2532                                      opnode, NI_get_hi_2d, v2i32, v2i64>;
2533   }
2534 }
2535
2536 defm ADDHNvvv  : NeonI_3VDN_addhn_2Op<0b0, 0b0100, "addhn", add, 1>;
2537 defm SUBHNvvv  : NeonI_3VDN_addhn_2Op<0b0, 0b0110, "subhn", sub, 0>;
2538
2539 // pattern for operation with 2 operands
2540 class NeonI_3VD_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2541                     string asmop, string ResS, string OpS,
2542                     SDPatternOperator opnode,
2543                     RegisterOperand ResVPR, RegisterOperand OpVPR,
2544                     ValueType ResTy, ValueType OpTy>
2545   : NeonI_3VDiff<q, u, size, opcode,
2546                  (outs ResVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2547                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2548                  [(set (ResTy ResVPR:$Rd),
2549                     (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))],
2550                  NoItinerary>;
2551
2552 // normal narrow pattern
2553 multiclass NeonI_3VDN_2Op<bit u, bits<4> opcode,
2554                           string asmop, SDPatternOperator opnode,
2555                           bit Commutable = 0>
2556 {
2557   let isCommutable = Commutable in {
2558     def _8b8h : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2559                               opnode, VPR64, VPR128, v8i8, v8i16>;
2560     def _4h4s : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2561                               opnode, VPR64, VPR128, v4i16, v4i32>;
2562     def _2s2d : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2563                               opnode, VPR64, VPR128, v2i32, v2i64>;
2564   }
2565 }
2566
2567 defm RADDHNvvv : NeonI_3VDN_2Op<0b1, 0b0100, "raddhn", int_arm_neon_vraddhn, 1>;
2568 defm RSUBHNvvv : NeonI_3VDN_2Op<0b1, 0b0110, "rsubhn", int_arm_neon_vrsubhn, 0>;
2569
2570 // pattern for acle intrinsic with 3 operands
2571 class NeonI_3VDN_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2572                      string asmop, string ResS, string OpS>
2573   : NeonI_3VDiff<q, u, size, opcode,
2574                  (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
2575                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2576                  [], NoItinerary> {
2577   let Constraints = "$src = $Rd";
2578   let neverHasSideEffects = 1;
2579 }
2580
2581 multiclass NeonI_3VDN_3Op_v1<bit u, bits<4> opcode,
2582                              string asmop> {
2583   def _16b8h : NeonI_3VDN_3Op<0b1, u, 0b00, opcode, asmop, "16b", "8h">;
2584   def _8h4s : NeonI_3VDN_3Op<0b1, u, 0b01, opcode, asmop, "8h", "4s">;
2585   def _4s2d : NeonI_3VDN_3Op<0b1, u, 0b10, opcode, asmop, "4s", "2d">;
2586 }
2587
2588 defm ADDHN2vvv  : NeonI_3VDN_3Op_v1<0b0, 0b0100, "addhn2">;
2589 defm SUBHN2vvv  : NeonI_3VDN_3Op_v1<0b0, 0b0110, "subhn2">;
2590
2591 defm RADDHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0100, "raddhn2">;
2592 defm RSUBHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0110, "rsubhn2">;
2593
2594 // Patterns have to be separate because there's a SUBREG_TO_REG in the output
2595 // part.
2596 class NarrowHighHalfPat<Instruction INST, ValueType DstTy, ValueType SrcTy,
2597                         SDPatternOperator coreop>
2598   : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2599                       (v1i64 (bitconvert (DstTy (coreop (SrcTy VPR128:$Rn),
2600                                                         (SrcTy VPR128:$Rm)))))),
2601         (INST (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2602               VPR128:$Rn, VPR128:$Rm)>;
2603
2604 // addhn2 patterns
2605 def : NarrowHighHalfPat<ADDHN2vvv_16b8h, v8i8,  v8i16,
2606           BinOpFrag<(NI_get_hi_8h (add node:$LHS, node:$RHS))>>;
2607 def : NarrowHighHalfPat<ADDHN2vvv_8h4s,  v4i16, v4i32,
2608           BinOpFrag<(NI_get_hi_4s (add node:$LHS, node:$RHS))>>;
2609 def : NarrowHighHalfPat<ADDHN2vvv_4s2d,  v2i32, v2i64,
2610           BinOpFrag<(NI_get_hi_2d (add node:$LHS, node:$RHS))>>;
2611
2612 // subhn2 patterns
2613 def : NarrowHighHalfPat<SUBHN2vvv_16b8h, v8i8,  v8i16,
2614           BinOpFrag<(NI_get_hi_8h (sub node:$LHS, node:$RHS))>>;
2615 def : NarrowHighHalfPat<SUBHN2vvv_8h4s,  v4i16, v4i32,
2616           BinOpFrag<(NI_get_hi_4s (sub node:$LHS, node:$RHS))>>;
2617 def : NarrowHighHalfPat<SUBHN2vvv_4s2d,  v2i32, v2i64,
2618           BinOpFrag<(NI_get_hi_2d (sub node:$LHS, node:$RHS))>>;
2619
2620 // raddhn2 patterns
2621 def : NarrowHighHalfPat<RADDHN2vvv_16b8h, v8i8,  v8i16, int_arm_neon_vraddhn>;
2622 def : NarrowHighHalfPat<RADDHN2vvv_8h4s,  v4i16, v4i32, int_arm_neon_vraddhn>;
2623 def : NarrowHighHalfPat<RADDHN2vvv_4s2d,  v2i32, v2i64, int_arm_neon_vraddhn>;
2624
2625 // rsubhn2 patterns
2626 def : NarrowHighHalfPat<RSUBHN2vvv_16b8h, v8i8,  v8i16, int_arm_neon_vrsubhn>;
2627 def : NarrowHighHalfPat<RSUBHN2vvv_8h4s,  v4i16, v4i32, int_arm_neon_vrsubhn>;
2628 def : NarrowHighHalfPat<RSUBHN2vvv_4s2d,  v2i32, v2i64, int_arm_neon_vrsubhn>;
2629
2630 // pattern that need to extend result
2631 class NeonI_3VDL_Ext<bit q, bit u, bits<2> size, bits<4> opcode,
2632                      string asmop, string ResS, string OpS,
2633                      SDPatternOperator opnode,
2634                      RegisterOperand OpVPR,
2635                      ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2636   : NeonI_3VDiff<q, u, size, opcode,
2637                  (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2638                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2639                  [(set (ResTy VPR128:$Rd),
2640                     (ResTy (zext (OpSTy (opnode (OpTy OpVPR:$Rn),
2641                                                 (OpTy OpVPR:$Rm))))))],
2642                  NoItinerary>;
2643
2644 multiclass NeonI_3VDL_zext<bit u, bits<4> opcode,
2645                            string asmop, SDPatternOperator opnode,
2646                            bit Commutable = 0>
2647 {
2648   let isCommutable = Commutable in {
2649     def _8h8b : NeonI_3VDL_Ext<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2650                                opnode, VPR64, v8i16, v8i8, v8i8>;
2651     def _4s4h : NeonI_3VDL_Ext<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2652                                opnode, VPR64, v4i32, v4i16, v4i16>;
2653     def _2d2s : NeonI_3VDL_Ext<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2654                                opnode, VPR64, v2i64, v2i32, v2i32>;
2655   }
2656 }
2657
2658 defm SABDLvvv : NeonI_3VDL_zext<0b0, 0b0111, "sabdl", int_arm_neon_vabds, 1>;
2659 defm UABDLvvv : NeonI_3VDL_zext<0b1, 0b0111, "uabdl", int_arm_neon_vabdu, 1>;
2660
2661 multiclass NeonI_Op_High<SDPatternOperator op>
2662 {
2663   def _16B : PatFrag<(ops node:$Rn, node:$Rm),
2664                      (op (v8i8 (Neon_High16B node:$Rn)), (v8i8 (Neon_High16B node:$Rm)))>;
2665   def _8H  : PatFrag<(ops node:$Rn, node:$Rm),
2666                      (op (v4i16 (Neon_High8H node:$Rn)), (v4i16 (Neon_High8H node:$Rm)))>;
2667   def _4S  : PatFrag<(ops node:$Rn, node:$Rm),
2668                      (op (v2i32 (Neon_High4S node:$Rn)), (v2i32 (Neon_High4S node:$Rm)))>;
2669
2670 }
2671
2672 defm NI_sabdl_hi : NeonI_Op_High<int_arm_neon_vabds>;
2673 defm NI_uabdl_hi : NeonI_Op_High<int_arm_neon_vabdu>;
2674 defm NI_smull_hi : NeonI_Op_High<int_arm_neon_vmulls>;
2675 defm NI_umull_hi : NeonI_Op_High<int_arm_neon_vmullu>;
2676 defm NI_qdmull_hi : NeonI_Op_High<int_arm_neon_vqdmull>;
2677 defm NI_pmull_hi : NeonI_Op_High<int_arm_neon_vmullp>;
2678
2679 multiclass NeonI_3VDL_Abd_u<bit u, bits<4> opcode,
2680                             string asmop, string opnode,
2681                             bit Commutable = 0>
2682 {
2683   let isCommutable = Commutable in {
2684     def _8h8b  : NeonI_3VDL_Ext<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2685                                 !cast<PatFrag>(opnode # "_16B"),
2686                                 VPR128, v8i16, v16i8, v8i8>;
2687     def _4s4h  : NeonI_3VDL_Ext<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2688                                 !cast<PatFrag>(opnode # "_8H"),
2689                                 VPR128, v4i32, v8i16, v4i16>;
2690     def _2d2s  : NeonI_3VDL_Ext<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2691                                 !cast<PatFrag>(opnode # "_4S"),
2692                                 VPR128, v2i64, v4i32, v2i32>;
2693   }
2694 }
2695
2696 defm SABDL2vvv : NeonI_3VDL_Abd_u<0b0, 0b0111, "sabdl2", "NI_sabdl_hi", 1>;
2697 defm UABDL2vvv : NeonI_3VDL_Abd_u<0b1, 0b0111, "uabdl2", "NI_uabdl_hi", 1>;
2698
2699 // For pattern that need two operators being chained.
2700 class NeonI_3VDL_Aba<bit q, bit u, bits<2> size, bits<4> opcode,
2701                      string asmop, string ResS, string OpS,
2702                      SDPatternOperator opnode, SDPatternOperator subop,
2703                      RegisterOperand OpVPR,
2704                      ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2705   : NeonI_3VDiff<q, u, size, opcode,
2706                  (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2707                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2708                  [(set (ResTy VPR128:$Rd),
2709                     (ResTy (opnode
2710                       (ResTy VPR128:$src),
2711                       (ResTy (zext (OpSTy (subop (OpTy OpVPR:$Rn),
2712                                                  (OpTy OpVPR:$Rm))))))))],
2713                  NoItinerary> {
2714   let Constraints = "$src = $Rd";
2715 }
2716
2717 multiclass NeonI_3VDL_Aba_v1<bit u, bits<4> opcode,
2718                              string asmop, SDPatternOperator opnode,
2719                              SDPatternOperator subop>
2720 {
2721   def _8h8b : NeonI_3VDL_Aba<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2722                              opnode, subop, VPR64, v8i16, v8i8, v8i8>;
2723   def _4s4h : NeonI_3VDL_Aba<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2724                              opnode, subop, VPR64, v4i32, v4i16, v4i16>;
2725   def _2d2s : NeonI_3VDL_Aba<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2726                              opnode, subop, VPR64, v2i64, v2i32, v2i32>;
2727 }
2728
2729 defm SABALvvv :  NeonI_3VDL_Aba_v1<0b0, 0b0101, "sabal",
2730                                    add, int_arm_neon_vabds>;
2731 defm UABALvvv :  NeonI_3VDL_Aba_v1<0b1, 0b0101, "uabal",
2732                                    add, int_arm_neon_vabdu>;
2733
2734 multiclass NeonI_3VDL2_Aba_v1<bit u, bits<4> opcode,
2735                               string asmop, SDPatternOperator opnode,
2736                               string subop>
2737 {
2738   def _8h8b : NeonI_3VDL_Aba<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2739                              opnode, !cast<PatFrag>(subop # "_16B"),
2740                              VPR128, v8i16, v16i8, v8i8>;
2741   def _4s4h : NeonI_3VDL_Aba<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2742                              opnode, !cast<PatFrag>(subop # "_8H"),
2743                              VPR128, v4i32, v8i16, v4i16>;
2744   def _2d2s : NeonI_3VDL_Aba<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2745                              opnode, !cast<PatFrag>(subop # "_4S"),
2746                              VPR128, v2i64, v4i32, v2i32>;
2747 }
2748
2749 defm SABAL2vvv :  NeonI_3VDL2_Aba_v1<0b0, 0b0101, "sabal2", add,
2750                                      "NI_sabdl_hi">;
2751 defm UABAL2vvv :  NeonI_3VDL2_Aba_v1<0b1, 0b0101, "uabal2", add,
2752                                      "NI_uabdl_hi">;
2753
2754 // Long pattern with 2 operands
2755 multiclass NeonI_3VDL_2Op<bit u, bits<4> opcode,
2756                           string asmop, SDPatternOperator opnode,
2757                           bit Commutable = 0>
2758 {
2759   let isCommutable = Commutable in {
2760     def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2761                               opnode, VPR128, VPR64, v8i16, v8i8>;
2762     def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2763                               opnode, VPR128, VPR64, v4i32, v4i16>;
2764     def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2765                               opnode, VPR128, VPR64, v2i64, v2i32>;
2766   }
2767 }
2768
2769 defm SMULLvvv :  NeonI_3VDL_2Op<0b0, 0b1100, "smull", int_arm_neon_vmulls, 1>;
2770 defm UMULLvvv :  NeonI_3VDL_2Op<0b1, 0b1100, "umull", int_arm_neon_vmullu, 1>;
2771
2772 class NeonI_3VDL2_2Op_mull<bit q, bit u, bits<2> size, bits<4> opcode,
2773                            string asmop, string ResS, string OpS,
2774                            SDPatternOperator opnode,
2775                            ValueType ResTy, ValueType OpTy>
2776   : NeonI_3VDiff<q, u, size, opcode,
2777                  (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2778                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2779                  [(set (ResTy VPR128:$Rd),
2780                     (ResTy (opnode (OpTy VPR128:$Rn), (OpTy VPR128:$Rm))))],
2781                  NoItinerary>;
2782
2783
2784 multiclass NeonI_3VDL2_2Op_mull_v1<bit u, bits<4> opcode,
2785                                    string asmop,
2786                                    string opnode,
2787                                    bit Commutable = 0>
2788 {
2789   let isCommutable = Commutable in {
2790     def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2791                                       !cast<PatFrag>(opnode # "_16B"),
2792                                       v8i16, v16i8>;
2793     def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2794                                      !cast<PatFrag>(opnode # "_8H"),
2795                                      v4i32, v8i16>;
2796     def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2797                                      !cast<PatFrag>(opnode # "_4S"),
2798                                      v2i64, v4i32>;
2799   }
2800 }
2801
2802 defm SMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b0, 0b1100, "smull2",
2803                                          "NI_smull_hi", 1>;
2804 defm UMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b1, 0b1100, "umull2",
2805                                          "NI_umull_hi", 1>;
2806
2807 // Long pattern with 3 operands
2808 class NeonI_3VDL_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2809                      string asmop, string ResS, string OpS,
2810                      SDPatternOperator opnode,
2811                      ValueType ResTy, ValueType OpTy>
2812   : NeonI_3VDiff<q, u, size, opcode,
2813                  (outs VPR128:$Rd), (ins VPR128:$src, VPR64:$Rn, VPR64:$Rm),
2814                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2815                  [(set (ResTy VPR128:$Rd),
2816                     (ResTy (opnode
2817                       (ResTy VPR128:$src),
2818                       (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))))],
2819                NoItinerary> {
2820   let Constraints = "$src = $Rd";
2821 }
2822
2823 multiclass NeonI_3VDL_3Op_v1<bit u, bits<4> opcode,
2824                              string asmop, SDPatternOperator opnode>
2825 {
2826   def _8h8b : NeonI_3VDL_3Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2827                              opnode, v8i16, v8i8>;
2828   def _4s4h : NeonI_3VDL_3Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2829                              opnode, v4i32, v4i16>;
2830   def _2d2s : NeonI_3VDL_3Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2831                              opnode, v2i64, v2i32>;
2832 }
2833
2834 def Neon_smlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2835                          (add node:$Rd,
2836                             (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
2837
2838 def Neon_umlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2839                          (add node:$Rd,
2840                             (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
2841
2842 def Neon_smlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2843                          (sub node:$Rd,
2844                             (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
2845
2846 def Neon_umlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2847                          (sub node:$Rd,
2848                             (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
2849
2850 defm SMLALvvv :  NeonI_3VDL_3Op_v1<0b0, 0b1000, "smlal", Neon_smlal>;
2851 defm UMLALvvv :  NeonI_3VDL_3Op_v1<0b1, 0b1000, "umlal", Neon_umlal>;
2852
2853 defm SMLSLvvv :  NeonI_3VDL_3Op_v1<0b0, 0b1010, "smlsl", Neon_smlsl>;
2854 defm UMLSLvvv :  NeonI_3VDL_3Op_v1<0b1, 0b1010, "umlsl", Neon_umlsl>;
2855
2856 class NeonI_3VDL2_3Op_mlas<bit q, bit u, bits<2> size, bits<4> opcode,
2857                            string asmop, string ResS, string OpS,
2858                            SDPatternOperator subop, SDPatternOperator opnode,
2859                            RegisterOperand OpVPR,
2860                            ValueType ResTy, ValueType OpTy>
2861   : NeonI_3VDiff<q, u, size, opcode,
2862                (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2863                asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2864                [(set (ResTy VPR128:$Rd),
2865                   (ResTy (subop
2866                     (ResTy VPR128:$src),
2867                     (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))))],
2868                NoItinerary> {
2869   let Constraints = "$src = $Rd";
2870 }
2871
2872 multiclass NeonI_3VDL2_3Op_mlas_v1<bit u, bits<4> opcode,
2873                                    string asmop,
2874                                    SDPatternOperator subop,
2875                                    string opnode>
2876 {
2877   def _8h16b : NeonI_3VDL2_3Op_mlas<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2878                                     subop, !cast<PatFrag>(opnode # "_16B"),
2879                                     VPR128, v8i16, v16i8>;
2880   def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2881                                    subop, !cast<PatFrag>(opnode # "_8H"),
2882                                    VPR128, v4i32, v8i16>;
2883   def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2884                                    subop, !cast<PatFrag>(opnode # "_4S"),
2885                                    VPR128, v2i64, v4i32>;
2886 }
2887
2888 defm SMLAL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1000, "smlal2",
2889                                           add, "NI_smull_hi">;
2890 defm UMLAL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1000, "umlal2",
2891                                           add, "NI_umull_hi">;
2892
2893 defm SMLSL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1010, "smlsl2",
2894                                           sub, "NI_smull_hi">;
2895 defm UMLSL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1010, "umlsl2",
2896                                           sub, "NI_umull_hi">;
2897
2898 multiclass NeonI_3VDL_qdmlal_3Op_v2<bit u, bits<4> opcode,
2899                                     string asmop, SDPatternOperator opnode>
2900 {
2901   def _4s4h : NeonI_3VDL2_3Op_mlas<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2902                                    opnode, int_arm_neon_vqdmull,
2903                                    VPR64, v4i32, v4i16>;
2904   def _2d2s : NeonI_3VDL2_3Op_mlas<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2905                                    opnode, int_arm_neon_vqdmull,
2906                                    VPR64, v2i64, v2i32>;
2907 }
2908
2909 defm SQDMLALvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1001, "sqdmlal",
2910                                            int_arm_neon_vqadds>;
2911 defm SQDMLSLvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1011, "sqdmlsl",
2912                                            int_arm_neon_vqsubs>;
2913
2914 multiclass NeonI_3VDL_v2<bit u, bits<4> opcode,
2915                          string asmop, SDPatternOperator opnode,
2916                          bit Commutable = 0>
2917 {
2918   let isCommutable = Commutable in {
2919     def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2920                               opnode, VPR128, VPR64, v4i32, v4i16>;
2921     def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2922                               opnode, VPR128, VPR64, v2i64, v2i32>;
2923   }
2924 }
2925
2926 defm SQDMULLvvv : NeonI_3VDL_v2<0b0, 0b1101, "sqdmull",
2927                                 int_arm_neon_vqdmull, 1>;
2928
2929 multiclass NeonI_3VDL2_2Op_mull_v2<bit u, bits<4> opcode,
2930                                    string asmop,
2931                                    string opnode,
2932                                    bit Commutable = 0>
2933 {
2934   let isCommutable = Commutable in {
2935     def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2936                                      !cast<PatFrag>(opnode # "_8H"),
2937                                      v4i32, v8i16>;
2938     def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2939                                      !cast<PatFrag>(opnode # "_4S"),
2940                                      v2i64, v4i32>;
2941   }
2942 }
2943
2944 defm SQDMULL2vvv : NeonI_3VDL2_2Op_mull_v2<0b0, 0b1101, "sqdmull2",
2945                                            "NI_qdmull_hi", 1>;
2946
2947 multiclass NeonI_3VDL2_3Op_qdmlal_v2<bit u, bits<4> opcode,
2948                                      string asmop,
2949                                      SDPatternOperator opnode>
2950 {
2951   def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2952                                    opnode, NI_qdmull_hi_8H,
2953                                    VPR128, v4i32, v8i16>;
2954   def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2955                                    opnode, NI_qdmull_hi_4S,
2956                                    VPR128, v2i64, v4i32>;
2957 }
2958
2959 defm SQDMLAL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1001, "sqdmlal2",
2960                                              int_arm_neon_vqadds>;
2961 defm SQDMLSL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1011, "sqdmlsl2",
2962                                              int_arm_neon_vqsubs>;
2963
2964 multiclass NeonI_3VDL_v3<bit u, bits<4> opcode,
2965                                    string asmop, SDPatternOperator opnode,
2966                                    bit Commutable = 0>
2967 {
2968   let isCommutable = Commutable in {
2969     def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2970                               opnode, VPR128, VPR64, v8i16, v8i8>;
2971   }
2972 }
2973
2974 defm PMULLvvv : NeonI_3VDL_v3<0b0, 0b1110, "pmull", int_arm_neon_vmullp, 1>;
2975
2976 multiclass NeonI_3VDL2_2Op_mull_v3<bit u, bits<4> opcode,
2977                                    string asmop,
2978                                    string opnode,
2979                                    bit Commutable = 0>
2980 {
2981   let isCommutable = Commutable in {
2982     def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2983                                       !cast<PatFrag>(opnode # "_16B"),
2984                                       v8i16, v16i8>;
2985   }
2986 }
2987
2988 defm PMULL2vvv : NeonI_3VDL2_2Op_mull_v3<0b0, 0b1110, "pmull2",
2989                                          "NI_pmull_hi", 1>;
2990
2991 // End of implementation for instruction class (3V Diff)
2992
2993 // The followings are vector load/store multiple N-element structure
2994 // (class SIMD lselem).
2995
2996 // ld1:         load multiple 1-element structure to 1/2/3/4 registers.
2997 // ld2/ld3/ld4: load multiple N-element structure to N registers (N = 2, 3, 4).
2998 //              The structure consists of a sequence of sets of N values.
2999 //              The first element of the structure is placed in the first lane
3000 //              of the first first vector, the second element in the first lane
3001 //              of the second vector, and so on.
3002 // E.g. LD1_3V_2S will load 32-bit elements {A, B, C, D, E, F} sequentially into
3003 // the three 64-bit vectors list {BA, DC, FE}.
3004 // E.g. LD3_2S will load 32-bit elements {A, B, C, D, E, F} into the three
3005 // 64-bit vectors list {DA, EB, FC}.
3006 // Store instructions store multiple structure to N registers like load.
3007
3008
3009 class NeonI_LDVList<bit q, bits<4> opcode, bits<2> size,
3010                     RegisterOperand VecList, string asmop>
3011   : NeonI_LdStMult<q, 1, opcode, size,
3012                  (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3013                  asmop # "\t$Rt, [$Rn]",
3014                  [],
3015                  NoItinerary> {
3016   let mayLoad = 1;
3017   let neverHasSideEffects = 1;
3018 }
3019
3020 multiclass LDVList_BHSD<bits<4> opcode, string List, string asmop> {
3021   def _8B : NeonI_LDVList<0, opcode, 0b00,
3022                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3023
3024   def _4H : NeonI_LDVList<0, opcode, 0b01,
3025                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3026
3027   def _2S : NeonI_LDVList<0, opcode, 0b10,
3028                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3029
3030   def _16B : NeonI_LDVList<1, opcode, 0b00,
3031                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3032
3033   def _8H : NeonI_LDVList<1, opcode, 0b01,
3034                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3035
3036   def _4S : NeonI_LDVList<1, opcode, 0b10,
3037                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3038
3039   def _2D : NeonI_LDVList<1, opcode, 0b11,
3040                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3041 }
3042
3043 // Load multiple N-element structure to N consecutive registers (N = 1,2,3,4)
3044 defm LD1 : LDVList_BHSD<0b0111, "VOne", "ld1">;
3045 def LD1_1D : NeonI_LDVList<0, 0b0111, 0b11, VOne1D_operand, "ld1">;
3046
3047 defm LD2 : LDVList_BHSD<0b1000, "VPair", "ld2">;
3048
3049 defm LD3 : LDVList_BHSD<0b0100, "VTriple", "ld3">;
3050
3051 defm LD4 : LDVList_BHSD<0b0000, "VQuad", "ld4">;
3052
3053 // Load multiple 1-element structure to N consecutive registers (N = 2,3,4)
3054 defm LD1_2V : LDVList_BHSD<0b1010, "VPair", "ld1">;
3055 def LD1_2V_1D : NeonI_LDVList<0, 0b1010, 0b11, VPair1D_operand, "ld1">;
3056
3057 defm LD1_3V : LDVList_BHSD<0b0110, "VTriple", "ld1">;
3058 def LD1_3V_1D : NeonI_LDVList<0, 0b0110, 0b11, VTriple1D_operand, "ld1">;
3059
3060 defm LD1_4V : LDVList_BHSD<0b0010, "VQuad", "ld1">;
3061 def LD1_4V_1D : NeonI_LDVList<0, 0b0010, 0b11, VQuad1D_operand, "ld1">;
3062
3063 class NeonI_STVList<bit q, bits<4> opcode, bits<2> size,
3064                     RegisterOperand VecList, string asmop>
3065   : NeonI_LdStMult<q, 0, opcode, size,
3066                  (outs), (ins GPR64xsp:$Rn, VecList:$Rt),
3067                  asmop # "\t$Rt, [$Rn]",
3068                  [],
3069                  NoItinerary> {
3070   let mayStore = 1;
3071   let neverHasSideEffects = 1;
3072 }
3073
3074 multiclass STVList_BHSD<bits<4> opcode, string List, string asmop> {
3075   def _8B : NeonI_STVList<0, opcode, 0b00,
3076                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3077
3078   def _4H : NeonI_STVList<0, opcode, 0b01,
3079                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3080
3081   def _2S : NeonI_STVList<0, opcode, 0b10,
3082                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3083
3084   def _16B : NeonI_STVList<1, opcode, 0b00,
3085                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3086
3087   def _8H : NeonI_STVList<1, opcode, 0b01,
3088                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3089
3090   def _4S : NeonI_STVList<1, opcode, 0b10,
3091                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3092
3093   def _2D : NeonI_STVList<1, opcode, 0b11,
3094                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3095 }
3096
3097 // Store multiple N-element structures from N registers (N = 1,2,3,4)
3098 defm ST1 : STVList_BHSD<0b0111, "VOne", "st1">;
3099 def ST1_1D : NeonI_STVList<0, 0b0111, 0b11, VOne1D_operand, "st1">;
3100
3101 defm ST2 : STVList_BHSD<0b1000, "VPair", "st2">;
3102
3103 defm ST3 : STVList_BHSD<0b0100, "VTriple", "st3">;
3104
3105 defm ST4 : STVList_BHSD<0b0000, "VQuad", "st4">;
3106
3107 // Store multiple 1-element structures from N consecutive registers (N = 2,3,4)
3108 defm ST1_2V : STVList_BHSD<0b1010, "VPair", "st1">;
3109 def ST1_2V_1D : NeonI_STVList<0, 0b1010, 0b11, VPair1D_operand, "st1">;
3110
3111 defm ST1_3V : STVList_BHSD<0b0110, "VTriple", "st1">;
3112 def ST1_3V_1D : NeonI_STVList<0, 0b0110, 0b11, VTriple1D_operand, "st1">;
3113
3114 defm ST1_4V : STVList_BHSD<0b0010, "VQuad", "st1">;
3115 def ST1_4V_1D : NeonI_STVList<0, 0b0010, 0b11, VQuad1D_operand, "st1">;
3116
3117 // End of vector load/store multiple N-element structure(class SIMD lselem)
3118
3119 // Scalar Arithmetic
3120
3121 class NeonI_Scalar3Same_D_size<bit u, bits<5> opcode, string asmop>
3122   : NeonI_Scalar3Same<u, 0b11, opcode,
3123                 (outs FPR64:$Rd), (ins FPR64:$Rn, FPR64:$Rm),
3124                 !strconcat(asmop, " $Rd, $Rn, $Rm"),
3125                 [],
3126                 NoItinerary>;
3127
3128 multiclass NeonI_Scalar3Same_HS_sizes<bit u, bits<5> opcode,
3129                                       string asmop, bit Commutable = 0>
3130 {
3131   let isCommutable = Commutable in {
3132     def hhh : NeonI_Scalar3Same<u, 0b01, opcode,
3133                                 (outs FPR16:$Rd), (ins FPR16:$Rn, FPR16:$Rm),
3134                                 !strconcat(asmop, " $Rd, $Rn, $Rm"),
3135                                 [],
3136                                 NoItinerary>;
3137     def sss : NeonI_Scalar3Same<u, 0b10, opcode,
3138                                 (outs FPR32:$Rd), (ins FPR32:$Rn, FPR32:$Rm),
3139                                 !strconcat(asmop, " $Rd, $Rn, $Rm"),
3140                                 [],
3141                                 NoItinerary>;
3142   }
3143 }
3144
3145 multiclass NeonI_Scalar3Same_SD_sizes<bit u, bit size_high, bits<5> opcode,
3146                                       string asmop, bit Commutable = 0>
3147 {
3148   let isCommutable = Commutable in {
3149     def sss : NeonI_Scalar3Same<u, {size_high, 0b0}, opcode,
3150                                 (outs FPR32:$Rd), (ins FPR32:$Rn, FPR32:$Rm),
3151                                 !strconcat(asmop, " $Rd, $Rn, $Rm"),
3152                                 [],
3153                                 NoItinerary>;
3154     def ddd : NeonI_Scalar3Same<u, {size_high, 0b1}, opcode,
3155                                 (outs FPR64:$Rd), (ins FPR64:$Rn, FPR64:$Rm),
3156                                 !strconcat(asmop, " $Rd, $Rn, $Rm"),
3157                                 [],
3158                                 NoItinerary>;
3159   }
3160 }
3161
3162 multiclass NeonI_Scalar3Same_BHSD_sizes<bit u, bits<5> opcode,
3163                                         string asmop, bit Commutable = 0>
3164 {
3165   let isCommutable = Commutable in {
3166     def bbb : NeonI_Scalar3Same<u, 0b00, opcode,
3167                                 (outs FPR8:$Rd), (ins FPR8:$Rn, FPR8:$Rm),
3168                                 !strconcat(asmop, " $Rd, $Rn, $Rm"),
3169                                 [],
3170                                 NoItinerary>;
3171     def hhh : NeonI_Scalar3Same<u, 0b01, opcode,
3172                                 (outs FPR16:$Rd), (ins FPR16:$Rn, FPR16:$Rm),
3173                                 !strconcat(asmop, " $Rd, $Rn, $Rm"),
3174                                 [],
3175                                 NoItinerary>;
3176     def sss : NeonI_Scalar3Same<u, 0b10, opcode,
3177                                 (outs FPR32:$Rd), (ins FPR32:$Rn, FPR32:$Rm),
3178                                 !strconcat(asmop, " $Rd, $Rn, $Rm"),
3179                                 [],
3180                                 NoItinerary>;
3181     def ddd : NeonI_Scalar3Same<u, 0b11, opcode,
3182                                (outs FPR64:$Rd), (ins FPR64:$Rn, FPR64:$Rm),
3183                                !strconcat(asmop, " $Rd, $Rn, $Rm"),
3184                                [],
3185                                NoItinerary>;
3186   }
3187 }
3188
3189 multiclass Neon_Scalar3Same_D_size_patterns<SDPatternOperator opnode,
3190                                             Instruction INSTD> {
3191   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
3192             (INSTD FPR64:$Rn, FPR64:$Rm)>;
3193 }
3194
3195 multiclass Neon_Scalar3Same_BHSD_size_patterns<SDPatternOperator opnode,
3196                                                Instruction INSTB,
3197                                                Instruction INSTH,
3198                                                Instruction INSTS,
3199                                                Instruction INSTD>
3200   : Neon_Scalar3Same_D_size_patterns<opnode, INSTD> {
3201   def: Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (v1i8 FPR8:$Rm))),
3202            (INSTB FPR8:$Rn, FPR8:$Rm)>;
3203
3204   def: Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
3205            (INSTH FPR16:$Rn, FPR16:$Rm)>;
3206
3207   def: Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
3208            (INSTS FPR32:$Rn, FPR32:$Rm)>;
3209 }
3210
3211 class Neon_Scalar3Same_cmp_D_size_patterns<SDPatternOperator opnode,
3212                                            Instruction INSTD>
3213   : Pat<(v1i64 (opnode (v1i64 VPR64:$Rn), (v1i64 VPR64:$Rm))),
3214         (INSTD VPR64:$Rn, VPR64:$Rm)>;
3215
3216 multiclass Neon_Scalar3Same_HS_size_patterns<SDPatternOperator opnode,
3217                                              Instruction INSTH,
3218                                              Instruction INSTS> {
3219   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
3220             (INSTH FPR16:$Rn, FPR16:$Rm)>;
3221   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
3222             (INSTS FPR32:$Rn, FPR32:$Rm)>;
3223 }
3224
3225 multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
3226                                              Instruction INSTS,
3227                                              Instruction INSTD> {
3228   def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
3229             (INSTS FPR32:$Rn, FPR32:$Rm)>;
3230   def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3231             (INSTD FPR64:$Rn, FPR64:$Rm)>;
3232 }
3233
3234 // Scalar Two Registers Miscellaneous
3235
3236 multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
3237                                          string asmop> {
3238   def ss : NeonI_Scalar2SameMisc<u, {size_high, 0b0}, opcode,
3239                           (outs FPR32:$Rd), (ins FPR32:$Rn),
3240                           !strconcat(asmop, " $Rd, $Rn"),
3241                           [], NoItinerary>;
3242   def dd : NeonI_Scalar2SameMisc<u, {size_high, 0b1}, opcode,
3243                           (outs FPR64:$Rd), (ins FPR64:$Rn),
3244                           !strconcat(asmop, " $Rd, $Rn"),
3245                           [], NoItinerary>;
3246 }
3247
3248 multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>{
3249   def bb : NeonI_Scalar2SameMisc<u, 0b00, opcode,
3250                           (outs FPR8:$Rd), (ins FPR8:$Rn),
3251                           !strconcat(asmop, " $Rd, $Rn"),
3252                           [], NoItinerary>;
3253   def hh : NeonI_Scalar2SameMisc<u, 0b01, opcode,
3254                           (outs FPR16:$Rd), (ins FPR16:$Rn),
3255                           !strconcat(asmop, " $Rd, $Rn"),
3256                           [], NoItinerary>;
3257   def ss : NeonI_Scalar2SameMisc<u, 0b10, opcode,
3258                           (outs FPR32:$Rd), (ins FPR32:$Rn),
3259                           !strconcat(asmop, " $Rd, $Rn"),
3260                           [], NoItinerary>;
3261   def dd: NeonI_Scalar2SameMisc<u, 0b11, opcode,
3262                          (outs FPR64:$Rd), (ins FPR64:$Rn),
3263                          !strconcat(asmop, " $Rd, $Rn"),
3264                          [], NoItinerary>;
3265 }
3266
3267 multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator Sopnode,
3268                                                      SDPatternOperator Dopnode,
3269                                                      Instruction INSTS,
3270                                                      Instruction INSTD> {
3271   def : Pat<(v1f32 (Sopnode (v1i32 FPR32:$Rn))),
3272             (INSTS FPR32:$Rn)>;
3273   def : Pat<(v1f64 (Dopnode (v1i64 FPR64:$Rn))),
3274             (INSTD FPR64:$Rn)>;
3275 }
3276
3277 multiclass Neon_Scalar2SameMisc_SD_size_patterns<SDPatternOperator opnode,
3278                                                  Instruction INSTS,
3279                                                  Instruction INSTD> {
3280   def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn))),
3281             (INSTS FPR32:$Rn)>;
3282   def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))),
3283             (INSTD FPR64:$Rn)>;
3284 }
3285
3286 // AdvSIMD Scalar Two Registers Miscellaneous
3287 class NeonI_Scalar2SameMisc_cmpz_D_size<bit u, bits<5> opcode, string asmop>
3288   : NeonI_Scalar2SameMisc<u, 0b11, opcode,
3289                           (outs FPR64:$Rd), (ins FPR64:$Rn, neon_uimm0:$Imm),
3290                           !strconcat(asmop, " $Rd, $Rn, $Imm"),
3291                           [],
3292                           NoItinerary>;
3293
3294 class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode,
3295                                                 Instruction INSTD>
3296   : Pat<(v1i64 (opnode (v1i64 VPR64:$Rn), (v1i64 (bitconvert (v8i8 Neon_immAllZeros))))),
3297         (INSTD VPR64:$Rn, 0)>;
3298
3299 multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
3300                                                    Instruction INSTB,
3301                                                    Instruction INSTH,
3302                                                    Instruction INSTS,
3303                                                    Instruction INSTD> {
3304   def : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn))),
3305             (INSTB FPR8:$Rn)>;
3306   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn))),
3307             (INSTH FPR16:$Rn)>;
3308   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn))),
3309             (INSTS FPR32:$Rn)>;
3310   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))),
3311             (INSTD FPR64:$Rn)>;
3312 }
3313
3314 // Scalar Integer Add
3315 let isCommutable = 1 in {
3316 def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
3317 }
3318
3319 // Scalar Integer Sub
3320 def SUBddd : NeonI_Scalar3Same_D_size<0b1, 0b10000, "sub">;
3321
3322 // Pattern for Scalar Integer Add and Sub with D register only
3323 defm : Neon_Scalar3Same_D_size_patterns<add, ADDddd>;
3324 defm : Neon_Scalar3Same_D_size_patterns<sub, SUBddd>;
3325
3326 // Patterns to match llvm.aarch64.* intrinsic for Scalar Add, Sub
3327 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vaddds, ADDddd>;
3328 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vadddu, ADDddd>;
3329 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubds, SUBddd>;
3330 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubdu, SUBddd>;
3331
3332 // Scalar Integer Saturating Add (Signed, Unsigned)
3333 defm SQADD : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00001, "sqadd", 1>;
3334 defm UQADD : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00001, "uqadd", 1>;
3335
3336 // Scalar Integer Saturating Sub (Signed, Unsigned)
3337 defm SQSUB : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00101, "sqsub", 0>;
3338 defm UQSUB : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00101, "uqsub", 0>;
3339
3340 // Patterns to match llvm.arm.* intrinsic for
3341 // Scalar Integer Saturating Add, Sub  (Signed, Unsigned)
3342 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqadds, SQADDddd>;
3343 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqaddu, UQADDddd>;
3344 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqsubs, SQSUBddd>;
3345 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqsubu, UQSUBddd>;
3346
3347 // Patterns to match llvm.aarch64.* intrinsic for
3348 // Scalar Integer Saturating Add, Sub  (Signed, Unsigned)
3349 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqadds, SQADDbbb,
3350                                            SQADDhhh, SQADDsss, SQADDddd>;
3351 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqaddu, UQADDbbb,
3352                                            UQADDhhh, UQADDsss, UQADDddd>;
3353 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqsubs, SQSUBbbb,
3354                                            SQSUBhhh, SQSUBsss, SQSUBddd>;
3355 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqsubu, UQSUBbbb,
3356                                            UQSUBhhh, UQSUBsss, UQSUBddd>;
3357
3358 // Scalar Integer Saturating Doubling Multiply Half High
3359 defm SQDMULH : NeonI_Scalar3Same_HS_sizes<0b0, 0b10110, "sqdmulh", 1>;
3360
3361 // Scalar Integer Saturating Rounding Doubling Multiply Half High
3362 defm SQRDMULH : NeonI_Scalar3Same_HS_sizes<0b1, 0b10110, "sqrdmulh", 1>;
3363
3364 // Patterns to match llvm.arm.* intrinsic for
3365 // Scalar Integer Saturating Doubling Multiply Half High and
3366 // Scalar Integer Saturating Rounding Doubling Multiply Half High
3367 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqdmulh, SQDMULHhhh,
3368                                                                SQDMULHsss>;
3369 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqrdmulh, SQRDMULHhhh,
3370                                                                 SQRDMULHsss>;
3371
3372 // Scalar Floating-point Multiply Extended
3373 defm FMULX : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11011, "fmulx", 1>;
3374
3375 // Scalar Floating-point Reciprocal Step
3376 defm FRECPS : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11111, "frecps", 0>;
3377
3378 // Scalar Floating-point Reciprocal Square Root Step
3379 defm FRSQRTS : NeonI_Scalar3Same_SD_sizes<0b0, 0b1, 0b11111, "frsqrts", 0>;
3380
3381 // Patterns to match llvm.arm.* intrinsic for
3382 // Scalar Floating-point Reciprocal Step and
3383 // Scalar Floating-point Reciprocal Square Root Step
3384 defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrecps, FRECPSsss,
3385                                                               FRECPSddd>;
3386 defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrsqrts, FRSQRTSsss,
3387                                                                FRSQRTSddd>;
3388
3389 // Patterns to match llvm.aarch64.* intrinsic for
3390 // Scalar Floating-point Multiply Extended,
3391 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vmulx, FMULXsss,
3392                                          FMULXddd>;
3393
3394 // Scalar Integer Shift Left (Signed, Unsigned)
3395 def SSHLddd : NeonI_Scalar3Same_D_size<0b0, 0b01000, "sshl">;
3396 def USHLddd : NeonI_Scalar3Same_D_size<0b1, 0b01000, "ushl">;
3397
3398 // Patterns to match llvm.arm.* intrinsic for
3399 // Scalar Integer Shift Left (Signed, Unsigned)
3400 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshifts, SSHLddd>;
3401 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshiftu, USHLddd>;
3402
3403 // Patterns to match llvm.aarch64.* intrinsic for
3404 // Scalar Integer Shift Left (Signed, Unsigned)
3405 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshlds, SSHLddd>;
3406 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshldu, USHLddd>;
3407
3408 // Scalar Integer Saturating Shift Left (Signed, Unsigned)
3409 defm SQSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01001, "sqshl", 0>;
3410 defm UQSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01001, "uqshl", 0>;
3411
3412 // Patterns to match llvm.aarch64.* intrinsic for
3413 // Scalar  Integer Saturating Shift Letf (Signed, Unsigned)
3414 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshls, SQSHLbbb,
3415                                            SQSHLhhh, SQSHLsss, SQSHLddd>;
3416 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshlu, UQSHLbbb,
3417                                            UQSHLhhh, UQSHLsss, UQSHLddd>;
3418
3419 // Patterns to match llvm.arm.* intrinsic for
3420 // Scalar  Integer Saturating Shift Letf (Signed, Unsigned)
3421 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshifts, SQSHLddd>;
3422 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshiftu, UQSHLddd>;
3423
3424 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
3425 def SRSHLddd: NeonI_Scalar3Same_D_size<0b0, 0b01010, "srshl">;
3426 def URSHLddd: NeonI_Scalar3Same_D_size<0b1, 0b01010, "urshl">;
3427
3428 // Patterns to match llvm.aarch64.* intrinsic for
3429 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
3430 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshlds, SRSHLddd>;
3431 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshldu, URSHLddd>;
3432
3433 // Patterns to match llvm.arm.* intrinsic for
3434 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
3435 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshifts, SRSHLddd>;
3436 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshiftu, URSHLddd>;
3437
3438 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
3439 defm SQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01011, "sqrshl", 0>;
3440 defm UQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01011, "uqrshl", 0>;
3441
3442 // Patterns to match llvm.aarch64.* intrinsic for
3443 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
3444 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshls, SQRSHLbbb,
3445                                            SQRSHLhhh, SQRSHLsss, SQRSHLddd>;
3446 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb,
3447                                            UQRSHLhhh, UQRSHLsss, UQRSHLddd>;
3448
3449 // Patterns to match llvm.arm.* intrinsic for
3450 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
3451 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
3452 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
3453
3454 // Scalar Signed Integer Convert To Floating-point
3455 defm SCVTF  : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">;
3456 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_s32,
3457                                                  int_aarch64_neon_vcvtf64_s64,
3458                                                  SCVTFss, SCVTFdd>;
3459
3460 // Scalar Unsigned Integer Convert To Floating-point
3461 defm UCVTF  : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11101, "ucvtf">;
3462 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_u32,
3463                                                  int_aarch64_neon_vcvtf64_u64,
3464                                                  UCVTFss, UCVTFdd>;
3465
3466 // Scalar Floating-point Reciprocal Estimate
3467 defm FRECPE : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11101, "frecpe">;
3468 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrecpe,
3469                                              FRECPEss, FRECPEdd>;
3470
3471 // Scalar Floating-point Reciprocal Exponent
3472 defm FRECPX : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11111, "frecpx">;
3473 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpx,
3474                                              FRECPXss, FRECPXdd>;
3475
3476 // Scalar Floating-point Reciprocal Square Root Estimate
3477 defm FRSQRTE: NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11101, "frsqrte">;
3478 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrsqrte,
3479                                              FRSQRTEss, FRSQRTEdd>;
3480
3481 // Scalar Integer Compare
3482
3483 // Scalar Compare Bitwise Equal
3484 def CMEQddd: NeonI_Scalar3Same_D_size<0b1, 0b10001, "cmeq">;
3485 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vceq, CMEQddd>;
3486
3487 // Scalar Compare Signed Greather Than Or Equal
3488 def CMGEddd: NeonI_Scalar3Same_D_size<0b0, 0b00111, "cmge">;
3489 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcge, CMGEddd>;
3490
3491 // Scalar Compare Unsigned Higher Or Same
3492 def CMHSddd: NeonI_Scalar3Same_D_size<0b1, 0b00111, "cmhs">;
3493 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchs, CMHSddd>;
3494
3495 // Scalar Compare Unsigned Higher
3496 def CMHIddd: NeonI_Scalar3Same_D_size<0b1, 0b00110, "cmhi">;
3497 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchi, CMHIddd>;
3498
3499 // Scalar Compare Signed Greater Than
3500 def CMGTddd: NeonI_Scalar3Same_D_size<0b0, 0b00110, "cmgt">;
3501 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcgt, CMGTddd>;
3502
3503 // Scalar Compare Bitwise Test Bits
3504 def CMTSTddd: NeonI_Scalar3Same_D_size<0b0, 0b10001, "cmtst">;
3505 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vtstd, CMTSTddd>;
3506
3507 // Scalar Compare Bitwise Equal To Zero
3508 def CMEQddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01001, "cmeq">;
3509 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vceq,
3510                                                 CMEQddi>;
3511
3512 // Scalar Compare Signed Greather Than Or Equal To Zero
3513 def CMGEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01000, "cmge">;
3514 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcge,
3515                                                 CMGEddi>;
3516
3517 // Scalar Compare Signed Greater Than Zero
3518 def CMGTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01000, "cmgt">;
3519 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcgt,
3520                                                 CMGTddi>;
3521
3522 // Scalar Compare Signed Less Than Or Equal To Zero
3523 def CMLEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01001, "cmle">;
3524 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vclez,
3525                                                 CMLEddi>;
3526
3527 // Scalar Compare Less Than Zero
3528 def CMLTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01010, "cmlt">;
3529 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcltz,
3530                                                 CMLTddi>;
3531
3532 // Scalar Signed Saturating Absolute Value
3533 defm SQABS : NeonI_Scalar2SameMisc_BHSD_size<0b0, 0b00111, "sqabs">;
3534 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqabs,
3535                                                SQABSbb, SQABShh, SQABSss, SQABSdd>;
3536
3537 // Scalar Signed Saturating Negate
3538 defm SQNEG : NeonI_Scalar2SameMisc_BHSD_size<0b1, 0b00111, "sqneg">;
3539 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqneg,
3540                                                SQNEGbb, SQNEGhh, SQNEGss, SQNEGdd>;
3541
3542 // Scalar Reduce Pairwise
3543
3544 multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode,
3545                                      string asmop, bit Commutable = 0> {
3546   let isCommutable = Commutable in {
3547     def _D_2D : NeonI_ScalarPair<u, {size, 0b1}, opcode,
3548                                 (outs FPR64:$Rd), (ins VPR128:$Rn),
3549                                 !strconcat(asmop, " $Rd, $Rn.2d"),
3550                                 [],
3551                                 NoItinerary>;
3552   }
3553 }
3554
3555 multiclass NeonI_ScalarPair_SD_sizes<bit u, bit size, bits<5> opcode,
3556                                      string asmop, bit Commutable = 0>
3557   : NeonI_ScalarPair_D_sizes<u, size, opcode, asmop, Commutable> {
3558   let isCommutable = Commutable in {
3559     def _S_2S : NeonI_ScalarPair<u, {size, 0b0}, opcode,
3560                                 (outs FPR32:$Rd), (ins VPR64:$Rn),
3561                                 !strconcat(asmop, " $Rd, $Rn.2s"),
3562                                 [],
3563                                 NoItinerary>;
3564   }
3565 }
3566
3567 // Scalar Reduce Addition Pairwise (Integer) with
3568 // Pattern to match llvm.arm.* intrinsic
3569 defm ADDPvv : NeonI_ScalarPair_D_sizes<0b0, 0b1, 0b11011, "addp", 0>;
3570
3571 // Pattern to match llvm.aarch64.* intrinsic for
3572 // Scalar Reduce Addition Pairwise (Integer)
3573 def : Pat<(v1i64 (int_aarch64_neon_vpadd (v2i64 VPR128:$Rn))),
3574           (ADDPvv_D_2D VPR128:$Rn)>;
3575
3576 // Scalar Reduce Addition Pairwise (Floating Point)
3577 defm FADDPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01101, "faddp", 0>;
3578
3579 // Scalar Reduce Maximum Pairwise (Floating Point)
3580 defm FMAXPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01111, "fmaxp", 0>;
3581
3582 // Scalar Reduce Minimum Pairwise (Floating Point)
3583 defm FMINPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01111, "fminp", 0>;
3584
3585 // Scalar Reduce maxNum Pairwise (Floating Point)
3586 defm FMAXNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01100, "fmaxnmp", 0>;
3587
3588 // Scalar Reduce minNum Pairwise (Floating Point)
3589 defm FMINNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01100, "fminnmp", 0>;
3590
3591 multiclass Neon_ScalarPair_SD_size_patterns<SDPatternOperator opnodeS,
3592                                             SDPatternOperator opnodeD,
3593                                             Instruction INSTS,
3594                                             Instruction INSTD> {
3595   def : Pat<(v1f32 (opnodeS (v2f32 VPR64:$Rn))),
3596             (INSTS VPR64:$Rn)>;
3597   def : Pat<(v1f64 (opnodeD (v2f64 VPR128:$Rn))),
3598             (INSTD VPR128:$Rn)>;
3599 }
3600
3601 // Patterns to match llvm.aarch64.* intrinsic for
3602 // Scalar Reduce Add, Max, Min, MaxiNum, MinNum Pairwise (Floating Point)
3603 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfadd,
3604   int_aarch64_neon_vpfaddq, FADDPvv_S_2S, FADDPvv_D_2D>;
3605
3606 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmax,
3607   int_aarch64_neon_vpmaxq, FMAXPvv_S_2S, FMAXPvv_D_2D>;
3608
3609 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmin,
3610   int_aarch64_neon_vpminq, FMINPvv_S_2S, FMINPvv_D_2D>;
3611
3612 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfmaxnm,
3613   int_aarch64_neon_vpfmaxnmq, FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
3614
3615 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfminnm,
3616   int_aarch64_neon_vpfminnmq, FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
3617
3618
3619
3620 //===----------------------------------------------------------------------===//
3621 // Non-Instruction Patterns
3622 //===----------------------------------------------------------------------===//
3623
3624 // 64-bit vector bitcasts...
3625
3626 def : Pat<(v1i64 (bitconvert (v8i8  VPR64:$src))), (v1i64 VPR64:$src)>;
3627 def : Pat<(v2f32 (bitconvert (v8i8  VPR64:$src))), (v2f32 VPR64:$src)>;
3628 def : Pat<(v2i32 (bitconvert (v8i8  VPR64:$src))), (v2i32 VPR64:$src)>;
3629 def : Pat<(v4i16 (bitconvert (v8i8  VPR64:$src))), (v4i16 VPR64:$src)>;
3630
3631 def : Pat<(v1i64 (bitconvert (v4i16  VPR64:$src))), (v1i64 VPR64:$src)>;
3632 def : Pat<(v2i32 (bitconvert (v4i16  VPR64:$src))), (v2i32 VPR64:$src)>;
3633 def : Pat<(v2f32 (bitconvert (v4i16  VPR64:$src))), (v2f32 VPR64:$src)>;
3634 def : Pat<(v8i8  (bitconvert (v4i16  VPR64:$src))), (v8i8 VPR64:$src)>;
3635
3636 def : Pat<(v1i64 (bitconvert (v2i32  VPR64:$src))), (v1i64 VPR64:$src)>;
3637 def : Pat<(v2f32 (bitconvert (v2i32  VPR64:$src))), (v2f32 VPR64:$src)>;
3638 def : Pat<(v4i16 (bitconvert (v2i32  VPR64:$src))), (v4i16 VPR64:$src)>;
3639 def : Pat<(v8i8  (bitconvert (v2i32  VPR64:$src))), (v8i8 VPR64:$src)>;
3640
3641 def : Pat<(v1i64 (bitconvert (v2f32  VPR64:$src))), (v1i64 VPR64:$src)>;
3642 def : Pat<(v2i32 (bitconvert (v2f32  VPR64:$src))), (v2i32 VPR64:$src)>;
3643 def : Pat<(v4i16 (bitconvert (v2f32  VPR64:$src))), (v4i16 VPR64:$src)>;
3644 def : Pat<(v8i8  (bitconvert (v2f32  VPR64:$src))), (v8i8 VPR64:$src)>;
3645
3646 def : Pat<(v2f32 (bitconvert (v1i64  VPR64:$src))), (v2f32 VPR64:$src)>;
3647 def : Pat<(v2i32 (bitconvert (v1i64  VPR64:$src))), (v2i32 VPR64:$src)>;
3648 def : Pat<(v4i16 (bitconvert (v1i64  VPR64:$src))), (v4i16 VPR64:$src)>;
3649 def : Pat<(v8i8  (bitconvert (v1i64  VPR64:$src))), (v8i8 VPR64:$src)>;
3650
3651 // ..and 128-bit vector bitcasts...
3652
3653 def : Pat<(v2f64 (bitconvert (v16i8  VPR128:$src))), (v2f64 VPR128:$src)>;
3654 def : Pat<(v2i64 (bitconvert (v16i8  VPR128:$src))), (v2i64 VPR128:$src)>;
3655 def : Pat<(v4f32 (bitconvert (v16i8  VPR128:$src))), (v4f32 VPR128:$src)>;
3656 def : Pat<(v4i32 (bitconvert (v16i8  VPR128:$src))), (v4i32 VPR128:$src)>;
3657 def : Pat<(v8i16 (bitconvert (v16i8  VPR128:$src))), (v8i16 VPR128:$src)>;
3658
3659 def : Pat<(v2f64 (bitconvert (v8i16  VPR128:$src))), (v2f64 VPR128:$src)>;
3660 def : Pat<(v2i64 (bitconvert (v8i16  VPR128:$src))), (v2i64 VPR128:$src)>;
3661 def : Pat<(v4i32 (bitconvert (v8i16  VPR128:$src))), (v4i32 VPR128:$src)>;
3662 def : Pat<(v4f32 (bitconvert (v8i16  VPR128:$src))), (v4f32 VPR128:$src)>;
3663 def : Pat<(v16i8 (bitconvert (v8i16  VPR128:$src))), (v16i8 VPR128:$src)>;
3664
3665 def : Pat<(v2f64 (bitconvert (v4i32  VPR128:$src))), (v2f64 VPR128:$src)>;
3666 def : Pat<(v2i64 (bitconvert (v4i32  VPR128:$src))), (v2i64 VPR128:$src)>;
3667 def : Pat<(v4f32 (bitconvert (v4i32  VPR128:$src))), (v4f32 VPR128:$src)>;
3668 def : Pat<(v8i16 (bitconvert (v4i32  VPR128:$src))), (v8i16 VPR128:$src)>;
3669 def : Pat<(v16i8 (bitconvert (v4i32  VPR128:$src))), (v16i8 VPR128:$src)>;
3670
3671 def : Pat<(v2f64 (bitconvert (v4f32  VPR128:$src))), (v2f64 VPR128:$src)>;
3672 def : Pat<(v2i64 (bitconvert (v4f32  VPR128:$src))), (v2i64 VPR128:$src)>;
3673 def : Pat<(v4i32 (bitconvert (v4f32  VPR128:$src))), (v4i32 VPR128:$src)>;
3674 def : Pat<(v8i16 (bitconvert (v4f32  VPR128:$src))), (v8i16 VPR128:$src)>;
3675 def : Pat<(v16i8 (bitconvert (v4f32  VPR128:$src))), (v16i8 VPR128:$src)>;
3676
3677 def : Pat<(v2f64 (bitconvert (v2i64  VPR128:$src))), (v2f64 VPR128:$src)>;
3678 def : Pat<(v4f32 (bitconvert (v2i64  VPR128:$src))), (v4f32 VPR128:$src)>;
3679 def : Pat<(v4i32 (bitconvert (v2i64  VPR128:$src))), (v4i32 VPR128:$src)>;
3680 def : Pat<(v8i16 (bitconvert (v2i64  VPR128:$src))), (v8i16 VPR128:$src)>;
3681 def : Pat<(v16i8 (bitconvert (v2i64  VPR128:$src))), (v16i8 VPR128:$src)>;
3682
3683 def : Pat<(v2i64 (bitconvert (v2f64  VPR128:$src))), (v2i64 VPR128:$src)>;
3684 def : Pat<(v4f32 (bitconvert (v2f64  VPR128:$src))), (v4f32 VPR128:$src)>;
3685 def : Pat<(v4i32 (bitconvert (v2f64  VPR128:$src))), (v4i32 VPR128:$src)>;
3686 def : Pat<(v8i16 (bitconvert (v2f64  VPR128:$src))), (v8i16 VPR128:$src)>;
3687 def : Pat<(v16i8 (bitconvert (v2f64  VPR128:$src))), (v16i8 VPR128:$src)>;
3688
3689
3690 // ...and scalar bitcasts...
3691 def : Pat<(f16 (bitconvert (v1i16  FPR16:$src))), (f16 FPR16:$src)>;
3692 def : Pat<(f32 (bitconvert (v1i32  FPR32:$src))), (f32 FPR32:$src)>;
3693 def : Pat<(f64 (bitconvert (v1i64  FPR64:$src))), (f64 FPR64:$src)>;
3694 def : Pat<(f32 (bitconvert (v1f32  FPR32:$src))), (f32 FPR32:$src)>;
3695 def : Pat<(f64 (bitconvert (v1f64  FPR64:$src))), (f64 FPR64:$src)>;
3696
3697 def : Pat<(i64 (bitconvert (v1i64  FPR64:$src))), (FMOVxd $src)>;
3698 def : Pat<(i32 (bitconvert (v1i32  FPR32:$src))), (FMOVws $src)>;
3699
3700 def : Pat<(v8i8  (bitconvert (v1i64  VPR64:$src))), (v8i8 VPR64:$src)>;
3701 def : Pat<(v4i16 (bitconvert (v1i64  VPR64:$src))), (v4i16 VPR64:$src)>;
3702 def : Pat<(v2i32 (bitconvert (v1i64  VPR64:$src))), (v2i32 VPR64:$src)>;
3703
3704 def : Pat<(f64   (bitconvert (v8i8  VPR64:$src))), (f64 VPR64:$src)>;
3705 def : Pat<(f64   (bitconvert (v4i16  VPR64:$src))), (f64 VPR64:$src)>;
3706 def : Pat<(f64   (bitconvert (v2i32  VPR64:$src))), (f64 VPR64:$src)>;
3707 def : Pat<(f64   (bitconvert (v2f32  VPR64:$src))), (f64 VPR64:$src)>;
3708 def : Pat<(f64   (bitconvert (v1i64  VPR64:$src))), (f64 VPR64:$src)>;
3709
3710 def : Pat<(f128  (bitconvert (v16i8  VPR128:$src))), (f128 VPR128:$src)>;
3711 def : Pat<(f128  (bitconvert (v8i16  VPR128:$src))), (f128 VPR128:$src)>;
3712 def : Pat<(f128  (bitconvert (v4i32  VPR128:$src))), (f128 VPR128:$src)>;
3713 def : Pat<(f128  (bitconvert (v2i64  VPR128:$src))), (f128 VPR128:$src)>;
3714 def : Pat<(f128  (bitconvert (v4f32  VPR128:$src))), (f128 VPR128:$src)>;
3715 def : Pat<(f128  (bitconvert (v2f64  VPR128:$src))), (f128 VPR128:$src)>;
3716
3717 def : Pat<(v1i16 (bitconvert (f16  FPR16:$src))), (v1i16 FPR16:$src)>;
3718 def : Pat<(v1i32 (bitconvert (f32  FPR32:$src))), (v1i32 FPR32:$src)>;
3719 def : Pat<(v1i64 (bitconvert (f64  FPR64:$src))), (v1i64 FPR64:$src)>;
3720 def : Pat<(v1f32 (bitconvert (f32  FPR32:$src))), (v1f32 FPR32:$src)>;
3721 def : Pat<(v1f64 (bitconvert (f64  FPR64:$src))), (v1f64 FPR64:$src)>;
3722
3723 def : Pat<(v1i64 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
3724 def : Pat<(v1i32 (bitconvert (i32  GPR32:$src))), (FMOVsw $src)>;
3725
3726 def : Pat<(v8i8   (bitconvert (f64   FPR64:$src))), (v8i8 FPR64:$src)>;
3727 def : Pat<(v4i16  (bitconvert (f64   FPR64:$src))), (v4i16 FPR64:$src)>;
3728 def : Pat<(v2i32  (bitconvert (f64   FPR64:$src))), (v2i32 FPR64:$src)>;
3729 def : Pat<(v2f32  (bitconvert (f64   FPR64:$src))), (v2f32 FPR64:$src)>;
3730 def : Pat<(v1i64  (bitconvert (f64   FPR64:$src))), (v1i64 FPR64:$src)>;
3731
3732 def : Pat<(v16i8  (bitconvert (f128   FPR128:$src))), (v16i8 FPR128:$src)>;
3733 def : Pat<(v8i16  (bitconvert (f128   FPR128:$src))), (v8i16 FPR128:$src)>;
3734 def : Pat<(v4i32  (bitconvert (f128   FPR128:$src))), (v4i32 FPR128:$src)>;
3735 def : Pat<(v2i64  (bitconvert (f128   FPR128:$src))), (v2i64 FPR128:$src)>;
3736 def : Pat<(v4f32  (bitconvert (f128   FPR128:$src))), (v4f32 FPR128:$src)>;
3737 def : Pat<(v2f64  (bitconvert (f128   FPR128:$src))), (v2f64 FPR128:$src)>;
3738
3739 def neon_uimm0_bare : Operand<i64>,
3740                         ImmLeaf<i64, [{return Imm == 0;}]> {
3741   let ParserMatchClass = neon_uimm0_asmoperand;
3742   let PrintMethod = "printNeonUImm8OperandBare";
3743 }
3744
3745 def neon_uimm1_bare : Operand<i64>,
3746                         ImmLeaf<i64, [{(void)Imm; return true;}]> {
3747   let ParserMatchClass = neon_uimm1_asmoperand;
3748   let PrintMethod = "printNeonUImm8OperandBare";
3749 }
3750
3751 def neon_uimm2_bare : Operand<i64>,
3752                         ImmLeaf<i64, [{(void)Imm; return true;}]> {
3753   let ParserMatchClass = neon_uimm2_asmoperand;
3754   let PrintMethod = "printNeonUImm8OperandBare";
3755 }
3756
3757 def neon_uimm3_bare : Operand<i64>,
3758                         ImmLeaf<i64, [{(void)Imm; return true;}]> {
3759   let ParserMatchClass = uimm3_asmoperand;
3760   let PrintMethod = "printNeonUImm8OperandBare";
3761 }
3762
3763 def neon_uimm4_bare : Operand<i64>,
3764                         ImmLeaf<i64, [{(void)Imm; return true;}]> {
3765   let ParserMatchClass = uimm4_asmoperand;
3766   let PrintMethod = "printNeonUImm8OperandBare";
3767 }
3768
3769 class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
3770                      RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
3771   : NeonI_copy<0b1, 0b0, 0b0011,
3772                (outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
3773                asmop # "\t$Rd." # Res # "[$Imm], $Rn",
3774                [(set (ResTy VPR128:$Rd),
3775                  (ResTy (vector_insert
3776                    (ResTy VPR128:$src),
3777                    (OpTy OpGPR:$Rn),
3778                    (OpImm:$Imm))))],
3779                NoItinerary> {
3780   bits<4> Imm;
3781   let Constraints = "$src = $Rd";
3782 }
3783
3784 // The followings are for instruction class (3V Elem)
3785
3786 // Variant 1
3787
3788 class NI_2VE<bit q, bit u, bits<2> size, bits<4> opcode,
3789              string asmop, string ResS, string OpS, string EleOpS,
3790              Operand OpImm, RegisterOperand ResVPR,
3791              RegisterOperand OpVPR, RegisterOperand EleOpVPR>
3792   : NeonI_2VElem<q, u, size, opcode,
3793                  (outs ResVPR:$Rd), (ins ResVPR:$src, OpVPR:$Rn,
3794                                          EleOpVPR:$Re, OpImm:$Index),
3795                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
3796                  ", $Re." # EleOpS # "[$Index]",
3797                  [],
3798                  NoItinerary> {
3799   bits<3> Index;
3800   bits<5> Re;
3801
3802   let Constraints = "$src = $Rd";
3803 }
3804
3805 multiclass NI_2VE_v1<bit u, bits<4> opcode, string asmop>
3806 {
3807   // vector register class for element is always 128-bit to cover the max index
3808   def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
3809                      neon_uimm2_bare, VPR64, VPR64, VPR128> {
3810     let Inst{11} = {Index{1}};
3811     let Inst{21} = {Index{0}};
3812     let Inst{20-16} = Re;
3813   }
3814
3815   def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
3816                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
3817     let Inst{11} = {Index{1}};
3818     let Inst{21} = {Index{0}};
3819     let Inst{20-16} = Re;
3820   }
3821
3822   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
3823   def _4h8h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
3824                      neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
3825     let Inst{11} = {Index{2}};
3826     let Inst{21} = {Index{1}};
3827     let Inst{20} = {Index{0}};
3828     let Inst{19-16} = Re{3-0};
3829   }
3830
3831   def _8h8h : NI_2VE<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
3832                      neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
3833     let Inst{11} = {Index{2}};
3834     let Inst{21} = {Index{1}};
3835     let Inst{20} = {Index{0}};
3836     let Inst{19-16} = Re{3-0};
3837   }
3838 }
3839
3840 defm MLAvve : NI_2VE_v1<0b1, 0b0000, "mla">;
3841 defm MLSvve : NI_2VE_v1<0b1, 0b0100, "mls">;
3842
3843 // Pattern for lane in 128-bit vector
3844 class NI_2VE_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
3845                    RegisterOperand ResVPR, RegisterOperand OpVPR,
3846                    RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
3847                    ValueType EleOpTy, SDPatternOperator coreop>
3848   : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
3849           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
3850         (INST ResVPR:$src, OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
3851
3852 // Pattern for lane in 64-bit vector
3853 class NI_2VE_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
3854                   RegisterOperand ResVPR, RegisterOperand OpVPR,
3855                   RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
3856                   ValueType EleOpTy, SDPatternOperator coreop>
3857   : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
3858           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
3859         (INST ResVPR:$src, OpVPR:$Rn,
3860           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
3861
3862 multiclass NI_2VE_v1_pat<string subop, SDPatternOperator op>
3863 {
3864   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
3865                      op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32,
3866                      BinOpFrag<(Neon_vduplane
3867                                  (Neon_low4S node:$LHS), node:$RHS)>>;
3868
3869   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
3870                      op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32,
3871                      BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
3872
3873   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
3874                      op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16,
3875                      BinOpFrag<(Neon_vduplane
3876                                  (Neon_low8H node:$LHS), node:$RHS)>>;
3877
3878   def : NI_2VE_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
3879                      op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16,
3880                      BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
3881
3882   // Index can only be half of the max value for lane in 64-bit vector
3883
3884   def : NI_2VE_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
3885                     op, VPR64, VPR64, VPR64, v2i32, v2i32, v2i32,
3886                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
3887
3888   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4s"), neon_uimm1_bare,
3889                     op, VPR128, VPR128, VPR64, v4i32, v4i32, v2i32,
3890                     BinOpFrag<(Neon_vduplane
3891                                 (Neon_combine_4S node:$LHS, undef),
3892                                  node:$RHS)>>;
3893
3894   def : NI_2VE_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
3895                     op, VPR64, VPR64, VPR64Lo, v4i16, v4i16, v4i16,
3896                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
3897
3898   def : NI_2VE_lane<!cast<Instruction>(subop # "_8h8h"), neon_uimm2_bare,
3899                     op, VPR128, VPR128, VPR64Lo, v8i16, v8i16, v4i16,
3900                     BinOpFrag<(Neon_vduplane
3901                                 (Neon_combine_8H node:$LHS, undef),
3902                                 node:$RHS)>>;
3903 }
3904
3905 defm MLA_lane_v1 : NI_2VE_v1_pat<"MLAvve", Neon_mla>;
3906 defm MLS_lane_v1 : NI_2VE_v1_pat<"MLSvve", Neon_mls>;
3907
3908 class NI_2VE_2op<bit q, bit u, bits<2> size, bits<4> opcode,
3909                  string asmop, string ResS, string OpS, string EleOpS,
3910                  Operand OpImm, RegisterOperand ResVPR,
3911                  RegisterOperand OpVPR, RegisterOperand EleOpVPR>
3912   : NeonI_2VElem<q, u, size, opcode,
3913                  (outs ResVPR:$Rd), (ins OpVPR:$Rn,
3914                                          EleOpVPR:$Re, OpImm:$Index),
3915                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
3916                  ", $Re." # EleOpS # "[$Index]",
3917                  [],
3918                  NoItinerary> {
3919   bits<3> Index;
3920   bits<5> Re;
3921 }
3922
3923 multiclass NI_2VE_v1_2op<bit u, bits<4> opcode, string asmop>
3924 {
3925   // vector register class for element is always 128-bit to cover the max index
3926   def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
3927                          neon_uimm2_bare, VPR64, VPR64, VPR128> {
3928     let Inst{11} = {Index{1}};
3929     let Inst{21} = {Index{0}};
3930     let Inst{20-16} = Re;
3931   }
3932
3933   def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
3934                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
3935     let Inst{11} = {Index{1}};
3936     let Inst{21} = {Index{0}};
3937     let Inst{20-16} = Re;
3938   }
3939
3940   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
3941   def _4h8h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
3942                          neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
3943     let Inst{11} = {Index{2}};
3944     let Inst{21} = {Index{1}};
3945     let Inst{20} = {Index{0}};
3946     let Inst{19-16} = Re{3-0};
3947   }
3948
3949   def _8h8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
3950                          neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
3951     let Inst{11} = {Index{2}};
3952     let Inst{21} = {Index{1}};
3953     let Inst{20} = {Index{0}};
3954     let Inst{19-16} = Re{3-0};
3955   }
3956 }
3957
3958 defm MULve : NI_2VE_v1_2op<0b0, 0b1000, "mul">;
3959 defm SQDMULHve : NI_2VE_v1_2op<0b0, 0b1100, "sqdmulh">;
3960 defm SQRDMULHve : NI_2VE_v1_2op<0b0, 0b1101, "sqrdmulh">;
3961
3962 // Pattern for lane in 128-bit vector
3963 class NI_2VE_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
3964                        RegisterOperand OpVPR, RegisterOperand EleOpVPR,
3965                        ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
3966                        SDPatternOperator coreop>
3967   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
3968           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
3969         (INST OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
3970
3971 // Pattern for lane in 64-bit vector
3972 class NI_2VE_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
3973                       RegisterOperand OpVPR, RegisterOperand EleOpVPR,
3974                       ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
3975                       SDPatternOperator coreop>
3976   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
3977           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
3978         (INST OpVPR:$Rn,
3979           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
3980
3981 multiclass NI_2VE_mul_v1_pat<string subop, SDPatternOperator op>
3982 {
3983   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
3984                          op, VPR64, VPR128, v2i32, v2i32, v4i32,
3985                          BinOpFrag<(Neon_vduplane
3986                                      (Neon_low4S node:$LHS), node:$RHS)>>;
3987
3988   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
3989                          op, VPR128, VPR128, v4i32, v4i32, v4i32,
3990                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
3991
3992   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
3993                          op, VPR64, VPR128Lo, v4i16, v4i16, v8i16,
3994                          BinOpFrag<(Neon_vduplane
3995                                     (Neon_low8H node:$LHS), node:$RHS)>>;
3996
3997   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
3998                          op, VPR128, VPR128Lo, v8i16, v8i16, v8i16,
3999                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4000
4001   // Index can only be half of the max value for lane in 64-bit vector
4002
4003   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
4004                         op, VPR64, VPR64, v2i32, v2i32, v2i32,
4005                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4006
4007   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4s"), neon_uimm1_bare,
4008                         op, VPR128, VPR64, v4i32, v4i32, v2i32,
4009                         BinOpFrag<(Neon_vduplane
4010                                     (Neon_combine_4S node:$LHS, undef),
4011                                      node:$RHS)>>;
4012
4013   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
4014                         op, VPR64, VPR64Lo, v4i16, v4i16, v4i16,
4015                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4016
4017   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_8h8h"), neon_uimm2_bare,
4018                         op, VPR128, VPR64Lo, v8i16, v8i16, v4i16,
4019                         BinOpFrag<(Neon_vduplane
4020                                     (Neon_combine_8H node:$LHS, undef),
4021                                     node:$RHS)>>;
4022 }
4023
4024 defm MUL_lane_v1 : NI_2VE_mul_v1_pat<"MULve", mul>;
4025 defm SQDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQDMULHve", int_arm_neon_vqdmulh>;
4026 defm SQRDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQRDMULHve", int_arm_neon_vqrdmulh>;
4027
4028 // Variant 2
4029
4030 multiclass NI_2VE_v2_2op<bit u, bits<4> opcode, string asmop>
4031 {
4032   // vector register class for element is always 128-bit to cover the max index
4033   def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
4034                          neon_uimm2_bare, VPR64, VPR64, VPR128> {
4035     let Inst{11} = {Index{1}};
4036     let Inst{21} = {Index{0}};
4037     let Inst{20-16} = Re;
4038   }
4039
4040   def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
4041                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
4042     let Inst{11} = {Index{1}};
4043     let Inst{21} = {Index{0}};
4044     let Inst{20-16} = Re;
4045   }
4046
4047   // _1d2d doesn't exist!
4048
4049   def _2d2d : NI_2VE_2op<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
4050                          neon_uimm1_bare, VPR128, VPR128, VPR128> {
4051     let Inst{11} = {Index{0}};
4052     let Inst{21} = 0b0;
4053     let Inst{20-16} = Re;
4054   }
4055 }
4056
4057 defm FMULve : NI_2VE_v2_2op<0b0, 0b1001, "fmul">;
4058 defm FMULXve : NI_2VE_v2_2op<0b1, 0b1001, "fmulx">;
4059
4060 class NI_2VE_mul_lane_2d<Instruction INST, Operand OpImm, SDPatternOperator op,
4061                          RegisterOperand OpVPR, RegisterOperand EleOpVPR,
4062                          ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
4063                          SDPatternOperator coreop>
4064   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
4065           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (EleOpTy EleOpVPR:$Re))))),
4066         (INST OpVPR:$Rn,
4067           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), 0)>;
4068
4069 multiclass NI_2VE_mul_v2_pat<string subop, SDPatternOperator op>
4070 {
4071   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
4072                          op, VPR64, VPR128, v2f32, v2f32, v4f32,
4073                          BinOpFrag<(Neon_vduplane
4074                                      (Neon_low4f node:$LHS), node:$RHS)>>;
4075
4076   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
4077                          op, VPR128, VPR128, v4f32, v4f32, v4f32,
4078                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4079
4080   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
4081                          op, VPR128, VPR128, v2f64, v2f64, v2f64,
4082                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4083
4084   // Index can only be half of the max value for lane in 64-bit vector
4085
4086   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
4087                         op, VPR64, VPR64, v2f32, v2f32, v2f32,
4088                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4089
4090   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4s"), neon_uimm1_bare,
4091                         op, VPR128, VPR64, v4f32, v4f32, v2f32,
4092                         BinOpFrag<(Neon_vduplane
4093                                     (Neon_combine_4f node:$LHS, undef),
4094                                     node:$RHS)>>;
4095
4096   def : NI_2VE_mul_lane_2d<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
4097                            op, VPR128, VPR64, v2f64, v2f64, v1f64,
4098                            BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
4099 }
4100
4101 defm FMUL_lane_v2 : NI_2VE_mul_v2_pat<"FMULve", fmul>;
4102 defm FMULX_lane_v2 : NI_2VE_mul_v2_pat<"FMULXve", int_aarch64_neon_vmulx>;
4103
4104 // The followings are patterns using fma
4105 // -ffp-contract=fast generates fma
4106
4107 multiclass NI_2VE_v2<bit u, bits<4> opcode, string asmop>
4108 {
4109   // vector register class for element is always 128-bit to cover the max index
4110   def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
4111                      neon_uimm2_bare, VPR64, VPR64, VPR128> {
4112     let Inst{11} = {Index{1}};
4113     let Inst{21} = {Index{0}};
4114     let Inst{20-16} = Re;
4115   }
4116
4117   def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
4118                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
4119     let Inst{11} = {Index{1}};
4120     let Inst{21} = {Index{0}};
4121     let Inst{20-16} = Re;
4122   }
4123
4124   // _1d2d doesn't exist!
4125
4126   def _2d2d : NI_2VE<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
4127                      neon_uimm1_bare, VPR128, VPR128, VPR128> {
4128     let Inst{11} = {Index{0}};
4129     let Inst{21} = 0b0;
4130     let Inst{20-16} = Re;
4131   }
4132 }
4133
4134 defm FMLAvve : NI_2VE_v2<0b0, 0b0001, "fmla">;
4135 defm FMLSvve : NI_2VE_v2<0b0, 0b0101, "fmls">;
4136
4137 // Pattern for lane in 128-bit vector
4138 class NI_2VEswap_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
4139                        RegisterOperand ResVPR, RegisterOperand OpVPR,
4140                        ValueType ResTy, ValueType OpTy,
4141                        SDPatternOperator coreop>
4142   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
4143                    (ResTy ResVPR:$src), (ResTy ResVPR:$Rn))),
4144         (INST ResVPR:$src, ResVPR:$Rn, OpVPR:$Re, OpImm:$Index)>;
4145
4146 // Pattern for lane in 64-bit vector
4147 class NI_2VEswap_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
4148                       RegisterOperand ResVPR, RegisterOperand OpVPR,
4149                       ValueType ResTy, ValueType OpTy,
4150                       SDPatternOperator coreop>
4151   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
4152                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
4153         (INST ResVPR:$src, ResVPR:$Rn,
4154           (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), OpImm:$Index)>;
4155
4156 // Pattern for lane in 64-bit vector
4157 class NI_2VEswap_lane_2d2d<Instruction INST, Operand OpImm,
4158                            SDPatternOperator op,
4159                            RegisterOperand ResVPR, RegisterOperand OpVPR,
4160                            ValueType ResTy, ValueType OpTy,
4161                            SDPatternOperator coreop>
4162   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (OpTy OpVPR:$Re))),
4163                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
4164         (INST ResVPR:$src, ResVPR:$Rn,
4165           (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), 0)>;
4166
4167
4168 multiclass NI_2VE_fma_v2_pat<string subop, SDPatternOperator op>
4169 {
4170   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
4171                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
4172                          BinOpFrag<(Neon_vduplane
4173                                      (Neon_low4f node:$LHS), node:$RHS)>>;
4174
4175   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
4176                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
4177                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4178
4179   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
4180                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
4181                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4182
4183   // Index can only be half of the max value for lane in 64-bit vector
4184
4185   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
4186                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
4187                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4188
4189   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
4190                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
4191                         BinOpFrag<(Neon_vduplane
4192                                     (Neon_combine_4f node:$LHS, undef),
4193                                     node:$RHS)>>;
4194
4195   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
4196                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
4197                              BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
4198 }
4199
4200 defm FMLA_lane_v2_s : NI_2VE_fma_v2_pat<"FMLAvve", fma>;
4201
4202 multiclass NI_2VE_fms_v2_pat<string subop, SDPatternOperator op>
4203 {
4204   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
4205                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
4206                          BinOpFrag<(fneg (Neon_vduplane
4207                                      (Neon_low4f node:$LHS), node:$RHS))>>;
4208
4209   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
4210                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
4211                          BinOpFrag<(Neon_vduplane
4212                                      (Neon_low4f (fneg node:$LHS)),
4213                                      node:$RHS)>>;
4214
4215   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
4216                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
4217                          BinOpFrag<(fneg (Neon_vduplane
4218                                      node:$LHS, node:$RHS))>>;
4219
4220   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
4221                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
4222                          BinOpFrag<(Neon_vduplane
4223                                      (fneg node:$LHS), node:$RHS)>>;
4224
4225   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
4226                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
4227                          BinOpFrag<(fneg (Neon_vduplane
4228                                      node:$LHS, node:$RHS))>>;
4229
4230   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
4231                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
4232                          BinOpFrag<(Neon_vduplane
4233                                      (fneg node:$LHS), node:$RHS)>>;
4234
4235   // Index can only be half of the max value for lane in 64-bit vector
4236
4237   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
4238                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
4239                         BinOpFrag<(fneg (Neon_vduplane
4240                                     node:$LHS, node:$RHS))>>;
4241
4242   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
4243                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
4244                         BinOpFrag<(Neon_vduplane
4245                                     (fneg node:$LHS), node:$RHS)>>;
4246
4247   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
4248                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
4249                         BinOpFrag<(fneg (Neon_vduplane
4250                                     (Neon_combine_4f node:$LHS, undef),
4251                                     node:$RHS))>>;
4252
4253   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
4254                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
4255                         BinOpFrag<(Neon_vduplane
4256                                     (Neon_combine_4f (fneg node:$LHS), undef),
4257                                     node:$RHS)>>;
4258
4259   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
4260                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
4261                              BinOpFrag<(fneg (Neon_combine_2d
4262                                          node:$LHS, node:$RHS))>>;
4263
4264   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
4265                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
4266                              BinOpFrag<(Neon_combine_2d
4267                                          (fneg node:$LHS), (fneg node:$RHS))>>;
4268 }
4269
4270 defm FMLS_lane_v2_s : NI_2VE_fms_v2_pat<"FMLSvve", fma>;
4271
4272 // Variant 3: Long type
4273 // E.g. SMLAL : 4S/4H/H (v0-v15), 2D/2S/S
4274 //      SMLAL2: 4S/8H/H (v0-v15), 2D/4S/S
4275
4276 multiclass NI_2VE_v3<bit u, bits<4> opcode, string asmop>
4277 {
4278   // vector register class for element is always 128-bit to cover the max index
4279   def _2d2s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
4280                      neon_uimm2_bare, VPR128, VPR64, VPR128> {
4281     let Inst{11} = {Index{1}};
4282     let Inst{21} = {Index{0}};
4283     let Inst{20-16} = Re;
4284   }
4285
4286   def _2d4s : NI_2VE<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
4287                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
4288     let Inst{11} = {Index{1}};
4289     let Inst{21} = {Index{0}};
4290     let Inst{20-16} = Re;
4291   }
4292
4293   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
4294   def _4s8h : NI_2VE<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
4295                      neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
4296     let Inst{11} = {Index{2}};
4297     let Inst{21} = {Index{1}};
4298     let Inst{20} = {Index{0}};
4299     let Inst{19-16} = Re{3-0};
4300   }
4301
4302   def _4s4h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
4303                      neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
4304     let Inst{11} = {Index{2}};
4305     let Inst{21} = {Index{1}};
4306     let Inst{20} = {Index{0}};
4307     let Inst{19-16} = Re{3-0};
4308   }
4309 }
4310
4311 defm SMLALvve : NI_2VE_v3<0b0, 0b0010, "smlal">;
4312 defm UMLALvve : NI_2VE_v3<0b1, 0b0010, "umlal">;
4313 defm SMLSLvve : NI_2VE_v3<0b0, 0b0110, "smlsl">;
4314 defm UMLSLvve : NI_2VE_v3<0b1, 0b0110, "umlsl">;
4315 defm SQDMLALvve : NI_2VE_v3<0b0, 0b0011, "sqdmlal">;
4316 defm SQDMLSLvve : NI_2VE_v3<0b0, 0b0111, "sqdmlsl">;
4317
4318 multiclass NI_2VE_v3_2op<bit u, bits<4> opcode, string asmop>
4319 {
4320   // vector register class for element is always 128-bit to cover the max index
4321   def _2d2s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
4322                          neon_uimm2_bare, VPR128, VPR64, VPR128> {
4323     let Inst{11} = {Index{1}};
4324     let Inst{21} = {Index{0}};
4325     let Inst{20-16} = Re;
4326   }
4327
4328   def _2d4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
4329                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
4330     let Inst{11} = {Index{1}};
4331     let Inst{21} = {Index{0}};
4332     let Inst{20-16} = Re;
4333   }
4334
4335   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
4336   def _4s8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
4337                          neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
4338     let Inst{11} = {Index{2}};
4339     let Inst{21} = {Index{1}};
4340     let Inst{20} = {Index{0}};
4341     let Inst{19-16} = Re{3-0};
4342   }
4343
4344   def _4s4h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
4345                          neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
4346     let Inst{11} = {Index{2}};
4347     let Inst{21} = {Index{1}};
4348     let Inst{20} = {Index{0}};
4349     let Inst{19-16} = Re{3-0};
4350   }
4351 }
4352
4353 defm SMULLve : NI_2VE_v3_2op<0b0, 0b1010, "smull">;
4354 defm UMULLve : NI_2VE_v3_2op<0b1, 0b1010, "umull">;
4355 defm SQDMULLve : NI_2VE_v3_2op<0b0, 0b1011, "sqdmull">;
4356
4357 // Pattern for lane in 128-bit vector
4358 class NI_2VEL2_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
4359                      RegisterOperand EleOpVPR, ValueType ResTy,
4360                      ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
4361                      SDPatternOperator hiop, SDPatternOperator coreop>
4362   : Pat<(ResTy (op (ResTy VPR128:$src),
4363           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
4364           (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
4365         (INST VPR128:$src, VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
4366
4367 // Pattern for lane in 64-bit vector
4368 class NI_2VEL2_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
4369                     RegisterOperand EleOpVPR, ValueType ResTy,
4370                     ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
4371                     SDPatternOperator hiop, SDPatternOperator coreop>
4372   : Pat<(ResTy (op (ResTy VPR128:$src),
4373           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
4374           (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
4375         (INST VPR128:$src, VPR128:$Rn,
4376           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
4377
4378 multiclass NI_2VEL_v3_pat<string subop, SDPatternOperator op>
4379 {
4380   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
4381                      op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16,
4382                      BinOpFrag<(Neon_vduplane
4383                                  (Neon_low8H node:$LHS), node:$RHS)>>;
4384
4385   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
4386                      op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32,
4387                      BinOpFrag<(Neon_vduplane
4388                                  (Neon_low4S node:$LHS), node:$RHS)>>;
4389
4390   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
4391                        op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H,
4392                        BinOpFrag<(Neon_vduplane
4393                                    (Neon_low8H node:$LHS), node:$RHS)>>;
4394
4395   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
4396                        op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S,
4397                        BinOpFrag<(Neon_vduplane
4398                                    (Neon_low4S node:$LHS), node:$RHS)>>;
4399
4400   // Index can only be half of the max value for lane in 64-bit vector
4401
4402   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
4403                     op, VPR128, VPR64, VPR64Lo, v4i32, v4i16, v4i16,
4404                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4405
4406   def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
4407                     op, VPR128, VPR64, VPR64, v2i64, v2i32, v2i32,
4408                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4409
4410   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
4411                       op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H,
4412                       BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4413
4414   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
4415                       op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S,
4416                       BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4417 }
4418
4419 defm SMLAL_lane_v3 : NI_2VEL_v3_pat<"SMLALvve", Neon_smlal>;
4420 defm UMLAL_lane_v3 : NI_2VEL_v3_pat<"UMLALvve", Neon_umlal>;
4421 defm SMLSL_lane_v3 : NI_2VEL_v3_pat<"SMLSLvve", Neon_smlsl>;
4422 defm UMLSL_lane_v3 : NI_2VEL_v3_pat<"UMLSLvve", Neon_umlsl>;
4423
4424 // Pattern for lane in 128-bit vector
4425 class NI_2VEL2_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
4426                          RegisterOperand EleOpVPR, ValueType ResTy,
4427                          ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
4428                          SDPatternOperator hiop, SDPatternOperator coreop>
4429   : Pat<(ResTy (op
4430           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
4431           (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
4432         (INST VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
4433
4434 // Pattern for lane in 64-bit vector
4435 class NI_2VEL2_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
4436                         RegisterOperand EleOpVPR, ValueType ResTy,
4437                         ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
4438                         SDPatternOperator hiop, SDPatternOperator coreop>
4439   : Pat<(ResTy (op
4440           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
4441           (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
4442         (INST VPR128:$Rn,
4443           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
4444
4445 multiclass NI_2VEL_mul_v3_pat<string subop, SDPatternOperator op>
4446 {
4447   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
4448                          op, VPR64, VPR128Lo, v4i32, v4i16, v8i16,
4449                          BinOpFrag<(Neon_vduplane
4450                                      (Neon_low8H node:$LHS), node:$RHS)>>;
4451
4452   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
4453                          op, VPR64, VPR128, v2i64, v2i32, v4i32,
4454                          BinOpFrag<(Neon_vduplane
4455                                      (Neon_low4S node:$LHS), node:$RHS)>>;
4456
4457   def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
4458                            op, VPR128Lo, v4i32, v8i16, v8i16, v4i16,
4459                            Neon_High8H,
4460                            BinOpFrag<(Neon_vduplane
4461                                        (Neon_low8H node:$LHS), node:$RHS)>>;
4462
4463   def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
4464                            op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S,
4465                            BinOpFrag<(Neon_vduplane
4466                                        (Neon_low4S node:$LHS), node:$RHS)>>;
4467
4468   // Index can only be half of the max value for lane in 64-bit vector
4469
4470   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
4471                         op, VPR64, VPR64Lo, v4i32, v4i16, v4i16,
4472                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4473
4474   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
4475                         op, VPR64, VPR64, v2i64, v2i32, v2i32,
4476                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4477
4478   def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
4479                           op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H,
4480                           BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4481
4482   def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
4483                           op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S,
4484                           BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4485 }
4486
4487 defm SMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SMULLve", int_arm_neon_vmulls>;
4488 defm UMULL_lane_v3 : NI_2VEL_mul_v3_pat<"UMULLve", int_arm_neon_vmullu>;
4489 defm SQDMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SQDMULLve", int_arm_neon_vqdmull>;
4490
4491 multiclass NI_qdma<SDPatternOperator op>
4492 {
4493   def _4s : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
4494                     (op node:$Ra,
4495                       (v4i32 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
4496
4497   def _2d : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
4498                     (op node:$Ra,
4499                       (v2i64 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
4500 }
4501
4502 defm Neon_qdmlal : NI_qdma<int_arm_neon_vqadds>;
4503 defm Neon_qdmlsl : NI_qdma<int_arm_neon_vqsubs>;
4504
4505 multiclass NI_2VEL_v3_qdma_pat<string subop, string op>
4506 {
4507   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
4508                      !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR128Lo,
4509                      v4i32, v4i16, v8i16,
4510                      BinOpFrag<(Neon_vduplane
4511                                  (Neon_low8H node:$LHS), node:$RHS)>>;
4512
4513   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
4514                      !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR128,
4515                      v2i64, v2i32, v4i32,
4516                      BinOpFrag<(Neon_vduplane
4517                                  (Neon_low4S node:$LHS), node:$RHS)>>;
4518
4519   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
4520                        !cast<PatFrag>(op # "_4s"), VPR128Lo,
4521                        v4i32, v8i16, v8i16, v4i16, Neon_High8H,
4522                        BinOpFrag<(Neon_vduplane
4523                                    (Neon_low8H node:$LHS), node:$RHS)>>;
4524
4525   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
4526                        !cast<PatFrag>(op # "_2d"), VPR128,
4527                        v2i64, v4i32, v4i32, v2i32, Neon_High4S,
4528                        BinOpFrag<(Neon_vduplane
4529                                    (Neon_low4S node:$LHS), node:$RHS)>>;
4530
4531   // Index can only be half of the max value for lane in 64-bit vector
4532
4533   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
4534                     !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR64Lo,
4535                     v4i32, v4i16, v4i16,
4536                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4537
4538   def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
4539                     !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR64,
4540                     v2i64, v2i32, v2i32,
4541                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4542
4543   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
4544                       !cast<PatFrag>(op # "_4s"), VPR64Lo,
4545                       v4i32, v8i16, v4i16, v4i16, Neon_High8H,
4546                       BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4547
4548   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
4549                       !cast<PatFrag>(op # "_2d"), VPR64,
4550                       v2i64, v4i32, v2i32, v2i32, Neon_High4S,
4551                       BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4552 }
4553
4554 defm SQDMLAL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLALvve", "Neon_qdmlal">;
4555 defm SQDMLSL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLSLvve", "Neon_qdmlsl">;
4556
4557 // End of implementation for instruction class (3V Elem)
4558
4559 //Insert element (vector, from main)
4560 def INSbw : NeonI_INS_main<"ins", "b", v16i8, GPR32, i32,
4561                            neon_uimm4_bare> {
4562   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
4563 }
4564 def INShw : NeonI_INS_main<"ins", "h", v8i16, GPR32, i32,
4565                            neon_uimm3_bare> {
4566   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
4567 }
4568 def INSsw : NeonI_INS_main<"ins", "s", v4i32, GPR32, i32,
4569                            neon_uimm2_bare> {
4570   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
4571 }
4572 def INSdx : NeonI_INS_main<"ins", "d", v2i64, GPR64, i64,
4573                            neon_uimm1_bare> {
4574   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
4575 }
4576
4577 class Neon_INS_main_pattern <ValueType ResTy,ValueType ExtResTy,
4578                              RegisterClass OpGPR, ValueType OpTy,
4579                              Operand OpImm, Instruction INS>
4580   : Pat<(ResTy (vector_insert
4581               (ResTy VPR64:$src),
4582               (OpTy OpGPR:$Rn),
4583               (OpImm:$Imm))),
4584         (ResTy (EXTRACT_SUBREG
4585           (ExtResTy (INS (ExtResTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
4586             OpGPR:$Rn, OpImm:$Imm)), sub_64))>;
4587
4588 def INSbw_pattern : Neon_INS_main_pattern<v8i8, v16i8, GPR32, i32,
4589                                           neon_uimm3_bare, INSbw>;
4590 def INShw_pattern : Neon_INS_main_pattern<v4i16, v8i16, GPR32, i32,
4591                                           neon_uimm2_bare, INShw>;
4592 def INSsw_pattern : Neon_INS_main_pattern<v2i32, v4i32, GPR32, i32,
4593                                           neon_uimm1_bare, INSsw>;
4594 def INSdx_pattern : Neon_INS_main_pattern<v1i64, v2i64, GPR64, i64,
4595                                           neon_uimm0_bare, INSdx>;
4596
4597 class NeonI_INS_element<string asmop, string Res, ValueType ResTy,
4598                         Operand ResImm, ValueType MidTy>
4599   : NeonI_insert<0b1, 0b1,
4600                  (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn,
4601                  ResImm:$Immd, ResImm:$Immn),
4602                  asmop # "\t$Rd." # Res # "[$Immd], $Rn." # Res # "[$Immn]",
4603                  [(set (ResTy VPR128:$Rd),
4604                     (ResTy (vector_insert
4605                       (ResTy VPR128:$src),
4606                       (MidTy (vector_extract
4607                         (ResTy VPR128:$Rn),
4608                         (ResImm:$Immn))),
4609                       (ResImm:$Immd))))],
4610                  NoItinerary> {
4611   let Constraints = "$src = $Rd";
4612   bits<4> Immd;
4613   bits<4> Immn;
4614 }
4615
4616 //Insert element (vector, from element)
4617 def INSELb : NeonI_INS_element<"ins", "b", v16i8, neon_uimm4_bare, i32> {
4618   let Inst{20-16} = {Immd{3}, Immd{2}, Immd{1}, Immd{0}, 0b1};
4619   let Inst{14-11} = {Immn{3}, Immn{2}, Immn{1}, Immn{0}};
4620 }
4621 def INSELh : NeonI_INS_element<"ins", "h", v8i16, neon_uimm3_bare, i32> {
4622   let Inst{20-16} = {Immd{2}, Immd{1}, Immd{0}, 0b1, 0b0};
4623   let Inst{14-12} = {Immn{2}, Immn{1}, Immn{0}};
4624   // bit 11 is unspecified.
4625 }
4626 def INSELs : NeonI_INS_element<"ins", "s", v4i32, neon_uimm2_bare, i32> {
4627   let Inst{20-16} = {Immd{1}, Immd{0}, 0b1, 0b0, 0b0};
4628   let Inst{14-13} = {Immn{1}, Immn{0}};
4629   // bits 11-12 are unspecified.
4630 }
4631 def INSELd : NeonI_INS_element<"ins", "d", v2i64, neon_uimm1_bare, i64> {
4632   let Inst{20-16} = {Immd, 0b1, 0b0, 0b0, 0b0};
4633   let Inst{14} = Immn{0};
4634   // bits 11-13 are unspecified.
4635 }
4636
4637 multiclass Neon_INS_elt_float_pattern<ValueType ResTy, ValueType NaTy,
4638                                       ValueType MidTy,
4639                                       RegisterClass OpFPR, Operand ResImm,
4640                                       SubRegIndex SubIndex, Instruction INS> {
4641 def : Pat<(ResTy (vector_insert
4642           (ResTy VPR128:$src),
4643           (MidTy (vector_extract
4644             (ResTy VPR128:$Rn),
4645             (ResImm:$Immn))),
4646           (ResImm:$Immd))),
4647         (INS (ResTy VPR128:$src), (ResTy VPR128:$Rn),
4648           ResImm:$Immd, ResImm:$Immn)>;
4649
4650 def : Pat <(ResTy (vector_insert
4651              (ResTy VPR128:$src),
4652              (MidTy OpFPR:$Rn),
4653              (ResImm:$Imm))),
4654            (INS (ResTy VPR128:$src),
4655              (ResTy (SUBREG_TO_REG (i64 0), OpFPR:$Rn, SubIndex)),
4656              ResImm:$Imm,
4657              (i64 0))>;
4658
4659 def : Pat <(NaTy (vector_insert
4660              (NaTy VPR64:$src),
4661              (MidTy OpFPR:$Rn),
4662              (ResImm:$Imm))),
4663            (NaTy (EXTRACT_SUBREG
4664              (ResTy (INS
4665                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
4666                (ResTy (SUBREG_TO_REG (i64 0), (MidTy OpFPR:$Rn), SubIndex)),
4667                ResImm:$Imm,
4668                (i64 0))),
4669              sub_64))>;
4670 }
4671
4672 defm : Neon_INS_elt_float_pattern<v4f32, v2f32, f32, FPR32, neon_uimm2_bare,
4673                                   sub_32, INSELs>;
4674 defm : Neon_INS_elt_float_pattern<v2f64, v1f64, f64, FPR64, neon_uimm1_bare,
4675                                   sub_64, INSELd>;
4676
4677 multiclass Neon_INS_elt_pattern <ValueType NaTy, Operand NaImm,
4678                                 ValueType MidTy, ValueType StTy,
4679                                 Operand StImm, Instruction INS> {
4680 def : Pat<(NaTy (vector_insert
4681             (NaTy VPR64:$src),
4682             (MidTy (vector_extract
4683               (StTy VPR128:$Rn),
4684               (StImm:$Immn))),
4685             (NaImm:$Immd))),
4686           (NaTy (EXTRACT_SUBREG
4687             (StTy (INS
4688               (StTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
4689               (StTy VPR128:$Rn),
4690               NaImm:$Immd,
4691               StImm:$Immn)),
4692           sub_64))>;
4693
4694 def : Pat<(StTy (vector_insert
4695             (StTy VPR128:$src),
4696             (MidTy (vector_extract
4697               (NaTy VPR64:$Rn),
4698               (NaImm:$Immn))),
4699             (StImm:$Immd))),
4700           (StTy (INS
4701             (StTy VPR128:$src),
4702             (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
4703             StImm:$Immd,
4704             NaImm:$Immn))>;
4705
4706 def : Pat<(NaTy (vector_insert
4707             (NaTy VPR64:$src),
4708             (MidTy (vector_extract
4709               (NaTy VPR64:$Rn),
4710               (NaImm:$Immn))),
4711             (NaImm:$Immd))),
4712           (NaTy (EXTRACT_SUBREG
4713             (StTy (INS
4714               (StTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
4715               (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
4716               NaImm:$Immd,
4717               NaImm:$Immn)),
4718           sub_64))>;
4719 }
4720
4721 defm : Neon_INS_elt_pattern<v8i8, neon_uimm3_bare, i32,
4722                             v16i8, neon_uimm4_bare, INSELb>;
4723 defm : Neon_INS_elt_pattern<v4i16, neon_uimm2_bare, i32,
4724                             v8i16, neon_uimm3_bare, INSELh>;
4725 defm : Neon_INS_elt_pattern<v2i32, neon_uimm1_bare, i32,
4726                             v4i32, neon_uimm2_bare, INSELs>;
4727 defm : Neon_INS_elt_pattern<v1i64, neon_uimm0_bare, i64,
4728                             v2i64, neon_uimm1_bare, INSELd>;
4729
4730
4731 class NeonI_SMOV<string asmop, string Res, bit Q,
4732                  ValueType OpTy, ValueType eleTy,
4733                  Operand OpImm, RegisterClass ResGPR, ValueType ResTy>
4734   : NeonI_copy<Q, 0b0, 0b0101,
4735                (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
4736                asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
4737                [(set (ResTy ResGPR:$Rd),
4738                  (ResTy (sext_inreg
4739                    (ResTy (vector_extract
4740                      (OpTy VPR128:$Rn), (OpImm:$Imm))),
4741                    eleTy)))],
4742                NoItinerary> {
4743   bits<4> Imm;
4744 }
4745
4746 //Signed integer move (main, from element)
4747 def SMOVwb : NeonI_SMOV<"smov", "b", 0b0, v16i8, i8, neon_uimm4_bare,
4748                         GPR32, i32> {
4749   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
4750 }
4751 def SMOVwh : NeonI_SMOV<"smov", "h", 0b0, v8i16, i16, neon_uimm3_bare,
4752                         GPR32, i32> {
4753   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
4754 }
4755 def SMOVxb : NeonI_SMOV<"smov", "b", 0b1, v16i8, i8, neon_uimm4_bare,
4756                         GPR64, i64> {
4757   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
4758 }
4759 def SMOVxh : NeonI_SMOV<"smov", "h", 0b1, v8i16, i16, neon_uimm3_bare,
4760                         GPR64, i64> {
4761   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
4762 }
4763 def SMOVxs : NeonI_SMOV<"smov", "s", 0b1, v4i32, i32, neon_uimm2_bare,
4764                         GPR64, i64> {
4765   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
4766 }
4767
4768 multiclass Neon_SMOVx_pattern <ValueType StTy, ValueType NaTy,
4769                                ValueType eleTy, Operand StImm,  Operand NaImm,
4770                                Instruction SMOVI> {
4771   def : Pat<(i64 (sext_inreg
4772               (i64 (anyext
4773                 (i32 (vector_extract
4774                   (StTy VPR128:$Rn), (StImm:$Imm))))),
4775               eleTy)),
4776             (SMOVI VPR128:$Rn, StImm:$Imm)>;
4777
4778   def : Pat<(i64 (sext
4779               (i32 (vector_extract
4780                 (StTy VPR128:$Rn), (StImm:$Imm))))),
4781             (SMOVI VPR128:$Rn, StImm:$Imm)>;
4782
4783   def : Pat<(i64 (sext_inreg
4784               (i64 (vector_extract
4785                 (NaTy VPR64:$Rn), (NaImm:$Imm))),
4786               eleTy)),
4787             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
4788               NaImm:$Imm)>;
4789
4790   def : Pat<(i64 (sext_inreg
4791               (i64 (anyext
4792                 (i32 (vector_extract
4793                   (NaTy VPR64:$Rn), (NaImm:$Imm))))),
4794               eleTy)),
4795             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
4796               NaImm:$Imm)>;
4797
4798   def : Pat<(i64 (sext
4799               (i32 (vector_extract
4800                 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
4801             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
4802               NaImm:$Imm)>;
4803 }
4804
4805 defm : Neon_SMOVx_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
4806                           neon_uimm3_bare, SMOVxb>;
4807 defm : Neon_SMOVx_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
4808                           neon_uimm2_bare, SMOVxh>;
4809 defm : Neon_SMOVx_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
4810                           neon_uimm1_bare, SMOVxs>;
4811
4812 class Neon_SMOVw_pattern <ValueType StTy, ValueType NaTy,
4813                           ValueType eleTy, Operand StImm,  Operand NaImm,
4814                           Instruction SMOVI>
4815   : Pat<(i32 (sext_inreg
4816           (i32 (vector_extract
4817             (NaTy VPR64:$Rn), (NaImm:$Imm))),
4818           eleTy)),
4819         (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
4820           NaImm:$Imm)>;
4821
4822 def : Neon_SMOVw_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
4823                          neon_uimm3_bare, SMOVwb>;
4824 def : Neon_SMOVw_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
4825                          neon_uimm2_bare, SMOVwh>;
4826
4827 class NeonI_UMOV<string asmop, string Res, bit Q,
4828                  ValueType OpTy, Operand OpImm,
4829                  RegisterClass ResGPR, ValueType ResTy>
4830   : NeonI_copy<Q, 0b0, 0b0111,
4831                (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
4832                asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
4833                [(set (ResTy ResGPR:$Rd),
4834                   (ResTy (vector_extract
4835                     (OpTy VPR128:$Rn), (OpImm:$Imm))))],
4836                NoItinerary> {
4837   bits<4> Imm;
4838 }
4839
4840 //Unsigned integer move (main, from element)
4841 def UMOVwb : NeonI_UMOV<"umov", "b", 0b0, v16i8, neon_uimm4_bare,
4842                          GPR32, i32> {
4843   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
4844 }
4845 def UMOVwh : NeonI_UMOV<"umov", "h", 0b0, v8i16, neon_uimm3_bare,
4846                          GPR32, i32> {
4847   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
4848 }
4849 def UMOVws : NeonI_UMOV<"umov", "s", 0b0, v4i32, neon_uimm2_bare,
4850                          GPR32, i32> {
4851   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
4852 }
4853 def UMOVxd : NeonI_UMOV<"umov", "d", 0b1, v2i64, neon_uimm1_bare,
4854                          GPR64, i64> {
4855   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
4856 }
4857
4858 class Neon_UMOV_pattern <ValueType StTy, ValueType NaTy, ValueType ResTy,
4859                          Operand StImm,  Operand NaImm,
4860                          Instruction SMOVI>
4861   : Pat<(ResTy (vector_extract
4862           (NaTy VPR64:$Rn), NaImm:$Imm)),
4863         (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
4864           NaImm:$Imm)>;
4865
4866 def : Neon_UMOV_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
4867                         neon_uimm3_bare, UMOVwb>;
4868 def : Neon_UMOV_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
4869                         neon_uimm2_bare, UMOVwh>;
4870 def : Neon_UMOV_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
4871                         neon_uimm1_bare, UMOVws>;
4872
4873 def : Pat<(i32 (and
4874             (i32 (vector_extract
4875               (v16i8 VPR128:$Rn), (neon_uimm4_bare:$Imm))),
4876             255)),
4877           (UMOVwb VPR128:$Rn, neon_uimm4_bare:$Imm)>;
4878
4879 def : Pat<(i32 (and
4880             (i32 (vector_extract
4881               (v8i16 VPR128:$Rn), (neon_uimm3_bare:$Imm))),
4882             65535)),
4883           (UMOVwh VPR128:$Rn, neon_uimm3_bare:$Imm)>;
4884
4885 def : Pat<(i64 (zext
4886             (i32 (vector_extract
4887               (v2i64 VPR128:$Rn), (neon_uimm1_bare:$Imm))))),
4888           (UMOVxd VPR128:$Rn, neon_uimm1_bare:$Imm)>;
4889
4890 def : Pat<(i32 (and
4891             (i32 (vector_extract
4892               (v8i8 VPR64:$Rn), (neon_uimm3_bare:$Imm))),
4893             255)),
4894           (UMOVwb (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
4895             neon_uimm3_bare:$Imm)>;
4896
4897 def : Pat<(i32 (and
4898             (i32 (vector_extract
4899               (v4i16 VPR64:$Rn), (neon_uimm2_bare:$Imm))),
4900             65535)),
4901           (UMOVwh (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
4902             neon_uimm2_bare:$Imm)>;
4903
4904 def : Pat<(i64 (zext
4905             (i32 (vector_extract
4906               (v1i64 VPR64:$Rn), (neon_uimm0_bare:$Imm))))),
4907           (UMOVxd (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
4908             neon_uimm0_bare:$Imm)>;
4909
4910 // Additional copy patterns for scalar types
4911 def : Pat<(i32 (vector_extract (v1i8 FPR8:$Rn), (i64 0))),
4912           (UMOVwb (v16i8
4913             (SUBREG_TO_REG (i64 0), FPR8:$Rn, sub_8)), (i64 0))>;
4914
4915 def : Pat<(i32 (vector_extract (v1i16 FPR16:$Rn), (i64 0))),
4916           (UMOVwh (v8i16
4917             (SUBREG_TO_REG (i64 0), FPR16:$Rn, sub_16)), (i64 0))>;
4918
4919 def : Pat<(i32 (vector_extract (v1i32 FPR32:$Rn), (i64 0))),
4920           (FMOVws FPR32:$Rn)>;
4921
4922 def : Pat<(i64 (vector_extract (v1i64 FPR64:$Rn), (i64 0))),
4923           (FMOVxd FPR64:$Rn)>;
4924
4925 def : Pat<(f64 (vector_extract (v1f64 FPR64:$Rn), (i64 0))),
4926           (f64 FPR64:$Rn)>;
4927
4928 def : Pat<(f32 (vector_extract (v1f32 FPR32:$Rn), (i64 0))),
4929           (f32 FPR32:$Rn)>;
4930
4931 def : Pat<(v1i8 (scalar_to_vector GPR32:$Rn)),
4932           (v1i8 (EXTRACT_SUBREG (v16i8
4933             (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
4934             sub_8))>;
4935
4936 def : Pat<(v1i16 (scalar_to_vector GPR32:$Rn)),
4937           (v1i16 (EXTRACT_SUBREG (v8i16
4938             (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
4939             sub_16))>;
4940
4941 def : Pat<(v1i32 (scalar_to_vector GPR32:$src)),
4942           (FMOVsw $src)>;
4943
4944 def : Pat<(v1i64 (scalar_to_vector GPR64:$src)),
4945           (FMOVdx $src)>;
4946
4947 def : Pat<(v1f32 (scalar_to_vector (f32 FPR32:$Rn))),
4948           (v1f32 FPR32:$Rn)>;
4949 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
4950           (v1f64 FPR64:$Rn)>;
4951
4952 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
4953           (FMOVdd $src)>;
4954
4955 class NeonI_DUP_Elt<bit Q, string asmop, string rdlane,  string rnlane,
4956                     RegisterOperand ResVPR, ValueType ResTy,
4957                     ValueType OpTy, Operand OpImm>
4958   : NeonI_copy<Q, 0b0, 0b0000, (outs ResVPR:$Rd),
4959                (ins VPR128:$Rn, OpImm:$Imm),
4960                asmop # "\t$Rd" # rdlane # ", $Rn" # rnlane # "[$Imm]",
4961                [],
4962                NoItinerary> {
4963   bits<4> Imm;
4964 }
4965
4966 def DUPELT16b : NeonI_DUP_Elt<0b1, "dup", ".16b", ".b", VPR128, v16i8, v16i8,
4967                               neon_uimm4_bare> {
4968   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
4969 }
4970
4971 def DUPELT8h : NeonI_DUP_Elt<0b1, "dup", ".8h", ".h", VPR128, v8i16, v8i16,
4972                               neon_uimm3_bare> {
4973   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
4974 }
4975
4976 def DUPELT4s : NeonI_DUP_Elt<0b1, "dup", ".4s", ".s", VPR128, v4i32, v4i32,
4977                               neon_uimm2_bare> {
4978   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
4979 }
4980
4981 def DUPELT2d : NeonI_DUP_Elt<0b1, "dup", ".2d", ".d", VPR128, v2i64, v2i64,
4982                               neon_uimm1_bare> {
4983   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
4984 }
4985
4986 def DUPELT8b : NeonI_DUP_Elt<0b0, "dup", ".8b", ".b", VPR64, v8i8, v16i8,
4987                               neon_uimm4_bare> {
4988   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
4989 }
4990
4991 def DUPELT4h : NeonI_DUP_Elt<0b0, "dup", ".4h", ".h", VPR64, v4i16, v8i16,
4992                               neon_uimm3_bare> {
4993   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
4994 }
4995
4996 def DUPELT2s : NeonI_DUP_Elt<0b0, "dup", ".2s", ".s", VPR64, v2i32, v4i32,
4997                               neon_uimm2_bare> {
4998   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
4999 }
5000
5001 multiclass NeonI_DUP_Elt_pattern<Instruction DUPELT, ValueType ResTy,
5002                                        ValueType OpTy,ValueType NaTy,
5003                                        ValueType ExTy, Operand OpLImm,
5004                                        Operand OpNImm> {
5005 def  : Pat<(ResTy (Neon_vduplane (OpTy VPR128:$Rn), OpLImm:$Imm)),
5006         (ResTy (DUPELT (OpTy VPR128:$Rn), OpLImm:$Imm))>;
5007
5008 def : Pat<(ResTy (Neon_vduplane
5009             (NaTy VPR64:$Rn), OpNImm:$Imm)),
5010           (ResTy (DUPELT
5011             (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)), OpNImm:$Imm))>;
5012 }
5013 defm : NeonI_DUP_Elt_pattern<DUPELT16b, v16i8, v16i8, v8i8, v16i8,
5014                              neon_uimm4_bare, neon_uimm3_bare>;
5015 defm : NeonI_DUP_Elt_pattern<DUPELT8b, v8i8, v16i8, v8i8, v16i8,
5016                              neon_uimm4_bare, neon_uimm3_bare>;
5017 defm : NeonI_DUP_Elt_pattern<DUPELT8h, v8i16, v8i16, v4i16, v8i16,
5018                              neon_uimm3_bare, neon_uimm2_bare>;
5019 defm : NeonI_DUP_Elt_pattern<DUPELT4h, v4i16, v8i16, v4i16, v8i16,
5020                              neon_uimm3_bare, neon_uimm2_bare>;
5021 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4i32, v4i32, v2i32, v4i32,
5022                              neon_uimm2_bare, neon_uimm1_bare>;
5023 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2i32, v4i32, v2i32, v4i32,
5024                              neon_uimm2_bare, neon_uimm1_bare>;
5025 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2i64, v2i64, v1i64, v2i64,
5026                              neon_uimm1_bare, neon_uimm0_bare>;
5027 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4f32, v4f32, v2f32, v4f32,
5028                              neon_uimm2_bare, neon_uimm1_bare>;
5029 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2f32, v4f32, v2f32, v4f32,
5030                              neon_uimm2_bare, neon_uimm1_bare>;
5031 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2f64, v2f64, v1f64, v2f64,
5032                              neon_uimm1_bare, neon_uimm0_bare>;
5033
5034 def : Pat<(v2f32 (Neon_vdup (f32 FPR32:$Rn))),
5035           (v2f32 (DUPELT2s
5036             (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
5037             (i64 0)))>;
5038 def : Pat<(v4f32 (Neon_vdup (f32 FPR32:$Rn))),
5039           (v4f32 (DUPELT4s
5040             (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
5041             (i64 0)))>;
5042 def : Pat<(v2f64 (Neon_vdup (f64 FPR64:$Rn))),
5043           (v2f64 (DUPELT2d
5044             (SUBREG_TO_REG (i64 0), FPR64:$Rn, sub_64),
5045             (i64 0)))>;
5046
5047 class NeonI_DUP<bit Q, string asmop, string rdlane,
5048                 RegisterOperand ResVPR, ValueType ResTy,
5049                 RegisterClass OpGPR, ValueType OpTy>
5050   : NeonI_copy<Q, 0b0, 0b0001, (outs ResVPR:$Rd), (ins OpGPR:$Rn),
5051                asmop # "\t$Rd" # rdlane # ", $Rn",
5052                [(set (ResTy ResVPR:$Rd),
5053                  (ResTy (Neon_vdup (OpTy OpGPR:$Rn))))],
5054                NoItinerary>;
5055
5056 def DUP16b : NeonI_DUP<0b1, "dup", ".16b", VPR128, v16i8, GPR32, i32> {
5057   let Inst{16} = 0b1;
5058   // bits 17-19 are unspecified.
5059 }
5060
5061 def DUP8h : NeonI_DUP<0b1, "dup", ".8h", VPR128, v8i16, GPR32, i32> {
5062   let Inst{17-16} = 0b10;
5063   // bits 18-19 are unspecified.
5064 }
5065
5066 def DUP4s : NeonI_DUP<0b1, "dup", ".4s", VPR128, v4i32, GPR32, i32> {
5067   let Inst{18-16} = 0b100;
5068   // bit 19 is unspecified.
5069 }
5070
5071 def DUP2d : NeonI_DUP<0b1, "dup", ".2d", VPR128, v2i64, GPR64, i64> {
5072   let Inst{19-16} = 0b1000;
5073 }
5074
5075 def DUP8b : NeonI_DUP<0b0, "dup", ".8b", VPR64, v8i8, GPR32, i32> {
5076   let Inst{16} = 0b1;
5077   // bits 17-19 are unspecified.
5078 }
5079
5080 def DUP4h : NeonI_DUP<0b0, "dup", ".4h", VPR64, v4i16, GPR32, i32> {
5081   let Inst{17-16} = 0b10;
5082   // bits 18-19 are unspecified.
5083 }
5084
5085 def DUP2s : NeonI_DUP<0b0, "dup", ".2s", VPR64, v2i32, GPR32, i32> {
5086   let Inst{18-16} = 0b100;
5087   // bit 19 is unspecified.
5088 }
5089
5090 // patterns for CONCAT_VECTORS
5091 multiclass Concat_Vector_Pattern<ValueType ResTy, ValueType OpTy> {
5092 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), undef)),
5093           (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)>;
5094 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))),
5095           (INSELd
5096             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5097             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rm, sub_64)),
5098             (i64 1),
5099             (i64 0))>;
5100 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rn))),
5101           (DUPELT2d
5102             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5103             (i64 0))> ;
5104 }
5105
5106 defm : Concat_Vector_Pattern<v16i8, v8i8>;
5107 defm : Concat_Vector_Pattern<v8i16, v4i16>;
5108 defm : Concat_Vector_Pattern<v4i32, v2i32>;
5109 defm : Concat_Vector_Pattern<v2i64, v1i64>;
5110 defm : Concat_Vector_Pattern<v4f32, v2f32>;
5111 defm : Concat_Vector_Pattern<v2f64, v1f64>;
5112
5113 //patterns for EXTRACT_SUBVECTOR
5114 def : Pat<(v8i8 (extract_subvector (v16i8 VPR128:$Rn), (i64 0))),
5115           (v8i8 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
5116 def : Pat<(v4i16 (extract_subvector (v8i16 VPR128:$Rn), (i64 0))),
5117           (v4i16 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
5118 def : Pat<(v2i32 (extract_subvector (v4i32 VPR128:$Rn), (i64 0))),
5119           (v2i32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
5120 def : Pat<(v1i64 (extract_subvector (v2i64 VPR128:$Rn), (i64 0))),
5121           (v1i64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
5122 def : Pat<(v2f32 (extract_subvector (v4f32 VPR128:$Rn), (i64 0))),
5123           (v2f32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
5124 def : Pat<(v1f64 (extract_subvector (v2f64 VPR128:$Rn), (i64 0))),
5125           (v1f64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;