lib/Target/AArch64/AArch64InstrNEON.td

   1 //===-- AArch64InstrNEON.td - NEON support for AArch64 -----*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the AArch64 NEON instruction set.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // NEON-specific DAG Nodes.
  16 //===----------------------------------------------------------------------===//
  17 def Neon_bsl       : SDNode<"AArch64ISD::NEON_BSL", SDTypeProfile<1, 3,
  18                       [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
  19                       SDTCisSameAs<0, 3>]>>;
  20
  21 // (outs Result), (ins Imm, OpCmode)
  22 def SDT_Neon_movi : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
  23
  24 def Neon_movi     : SDNode<"AArch64ISD::NEON_MOVIMM", SDT_Neon_movi>;
  25
  26 def Neon_mvni     : SDNode<"AArch64ISD::NEON_MVNIMM", SDT_Neon_movi>;
  27
  28 // (outs Result), (ins Imm)
  29 def Neon_fmovi : SDNode<"AArch64ISD::NEON_FMOVIMM", SDTypeProfile<1, 1,
  30                         [SDTCisVec<0>, SDTCisVT<1, i32>]>>;
  31
  32 // (outs Result), (ins LHS, RHS, CondCode)
  33 def Neon_cmp : SDNode<"AArch64ISD::NEON_CMP", SDTypeProfile<1, 3,
  34                  [SDTCisVec<0>,  SDTCisSameAs<1, 2>]>>;
  35
  36 // (outs Result), (ins LHS, 0/0.0 constant, CondCode)
  37 def Neon_cmpz : SDNode<"AArch64ISD::NEON_CMPZ", SDTypeProfile<1, 3,
  38                  [SDTCisVec<0>,  SDTCisVec<1>]>>;
  39
  40 // (outs Result), (ins LHS, RHS)
  41 def Neon_tst : SDNode<"AArch64ISD::NEON_TST", SDTypeProfile<1, 2,
  42                  [SDTCisVec<0>,  SDTCisSameAs<1, 2>]>>;
  43
  44 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  45                                      SDTCisVT<2, i32>]>;
  46 def Neon_sqrshlImm   : SDNode<"AArch64ISD::NEON_QSHLs", SDTARMVSH>;
  47 def Neon_uqrshlImm   : SDNode<"AArch64ISD::NEON_QSHLu", SDTARMVSH>;
  48
  49 def Neon_vdup : SDNode<"AArch64ISD::NEON_VDUP", SDTypeProfile<1, 1,
  50                        [SDTCisVec<0>]>>;
  51 def Neon_vduplane : SDNode<"AArch64ISD::NEON_VDUPLANE", SDTypeProfile<1, 2,
  52                            [SDTCisVec<0>, SDTCisVec<1>, SDTCisVT<2, i64>]>>;
  53 def Neon_vextract : SDNode<"AArch64ISD::NEON_VEXTRACT", SDTypeProfile<1, 3,
  54                            [SDTCisVec<0>,  SDTCisSameAs<0, 1>,
  55                            SDTCisSameAs<0, 2>, SDTCisVT<3, i64>]>>;
  56
  57 //===----------------------------------------------------------------------===//
  58 // Multiclasses
  59 //===----------------------------------------------------------------------===//
  60
  61 multiclass NeonI_3VSame_B_sizes<bit u, bits<2> size,  bits<5> opcode,
  62                                 string asmop, SDPatternOperator opnode8B,
  63                                 SDPatternOperator opnode16B,
  64                                 bit Commutable = 0> {
  65   let isCommutable = Commutable in {
  66     def _8B :  NeonI_3VSame<0b0, u, size, opcode,
  67                (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
  68                asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
  69                [(set (v8i8 VPR64:$Rd),
  70                   (v8i8 (opnode8B (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
  71                NoItinerary>;
  72
  73     def _16B : NeonI_3VSame<0b1, u, size, opcode,
  74                (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
  75                asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
  76                [(set (v16i8 VPR128:$Rd),
  77                   (v16i8 (opnode16B (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
  78                NoItinerary>;
  79   }
  80
  81 }
  82
  83 multiclass NeonI_3VSame_HS_sizes<bit u, bits<5> opcode,
  84                                   string asmop, SDPatternOperator opnode,
  85                                   bit Commutable = 0> {
  86   let isCommutable = Commutable in {
  87     def _4H : NeonI_3VSame<0b0, u, 0b01, opcode,
  88               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
  89               asmop # "\t$Rd.4h, $Rn.4h, $Rm.4h",
  90               [(set (v4i16 VPR64:$Rd),
  91                  (v4i16 (opnode (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))))],
  92               NoItinerary>;
  93
  94     def _8H : NeonI_3VSame<0b1, u, 0b01, opcode,
  95               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
  96               asmop # "\t$Rd.8h, $Rn.8h, $Rm.8h",
  97               [(set (v8i16 VPR128:$Rd),
  98                  (v8i16 (opnode (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))))],
  99               NoItinerary>;
 100
 101     def _2S : NeonI_3VSame<0b0, u, 0b10, opcode,
 102               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 103               asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
 104               [(set (v2i32 VPR64:$Rd),
 105                  (v2i32 (opnode (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))))],
 106               NoItinerary>;
 107
 108     def _4S : NeonI_3VSame<0b1, u, 0b10, opcode,
 109               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 110               asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
 111               [(set (v4i32 VPR128:$Rd),
 112                  (v4i32 (opnode (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))))],
 113               NoItinerary>;
 114   }
 115 }
 116 multiclass NeonI_3VSame_BHS_sizes<bit u, bits<5> opcode,
 117                                   string asmop, SDPatternOperator opnode,
 118                                   bit Commutable = 0>
 119    : NeonI_3VSame_HS_sizes<u, opcode,  asmop, opnode, Commutable> {
 120   let isCommutable = Commutable in {
 121     def _8B :  NeonI_3VSame<0b0, u, 0b00, opcode,
 122                (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 123                asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
 124                [(set (v8i8 VPR64:$Rd),
 125                   (v8i8 (opnode (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
 126                NoItinerary>;
 127
 128     def _16B : NeonI_3VSame<0b1, u, 0b00, opcode,
 129                (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 130                asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
 131                [(set (v16i8 VPR128:$Rd),
 132                   (v16i8 (opnode (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
 133                NoItinerary>;
 134   }
 135 }
 136
 137 multiclass NeonI_3VSame_BHSD_sizes<bit u, bits<5> opcode,
 138                                    string asmop, SDPatternOperator opnode,
 139                                    bit Commutable = 0>
 140    : NeonI_3VSame_BHS_sizes<u, opcode,  asmop, opnode, Commutable> {
 141   let isCommutable = Commutable in {
 142     def _2D : NeonI_3VSame<0b1, u, 0b11, opcode,
 143               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 144               asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
 145               [(set (v2i64 VPR128:$Rd),
 146                  (v2i64 (opnode (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))))],
 147               NoItinerary>;
 148   }
 149 }
 150
 151 // Multiclass NeonI_3VSame_SD_sizes: Operand types are floating point types,
 152 // but Result types can be integer or floating point types.
 153 multiclass NeonI_3VSame_SD_sizes<bit u, bit size, bits<5> opcode,
 154                                  string asmop, SDPatternOperator opnode2S,
 155                                  SDPatternOperator opnode4S,
 156                                  SDPatternOperator opnode2D,
 157                                  ValueType ResTy2S, ValueType ResTy4S,
 158                                  ValueType ResTy2D, bit Commutable = 0> {
 159   let isCommutable = Commutable in {
 160     def _2S : NeonI_3VSame<0b0, u, {size, 0b0}, opcode,
 161               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 162               asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
 163               [(set (ResTy2S VPR64:$Rd),
 164                  (ResTy2S (opnode2S (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
 165               NoItinerary>;
 166
 167     def _4S : NeonI_3VSame<0b1, u, {size, 0b0}, opcode,
 168               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 169               asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
 170               [(set (ResTy4S VPR128:$Rd),
 171                  (ResTy4S (opnode4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
 172               NoItinerary>;
 173
 174     def _2D : NeonI_3VSame<0b1, u, {size, 0b1}, opcode,
 175               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 176               asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
 177               [(set (ResTy2D VPR128:$Rd),
 178                  (ResTy2D (opnode2D (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))))],
 179                NoItinerary>;
 180   }
 181 }
 182
 183 //===----------------------------------------------------------------------===//
 184 // Instruction Definitions
 185 //===----------------------------------------------------------------------===//
 186
 187 // Vector Arithmetic Instructions
 188
 189 // Vector Add (Integer and Floating-Point)
 190
 191 defm ADDvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b10000, "add", add, 1>;
 192 defm FADDvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11010, "fadd", fadd, fadd, fadd,
 193                                      v2f32, v4f32, v2f64, 1>;
 194
 195 // Vector Sub (Integer and Floating-Point)
 196
 197 defm SUBvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b10000, "sub", sub, 0>;
 198 defm FSUBvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11010, "fsub", fsub, fsub, fsub,
 199                                      v2f32, v4f32, v2f64, 0>;
 200
 201 // Vector Multiply (Integer and Floating-Point)
 202
 203 defm MULvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b10011, "mul", mul, 1>;
 204 defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul, fmul, fmul,
 205                                      v2f32, v4f32, v2f64, 1>;
 206
 207 // Vector Multiply (Polynomial)
 208
 209 defm PMULvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b10011, "pmul",
 210                                     int_arm_neon_vmulp, int_arm_neon_vmulp, 1>;
 211
 212 // Vector Multiply-accumulate and Multiply-subtract (Integer)
 213
 214 // class NeonI_3VSame_Constraint_impl: NeonI_3VSame with no data type and
 215 // two operands constraints.
 216 class NeonI_3VSame_Constraint_impl<string asmop, string asmlane,
 217   RegisterOperand VPRC, ValueType OpTy, bit q, bit u, bits<2> size,
 218   bits<5> opcode, SDPatternOperator opnode>
 219   : NeonI_3VSame<q, u, size, opcode,
 220     (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, VPRC:$Rm),
 221     asmop # "\t$Rd" # asmlane # ", $Rn" # asmlane # ", $Rm" # asmlane,
 222     [(set (OpTy VPRC:$Rd),
 223        (OpTy (opnode (OpTy VPRC:$src), (OpTy VPRC:$Rn), (OpTy VPRC:$Rm))))],
 224     NoItinerary> {
 225   let Constraints = "$src = $Rd";
 226 }
 227
 228 def Neon_mla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 229                        (add node:$Ra, (mul node:$Rn, node:$Rm))>;
 230
 231 def Neon_mls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 232                        (sub node:$Ra, (mul node:$Rn, node:$Rm))>;
 233
 234
 235 def MLAvvv_8B:  NeonI_3VSame_Constraint_impl<"mla", ".8b",  VPR64,  v8i8,
 236                                              0b0, 0b0, 0b00, 0b10010, Neon_mla>;
 237 def MLAvvv_16B: NeonI_3VSame_Constraint_impl<"mla", ".16b", VPR128, v16i8,
 238                                              0b1, 0b0, 0b00, 0b10010, Neon_mla>;
 239 def MLAvvv_4H:  NeonI_3VSame_Constraint_impl<"mla", ".4h",  VPR64,  v4i16,
 240                                              0b0, 0b0, 0b01, 0b10010, Neon_mla>;
 241 def MLAvvv_8H:  NeonI_3VSame_Constraint_impl<"mla", ".8h",  VPR128, v8i16,
 242                                              0b1, 0b0, 0b01, 0b10010, Neon_mla>;
 243 def MLAvvv_2S:  NeonI_3VSame_Constraint_impl<"mla", ".2s",  VPR64,  v2i32,
 244                                              0b0, 0b0, 0b10, 0b10010, Neon_mla>;
 245 def MLAvvv_4S:  NeonI_3VSame_Constraint_impl<"mla", ".4s",  VPR128, v4i32,
 246                                              0b1, 0b0, 0b10, 0b10010, Neon_mla>;
 247
 248 def MLSvvv_8B:  NeonI_3VSame_Constraint_impl<"mls", ".8b",  VPR64,  v8i8,
 249                                              0b0, 0b1, 0b00, 0b10010, Neon_mls>;
 250 def MLSvvv_16B: NeonI_3VSame_Constraint_impl<"mls", ".16b", VPR128, v16i8,
 251                                              0b1, 0b1, 0b00, 0b10010, Neon_mls>;
 252 def MLSvvv_4H:  NeonI_3VSame_Constraint_impl<"mls", ".4h",  VPR64,  v4i16,
 253                                              0b0, 0b1, 0b01, 0b10010, Neon_mls>;
 254 def MLSvvv_8H:  NeonI_3VSame_Constraint_impl<"mls", ".8h",  VPR128, v8i16,
 255                                              0b1, 0b1, 0b01, 0b10010, Neon_mls>;
 256 def MLSvvv_2S:  NeonI_3VSame_Constraint_impl<"mls", ".2s",  VPR64,  v2i32,
 257                                              0b0, 0b1, 0b10, 0b10010, Neon_mls>;
 258 def MLSvvv_4S:  NeonI_3VSame_Constraint_impl<"mls", ".4s",  VPR128, v4i32,
 259                                              0b1, 0b1, 0b10, 0b10010, Neon_mls>;
 260
 261 // Vector Multiply-accumulate and Multiply-subtract (Floating Point)
 262
 263 def Neon_fmla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 264                         (fadd node:$Ra, (fmul node:$Rn, node:$Rm))>;
 265
 266 def Neon_fmls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 267                         (fsub node:$Ra, (fmul node:$Rn, node:$Rm))>;
 268
 269 let Predicates = [HasNEON, UseFusedMAC] in {
 270 def FMLAvvv_2S: NeonI_3VSame_Constraint_impl<"fmla", ".2s",  VPR64,  v2f32,
 271                                              0b0, 0b0, 0b00, 0b11001, Neon_fmla>;
 272 def FMLAvvv_4S: NeonI_3VSame_Constraint_impl<"fmla", ".4s",  VPR128, v4f32,
 273                                              0b1, 0b0, 0b00, 0b11001, Neon_fmla>;
 274 def FMLAvvv_2D: NeonI_3VSame_Constraint_impl<"fmla", ".2d",  VPR128, v2f64,
 275                                              0b1, 0b0, 0b01, 0b11001, Neon_fmla>;
 276
 277 def FMLSvvv_2S: NeonI_3VSame_Constraint_impl<"fmls", ".2s",  VPR64,  v2f32,
 278                                               0b0, 0b0, 0b10, 0b11001, Neon_fmls>;
 279 def FMLSvvv_4S: NeonI_3VSame_Constraint_impl<"fmls", ".4s",  VPR128, v4f32,
 280                                              0b1, 0b0, 0b10, 0b11001, Neon_fmls>;
 281 def FMLSvvv_2D: NeonI_3VSame_Constraint_impl<"fmls", ".2d",  VPR128, v2f64,
 282                                              0b1, 0b0, 0b11, 0b11001, Neon_fmls>;
 283 }
 284
 285 // We're also allowed to match the fma instruction regardless of compile
 286 // options.
 287 def : Pat<(v2f32 (fma VPR64:$Rn, VPR64:$Rm, VPR64:$Ra)),
 288           (FMLAvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
 289 def : Pat<(v4f32 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
 290           (FMLAvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 291 def : Pat<(v2f64 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
 292           (FMLAvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 293
 294 def : Pat<(v2f32 (fma (fneg VPR64:$Rn), VPR64:$Rm, VPR64:$Ra)),
 295           (FMLSvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
 296 def : Pat<(v4f32 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
 297           (FMLSvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 298 def : Pat<(v2f64 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
 299           (FMLSvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 300
 301 // Vector Divide (Floating-Point)
 302
 303 defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv, fdiv, fdiv,
 304                                      v2f32, v4f32, v2f64, 0>;
 305
 306 // Vector Bitwise Operations
 307
 308 // Vector Bitwise AND
 309
 310 defm ANDvvv : NeonI_3VSame_B_sizes<0b0, 0b00, 0b00011, "and", and, and, 1>;
 311
 312 // Vector Bitwise Exclusive OR
 313
 314 defm EORvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b00011, "eor", xor, xor, 1>;
 315
 316 // Vector Bitwise OR
 317
 318 defm ORRvvv : NeonI_3VSame_B_sizes<0b0, 0b10, 0b00011, "orr", or, or, 1>;
 319
 320 // ORR disassembled as MOV if Vn==Vm
 321
 322 // Vector Move - register
 323 // Alias for ORR if Vn=Vm.
 324 // FIXME: This is actually the preferred syntax but TableGen can't deal with
 325 // custom printing of aliases.
 326 def : NeonInstAlias<"mov $Rd.8b, $Rn.8b",
 327                     (ORRvvv_8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rn), 0>;
 328 def : NeonInstAlias<"mov $Rd.16b, $Rn.16b",
 329                     (ORRvvv_16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rn), 0>;
 330
 331 def Neon_immAllOnes: PatLeaf<(Neon_movi (i32 timm), (i32 imm)), [{
 332   ConstantSDNode *ImmConstVal = cast<ConstantSDNode>(N->getOperand(0));
 333   ConstantSDNode *OpCmodeConstVal = cast<ConstantSDNode>(N->getOperand(1));
 334   unsigned EltBits;
 335   uint64_t EltVal = A64Imms::decodeNeonModImm(ImmConstVal->getZExtValue(),
 336     OpCmodeConstVal->getZExtValue(), EltBits);
 337   return (EltBits == 8 && EltVal == 0xff);
 338 }]>;
 339
 340 def Neon_immAllZeros: PatLeaf<(Neon_movi (i32 timm), (i32 imm)), [{
 341   ConstantSDNode *ImmConstVal = cast<ConstantSDNode>(N->getOperand(0));
 342   ConstantSDNode *OpCmodeConstVal = cast<ConstantSDNode>(N->getOperand(1));
 343   unsigned EltBits;
 344   uint64_t EltVal = A64Imms::decodeNeonModImm(ImmConstVal->getZExtValue(),
 345     OpCmodeConstVal->getZExtValue(), EltBits);
 346   return (EltBits == 8 && EltVal == 0x0);
 347 }]>;
 348
 349
 350 def Neon_not8B  : PatFrag<(ops node:$in),
 351                           (xor node:$in, (bitconvert (v8i8 Neon_immAllOnes)))>;
 352 def Neon_not16B : PatFrag<(ops node:$in),
 353                           (xor node:$in, (bitconvert (v16i8 Neon_immAllOnes)))>;
 354
 355 def Neon_orn8B : PatFrag<(ops node:$Rn, node:$Rm),
 356                          (or node:$Rn, (Neon_not8B node:$Rm))>;
 357
 358 def Neon_orn16B : PatFrag<(ops node:$Rn, node:$Rm),
 359                           (or node:$Rn, (Neon_not16B node:$Rm))>;
 360
 361 def Neon_bic8B : PatFrag<(ops node:$Rn, node:$Rm),
 362                          (and node:$Rn, (Neon_not8B node:$Rm))>;
 363
 364 def Neon_bic16B : PatFrag<(ops node:$Rn, node:$Rm),
 365                           (and node:$Rn, (Neon_not16B node:$Rm))>;
 366
 367
 368 // Vector Bitwise OR NOT - register
 369
 370 defm ORNvvv : NeonI_3VSame_B_sizes<0b0, 0b11, 0b00011, "orn",
 371                                    Neon_orn8B, Neon_orn16B, 0>;
 372
 373 // Vector Bitwise Bit Clear (AND NOT) - register
 374
 375 defm BICvvv : NeonI_3VSame_B_sizes<0b0, 0b01, 0b00011, "bic",
 376                                    Neon_bic8B, Neon_bic16B, 0>;
 377
 378 multiclass Neon_bitwise2V_patterns<SDPatternOperator opnode8B,
 379                                    SDPatternOperator opnode16B,
 380                                    Instruction INST8B,
 381                                    Instruction INST16B> {
 382   def : Pat<(v2i32 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 383             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 384   def : Pat<(v4i16 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 385             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 386   def : Pat<(v1i64 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 387             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 388   def : Pat<(v4i32 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 389             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 390   def : Pat<(v8i16 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 391             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 392   def : Pat<(v2i64 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 393             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 394 }
 395
 396 // Additional patterns for bitwise instructions AND, EOR, ORR, BIC, ORN
 397 defm : Neon_bitwise2V_patterns<and, and, ANDvvv_8B, ANDvvv_16B>;
 398 defm : Neon_bitwise2V_patterns<or,  or,  ORRvvv_8B, ORRvvv_16B>;
 399 defm : Neon_bitwise2V_patterns<xor, xor, EORvvv_8B, EORvvv_16B>;
 400 defm : Neon_bitwise2V_patterns<Neon_bic8B, Neon_bic16B, BICvvv_8B, BICvvv_16B>;
 401 defm : Neon_bitwise2V_patterns<Neon_orn8B, Neon_orn16B, ORNvvv_8B, ORNvvv_16B>;
 402
 403 //   Vector Bitwise Select
 404 def BSLvvv_8B  : NeonI_3VSame_Constraint_impl<"bsl", ".8b",  VPR64, v8i8,
 405                                               0b0, 0b1, 0b01, 0b00011, Neon_bsl>;
 406
 407 def BSLvvv_16B : NeonI_3VSame_Constraint_impl<"bsl", ".16b", VPR128, v16i8,
 408                                               0b1, 0b1, 0b01, 0b00011, Neon_bsl>;
 409
 410 multiclass Neon_bitwise3V_patterns<SDPatternOperator opnode,
 411                                    Instruction INST8B,
 412                                    Instruction INST16B> {
 413   // Disassociate type from instruction definition
 414   def : Pat<(v2i32 (opnode VPR64:$src,VPR64:$Rn, VPR64:$Rm)),
 415             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 416   def : Pat<(v4i16 (opnode VPR64:$src, VPR64:$Rn, VPR64:$Rm)),
 417             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 418   def : Pat<(v1i64 (opnode VPR64:$src, VPR64:$Rn, VPR64:$Rm)),
 419             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 420   def : Pat<(v4i32 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
 421             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 422   def : Pat<(v8i16 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
 423             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 424   def : Pat<(v2i64 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
 425             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 426
 427   // Allow to match BSL instruction pattern with non-constant operand
 428   def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
 429                     (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 430           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 431   def : Pat<(v4i16 (or (and VPR64:$Rn, VPR64:$Rd),
 432                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 433           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 434   def : Pat<(v2i32 (or (and VPR64:$Rn, VPR64:$Rd),
 435                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 436           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 437   def : Pat<(v1i64 (or (and VPR64:$Rn, VPR64:$Rd),
 438                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 439           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 440   def : Pat<(v16i8 (or (and VPR128:$Rn, VPR128:$Rd),
 441                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 442           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 443   def : Pat<(v8i16 (or (and VPR128:$Rn, VPR128:$Rd),
 444                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 445           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 446   def : Pat<(v4i32 (or (and VPR128:$Rn, VPR128:$Rd),
 447                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 448           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 449   def : Pat<(v2i64 (or (and VPR128:$Rn, VPR128:$Rd),
 450                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 451           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 452
 453   // Allow to match llvm.arm.* intrinsics.
 454   def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 VPR64:$src),
 455                     (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
 456             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 457   def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 VPR64:$src),
 458                     (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
 459             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 460   def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 VPR64:$src),
 461                     (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
 462             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 463   def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 VPR64:$src),
 464                     (v1i64 VPR64:$Rn), (v1i64 VPR64:$Rm))),
 465             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 466   def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 VPR64:$src),
 467                     (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
 468             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 469   def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 VPR128:$src),
 470                     (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
 471             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 472   def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 VPR128:$src),
 473                     (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
 474             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 475   def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 VPR128:$src),
 476                     (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
 477             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 478   def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 VPR128:$src),
 479                     (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
 480             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 481   def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 VPR128:$src),
 482                     (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
 483             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 484   def : Pat<(v2f64 (int_arm_neon_vbsl (v2f64 VPR128:$src),
 485                     (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
 486             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 487 }
 488
 489 // Additional patterns for bitwise instruction BSL
 490 defm: Neon_bitwise3V_patterns<Neon_bsl, BSLvvv_8B, BSLvvv_16B>;
 491
 492 def Neon_NoBSLop : PatFrag<(ops node:$src, node:$Rn, node:$Rm),
 493                            (Neon_bsl node:$src, node:$Rn, node:$Rm),
 494                            [{ (void)N; return false; }]>;
 495
 496 // Vector Bitwise Insert if True
 497
 498 def BITvvv_8B  : NeonI_3VSame_Constraint_impl<"bit", ".8b", VPR64,   v8i8,
 499                    0b0, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
 500 def BITvvv_16B : NeonI_3VSame_Constraint_impl<"bit", ".16b", VPR128, v16i8,
 501                    0b1, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
 502
 503 // Vector Bitwise Insert if False
 504
 505 def BIFvvv_8B  : NeonI_3VSame_Constraint_impl<"bif", ".8b", VPR64,  v8i8,
 506                                 0b0, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
 507 def BIFvvv_16B : NeonI_3VSame_Constraint_impl<"bif", ".16b", VPR128, v16i8,
 508                                 0b1, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
 509
 510 // Vector Absolute Difference and Accumulate (Signed, Unsigned)
 511
 512 def Neon_uaba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 513                        (add node:$Ra, (int_arm_neon_vabdu node:$Rn, node:$Rm))>;
 514 def Neon_saba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 515                        (add node:$Ra, (int_arm_neon_vabds node:$Rn, node:$Rm))>;
 516
 517 // Vector Absolute Difference and Accumulate (Unsigned)
 518 def UABAvvv_8B :  NeonI_3VSame_Constraint_impl<"uaba", ".8b",  VPR64,  v8i8,
 519                     0b0, 0b1, 0b00, 0b01111, Neon_uaba>;
 520 def UABAvvv_16B : NeonI_3VSame_Constraint_impl<"uaba", ".16b", VPR128, v16i8,
 521                     0b1, 0b1, 0b00, 0b01111, Neon_uaba>;
 522 def UABAvvv_4H :  NeonI_3VSame_Constraint_impl<"uaba", ".4h",  VPR64,  v4i16,
 523                     0b0, 0b1, 0b01, 0b01111, Neon_uaba>;
 524 def UABAvvv_8H :  NeonI_3VSame_Constraint_impl<"uaba", ".8h",  VPR128, v8i16,
 525                     0b1, 0b1, 0b01, 0b01111, Neon_uaba>;
 526 def UABAvvv_2S :  NeonI_3VSame_Constraint_impl<"uaba", ".2s",  VPR64,  v2i32,
 527                     0b0, 0b1, 0b10, 0b01111, Neon_uaba>;
 528 def UABAvvv_4S :  NeonI_3VSame_Constraint_impl<"uaba", ".4s",  VPR128, v4i32,
 529                     0b1, 0b1, 0b10, 0b01111, Neon_uaba>;
 530
 531 // Vector Absolute Difference and Accumulate (Signed)
 532 def SABAvvv_8B :  NeonI_3VSame_Constraint_impl<"saba", ".8b",  VPR64,  v8i8,
 533                     0b0, 0b0, 0b00, 0b01111, Neon_saba>;
 534 def SABAvvv_16B : NeonI_3VSame_Constraint_impl<"saba", ".16b", VPR128, v16i8,
 535                     0b1, 0b0, 0b00, 0b01111, Neon_saba>;
 536 def SABAvvv_4H :  NeonI_3VSame_Constraint_impl<"saba", ".4h",  VPR64,  v4i16,
 537                     0b0, 0b0, 0b01, 0b01111, Neon_saba>;
 538 def SABAvvv_8H :  NeonI_3VSame_Constraint_impl<"saba", ".8h",  VPR128, v8i16,
 539                     0b1, 0b0, 0b01, 0b01111, Neon_saba>;
 540 def SABAvvv_2S :  NeonI_3VSame_Constraint_impl<"saba", ".2s",  VPR64,  v2i32,
 541                     0b0, 0b0, 0b10, 0b01111, Neon_saba>;
 542 def SABAvvv_4S :  NeonI_3VSame_Constraint_impl<"saba", ".4s",  VPR128, v4i32,
 543                     0b1, 0b0, 0b10, 0b01111, Neon_saba>;
 544
 545
 546 // Vector Absolute Difference (Signed, Unsigned)
 547 defm UABDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01110, "uabd", int_arm_neon_vabdu, 0>;
 548 defm SABDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01110, "sabd", int_arm_neon_vabds, 0>;
 549
 550 // Vector Absolute Difference (Floating Point)
 551 defm FABDvvv: NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11010, "fabd",
 552                                     int_arm_neon_vabds, int_arm_neon_vabds,
 553                                     int_arm_neon_vabds, v2f32, v4f32, v2f64, 0>;
 554
 555 // Vector Reciprocal Step (Floating Point)
 556 defm FRECPSvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11111, "frecps",
 557                                        int_arm_neon_vrecps, int_arm_neon_vrecps,
 558                                        int_arm_neon_vrecps,
 559                                        v2f32, v4f32, v2f64, 0>;
 560
 561 // Vector Reciprocal Square Root Step (Floating Point)
 562 defm FRSQRTSvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11111, "frsqrts",
 563                                         int_arm_neon_vrsqrts,
 564                                         int_arm_neon_vrsqrts,
 565                                         int_arm_neon_vrsqrts,
 566                                         v2f32, v4f32, v2f64, 0>;
 567
 568 // Vector Comparisons
 569
 570 def Neon_cmeq : PatFrag<(ops node:$lhs, node:$rhs),
 571                         (Neon_cmp node:$lhs, node:$rhs, SETEQ)>;
 572 def Neon_cmphs : PatFrag<(ops node:$lhs, node:$rhs),
 573                          (Neon_cmp node:$lhs, node:$rhs, SETUGE)>;
 574 def Neon_cmge : PatFrag<(ops node:$lhs, node:$rhs),
 575                         (Neon_cmp node:$lhs, node:$rhs, SETGE)>;
 576 def Neon_cmhi : PatFrag<(ops node:$lhs, node:$rhs),
 577                         (Neon_cmp node:$lhs, node:$rhs, SETUGT)>;
 578 def Neon_cmgt : PatFrag<(ops node:$lhs, node:$rhs),
 579                         (Neon_cmp node:$lhs, node:$rhs, SETGT)>;
 580
 581 // NeonI_compare_aliases class: swaps register operands to implement
 582 // comparison aliases, e.g., CMLE is alias for CMGE with operands reversed.
 583 class NeonI_compare_aliases<string asmop, string asmlane,
 584                             Instruction inst, RegisterOperand VPRC>
 585   : NeonInstAlias<asmop # "\t$Rd" # asmlane #", $Rn" # asmlane #
 586                     ", $Rm" # asmlane,
 587                   (inst VPRC:$Rd, VPRC:$Rm, VPRC:$Rn), 0b0>;
 588
 589 // Vector Comparisons (Integer)
 590
 591 // Vector Compare Mask Equal (Integer)
 592 let isCommutable =1 in {
 593 defm CMEQvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10001, "cmeq", Neon_cmeq, 0>;
 594 }
 595
 596 // Vector Compare Mask Higher or Same (Unsigned Integer)
 597 defm CMHSvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00111, "cmhs", Neon_cmphs, 0>;
 598
 599 // Vector Compare Mask Greater Than or Equal (Integer)
 600 defm CMGEvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00111, "cmge", Neon_cmge, 0>;
 601
 602 // Vector Compare Mask Higher (Unsigned Integer)
 603 defm CMHIvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00110, "cmhi", Neon_cmhi, 0>;
 604
 605 // Vector Compare Mask Greater Than (Integer)
 606 defm CMGTvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00110, "cmgt", Neon_cmgt, 0>;
 607
 608 // Vector Compare Mask Bitwise Test (Integer)
 609 defm CMTSTvvv:  NeonI_3VSame_BHSD_sizes<0b0, 0b10001, "cmtst", Neon_tst, 0>;
 610
 611 // Vector Compare Mask Less or Same (Unsigned Integer)
 612 // CMLS is alias for CMHS with operands reversed.
 613 def CMLSvvv_8B  : NeonI_compare_aliases<"cmls", ".8b",  CMHSvvv_8B,  VPR64>;
 614 def CMLSvvv_16B : NeonI_compare_aliases<"cmls", ".16b", CMHSvvv_16B, VPR128>;
 615 def CMLSvvv_4H  : NeonI_compare_aliases<"cmls", ".4h",  CMHSvvv_4H,  VPR64>;
 616 def CMLSvvv_8H  : NeonI_compare_aliases<"cmls", ".8h",  CMHSvvv_8H,  VPR128>;
 617 def CMLSvvv_2S  : NeonI_compare_aliases<"cmls", ".2s",  CMHSvvv_2S,  VPR64>;
 618 def CMLSvvv_4S  : NeonI_compare_aliases<"cmls", ".4s",  CMHSvvv_4S,  VPR128>;
 619 def CMLSvvv_2D  : NeonI_compare_aliases<"cmls", ".2d",  CMHSvvv_2D,  VPR128>;
 620
 621 // Vector Compare Mask Less Than or Equal (Integer)
 622 // CMLE is alias for CMGE with operands reversed.
 623 def CMLEvvv_8B  : NeonI_compare_aliases<"cmle", ".8b",  CMGEvvv_8B,  VPR64>;
 624 def CMLEvvv_16B : NeonI_compare_aliases<"cmle", ".16b", CMGEvvv_16B, VPR128>;
 625 def CMLEvvv_4H  : NeonI_compare_aliases<"cmle", ".4h",  CMGEvvv_4H,  VPR64>;
 626 def CMLEvvv_8H  : NeonI_compare_aliases<"cmle", ".8h",  CMGEvvv_8H,  VPR128>;
 627 def CMLEvvv_2S  : NeonI_compare_aliases<"cmle", ".2s",  CMGEvvv_2S,  VPR64>;
 628 def CMLEvvv_4S  : NeonI_compare_aliases<"cmle", ".4s",  CMGEvvv_4S,  VPR128>;
 629 def CMLEvvv_2D  : NeonI_compare_aliases<"cmle", ".2d",  CMGEvvv_2D,  VPR128>;
 630
 631 // Vector Compare Mask Lower (Unsigned Integer)
 632 // CMLO is alias for CMHI with operands reversed.
 633 def CMLOvvv_8B  : NeonI_compare_aliases<"cmlo", ".8b",  CMHIvvv_8B,  VPR64>;
 634 def CMLOvvv_16B : NeonI_compare_aliases<"cmlo", ".16b", CMHIvvv_16B, VPR128>;
 635 def CMLOvvv_4H  : NeonI_compare_aliases<"cmlo", ".4h",  CMHIvvv_4H,  VPR64>;
 636 def CMLOvvv_8H  : NeonI_compare_aliases<"cmlo", ".8h",  CMHIvvv_8H,  VPR128>;
 637 def CMLOvvv_2S  : NeonI_compare_aliases<"cmlo", ".2s",  CMHIvvv_2S,  VPR64>;
 638 def CMLOvvv_4S  : NeonI_compare_aliases<"cmlo", ".4s",  CMHIvvv_4S,  VPR128>;
 639 def CMLOvvv_2D  : NeonI_compare_aliases<"cmlo", ".2d",  CMHIvvv_2D,  VPR128>;
 640
 641 // Vector Compare Mask Less Than (Integer)
 642 // CMLT is alias for CMGT with operands reversed.
 643 def CMLTvvv_8B  : NeonI_compare_aliases<"cmlt", ".8b",  CMGTvvv_8B,  VPR64>;
 644 def CMLTvvv_16B : NeonI_compare_aliases<"cmlt", ".16b", CMGTvvv_16B, VPR128>;
 645 def CMLTvvv_4H  : NeonI_compare_aliases<"cmlt", ".4h",  CMGTvvv_4H,  VPR64>;
 646 def CMLTvvv_8H  : NeonI_compare_aliases<"cmlt", ".8h",  CMGTvvv_8H,  VPR128>;
 647 def CMLTvvv_2S  : NeonI_compare_aliases<"cmlt", ".2s",  CMGTvvv_2S,  VPR64>;
 648 def CMLTvvv_4S  : NeonI_compare_aliases<"cmlt", ".4s",  CMGTvvv_4S,  VPR128>;
 649 def CMLTvvv_2D  : NeonI_compare_aliases<"cmlt", ".2d",  CMGTvvv_2D,  VPR128>;
 650
 651
 652 def neon_uimm0_asmoperand : AsmOperandClass
 653 {
 654   let Name = "UImm0";
 655   let PredicateMethod = "isUImm<0>";
 656   let RenderMethod = "addImmOperands";
 657 }
 658
 659 def neon_uimm0 : Operand<i32>, ImmLeaf<i32, [{return Imm == 0;}]> {
 660   let ParserMatchClass = neon_uimm0_asmoperand;
 661   let PrintMethod = "printNeonUImm0Operand";
 662
 663 }
 664
 665 multiclass NeonI_cmpz_sizes<bit u, bits<5> opcode, string asmop, CondCode CC>
 666 {
 667   def _8B :  NeonI_2VMisc<0b0, u, 0b00, opcode,
 668              (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 669              asmop # "\t$Rd.8b, $Rn.8b, $Imm",
 670              [(set (v8i8 VPR64:$Rd),
 671                 (v8i8 (Neon_cmpz (v8i8 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 672              NoItinerary>;
 673
 674   def _16B : NeonI_2VMisc<0b1, u, 0b00, opcode,
 675              (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 676              asmop # "\t$Rd.16b, $Rn.16b, $Imm",
 677              [(set (v16i8 VPR128:$Rd),
 678                 (v16i8 (Neon_cmpz (v16i8 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 679              NoItinerary>;
 680
 681   def _4H : NeonI_2VMisc<0b0, u, 0b01, opcode,
 682             (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 683             asmop # "\t$Rd.4h, $Rn.4h, $Imm",
 684             [(set (v4i16 VPR64:$Rd),
 685                (v4i16 (Neon_cmpz (v4i16 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 686             NoItinerary>;
 687
 688   def _8H : NeonI_2VMisc<0b1, u, 0b01, opcode,
 689             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 690             asmop # "\t$Rd.8h, $Rn.8h, $Imm",
 691             [(set (v8i16 VPR128:$Rd),
 692                (v8i16 (Neon_cmpz (v8i16 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 693             NoItinerary>;
 694
 695   def _2S : NeonI_2VMisc<0b0, u, 0b10, opcode,
 696             (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 697             asmop # "\t$Rd.2s, $Rn.2s, $Imm",
 698             [(set (v2i32 VPR64:$Rd),
 699                (v2i32 (Neon_cmpz (v2i32 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 700             NoItinerary>;
 701
 702   def _4S : NeonI_2VMisc<0b1, u, 0b10, opcode,
 703             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 704             asmop # "\t$Rd.4s, $Rn.4s, $Imm",
 705             [(set (v4i32 VPR128:$Rd),
 706                (v4i32 (Neon_cmpz (v4i32 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 707             NoItinerary>;
 708
 709   def _2D : NeonI_2VMisc<0b1, u, 0b11, opcode,
 710             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 711             asmop # "\t$Rd.2d, $Rn.2d, $Imm",
 712             [(set (v2i64 VPR128:$Rd),
 713                (v2i64 (Neon_cmpz (v2i64 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 714             NoItinerary>;
 715 }
 716
 717 // Vector Compare Mask Equal to Zero (Integer)
 718 defm CMEQvvi : NeonI_cmpz_sizes<0b0, 0b01001, "cmeq", SETEQ>;
 719
 720 // Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
 721 defm CMGEvvi : NeonI_cmpz_sizes<0b1, 0b01000, "cmge", SETGE>;
 722
 723 // Vector Compare Mask Greater Than Zero (Signed Integer)
 724 defm CMGTvvi : NeonI_cmpz_sizes<0b0, 0b01000, "cmgt", SETGT>;
 725
 726 // Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
 727 defm CMLEvvi : NeonI_cmpz_sizes<0b1, 0b01001, "cmle", SETLE>;
 728
 729 // Vector Compare Mask Less Than Zero (Signed Integer)
 730 defm CMLTvvi : NeonI_cmpz_sizes<0b0, 0b01010, "cmlt", SETLT>;
 731
 732 // Vector Comparisons (Floating Point)
 733
 734 // Vector Compare Mask Equal (Floating Point)
 735 let isCommutable =1 in {
 736 defm FCMEQvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11100, "fcmeq", Neon_cmeq,
 737                                       Neon_cmeq, Neon_cmeq,
 738                                       v2i32, v4i32, v2i64, 0>;
 739 }
 740
 741 // Vector Compare Mask Greater Than Or Equal (Floating Point)
 742 defm FCMGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11100, "fcmge", Neon_cmge,
 743                                       Neon_cmge, Neon_cmge,
 744                                       v2i32, v4i32, v2i64, 0>;
 745
 746 // Vector Compare Mask Greater Than (Floating Point)
 747 defm FCMGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11100, "fcmgt", Neon_cmgt,
 748                                       Neon_cmgt, Neon_cmgt,
 749                                       v2i32, v4i32, v2i64, 0>;
 750
 751 // Vector Compare Mask Less Than Or Equal (Floating Point)
 752 // FCMLE is alias for FCMGE with operands reversed.
 753 def FCMLEvvv_2S  : NeonI_compare_aliases<"fcmle", ".2s",  FCMGEvvv_2S,  VPR64>;
 754 def FCMLEvvv_4S  : NeonI_compare_aliases<"fcmle", ".4s",  FCMGEvvv_4S,  VPR128>;
 755 def FCMLEvvv_2D  : NeonI_compare_aliases<"fcmle", ".2d",  FCMGEvvv_2D,  VPR128>;
 756
 757 // Vector Compare Mask Less Than (Floating Point)
 758 // FCMLT is alias for FCMGT with operands reversed.
 759 def FCMLTvvv_2S  : NeonI_compare_aliases<"fcmlt", ".2s",  FCMGTvvv_2S,  VPR64>;
 760 def FCMLTvvv_4S  : NeonI_compare_aliases<"fcmlt", ".4s",  FCMGTvvv_4S,  VPR128>;
 761 def FCMLTvvv_2D  : NeonI_compare_aliases<"fcmlt", ".2d",  FCMGTvvv_2D,  VPR128>;
 762
 763
 764 multiclass NeonI_fpcmpz_sizes<bit u, bit size, bits<5> opcode,
 765                               string asmop, CondCode CC>
 766 {
 767   def _2S : NeonI_2VMisc<0b0, u, {size, 0b0}, opcode,
 768             (outs VPR64:$Rd), (ins VPR64:$Rn, fpz32:$FPImm),
 769             asmop # "\t$Rd.2s, $Rn.2s, $FPImm",
 770             [(set (v2i32 VPR64:$Rd),
 771                (v2i32 (Neon_cmpz (v2f32 VPR64:$Rn), (f32 fpimm:$FPImm), CC)))],
 772             NoItinerary>;
 773
 774   def _4S : NeonI_2VMisc<0b1, u, {size, 0b0}, opcode,
 775             (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
 776             asmop # "\t$Rd.4s, $Rn.4s, $FPImm",
 777             [(set (v4i32 VPR128:$Rd),
 778                (v4i32 (Neon_cmpz (v4f32 VPR128:$Rn), (f32 fpimm:$FPImm), CC)))],
 779             NoItinerary>;
 780
 781   def _2D : NeonI_2VMisc<0b1, u, {size, 0b1}, opcode,
 782             (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
 783             asmop # "\t$Rd.2d, $Rn.2d, $FPImm",
 784             [(set (v2i64 VPR128:$Rd),
 785                (v2i64 (Neon_cmpz (v2f64 VPR128:$Rn), (f32 fpimm:$FPImm), CC)))],
 786             NoItinerary>;
 787 }
 788
 789 // Vector Compare Mask Equal to Zero (Floating Point)
 790 defm FCMEQvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01101, "fcmeq", SETEQ>;
 791
 792 // Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
 793 defm FCMGEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01100, "fcmge", SETGE>;
 794
 795 // Vector Compare Mask Greater Than Zero (Floating Point)
 796 defm FCMGTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01100, "fcmgt", SETGT>;
 797
 798 // Vector Compare Mask Less Than or Equal To Zero (Floating Point)
 799 defm FCMLEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01101, "fcmle", SETLE>;
 800
 801 // Vector Compare Mask Less Than Zero (Floating Point)
 802 defm FCMLTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01110, "fcmlt", SETLT>;
 803
 804 // Vector Absolute Comparisons (Floating Point)
 805
 806 // Vector Absolute Compare Mask Greater Than Or Equal (Floating Point)
 807 defm FACGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11101, "facge",
 808                                       int_arm_neon_vacged, int_arm_neon_vacgeq,
 809                                       int_aarch64_neon_vacgeq,
 810                                       v2i32, v4i32, v2i64, 0>;
 811
 812 // Vector Absolute Compare Mask Greater Than (Floating Point)
 813 defm FACGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11101, "facgt",
 814                                       int_arm_neon_vacgtd, int_arm_neon_vacgtq,
 815                                       int_aarch64_neon_vacgtq,
 816                                       v2i32, v4i32, v2i64, 0>;
 817
 818 // Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
 819 // FACLE is alias for FACGE with operands reversed.
 820 def FACLEvvv_2S  : NeonI_compare_aliases<"facle", ".2s",  FACGEvvv_2S,  VPR64>;
 821 def FACLEvvv_4S  : NeonI_compare_aliases<"facle", ".4s",  FACGEvvv_4S,  VPR128>;
 822 def FACLEvvv_2D  : NeonI_compare_aliases<"facle", ".2d",  FACGEvvv_2D,  VPR128>;
 823
 824 // Vector Absolute Compare Mask Less Than (Floating Point)
 825 // FACLT is alias for FACGT with operands reversed.
 826 def FACLTvvv_2S  : NeonI_compare_aliases<"faclt", ".2s",  FACGTvvv_2S,  VPR64>;
 827 def FACLTvvv_4S  : NeonI_compare_aliases<"faclt", ".4s",  FACGTvvv_4S,  VPR128>;
 828 def FACLTvvv_2D  : NeonI_compare_aliases<"faclt", ".2d",  FACGTvvv_2D,  VPR128>;
 829
 830 // Vector halving add (Integer Signed, Unsigned)
 831 defm SHADDvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00000, "shadd",
 832                                         int_arm_neon_vhadds, 1>;
 833 defm UHADDvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00000, "uhadd",
 834                                         int_arm_neon_vhaddu, 1>;
 835
 836 // Vector halving sub (Integer Signed, Unsigned)
 837 defm SHSUBvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00100, "shsub",
 838                                         int_arm_neon_vhsubs, 0>;
 839 defm UHSUBvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00100, "uhsub",
 840                                         int_arm_neon_vhsubu, 0>;
 841
 842 // Vector rouding halving add (Integer Signed, Unsigned)
 843 defm SRHADDvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00010, "srhadd",
 844                                          int_arm_neon_vrhadds, 1>;
 845 defm URHADDvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00010, "urhadd",
 846                                          int_arm_neon_vrhaddu, 1>;
 847
 848 // Vector Saturating add (Integer Signed, Unsigned)
 849 defm SQADDvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b00001, "sqadd",
 850                    int_arm_neon_vqadds, 1>;
 851 defm UQADDvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b00001, "uqadd",
 852                    int_arm_neon_vqaddu, 1>;
 853
 854 // Vector Saturating sub (Integer Signed, Unsigned)
 855 defm SQSUBvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b00101, "sqsub",
 856                    int_arm_neon_vqsubs, 1>;
 857 defm UQSUBvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b00101, "uqsub",
 858                    int_arm_neon_vqsubu, 1>;
 859
 860 // Vector Shift Left (Signed and Unsigned Integer)
 861 defm SSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01000, "sshl",
 862                  int_arm_neon_vshifts, 1>;
 863 defm USHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01000, "ushl",
 864                  int_arm_neon_vshiftu, 1>;
 865
 866 // Vector Saturating Shift Left (Signed and Unsigned Integer)
 867 defm SQSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01001, "sqshl",
 868                   int_arm_neon_vqshifts, 1>;
 869 defm UQSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01001, "uqshl",
 870                   int_arm_neon_vqshiftu, 1>;
 871
 872 // Vector Rouding Shift Left (Signed and Unsigned Integer)
 873 defm SRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01010, "srshl",
 874                   int_arm_neon_vrshifts, 1>;
 875 defm URSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01010, "urshl",
 876                   int_arm_neon_vrshiftu, 1>;
 877
 878 // Vector Saturating Rouding Shift Left (Signed and Unsigned Integer)
 879 defm SQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01011, "sqrshl",
 880                    int_arm_neon_vqrshifts, 1>;
 881 defm UQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01011, "uqrshl",
 882                    int_arm_neon_vqrshiftu, 1>;
 883
 884 // Vector Maximum (Signed and Unsigned Integer)
 885 defm SMAXvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01100, "smax", int_arm_neon_vmaxs, 1>;
 886 defm UMAXvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01100, "umax", int_arm_neon_vmaxu, 1>;
 887
 888 // Vector Minimum (Signed and Unsigned Integer)
 889 defm SMINvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01101, "smin", int_arm_neon_vmins, 1>;
 890 defm UMINvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01101, "umin", int_arm_neon_vminu, 1>;
 891
 892 // Vector Maximum (Floating Point)
 893 defm FMAXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11110, "fmax",
 894                                      int_arm_neon_vmaxs, int_arm_neon_vmaxs,
 895                                      int_arm_neon_vmaxs, v2f32, v4f32, v2f64, 1>;
 896
 897 // Vector Minimum (Floating Point)
 898 defm FMINvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11110, "fmin",
 899                                      int_arm_neon_vmins, int_arm_neon_vmins,
 900                                      int_arm_neon_vmins, v2f32, v4f32, v2f64, 1>;
 901
 902 // Vector maxNum (Floating Point) -  prefer a number over a quiet NaN)
 903 defm FMAXNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11000, "fmaxnm",
 904                                        int_aarch64_neon_vmaxnm,
 905                                        int_aarch64_neon_vmaxnm,
 906                                        int_aarch64_neon_vmaxnm,
 907                                        v2f32, v4f32, v2f64, 1>;
 908
 909 // Vector minNum (Floating Point) - prefer a number over a quiet NaN)
 910 defm FMINNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11000, "fminnm",
 911                                        int_aarch64_neon_vminnm,
 912                                        int_aarch64_neon_vminnm,
 913                                        int_aarch64_neon_vminnm,
 914                                        v2f32, v4f32, v2f64, 1>;
 915
 916 // Vector Maximum Pairwise (Signed and Unsigned Integer)
 917 defm SMAXPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10100, "smaxp", int_arm_neon_vpmaxs, 1>;
 918 defm UMAXPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10100, "umaxp", int_arm_neon_vpmaxu, 1>;
 919
 920 // Vector Minimum Pairwise (Signed and Unsigned Integer)
 921 defm SMINPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10101, "sminp", int_arm_neon_vpmins, 1>;
 922 defm UMINPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10101, "uminp", int_arm_neon_vpminu, 1>;
 923
 924 // Vector Maximum Pairwise (Floating Point)
 925 defm FMAXPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11110, "fmaxp",
 926                                      int_arm_neon_vpmaxs, int_arm_neon_vpmaxs,
 927                                      int_arm_neon_vpmaxs, v2f32, v4f32, v2f64, 1>;
 928
 929 // Vector Minimum Pairwise (Floating Point)
 930 defm FMINPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11110, "fminp",
 931                                      int_arm_neon_vpmins, int_arm_neon_vpmins,
 932                                      int_arm_neon_vpmins, v2f32, v4f32, v2f64, 1>;
 933
 934 // Vector maxNum Pairwise (Floating Point) -  prefer a number over a quiet NaN)
 935 defm FMAXNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11000, "fmaxnmp",
 936                                        int_aarch64_neon_vpmaxnm,
 937                                        int_aarch64_neon_vpmaxnm,
 938                                        int_aarch64_neon_vpmaxnm,
 939                                        v2f32, v4f32, v2f64, 1>;
 940
 941 // Vector minNum Pairwise (Floating Point) -  prefer a number over a quiet NaN)
 942 defm FMINNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11000, "fminnmp",
 943                                        int_aarch64_neon_vpminnm,
 944                                        int_aarch64_neon_vpminnm,
 945                                        int_aarch64_neon_vpminnm,
 946                                        v2f32, v4f32, v2f64, 1>;
 947
 948 // Vector Addition Pairwise (Integer)
 949 defm ADDP : NeonI_3VSame_BHSD_sizes<0b0, 0b10111, "addp", int_arm_neon_vpadd, 1>;
 950
 951 // Vector Addition Pairwise (Floating Point)
 952 defm FADDP : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11010, "faddp",
 953                                        int_arm_neon_vpadd,
 954                                        int_arm_neon_vpadd,
 955                                        int_arm_neon_vpadd,
 956                                        v2f32, v4f32, v2f64, 1>;
 957
 958 // Vector Saturating Doubling Multiply High
 959 defm SQDMULHvvv : NeonI_3VSame_HS_sizes<0b0, 0b10110, "sqdmulh",
 960                     int_arm_neon_vqdmulh, 1>;
 961
 962 // Vector Saturating Rouding Doubling Multiply High
 963 defm SQRDMULHvvv : NeonI_3VSame_HS_sizes<0b1, 0b10110, "sqrdmulh",
 964                      int_arm_neon_vqrdmulh, 1>;
 965
 966 // Vector Multiply Extended (Floating Point)
 967 defm FMULXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11011, "fmulx",
 968                                       int_aarch64_neon_vmulx,
 969                                       int_aarch64_neon_vmulx,
 970                                       int_aarch64_neon_vmulx,
 971                                       v2f32, v4f32, v2f64, 1>;
 972
 973 // Vector Immediate Instructions
 974
 975 multiclass neon_mov_imm_shift_asmoperands<string PREFIX>
 976 {
 977   def _asmoperand : AsmOperandClass
 978     {
 979       let Name = "NeonMovImmShift" # PREFIX;
 980       let RenderMethod = "addNeonMovImmShift" # PREFIX # "Operands";
 981       let PredicateMethod = "isNeonMovImmShift" # PREFIX;
 982     }
 983 }
 984
 985 // Definition of vector immediates shift operands
 986
 987 // The selectable use-cases extract the shift operation
 988 // information from the OpCmode fields encoded in the immediate.
 989 def neon_mod_shift_imm_XFORM : SDNodeXForm<imm, [{
 990   uint64_t OpCmode = N->getZExtValue();
 991   unsigned ShiftImm;
 992   unsigned ShiftOnesIn;
 993   unsigned HasShift =
 994     A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
 995   if (!HasShift) return SDValue();
 996   return CurDAG->getTargetConstant(ShiftImm, MVT::i32);
 997 }]>;
 998
 999 // Vector immediates shift operands which accept LSL and MSL
1000 // shift operators with shift value in the range of 0, 8, 16, 24 (LSL),
1001 // or 0, 8 (LSLH) or 8, 16 (MSL).
1002 defm neon_mov_imm_LSL : neon_mov_imm_shift_asmoperands<"LSL">;
1003 defm neon_mov_imm_MSL : neon_mov_imm_shift_asmoperands<"MSL">;
1004 // LSLH restricts shift amount to  0, 8 out of 0, 8, 16, 24
1005 defm neon_mov_imm_LSLH : neon_mov_imm_shift_asmoperands<"LSLH">;
1006
1007 multiclass neon_mov_imm_shift_operands<string PREFIX,
1008                                        string HALF, string ISHALF, code pred>
1009 {
1010    def _operand : Operand<i32>, ImmLeaf<i32, pred, neon_mod_shift_imm_XFORM>
1011     {
1012       let PrintMethod =
1013         "printNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1014       let DecoderMethod =
1015         "DecodeNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1016       let ParserMatchClass =
1017         !cast<AsmOperandClass>("neon_mov_imm_" # PREFIX # HALF # "_asmoperand");
1018     }
1019 }
1020
1021 defm neon_mov_imm_LSL  : neon_mov_imm_shift_operands<"LSL", "", "false", [{
1022   unsigned ShiftImm;
1023   unsigned ShiftOnesIn;
1024   unsigned HasShift =
1025     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1026   return (HasShift && !ShiftOnesIn);
1027 }]>;
1028
1029 defm neon_mov_imm_MSL  : neon_mov_imm_shift_operands<"MSL", "", "false", [{
1030   unsigned ShiftImm;
1031   unsigned ShiftOnesIn;
1032   unsigned HasShift =
1033     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1034   return (HasShift && ShiftOnesIn);
1035 }]>;
1036
1037 defm neon_mov_imm_LSLH  : neon_mov_imm_shift_operands<"LSL", "H", "true", [{
1038   unsigned ShiftImm;
1039   unsigned ShiftOnesIn;
1040   unsigned HasShift =
1041     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1042   return (HasShift && !ShiftOnesIn);
1043 }]>;
1044
1045 def neon_uimm1_asmoperand : AsmOperandClass
1046 {
1047   let Name = "UImm1";
1048   let PredicateMethod = "isUImm<1>";
1049   let RenderMethod = "addImmOperands";
1050 }
1051
1052 def neon_uimm2_asmoperand : AsmOperandClass
1053 {
1054   let Name = "UImm2";
1055   let PredicateMethod = "isUImm<2>";
1056   let RenderMethod = "addImmOperands";
1057 }
1058
1059 def neon_uimm8_asmoperand : AsmOperandClass
1060 {
1061   let Name = "UImm8";
1062   let PredicateMethod = "isUImm<8>";
1063   let RenderMethod = "addImmOperands";
1064 }
1065
1066 def neon_uimm8 : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1067   let ParserMatchClass = neon_uimm8_asmoperand;
1068   let PrintMethod = "printUImmHexOperand";
1069 }
1070
1071 def neon_uimm64_mask_asmoperand : AsmOperandClass
1072 {
1073   let Name = "NeonUImm64Mask";
1074   let PredicateMethod = "isNeonUImm64Mask";
1075   let RenderMethod = "addNeonUImm64MaskOperands";
1076 }
1077
1078 // MCOperand for 64-bit bytemask with each byte having only the
1079 // value 0x00 and 0xff is encoded as an unsigned 8-bit value
1080 def neon_uimm64_mask : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1081   let ParserMatchClass = neon_uimm64_mask_asmoperand;
1082   let PrintMethod = "printNeonUImm64MaskOperand";
1083 }
1084
1085 multiclass NeonI_mov_imm_lsl_sizes<string asmop, bit op,
1086                                    SDPatternOperator opnode>
1087 {
1088     // shift zeros, per word
1089     def _2S  : NeonI_1VModImm<0b0, op,
1090                               (outs VPR64:$Rd),
1091                               (ins neon_uimm8:$Imm,
1092                                 neon_mov_imm_LSL_operand:$Simm),
1093                               !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1094                               [(set (v2i32 VPR64:$Rd),
1095                                  (v2i32 (opnode (timm:$Imm),
1096                                    (neon_mov_imm_LSL_operand:$Simm))))],
1097                               NoItinerary> {
1098        bits<2> Simm;
1099        let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1100      }
1101
1102     def _4S  : NeonI_1VModImm<0b1, op,
1103                               (outs VPR128:$Rd),
1104                               (ins neon_uimm8:$Imm,
1105                                 neon_mov_imm_LSL_operand:$Simm),
1106                               !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1107                               [(set (v4i32 VPR128:$Rd),
1108                                  (v4i32 (opnode (timm:$Imm),
1109                                    (neon_mov_imm_LSL_operand:$Simm))))],
1110                               NoItinerary> {
1111       bits<2> Simm;
1112       let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1113     }
1114
1115     // shift zeros, per halfword
1116     def _4H  : NeonI_1VModImm<0b0, op,
1117                               (outs VPR64:$Rd),
1118                               (ins neon_uimm8:$Imm,
1119                                 neon_mov_imm_LSLH_operand:$Simm),
1120                               !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1121                               [(set (v4i16 VPR64:$Rd),
1122                                  (v4i16 (opnode (timm:$Imm),
1123                                    (neon_mov_imm_LSLH_operand:$Simm))))],
1124                               NoItinerary> {
1125       bit  Simm;
1126       let cmode = {0b1, 0b0, Simm, 0b0};
1127     }
1128
1129     def _8H  : NeonI_1VModImm<0b1, op,
1130                               (outs VPR128:$Rd),
1131                               (ins neon_uimm8:$Imm,
1132                                 neon_mov_imm_LSLH_operand:$Simm),
1133                               !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1134                               [(set (v8i16 VPR128:$Rd),
1135                                  (v8i16 (opnode (timm:$Imm),
1136                                    (neon_mov_imm_LSLH_operand:$Simm))))],
1137                               NoItinerary> {
1138       bit Simm;
1139       let cmode = {0b1, 0b0, Simm, 0b0};
1140      }
1141 }
1142
1143 multiclass NeonI_mov_imm_with_constraint_lsl_sizes<string asmop, bit op,
1144                                                    SDPatternOperator opnode,
1145                                                    SDPatternOperator neonopnode>
1146 {
1147   let Constraints = "$src = $Rd" in {
1148     // shift zeros, per word
1149     def _2S  : NeonI_1VModImm<0b0, op,
1150                  (outs VPR64:$Rd),
1151                  (ins VPR64:$src, neon_uimm8:$Imm,
1152                    neon_mov_imm_LSL_operand:$Simm),
1153                  !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1154                  [(set (v2i32 VPR64:$Rd),
1155                     (v2i32 (opnode (v2i32 VPR64:$src),
1156                       (v2i32 (bitconvert (v2i32 (neonopnode timm:$Imm,
1157                         neon_mov_imm_LSL_operand:$Simm)))))))],
1158                  NoItinerary> {
1159       bits<2> Simm;
1160       let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1161     }
1162
1163     def _4S  : NeonI_1VModImm<0b1, op,
1164                  (outs VPR128:$Rd),
1165                  (ins VPR128:$src, neon_uimm8:$Imm,
1166                    neon_mov_imm_LSL_operand:$Simm),
1167                  !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1168                  [(set (v4i32 VPR128:$Rd),
1169                     (v4i32 (opnode (v4i32 VPR128:$src),
1170                       (v4i32 (bitconvert (v4i32 (neonopnode timm:$Imm,
1171                         neon_mov_imm_LSL_operand:$Simm)))))))],
1172                  NoItinerary> {
1173       bits<2> Simm;
1174       let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1175     }
1176
1177     // shift zeros, per halfword
1178     def _4H  : NeonI_1VModImm<0b0, op,
1179                  (outs VPR64:$Rd),
1180                  (ins VPR64:$src, neon_uimm8:$Imm,
1181                    neon_mov_imm_LSLH_operand:$Simm),
1182                  !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1183                  [(set (v4i16 VPR64:$Rd),
1184                     (v4i16 (opnode (v4i16 VPR64:$src),
1185                        (v4i16 (bitconvert (v4i16 (neonopnode timm:$Imm,
1186                           neon_mov_imm_LSL_operand:$Simm)))))))],
1187                  NoItinerary> {
1188       bit  Simm;
1189       let cmode = {0b1, 0b0, Simm, 0b1};
1190     }
1191
1192     def _8H  : NeonI_1VModImm<0b1, op,
1193                  (outs VPR128:$Rd),
1194                  (ins VPR128:$src, neon_uimm8:$Imm,
1195                    neon_mov_imm_LSLH_operand:$Simm),
1196                  !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1197                  [(set (v8i16 VPR128:$Rd),
1198                     (v8i16 (opnode (v8i16 VPR128:$src),
1199                       (v8i16 (bitconvert (v8i16 (neonopnode timm:$Imm,
1200                         neon_mov_imm_LSL_operand:$Simm)))))))],
1201                  NoItinerary> {
1202       bit Simm;
1203       let cmode = {0b1, 0b0, Simm, 0b1};
1204     }
1205   }
1206 }
1207
1208 multiclass NeonI_mov_imm_msl_sizes<string asmop, bit op,
1209                                    SDPatternOperator opnode>
1210 {
1211     // shift ones, per word
1212     def _2S  : NeonI_1VModImm<0b0, op,
1213                              (outs VPR64:$Rd),
1214                              (ins neon_uimm8:$Imm,
1215                                neon_mov_imm_MSL_operand:$Simm),
1216                              !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1217                               [(set (v2i32 VPR64:$Rd),
1218                                  (v2i32 (opnode (timm:$Imm),
1219                                    (neon_mov_imm_MSL_operand:$Simm))))],
1220                              NoItinerary> {
1221        bit Simm;
1222        let cmode = {0b1, 0b1, 0b0, Simm};
1223      }
1224
1225    def _4S  : NeonI_1VModImm<0b1, op,
1226                               (outs VPR128:$Rd),
1227                               (ins neon_uimm8:$Imm,
1228                                 neon_mov_imm_MSL_operand:$Simm),
1229                               !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1230                               [(set (v4i32 VPR128:$Rd),
1231                                  (v4i32 (opnode (timm:$Imm),
1232                                    (neon_mov_imm_MSL_operand:$Simm))))],
1233                               NoItinerary> {
1234      bit Simm;
1235      let cmode = {0b1, 0b1, 0b0, Simm};
1236    }
1237 }
1238
1239 // Vector Move Immediate Shifted
1240 let isReMaterializable = 1 in {
1241 defm MOVIvi_lsl : NeonI_mov_imm_lsl_sizes<"movi", 0b0, Neon_movi>;
1242 }
1243
1244 // Vector Move Inverted Immediate Shifted
1245 let isReMaterializable = 1 in {
1246 defm MVNIvi_lsl : NeonI_mov_imm_lsl_sizes<"mvni", 0b1, Neon_mvni>;
1247 }
1248
1249 // Vector Bitwise Bit Clear (AND NOT) - immediate
1250 let isReMaterializable = 1 in {
1251 defm BICvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"bic", 0b1,
1252                                                          and, Neon_mvni>;
1253 }
1254
1255 // Vector Bitwise OR - immedidate
1256
1257 let isReMaterializable = 1 in {
1258 defm ORRvi_lsl   : NeonI_mov_imm_with_constraint_lsl_sizes<"orr", 0b0,
1259                                                            or, Neon_movi>;
1260 }
1261
1262 // Additional patterns for Vector Bitwise Bit Clear (AND NOT) - immedidate
1263 // LowerBUILD_VECTOR favors lowering MOVI over MVNI.
1264 // BIC immediate instructions selection requires additional patterns to
1265 // transform Neon_movi operands into BIC immediate operands
1266
1267 def neon_mov_imm_LSLH_transform_XFORM : SDNodeXForm<imm, [{
1268   uint64_t OpCmode = N->getZExtValue();
1269   unsigned ShiftImm;
1270   unsigned ShiftOnesIn;
1271   (void)A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1272   // LSLH restricts shift amount to  0, 8 which are encoded as 0 and 1
1273   // Transform encoded shift amount 0 to 1 and 1 to 0.
1274   return CurDAG->getTargetConstant(!ShiftImm, MVT::i32);
1275 }]>;
1276
1277 def neon_mov_imm_LSLH_transform_operand
1278   : ImmLeaf<i32, [{
1279     unsigned ShiftImm;
1280     unsigned ShiftOnesIn;
1281     unsigned HasShift =
1282       A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1283     return (HasShift && !ShiftOnesIn); }],
1284   neon_mov_imm_LSLH_transform_XFORM>;
1285
1286 // Transform (and A, (4h Neon_movi 0xff)) -> BIC 4h (A, 0x00, LSL 8)
1287 // Transform (and A, (4h Neon_movi 0xff LSL #8)) -> BIC 4h (A, 0x00)
1288 def : Pat<(v4i16 (and VPR64:$src,
1289             (v4i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1290           (BICvi_lsl_4H VPR64:$src, 0,
1291             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1292
1293 // Transform (and A, (8h Neon_movi 8h 0xff)) -> BIC 8h (A, 0x00, LSL 8)
1294 // Transform (and A, (8h Neon_movi 0xff LSL #8)) -> BIC 8h (A, 0x00)
1295 def : Pat<(v8i16 (and VPR128:$src,
1296             (v8i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1297           (BICvi_lsl_8H VPR128:$src, 0,
1298             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1299
1300
1301 multiclass Neon_bitwiseVi_patterns<SDPatternOperator opnode,
1302                                    SDPatternOperator neonopnode,
1303                                    Instruction INST4H,
1304                                    Instruction INST8H> {
1305   def : Pat<(v8i8 (opnode VPR64:$src,
1306                     (bitconvert(v4i16 (neonopnode timm:$Imm,
1307                       neon_mov_imm_LSLH_operand:$Simm))))),
1308             (INST4H VPR64:$src, neon_uimm8:$Imm,
1309               neon_mov_imm_LSLH_operand:$Simm)>;
1310   def : Pat<(v1i64 (opnode VPR64:$src,
1311                   (bitconvert(v4i16 (neonopnode timm:$Imm,
1312                     neon_mov_imm_LSLH_operand:$Simm))))),
1313           (INST4H VPR64:$src, neon_uimm8:$Imm,
1314             neon_mov_imm_LSLH_operand:$Simm)>;
1315
1316   def : Pat<(v16i8 (opnode VPR128:$src,
1317                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1318                      neon_mov_imm_LSLH_operand:$Simm))))),
1319           (INST8H VPR128:$src, neon_uimm8:$Imm,
1320             neon_mov_imm_LSLH_operand:$Simm)>;
1321   def : Pat<(v4i32 (opnode VPR128:$src,
1322                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1323                      neon_mov_imm_LSLH_operand:$Simm))))),
1324           (INST8H VPR128:$src, neon_uimm8:$Imm,
1325             neon_mov_imm_LSLH_operand:$Simm)>;
1326   def : Pat<(v2i64 (opnode VPR128:$src,
1327                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1328                      neon_mov_imm_LSLH_operand:$Simm))))),
1329           (INST8H VPR128:$src, neon_uimm8:$Imm,
1330             neon_mov_imm_LSLH_operand:$Simm)>;
1331 }
1332
1333 // Additional patterns for Vector Vector Bitwise Bit Clear (AND NOT) - immediate
1334 defm : Neon_bitwiseVi_patterns<or, Neon_mvni, BICvi_lsl_4H, BICvi_lsl_8H>;
1335
1336 // Additional patterns for Vector Bitwise OR - immedidate
1337 defm : Neon_bitwiseVi_patterns<or, Neon_movi, ORRvi_lsl_4H, ORRvi_lsl_8H>;
1338
1339
1340 // Vector Move Immediate Masked
1341 let isReMaterializable = 1 in {
1342 defm MOVIvi_msl : NeonI_mov_imm_msl_sizes<"movi", 0b0, Neon_movi>;
1343 }
1344
1345 // Vector Move Inverted Immediate Masked
1346 let isReMaterializable = 1 in {
1347 defm MVNIvi_msl : NeonI_mov_imm_msl_sizes<"mvni", 0b1, Neon_mvni>;
1348 }
1349
1350 class NeonI_mov_imm_lsl_aliases<string asmop, string asmlane,
1351                                 Instruction inst, RegisterOperand VPRC>
1352   : NeonInstAlias<!strconcat(asmop, "\t$Rd," # asmlane # ", $Imm"),
1353                         (inst VPRC:$Rd, neon_uimm8:$Imm,  0), 0b0>;
1354
1355 // Aliases for Vector Move Immediate Shifted
1356 def : NeonI_mov_imm_lsl_aliases<"movi", ".2s", MOVIvi_lsl_2S, VPR64>;
1357 def : NeonI_mov_imm_lsl_aliases<"movi", ".4s", MOVIvi_lsl_4S, VPR128>;
1358 def : NeonI_mov_imm_lsl_aliases<"movi", ".4h", MOVIvi_lsl_4H, VPR64>;
1359 def : NeonI_mov_imm_lsl_aliases<"movi", ".8h", MOVIvi_lsl_8H, VPR128>;
1360
1361 // Aliases for Vector Move Inverted Immediate Shifted
1362 def : NeonI_mov_imm_lsl_aliases<"mvni", ".2s", MVNIvi_lsl_2S, VPR64>;
1363 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4s", MVNIvi_lsl_4S, VPR128>;
1364 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4h", MVNIvi_lsl_4H, VPR64>;
1365 def : NeonI_mov_imm_lsl_aliases<"mvni", ".8h", MVNIvi_lsl_8H, VPR128>;
1366
1367 // Aliases for Vector Bitwise Bit Clear (AND NOT) - immediate
1368 def : NeonI_mov_imm_lsl_aliases<"bic", ".2s", BICvi_lsl_2S, VPR64>;
1369 def : NeonI_mov_imm_lsl_aliases<"bic", ".4s", BICvi_lsl_4S, VPR128>;
1370 def : NeonI_mov_imm_lsl_aliases<"bic", ".4h", BICvi_lsl_4H, VPR64>;
1371 def : NeonI_mov_imm_lsl_aliases<"bic", ".8h", BICvi_lsl_8H, VPR128>;
1372
1373 // Aliases for Vector Bitwise OR - immedidate
1374 def : NeonI_mov_imm_lsl_aliases<"orr", ".2s", ORRvi_lsl_2S, VPR64>;
1375 def : NeonI_mov_imm_lsl_aliases<"orr", ".4s", ORRvi_lsl_4S, VPR128>;
1376 def : NeonI_mov_imm_lsl_aliases<"orr", ".4h", ORRvi_lsl_4H, VPR64>;
1377 def : NeonI_mov_imm_lsl_aliases<"orr", ".8h", ORRvi_lsl_8H, VPR128>;
1378
1379 //  Vector Move Immediate - per byte
1380 let isReMaterializable = 1 in {
1381 def MOVIvi_8B : NeonI_1VModImm<0b0, 0b0,
1382                                (outs VPR64:$Rd), (ins neon_uimm8:$Imm),
1383                                "movi\t$Rd.8b, $Imm",
1384                                [(set (v8i8 VPR64:$Rd),
1385                                   (v8i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1386                                 NoItinerary> {
1387   let cmode = 0b1110;
1388 }
1389
1390 def MOVIvi_16B : NeonI_1VModImm<0b1, 0b0,
1391                                 (outs VPR128:$Rd), (ins neon_uimm8:$Imm),
1392                                 "movi\t$Rd.16b, $Imm",
1393                                 [(set (v16i8 VPR128:$Rd),
1394                                    (v16i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1395                                  NoItinerary> {
1396   let cmode = 0b1110;
1397 }
1398 }
1399
1400 // Vector Move Immediate - bytemask, per double word
1401 let isReMaterializable = 1 in {
1402 def MOVIvi_2D : NeonI_1VModImm<0b1, 0b1,
1403                                (outs VPR128:$Rd), (ins neon_uimm64_mask:$Imm),
1404                                "movi\t $Rd.2d, $Imm",
1405                                [(set (v2i64 VPR128:$Rd),
1406                                   (v2i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1407                                NoItinerary> {
1408   let cmode = 0b1110;
1409 }
1410 }
1411
1412 // Vector Move Immediate - bytemask, one doubleword
1413
1414 let isReMaterializable = 1 in {
1415 def MOVIdi : NeonI_1VModImm<0b0, 0b1,
1416                            (outs FPR64:$Rd), (ins neon_uimm64_mask:$Imm),
1417                            "movi\t $Rd, $Imm",
1418                            [(set (f64 FPR64:$Rd),
1419                               (f64 (bitconvert
1420                                 (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))))],
1421                            NoItinerary> {
1422   let cmode = 0b1110;
1423 }
1424 }
1425
1426 // Vector Floating Point Move Immediate
1427
1428 class NeonI_FMOV_impl<string asmlane, RegisterOperand VPRC, ValueType OpTy,
1429                       Operand immOpType, bit q, bit op>
1430   : NeonI_1VModImm<q, op,
1431                    (outs VPRC:$Rd), (ins immOpType:$Imm),
1432                    "fmov\t$Rd" # asmlane # ", $Imm",
1433                    [(set (OpTy VPRC:$Rd),
1434                       (OpTy (Neon_fmovi (timm:$Imm))))],
1435                    NoItinerary> {
1436      let cmode = 0b1111;
1437    }
1438
1439 let isReMaterializable = 1 in {
1440 def FMOVvi_2S : NeonI_FMOV_impl<".2s", VPR64,  v2f32, fmov32_operand, 0b0, 0b0>;
1441 def FMOVvi_4S : NeonI_FMOV_impl<".4s", VPR128, v4f32, fmov32_operand, 0b1, 0b0>;
1442 def FMOVvi_2D : NeonI_FMOV_impl<".2d", VPR128, v2f64, fmov64_operand, 0b1, 0b1>;
1443 }
1444
1445 // Vector Shift (Immediate)
1446 // Immediate in [0, 63]
1447 def imm0_63 : Operand<i32> {
1448   let ParserMatchClass = uimm6_asmoperand;
1449 }
1450
1451 // Shift Right/Left Immediate - The immh:immb field of these shifts are encoded
1452 // as follows:
1453 //
1454 //    Offset    Encoding
1455 //     8        immh:immb<6:3> = '0001xxx', <imm> is encoded in immh:immb<2:0>
1456 //     16       immh:immb<6:4> = '001xxxx', <imm> is encoded in immh:immb<3:0>
1457 //     32       immh:immb<6:5> = '01xxxxx', <imm> is encoded in immh:immb<4:0>
1458 //     64       immh:immb<6>   = '1xxxxxx', <imm> is encoded in immh:immb<5:0>
1459 //
1460 // The shift right immediate amount, in the range 1 to element bits, is computed
1461 // as Offset - UInt(immh:immb).  The shift left immediate amount, in the range 0
1462 // to element bits - 1, is computed as UInt(immh:immb) - Offset.
1463
1464 class shr_imm_asmoperands<string OFFSET> : AsmOperandClass {
1465   let Name = "ShrImm" # OFFSET;
1466   let RenderMethod = "addImmOperands";
1467   let DiagnosticType = "ShrImm" # OFFSET;
1468 }
1469
1470 class shr_imm<string OFFSET> : Operand<i32> {
1471   let EncoderMethod = "getShiftRightImm" # OFFSET;
1472   let DecoderMethod = "DecodeShiftRightImm" # OFFSET;
1473   let ParserMatchClass =
1474     !cast<AsmOperandClass>("shr_imm" # OFFSET # "_asmoperand");
1475 }
1476
1477 def shr_imm8_asmoperand : shr_imm_asmoperands<"8">;
1478 def shr_imm16_asmoperand : shr_imm_asmoperands<"16">;
1479 def shr_imm32_asmoperand : shr_imm_asmoperands<"32">;
1480 def shr_imm64_asmoperand : shr_imm_asmoperands<"64">;
1481
1482 def shr_imm8 : shr_imm<"8">;
1483 def shr_imm16 : shr_imm<"16">;
1484 def shr_imm32 : shr_imm<"32">;
1485 def shr_imm64 : shr_imm<"64">;
1486
1487 class shl_imm_asmoperands<string OFFSET> : AsmOperandClass {
1488   let Name = "ShlImm" # OFFSET;
1489   let RenderMethod = "addImmOperands";
1490   let DiagnosticType = "ShlImm" # OFFSET;
1491 }
1492
1493 class shl_imm<string OFFSET> : Operand<i32> {
1494   let EncoderMethod = "getShiftLeftImm" # OFFSET;
1495   let DecoderMethod = "DecodeShiftLeftImm" # OFFSET;
1496   let ParserMatchClass =
1497     !cast<AsmOperandClass>("shl_imm" # OFFSET # "_asmoperand");
1498 }
1499
1500 def shl_imm8_asmoperand : shl_imm_asmoperands<"8">;
1501 def shl_imm16_asmoperand : shl_imm_asmoperands<"16">;
1502 def shl_imm32_asmoperand : shl_imm_asmoperands<"32">;
1503 def shl_imm64_asmoperand : shl_imm_asmoperands<"64">;
1504
1505 def shl_imm8 : shl_imm<"8">;
1506 def shl_imm16 : shl_imm<"16">;
1507 def shl_imm32 : shl_imm<"32">;
1508 def shl_imm64 : shl_imm<"64">;
1509
1510 class N2VShift<bit q, bit u, bits<5> opcode, string asmop, string T,
1511                RegisterOperand VPRC, ValueType Ty, Operand ImmTy, SDNode OpNode>
1512   : NeonI_2VShiftImm<q, u, opcode,
1513                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1514                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1515                      [(set (Ty VPRC:$Rd),
1516                         (Ty (OpNode (Ty VPRC:$Rn),
1517                           (Ty (Neon_vdup (i32 imm:$Imm))))))],
1518                      NoItinerary>;
1519
1520 multiclass NeonI_N2VShL<bit u, bits<5> opcode, string asmop> {
1521   // 64-bit vector types.
1522   def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, uimm3, shl> {
1523     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1524   }
1525
1526   def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, uimm4, shl> {
1527     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1528   }
1529
1530   def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, uimm5, shl> {
1531     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1532   }
1533
1534   // 128-bit vector types.
1535   def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, uimm3, shl> {
1536     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1537   }
1538
1539   def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, uimm4, shl> {
1540     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1541   }
1542
1543   def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, uimm5, shl> {
1544     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1545   }
1546
1547   def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, imm0_63, shl> {
1548     let Inst{22} = 0b1;        // immh:immb = 1xxxxxx
1549   }
1550 }
1551
1552 multiclass NeonI_N2VShR<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1553   def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1554                      OpNode> {
1555     let Inst{22-19} = 0b0001;
1556   }
1557
1558   def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1559                      OpNode> {
1560     let Inst{22-20} = 0b001;
1561   }
1562
1563   def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1564                      OpNode> {
1565      let Inst{22-21} = 0b01;
1566   }
1567
1568   def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1569                       OpNode> {
1570                       let Inst{22-19} = 0b0001;
1571                     }
1572
1573   def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1574                      OpNode> {
1575                      let Inst{22-20} = 0b001;
1576                     }
1577
1578   def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1579                      OpNode> {
1580                       let Inst{22-21} = 0b01;
1581                     }
1582
1583   def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1584                      OpNode> {
1585                       let Inst{22} = 0b1;
1586                     }
1587 }
1588
1589 // Shift left
1590 defm SHLvvi : NeonI_N2VShL<0b0, 0b01010, "shl">;
1591
1592 // Shift right
1593 defm SSHRvvi : NeonI_N2VShR<0b0, 0b00000, "sshr", sra>;
1594 defm USHRvvi : NeonI_N2VShR<0b1, 0b00000, "ushr", srl>;
1595
1596 def Neon_High16B : PatFrag<(ops node:$in),
1597                            (extract_subvector (v16i8 node:$in), (iPTR 8))>;
1598 def Neon_High8H  : PatFrag<(ops node:$in),
1599                            (extract_subvector (v8i16 node:$in), (iPTR 4))>;
1600 def Neon_High4S  : PatFrag<(ops node:$in),
1601                            (extract_subvector (v4i32 node:$in), (iPTR 2))>;
1602
1603 def Neon_low8H : PatFrag<(ops node:$in),
1604                          (v4i16 (extract_subvector (v8i16 node:$in),
1605                                                    (iPTR 0)))>;
1606 def Neon_low4S : PatFrag<(ops node:$in),
1607                          (v2i32 (extract_subvector (v4i32 node:$in),
1608                                                    (iPTR 0)))>;
1609 def Neon_low4f : PatFrag<(ops node:$in),
1610                          (v2f32 (extract_subvector (v4f32 node:$in),
1611                                                    (iPTR 0)))>;
1612
1613 class N2VShiftLong<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1614                    string SrcT, ValueType DestTy, ValueType SrcTy,
1615                    Operand ImmTy, SDPatternOperator ExtOp>
1616   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1617                      (ins VPR64:$Rn, ImmTy:$Imm),
1618                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1619                      [(set (DestTy VPR128:$Rd),
1620                         (DestTy (shl
1621                           (DestTy (ExtOp (SrcTy VPR64:$Rn))),
1622                             (DestTy (Neon_vdup (i32 imm:$Imm))))))],
1623                      NoItinerary>;
1624
1625 class N2VShiftLongHigh<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1626                        string SrcT, ValueType DestTy, ValueType SrcTy,
1627                        int StartIndex, Operand ImmTy,
1628                        SDPatternOperator ExtOp, PatFrag getTop>
1629   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1630                      (ins VPR128:$Rn, ImmTy:$Imm),
1631                      asmop # "2\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1632                      [(set (DestTy VPR128:$Rd),
1633                         (DestTy (shl
1634                           (DestTy (ExtOp
1635                             (SrcTy (getTop VPR128:$Rn)))),
1636                               (DestTy (Neon_vdup (i32 imm:$Imm))))))],
1637                      NoItinerary>;
1638
1639 multiclass NeonI_N2VShLL<string prefix, bit u, bits<5> opcode, string asmop,
1640                          SDNode ExtOp> {
1641   // 64-bit vector types.
1642   def _8B : N2VShiftLong<0b0, u, opcode, asmop, "8h", "8b", v8i16, v8i8,
1643                          uimm3, ExtOp> {
1644     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1645   }
1646
1647   def _4H : N2VShiftLong<0b0, u, opcode, asmop, "4s", "4h", v4i32, v4i16,
1648                          uimm4, ExtOp> {
1649     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1650   }
1651
1652   def _2S : N2VShiftLong<0b0, u, opcode, asmop, "2d", "2s", v2i64, v2i32,
1653                          uimm5, ExtOp> {
1654     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1655   }
1656
1657   // 128-bit vector types
1658   def _16B : N2VShiftLongHigh<0b1, u, opcode, asmop, "8h", "16b",
1659                               v8i16, v8i8, 8, uimm3, ExtOp, Neon_High16B> {
1660     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1661   }
1662
1663   def _8H : N2VShiftLongHigh<0b1, u, opcode, asmop, "4s", "8h",
1664                              v4i32, v4i16, 4, uimm4, ExtOp, Neon_High8H> {
1665     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1666   }
1667
1668   def _4S : N2VShiftLongHigh<0b1, u, opcode, asmop, "2d", "4s",
1669                              v2i64, v2i32, 2, uimm5, ExtOp, Neon_High4S> {
1670     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1671   }
1672
1673   // Use other patterns to match when the immediate is 0.
1674   def : Pat<(v8i16 (ExtOp (v8i8 VPR64:$Rn))),
1675             (!cast<Instruction>(prefix # "_8B") VPR64:$Rn, 0)>;
1676
1677   def : Pat<(v4i32 (ExtOp (v4i16 VPR64:$Rn))),
1678             (!cast<Instruction>(prefix # "_4H") VPR64:$Rn, 0)>;
1679
1680   def : Pat<(v2i64 (ExtOp (v2i32 VPR64:$Rn))),
1681             (!cast<Instruction>(prefix # "_2S") VPR64:$Rn, 0)>;
1682
1683   def : Pat<(v8i16 (ExtOp (v8i8 (Neon_High16B VPR128:$Rn)))),
1684             (!cast<Instruction>(prefix # "_16B") VPR128:$Rn, 0)>;
1685
1686   def : Pat<(v4i32 (ExtOp (v4i16 (Neon_High8H VPR128:$Rn)))),
1687             (!cast<Instruction>(prefix # "_8H") VPR128:$Rn, 0)>;
1688
1689   def : Pat<(v2i64 (ExtOp (v2i32 (Neon_High4S VPR128:$Rn)))),
1690             (!cast<Instruction>(prefix # "_4S") VPR128:$Rn, 0)>;
1691 }
1692
1693 // Shift left long
1694 defm SSHLLvvi : NeonI_N2VShLL<"SSHLLvvi", 0b0, 0b10100, "sshll", sext>;
1695 defm USHLLvvi : NeonI_N2VShLL<"USHLLvvi", 0b1, 0b10100, "ushll", zext>;
1696
1697 // Rounding/Saturating shift
1698 class N2VShift_RQ<bit q, bit u, bits<5> opcode, string asmop, string T,
1699                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1700                   SDPatternOperator OpNode>
1701   : NeonI_2VShiftImm<q, u, opcode,
1702                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1703                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1704                      [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$Rn),
1705                         (i32 imm:$Imm))))],
1706                      NoItinerary>;
1707
1708 // shift right (vector by immediate)
1709 multiclass NeonI_N2VShR_RQ<bit u, bits<5> opcode, string asmop,
1710                            SDPatternOperator OpNode> {
1711   def _8B  : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1712                          OpNode> {
1713     let Inst{22-19} = 0b0001;
1714   }
1715
1716   def _4H  : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1717                          OpNode> {
1718     let Inst{22-20} = 0b001;
1719   }
1720
1721   def _2S  : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1722                          OpNode> {
1723     let Inst{22-21} = 0b01;
1724   }
1725
1726   def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1727                          OpNode> {
1728     let Inst{22-19} = 0b0001;
1729   }
1730
1731   def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1732                         OpNode> {
1733     let Inst{22-20} = 0b001;
1734   }
1735
1736   def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1737                         OpNode> {
1738     let Inst{22-21} = 0b01;
1739   }
1740
1741   def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1742                         OpNode> {
1743     let Inst{22} = 0b1;
1744   }
1745 }
1746
1747 multiclass NeonI_N2VShL_Q<bit u, bits<5> opcode, string asmop,
1748                           SDPatternOperator OpNode> {
1749   // 64-bit vector types.
1750   def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, uimm3,
1751                         OpNode> {
1752     let Inst{22-19} = 0b0001;
1753   }
1754
1755   def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, uimm4,
1756                         OpNode> {
1757     let Inst{22-20} = 0b001;
1758   }
1759
1760   def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, uimm5,
1761                         OpNode> {
1762     let Inst{22-21} = 0b01;
1763   }
1764
1765   // 128-bit vector types.
1766   def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, uimm3,
1767                          OpNode> {
1768     let Inst{22-19} = 0b0001;
1769   }
1770
1771   def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, uimm4,
1772                         OpNode> {
1773     let Inst{22-20} = 0b001;
1774   }
1775
1776   def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, uimm5,
1777                         OpNode> {
1778     let Inst{22-21} = 0b01;
1779   }
1780
1781   def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, imm0_63,
1782                         OpNode> {
1783     let Inst{22} = 0b1;
1784   }
1785 }
1786
1787 // Rounding shift right
1788 defm SRSHRvvi : NeonI_N2VShR_RQ<0b0, 0b00100, "srshr",
1789                                 int_aarch64_neon_vsrshr>;
1790 defm URSHRvvi : NeonI_N2VShR_RQ<0b1, 0b00100, "urshr",
1791                                 int_aarch64_neon_vurshr>;
1792
1793 // Saturating shift left unsigned
1794 defm SQSHLUvvi : NeonI_N2VShL_Q<0b1, 0b01100, "sqshlu", int_aarch64_neon_vsqshlu>;
1795
1796 // Saturating shift left
1797 defm SQSHLvvi : NeonI_N2VShL_Q<0b0, 0b01110, "sqshl", Neon_sqrshlImm>;
1798 defm UQSHLvvi : NeonI_N2VShL_Q<0b1, 0b01110, "uqshl", Neon_uqrshlImm>;
1799
1800 class N2VShiftAdd<bit q, bit u, bits<5> opcode, string asmop, string T,
1801                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1802                   SDNode OpNode>
1803   : NeonI_2VShiftImm<q, u, opcode,
1804            (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1805            asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1806            [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1807               (Ty (OpNode (Ty VPRC:$Rn),
1808                 (Ty (Neon_vdup (i32 imm:$Imm))))))))],
1809            NoItinerary> {
1810   let Constraints = "$src = $Rd";
1811 }
1812
1813 // Shift Right accumulate
1814 multiclass NeonI_N2VShRAdd<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1815   def _8B : N2VShiftAdd<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1816                         OpNode> {
1817     let Inst{22-19} = 0b0001;
1818   }
1819
1820   def _4H : N2VShiftAdd<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1821                         OpNode> {
1822     let Inst{22-20} = 0b001;
1823   }
1824
1825   def _2S : N2VShiftAdd<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1826                         OpNode> {
1827     let Inst{22-21} = 0b01;
1828   }
1829
1830   def _16B : N2VShiftAdd<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1831                          OpNode> {
1832     let Inst{22-19} = 0b0001;
1833   }
1834
1835   def _8H : N2VShiftAdd<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1836                         OpNode> {
1837     let Inst{22-20} = 0b001;
1838   }
1839
1840   def _4S : N2VShiftAdd<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1841                         OpNode> {
1842     let Inst{22-21} = 0b01;
1843   }
1844
1845   def _2D : N2VShiftAdd<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1846                         OpNode> {
1847     let Inst{22} = 0b1;
1848   }
1849 }
1850
1851 // Shift right and accumulate
1852 defm SSRAvvi    : NeonI_N2VShRAdd<0, 0b00010, "ssra", sra>;
1853 defm USRAvvi    : NeonI_N2VShRAdd<1, 0b00010, "usra", srl>;
1854
1855 // Rounding shift accumulate
1856 class N2VShiftAdd_R<bit q, bit u, bits<5> opcode, string asmop, string T,
1857                     RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1858                     SDPatternOperator OpNode>
1859   : NeonI_2VShiftImm<q, u, opcode,
1860                      (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1861                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1862                      [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1863                         (Ty (OpNode (Ty VPRC:$Rn), (i32 imm:$Imm))))))],
1864                      NoItinerary> {
1865   let Constraints = "$src = $Rd";
1866 }
1867
1868 multiclass NeonI_N2VShRAdd_R<bit u, bits<5> opcode, string asmop,
1869                              SDPatternOperator OpNode> {
1870   def _8B : N2VShiftAdd_R<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1871                           OpNode> {
1872     let Inst{22-19} = 0b0001;
1873   }
1874
1875   def _4H : N2VShiftAdd_R<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1876                           OpNode> {
1877     let Inst{22-20} = 0b001;
1878   }
1879
1880   def _2S : N2VShiftAdd_R<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1881                           OpNode> {
1882     let Inst{22-21} = 0b01;
1883   }
1884
1885   def _16B : N2VShiftAdd_R<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1886                            OpNode> {
1887     let Inst{22-19} = 0b0001;
1888   }
1889
1890   def _8H : N2VShiftAdd_R<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1891                           OpNode> {
1892     let Inst{22-20} = 0b001;
1893   }
1894
1895   def _4S : N2VShiftAdd_R<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1896                           OpNode> {
1897     let Inst{22-21} = 0b01;
1898   }
1899
1900   def _2D : N2VShiftAdd_R<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1901                           OpNode> {
1902     let Inst{22} = 0b1;
1903   }
1904 }
1905
1906 // Rounding shift right and accumulate
1907 defm SRSRAvvi : NeonI_N2VShRAdd_R<0, 0b00110, "srsra", int_aarch64_neon_vsrshr>;
1908 defm URSRAvvi : NeonI_N2VShRAdd_R<1, 0b00110, "ursra", int_aarch64_neon_vurshr>;
1909
1910 // Shift insert by immediate
1911 class N2VShiftIns<bit q, bit u, bits<5> opcode, string asmop, string T,
1912                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1913                   SDPatternOperator OpNode>
1914     : NeonI_2VShiftImm<q, u, opcode,
1915            (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1916            asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1917            [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$src), (Ty VPRC:$Rn),
1918              (i32 imm:$Imm))))],
1919            NoItinerary> {
1920   let Constraints = "$src = $Rd";
1921 }
1922
1923 // shift left insert (vector by immediate)
1924 multiclass NeonI_N2VShLIns<bit u, bits<5> opcode, string asmop> {
1925   def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, uimm3,
1926                         int_aarch64_neon_vsli> {
1927     let Inst{22-19} = 0b0001;
1928   }
1929
1930   def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, uimm4,
1931                         int_aarch64_neon_vsli> {
1932     let Inst{22-20} = 0b001;
1933   }
1934
1935   def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, uimm5,
1936                         int_aarch64_neon_vsli> {
1937     let Inst{22-21} = 0b01;
1938   }
1939
1940     // 128-bit vector types
1941   def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, uimm3,
1942                          int_aarch64_neon_vsli> {
1943     let Inst{22-19} = 0b0001;
1944   }
1945
1946   def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, uimm4,
1947                         int_aarch64_neon_vsli> {
1948     let Inst{22-20} = 0b001;
1949   }
1950
1951   def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, uimm5,
1952                         int_aarch64_neon_vsli> {
1953     let Inst{22-21} = 0b01;
1954   }
1955
1956   def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, imm0_63,
1957                         int_aarch64_neon_vsli> {
1958     let Inst{22} = 0b1;
1959   }
1960 }
1961
1962 // shift right insert (vector by immediate)
1963 multiclass NeonI_N2VShRIns<bit u, bits<5> opcode, string asmop> {
1964     // 64-bit vector types.
1965   def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1966                         int_aarch64_neon_vsri> {
1967     let Inst{22-19} = 0b0001;
1968   }
1969
1970   def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1971                         int_aarch64_neon_vsri> {
1972     let Inst{22-20} = 0b001;
1973   }
1974
1975   def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1976                         int_aarch64_neon_vsri> {
1977     let Inst{22-21} = 0b01;
1978   }
1979
1980     // 128-bit vector types
1981   def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1982                          int_aarch64_neon_vsri> {
1983     let Inst{22-19} = 0b0001;
1984   }
1985
1986   def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1987                         int_aarch64_neon_vsri> {
1988     let Inst{22-20} = 0b001;
1989   }
1990
1991   def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1992                         int_aarch64_neon_vsri> {
1993     let Inst{22-21} = 0b01;
1994   }
1995
1996   def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1997                         int_aarch64_neon_vsri> {
1998     let Inst{22} = 0b1;
1999   }
2000 }
2001
2002 // Shift left and insert
2003 defm SLIvvi   : NeonI_N2VShLIns<0b1, 0b01010, "sli">;
2004
2005 // Shift right and insert
2006 defm SRIvvi   : NeonI_N2VShRIns<0b1, 0b01000, "sri">;
2007
2008 class N2VShR_Narrow<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2009                     string SrcT, Operand ImmTy>
2010   : NeonI_2VShiftImm<q, u, opcode,
2011                      (outs VPR64:$Rd), (ins VPR128:$Rn, ImmTy:$Imm),
2012                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2013                      [], NoItinerary>;
2014
2015 class N2VShR_Narrow_Hi<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2016                        string SrcT, Operand ImmTy>
2017   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
2018                      (ins VPR128:$src, VPR128:$Rn, ImmTy:$Imm),
2019                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2020                      [], NoItinerary> {
2021   let Constraints = "$src = $Rd";
2022 }
2023
2024 // left long shift by immediate
2025 multiclass NeonI_N2VShR_Narrow<bit u, bits<5> opcode, string asmop> {
2026   def _8B : N2VShR_Narrow<0b0, u, opcode, asmop, "8b", "8h", shr_imm8> {
2027     let Inst{22-19} = 0b0001;
2028   }
2029
2030   def _4H : N2VShR_Narrow<0b0, u, opcode, asmop, "4h", "4s", shr_imm16> {
2031     let Inst{22-20} = 0b001;
2032   }
2033
2034   def _2S : N2VShR_Narrow<0b0, u, opcode, asmop, "2s", "2d", shr_imm32> {
2035     let Inst{22-21} = 0b01;
2036   }
2037
2038   // Shift Narrow High
2039   def _16B : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "16b", "8h",
2040                               shr_imm8> {
2041     let Inst{22-19} = 0b0001;
2042   }
2043
2044   def _8H : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "8h", "4s",
2045                              shr_imm16> {
2046     let Inst{22-20} = 0b001;
2047   }
2048
2049   def _4S : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "4s", "2d",
2050                              shr_imm32> {
2051     let Inst{22-21} = 0b01;
2052   }
2053 }
2054
2055 // Shift right narrow
2056 defm SHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10000, "shrn">;
2057
2058 // Shift right narrow (prefix Q is saturating, prefix R is rounding)
2059 defm QSHRUNvvi :NeonI_N2VShR_Narrow<0b1, 0b10000, "sqshrun">;
2060 defm RSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10001, "rshrn">;
2061 defm QRSHRUNvvi : NeonI_N2VShR_Narrow<0b1, 0b10001, "sqrshrun">;
2062 defm SQSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10010, "sqshrn">;
2063 defm UQSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10010, "uqshrn">;
2064 defm SQRSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10011, "sqrshrn">;
2065 defm UQRSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10011, "uqrshrn">;
2066
2067 def Neon_combine_2D : PatFrag<(ops node:$Rm, node:$Rn),
2068                               (v2i64 (concat_vectors (v1i64 node:$Rm),
2069                                                      (v1i64 node:$Rn)))>;
2070 def Neon_combine_8H : PatFrag<(ops node:$Rm, node:$Rn),
2071                               (v8i16 (concat_vectors (v4i16 node:$Rm),
2072                                                      (v4i16 node:$Rn)))>;
2073 def Neon_combine_4S : PatFrag<(ops node:$Rm, node:$Rn),
2074                               (v4i32 (concat_vectors (v2i32 node:$Rm),
2075                                                      (v2i32 node:$Rn)))>;
2076 def Neon_combine_4f : PatFrag<(ops node:$Rm, node:$Rn),
2077                               (v4f32 (concat_vectors (v2f32 node:$Rm),
2078                                                      (v2f32 node:$Rn)))>;
2079 def Neon_combine_2d : PatFrag<(ops node:$Rm, node:$Rn),
2080                               (v2f64 (concat_vectors (v1f64 node:$Rm),
2081                                                      (v1f64 node:$Rn)))>;
2082
2083 def Neon_lshrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2084                              (v8i16 (srl (v8i16 node:$lhs),
2085                                (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2086 def Neon_lshrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2087                              (v4i32 (srl (v4i32 node:$lhs),
2088                                (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2089 def Neon_lshrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2090                              (v2i64 (srl (v2i64 node:$lhs),
2091                                (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2092 def Neon_ashrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2093                              (v8i16 (sra (v8i16 node:$lhs),
2094                                (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2095 def Neon_ashrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2096                              (v4i32 (sra (v4i32 node:$lhs),
2097                                (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2098 def Neon_ashrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2099                              (v2i64 (sra (v2i64 node:$lhs),
2100                                (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2101
2102 // Normal shift right narrow is matched by IR (srl/sra, trunc, concat_vectors)
2103 multiclass Neon_shiftNarrow_patterns<string shr> {
2104   def : Pat<(v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H") VPR128:$Rn,
2105               (i32 imm:$Imm)))),
2106             (SHRNvvi_8B VPR128:$Rn, imm:$Imm)>;
2107   def : Pat<(v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S") VPR128:$Rn,
2108               (i32 imm:$Imm)))),
2109             (SHRNvvi_4H VPR128:$Rn, imm:$Imm)>;
2110   def : Pat<(v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D") VPR128:$Rn,
2111               (i32 imm:$Imm)))),
2112             (SHRNvvi_2S VPR128:$Rn, imm:$Imm)>;
2113
2114   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2115               (v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H")
2116                 VPR128:$Rn, (i32 imm:$Imm))))))),
2117             (SHRNvvi_16B (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
2118                          VPR128:$Rn, imm:$Imm)>;
2119   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2120               (v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S")
2121                 VPR128:$Rn, (i32 imm:$Imm))))))),
2122             (SHRNvvi_8H (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2123                         VPR128:$Rn, imm:$Imm)>;
2124   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2125               (v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D")
2126                 VPR128:$Rn, (i32 imm:$Imm))))))),
2127             (SHRNvvi_4S (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2128                         VPR128:$Rn, imm:$Imm)>;
2129 }
2130
2131 multiclass Neon_shiftNarrow_QR_patterns<SDPatternOperator op, string prefix> {
2132   def : Pat<(v8i8 (op (v8i16 VPR128:$Rn), imm:$Imm)),
2133             (!cast<Instruction>(prefix # "_8B") VPR128:$Rn, imm:$Imm)>;
2134   def : Pat<(v4i16 (op (v4i32 VPR128:$Rn), imm:$Imm)),
2135             (!cast<Instruction>(prefix # "_4H") VPR128:$Rn, imm:$Imm)>;
2136   def : Pat<(v2i32 (op (v2i64 VPR128:$Rn), imm:$Imm)),
2137             (!cast<Instruction>(prefix # "_2S") VPR128:$Rn, imm:$Imm)>;
2138
2139   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2140                 (v1i64 (bitconvert (v8i8 (op (v8i16 VPR128:$Rn), imm:$Imm))))),
2141             (!cast<Instruction>(prefix # "_16B")
2142                 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2143                 VPR128:$Rn, imm:$Imm)>;
2144   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2145                 (v1i64 (bitconvert (v4i16 (op (v4i32 VPR128:$Rn), imm:$Imm))))),
2146             (!cast<Instruction>(prefix # "_8H")
2147                 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2148                 VPR128:$Rn, imm:$Imm)>;
2149   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2150                 (v1i64 (bitconvert (v2i32 (op (v2i64 VPR128:$Rn), imm:$Imm))))),
2151             (!cast<Instruction>(prefix # "_4S")
2152                   (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2153                   VPR128:$Rn, imm:$Imm)>;
2154 }
2155
2156 defm : Neon_shiftNarrow_patterns<"lshr">;
2157 defm : Neon_shiftNarrow_patterns<"ashr">;
2158
2159 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrun, "QSHRUNvvi">;
2160 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vrshrn, "RSHRNvvi">;
2161 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrun, "QRSHRUNvvi">;
2162 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrn, "SQSHRNvvi">;
2163 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqshrn, "UQSHRNvvi">;
2164 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrn, "SQRSHRNvvi">;
2165 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqrshrn, "UQRSHRNvvi">;
2166
2167 // Convert fix-point and float-pointing
2168 class N2VCvt_Fx<bit q, bit u, bits<5> opcode, string asmop, string T,
2169                 RegisterOperand VPRC, ValueType DestTy, ValueType SrcTy,
2170                 Operand ImmTy, SDPatternOperator IntOp>
2171   : NeonI_2VShiftImm<q, u, opcode,
2172                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
2173                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2174                      [(set (DestTy VPRC:$Rd), (DestTy (IntOp (SrcTy VPRC:$Rn),
2175                        (i32 imm:$Imm))))],
2176                      NoItinerary>;
2177
2178 multiclass NeonI_N2VCvt_Fx2fp<bit u, bits<5> opcode, string asmop,
2179                               SDPatternOperator IntOp> {
2180   def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2f32, v2i32,
2181                       shr_imm32, IntOp> {
2182     let Inst{22-21} = 0b01;
2183   }
2184
2185   def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4f32, v4i32,
2186                       shr_imm32, IntOp> {
2187     let Inst{22-21} = 0b01;
2188   }
2189
2190   def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2f64, v2i64,
2191                       shr_imm64, IntOp> {
2192     let Inst{22} = 0b1;
2193   }
2194 }
2195
2196 multiclass NeonI_N2VCvt_Fp2fx<bit u, bits<5> opcode, string asmop,
2197                               SDPatternOperator IntOp> {
2198   def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2i32, v2f32,
2199                       shr_imm32, IntOp> {
2200     let Inst{22-21} = 0b01;
2201   }
2202
2203   def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4i32, v4f32,
2204                       shr_imm32, IntOp> {
2205     let Inst{22-21} = 0b01;
2206   }
2207
2208   def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2i64, v2f64,
2209                       shr_imm64, IntOp> {
2210     let Inst{22} = 0b1;
2211   }
2212 }
2213
2214 // Convert fixed-point to floating-point
2215 defm VCVTxs2f : NeonI_N2VCvt_Fx2fp<0, 0b11100, "scvtf",
2216                                    int_arm_neon_vcvtfxs2fp>;
2217 defm VCVTxu2f : NeonI_N2VCvt_Fx2fp<1, 0b11100, "ucvtf",
2218                                    int_arm_neon_vcvtfxu2fp>;
2219
2220 // Convert floating-point to fixed-point
2221 defm VCVTf2xs : NeonI_N2VCvt_Fp2fx<0, 0b11111, "fcvtzs",
2222                                    int_arm_neon_vcvtfp2fxs>;
2223 defm VCVTf2xu : NeonI_N2VCvt_Fp2fx<1, 0b11111, "fcvtzu",
2224                                    int_arm_neon_vcvtfp2fxu>;
2225
2226 multiclass Neon_sshll2_0<SDNode ext>
2227 {
2228   def _v8i8  : PatFrag<(ops node:$Rn),
2229                        (v8i16 (ext (v8i8 (Neon_High16B node:$Rn))))>;
2230   def _v4i16 : PatFrag<(ops node:$Rn),
2231                        (v4i32 (ext (v4i16 (Neon_High8H node:$Rn))))>;
2232   def _v2i32 : PatFrag<(ops node:$Rn),
2233                        (v2i64 (ext (v2i32 (Neon_High4S node:$Rn))))>;
2234 }
2235
2236 defm NI_sext_high : Neon_sshll2_0<sext>;
2237 defm NI_zext_high : Neon_sshll2_0<zext>;
2238
2239
2240 //===----------------------------------------------------------------------===//
2241 // Multiclasses for NeonI_Across
2242 //===----------------------------------------------------------------------===//
2243
2244 // Variant 1
2245
2246 multiclass NeonI_2VAcross_1<bit u, bits<5> opcode,
2247                             string asmop, SDPatternOperator opnode>
2248 {
2249     def _1h8b:  NeonI_2VAcross<0b0, u, 0b00, opcode,
2250                 (outs FPR16:$Rd), (ins VPR64:$Rn),
2251                 asmop # "\t$Rd, $Rn.8b",
2252                 [(set (v1i16 FPR16:$Rd),
2253                     (v1i16 (opnode (v8i8 VPR64:$Rn))))],
2254                 NoItinerary>;
2255
2256     def _1h16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2257                 (outs FPR16:$Rd), (ins VPR128:$Rn),
2258                 asmop # "\t$Rd, $Rn.16b",
2259                 [(set (v1i16 FPR16:$Rd),
2260                     (v1i16 (opnode (v16i8 VPR128:$Rn))))],
2261                 NoItinerary>;
2262
2263     def _1s4h:  NeonI_2VAcross<0b0, u, 0b01, opcode,
2264                 (outs FPR32:$Rd), (ins VPR64:$Rn),
2265                 asmop # "\t$Rd, $Rn.4h",
2266                 [(set (v1i32 FPR32:$Rd),
2267                     (v1i32 (opnode (v4i16 VPR64:$Rn))))],
2268                 NoItinerary>;
2269
2270     def _1s8h:  NeonI_2VAcross<0b1, u, 0b01, opcode,
2271                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2272                 asmop # "\t$Rd, $Rn.8h",
2273                 [(set (v1i32 FPR32:$Rd),
2274                     (v1i32 (opnode (v8i16 VPR128:$Rn))))],
2275                 NoItinerary>;
2276
2277     // _1d2s doesn't exist!
2278
2279     def _1d4s:  NeonI_2VAcross<0b1, u, 0b10, opcode,
2280                 (outs FPR64:$Rd), (ins VPR128:$Rn),
2281                 asmop # "\t$Rd, $Rn.4s",
2282                 [(set (v1i64 FPR64:$Rd),
2283                     (v1i64 (opnode (v4i32 VPR128:$Rn))))],
2284                 NoItinerary>;
2285 }
2286
2287 defm SADDLV : NeonI_2VAcross_1<0b0, 0b00011, "saddlv", int_aarch64_neon_saddlv>;
2288 defm UADDLV : NeonI_2VAcross_1<0b1, 0b00011, "uaddlv", int_aarch64_neon_uaddlv>;
2289
2290 // Variant 2
2291
2292 multiclass NeonI_2VAcross_2<bit u, bits<5> opcode,
2293                             string asmop, SDPatternOperator opnode>
2294 {
2295     def _1b8b:  NeonI_2VAcross<0b0, u, 0b00, opcode,
2296                 (outs FPR8:$Rd), (ins VPR64:$Rn),
2297                 asmop # "\t$Rd, $Rn.8b",
2298                 [(set (v1i8 FPR8:$Rd),
2299                     (v1i8 (opnode (v8i8 VPR64:$Rn))))],
2300                 NoItinerary>;
2301
2302     def _1b16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2303                 (outs FPR8:$Rd), (ins VPR128:$Rn),
2304                 asmop # "\t$Rd, $Rn.16b",
2305                 [(set (v1i8 FPR8:$Rd),
2306                     (v1i8 (opnode (v16i8 VPR128:$Rn))))],
2307                 NoItinerary>;
2308
2309     def _1h4h:  NeonI_2VAcross<0b0, u, 0b01, opcode,
2310                 (outs FPR16:$Rd), (ins VPR64:$Rn),
2311                 asmop # "\t$Rd, $Rn.4h",
2312                 [(set (v1i16 FPR16:$Rd),
2313                     (v1i16 (opnode (v4i16 VPR64:$Rn))))],
2314                 NoItinerary>;
2315
2316     def _1h8h:  NeonI_2VAcross<0b1, u, 0b01, opcode,
2317                 (outs FPR16:$Rd), (ins VPR128:$Rn),
2318                 asmop # "\t$Rd, $Rn.8h",
2319                 [(set (v1i16 FPR16:$Rd),
2320                     (v1i16 (opnode (v8i16 VPR128:$Rn))))],
2321                 NoItinerary>;
2322
2323     // _1s2s doesn't exist!
2324
2325     def _1s4s:  NeonI_2VAcross<0b1, u, 0b10, opcode,
2326                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2327                 asmop # "\t$Rd, $Rn.4s",
2328                 [(set (v1i32 FPR32:$Rd),
2329                     (v1i32 (opnode (v4i32 VPR128:$Rn))))],
2330                 NoItinerary>;
2331 }
2332
2333 defm SMAXV : NeonI_2VAcross_2<0b0, 0b01010, "smaxv", int_aarch64_neon_smaxv>;
2334 defm UMAXV : NeonI_2VAcross_2<0b1, 0b01010, "umaxv", int_aarch64_neon_umaxv>;
2335
2336 defm SMINV : NeonI_2VAcross_2<0b0, 0b11010, "sminv", int_aarch64_neon_sminv>;
2337 defm UMINV : NeonI_2VAcross_2<0b1, 0b11010, "uminv", int_aarch64_neon_uminv>;
2338
2339 defm ADDV : NeonI_2VAcross_2<0b0, 0b11011, "addv", int_aarch64_neon_vaddv>;
2340
2341 // Variant 3
2342
2343 multiclass NeonI_2VAcross_3<bit u, bits<5> opcode, bits<2> size,
2344                             string asmop, SDPatternOperator opnode> {
2345     def _1s4s:  NeonI_2VAcross<0b1, u, size, opcode,
2346                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2347                 asmop # "\t$Rd, $Rn.4s",
2348                 [(set (v1f32 FPR32:$Rd),
2349                     (v1f32 (opnode (v4f32 VPR128:$Rn))))],
2350                 NoItinerary>;
2351 }
2352
2353 defm FMAXNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b00, "fmaxnmv",
2354                                 int_aarch64_neon_vmaxnmv>;
2355 defm FMINNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b10, "fminnmv",
2356                                 int_aarch64_neon_vminnmv>;
2357
2358 defm FMAXV : NeonI_2VAcross_3<0b1, 0b01111, 0b00, "fmaxv",
2359                               int_aarch64_neon_vmaxv>;
2360 defm FMINV : NeonI_2VAcross_3<0b1, 0b01111, 0b10, "fminv",
2361                               int_aarch64_neon_vminv>;
2362
2363 // The followings are for instruction class (3V Diff)
2364
2365 // normal long/long2 pattern
2366 class NeonI_3VDL<bit q, bit u, bits<2> size, bits<4> opcode,
2367                  string asmop, string ResS, string OpS,
2368                  SDPatternOperator opnode, SDPatternOperator ext,
2369                  RegisterOperand OpVPR,
2370                  ValueType ResTy, ValueType OpTy>
2371   : NeonI_3VDiff<q, u, size, opcode,
2372                  (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2373                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2374                  [(set (ResTy VPR128:$Rd),
2375                     (ResTy (opnode (ResTy (ext (OpTy OpVPR:$Rn))),
2376                                    (ResTy (ext (OpTy OpVPR:$Rm))))))],
2377                  NoItinerary>;
2378
2379 multiclass NeonI_3VDL_s<bit u, bits<4> opcode,
2380                         string asmop, SDPatternOperator opnode,
2381                         bit Commutable = 0> {
2382   let isCommutable = Commutable in {
2383     def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2384                            opnode, sext, VPR64, v8i16, v8i8>;
2385     def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2386                            opnode, sext, VPR64, v4i32, v4i16>;
2387     def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2388                            opnode, sext, VPR64, v2i64, v2i32>;
2389   }
2390 }
2391
2392 multiclass NeonI_3VDL2_s<bit u, bits<4> opcode, string asmop,
2393                          SDPatternOperator opnode, bit Commutable = 0> {
2394   let isCommutable = Commutable in {
2395     def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2396                             opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2397     def _4s8h  : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2398                             opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2399     def _2d4s  : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2400                             opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2401   }
2402 }
2403
2404 multiclass NeonI_3VDL_u<bit u, bits<4> opcode, string asmop,
2405                         SDPatternOperator opnode, bit Commutable = 0> {
2406   let isCommutable = Commutable in {
2407     def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2408                            opnode, zext, VPR64, v8i16, v8i8>;
2409     def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2410                            opnode, zext, VPR64, v4i32, v4i16>;
2411     def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2412                            opnode, zext, VPR64, v2i64, v2i32>;
2413   }
2414 }
2415
2416 multiclass NeonI_3VDL2_u<bit u, bits<4> opcode, string asmop,
2417                          SDPatternOperator opnode, bit Commutable = 0> {
2418   let isCommutable = Commutable in {
2419     def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2420                             opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2421     def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2422                            opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2423     def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2424                            opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2425   }
2426 }
2427
2428 defm SADDLvvv :  NeonI_3VDL_s<0b0, 0b0000, "saddl", add, 1>;
2429 defm UADDLvvv :  NeonI_3VDL_u<0b1, 0b0000, "uaddl", add, 1>;
2430
2431 defm SADDL2vvv :  NeonI_3VDL2_s<0b0, 0b0000, "saddl2", add, 1>;
2432 defm UADDL2vvv :  NeonI_3VDL2_u<0b1, 0b0000, "uaddl2", add, 1>;
2433
2434 defm SSUBLvvv :  NeonI_3VDL_s<0b0, 0b0010, "ssubl", sub, 0>;
2435 defm USUBLvvv :  NeonI_3VDL_u<0b1, 0b0010, "usubl", sub, 0>;
2436
2437 defm SSUBL2vvv :  NeonI_3VDL2_s<0b0, 0b0010, "ssubl2", sub, 0>;
2438 defm USUBL2vvv :  NeonI_3VDL2_u<0b1, 0b0010, "usubl2", sub, 0>;
2439
2440 // normal wide/wide2 pattern
2441 class NeonI_3VDW<bit q, bit u, bits<2> size, bits<4> opcode,
2442                  string asmop, string ResS, string OpS,
2443                  SDPatternOperator opnode, SDPatternOperator ext,
2444                  RegisterOperand OpVPR,
2445                  ValueType ResTy, ValueType OpTy>
2446   : NeonI_3VDiff<q, u, size, opcode,
2447                  (outs VPR128:$Rd), (ins VPR128:$Rn, OpVPR:$Rm),
2448                  asmop # "\t$Rd." # ResS # ", $Rn." # ResS # ", $Rm." # OpS,
2449                  [(set (ResTy VPR128:$Rd),
2450                     (ResTy (opnode (ResTy VPR128:$Rn),
2451                                    (ResTy (ext (OpTy OpVPR:$Rm))))))],
2452                  NoItinerary>;
2453
2454 multiclass NeonI_3VDW_s<bit u, bits<4> opcode, string asmop,
2455                         SDPatternOperator opnode> {
2456   def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2457                          opnode, sext, VPR64, v8i16, v8i8>;
2458   def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2459                          opnode, sext, VPR64, v4i32, v4i16>;
2460   def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2461                          opnode, sext, VPR64, v2i64, v2i32>;
2462 }
2463
2464 defm SADDWvvv :  NeonI_3VDW_s<0b0, 0b0001, "saddw", add>;
2465 defm SSUBWvvv :  NeonI_3VDW_s<0b0, 0b0011, "ssubw", sub>;
2466
2467 multiclass NeonI_3VDW2_s<bit u, bits<4> opcode, string asmop,
2468                          SDPatternOperator opnode> {
2469   def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2470                           opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2471   def _4s8h  : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2472                           opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2473   def _2d4s  : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2474                           opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2475 }
2476
2477 defm SADDW2vvv :  NeonI_3VDW2_s<0b0, 0b0001, "saddw2", add>;
2478 defm SSUBW2vvv :  NeonI_3VDW2_s<0b0, 0b0011, "ssubw2", sub>;
2479
2480 multiclass NeonI_3VDW_u<bit u, bits<4> opcode, string asmop,
2481                         SDPatternOperator opnode> {
2482   def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2483                          opnode, zext, VPR64, v8i16, v8i8>;
2484   def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2485                          opnode, zext, VPR64, v4i32, v4i16>;
2486   def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2487                          opnode, zext, VPR64, v2i64, v2i32>;
2488 }
2489
2490 defm UADDWvvv :  NeonI_3VDW_u<0b1, 0b0001, "uaddw", add>;
2491 defm USUBWvvv :  NeonI_3VDW_u<0b1, 0b0011, "usubw", sub>;
2492
2493 multiclass NeonI_3VDW2_u<bit u, bits<4> opcode, string asmop,
2494                          SDPatternOperator opnode> {
2495   def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2496                           opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2497   def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2498                          opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2499   def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2500                          opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2501 }
2502
2503 defm UADDW2vvv :  NeonI_3VDW2_u<0b1, 0b0001, "uaddw2", add>;
2504 defm USUBW2vvv :  NeonI_3VDW2_u<0b1, 0b0011, "usubw2", sub>;
2505
2506 // Get the high half part of the vector element.
2507 multiclass NeonI_get_high {
2508   def _8h : PatFrag<(ops node:$Rn),
2509                     (v8i8 (trunc (v8i16 (srl (v8i16 node:$Rn),
2510                                              (v8i16 (Neon_vdup (i32 8)))))))>;
2511   def _4s : PatFrag<(ops node:$Rn),
2512                     (v4i16 (trunc (v4i32 (srl (v4i32 node:$Rn),
2513                                               (v4i32 (Neon_vdup (i32 16)))))))>;
2514   def _2d : PatFrag<(ops node:$Rn),
2515                     (v2i32 (trunc (v2i64 (srl (v2i64 node:$Rn),
2516                                               (v2i64 (Neon_vdup (i32 32)))))))>;
2517 }
2518
2519 defm NI_get_hi : NeonI_get_high;
2520
2521 // pattern for addhn/subhn with 2 operands
2522 class NeonI_3VDN_addhn_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2523                            string asmop, string ResS, string OpS,
2524                            SDPatternOperator opnode, SDPatternOperator get_hi,
2525                            ValueType ResTy, ValueType OpTy>
2526   : NeonI_3VDiff<q, u, size, opcode,
2527                  (outs VPR64:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2528                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2529                  [(set (ResTy VPR64:$Rd),
2530                     (ResTy (get_hi
2531                       (OpTy (opnode (OpTy VPR128:$Rn),
2532                                     (OpTy VPR128:$Rm))))))],
2533                  NoItinerary>;
2534
2535 multiclass NeonI_3VDN_addhn_2Op<bit u, bits<4> opcode, string asmop,
2536                                 SDPatternOperator opnode, bit Commutable = 0> {
2537   let isCommutable = Commutable in {
2538     def _8b8h : NeonI_3VDN_addhn_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2539                                      opnode, NI_get_hi_8h, v8i8, v8i16>;
2540     def _4h4s : NeonI_3VDN_addhn_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2541                                      opnode, NI_get_hi_4s, v4i16, v4i32>;
2542     def _2s2d : NeonI_3VDN_addhn_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2543                                      opnode, NI_get_hi_2d, v2i32, v2i64>;
2544   }
2545 }
2546
2547 defm ADDHNvvv  : NeonI_3VDN_addhn_2Op<0b0, 0b0100, "addhn", add, 1>;
2548 defm SUBHNvvv  : NeonI_3VDN_addhn_2Op<0b0, 0b0110, "subhn", sub, 0>;
2549
2550 // pattern for operation with 2 operands
2551 class NeonI_3VD_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2552                     string asmop, string ResS, string OpS,
2553                     SDPatternOperator opnode,
2554                     RegisterOperand ResVPR, RegisterOperand OpVPR,
2555                     ValueType ResTy, ValueType OpTy>
2556   : NeonI_3VDiff<q, u, size, opcode,
2557                  (outs ResVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2558                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2559                  [(set (ResTy ResVPR:$Rd),
2560                     (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))],
2561                  NoItinerary>;
2562
2563 // normal narrow pattern
2564 multiclass NeonI_3VDN_2Op<bit u, bits<4> opcode, string asmop,
2565                           SDPatternOperator opnode, bit Commutable = 0> {
2566   let isCommutable = Commutable in {
2567     def _8b8h : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2568                               opnode, VPR64, VPR128, v8i8, v8i16>;
2569     def _4h4s : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2570                               opnode, VPR64, VPR128, v4i16, v4i32>;
2571     def _2s2d : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2572                               opnode, VPR64, VPR128, v2i32, v2i64>;
2573   }
2574 }
2575
2576 defm RADDHNvvv : NeonI_3VDN_2Op<0b1, 0b0100, "raddhn", int_arm_neon_vraddhn, 1>;
2577 defm RSUBHNvvv : NeonI_3VDN_2Op<0b1, 0b0110, "rsubhn", int_arm_neon_vrsubhn, 0>;
2578
2579 // pattern for acle intrinsic with 3 operands
2580 class NeonI_3VDN_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2581                      string asmop, string ResS, string OpS>
2582   : NeonI_3VDiff<q, u, size, opcode,
2583                  (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
2584                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2585                  [], NoItinerary> {
2586   let Constraints = "$src = $Rd";
2587   let neverHasSideEffects = 1;
2588 }
2589
2590 multiclass NeonI_3VDN_3Op_v1<bit u, bits<4> opcode, string asmop> {
2591   def _16b8h : NeonI_3VDN_3Op<0b1, u, 0b00, opcode, asmop, "16b", "8h">;
2592   def _8h4s : NeonI_3VDN_3Op<0b1, u, 0b01, opcode, asmop, "8h", "4s">;
2593   def _4s2d : NeonI_3VDN_3Op<0b1, u, 0b10, opcode, asmop, "4s", "2d">;
2594 }
2595
2596 defm ADDHN2vvv  : NeonI_3VDN_3Op_v1<0b0, 0b0100, "addhn2">;
2597 defm SUBHN2vvv  : NeonI_3VDN_3Op_v1<0b0, 0b0110, "subhn2">;
2598
2599 defm RADDHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0100, "raddhn2">;
2600 defm RSUBHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0110, "rsubhn2">;
2601
2602 // Patterns have to be separate because there's a SUBREG_TO_REG in the output
2603 // part.
2604 class NarrowHighHalfPat<Instruction INST, ValueType DstTy, ValueType SrcTy,
2605                         SDPatternOperator coreop>
2606   : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2607                       (v1i64 (bitconvert (DstTy (coreop (SrcTy VPR128:$Rn),
2608                                                         (SrcTy VPR128:$Rm)))))),
2609         (INST (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2610               VPR128:$Rn, VPR128:$Rm)>;
2611
2612 // addhn2 patterns
2613 def : NarrowHighHalfPat<ADDHN2vvv_16b8h, v8i8,  v8i16,
2614           BinOpFrag<(NI_get_hi_8h (add node:$LHS, node:$RHS))>>;
2615 def : NarrowHighHalfPat<ADDHN2vvv_8h4s,  v4i16, v4i32,
2616           BinOpFrag<(NI_get_hi_4s (add node:$LHS, node:$RHS))>>;
2617 def : NarrowHighHalfPat<ADDHN2vvv_4s2d,  v2i32, v2i64,
2618           BinOpFrag<(NI_get_hi_2d (add node:$LHS, node:$RHS))>>;
2619
2620 // subhn2 patterns
2621 def : NarrowHighHalfPat<SUBHN2vvv_16b8h, v8i8,  v8i16,
2622           BinOpFrag<(NI_get_hi_8h (sub node:$LHS, node:$RHS))>>;
2623 def : NarrowHighHalfPat<SUBHN2vvv_8h4s,  v4i16, v4i32,
2624           BinOpFrag<(NI_get_hi_4s (sub node:$LHS, node:$RHS))>>;
2625 def : NarrowHighHalfPat<SUBHN2vvv_4s2d,  v2i32, v2i64,
2626           BinOpFrag<(NI_get_hi_2d (sub node:$LHS, node:$RHS))>>;
2627
2628 // raddhn2 patterns
2629 def : NarrowHighHalfPat<RADDHN2vvv_16b8h, v8i8,  v8i16, int_arm_neon_vraddhn>;
2630 def : NarrowHighHalfPat<RADDHN2vvv_8h4s,  v4i16, v4i32, int_arm_neon_vraddhn>;
2631 def : NarrowHighHalfPat<RADDHN2vvv_4s2d,  v2i32, v2i64, int_arm_neon_vraddhn>;
2632
2633 // rsubhn2 patterns
2634 def : NarrowHighHalfPat<RSUBHN2vvv_16b8h, v8i8,  v8i16, int_arm_neon_vrsubhn>;
2635 def : NarrowHighHalfPat<RSUBHN2vvv_8h4s,  v4i16, v4i32, int_arm_neon_vrsubhn>;
2636 def : NarrowHighHalfPat<RSUBHN2vvv_4s2d,  v2i32, v2i64, int_arm_neon_vrsubhn>;
2637
2638 // pattern that need to extend result
2639 class NeonI_3VDL_Ext<bit q, bit u, bits<2> size, bits<4> opcode,
2640                      string asmop, string ResS, string OpS,
2641                      SDPatternOperator opnode,
2642                      RegisterOperand OpVPR,
2643                      ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2644   : NeonI_3VDiff<q, u, size, opcode,
2645                  (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2646                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2647                  [(set (ResTy VPR128:$Rd),
2648                     (ResTy (zext (OpSTy (opnode (OpTy OpVPR:$Rn),
2649                                                 (OpTy OpVPR:$Rm))))))],
2650                  NoItinerary>;
2651
2652 multiclass NeonI_3VDL_zext<bit u, bits<4> opcode, string asmop,
2653                            SDPatternOperator opnode, bit Commutable = 0> {
2654   let isCommutable = Commutable in {
2655     def _8h8b : NeonI_3VDL_Ext<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2656                                opnode, VPR64, v8i16, v8i8, v8i8>;
2657     def _4s4h : NeonI_3VDL_Ext<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2658                                opnode, VPR64, v4i32, v4i16, v4i16>;
2659     def _2d2s : NeonI_3VDL_Ext<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2660                                opnode, VPR64, v2i64, v2i32, v2i32>;
2661   }
2662 }
2663
2664 defm SABDLvvv : NeonI_3VDL_zext<0b0, 0b0111, "sabdl", int_arm_neon_vabds, 1>;
2665 defm UABDLvvv : NeonI_3VDL_zext<0b1, 0b0111, "uabdl", int_arm_neon_vabdu, 1>;
2666
2667 multiclass NeonI_Op_High<SDPatternOperator op> {
2668   def _16B : PatFrag<(ops node:$Rn, node:$Rm),
2669                      (op (v8i8 (Neon_High16B node:$Rn)),
2670                          (v8i8 (Neon_High16B node:$Rm)))>;
2671   def _8H  : PatFrag<(ops node:$Rn, node:$Rm),
2672                      (op (v4i16 (Neon_High8H node:$Rn)),
2673                          (v4i16 (Neon_High8H node:$Rm)))>;
2674   def _4S  : PatFrag<(ops node:$Rn, node:$Rm),
2675                      (op (v2i32 (Neon_High4S node:$Rn)),
2676                          (v2i32 (Neon_High4S node:$Rm)))>;
2677 }
2678
2679 defm NI_sabdl_hi : NeonI_Op_High<int_arm_neon_vabds>;
2680 defm NI_uabdl_hi : NeonI_Op_High<int_arm_neon_vabdu>;
2681 defm NI_smull_hi : NeonI_Op_High<int_arm_neon_vmulls>;
2682 defm NI_umull_hi : NeonI_Op_High<int_arm_neon_vmullu>;
2683 defm NI_qdmull_hi : NeonI_Op_High<int_arm_neon_vqdmull>;
2684 defm NI_pmull_hi : NeonI_Op_High<int_arm_neon_vmullp>;
2685
2686 multiclass NeonI_3VDL_Abd_u<bit u, bits<4> opcode, string asmop, string opnode,
2687                             bit Commutable = 0> {
2688   let isCommutable = Commutable in {
2689     def _8h8b  : NeonI_3VDL_Ext<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2690                                 !cast<PatFrag>(opnode # "_16B"),
2691                                 VPR128, v8i16, v16i8, v8i8>;
2692     def _4s4h  : NeonI_3VDL_Ext<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2693                                 !cast<PatFrag>(opnode # "_8H"),
2694                                 VPR128, v4i32, v8i16, v4i16>;
2695     def _2d2s  : NeonI_3VDL_Ext<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2696                                 !cast<PatFrag>(opnode # "_4S"),
2697                                 VPR128, v2i64, v4i32, v2i32>;
2698   }
2699 }
2700
2701 defm SABDL2vvv : NeonI_3VDL_Abd_u<0b0, 0b0111, "sabdl2", "NI_sabdl_hi", 1>;
2702 defm UABDL2vvv : NeonI_3VDL_Abd_u<0b1, 0b0111, "uabdl2", "NI_uabdl_hi", 1>;
2703
2704 // For pattern that need two operators being chained.
2705 class NeonI_3VDL_Aba<bit q, bit u, bits<2> size, bits<4> opcode,
2706                      string asmop, string ResS, string OpS,
2707                      SDPatternOperator opnode, SDPatternOperator subop,
2708                      RegisterOperand OpVPR,
2709                      ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2710   : NeonI_3VDiff<q, u, size, opcode,
2711                  (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2712                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2713                  [(set (ResTy VPR128:$Rd),
2714                     (ResTy (opnode
2715                       (ResTy VPR128:$src),
2716                       (ResTy (zext (OpSTy (subop (OpTy OpVPR:$Rn),
2717                                                  (OpTy OpVPR:$Rm))))))))],
2718                  NoItinerary> {
2719   let Constraints = "$src = $Rd";
2720 }
2721
2722 multiclass NeonI_3VDL_Aba_v1<bit u, bits<4> opcode, string asmop,
2723                              SDPatternOperator opnode, SDPatternOperator subop>{
2724   def _8h8b : NeonI_3VDL_Aba<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2725                              opnode, subop, VPR64, v8i16, v8i8, v8i8>;
2726   def _4s4h : NeonI_3VDL_Aba<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2727                              opnode, subop, VPR64, v4i32, v4i16, v4i16>;
2728   def _2d2s : NeonI_3VDL_Aba<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2729                              opnode, subop, VPR64, v2i64, v2i32, v2i32>;
2730 }
2731
2732 defm SABALvvv :  NeonI_3VDL_Aba_v1<0b0, 0b0101, "sabal",
2733                                    add, int_arm_neon_vabds>;
2734 defm UABALvvv :  NeonI_3VDL_Aba_v1<0b1, 0b0101, "uabal",
2735                                    add, int_arm_neon_vabdu>;
2736
2737 multiclass NeonI_3VDL2_Aba_v1<bit u, bits<4> opcode, string asmop,
2738                               SDPatternOperator opnode, string subop> {
2739   def _8h8b : NeonI_3VDL_Aba<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2740                              opnode, !cast<PatFrag>(subop # "_16B"),
2741                              VPR128, v8i16, v16i8, v8i8>;
2742   def _4s4h : NeonI_3VDL_Aba<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2743                              opnode, !cast<PatFrag>(subop # "_8H"),
2744                              VPR128, v4i32, v8i16, v4i16>;
2745   def _2d2s : NeonI_3VDL_Aba<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2746                              opnode, !cast<PatFrag>(subop # "_4S"),
2747                              VPR128, v2i64, v4i32, v2i32>;
2748 }
2749
2750 defm SABAL2vvv :  NeonI_3VDL2_Aba_v1<0b0, 0b0101, "sabal2", add,
2751                                      "NI_sabdl_hi">;
2752 defm UABAL2vvv :  NeonI_3VDL2_Aba_v1<0b1, 0b0101, "uabal2", add,
2753                                      "NI_uabdl_hi">;
2754
2755 // Long pattern with 2 operands
2756 multiclass NeonI_3VDL_2Op<bit u, bits<4> opcode, string asmop,
2757                           SDPatternOperator opnode, bit Commutable = 0> {
2758   let isCommutable = Commutable in {
2759     def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2760                               opnode, VPR128, VPR64, v8i16, v8i8>;
2761     def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2762                               opnode, VPR128, VPR64, v4i32, v4i16>;
2763     def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2764                               opnode, VPR128, VPR64, v2i64, v2i32>;
2765   }
2766 }
2767
2768 defm SMULLvvv :  NeonI_3VDL_2Op<0b0, 0b1100, "smull", int_arm_neon_vmulls, 1>;
2769 defm UMULLvvv :  NeonI_3VDL_2Op<0b1, 0b1100, "umull", int_arm_neon_vmullu, 1>;
2770
2771 class NeonI_3VDL2_2Op_mull<bit q, bit u, bits<2> size, bits<4> opcode,
2772                            string asmop, string ResS, string OpS,
2773                            SDPatternOperator opnode,
2774                            ValueType ResTy, ValueType OpTy>
2775   : NeonI_3VDiff<q, u, size, opcode,
2776                  (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2777                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2778                  [(set (ResTy VPR128:$Rd),
2779                     (ResTy (opnode (OpTy VPR128:$Rn), (OpTy VPR128:$Rm))))],
2780                  NoItinerary>;
2781
2782 multiclass NeonI_3VDL2_2Op_mull_v1<bit u, bits<4> opcode, string asmop,
2783                                    string opnode, bit Commutable = 0> {
2784   let isCommutable = Commutable in {
2785     def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2786                                       !cast<PatFrag>(opnode # "_16B"),
2787                                       v8i16, v16i8>;
2788     def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2789                                      !cast<PatFrag>(opnode # "_8H"),
2790                                      v4i32, v8i16>;
2791     def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2792                                      !cast<PatFrag>(opnode # "_4S"),
2793                                      v2i64, v4i32>;
2794   }
2795 }
2796
2797 defm SMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b0, 0b1100, "smull2",
2798                                          "NI_smull_hi", 1>;
2799 defm UMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b1, 0b1100, "umull2",
2800                                          "NI_umull_hi", 1>;
2801
2802 // Long pattern with 3 operands
2803 class NeonI_3VDL_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2804                      string asmop, string ResS, string OpS,
2805                      SDPatternOperator opnode,
2806                      ValueType ResTy, ValueType OpTy>
2807   : NeonI_3VDiff<q, u, size, opcode,
2808                  (outs VPR128:$Rd), (ins VPR128:$src, VPR64:$Rn, VPR64:$Rm),
2809                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2810                  [(set (ResTy VPR128:$Rd),
2811                     (ResTy (opnode
2812                       (ResTy VPR128:$src),
2813                       (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))))],
2814                NoItinerary> {
2815   let Constraints = "$src = $Rd";
2816 }
2817
2818 multiclass NeonI_3VDL_3Op_v1<bit u, bits<4> opcode, string asmop,
2819                              SDPatternOperator opnode> {
2820   def _8h8b : NeonI_3VDL_3Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2821                              opnode, v8i16, v8i8>;
2822   def _4s4h : NeonI_3VDL_3Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2823                              opnode, v4i32, v4i16>;
2824   def _2d2s : NeonI_3VDL_3Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2825                              opnode, v2i64, v2i32>;
2826 }
2827
2828 def Neon_smlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2829                          (add node:$Rd,
2830                             (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
2831
2832 def Neon_umlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2833                          (add node:$Rd,
2834                             (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
2835
2836 def Neon_smlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2837                          (sub node:$Rd,
2838                             (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
2839
2840 def Neon_umlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2841                          (sub node:$Rd,
2842                             (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
2843
2844 defm SMLALvvv :  NeonI_3VDL_3Op_v1<0b0, 0b1000, "smlal", Neon_smlal>;
2845 defm UMLALvvv :  NeonI_3VDL_3Op_v1<0b1, 0b1000, "umlal", Neon_umlal>;
2846
2847 defm SMLSLvvv :  NeonI_3VDL_3Op_v1<0b0, 0b1010, "smlsl", Neon_smlsl>;
2848 defm UMLSLvvv :  NeonI_3VDL_3Op_v1<0b1, 0b1010, "umlsl", Neon_umlsl>;
2849
2850 class NeonI_3VDL2_3Op_mlas<bit q, bit u, bits<2> size, bits<4> opcode,
2851                            string asmop, string ResS, string OpS,
2852                            SDPatternOperator subop, SDPatternOperator opnode,
2853                            RegisterOperand OpVPR,
2854                            ValueType ResTy, ValueType OpTy>
2855   : NeonI_3VDiff<q, u, size, opcode,
2856                (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2857                asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2858                [(set (ResTy VPR128:$Rd),
2859                   (ResTy (subop
2860                     (ResTy VPR128:$src),
2861                     (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))))],
2862                NoItinerary> {
2863   let Constraints = "$src = $Rd";
2864 }
2865
2866 multiclass NeonI_3VDL2_3Op_mlas_v1<bit u, bits<4> opcode, string asmop,
2867                                    SDPatternOperator subop, string opnode> {
2868   def _8h16b : NeonI_3VDL2_3Op_mlas<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2869                                     subop, !cast<PatFrag>(opnode # "_16B"),
2870                                     VPR128, v8i16, v16i8>;
2871   def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2872                                    subop, !cast<PatFrag>(opnode # "_8H"),
2873                                    VPR128, v4i32, v8i16>;
2874   def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2875                                    subop, !cast<PatFrag>(opnode # "_4S"),
2876                                    VPR128, v2i64, v4i32>;
2877 }
2878
2879 defm SMLAL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1000, "smlal2",
2880                                           add, "NI_smull_hi">;
2881 defm UMLAL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1000, "umlal2",
2882                                           add, "NI_umull_hi">;
2883
2884 defm SMLSL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1010, "smlsl2",
2885                                           sub, "NI_smull_hi">;
2886 defm UMLSL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1010, "umlsl2",
2887                                           sub, "NI_umull_hi">;
2888
2889 multiclass NeonI_3VDL_qdmlal_3Op_v2<bit u, bits<4> opcode, string asmop,
2890                                     SDPatternOperator opnode> {
2891   def _4s4h : NeonI_3VDL2_3Op_mlas<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2892                                    opnode, int_arm_neon_vqdmull,
2893                                    VPR64, v4i32, v4i16>;
2894   def _2d2s : NeonI_3VDL2_3Op_mlas<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2895                                    opnode, int_arm_neon_vqdmull,
2896                                    VPR64, v2i64, v2i32>;
2897 }
2898
2899 defm SQDMLALvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1001, "sqdmlal",
2900                                            int_arm_neon_vqadds>;
2901 defm SQDMLSLvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1011, "sqdmlsl",
2902                                            int_arm_neon_vqsubs>;
2903
2904 multiclass NeonI_3VDL_v2<bit u, bits<4> opcode, string asmop,
2905                          SDPatternOperator opnode, bit Commutable = 0> {
2906   let isCommutable = Commutable in {
2907     def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2908                               opnode, VPR128, VPR64, v4i32, v4i16>;
2909     def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2910                               opnode, VPR128, VPR64, v2i64, v2i32>;
2911   }
2912 }
2913
2914 defm SQDMULLvvv : NeonI_3VDL_v2<0b0, 0b1101, "sqdmull",
2915                                 int_arm_neon_vqdmull, 1>;
2916
2917 multiclass NeonI_3VDL2_2Op_mull_v2<bit u, bits<4> opcode, string asmop,
2918                                    string opnode, bit Commutable = 0> {
2919   let isCommutable = Commutable in {
2920     def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2921                                      !cast<PatFrag>(opnode # "_8H"),
2922                                      v4i32, v8i16>;
2923     def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2924                                      !cast<PatFrag>(opnode # "_4S"),
2925                                      v2i64, v4i32>;
2926   }
2927 }
2928
2929 defm SQDMULL2vvv : NeonI_3VDL2_2Op_mull_v2<0b0, 0b1101, "sqdmull2",
2930                                            "NI_qdmull_hi", 1>;
2931
2932 multiclass NeonI_3VDL2_3Op_qdmlal_v2<bit u, bits<4> opcode, string asmop,
2933                                      SDPatternOperator opnode> {
2934   def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2935                                    opnode, NI_qdmull_hi_8H,
2936                                    VPR128, v4i32, v8i16>;
2937   def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2938                                    opnode, NI_qdmull_hi_4S,
2939                                    VPR128, v2i64, v4i32>;
2940 }
2941
2942 defm SQDMLAL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1001, "sqdmlal2",
2943                                              int_arm_neon_vqadds>;
2944 defm SQDMLSL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1011, "sqdmlsl2",
2945                                              int_arm_neon_vqsubs>;
2946
2947 multiclass NeonI_3VDL_v3<bit u, bits<4> opcode, string asmop,
2948                          SDPatternOperator opnode, bit Commutable = 0> {
2949   let isCommutable = Commutable in {
2950     def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2951                               opnode, VPR128, VPR64, v8i16, v8i8>;
2952   }
2953 }
2954
2955 defm PMULLvvv : NeonI_3VDL_v3<0b0, 0b1110, "pmull", int_arm_neon_vmullp, 1>;
2956
2957 multiclass NeonI_3VDL2_2Op_mull_v3<bit u, bits<4> opcode, string asmop,
2958                                    string opnode, bit Commutable = 0> {
2959   let isCommutable = Commutable in {
2960     def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2961                                       !cast<PatFrag>(opnode # "_16B"),
2962                                       v8i16, v16i8>;
2963   }
2964 }
2965
2966 defm PMULL2vvv : NeonI_3VDL2_2Op_mull_v3<0b0, 0b1110, "pmull2", "NI_pmull_hi",
2967                                          1>;
2968
2969 // End of implementation for instruction class (3V Diff)
2970
2971 // The followings are vector load/store multiple N-element structure
2972 // (class SIMD lselem).
2973
2974 // ld1:         load multiple 1-element structure to 1/2/3/4 registers.
2975 // ld2/ld3/ld4: load multiple N-element structure to N registers (N = 2, 3, 4).
2976 //              The structure consists of a sequence of sets of N values.
2977 //              The first element of the structure is placed in the first lane
2978 //              of the first first vector, the second element in the first lane
2979 //              of the second vector, and so on.
2980 // E.g. LD1_3V_2S will load 32-bit elements {A, B, C, D, E, F} sequentially into
2981 // the three 64-bit vectors list {BA, DC, FE}.
2982 // E.g. LD3_2S will load 32-bit elements {A, B, C, D, E, F} into the three
2983 // 64-bit vectors list {DA, EB, FC}.
2984 // Store instructions store multiple structure to N registers like load.
2985
2986
2987 class NeonI_LDVList<bit q, bits<4> opcode, bits<2> size,
2988                     RegisterOperand VecList, string asmop>
2989   : NeonI_LdStMult<q, 1, opcode, size,
2990                  (outs VecList:$Rt), (ins GPR64xsp:$Rn),
2991                  asmop # "\t$Rt, [$Rn]",
2992                  [],
2993                  NoItinerary> {
2994   let mayLoad = 1;
2995   let neverHasSideEffects = 1;
2996 }
2997
2998 multiclass LDVList_BHSD<bits<4> opcode, string List, string asmop> {
2999   def _8B : NeonI_LDVList<0, opcode, 0b00,
3000                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3001
3002   def _4H : NeonI_LDVList<0, opcode, 0b01,
3003                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3004
3005   def _2S : NeonI_LDVList<0, opcode, 0b10,
3006                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3007
3008   def _16B : NeonI_LDVList<1, opcode, 0b00,
3009                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3010
3011   def _8H : NeonI_LDVList<1, opcode, 0b01,
3012                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3013
3014   def _4S : NeonI_LDVList<1, opcode, 0b10,
3015                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3016
3017   def _2D : NeonI_LDVList<1, opcode, 0b11,
3018                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3019 }
3020
3021 // Load multiple N-element structure to N consecutive registers (N = 1,2,3,4)
3022 defm LD1 : LDVList_BHSD<0b0111, "VOne", "ld1">;
3023 def LD1_1D : NeonI_LDVList<0, 0b0111, 0b11, VOne1D_operand, "ld1">;
3024
3025 defm LD2 : LDVList_BHSD<0b1000, "VPair", "ld2">;
3026
3027 defm LD3 : LDVList_BHSD<0b0100, "VTriple", "ld3">;
3028
3029 defm LD4 : LDVList_BHSD<0b0000, "VQuad", "ld4">;
3030
3031 // Load multiple 1-element structure to N consecutive registers (N = 2,3,4)
3032 defm LD1_2V : LDVList_BHSD<0b1010, "VPair", "ld1">;
3033 def LD1_2V_1D : NeonI_LDVList<0, 0b1010, 0b11, VPair1D_operand, "ld1">;
3034
3035 defm LD1_3V : LDVList_BHSD<0b0110, "VTriple", "ld1">;
3036 def LD1_3V_1D : NeonI_LDVList<0, 0b0110, 0b11, VTriple1D_operand, "ld1">;
3037
3038 defm LD1_4V : LDVList_BHSD<0b0010, "VQuad", "ld1">;
3039 def LD1_4V_1D : NeonI_LDVList<0, 0b0010, 0b11, VQuad1D_operand, "ld1">;
3040
3041 class NeonI_STVList<bit q, bits<4> opcode, bits<2> size,
3042                     RegisterOperand VecList, string asmop>
3043   : NeonI_LdStMult<q, 0, opcode, size,
3044                  (outs), (ins GPR64xsp:$Rn, VecList:$Rt),
3045                  asmop # "\t$Rt, [$Rn]",
3046                  [],
3047                  NoItinerary> {
3048   let mayStore = 1;
3049   let neverHasSideEffects = 1;
3050 }
3051
3052 multiclass STVList_BHSD<bits<4> opcode, string List, string asmop> {
3053   def _8B : NeonI_STVList<0, opcode, 0b00,
3054                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3055
3056   def _4H : NeonI_STVList<0, opcode, 0b01,
3057                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3058
3059   def _2S : NeonI_STVList<0, opcode, 0b10,
3060                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3061
3062   def _16B : NeonI_STVList<1, opcode, 0b00,
3063                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3064
3065   def _8H : NeonI_STVList<1, opcode, 0b01,
3066                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3067
3068   def _4S : NeonI_STVList<1, opcode, 0b10,
3069                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3070
3071   def _2D : NeonI_STVList<1, opcode, 0b11,
3072                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3073 }
3074
3075 // Store multiple N-element structures from N registers (N = 1,2,3,4)
3076 defm ST1 : STVList_BHSD<0b0111, "VOne", "st1">;
3077 def ST1_1D : NeonI_STVList<0, 0b0111, 0b11, VOne1D_operand, "st1">;
3078
3079 defm ST2 : STVList_BHSD<0b1000, "VPair", "st2">;
3080
3081 defm ST3 : STVList_BHSD<0b0100, "VTriple", "st3">;
3082
3083 defm ST4 : STVList_BHSD<0b0000, "VQuad", "st4">;
3084
3085 // Store multiple 1-element structures from N consecutive registers (N = 2,3,4)
3086 defm ST1_2V : STVList_BHSD<0b1010, "VPair", "st1">;
3087 def ST1_2V_1D : NeonI_STVList<0, 0b1010, 0b11, VPair1D_operand, "st1">;
3088
3089 defm ST1_3V : STVList_BHSD<0b0110, "VTriple", "st1">;
3090 def ST1_3V_1D : NeonI_STVList<0, 0b0110, 0b11, VTriple1D_operand, "st1">;
3091
3092 defm ST1_4V : STVList_BHSD<0b0010, "VQuad", "st1">;
3093 def ST1_4V_1D : NeonI_STVList<0, 0b0010, 0b11, VQuad1D_operand, "st1">;
3094
3095 // End of vector load/store multiple N-element structure(class SIMD lselem)
3096
3097 // The followings are post-index vector load/store multiple N-element
3098 // structure(class SIMD lselem-post)
3099 def exact8_asmoperand : AsmOperandClass {
3100   let Name = "Exact8";
3101   let PredicateMethod = "isExactImm<8>";
3102   let RenderMethod = "addImmOperands";
3103 }
3104 def uimm_exact8 : Operand<i32>, ImmLeaf<i32, [{return Imm == 8;}]> {
3105   let ParserMatchClass = exact8_asmoperand;
3106 }
3107
3108 def exact16_asmoperand : AsmOperandClass {
3109   let Name = "Exact16";
3110   let PredicateMethod = "isExactImm<16>";
3111   let RenderMethod = "addImmOperands";
3112 }
3113 def uimm_exact16 : Operand<i32>, ImmLeaf<i32, [{return Imm == 16;}]> {
3114   let ParserMatchClass = exact16_asmoperand;
3115 }
3116
3117 def exact24_asmoperand : AsmOperandClass {
3118   let Name = "Exact24";
3119   let PredicateMethod = "isExactImm<24>";
3120   let RenderMethod = "addImmOperands";
3121 }
3122 def uimm_exact24 : Operand<i32>, ImmLeaf<i32, [{return Imm == 24;}]> {
3123   let ParserMatchClass = exact24_asmoperand;
3124 }
3125
3126 def exact32_asmoperand : AsmOperandClass {
3127   let Name = "Exact32";
3128   let PredicateMethod = "isExactImm<32>";
3129   let RenderMethod = "addImmOperands";
3130 }
3131 def uimm_exact32 : Operand<i32>, ImmLeaf<i32, [{return Imm == 32;}]> {
3132   let ParserMatchClass = exact32_asmoperand;
3133 }
3134
3135 def exact48_asmoperand : AsmOperandClass {
3136   let Name = "Exact48";
3137   let PredicateMethod = "isExactImm<48>";
3138   let RenderMethod = "addImmOperands";
3139 }
3140 def uimm_exact48 : Operand<i32>, ImmLeaf<i32, [{return Imm == 48;}]> {
3141   let ParserMatchClass = exact48_asmoperand;
3142 }
3143
3144 def exact64_asmoperand : AsmOperandClass {
3145   let Name = "Exact64";
3146   let PredicateMethod = "isExactImm<64>";
3147   let RenderMethod = "addImmOperands";
3148 }
3149 def uimm_exact64 : Operand<i32>, ImmLeaf<i32, [{return Imm == 64;}]> {
3150   let ParserMatchClass = exact64_asmoperand;
3151 }
3152
3153 multiclass NeonI_LDWB_VList<bit q, bits<4> opcode, bits<2> size,
3154                            RegisterOperand VecList, Operand ImmTy,
3155                            string asmop> {
3156   let Constraints = "$Rn = $wb", mayLoad = 1, neverHasSideEffects = 1,
3157       DecoderMethod = "DecodeVLDSTPostInstruction" in {
3158     def _fixed : NeonI_LdStMult_Post<q, 1, opcode, size,
3159                      (outs VecList:$Rt, GPR64xsp:$wb),
3160                      (ins GPR64xsp:$Rn, ImmTy:$amt),
3161                      asmop # "\t$Rt, [$Rn], $amt",
3162                      [],
3163                      NoItinerary> {
3164       let Rm = 0b11111;
3165     }
3166
3167     def _register : NeonI_LdStMult_Post<q, 1, opcode, size,
3168                         (outs VecList:$Rt, GPR64xsp:$wb),
3169                         (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3170                         asmop # "\t$Rt, [$Rn], $Rm",
3171                         [],
3172                         NoItinerary>;
3173   }
3174 }
3175
3176 multiclass LDWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3177     Operand ImmTy2, string asmop> {
3178   defm _8B : NeonI_LDWB_VList<0, opcode, 0b00,
3179                               !cast<RegisterOperand>(List # "8B_operand"),
3180                               ImmTy, asmop>;
3181
3182   defm _4H : NeonI_LDWB_VList<0, opcode, 0b01,
3183                               !cast<RegisterOperand>(List # "4H_operand"),
3184                               ImmTy, asmop>;
3185
3186   defm _2S : NeonI_LDWB_VList<0, opcode, 0b10,
3187                               !cast<RegisterOperand>(List # "2S_operand"),
3188                               ImmTy, asmop>;
3189
3190   defm _16B : NeonI_LDWB_VList<1, opcode, 0b00,
3191                                !cast<RegisterOperand>(List # "16B_operand"),
3192                                ImmTy2, asmop>;
3193
3194   defm _8H : NeonI_LDWB_VList<1, opcode, 0b01,
3195                               !cast<RegisterOperand>(List # "8H_operand"),
3196                               ImmTy2, asmop>;
3197
3198   defm _4S : NeonI_LDWB_VList<1, opcode, 0b10,
3199                               !cast<RegisterOperand>(List # "4S_operand"),
3200                               ImmTy2, asmop>;
3201
3202   defm _2D : NeonI_LDWB_VList<1, opcode, 0b11,
3203                               !cast<RegisterOperand>(List # "2D_operand"),
3204                               ImmTy2, asmop>;
3205 }
3206
3207 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3208 defm LD1WB : LDWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "ld1">;
3209 defm LD1WB_1D : NeonI_LDWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3210                                  "ld1">;
3211
3212 defm LD2WB : LDWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "ld2">;
3213
3214 defm LD3WB : LDWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3215                              "ld3">;
3216
3217 defm LD4WB : LDWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "ld4">;
3218
3219 // Post-index load multiple 1-element structures from N consecutive registers
3220 // (N = 2,3,4)
3221 defm LD1WB2V : LDWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3222                                "ld1">;
3223 defm LD1WB2V_1D : NeonI_LDWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3224                                    uimm_exact16, "ld1">;
3225
3226 defm LD1WB3V : LDWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3227                                "ld1">;
3228 defm LD1WB3V_1D : NeonI_LDWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3229                                    uimm_exact24, "ld1">;
3230
3231 defm LD1WB_4V : LDWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3232                                 "ld1">;
3233 defm LD1WB4V_1D : NeonI_LDWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3234                                    uimm_exact32, "ld1">;
3235
3236 multiclass NeonI_STWB_VList<bit q, bits<4> opcode, bits<2> size,
3237                             RegisterOperand VecList, Operand ImmTy,
3238                             string asmop> {
3239   let Constraints = "$Rn = $wb", mayStore = 1, neverHasSideEffects = 1,
3240       DecoderMethod = "DecodeVLDSTPostInstruction" in {
3241     def _fixed : NeonI_LdStMult_Post<q, 0, opcode, size,
3242                      (outs GPR64xsp:$wb),
3243                      (ins GPR64xsp:$Rn, ImmTy:$amt, VecList:$Rt),
3244                      asmop # "\t$Rt, [$Rn], $amt",
3245                      [],
3246                      NoItinerary> {
3247       let Rm = 0b11111;
3248     }
3249
3250     def _register : NeonI_LdStMult_Post<q, 0, opcode, size,
3251                       (outs GPR64xsp:$wb),
3252                       (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VecList:$Rt),
3253                       asmop # "\t$Rt, [$Rn], $Rm",
3254                       [],
3255                       NoItinerary>;
3256   }
3257 }
3258
3259 multiclass STWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3260                            Operand ImmTy2, string asmop> {
3261   defm _8B : NeonI_STWB_VList<0, opcode, 0b00,
3262                  !cast<RegisterOperand>(List # "8B_operand"), ImmTy, asmop>;
3263
3264   defm _4H : NeonI_STWB_VList<0, opcode, 0b01,
3265                               !cast<RegisterOperand>(List # "4H_operand"),
3266                               ImmTy, asmop>;
3267
3268   defm _2S : NeonI_STWB_VList<0, opcode, 0b10,
3269                               !cast<RegisterOperand>(List # "2S_operand"),
3270                               ImmTy, asmop>;
3271
3272   defm _16B : NeonI_STWB_VList<1, opcode, 0b00,
3273                                !cast<RegisterOperand>(List # "16B_operand"),
3274                                ImmTy2, asmop>;
3275
3276   defm _8H : NeonI_STWB_VList<1, opcode, 0b01,
3277                               !cast<RegisterOperand>(List # "8H_operand"),
3278                               ImmTy2, asmop>;
3279
3280   defm _4S : NeonI_STWB_VList<1, opcode, 0b10,
3281                               !cast<RegisterOperand>(List # "4S_operand"),
3282                               ImmTy2, asmop>;
3283
3284   defm _2D : NeonI_STWB_VList<1, opcode, 0b11,
3285                               !cast<RegisterOperand>(List # "2D_operand"),
3286                               ImmTy2, asmop>;
3287 }
3288
3289 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3290 defm ST1WB : STWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "st1">;
3291 defm ST1WB_1D : NeonI_STWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3292                                  "st1">;
3293
3294 defm ST2WB : STWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "st2">;
3295
3296 defm ST3WB : STWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3297                              "st3">;
3298
3299 defm ST4WB : STWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "st4">;
3300
3301 // Post-index load multiple 1-element structures from N consecutive registers
3302 // (N = 2,3,4)
3303 defm ST1WB2V : STWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3304                                "st1">;
3305 defm ST1WB2V_1D : NeonI_STWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3306                                    uimm_exact16, "st1">;
3307
3308 defm ST1WB3V : STWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3309                                "st1">;
3310 defm ST1WB3V_1D : NeonI_STWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3311                                    uimm_exact24, "st1">;
3312
3313 defm ST1WB4V : STWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3314                                "st1">;
3315 defm ST1WB4V_1D : NeonI_STWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3316                                    uimm_exact32, "st1">;
3317
3318 // End of post-index vector load/store multiple N-element structure
3319 // (class SIMD lselem-post)
3320
3321 // Scalar Three Same
3322
3323 class NeonI_Scalar3Same_size<bit u, bits<2> size, bits<5> opcode, string asmop,
3324                              RegisterClass FPRC>
3325   : NeonI_Scalar3Same<u, size, opcode,
3326                       (outs FPRC:$Rd), (ins FPRC:$Rn, FPRC:$Rm),
3327                       !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
3328                       [],
3329                       NoItinerary>;
3330
3331 class NeonI_Scalar3Same_D_size<bit u, bits<5> opcode, string asmop>
3332   : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
3333
3334 multiclass NeonI_Scalar3Same_HS_sizes<bit u, bits<5> opcode, string asmop,
3335                                       bit Commutable = 0> {
3336   let isCommutable = Commutable in {
3337     def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
3338     def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
3339   }
3340 }
3341
3342 multiclass NeonI_Scalar3Same_SD_sizes<bit u, bit size_high, bits<5> opcode,
3343                                       string asmop, bit Commutable = 0> {
3344   let isCommutable = Commutable in {
3345     def sss : NeonI_Scalar3Same_size<u, {size_high, 0b0}, opcode, asmop, FPR32>;
3346     def ddd : NeonI_Scalar3Same_size<u, {size_high, 0b1}, opcode, asmop, FPR64>;
3347   }
3348 }
3349
3350 multiclass NeonI_Scalar3Same_BHSD_sizes<bit u, bits<5> opcode,
3351                                         string asmop, bit Commutable = 0> {
3352   let isCommutable = Commutable in {
3353     def bbb : NeonI_Scalar3Same_size<u, 0b00, opcode, asmop, FPR8>;
3354     def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
3355     def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
3356     def ddd : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
3357   }
3358 }
3359
3360 multiclass Neon_Scalar3Same_D_size_patterns<SDPatternOperator opnode,
3361                                             Instruction INSTD> {
3362   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
3363             (INSTD FPR64:$Rn, FPR64:$Rm)>;
3364 }
3365
3366 multiclass Neon_Scalar3Same_BHSD_size_patterns<SDPatternOperator opnode,
3367                                                Instruction INSTB,
3368                                                Instruction INSTH,
3369                                                Instruction INSTS,
3370                                                Instruction INSTD>
3371   : Neon_Scalar3Same_D_size_patterns<opnode, INSTD> {
3372   def: Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (v1i8 FPR8:$Rm))),
3373            (INSTB FPR8:$Rn, FPR8:$Rm)>;
3374
3375   def: Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
3376            (INSTH FPR16:$Rn, FPR16:$Rm)>;
3377
3378   def: Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
3379            (INSTS FPR32:$Rn, FPR32:$Rm)>;
3380 }
3381
3382 class Neon_Scalar3Same_cmp_D_size_patterns<SDPatternOperator opnode,
3383                                            Instruction INSTD>
3384   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
3385         (INSTD FPR64:$Rn, FPR64:$Rm)>;
3386
3387 multiclass Neon_Scalar3Same_HS_size_patterns<SDPatternOperator opnode,
3388                                              Instruction INSTH,
3389                                              Instruction INSTS> {
3390   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
3391             (INSTH FPR16:$Rn, FPR16:$Rm)>;
3392   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
3393             (INSTS FPR32:$Rn, FPR32:$Rm)>;
3394 }
3395
3396 multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
3397                                              Instruction INSTS,
3398                                              Instruction INSTD> {
3399   def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
3400             (INSTS FPR32:$Rn, FPR32:$Rm)>;
3401   def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3402             (INSTD FPR64:$Rn, FPR64:$Rm)>;
3403 }
3404
3405 multiclass Neon_Scalar3Same_cmp_SD_size_patterns<SDPatternOperator opnode,
3406                                                  Instruction INSTS,
3407                                                  Instruction INSTD> {
3408   def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
3409             (INSTS FPR32:$Rn, FPR32:$Rm)>;
3410   def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3411             (INSTD FPR64:$Rn, FPR64:$Rm)>;
3412 }
3413
3414 // Scalar Three Different
3415
3416 class NeonI_Scalar3Diff_size<bit u, bits<2> size, bits<4> opcode, string asmop,
3417                              RegisterClass FPRCD, RegisterClass FPRCS>
3418   : NeonI_Scalar3Diff<u, size, opcode,
3419                       (outs FPRCD:$Rd), (ins FPRCS:$Rn, FPRCS:$Rm),
3420                       !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
3421                       [],
3422                       NoItinerary>;
3423
3424 multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> {
3425   def shh : NeonI_Scalar3Diff_size<u, 0b01, opcode, asmop, FPR32, FPR16>;
3426   def dss : NeonI_Scalar3Diff_size<u, 0b10, opcode, asmop, FPR64, FPR32>;
3427 }
3428
3429 multiclass NeonI_Scalar3Diff_ml_HS_size<bit u, bits<4> opcode, string asmop> {
3430   let Constraints = "$Src = $Rd" in {
3431     def shh : NeonI_Scalar3Diff<u, 0b01, opcode,
3432                        (outs FPR32:$Rd), (ins FPR32:$Src, FPR16:$Rn, FPR16:$Rm),
3433                        !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
3434                        [],
3435                        NoItinerary>;
3436     def dss : NeonI_Scalar3Diff<u, 0b10, opcode,
3437                        (outs FPR64:$Rd), (ins FPR64:$Src, FPR32:$Rn, FPR32:$Rm),
3438                        !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
3439                        [],
3440                        NoItinerary>;
3441   }
3442 }
3443
3444 multiclass Neon_Scalar3Diff_HS_size_patterns<SDPatternOperator opnode,
3445                                              Instruction INSTH,
3446                                              Instruction INSTS> {
3447   def : Pat<(v1i32 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
3448             (INSTH FPR16:$Rn, FPR16:$Rm)>;
3449   def : Pat<(v1i64 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
3450             (INSTS FPR32:$Rn, FPR32:$Rm)>;
3451 }
3452
3453 multiclass Neon_Scalar3Diff_ml_HS_size_patterns<SDPatternOperator opnode,
3454                                              Instruction INSTH,
3455                                              Instruction INSTS> {
3456   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
3457             (INSTH FPR32:$Src, FPR16:$Rn, FPR16:$Rm)>;
3458   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
3459             (INSTS FPR64:$Src, FPR32:$Rn, FPR32:$Rm)>;
3460 }
3461
3462 // Scalar Two Registers Miscellaneous
3463
3464 class NeonI_Scalar2SameMisc_size<bit u, bits<2> size, bits<5> opcode, string asmop,
3465                              RegisterClass FPRCD, RegisterClass FPRCS>
3466   : NeonI_Scalar2SameMisc<u, size, opcode,
3467                           (outs FPRCD:$Rd), (ins FPRCS:$Rn),
3468                           !strconcat(asmop, "\t$Rd, $Rn"),
3469                           [],
3470                           NoItinerary>;
3471
3472 multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
3473                                          string asmop> {
3474   def ss : NeonI_Scalar2SameMisc_size<u, {size_high, 0b0}, opcode, asmop, FPR32,
3475                                       FPR32>;
3476   def dd : NeonI_Scalar2SameMisc_size<u, {size_high, 0b1}, opcode, asmop, FPR64,
3477                                       FPR64>;
3478 }
3479
3480 multiclass NeonI_Scalar2SameMisc_D_size<bit u, bits<5> opcode, string asmop> {
3481   def dd: NeonI_Scalar2SameMisc_size<u, 0b11, opcode, asmop, FPR64, FPR64>;
3482 }
3483
3484 multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>
3485   : NeonI_Scalar2SameMisc_D_size<u, opcode, asmop> {
3486   def bb : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR8>;
3487   def hh : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR16>;
3488   def ss : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR32>;
3489 }
3490
3491 multiclass NeonI_Scalar2SameMisc_narrow_HSD_size<bit u, bits<5> opcode,
3492                                                  string asmop> {
3493   def bh : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR16>;
3494   def hs : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR32>;
3495   def sd : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR64>;
3496 }
3497
3498 class NeonI_Scalar2SameMisc_accum_size<bit u, bits<2> size, bits<5> opcode,
3499                                        string asmop, RegisterClass FPRC>
3500   : NeonI_Scalar2SameMisc<u, size, opcode,
3501                           (outs FPRC:$Rd), (ins FPRC:$Src, FPRC:$Rn),
3502                           !strconcat(asmop, "\t$Rd, $Rn"),
3503                           [],
3504                           NoItinerary>;
3505
3506 multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
3507                                                  string asmop> {
3508
3509   let Constraints = "$Src = $Rd" in {
3510     def bb : NeonI_Scalar2SameMisc_accum_size<u, 0b00, opcode, asmop, FPR8>;
3511     def hh : NeonI_Scalar2SameMisc_accum_size<u, 0b01, opcode, asmop, FPR16>;
3512     def ss : NeonI_Scalar2SameMisc_accum_size<u, 0b10, opcode, asmop, FPR32>;
3513     def dd : NeonI_Scalar2SameMisc_accum_size<u, 0b11, opcode, asmop, FPR64>;
3514   }
3515 }
3516
3517 multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator Sopnode,
3518                                                      SDPatternOperator Dopnode,
3519                                                      Instruction INSTS,
3520                                                      Instruction INSTD> {
3521   def : Pat<(v1f32 (Sopnode (v1i32 FPR32:$Rn))),
3522             (INSTS FPR32:$Rn)>;
3523   def : Pat<(v1f64 (Dopnode (v1i64 FPR64:$Rn))),
3524             (INSTD FPR64:$Rn)>;
3525 }
3526
3527 multiclass Neon_Scalar2SameMisc_SD_size_patterns<SDPatternOperator opnode,
3528                                                  Instruction INSTS,
3529                                                  Instruction INSTD> {
3530   def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn))),
3531             (INSTS FPR32:$Rn)>;
3532   def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))),
3533             (INSTD FPR64:$Rn)>;
3534 }
3535
3536 class NeonI_Scalar2SameMisc_cmpz_D_size<bit u, bits<5> opcode, string asmop>
3537   : NeonI_Scalar2SameMisc<u, 0b11, opcode,
3538                           (outs FPR64:$Rd), (ins FPR64:$Rn, neon_uimm0:$Imm),
3539                           !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3540                           [],
3541                           NoItinerary>;
3542
3543 multiclass NeonI_Scalar2SameMisc_cmpz_SD_size<bit u, bits<5> opcode,
3544                                               string asmop> {
3545   def ssi : NeonI_Scalar2SameMisc<u, 0b10, opcode,
3546                            (outs FPR32:$Rd), (ins FPR32:$Rn, fpz32:$FPImm),
3547                            !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
3548                            [],
3549                            NoItinerary>;
3550   def ddi : NeonI_Scalar2SameMisc<u, 0b11, opcode,
3551                            (outs FPR64:$Rd), (ins FPR64:$Rn, fpz64movi:$FPImm),
3552                            !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
3553                            [],
3554                            NoItinerary>;
3555 }
3556
3557 class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode,
3558                                                 Instruction INSTD>
3559   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
3560                        (v1i64 (bitconvert (v8i8 Neon_immAllZeros))))),
3561         (INSTD FPR64:$Rn, 0)>;
3562
3563 multiclass Neon_Scalar2SameMisc_cmpz_SD_size_patterns<SDPatternOperator opnode,
3564                                                       Instruction INSTS,
3565                                                       Instruction INSTD> {
3566   def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn),
3567                            (v1f32 (scalar_to_vector (f32 fpimm:$FPImm))))),
3568             (INSTS FPR32:$Rn, fpimm:$FPImm)>;
3569   def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn),
3570                            (v1f64 (bitconvert (v8i8 Neon_immAllZeros))))),
3571             (INSTD FPR64:$Rn, 0)>;
3572 }
3573
3574 multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode,
3575                                                 Instruction INSTD> {
3576   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))),
3577             (INSTD FPR64:$Rn)>;
3578 }
3579
3580 multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
3581                                                    Instruction INSTB,
3582                                                    Instruction INSTH,
3583                                                    Instruction INSTS,
3584                                                    Instruction INSTD>
3585   : Neon_Scalar2SameMisc_D_size_patterns<opnode, INSTD> {
3586   def : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn))),
3587             (INSTB FPR8:$Rn)>;
3588   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn))),
3589             (INSTH FPR16:$Rn)>;
3590   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn))),
3591             (INSTS FPR32:$Rn)>;
3592 }
3593
3594 multiclass Neon_Scalar2SameMisc_narrow_HSD_size_patterns<
3595                                                        SDPatternOperator opnode,
3596                                                        Instruction INSTH,
3597                                                        Instruction INSTS,
3598                                                        Instruction INSTD> {
3599   def : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn))),
3600             (INSTH FPR16:$Rn)>;
3601   def : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn))),
3602             (INSTS FPR32:$Rn)>;
3603   def : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn))),
3604             (INSTD FPR64:$Rn)>;
3605
3606 }
3607
3608 multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns<
3609                                                        SDPatternOperator opnode,
3610                                                        Instruction INSTB,
3611                                                        Instruction INSTH,
3612                                                        Instruction INSTS,
3613                                                        Instruction INSTD> {
3614   def : Pat<(v1i8 (opnode (v1i8 FPR8:$Src), (v1i8 FPR8:$Rn))),
3615             (INSTB FPR8:$Src, FPR8:$Rn)>;
3616   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Src), (v1i16 FPR16:$Rn))),
3617             (INSTH FPR16:$Src, FPR16:$Rn)>;
3618   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i32 FPR32:$Rn))),
3619             (INSTS FPR32:$Src, FPR32:$Rn)>;
3620   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn))),
3621             (INSTD FPR64:$Src, FPR64:$Rn)>;
3622 }
3623
3624 // Scalar Shift By Immediate
3625
3626 class NeonI_ScalarShiftImm_size<bit u, bits<5> opcode, string asmop,
3627                                 RegisterClass FPRC, Operand ImmTy>
3628   : NeonI_ScalarShiftImm<u, opcode,
3629                          (outs FPRC:$Rd), (ins FPRC:$Rn, ImmTy:$Imm),
3630                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3631                          [], NoItinerary>;
3632
3633 multiclass NeonI_ScalarShiftRightImm_D_size<bit u, bits<5> opcode,
3634                                             string asmop> {
3635   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
3636     bits<6> Imm;
3637     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
3638     let Inst{21-16} = Imm;
3639   }
3640 }
3641
3642 multiclass NeonI_ScalarShiftRightImm_BHSD_size<bit u, bits<5> opcode,
3643                                                string asmop>
3644   : NeonI_ScalarShiftRightImm_D_size<u, opcode, asmop> {
3645   def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shr_imm8> {
3646     bits<3> Imm;
3647     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
3648     let Inst{18-16} = Imm;
3649   }
3650   def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shr_imm16> {
3651     bits<4> Imm;
3652     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
3653     let Inst{19-16} = Imm;
3654   }
3655   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
3656     bits<5> Imm;
3657     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
3658     let Inst{20-16} = Imm;
3659   }
3660 }
3661
3662 multiclass NeonI_ScalarShiftLeftImm_D_size<bit u, bits<5> opcode,
3663                                             string asmop> {
3664   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shl_imm64> {
3665     bits<6> Imm;
3666     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
3667     let Inst{21-16} = Imm;
3668   }
3669 }
3670
3671 multiclass NeonI_ScalarShiftLeftImm_BHSD_size<bit u, bits<5> opcode,
3672                                               string asmop>
3673   : NeonI_ScalarShiftLeftImm_D_size<u, opcode, asmop> {
3674   def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shl_imm8> {
3675     bits<3> Imm;
3676     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
3677     let Inst{18-16} = Imm;
3678   }
3679   def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shl_imm16> {
3680     bits<4> Imm;
3681     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
3682     let Inst{19-16} = Imm;
3683   }
3684   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shl_imm32> {
3685     bits<5> Imm;
3686     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
3687     let Inst{20-16} = Imm;
3688   }
3689 }
3690
3691 class NeonI_ScalarShiftImm_accum_D_size<bit u, bits<5> opcode, string asmop>
3692   : NeonI_ScalarShiftImm<u, opcode,
3693                          (outs FPR64:$Rd), (ins FPR64:$Src, FPR64:$Rn, shr_imm64:$Imm),
3694                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3695                          [], NoItinerary> {
3696     bits<6> Imm;
3697     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
3698     let Inst{21-16} = Imm;
3699     let Constraints = "$Src = $Rd";
3700 }
3701
3702 class NeonI_ScalarShiftImm_narrow_size<bit u, bits<5> opcode, string asmop,
3703                                        RegisterClass FPRCD, RegisterClass FPRCS,
3704                                        Operand ImmTy>
3705   : NeonI_ScalarShiftImm<u, opcode,
3706                          (outs FPRCD:$Rd), (ins FPRCS:$Rn, ImmTy:$Imm),
3707                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3708                          [], NoItinerary>;
3709
3710 multiclass NeonI_ScalarShiftImm_narrow_HSD_size<bit u, bits<5> opcode,
3711                                                 string asmop> {
3712   def bhi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR8, FPR16,
3713                                              shr_imm8> {
3714     bits<3> Imm;
3715     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
3716     let Inst{18-16} = Imm;
3717   }
3718   def hsi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR16, FPR32,
3719                                              shr_imm16> {
3720     bits<4> Imm;
3721     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
3722     let Inst{19-16} = Imm;
3723   }
3724   def sdi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR32, FPR64,
3725                                              shr_imm32> {
3726     bits<5> Imm;
3727     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
3728     let Inst{20-16} = Imm;
3729   }
3730 }
3731
3732 multiclass NeonI_ScalarShiftImm_scvtf_SD_size<bit u, bits<5> opcode, string asmop> {
3733   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
3734     bits<5> Imm;
3735     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
3736     let Inst{20-16} = Imm;
3737   }
3738   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
3739     bits<6> Imm;
3740     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
3741     let Inst{21-16} = Imm;
3742   }
3743 }
3744
3745 multiclass Neon_ScalarShiftImm_D_size_patterns<SDPatternOperator opnode,
3746                                                Instruction INSTD> {
3747   def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
3748                 (INSTD FPR64:$Rn, imm:$Imm)>;
3749 }
3750
3751 multiclass Neon_ScalarShiftImm_BHSD_size_patterns<SDPatternOperator opnode,
3752                                                   Instruction INSTB,
3753                                                   Instruction INSTH,
3754                                                   Instruction INSTS,
3755                                                   Instruction INSTD>
3756   : Neon_ScalarShiftImm_D_size_patterns<opnode, INSTD> {
3757   def bbi : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (i32 imm:$Imm))),
3758                 (INSTB FPR8:$Rn, imm:$Imm)>;
3759   def hhi : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (i32 imm:$Imm))),
3760                 (INSTH FPR16:$Rn, imm:$Imm)>;
3761   def ssi : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (i32 imm:$Imm))),
3762                 (INSTS FPR32:$Rn, imm:$Imm)>;
3763 }
3764
3765 class Neon_ScalarShiftImm_accum_D_size_patterns<SDPatternOperator opnode,
3766                                           Instruction INSTD>
3767   : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
3768         (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
3769
3770 multiclass Neon_ScalarShiftImm_narrow_HSD_size_patterns<
3771                                                        SDPatternOperator opnode,
3772                                                        Instruction INSTH,
3773                                                        Instruction INSTS,
3774                                                        Instruction INSTD> {
3775   def bhi : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn), (i32 imm:$Imm))),
3776                 (INSTH FPR16:$Rn, imm:$Imm)>;
3777   def hsi : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn), (i32 imm:$Imm))),
3778                 (INSTS FPR32:$Rn, imm:$Imm)>;
3779   def sdi : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
3780                 (INSTD FPR64:$Rn, imm:$Imm)>;
3781 }
3782
3783 multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns<SDPatternOperator Sopnode,
3784                                                       SDPatternOperator Dopnode,
3785                                                       Instruction INSTS,
3786                                                       Instruction INSTD> {
3787   def ssi : Pat<(v1f32 (Sopnode (v1i32 FPR32:$Rn), (i32 imm:$Imm))),
3788                 (INSTS FPR32:$Rn, imm:$Imm)>;
3789   def ddi : Pat<(v1f64 (Dopnode (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
3790                 (INSTD FPR64:$Rn, imm:$Imm)>;
3791 }
3792
3793 // Scalar Signed Shift Right (Immediate)
3794 defm SSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00000, "sshr">;
3795 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vshrds_n, SSHRddi>;
3796
3797 // Scalar Unsigned Shift Right (Immediate)
3798 defm USHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00000, "ushr">;
3799 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vshrdu_n, USHRddi>;
3800
3801 // Scalar Signed Rounding Shift Right (Immediate)
3802 defm SRSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00100, "srshr">;
3803 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vrshrds_n, SRSHRddi>;
3804
3805 // Scalar Unigned Rounding Shift Right (Immediate)
3806 defm URSHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00100, "urshr">;
3807 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vrshrdu_n, URSHRddi>;
3808
3809 // Scalar Signed Shift Right and Accumulate (Immediate)
3810 def SSRA : NeonI_ScalarShiftImm_accum_D_size<0b0, 0b00010, "ssra">;
3811 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vsrads_n, SSRA>;
3812
3813 // Scalar Unsigned Shift Right and Accumulate (Immediate)
3814 def USRA : NeonI_ScalarShiftImm_accum_D_size<0b1, 0b00010, "usra">;
3815 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vsradu_n, USRA>;
3816
3817 // Scalar Signed Rounding Shift Right and Accumulate (Immediate)
3818 def SRSRA : NeonI_ScalarShiftImm_accum_D_size<0b0, 0b00110, "srsra">;
3819 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vrsrads_n, SRSRA>;
3820
3821 // Scalar Unsigned Rounding Shift Right and Accumulate (Immediate)
3822 def URSRA : NeonI_ScalarShiftImm_accum_D_size<0b1, 0b00110, "ursra">;
3823 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vrsradu_n, URSRA>;
3824
3825 // Scalar Shift Left (Immediate)
3826 defm SHL : NeonI_ScalarShiftLeftImm_D_size<0b0, 0b01010, "shl">;
3827 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vshld_n, SHLddi>;
3828
3829 // Signed Saturating Shift Left (Immediate)
3830 defm SQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b0, 0b01110, "sqshl">;
3831 defm : Neon_ScalarShiftImm_BHSD_size_patterns<int_aarch64_neon_vqshls_n,
3832                                               SQSHLbbi, SQSHLhhi,
3833                                               SQSHLssi, SQSHLddi>;
3834
3835 // Unsigned Saturating Shift Left (Immediate)
3836 defm UQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01110, "uqshl">;
3837 defm : Neon_ScalarShiftImm_BHSD_size_patterns<int_aarch64_neon_vqshlu_n,
3838                                               UQSHLbbi, UQSHLhhi,
3839                                               UQSHLssi, UQSHLddi>;
3840
3841 // Signed Saturating Shift Left Unsigned (Immediate)
3842 defm SQSHLU : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01100, "sqshlu">;
3843 defm : Neon_ScalarShiftImm_BHSD_size_patterns<int_aarch64_neon_vqshlus_n,
3844                                               SQSHLUbbi, SQSHLUhhi,
3845                                               SQSHLUssi, SQSHLUddi>;
3846
3847 // Shift Right And Insert (Immediate)
3848 defm SRI : NeonI_ScalarShiftRightImm_D_size<0b1, 0b01000, "sri">;
3849 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vsrid_n, SRIddi>;
3850
3851 // Shift Left And Insert (Immediate)
3852 defm SLI : NeonI_ScalarShiftLeftImm_D_size<0b1, 0b01010, "sli">;
3853 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vslid_n, SLIddi>;
3854
3855 // Signed Saturating Shift Right Narrow (Immediate)
3856 defm SQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10010, "sqshrn">;
3857 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrn,
3858                                                     SQSHRNbhi, SQSHRNhsi,
3859                                                     SQSHRNsdi>;
3860
3861 // Unsigned Saturating Shift Right Narrow (Immediate)
3862 defm UQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10010, "uqshrn">;
3863 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqshrn,
3864                                                     UQSHRNbhi, UQSHRNhsi,
3865                                                     UQSHRNsdi>;
3866
3867 // Signed Saturating Rounded Shift Right Narrow (Immediate)
3868 defm SQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10011, "sqrshrn">;
3869 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrn,
3870                                                     SQRSHRNbhi, SQRSHRNhsi,
3871                                                     SQRSHRNsdi>;
3872
3873 // Unsigned Saturating Rounded Shift Right Narrow (Immediate)
3874 defm UQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10011, "uqrshrn">;
3875 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqrshrn,
3876                                                     UQRSHRNbhi, UQRSHRNhsi,
3877                                                     UQRSHRNsdi>;
3878
3879 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
3880 defm SQSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10000, "sqshrun">;
3881 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrun,
3882                                                     SQSHRUNbhi, SQSHRUNhsi,
3883                                                     SQSHRUNsdi>;
3884
3885 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
3886 defm SQRSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10001, "sqrshrun">;
3887 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrun,
3888                                                     SQRSHRUNbhi, SQRSHRUNhsi,
3889                                                     SQRSHRUNsdi>;
3890
3891 // Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
3892 defm SCVTF_N : NeonI_ScalarShiftImm_scvtf_SD_size<0b0, 0b11100, "scvtf">;
3893 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtf32_n_s32,
3894                                                   int_aarch64_neon_vcvtf64_n_s64,
3895                                                   SCVTF_Nssi, SCVTF_Nddi>;
3896
3897 // Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
3898 defm UCVTF_N : NeonI_ScalarShiftImm_scvtf_SD_size<0b1, 0b11100, "ucvtf">;
3899 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtf32_n_u32,
3900                                                   int_aarch64_neon_vcvtf64_n_u64,
3901                                                   UCVTF_Nssi, UCVTF_Nddi>;
3902
3903 // Scalar Integer Add
3904 let isCommutable = 1 in {
3905 def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
3906 }
3907
3908 // Scalar Integer Sub
3909 def SUBddd : NeonI_Scalar3Same_D_size<0b1, 0b10000, "sub">;
3910
3911 // Pattern for Scalar Integer Add and Sub with D register only
3912 defm : Neon_Scalar3Same_D_size_patterns<add, ADDddd>;
3913 defm : Neon_Scalar3Same_D_size_patterns<sub, SUBddd>;
3914
3915 // Patterns to match llvm.aarch64.* intrinsic for Scalar Add, Sub
3916 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vaddds, ADDddd>;
3917 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vadddu, ADDddd>;
3918 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubds, SUBddd>;
3919 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubdu, SUBddd>;
3920
3921 // Scalar Integer Saturating Add (Signed, Unsigned)
3922 defm SQADD : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00001, "sqadd", 1>;
3923 defm UQADD : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00001, "uqadd", 1>;
3924
3925 // Scalar Integer Saturating Sub (Signed, Unsigned)
3926 defm SQSUB : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00101, "sqsub", 0>;
3927 defm UQSUB : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00101, "uqsub", 0>;
3928
3929 // Patterns to match llvm.arm.* intrinsic for
3930 // Scalar Integer Saturating Add, Sub  (Signed, Unsigned)
3931 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqadds, SQADDddd>;
3932 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqaddu, UQADDddd>;
3933 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqsubs, SQSUBddd>;
3934 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqsubu, UQSUBddd>;
3935
3936 // Patterns to match llvm.aarch64.* intrinsic for
3937 // Scalar Integer Saturating Add, Sub  (Signed, Unsigned)
3938 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqadds, SQADDbbb,
3939                                            SQADDhhh, SQADDsss, SQADDddd>;
3940 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqaddu, UQADDbbb,
3941                                            UQADDhhh, UQADDsss, UQADDddd>;
3942 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqsubs, SQSUBbbb,
3943                                            SQSUBhhh, SQSUBsss, SQSUBddd>;
3944 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqsubu, UQSUBbbb,
3945                                            UQSUBhhh, UQSUBsss, UQSUBddd>;
3946
3947 // Scalar Integer Saturating Doubling Multiply Half High
3948 defm SQDMULH : NeonI_Scalar3Same_HS_sizes<0b0, 0b10110, "sqdmulh", 1>;
3949
3950 // Scalar Integer Saturating Rounding Doubling Multiply Half High
3951 defm SQRDMULH : NeonI_Scalar3Same_HS_sizes<0b1, 0b10110, "sqrdmulh", 1>;
3952
3953 // Patterns to match llvm.arm.* intrinsic for
3954 // Scalar Integer Saturating Doubling Multiply Half High and
3955 // Scalar Integer Saturating Rounding Doubling Multiply Half High
3956 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqdmulh, SQDMULHhhh,
3957                                                                SQDMULHsss>;
3958 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqrdmulh, SQRDMULHhhh,
3959                                                                 SQRDMULHsss>;
3960
3961 // Scalar Floating-point Multiply Extended
3962 defm FMULX : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11011, "fmulx", 1>;
3963
3964 // Scalar Floating-point Reciprocal Step
3965 defm FRECPS : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11111, "frecps", 0>;
3966
3967 // Scalar Floating-point Reciprocal Square Root Step
3968 defm FRSQRTS : NeonI_Scalar3Same_SD_sizes<0b0, 0b1, 0b11111, "frsqrts", 0>;
3969
3970 // Patterns to match llvm.arm.* intrinsic for
3971 // Scalar Floating-point Reciprocal Step and
3972 // Scalar Floating-point Reciprocal Square Root Step
3973 defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrecps, FRECPSsss,
3974                                                               FRECPSddd>;
3975 defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrsqrts, FRSQRTSsss,
3976                                                                FRSQRTSddd>;
3977
3978 // Patterns to match llvm.aarch64.* intrinsic for
3979 // Scalar Floating-point Multiply Extended,
3980 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vmulx, FMULXsss,
3981                                          FMULXddd>;
3982
3983 // Scalar Integer Shift Left (Signed, Unsigned)
3984 def SSHLddd : NeonI_Scalar3Same_D_size<0b0, 0b01000, "sshl">;
3985 def USHLddd : NeonI_Scalar3Same_D_size<0b1, 0b01000, "ushl">;
3986
3987 // Patterns to match llvm.arm.* intrinsic for
3988 // Scalar Integer Shift Left (Signed, Unsigned)
3989 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshifts, SSHLddd>;
3990 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshiftu, USHLddd>;
3991
3992 // Patterns to match llvm.aarch64.* intrinsic for
3993 // Scalar Integer Shift Left (Signed, Unsigned)
3994 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshlds, SSHLddd>;
3995 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshldu, USHLddd>;
3996
3997 // Scalar Integer Saturating Shift Left (Signed, Unsigned)
3998 defm SQSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01001, "sqshl", 0>;
3999 defm UQSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01001, "uqshl", 0>;
4000
4001 // Patterns to match llvm.aarch64.* intrinsic for
4002 // Scalar  Integer Saturating Shift Letf (Signed, Unsigned)
4003 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshls, SQSHLbbb,
4004                                            SQSHLhhh, SQSHLsss, SQSHLddd>;
4005 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshlu, UQSHLbbb,
4006                                            UQSHLhhh, UQSHLsss, UQSHLddd>;
4007
4008 // Patterns to match llvm.arm.* intrinsic for
4009 // Scalar  Integer Saturating Shift Letf (Signed, Unsigned)
4010 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshifts, SQSHLddd>;
4011 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshiftu, UQSHLddd>;
4012
4013 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4014 def SRSHLddd: NeonI_Scalar3Same_D_size<0b0, 0b01010, "srshl">;
4015 def URSHLddd: NeonI_Scalar3Same_D_size<0b1, 0b01010, "urshl">;
4016
4017 // Patterns to match llvm.aarch64.* intrinsic for
4018 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4019 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshlds, SRSHLddd>;
4020 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshldu, URSHLddd>;
4021
4022 // Patterns to match llvm.arm.* intrinsic for
4023 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4024 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshifts, SRSHLddd>;
4025 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshiftu, URSHLddd>;
4026
4027 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4028 defm SQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01011, "sqrshl", 0>;
4029 defm UQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01011, "uqrshl", 0>;
4030
4031 // Patterns to match llvm.aarch64.* intrinsic for
4032 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4033 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshls, SQRSHLbbb,
4034                                            SQRSHLhhh, SQRSHLsss, SQRSHLddd>;
4035 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb,
4036                                            UQRSHLhhh, UQRSHLsss, UQRSHLddd>;
4037
4038 // Patterns to match llvm.arm.* intrinsic for
4039 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4040 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
4041 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
4042
4043 // Signed Saturating Doubling Multiply-Add Long
4044 defm SQDMLAL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1001, "sqdmlal">;
4045 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlal,
4046                                             SQDMLALshh, SQDMLALdss>;
4047
4048 // Signed Saturating Doubling Multiply-Subtract Long
4049 defm SQDMLSL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1011, "sqdmlsl">;
4050 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlsl,
4051                                             SQDMLSLshh, SQDMLSLdss>;
4052
4053 // Signed Saturating Doubling Multiply Long
4054 defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">;
4055 defm : Neon_Scalar3Diff_HS_size_patterns<int_aarch64_neon_vqdmull,
4056                                          SQDMULLshh, SQDMULLdss>;
4057
4058 // Scalar Signed Integer Convert To Floating-point
4059 defm SCVTF  : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">;
4060 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_s32,
4061                                                  int_aarch64_neon_vcvtf64_s64,
4062                                                  SCVTFss, SCVTFdd>;
4063
4064 // Scalar Unsigned Integer Convert To Floating-point
4065 defm UCVTF  : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11101, "ucvtf">;
4066 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_u32,
4067                                                  int_aarch64_neon_vcvtf64_u64,
4068                                                  UCVTFss, UCVTFdd>;
4069
4070 // Scalar Floating-point Reciprocal Estimate
4071 defm FRECPE : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11101, "frecpe">;
4072 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrecpe,
4073                                              FRECPEss, FRECPEdd>;
4074
4075 // Scalar Floating-point Reciprocal Exponent
4076 defm FRECPX : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11111, "frecpx">;
4077 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpx,
4078                                              FRECPXss, FRECPXdd>;
4079
4080 // Scalar Floating-point Reciprocal Square Root Estimate
4081 defm FRSQRTE: NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11101, "frsqrte">;
4082 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrsqrte,
4083                                              FRSQRTEss, FRSQRTEdd>;
4084
4085 // Scalar Integer Compare
4086
4087 // Scalar Compare Bitwise Equal
4088 def CMEQddd: NeonI_Scalar3Same_D_size<0b1, 0b10001, "cmeq">;
4089 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vceq, CMEQddd>;
4090
4091 // Scalar Compare Signed Greather Than Or Equal
4092 def CMGEddd: NeonI_Scalar3Same_D_size<0b0, 0b00111, "cmge">;
4093 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcge, CMGEddd>;
4094
4095 // Scalar Compare Unsigned Higher Or Same
4096 def CMHSddd: NeonI_Scalar3Same_D_size<0b1, 0b00111, "cmhs">;
4097 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchs, CMHSddd>;
4098
4099 // Scalar Compare Unsigned Higher
4100 def CMHIddd: NeonI_Scalar3Same_D_size<0b1, 0b00110, "cmhi">;
4101 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchi, CMHIddd>;
4102
4103 // Scalar Compare Signed Greater Than
4104 def CMGTddd: NeonI_Scalar3Same_D_size<0b0, 0b00110, "cmgt">;
4105 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcgt, CMGTddd>;
4106
4107 // Scalar Compare Bitwise Test Bits
4108 def CMTSTddd: NeonI_Scalar3Same_D_size<0b0, 0b10001, "cmtst">;
4109 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vtstd, CMTSTddd>;
4110
4111 // Scalar Compare Bitwise Equal To Zero
4112 def CMEQddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01001, "cmeq">;
4113 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vceq,
4114                                                 CMEQddi>;
4115
4116 // Scalar Compare Signed Greather Than Or Equal To Zero
4117 def CMGEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01000, "cmge">;
4118 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcge,
4119                                                 CMGEddi>;
4120
4121 // Scalar Compare Signed Greater Than Zero
4122 def CMGTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01000, "cmgt">;
4123 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcgt,
4124                                                 CMGTddi>;
4125
4126 // Scalar Compare Signed Less Than Or Equal To Zero
4127 def CMLEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01001, "cmle">;
4128 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vclez,
4129                                                 CMLEddi>;
4130
4131 // Scalar Compare Less Than Zero
4132 def CMLTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01010, "cmlt">;
4133 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcltz,
4134                                                 CMLTddi>;
4135
4136 // Scalar Floating-point Compare
4137
4138 // Scalar Floating-point Compare Mask Equal
4139 defm FCMEQ: NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11100, "fcmeq">;
4140 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vceq,
4141                                              FCMEQsss, FCMEQddd>;
4142
4143 // Scalar Floating-point Compare Mask Equal To Zero
4144 defm FCMEQZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01101, "fcmeq">;
4145 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vceq,
4146                                                   FCMEQZssi, FCMEQZddi>;
4147
4148 // Scalar Floating-point Compare Mask Greater Than Or Equal
4149 defm FCMGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11100, "fcmge">;
4150 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcge,
4151                                              FCMGEsss, FCMGEddd>;
4152
4153 // Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
4154 defm FCMGEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01100, "fcmge">;
4155 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcge,
4156                                                   FCMGEZssi, FCMGEZddi>;
4157
4158 // Scalar Floating-point Compare Mask Greather Than
4159 defm FCMGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11100, "fcmgt">;
4160 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcgt,
4161                                              FCMGTsss, FCMGTddd>;
4162
4163 // Scalar Floating-point Compare Mask Greather Than Zero
4164 defm FCMGTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01100, "fcmgt">;
4165 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcgt,
4166                                                   FCMGTZssi, FCMGTZddi>;
4167
4168 // Scalar Floating-point Compare Mask Less Than Or Equal To Zero
4169 defm FCMLEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01101, "fcmle">;
4170 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vclez,
4171                                                   FCMLEZssi, FCMLEZddi>;
4172
4173 // Scalar Floating-point Compare Mask Less Than Zero
4174 defm FCMLTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01110, "fcmlt">;
4175 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcltz,
4176                                                   FCMLTZssi, FCMLTZddi>;
4177
4178 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
4179 defm FACGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11101, "facge">;
4180 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcage,
4181                                              FACGEsss, FACGEddd>;
4182
4183 // Scalar Floating-point Absolute Compare Mask Greater Than
4184 defm FACGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11101, "facgt">;
4185 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcagt,
4186                                              FACGTsss, FACGTddd>;
4187
4188 // Scalar Absolute Value
4189 defm ABS : NeonI_Scalar2SameMisc_D_size<0b0, 0b01011, "abs">;
4190 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vabs, ABSdd>;
4191
4192 // Scalar Signed Saturating Absolute Value
4193 defm SQABS : NeonI_Scalar2SameMisc_BHSD_size<0b0, 0b00111, "sqabs">;
4194 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqabs,
4195                                                SQABSbb, SQABShh, SQABSss, SQABSdd>;
4196
4197 // Scalar Negate
4198 defm NEG : NeonI_Scalar2SameMisc_D_size<0b1, 0b01011, "neg">;
4199 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vneg, NEGdd>;
4200
4201 // Scalar Signed Saturating Negate
4202 defm SQNEG : NeonI_Scalar2SameMisc_BHSD_size<0b1, 0b00111, "sqneg">;
4203 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqneg,
4204                                                SQNEGbb, SQNEGhh, SQNEGss, SQNEGdd>;
4205
4206 // Scalar Signed Saturating Accumulated of Unsigned Value
4207 defm SUQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b0, 0b00011, "suqadd">;
4208 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vuqadd,
4209                                                      SUQADDbb, SUQADDhh,
4210                                                      SUQADDss, SUQADDdd>;
4211
4212 // Scalar Unsigned Saturating Accumulated of Signed Value
4213 defm USQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b1, 0b00011, "usqadd">;
4214 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vsqadd,
4215                                                      USQADDbb, USQADDhh,
4216                                                      USQADDss, USQADDdd>;
4217
4218 // Scalar Signed Saturating Extract Unsigned Narrow
4219 defm SQXTUN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10010, "sqxtun">;
4220 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnsu,
4221                                                      SQXTUNbh, SQXTUNhs,
4222                                                      SQXTUNsd>;
4223
4224 // Scalar Signed Saturating Extract Narrow
4225 defm SQXTN  : NeonI_Scalar2SameMisc_narrow_HSD_size<0b0, 0b10100, "sqxtn">;
4226 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovns,
4227                                                      SQXTNbh, SQXTNhs,
4228                                                      SQXTNsd>;
4229
4230 // Scalar Unsigned Saturating Extract Narrow
4231 defm UQXTN  : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10100, "uqxtn">;
4232 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnu,
4233                                                      UQXTNbh, UQXTNhs,
4234                                                      UQXTNsd>;
4235
4236 // Scalar Reduce Pairwise
4237
4238 multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode,
4239                                      string asmop, bit Commutable = 0> {
4240   let isCommutable = Commutable in {
4241     def _D_2D : NeonI_ScalarPair<u, {size, 0b1}, opcode,
4242                                 (outs FPR64:$Rd), (ins VPR128:$Rn),
4243                                 !strconcat(asmop, "\t$Rd, $Rn.2d"),
4244                                 [],
4245                                 NoItinerary>;
4246   }
4247 }
4248
4249 multiclass NeonI_ScalarPair_SD_sizes<bit u, bit size, bits<5> opcode,
4250                                      string asmop, bit Commutable = 0>
4251   : NeonI_ScalarPair_D_sizes<u, size, opcode, asmop, Commutable> {
4252   let isCommutable = Commutable in {
4253     def _S_2S : NeonI_ScalarPair<u, {size, 0b0}, opcode,
4254                                 (outs FPR32:$Rd), (ins VPR64:$Rn),
4255                                 !strconcat(asmop, "\t$Rd, $Rn.2s"),
4256                                 [],
4257                                 NoItinerary>;
4258   }
4259 }
4260
4261 // Scalar Reduce Addition Pairwise (Integer) with
4262 // Pattern to match llvm.arm.* intrinsic
4263 defm ADDPvv : NeonI_ScalarPair_D_sizes<0b0, 0b1, 0b11011, "addp", 0>;
4264
4265 // Pattern to match llvm.aarch64.* intrinsic for
4266 // Scalar Reduce Addition Pairwise (Integer)
4267 def : Pat<(v1i64 (int_aarch64_neon_vpadd (v2i64 VPR128:$Rn))),
4268           (ADDPvv_D_2D VPR128:$Rn)>;
4269
4270 // Scalar Reduce Addition Pairwise (Floating Point)
4271 defm FADDPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01101, "faddp", 0>;
4272
4273 // Scalar Reduce Maximum Pairwise (Floating Point)
4274 defm FMAXPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01111, "fmaxp", 0>;
4275
4276 // Scalar Reduce Minimum Pairwise (Floating Point)
4277 defm FMINPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01111, "fminp", 0>;
4278
4279 // Scalar Reduce maxNum Pairwise (Floating Point)
4280 defm FMAXNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01100, "fmaxnmp", 0>;
4281
4282 // Scalar Reduce minNum Pairwise (Floating Point)
4283 defm FMINNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01100, "fminnmp", 0>;
4284
4285 multiclass Neon_ScalarPair_SD_size_patterns<SDPatternOperator opnodeS,
4286                                             SDPatternOperator opnodeD,
4287                                             Instruction INSTS,
4288                                             Instruction INSTD> {
4289   def : Pat<(v1f32 (opnodeS (v2f32 VPR64:$Rn))),
4290             (INSTS VPR64:$Rn)>;
4291   def : Pat<(v1f64 (opnodeD (v2f64 VPR128:$Rn))),
4292             (INSTD VPR128:$Rn)>;
4293 }
4294
4295 // Patterns to match llvm.aarch64.* intrinsic for
4296 // Scalar Reduce Add, Max, Min, MaxiNum, MinNum Pairwise (Floating Point)
4297 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfadd,
4298   int_aarch64_neon_vpfaddq, FADDPvv_S_2S, FADDPvv_D_2D>;
4299
4300 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmax,
4301   int_aarch64_neon_vpmaxq, FMAXPvv_S_2S, FMAXPvv_D_2D>;
4302
4303 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmin,
4304   int_aarch64_neon_vpminq, FMINPvv_S_2S, FMINPvv_D_2D>;
4305
4306 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfmaxnm,
4307   int_aarch64_neon_vpfmaxnmq, FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
4308
4309 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfminnm,
4310   int_aarch64_neon_vpfminnmq, FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
4311
4312
4313
4314 //===----------------------------------------------------------------------===//
4315 // Non-Instruction Patterns
4316 //===----------------------------------------------------------------------===//
4317
4318 // 64-bit vector bitcasts...
4319
4320 def : Pat<(v1i64 (bitconvert (v8i8  VPR64:$src))), (v1i64 VPR64:$src)>;
4321 def : Pat<(v2f32 (bitconvert (v8i8  VPR64:$src))), (v2f32 VPR64:$src)>;
4322 def : Pat<(v2i32 (bitconvert (v8i8  VPR64:$src))), (v2i32 VPR64:$src)>;
4323 def : Pat<(v4i16 (bitconvert (v8i8  VPR64:$src))), (v4i16 VPR64:$src)>;
4324
4325 def : Pat<(v1i64 (bitconvert (v4i16  VPR64:$src))), (v1i64 VPR64:$src)>;
4326 def : Pat<(v2i32 (bitconvert (v4i16  VPR64:$src))), (v2i32 VPR64:$src)>;
4327 def : Pat<(v2f32 (bitconvert (v4i16  VPR64:$src))), (v2f32 VPR64:$src)>;
4328 def : Pat<(v8i8  (bitconvert (v4i16  VPR64:$src))), (v8i8 VPR64:$src)>;
4329
4330 def : Pat<(v1i64 (bitconvert (v2i32  VPR64:$src))), (v1i64 VPR64:$src)>;
4331 def : Pat<(v2f32 (bitconvert (v2i32  VPR64:$src))), (v2f32 VPR64:$src)>;
4332 def : Pat<(v4i16 (bitconvert (v2i32  VPR64:$src))), (v4i16 VPR64:$src)>;
4333 def : Pat<(v8i8  (bitconvert (v2i32  VPR64:$src))), (v8i8 VPR64:$src)>;
4334
4335 def : Pat<(v1i64 (bitconvert (v2f32  VPR64:$src))), (v1i64 VPR64:$src)>;
4336 def : Pat<(v2i32 (bitconvert (v2f32  VPR64:$src))), (v2i32 VPR64:$src)>;
4337 def : Pat<(v4i16 (bitconvert (v2f32  VPR64:$src))), (v4i16 VPR64:$src)>;
4338 def : Pat<(v8i8  (bitconvert (v2f32  VPR64:$src))), (v8i8 VPR64:$src)>;
4339
4340 def : Pat<(v2f32 (bitconvert (v1i64  VPR64:$src))), (v2f32 VPR64:$src)>;
4341 def : Pat<(v2i32 (bitconvert (v1i64  VPR64:$src))), (v2i32 VPR64:$src)>;
4342 def : Pat<(v4i16 (bitconvert (v1i64  VPR64:$src))), (v4i16 VPR64:$src)>;
4343 def : Pat<(v8i8  (bitconvert (v1i64  VPR64:$src))), (v8i8 VPR64:$src)>;
4344
4345 // ..and 128-bit vector bitcasts...
4346
4347 def : Pat<(v2f64 (bitconvert (v16i8  VPR128:$src))), (v2f64 VPR128:$src)>;
4348 def : Pat<(v2i64 (bitconvert (v16i8  VPR128:$src))), (v2i64 VPR128:$src)>;
4349 def : Pat<(v4f32 (bitconvert (v16i8  VPR128:$src))), (v4f32 VPR128:$src)>;
4350 def : Pat<(v4i32 (bitconvert (v16i8  VPR128:$src))), (v4i32 VPR128:$src)>;
4351 def : Pat<(v8i16 (bitconvert (v16i8  VPR128:$src))), (v8i16 VPR128:$src)>;
4352
4353 def : Pat<(v2f64 (bitconvert (v8i16  VPR128:$src))), (v2f64 VPR128:$src)>;
4354 def : Pat<(v2i64 (bitconvert (v8i16  VPR128:$src))), (v2i64 VPR128:$src)>;
4355 def : Pat<(v4i32 (bitconvert (v8i16  VPR128:$src))), (v4i32 VPR128:$src)>;
4356 def : Pat<(v4f32 (bitconvert (v8i16  VPR128:$src))), (v4f32 VPR128:$src)>;
4357 def : Pat<(v16i8 (bitconvert (v8i16  VPR128:$src))), (v16i8 VPR128:$src)>;
4358
4359 def : Pat<(v2f64 (bitconvert (v4i32  VPR128:$src))), (v2f64 VPR128:$src)>;
4360 def : Pat<(v2i64 (bitconvert (v4i32  VPR128:$src))), (v2i64 VPR128:$src)>;
4361 def : Pat<(v4f32 (bitconvert (v4i32  VPR128:$src))), (v4f32 VPR128:$src)>;
4362 def : Pat<(v8i16 (bitconvert (v4i32  VPR128:$src))), (v8i16 VPR128:$src)>;
4363 def : Pat<(v16i8 (bitconvert (v4i32  VPR128:$src))), (v16i8 VPR128:$src)>;
4364
4365 def : Pat<(v2f64 (bitconvert (v4f32  VPR128:$src))), (v2f64 VPR128:$src)>;
4366 def : Pat<(v2i64 (bitconvert (v4f32  VPR128:$src))), (v2i64 VPR128:$src)>;
4367 def : Pat<(v4i32 (bitconvert (v4f32  VPR128:$src))), (v4i32 VPR128:$src)>;
4368 def : Pat<(v8i16 (bitconvert (v4f32  VPR128:$src))), (v8i16 VPR128:$src)>;
4369 def : Pat<(v16i8 (bitconvert (v4f32  VPR128:$src))), (v16i8 VPR128:$src)>;
4370
4371 def : Pat<(v2f64 (bitconvert (v2i64  VPR128:$src))), (v2f64 VPR128:$src)>;
4372 def : Pat<(v4f32 (bitconvert (v2i64  VPR128:$src))), (v4f32 VPR128:$src)>;
4373 def : Pat<(v4i32 (bitconvert (v2i64  VPR128:$src))), (v4i32 VPR128:$src)>;
4374 def : Pat<(v8i16 (bitconvert (v2i64  VPR128:$src))), (v8i16 VPR128:$src)>;
4375 def : Pat<(v16i8 (bitconvert (v2i64  VPR128:$src))), (v16i8 VPR128:$src)>;
4376
4377 def : Pat<(v2i64 (bitconvert (v2f64  VPR128:$src))), (v2i64 VPR128:$src)>;
4378 def : Pat<(v4f32 (bitconvert (v2f64  VPR128:$src))), (v4f32 VPR128:$src)>;
4379 def : Pat<(v4i32 (bitconvert (v2f64  VPR128:$src))), (v4i32 VPR128:$src)>;
4380 def : Pat<(v8i16 (bitconvert (v2f64  VPR128:$src))), (v8i16 VPR128:$src)>;
4381 def : Pat<(v16i8 (bitconvert (v2f64  VPR128:$src))), (v16i8 VPR128:$src)>;
4382
4383
4384 // ...and scalar bitcasts...
4385 def : Pat<(f16 (bitconvert (v1i16  FPR16:$src))), (f16 FPR16:$src)>;
4386 def : Pat<(f32 (bitconvert (v1i32  FPR32:$src))), (f32 FPR32:$src)>;
4387 def : Pat<(f64 (bitconvert (v1i64  FPR64:$src))), (f64 FPR64:$src)>;
4388 def : Pat<(f32 (bitconvert (v1f32  FPR32:$src))), (f32 FPR32:$src)>;
4389 def : Pat<(f64 (bitconvert (v1f64  FPR64:$src))), (f64 FPR64:$src)>;
4390
4391 def : Pat<(i64 (bitconvert (v1i64  FPR64:$src))), (FMOVxd $src)>;
4392 def : Pat<(i32 (bitconvert (v1i32  FPR32:$src))), (FMOVws $src)>;
4393
4394 def : Pat<(v8i8  (bitconvert (v1i64  VPR64:$src))), (v8i8 VPR64:$src)>;
4395 def : Pat<(v4i16 (bitconvert (v1i64  VPR64:$src))), (v4i16 VPR64:$src)>;
4396 def : Pat<(v2i32 (bitconvert (v1i64  VPR64:$src))), (v2i32 VPR64:$src)>;
4397
4398 def : Pat<(f64   (bitconvert (v8i8  VPR64:$src))), (f64 VPR64:$src)>;
4399 def : Pat<(f64   (bitconvert (v4i16  VPR64:$src))), (f64 VPR64:$src)>;
4400 def : Pat<(f64   (bitconvert (v2i32  VPR64:$src))), (f64 VPR64:$src)>;
4401 def : Pat<(f64   (bitconvert (v2f32  VPR64:$src))), (f64 VPR64:$src)>;
4402 def : Pat<(f64   (bitconvert (v1i64  VPR64:$src))), (f64 VPR64:$src)>;
4403
4404 def : Pat<(f128  (bitconvert (v16i8  VPR128:$src))), (f128 VPR128:$src)>;
4405 def : Pat<(f128  (bitconvert (v8i16  VPR128:$src))), (f128 VPR128:$src)>;
4406 def : Pat<(f128  (bitconvert (v4i32  VPR128:$src))), (f128 VPR128:$src)>;
4407 def : Pat<(f128  (bitconvert (v2i64  VPR128:$src))), (f128 VPR128:$src)>;
4408 def : Pat<(f128  (bitconvert (v4f32  VPR128:$src))), (f128 VPR128:$src)>;
4409 def : Pat<(f128  (bitconvert (v2f64  VPR128:$src))), (f128 VPR128:$src)>;
4410
4411 def : Pat<(v1i16 (bitconvert (f16  FPR16:$src))), (v1i16 FPR16:$src)>;
4412 def : Pat<(v1i32 (bitconvert (f32  FPR32:$src))), (v1i32 FPR32:$src)>;
4413 def : Pat<(v1i64 (bitconvert (f64  FPR64:$src))), (v1i64 FPR64:$src)>;
4414 def : Pat<(v1f32 (bitconvert (f32  FPR32:$src))), (v1f32 FPR32:$src)>;
4415 def : Pat<(v1f64 (bitconvert (f64  FPR64:$src))), (v1f64 FPR64:$src)>;
4416
4417 def : Pat<(v1i64 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
4418 def : Pat<(v1i32 (bitconvert (i32  GPR32:$src))), (FMOVsw $src)>;
4419
4420 def : Pat<(v8i8   (bitconvert (f64   FPR64:$src))), (v8i8 FPR64:$src)>;
4421 def : Pat<(v4i16  (bitconvert (f64   FPR64:$src))), (v4i16 FPR64:$src)>;
4422 def : Pat<(v2i32  (bitconvert (f64   FPR64:$src))), (v2i32 FPR64:$src)>;
4423 def : Pat<(v2f32  (bitconvert (f64   FPR64:$src))), (v2f32 FPR64:$src)>;
4424 def : Pat<(v1i64  (bitconvert (f64   FPR64:$src))), (v1i64 FPR64:$src)>;
4425
4426 def : Pat<(v16i8  (bitconvert (f128   FPR128:$src))), (v16i8 FPR128:$src)>;
4427 def : Pat<(v8i16  (bitconvert (f128   FPR128:$src))), (v8i16 FPR128:$src)>;
4428 def : Pat<(v4i32  (bitconvert (f128   FPR128:$src))), (v4i32 FPR128:$src)>;
4429 def : Pat<(v2i64  (bitconvert (f128   FPR128:$src))), (v2i64 FPR128:$src)>;
4430 def : Pat<(v4f32  (bitconvert (f128   FPR128:$src))), (v4f32 FPR128:$src)>;
4431 def : Pat<(v2f64  (bitconvert (f128   FPR128:$src))), (v2f64 FPR128:$src)>;
4432
4433 def neon_uimm0_bare : Operand<i64>,
4434                         ImmLeaf<i64, [{return Imm == 0;}]> {
4435   let ParserMatchClass = neon_uimm0_asmoperand;
4436   let PrintMethod = "printUImmBareOperand";
4437 }
4438
4439 def neon_uimm1_bare : Operand<i64>,
4440                         ImmLeaf<i64, [{(void)Imm; return true;}]> {
4441   let ParserMatchClass = neon_uimm1_asmoperand;
4442   let PrintMethod = "printUImmBareOperand";
4443 }
4444
4445 def neon_uimm2_bare : Operand<i64>,
4446                         ImmLeaf<i64, [{(void)Imm; return true;}]> {
4447   let ParserMatchClass = neon_uimm2_asmoperand;
4448   let PrintMethod = "printUImmBareOperand";
4449 }
4450
4451 def neon_uimm3_bare : Operand<i64>,
4452                         ImmLeaf<i64, [{(void)Imm; return true;}]> {
4453   let ParserMatchClass = uimm3_asmoperand;
4454   let PrintMethod = "printUImmBareOperand";
4455 }
4456
4457 def neon_uimm4_bare : Operand<i64>,
4458                         ImmLeaf<i64, [{(void)Imm; return true;}]> {
4459   let ParserMatchClass = uimm4_asmoperand;
4460   let PrintMethod = "printUImmBareOperand";
4461 }
4462
4463 def neon_uimm3 : Operand<i64>,
4464                    ImmLeaf<i64, [{(void)Imm; return true;}]> {
4465   let ParserMatchClass = uimm3_asmoperand;
4466   let PrintMethod = "printUImmHexOperand";
4467 }
4468
4469 def neon_uimm4 : Operand<i64>,
4470                    ImmLeaf<i64, [{(void)Imm; return true;}]> {
4471   let ParserMatchClass = uimm4_asmoperand;
4472   let PrintMethod = "printUImmHexOperand";
4473 }
4474
4475 class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
4476                      RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
4477   : NeonI_copy<0b1, 0b0, 0b0011,
4478                (outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
4479                asmop # "\t$Rd." # Res # "[$Imm], $Rn",
4480                [(set (ResTy VPR128:$Rd),
4481                  (ResTy (vector_insert
4482                    (ResTy VPR128:$src),
4483                    (OpTy OpGPR:$Rn),
4484                    (OpImm:$Imm))))],
4485                NoItinerary> {
4486   bits<4> Imm;
4487   let Constraints = "$src = $Rd";
4488 }
4489
4490 // Bitwise Extract
4491 class NeonI_Extract<bit q, bits<2> op2, string asmop,
4492                     string OpS, RegisterOperand OpVPR, Operand OpImm>
4493   : NeonI_BitExtract<q, op2, (outs OpVPR:$Rd),
4494                      (ins OpVPR:$Rn, OpVPR:$Rm, OpImm:$Index),
4495                      asmop # "\t$Rd." # OpS # ", $Rn." # OpS #
4496                      ", $Rm." # OpS # ", $Index",
4497                      [],
4498                      NoItinerary>{
4499   bits<4> Index;
4500 }
4501
4502 def EXTvvvi_8b : NeonI_Extract<0b0, 0b00, "ext", "8b",
4503                                VPR64, neon_uimm3> {
4504   let Inst{14-11} = {0b0, Index{2}, Index{1}, Index{0}};
4505 }
4506
4507 def EXTvvvi_16b: NeonI_Extract<0b1, 0b00, "ext", "16b",
4508                                VPR128, neon_uimm4> {
4509   let Inst{14-11} = Index;
4510 }
4511
4512 class NI_Extract<ValueType OpTy, RegisterOperand OpVPR, Instruction INST,
4513                  Operand OpImm>
4514   : Pat<(OpTy (Neon_vextract (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm),
4515                                  (i64 OpImm:$Imm))),
4516               (INST OpVPR:$Rn, OpVPR:$Rm, OpImm:$Imm)>;
4517
4518 def : NI_Extract<v8i8,  VPR64,  EXTvvvi_8b,  neon_uimm3>;
4519 def : NI_Extract<v4i16, VPR64,  EXTvvvi_8b,  neon_uimm3>;
4520 def : NI_Extract<v2i32, VPR64,  EXTvvvi_8b,  neon_uimm3>;
4521 def : NI_Extract<v1i64, VPR64,  EXTvvvi_8b,  neon_uimm3>;
4522 def : NI_Extract<v2f32, VPR64,  EXTvvvi_8b,  neon_uimm3>;
4523 def : NI_Extract<v1f64, VPR64,  EXTvvvi_8b,  neon_uimm3>;
4524 def : NI_Extract<v16i8, VPR128, EXTvvvi_16b, neon_uimm4>;
4525 def : NI_Extract<v8i16, VPR128, EXTvvvi_16b, neon_uimm4>;
4526 def : NI_Extract<v4i32, VPR128, EXTvvvi_16b, neon_uimm4>;
4527 def : NI_Extract<v2i64, VPR128, EXTvvvi_16b, neon_uimm4>;
4528 def : NI_Extract<v4f32, VPR128, EXTvvvi_16b, neon_uimm4>;
4529 def : NI_Extract<v2f64, VPR128, EXTvvvi_16b, neon_uimm4>;
4530
4531 // The followings are for instruction class (3V Elem)
4532
4533 // Variant 1
4534
4535 class NI_2VE<bit q, bit u, bits<2> size, bits<4> opcode,
4536              string asmop, string ResS, string OpS, string EleOpS,
4537              Operand OpImm, RegisterOperand ResVPR,
4538              RegisterOperand OpVPR, RegisterOperand EleOpVPR>
4539   : NeonI_2VElem<q, u, size, opcode,
4540                  (outs ResVPR:$Rd), (ins ResVPR:$src, OpVPR:$Rn,
4541                                          EleOpVPR:$Re, OpImm:$Index),
4542                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
4543                  ", $Re." # EleOpS # "[$Index]",
4544                  [],
4545                  NoItinerary> {
4546   bits<3> Index;
4547   bits<5> Re;
4548
4549   let Constraints = "$src = $Rd";
4550 }
4551
4552 multiclass NI_2VE_v1<bit u, bits<4> opcode, string asmop> {
4553   // vector register class for element is always 128-bit to cover the max index
4554   def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
4555                      neon_uimm2_bare, VPR64, VPR64, VPR128> {
4556     let Inst{11} = {Index{1}};
4557     let Inst{21} = {Index{0}};
4558     let Inst{20-16} = Re;
4559   }
4560
4561   def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
4562                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
4563     let Inst{11} = {Index{1}};
4564     let Inst{21} = {Index{0}};
4565     let Inst{20-16} = Re;
4566   }
4567
4568   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
4569   def _4h8h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
4570                      neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
4571     let Inst{11} = {Index{2}};
4572     let Inst{21} = {Index{1}};
4573     let Inst{20} = {Index{0}};
4574     let Inst{19-16} = Re{3-0};
4575   }
4576
4577   def _8h8h : NI_2VE<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
4578                      neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
4579     let Inst{11} = {Index{2}};
4580     let Inst{21} = {Index{1}};
4581     let Inst{20} = {Index{0}};
4582     let Inst{19-16} = Re{3-0};
4583   }
4584 }
4585
4586 defm MLAvve : NI_2VE_v1<0b1, 0b0000, "mla">;
4587 defm MLSvve : NI_2VE_v1<0b1, 0b0100, "mls">;
4588
4589 // Pattern for lane in 128-bit vector
4590 class NI_2VE_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
4591                    RegisterOperand ResVPR, RegisterOperand OpVPR,
4592                    RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
4593                    ValueType EleOpTy, SDPatternOperator coreop>
4594   : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
4595           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
4596         (INST ResVPR:$src, OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
4597
4598 // Pattern for lane in 64-bit vector
4599 class NI_2VE_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
4600                   RegisterOperand ResVPR, RegisterOperand OpVPR,
4601                   RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
4602                   ValueType EleOpTy, SDPatternOperator coreop>
4603   : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
4604           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
4605         (INST ResVPR:$src, OpVPR:$Rn,
4606           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
4607
4608 multiclass NI_2VE_v1_pat<string subop, SDPatternOperator op>
4609 {
4610   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
4611                      op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32,
4612                      BinOpFrag<(Neon_vduplane
4613                                  (Neon_low4S node:$LHS), node:$RHS)>>;
4614
4615   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
4616                      op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32,
4617                      BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4618
4619   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
4620                      op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16,
4621                      BinOpFrag<(Neon_vduplane
4622                                  (Neon_low8H node:$LHS), node:$RHS)>>;
4623
4624   def : NI_2VE_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
4625                      op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16,
4626                      BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4627
4628   // Index can only be half of the max value for lane in 64-bit vector
4629
4630   def : NI_2VE_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
4631                     op, VPR64, VPR64, VPR64, v2i32, v2i32, v2i32,
4632                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4633
4634   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4s"), neon_uimm1_bare,
4635                     op, VPR128, VPR128, VPR64, v4i32, v4i32, v2i32,
4636                     BinOpFrag<(Neon_vduplane
4637                                 (Neon_combine_4S node:$LHS, undef),
4638                                  node:$RHS)>>;
4639
4640   def : NI_2VE_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
4641                     op, VPR64, VPR64, VPR64Lo, v4i16, v4i16, v4i16,
4642                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4643
4644   def : NI_2VE_lane<!cast<Instruction>(subop # "_8h8h"), neon_uimm2_bare,
4645                     op, VPR128, VPR128, VPR64Lo, v8i16, v8i16, v4i16,
4646                     BinOpFrag<(Neon_vduplane
4647                                 (Neon_combine_8H node:$LHS, undef),
4648                                 node:$RHS)>>;
4649 }
4650
4651 defm MLA_lane_v1 : NI_2VE_v1_pat<"MLAvve", Neon_mla>;
4652 defm MLS_lane_v1 : NI_2VE_v1_pat<"MLSvve", Neon_mls>;
4653
4654 class NI_2VE_2op<bit q, bit u, bits<2> size, bits<4> opcode,
4655                  string asmop, string ResS, string OpS, string EleOpS,
4656                  Operand OpImm, RegisterOperand ResVPR,
4657                  RegisterOperand OpVPR, RegisterOperand EleOpVPR>
4658   : NeonI_2VElem<q, u, size, opcode,
4659                  (outs ResVPR:$Rd), (ins OpVPR:$Rn,
4660                                          EleOpVPR:$Re, OpImm:$Index),
4661                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
4662                  ", $Re." # EleOpS # "[$Index]",
4663                  [],
4664                  NoItinerary> {
4665   bits<3> Index;
4666   bits<5> Re;
4667 }
4668
4669 multiclass NI_2VE_v1_2op<bit u, bits<4> opcode, string asmop> {
4670   // vector register class for element is always 128-bit to cover the max index
4671   def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
4672                          neon_uimm2_bare, VPR64, VPR64, VPR128> {
4673     let Inst{11} = {Index{1}};
4674     let Inst{21} = {Index{0}};
4675     let Inst{20-16} = Re;
4676   }
4677
4678   def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
4679                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
4680     let Inst{11} = {Index{1}};
4681     let Inst{21} = {Index{0}};
4682     let Inst{20-16} = Re;
4683   }
4684
4685   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
4686   def _4h8h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
4687                          neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
4688     let Inst{11} = {Index{2}};
4689     let Inst{21} = {Index{1}};
4690     let Inst{20} = {Index{0}};
4691     let Inst{19-16} = Re{3-0};
4692   }
4693
4694   def _8h8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
4695                          neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
4696     let Inst{11} = {Index{2}};
4697     let Inst{21} = {Index{1}};
4698     let Inst{20} = {Index{0}};
4699     let Inst{19-16} = Re{3-0};
4700   }
4701 }
4702
4703 defm MULve : NI_2VE_v1_2op<0b0, 0b1000, "mul">;
4704 defm SQDMULHve : NI_2VE_v1_2op<0b0, 0b1100, "sqdmulh">;
4705 defm SQRDMULHve : NI_2VE_v1_2op<0b0, 0b1101, "sqrdmulh">;
4706
4707 // Pattern for lane in 128-bit vector
4708 class NI_2VE_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
4709                        RegisterOperand OpVPR, RegisterOperand EleOpVPR,
4710                        ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
4711                        SDPatternOperator coreop>
4712   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
4713           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
4714         (INST OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
4715
4716 // Pattern for lane in 64-bit vector
4717 class NI_2VE_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
4718                       RegisterOperand OpVPR, RegisterOperand EleOpVPR,
4719                       ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
4720                       SDPatternOperator coreop>
4721   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
4722           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
4723         (INST OpVPR:$Rn,
4724           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
4725
4726 multiclass NI_2VE_mul_v1_pat<string subop, SDPatternOperator op> {
4727   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
4728                          op, VPR64, VPR128, v2i32, v2i32, v4i32,
4729                          BinOpFrag<(Neon_vduplane
4730                                      (Neon_low4S node:$LHS), node:$RHS)>>;
4731
4732   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
4733                          op, VPR128, VPR128, v4i32, v4i32, v4i32,
4734                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4735
4736   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
4737                          op, VPR64, VPR128Lo, v4i16, v4i16, v8i16,
4738                          BinOpFrag<(Neon_vduplane
4739                                     (Neon_low8H node:$LHS), node:$RHS)>>;
4740
4741   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
4742                          op, VPR128, VPR128Lo, v8i16, v8i16, v8i16,
4743                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4744
4745   // Index can only be half of the max value for lane in 64-bit vector
4746
4747   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
4748                         op, VPR64, VPR64, v2i32, v2i32, v2i32,
4749                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4750
4751   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4s"), neon_uimm1_bare,
4752                         op, VPR128, VPR64, v4i32, v4i32, v2i32,
4753                         BinOpFrag<(Neon_vduplane
4754                                     (Neon_combine_4S node:$LHS, undef),
4755                                      node:$RHS)>>;
4756
4757   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
4758                         op, VPR64, VPR64Lo, v4i16, v4i16, v4i16,
4759                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4760
4761   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_8h8h"), neon_uimm2_bare,
4762                         op, VPR128, VPR64Lo, v8i16, v8i16, v4i16,
4763                         BinOpFrag<(Neon_vduplane
4764                                     (Neon_combine_8H node:$LHS, undef),
4765                                     node:$RHS)>>;
4766 }
4767
4768 defm MUL_lane_v1 : NI_2VE_mul_v1_pat<"MULve", mul>;
4769 defm SQDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQDMULHve", int_arm_neon_vqdmulh>;
4770 defm SQRDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQRDMULHve", int_arm_neon_vqrdmulh>;
4771
4772 // Variant 2
4773
4774 multiclass NI_2VE_v2_2op<bit u, bits<4> opcode, string asmop> {
4775   // vector register class for element is always 128-bit to cover the max index
4776   def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
4777                          neon_uimm2_bare, VPR64, VPR64, VPR128> {
4778     let Inst{11} = {Index{1}};
4779     let Inst{21} = {Index{0}};
4780     let Inst{20-16} = Re;
4781   }
4782
4783   def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
4784                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
4785     let Inst{11} = {Index{1}};
4786     let Inst{21} = {Index{0}};
4787     let Inst{20-16} = Re;
4788   }
4789
4790   // _1d2d doesn't exist!
4791
4792   def _2d2d : NI_2VE_2op<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
4793                          neon_uimm1_bare, VPR128, VPR128, VPR128> {
4794     let Inst{11} = {Index{0}};
4795     let Inst{21} = 0b0;
4796     let Inst{20-16} = Re;
4797   }
4798 }
4799
4800 defm FMULve : NI_2VE_v2_2op<0b0, 0b1001, "fmul">;
4801 defm FMULXve : NI_2VE_v2_2op<0b1, 0b1001, "fmulx">;
4802
4803 class NI_2VE_mul_lane_2d<Instruction INST, Operand OpImm, SDPatternOperator op,
4804                          RegisterOperand OpVPR, RegisterOperand EleOpVPR,
4805                          ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
4806                          SDPatternOperator coreop>
4807   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
4808           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (EleOpTy EleOpVPR:$Re))))),
4809         (INST OpVPR:$Rn,
4810           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), 0)>;
4811
4812 multiclass NI_2VE_mul_v2_pat<string subop, SDPatternOperator op> {
4813   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
4814                          op, VPR64, VPR128, v2f32, v2f32, v4f32,
4815                          BinOpFrag<(Neon_vduplane
4816                                      (Neon_low4f node:$LHS), node:$RHS)>>;
4817
4818   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
4819                          op, VPR128, VPR128, v4f32, v4f32, v4f32,
4820                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4821
4822   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
4823                          op, VPR128, VPR128, v2f64, v2f64, v2f64,
4824                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4825
4826   // Index can only be half of the max value for lane in 64-bit vector
4827
4828   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
4829                         op, VPR64, VPR64, v2f32, v2f32, v2f32,
4830                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4831
4832   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4s"), neon_uimm1_bare,
4833                         op, VPR128, VPR64, v4f32, v4f32, v2f32,
4834                         BinOpFrag<(Neon_vduplane
4835                                     (Neon_combine_4f node:$LHS, undef),
4836                                     node:$RHS)>>;
4837
4838   def : NI_2VE_mul_lane_2d<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
4839                            op, VPR128, VPR64, v2f64, v2f64, v1f64,
4840                            BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
4841 }
4842
4843 defm FMUL_lane_v2 : NI_2VE_mul_v2_pat<"FMULve", fmul>;
4844 defm FMULX_lane_v2 : NI_2VE_mul_v2_pat<"FMULXve", int_aarch64_neon_vmulx>;
4845
4846 // The followings are patterns using fma
4847 // -ffp-contract=fast generates fma
4848
4849 multiclass NI_2VE_v2<bit u, bits<4> opcode, string asmop> {
4850   // vector register class for element is always 128-bit to cover the max index
4851   def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
4852                      neon_uimm2_bare, VPR64, VPR64, VPR128> {
4853     let Inst{11} = {Index{1}};
4854     let Inst{21} = {Index{0}};
4855     let Inst{20-16} = Re;
4856   }
4857
4858   def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
4859                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
4860     let Inst{11} = {Index{1}};
4861     let Inst{21} = {Index{0}};
4862     let Inst{20-16} = Re;
4863   }
4864
4865   // _1d2d doesn't exist!
4866
4867   def _2d2d : NI_2VE<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
4868                      neon_uimm1_bare, VPR128, VPR128, VPR128> {
4869     let Inst{11} = {Index{0}};
4870     let Inst{21} = 0b0;
4871     let Inst{20-16} = Re;
4872   }
4873 }
4874
4875 defm FMLAvve : NI_2VE_v2<0b0, 0b0001, "fmla">;
4876 defm FMLSvve : NI_2VE_v2<0b0, 0b0101, "fmls">;
4877
4878 // Pattern for lane in 128-bit vector
4879 class NI_2VEswap_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
4880                        RegisterOperand ResVPR, RegisterOperand OpVPR,
4881                        ValueType ResTy, ValueType OpTy,
4882                        SDPatternOperator coreop>
4883   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
4884                    (ResTy ResVPR:$src), (ResTy ResVPR:$Rn))),
4885         (INST ResVPR:$src, ResVPR:$Rn, OpVPR:$Re, OpImm:$Index)>;
4886
4887 // Pattern for lane in 64-bit vector
4888 class NI_2VEswap_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
4889                       RegisterOperand ResVPR, RegisterOperand OpVPR,
4890                       ValueType ResTy, ValueType OpTy,
4891                       SDPatternOperator coreop>
4892   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
4893                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
4894         (INST ResVPR:$src, ResVPR:$Rn,
4895           (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), OpImm:$Index)>;
4896
4897 // Pattern for lane in 64-bit vector
4898 class NI_2VEswap_lane_2d2d<Instruction INST, Operand OpImm,
4899                            SDPatternOperator op,
4900                            RegisterOperand ResVPR, RegisterOperand OpVPR,
4901                            ValueType ResTy, ValueType OpTy,
4902                            SDPatternOperator coreop>
4903   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (OpTy OpVPR:$Re))),
4904                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
4905         (INST ResVPR:$src, ResVPR:$Rn,
4906           (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), 0)>;
4907
4908
4909 multiclass NI_2VE_fma_v2_pat<string subop, SDPatternOperator op> {
4910   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
4911                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
4912                          BinOpFrag<(Neon_vduplane
4913                                      (Neon_low4f node:$LHS), node:$RHS)>>;
4914
4915   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
4916                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
4917                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4918
4919   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
4920                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
4921                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4922
4923   // Index can only be half of the max value for lane in 64-bit vector
4924
4925   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
4926                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
4927                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4928
4929   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
4930                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
4931                         BinOpFrag<(Neon_vduplane
4932                                     (Neon_combine_4f node:$LHS, undef),
4933                                     node:$RHS)>>;
4934
4935   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
4936                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
4937                              BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
4938 }
4939
4940 defm FMLA_lane_v2_s : NI_2VE_fma_v2_pat<"FMLAvve", fma>;
4941
4942 multiclass NI_2VE_fms_v2_pat<string subop, SDPatternOperator op>
4943 {
4944   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
4945                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
4946                          BinOpFrag<(fneg (Neon_vduplane
4947                                      (Neon_low4f node:$LHS), node:$RHS))>>;
4948
4949   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
4950                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
4951                          BinOpFrag<(Neon_vduplane
4952                                      (Neon_low4f (fneg node:$LHS)),
4953                                      node:$RHS)>>;
4954
4955   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
4956                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
4957                          BinOpFrag<(fneg (Neon_vduplane
4958                                      node:$LHS, node:$RHS))>>;
4959
4960   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
4961                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
4962                          BinOpFrag<(Neon_vduplane
4963                                      (fneg node:$LHS), node:$RHS)>>;
4964
4965   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
4966                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
4967                          BinOpFrag<(fneg (Neon_vduplane
4968                                      node:$LHS, node:$RHS))>>;
4969
4970   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
4971                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
4972                          BinOpFrag<(Neon_vduplane
4973                                      (fneg node:$LHS), node:$RHS)>>;
4974
4975   // Index can only be half of the max value for lane in 64-bit vector
4976
4977   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
4978                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
4979                         BinOpFrag<(fneg (Neon_vduplane
4980                                     node:$LHS, node:$RHS))>>;
4981
4982   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
4983                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
4984                         BinOpFrag<(Neon_vduplane
4985                                     (fneg node:$LHS), node:$RHS)>>;
4986
4987   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
4988                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
4989                         BinOpFrag<(fneg (Neon_vduplane
4990                                     (Neon_combine_4f node:$LHS, undef),
4991                                     node:$RHS))>>;
4992
4993   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
4994                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
4995                         BinOpFrag<(Neon_vduplane
4996                                     (Neon_combine_4f (fneg node:$LHS), undef),
4997                                     node:$RHS)>>;
4998
4999   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
5000                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
5001                              BinOpFrag<(fneg (Neon_combine_2d
5002                                          node:$LHS, node:$RHS))>>;
5003
5004   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
5005                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
5006                              BinOpFrag<(Neon_combine_2d
5007                                          (fneg node:$LHS), (fneg node:$RHS))>>;
5008 }
5009
5010 defm FMLS_lane_v2_s : NI_2VE_fms_v2_pat<"FMLSvve", fma>;
5011
5012 // Variant 3: Long type
5013 // E.g. SMLAL : 4S/4H/H (v0-v15), 2D/2S/S
5014 //      SMLAL2: 4S/8H/H (v0-v15), 2D/4S/S
5015
5016 multiclass NI_2VE_v3<bit u, bits<4> opcode, string asmop> {
5017   // vector register class for element is always 128-bit to cover the max index
5018   def _2d2s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
5019                      neon_uimm2_bare, VPR128, VPR64, VPR128> {
5020     let Inst{11} = {Index{1}};
5021     let Inst{21} = {Index{0}};
5022     let Inst{20-16} = Re;
5023   }
5024
5025   def _2d4s : NI_2VE<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
5026                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
5027     let Inst{11} = {Index{1}};
5028     let Inst{21} = {Index{0}};
5029     let Inst{20-16} = Re;
5030   }
5031
5032   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
5033   def _4s8h : NI_2VE<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
5034                      neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
5035     let Inst{11} = {Index{2}};
5036     let Inst{21} = {Index{1}};
5037     let Inst{20} = {Index{0}};
5038     let Inst{19-16} = Re{3-0};
5039   }
5040
5041   def _4s4h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
5042                      neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
5043     let Inst{11} = {Index{2}};
5044     let Inst{21} = {Index{1}};
5045     let Inst{20} = {Index{0}};
5046     let Inst{19-16} = Re{3-0};
5047   }
5048 }
5049
5050 defm SMLALvve : NI_2VE_v3<0b0, 0b0010, "smlal">;
5051 defm UMLALvve : NI_2VE_v3<0b1, 0b0010, "umlal">;
5052 defm SMLSLvve : NI_2VE_v3<0b0, 0b0110, "smlsl">;
5053 defm UMLSLvve : NI_2VE_v3<0b1, 0b0110, "umlsl">;
5054 defm SQDMLALvve : NI_2VE_v3<0b0, 0b0011, "sqdmlal">;
5055 defm SQDMLSLvve : NI_2VE_v3<0b0, 0b0111, "sqdmlsl">;
5056
5057 multiclass NI_2VE_v3_2op<bit u, bits<4> opcode, string asmop> {
5058   // vector register class for element is always 128-bit to cover the max index
5059   def _2d2s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
5060                          neon_uimm2_bare, VPR128, VPR64, VPR128> {
5061     let Inst{11} = {Index{1}};
5062     let Inst{21} = {Index{0}};
5063     let Inst{20-16} = Re;
5064   }
5065
5066   def _2d4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
5067                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
5068     let Inst{11} = {Index{1}};
5069     let Inst{21} = {Index{0}};
5070     let Inst{20-16} = Re;
5071   }
5072
5073   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
5074   def _4s8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
5075                          neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
5076     let Inst{11} = {Index{2}};
5077     let Inst{21} = {Index{1}};
5078     let Inst{20} = {Index{0}};
5079     let Inst{19-16} = Re{3-0};
5080   }
5081
5082   def _4s4h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
5083                          neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
5084     let Inst{11} = {Index{2}};
5085     let Inst{21} = {Index{1}};
5086     let Inst{20} = {Index{0}};
5087     let Inst{19-16} = Re{3-0};
5088   }
5089 }
5090
5091 defm SMULLve : NI_2VE_v3_2op<0b0, 0b1010, "smull">;
5092 defm UMULLve : NI_2VE_v3_2op<0b1, 0b1010, "umull">;
5093 defm SQDMULLve : NI_2VE_v3_2op<0b0, 0b1011, "sqdmull">;
5094
5095 // Pattern for lane in 128-bit vector
5096 class NI_2VEL2_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
5097                      RegisterOperand EleOpVPR, ValueType ResTy,
5098                      ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
5099                      SDPatternOperator hiop, SDPatternOperator coreop>
5100   : Pat<(ResTy (op (ResTy VPR128:$src),
5101           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
5102           (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
5103         (INST VPR128:$src, VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
5104
5105 // Pattern for lane in 64-bit vector
5106 class NI_2VEL2_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
5107                     RegisterOperand EleOpVPR, ValueType ResTy,
5108                     ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
5109                     SDPatternOperator hiop, SDPatternOperator coreop>
5110   : Pat<(ResTy (op (ResTy VPR128:$src),
5111           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
5112           (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
5113         (INST VPR128:$src, VPR128:$Rn,
5114           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
5115
5116 multiclass NI_2VEL_v3_pat<string subop, SDPatternOperator op> {
5117   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
5118                      op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16,
5119                      BinOpFrag<(Neon_vduplane
5120                                  (Neon_low8H node:$LHS), node:$RHS)>>;
5121
5122   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
5123                      op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32,
5124                      BinOpFrag<(Neon_vduplane
5125                                  (Neon_low4S node:$LHS), node:$RHS)>>;
5126
5127   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
5128                        op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H,
5129                        BinOpFrag<(Neon_vduplane
5130                                    (Neon_low8H node:$LHS), node:$RHS)>>;
5131
5132   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
5133                        op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S,
5134                        BinOpFrag<(Neon_vduplane
5135                                    (Neon_low4S node:$LHS), node:$RHS)>>;
5136
5137   // Index can only be half of the max value for lane in 64-bit vector
5138
5139   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
5140                     op, VPR128, VPR64, VPR64Lo, v4i32, v4i16, v4i16,
5141                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5142
5143   def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
5144                     op, VPR128, VPR64, VPR64, v2i64, v2i32, v2i32,
5145                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5146
5147   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
5148                       op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H,
5149                       BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5150
5151   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
5152                       op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S,
5153                       BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5154 }
5155
5156 defm SMLAL_lane_v3 : NI_2VEL_v3_pat<"SMLALvve", Neon_smlal>;
5157 defm UMLAL_lane_v3 : NI_2VEL_v3_pat<"UMLALvve", Neon_umlal>;
5158 defm SMLSL_lane_v3 : NI_2VEL_v3_pat<"SMLSLvve", Neon_smlsl>;
5159 defm UMLSL_lane_v3 : NI_2VEL_v3_pat<"UMLSLvve", Neon_umlsl>;
5160
5161 // Pattern for lane in 128-bit vector
5162 class NI_2VEL2_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
5163                          RegisterOperand EleOpVPR, ValueType ResTy,
5164                          ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
5165                          SDPatternOperator hiop, SDPatternOperator coreop>
5166   : Pat<(ResTy (op
5167           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
5168           (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
5169         (INST VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
5170
5171 // Pattern for lane in 64-bit vector
5172 class NI_2VEL2_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
5173                         RegisterOperand EleOpVPR, ValueType ResTy,
5174                         ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
5175                         SDPatternOperator hiop, SDPatternOperator coreop>
5176   : Pat<(ResTy (op
5177           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
5178           (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
5179         (INST VPR128:$Rn,
5180           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
5181
5182 multiclass NI_2VEL_mul_v3_pat<string subop, SDPatternOperator op> {
5183   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
5184                          op, VPR64, VPR128Lo, v4i32, v4i16, v8i16,
5185                          BinOpFrag<(Neon_vduplane
5186                                      (Neon_low8H node:$LHS), node:$RHS)>>;
5187
5188   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
5189                          op, VPR64, VPR128, v2i64, v2i32, v4i32,
5190                          BinOpFrag<(Neon_vduplane
5191                                      (Neon_low4S node:$LHS), node:$RHS)>>;
5192
5193   def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
5194                            op, VPR128Lo, v4i32, v8i16, v8i16, v4i16,
5195                            Neon_High8H,
5196                            BinOpFrag<(Neon_vduplane
5197                                        (Neon_low8H node:$LHS), node:$RHS)>>;
5198
5199   def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
5200                            op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S,
5201                            BinOpFrag<(Neon_vduplane
5202                                        (Neon_low4S node:$LHS), node:$RHS)>>;
5203
5204   // Index can only be half of the max value for lane in 64-bit vector
5205
5206   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
5207                         op, VPR64, VPR64Lo, v4i32, v4i16, v4i16,
5208                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5209
5210   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
5211                         op, VPR64, VPR64, v2i64, v2i32, v2i32,
5212                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5213
5214   def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
5215                           op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H,
5216                           BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5217
5218   def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
5219                           op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S,
5220                           BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5221 }
5222
5223 defm SMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SMULLve", int_arm_neon_vmulls>;
5224 defm UMULL_lane_v3 : NI_2VEL_mul_v3_pat<"UMULLve", int_arm_neon_vmullu>;
5225 defm SQDMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SQDMULLve", int_arm_neon_vqdmull>;
5226
5227 multiclass NI_qdma<SDPatternOperator op> {
5228   def _4s : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
5229                     (op node:$Ra,
5230                       (v4i32 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
5231
5232   def _2d : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
5233                     (op node:$Ra,
5234                       (v2i64 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
5235 }
5236
5237 defm Neon_qdmlal : NI_qdma<int_arm_neon_vqadds>;
5238 defm Neon_qdmlsl : NI_qdma<int_arm_neon_vqsubs>;
5239
5240 multiclass NI_2VEL_v3_qdma_pat<string subop, string op> {
5241   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
5242                      !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR128Lo,
5243                      v4i32, v4i16, v8i16,
5244                      BinOpFrag<(Neon_vduplane
5245                                  (Neon_low8H node:$LHS), node:$RHS)>>;
5246
5247   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
5248                      !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR128,
5249                      v2i64, v2i32, v4i32,
5250                      BinOpFrag<(Neon_vduplane
5251                                  (Neon_low4S node:$LHS), node:$RHS)>>;
5252
5253   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
5254                        !cast<PatFrag>(op # "_4s"), VPR128Lo,
5255                        v4i32, v8i16, v8i16, v4i16, Neon_High8H,
5256                        BinOpFrag<(Neon_vduplane
5257                                    (Neon_low8H node:$LHS), node:$RHS)>>;
5258
5259   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
5260                        !cast<PatFrag>(op # "_2d"), VPR128,
5261                        v2i64, v4i32, v4i32, v2i32, Neon_High4S,
5262                        BinOpFrag<(Neon_vduplane
5263                                    (Neon_low4S node:$LHS), node:$RHS)>>;
5264
5265   // Index can only be half of the max value for lane in 64-bit vector
5266
5267   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
5268                     !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR64Lo,
5269                     v4i32, v4i16, v4i16,
5270                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5271
5272   def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
5273                     !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR64,
5274                     v2i64, v2i32, v2i32,
5275                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5276
5277   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
5278                       !cast<PatFrag>(op # "_4s"), VPR64Lo,
5279                       v4i32, v8i16, v4i16, v4i16, Neon_High8H,
5280                       BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5281
5282   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
5283                       !cast<PatFrag>(op # "_2d"), VPR64,
5284                       v2i64, v4i32, v2i32, v2i32, Neon_High4S,
5285                       BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5286 }
5287
5288 defm SQDMLAL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLALvve", "Neon_qdmlal">;
5289 defm SQDMLSL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLSLvve", "Neon_qdmlsl">;
5290
5291 // End of implementation for instruction class (3V Elem)
5292
5293 //Insert element (vector, from main)
5294 def INSbw : NeonI_INS_main<"ins", "b", v16i8, GPR32, i32,
5295                            neon_uimm4_bare> {
5296   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
5297 }
5298 def INShw : NeonI_INS_main<"ins", "h", v8i16, GPR32, i32,
5299                            neon_uimm3_bare> {
5300   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
5301 }
5302 def INSsw : NeonI_INS_main<"ins", "s", v4i32, GPR32, i32,
5303                            neon_uimm2_bare> {
5304   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
5305 }
5306 def INSdx : NeonI_INS_main<"ins", "d", v2i64, GPR64, i64,
5307                            neon_uimm1_bare> {
5308   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
5309 }
5310
5311 class Neon_INS_main_pattern <ValueType ResTy,ValueType ExtResTy,
5312                              RegisterClass OpGPR, ValueType OpTy,
5313                              Operand OpImm, Instruction INS>
5314   : Pat<(ResTy (vector_insert
5315               (ResTy VPR64:$src),
5316               (OpTy OpGPR:$Rn),
5317               (OpImm:$Imm))),
5318         (ResTy (EXTRACT_SUBREG
5319           (ExtResTy (INS (ExtResTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
5320             OpGPR:$Rn, OpImm:$Imm)), sub_64))>;
5321
5322 def INSbw_pattern : Neon_INS_main_pattern<v8i8, v16i8, GPR32, i32,
5323                                           neon_uimm3_bare, INSbw>;
5324 def INShw_pattern : Neon_INS_main_pattern<v4i16, v8i16, GPR32, i32,
5325                                           neon_uimm2_bare, INShw>;
5326 def INSsw_pattern : Neon_INS_main_pattern<v2i32, v4i32, GPR32, i32,
5327                                           neon_uimm1_bare, INSsw>;
5328 def INSdx_pattern : Neon_INS_main_pattern<v1i64, v2i64, GPR64, i64,
5329                                           neon_uimm0_bare, INSdx>;
5330
5331 class NeonI_INS_element<string asmop, string Res, Operand ResImm>
5332   : NeonI_insert<0b1, 0b1,
5333                  (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn,
5334                  ResImm:$Immd, ResImm:$Immn),
5335                  asmop # "\t$Rd." # Res # "[$Immd], $Rn." # Res # "[$Immn]",
5336                  [],
5337                  NoItinerary> {
5338   let Constraints = "$src = $Rd";
5339   bits<4> Immd;
5340   bits<4> Immn;
5341 }
5342
5343 //Insert element (vector, from element)
5344 def INSELb : NeonI_INS_element<"ins", "b", neon_uimm4_bare> {
5345   let Inst{20-16} = {Immd{3}, Immd{2}, Immd{1}, Immd{0}, 0b1};
5346   let Inst{14-11} = {Immn{3}, Immn{2}, Immn{1}, Immn{0}};
5347 }
5348 def INSELh : NeonI_INS_element<"ins", "h", neon_uimm3_bare> {
5349   let Inst{20-16} = {Immd{2}, Immd{1}, Immd{0}, 0b1, 0b0};
5350   let Inst{14-12} = {Immn{2}, Immn{1}, Immn{0}};
5351   // bit 11 is unspecified.
5352 }
5353 def INSELs : NeonI_INS_element<"ins", "s", neon_uimm2_bare> {
5354   let Inst{20-16} = {Immd{1}, Immd{0}, 0b1, 0b0, 0b0};
5355   let Inst{14-13} = {Immn{1}, Immn{0}};
5356   // bits 11-12 are unspecified.
5357 }
5358 def INSELd : NeonI_INS_element<"ins", "d", neon_uimm1_bare> {
5359   let Inst{20-16} = {Immd, 0b1, 0b0, 0b0, 0b0};
5360   let Inst{14} = Immn{0};
5361   // bits 11-13 are unspecified.
5362 }
5363
5364 multiclass Neon_INS_elt_pattern<ValueType ResTy, ValueType NaTy,
5365                                 ValueType MidTy, Operand StImm, Operand NaImm,
5366                                 Instruction INS> {
5367 def : Pat<(ResTy (vector_insert
5368             (ResTy VPR128:$src),
5369             (MidTy (vector_extract
5370               (ResTy VPR128:$Rn),
5371               (StImm:$Immn))),
5372             (StImm:$Immd))),
5373           (INS (ResTy VPR128:$src), (ResTy VPR128:$Rn),
5374               StImm:$Immd, StImm:$Immn)>;
5375
5376 def : Pat <(ResTy (vector_insert
5377              (ResTy VPR128:$src),
5378              (MidTy (vector_extract
5379                (NaTy VPR64:$Rn),
5380                (NaImm:$Immn))),
5381              (StImm:$Immd))),
5382            (INS (ResTy VPR128:$src),
5383              (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
5384              StImm:$Immd, NaImm:$Immn)>;
5385
5386 def : Pat <(NaTy (vector_insert
5387              (NaTy VPR64:$src),
5388              (MidTy (vector_extract
5389                (ResTy VPR128:$Rn),
5390                (StImm:$Immn))),
5391              (NaImm:$Immd))),
5392            (NaTy (EXTRACT_SUBREG
5393              (ResTy (INS
5394                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
5395                (ResTy VPR128:$Rn),
5396                NaImm:$Immd, StImm:$Immn)),
5397              sub_64))>;
5398
5399 def : Pat <(NaTy (vector_insert
5400              (NaTy VPR64:$src),
5401              (MidTy (vector_extract
5402                (NaTy VPR64:$Rn),
5403                (NaImm:$Immn))),
5404              (NaImm:$Immd))),
5405            (NaTy (EXTRACT_SUBREG
5406              (ResTy (INS
5407                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
5408                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
5409                NaImm:$Immd, NaImm:$Immn)),
5410              sub_64))>;
5411 }
5412
5413 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, neon_uimm2_bare,
5414                             neon_uimm1_bare, INSELs>;
5415 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, neon_uimm1_bare,
5416                             neon_uimm0_bare, INSELd>;
5417 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
5418                             neon_uimm3_bare, INSELb>;
5419 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
5420                             neon_uimm2_bare, INSELh>;
5421 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
5422                             neon_uimm1_bare, INSELs>;
5423 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, neon_uimm1_bare,
5424                             neon_uimm0_bare, INSELd>;
5425
5426 multiclass Neon_INS_elt_float_pattern<ValueType ResTy, ValueType NaTy,
5427                                       ValueType MidTy,
5428                                       RegisterClass OpFPR, Operand ResImm,
5429                                       SubRegIndex SubIndex, Instruction INS> {
5430 def : Pat <(ResTy (vector_insert
5431              (ResTy VPR128:$src),
5432              (MidTy OpFPR:$Rn),
5433              (ResImm:$Imm))),
5434            (INS (ResTy VPR128:$src),
5435              (ResTy (SUBREG_TO_REG (i64 0), OpFPR:$Rn, SubIndex)),
5436              ResImm:$Imm,
5437              (i64 0))>;
5438
5439 def : Pat <(NaTy (vector_insert
5440              (NaTy VPR64:$src),
5441              (MidTy OpFPR:$Rn),
5442              (ResImm:$Imm))),
5443            (NaTy (EXTRACT_SUBREG
5444              (ResTy (INS
5445                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
5446                (ResTy (SUBREG_TO_REG (i64 0), (MidTy OpFPR:$Rn), SubIndex)),
5447                ResImm:$Imm,
5448                (i64 0))),
5449              sub_64))>;
5450 }
5451
5452 defm : Neon_INS_elt_float_pattern<v4f32, v2f32, f32, FPR32, neon_uimm2_bare,
5453                                   sub_32, INSELs>;
5454 defm : Neon_INS_elt_float_pattern<v2f64, v1f64, f64, FPR64, neon_uimm1_bare,
5455                                   sub_64, INSELd>;
5456
5457 class NeonI_SMOV<string asmop, string Res, bit Q,
5458                  ValueType OpTy, ValueType eleTy,
5459                  Operand OpImm, RegisterClass ResGPR, ValueType ResTy>
5460   : NeonI_copy<Q, 0b0, 0b0101,
5461                (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
5462                asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
5463                [(set (ResTy ResGPR:$Rd),
5464                  (ResTy (sext_inreg
5465                    (ResTy (vector_extract
5466                      (OpTy VPR128:$Rn), (OpImm:$Imm))),
5467                    eleTy)))],
5468                NoItinerary> {
5469   bits<4> Imm;
5470 }
5471
5472 //Signed integer move (main, from element)
5473 def SMOVwb : NeonI_SMOV<"smov", "b", 0b0, v16i8, i8, neon_uimm4_bare,
5474                         GPR32, i32> {
5475   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
5476 }
5477 def SMOVwh : NeonI_SMOV<"smov", "h", 0b0, v8i16, i16, neon_uimm3_bare,
5478                         GPR32, i32> {
5479   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
5480 }
5481 def SMOVxb : NeonI_SMOV<"smov", "b", 0b1, v16i8, i8, neon_uimm4_bare,
5482                         GPR64, i64> {
5483   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
5484 }
5485 def SMOVxh : NeonI_SMOV<"smov", "h", 0b1, v8i16, i16, neon_uimm3_bare,
5486                         GPR64, i64> {
5487   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
5488 }
5489 def SMOVxs : NeonI_SMOV<"smov", "s", 0b1, v4i32, i32, neon_uimm2_bare,
5490                         GPR64, i64> {
5491   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
5492 }
5493
5494 multiclass Neon_SMOVx_pattern <ValueType StTy, ValueType NaTy,
5495                                ValueType eleTy, Operand StImm,  Operand NaImm,
5496                                Instruction SMOVI> {
5497   def : Pat<(i64 (sext_inreg
5498               (i64 (anyext
5499                 (i32 (vector_extract
5500                   (StTy VPR128:$Rn), (StImm:$Imm))))),
5501               eleTy)),
5502             (SMOVI VPR128:$Rn, StImm:$Imm)>;
5503
5504   def : Pat<(i64 (sext
5505               (i32 (vector_extract
5506                 (StTy VPR128:$Rn), (StImm:$Imm))))),
5507             (SMOVI VPR128:$Rn, StImm:$Imm)>;
5508
5509   def : Pat<(i64 (sext_inreg
5510               (i64 (vector_extract
5511                 (NaTy VPR64:$Rn), (NaImm:$Imm))),
5512               eleTy)),
5513             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5514               NaImm:$Imm)>;
5515
5516   def : Pat<(i64 (sext_inreg
5517               (i64 (anyext
5518                 (i32 (vector_extract
5519                   (NaTy VPR64:$Rn), (NaImm:$Imm))))),
5520               eleTy)),
5521             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5522               NaImm:$Imm)>;
5523
5524   def : Pat<(i64 (sext
5525               (i32 (vector_extract
5526                 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
5527             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5528               NaImm:$Imm)>;
5529 }
5530
5531 defm : Neon_SMOVx_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
5532                           neon_uimm3_bare, SMOVxb>;
5533 defm : Neon_SMOVx_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
5534                           neon_uimm2_bare, SMOVxh>;
5535 defm : Neon_SMOVx_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
5536                           neon_uimm1_bare, SMOVxs>;
5537
5538 class Neon_SMOVw_pattern <ValueType StTy, ValueType NaTy,
5539                           ValueType eleTy, Operand StImm,  Operand NaImm,
5540                           Instruction SMOVI>
5541   : Pat<(i32 (sext_inreg
5542           (i32 (vector_extract
5543             (NaTy VPR64:$Rn), (NaImm:$Imm))),
5544           eleTy)),
5545         (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5546           NaImm:$Imm)>;
5547
5548 def : Neon_SMOVw_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
5549                          neon_uimm3_bare, SMOVwb>;
5550 def : Neon_SMOVw_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
5551                          neon_uimm2_bare, SMOVwh>;
5552
5553 class NeonI_UMOV<string asmop, string Res, bit Q,
5554                  ValueType OpTy, Operand OpImm,
5555                  RegisterClass ResGPR, ValueType ResTy>
5556   : NeonI_copy<Q, 0b0, 0b0111,
5557                (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
5558                asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
5559                [(set (ResTy ResGPR:$Rd),
5560                   (ResTy (vector_extract
5561                     (OpTy VPR128:$Rn), (OpImm:$Imm))))],
5562                NoItinerary> {
5563   bits<4> Imm;
5564 }
5565
5566 //Unsigned integer move (main, from element)
5567 def UMOVwb : NeonI_UMOV<"umov", "b", 0b0, v16i8, neon_uimm4_bare,
5568                          GPR32, i32> {
5569   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
5570 }
5571 def UMOVwh : NeonI_UMOV<"umov", "h", 0b0, v8i16, neon_uimm3_bare,
5572                          GPR32, i32> {
5573   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
5574 }
5575 def UMOVws : NeonI_UMOV<"umov", "s", 0b0, v4i32, neon_uimm2_bare,
5576                          GPR32, i32> {
5577   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
5578 }
5579 def UMOVxd : NeonI_UMOV<"umov", "d", 0b1, v2i64, neon_uimm1_bare,
5580                          GPR64, i64> {
5581   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
5582 }
5583
5584 class Neon_UMOV_pattern <ValueType StTy, ValueType NaTy, ValueType ResTy,
5585                          Operand StImm,  Operand NaImm,
5586                          Instruction SMOVI>
5587   : Pat<(ResTy (vector_extract
5588           (NaTy VPR64:$Rn), NaImm:$Imm)),
5589         (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5590           NaImm:$Imm)>;
5591
5592 def : Neon_UMOV_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
5593                         neon_uimm3_bare, UMOVwb>;
5594 def : Neon_UMOV_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
5595                         neon_uimm2_bare, UMOVwh>;
5596 def : Neon_UMOV_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
5597                         neon_uimm1_bare, UMOVws>;
5598
5599 def : Pat<(i32 (and
5600             (i32 (vector_extract
5601               (v16i8 VPR128:$Rn), (neon_uimm4_bare:$Imm))),
5602             255)),
5603           (UMOVwb VPR128:$Rn, neon_uimm4_bare:$Imm)>;
5604
5605 def : Pat<(i32 (and
5606             (i32 (vector_extract
5607               (v8i16 VPR128:$Rn), (neon_uimm3_bare:$Imm))),
5608             65535)),
5609           (UMOVwh VPR128:$Rn, neon_uimm3_bare:$Imm)>;
5610
5611 def : Pat<(i64 (zext
5612             (i32 (vector_extract
5613               (v2i64 VPR128:$Rn), (neon_uimm1_bare:$Imm))))),
5614           (UMOVxd VPR128:$Rn, neon_uimm1_bare:$Imm)>;
5615
5616 def : Pat<(i32 (and
5617             (i32 (vector_extract
5618               (v8i8 VPR64:$Rn), (neon_uimm3_bare:$Imm))),
5619             255)),
5620           (UMOVwb (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
5621             neon_uimm3_bare:$Imm)>;
5622
5623 def : Pat<(i32 (and
5624             (i32 (vector_extract
5625               (v4i16 VPR64:$Rn), (neon_uimm2_bare:$Imm))),
5626             65535)),
5627           (UMOVwh (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
5628             neon_uimm2_bare:$Imm)>;
5629
5630 def : Pat<(i64 (zext
5631             (i32 (vector_extract
5632               (v1i64 VPR64:$Rn), (neon_uimm0_bare:$Imm))))),
5633           (UMOVxd (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
5634             neon_uimm0_bare:$Imm)>;
5635
5636 // Additional copy patterns for scalar types
5637 def : Pat<(i32 (vector_extract (v1i8 FPR8:$Rn), (i64 0))),
5638           (UMOVwb (v16i8
5639             (SUBREG_TO_REG (i64 0), FPR8:$Rn, sub_8)), (i64 0))>;
5640
5641 def : Pat<(i32 (vector_extract (v1i16 FPR16:$Rn), (i64 0))),
5642           (UMOVwh (v8i16
5643             (SUBREG_TO_REG (i64 0), FPR16:$Rn, sub_16)), (i64 0))>;
5644
5645 def : Pat<(i32 (vector_extract (v1i32 FPR32:$Rn), (i64 0))),
5646           (FMOVws FPR32:$Rn)>;
5647
5648 def : Pat<(i64 (vector_extract (v1i64 FPR64:$Rn), (i64 0))),
5649           (FMOVxd FPR64:$Rn)>;
5650
5651 def : Pat<(f64 (vector_extract (v1f64 FPR64:$Rn), (i64 0))),
5652           (f64 FPR64:$Rn)>;
5653
5654 def : Pat<(f32 (vector_extract (v1f32 FPR32:$Rn), (i64 0))),
5655           (f32 FPR32:$Rn)>;
5656
5657 def : Pat<(v1i8 (scalar_to_vector GPR32:$Rn)),
5658           (v1i8 (EXTRACT_SUBREG (v16i8
5659             (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
5660             sub_8))>;
5661
5662 def : Pat<(v1i16 (scalar_to_vector GPR32:$Rn)),
5663           (v1i16 (EXTRACT_SUBREG (v8i16
5664             (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
5665             sub_16))>;
5666
5667 def : Pat<(v1i32 (scalar_to_vector GPR32:$src)),
5668           (FMOVsw $src)>;
5669
5670 def : Pat<(v1i64 (scalar_to_vector GPR64:$src)),
5671           (FMOVdx $src)>;
5672
5673 def : Pat<(v1f32 (scalar_to_vector (f32 FPR32:$Rn))),
5674           (v1f32 FPR32:$Rn)>;
5675 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
5676           (v1f64 FPR64:$Rn)>;
5677
5678 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
5679           (FMOVdd $src)>;
5680
5681 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$src))),
5682           (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
5683                          (f64 FPR64:$src), sub_64)>;
5684
5685 class NeonI_DUP_Elt<bit Q, string asmop, string rdlane,  string rnlane,
5686                     RegisterOperand ResVPR, Operand OpImm>
5687   : NeonI_copy<Q, 0b0, 0b0000, (outs ResVPR:$Rd),
5688                (ins VPR128:$Rn, OpImm:$Imm),
5689                asmop # "\t$Rd" # rdlane # ", $Rn" # rnlane # "[$Imm]",
5690                [],
5691                NoItinerary> {
5692   bits<4> Imm;
5693 }
5694
5695 def DUPELT16b : NeonI_DUP_Elt<0b1, "dup", ".16b", ".b", VPR128,
5696                               neon_uimm4_bare> {
5697   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
5698 }
5699
5700 def DUPELT8h : NeonI_DUP_Elt<0b1, "dup", ".8h", ".h", VPR128,
5701                               neon_uimm3_bare> {
5702   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
5703 }
5704
5705 def DUPELT4s : NeonI_DUP_Elt<0b1, "dup", ".4s", ".s", VPR128,
5706                               neon_uimm2_bare> {
5707   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
5708 }
5709
5710 def DUPELT2d : NeonI_DUP_Elt<0b1, "dup", ".2d", ".d", VPR128,
5711                               neon_uimm1_bare> {
5712   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
5713 }
5714
5715 def DUPELT8b : NeonI_DUP_Elt<0b0, "dup", ".8b", ".b", VPR64,
5716                               neon_uimm4_bare> {
5717   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
5718 }
5719
5720 def DUPELT4h : NeonI_DUP_Elt<0b0, "dup", ".4h", ".h", VPR64,
5721                               neon_uimm3_bare> {
5722   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
5723 }
5724
5725 def DUPELT2s : NeonI_DUP_Elt<0b0, "dup", ".2s", ".s", VPR64,
5726                               neon_uimm2_bare> {
5727   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
5728 }
5729
5730 multiclass NeonI_DUP_Elt_pattern<Instruction DUPELT, ValueType ResTy,
5731                                        ValueType OpTy,ValueType NaTy,
5732                                        ValueType ExTy, Operand OpLImm,
5733                                        Operand OpNImm> {
5734 def  : Pat<(ResTy (Neon_vduplane (OpTy VPR128:$Rn), OpLImm:$Imm)),
5735         (ResTy (DUPELT (OpTy VPR128:$Rn), OpLImm:$Imm))>;
5736
5737 def : Pat<(ResTy (Neon_vduplane
5738             (NaTy VPR64:$Rn), OpNImm:$Imm)),
5739           (ResTy (DUPELT
5740             (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)), OpNImm:$Imm))>;
5741 }
5742 defm : NeonI_DUP_Elt_pattern<DUPELT16b, v16i8, v16i8, v8i8, v16i8,
5743                              neon_uimm4_bare, neon_uimm3_bare>;
5744 defm : NeonI_DUP_Elt_pattern<DUPELT8b, v8i8, v16i8, v8i8, v16i8,
5745                              neon_uimm4_bare, neon_uimm3_bare>;
5746 defm : NeonI_DUP_Elt_pattern<DUPELT8h, v8i16, v8i16, v4i16, v8i16,
5747                              neon_uimm3_bare, neon_uimm2_bare>;
5748 defm : NeonI_DUP_Elt_pattern<DUPELT4h, v4i16, v8i16, v4i16, v8i16,
5749                              neon_uimm3_bare, neon_uimm2_bare>;
5750 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4i32, v4i32, v2i32, v4i32,
5751                              neon_uimm2_bare, neon_uimm1_bare>;
5752 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2i32, v4i32, v2i32, v4i32,
5753                              neon_uimm2_bare, neon_uimm1_bare>;
5754 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2i64, v2i64, v1i64, v2i64,
5755                              neon_uimm1_bare, neon_uimm0_bare>;
5756 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4f32, v4f32, v2f32, v4f32,
5757                              neon_uimm2_bare, neon_uimm1_bare>;
5758 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2f32, v4f32, v2f32, v4f32,
5759                              neon_uimm2_bare, neon_uimm1_bare>;
5760 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2f64, v2f64, v1f64, v2f64,
5761                              neon_uimm1_bare, neon_uimm0_bare>;
5762
5763 def : Pat<(v2f32 (Neon_vdup (f32 FPR32:$Rn))),
5764           (v2f32 (DUPELT2s
5765             (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
5766             (i64 0)))>;
5767 def : Pat<(v4f32 (Neon_vdup (f32 FPR32:$Rn))),
5768           (v4f32 (DUPELT4s
5769             (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
5770             (i64 0)))>;
5771 def : Pat<(v2f64 (Neon_vdup (f64 FPR64:$Rn))),
5772           (v2f64 (DUPELT2d
5773             (SUBREG_TO_REG (i64 0), FPR64:$Rn, sub_64),
5774             (i64 0)))>;
5775
5776 class NeonI_DUP<bit Q, string asmop, string rdlane,
5777                 RegisterOperand ResVPR, ValueType ResTy,
5778                 RegisterClass OpGPR, ValueType OpTy>
5779   : NeonI_copy<Q, 0b0, 0b0001, (outs ResVPR:$Rd), (ins OpGPR:$Rn),
5780                asmop # "\t$Rd" # rdlane # ", $Rn",
5781                [(set (ResTy ResVPR:$Rd),
5782                  (ResTy (Neon_vdup (OpTy OpGPR:$Rn))))],
5783                NoItinerary>;
5784
5785 def DUP16b : NeonI_DUP<0b1, "dup", ".16b", VPR128, v16i8, GPR32, i32> {
5786   let Inst{16} = 0b1;
5787   // bits 17-19 are unspecified.
5788 }
5789
5790 def DUP8h : NeonI_DUP<0b1, "dup", ".8h", VPR128, v8i16, GPR32, i32> {
5791   let Inst{17-16} = 0b10;
5792   // bits 18-19 are unspecified.
5793 }
5794
5795 def DUP4s : NeonI_DUP<0b1, "dup", ".4s", VPR128, v4i32, GPR32, i32> {
5796   let Inst{18-16} = 0b100;
5797   // bit 19 is unspecified.
5798 }
5799
5800 def DUP2d : NeonI_DUP<0b1, "dup", ".2d", VPR128, v2i64, GPR64, i64> {
5801   let Inst{19-16} = 0b1000;
5802 }
5803
5804 def DUP8b : NeonI_DUP<0b0, "dup", ".8b", VPR64, v8i8, GPR32, i32> {
5805   let Inst{16} = 0b1;
5806   // bits 17-19 are unspecified.
5807 }
5808
5809 def DUP4h : NeonI_DUP<0b0, "dup", ".4h", VPR64, v4i16, GPR32, i32> {
5810   let Inst{17-16} = 0b10;
5811   // bits 18-19 are unspecified.
5812 }
5813
5814 def DUP2s : NeonI_DUP<0b0, "dup", ".2s", VPR64, v2i32, GPR32, i32> {
5815   let Inst{18-16} = 0b100;
5816   // bit 19 is unspecified.
5817 }
5818
5819 // patterns for CONCAT_VECTORS
5820 multiclass Concat_Vector_Pattern<ValueType ResTy, ValueType OpTy> {
5821 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), undef)),
5822           (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)>;
5823 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))),
5824           (INSELd
5825             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5826             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rm, sub_64)),
5827             (i64 1),
5828             (i64 0))>;
5829 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rn))),
5830           (DUPELT2d
5831             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5832             (i64 0))> ;
5833 }
5834
5835 defm : Concat_Vector_Pattern<v16i8, v8i8>;
5836 defm : Concat_Vector_Pattern<v8i16, v4i16>;
5837 defm : Concat_Vector_Pattern<v4i32, v2i32>;
5838 defm : Concat_Vector_Pattern<v2i64, v1i64>;
5839 defm : Concat_Vector_Pattern<v4f32, v2f32>;
5840 defm : Concat_Vector_Pattern<v2f64, v1f64>;
5841
5842 //patterns for EXTRACT_SUBVECTOR
5843 def : Pat<(v8i8 (extract_subvector (v16i8 VPR128:$Rn), (i64 0))),
5844           (v8i8 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
5845 def : Pat<(v4i16 (extract_subvector (v8i16 VPR128:$Rn), (i64 0))),
5846           (v4i16 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
5847 def : Pat<(v2i32 (extract_subvector (v4i32 VPR128:$Rn), (i64 0))),
5848           (v2i32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
5849 def : Pat<(v1i64 (extract_subvector (v2i64 VPR128:$Rn), (i64 0))),
5850           (v1i64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
5851 def : Pat<(v2f32 (extract_subvector (v4f32 VPR128:$Rn), (i64 0))),
5852           (v2f32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
5853 def : Pat<(v1f64 (extract_subvector (v2f64 VPR128:$Rn), (i64 0))),
5854           (v1f64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
5855
5856 // Crypto Class
5857 class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
5858                          string asmop, SDPatternOperator opnode>
5859   : NeonI_Crypto_AES<size, opcode,
5860                      (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
5861                      asmop # "\t$Rd.16b, $Rn.16b",
5862                      [(set (v16i8 VPR128:$Rd),
5863                         (v16i8 (opnode (v16i8 VPR128:$src),
5864                                        (v16i8 VPR128:$Rn))))],
5865                      NoItinerary>{
5866   let Constraints = "$src = $Rd";
5867 }
5868
5869 def AESE : NeonI_Cryptoaes_2v<0b00, 0b00100, "aese", int_arm_neon_aese>;
5870 def AESD : NeonI_Cryptoaes_2v<0b00, 0b00101, "aesd", int_arm_neon_aesd>;
5871
5872 class NeonI_Cryptoaes<bits<2> size, bits<5> opcode,
5873                       string asmop, SDPatternOperator opnode>
5874   : NeonI_Crypto_AES<size, opcode,
5875                      (outs VPR128:$Rd), (ins VPR128:$Rn),
5876                      asmop # "\t$Rd.16b, $Rn.16b",
5877                      [(set (v16i8 VPR128:$Rd),
5878                         (v16i8 (opnode (v16i8 VPR128:$Rn))))],
5879                      NoItinerary>;
5880
5881 def AESMC : NeonI_Cryptoaes<0b00, 0b00110, "aesmc", int_arm_neon_aesmc>;
5882 def AESIMC : NeonI_Cryptoaes<0b00, 0b00111, "aesimc", int_arm_neon_aesimc>;
5883
5884 class NeonI_Cryptosha_vv<bits<2> size, bits<5> opcode,
5885                          string asmop, SDPatternOperator opnode>
5886   : NeonI_Crypto_SHA<size, opcode,
5887                      (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
5888                      asmop # "\t$Rd.4s, $Rn.4s",
5889                      [(set (v4i32 VPR128:$Rd),
5890                         (v4i32 (opnode (v4i32 VPR128:$src),
5891                                        (v4i32 VPR128:$Rn))))],
5892                      NoItinerary> {
5893   let Constraints = "$src = $Rd";
5894 }
5895
5896 def SHA1SU1 : NeonI_Cryptosha_vv<0b00, 0b00001, "sha1su1",
5897                                  int_arm_neon_sha1su1>;
5898 def SHA256SU0 : NeonI_Cryptosha_vv<0b00, 0b00010, "sha256su0",
5899                                    int_arm_neon_sha256su0>;
5900
5901 class NeonI_Cryptosha_ss<bits<2> size, bits<5> opcode,
5902                          string asmop, SDPatternOperator opnode>
5903   : NeonI_Crypto_SHA<size, opcode,
5904                      (outs FPR32:$Rd), (ins FPR32:$Rn),
5905                      asmop # "\t$Rd, $Rn",
5906                      [(set (v1i32 FPR32:$Rd),
5907                         (v1i32 (opnode (v1i32 FPR32:$Rn))))],
5908                      NoItinerary>;
5909
5910 def SHA1H : NeonI_Cryptosha_ss<0b00, 0b00000, "sha1h", int_arm_neon_sha1h>;
5911
5912 class NeonI_Cryptosha3_vvv<bits<2> size, bits<3> opcode, string asmop,
5913                            SDPatternOperator opnode>
5914   : NeonI_Crypto_3VSHA<size, opcode,
5915                        (outs VPR128:$Rd),
5916                        (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
5917                        asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
5918                        [(set (v4i32 VPR128:$Rd),
5919                           (v4i32 (opnode (v4i32 VPR128:$src),
5920                                          (v4i32 VPR128:$Rn),
5921                                          (v4i32 VPR128:$Rm))))],
5922                        NoItinerary> {
5923   let Constraints = "$src = $Rd";
5924 }
5925
5926 def SHA1SU0 : NeonI_Cryptosha3_vvv<0b00, 0b011, "sha1su0",
5927                                    int_arm_neon_sha1su0>;
5928 def SHA256SU1 : NeonI_Cryptosha3_vvv<0b00, 0b110, "sha256su1",
5929                                      int_arm_neon_sha256su1>;
5930
5931 class NeonI_Cryptosha3_qqv<bits<2> size, bits<3> opcode, string asmop,
5932                            SDPatternOperator opnode>
5933   : NeonI_Crypto_3VSHA<size, opcode,
5934                        (outs FPR128:$Rd),
5935                        (ins FPR128:$src, FPR128:$Rn, VPR128:$Rm),
5936                        asmop # "\t$Rd, $Rn, $Rm.4s",
5937                        [(set (v4i32 FPR128:$Rd),
5938                           (v4i32 (opnode (v4i32 FPR128:$src),
5939                                          (v4i32 FPR128:$Rn),
5940                                          (v4i32 VPR128:$Rm))))],
5941                        NoItinerary> {
5942   let Constraints = "$src = $Rd";
5943 }
5944
5945 def SHA256H : NeonI_Cryptosha3_qqv<0b00, 0b100, "sha256h",
5946                                    int_arm_neon_sha256h>;
5947 def SHA256H2 : NeonI_Cryptosha3_qqv<0b00, 0b101, "sha256h2",
5948                                     int_arm_neon_sha256h2>;
5949
5950 class NeonI_Cryptosha3_qsv<bits<2> size, bits<3> opcode, string asmop,
5951                            SDPatternOperator opnode>
5952   : NeonI_Crypto_3VSHA<size, opcode,
5953                        (outs FPR128:$Rd),
5954                        (ins FPR128:$src, FPR32:$Rn, VPR128:$Rm),
5955                        asmop # "\t$Rd, $Rn, $Rm.4s",
5956                        [(set (v4i32 FPR128:$Rd),
5957                           (v4i32 (opnode (v4i32 FPR128:$src),
5958                                          (v1i32 FPR32:$Rn),
5959                                          (v4i32 VPR128:$Rm))))],
5960                        NoItinerary> {
5961   let Constraints = "$src = $Rd";
5962 }
5963
5964 def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
5965 def SHA1P : NeonI_Cryptosha3_qsv<0b00, 0b001, "sha1p", int_aarch64_neon_sha1p>;
5966 def SHA1M : NeonI_Cryptosha3_qsv<0b00, 0b010, "sha1m", int_aarch64_neon_sha1m>;
5967