lib/Target/AArch64/AArch64InstrNEON.td

   1 //===-- AArch64InstrNEON.td - NEON support for AArch64 -----*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the AArch64 NEON instruction set.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // NEON-specific DAG Nodes.
  16 //===----------------------------------------------------------------------===//
  17 def Neon_bsl       : SDNode<"AArch64ISD::NEON_BSL", SDTypeProfile<1, 3,
  18                       [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
  19                       SDTCisSameAs<0, 3>]>>;
  20
  21 // (outs Result), (ins Imm, OpCmode)
  22 def SDT_Neon_movi : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
  23
  24 def Neon_movi     : SDNode<"AArch64ISD::NEON_MOVIMM", SDT_Neon_movi>;
  25
  26 def Neon_mvni     : SDNode<"AArch64ISD::NEON_MVNIMM", SDT_Neon_movi>;
  27
  28 // (outs Result), (ins Imm)
  29 def Neon_fmovi : SDNode<"AArch64ISD::NEON_FMOVIMM", SDTypeProfile<1, 1,
  30                         [SDTCisVec<0>, SDTCisVT<1, i32>]>>;
  31
  32 // (outs Result), (ins LHS, RHS, CondCode)
  33 def Neon_cmp : SDNode<"AArch64ISD::NEON_CMP", SDTypeProfile<1, 3,
  34                  [SDTCisVec<0>,  SDTCisSameAs<1, 2>]>>;
  35
  36 // (outs Result), (ins LHS, 0/0.0 constant, CondCode)
  37 def Neon_cmpz : SDNode<"AArch64ISD::NEON_CMPZ", SDTypeProfile<1, 3,
  38                  [SDTCisVec<0>,  SDTCisVec<1>]>>;
  39
  40 // (outs Result), (ins LHS, RHS)
  41 def Neon_tst : SDNode<"AArch64ISD::NEON_TST", SDTypeProfile<1, 2,
  42                  [SDTCisVec<0>,  SDTCisSameAs<1, 2>]>>;
  43
  44 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  45                                      SDTCisVT<2, i32>]>;
  46 def Neon_sqrshlImm   : SDNode<"AArch64ISD::NEON_QSHLs", SDTARMVSH>;
  47 def Neon_uqrshlImm   : SDNode<"AArch64ISD::NEON_QSHLu", SDTARMVSH>;
  48
  49 def SDTVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
  50 def Neon_rev64    : SDNode<"AArch64ISD::NEON_REV64", SDTVSHUF>;
  51 def Neon_rev32    : SDNode<"AArch64ISD::NEON_REV32", SDTVSHUF>;
  52 def Neon_rev16    : SDNode<"AArch64ISD::NEON_REV16", SDTVSHUF>;
  53 def Neon_vdup : SDNode<"AArch64ISD::NEON_VDUP", SDTypeProfile<1, 1,
  54                        [SDTCisVec<0>]>>;
  55 def Neon_vduplane : SDNode<"AArch64ISD::NEON_VDUPLANE", SDTypeProfile<1, 2,
  56                            [SDTCisVec<0>, SDTCisVec<1>, SDTCisVT<2, i64>]>>;
  57 def Neon_vextract : SDNode<"AArch64ISD::NEON_VEXTRACT", SDTypeProfile<1, 3,
  58                            [SDTCisVec<0>,  SDTCisSameAs<0, 1>,
  59                            SDTCisSameAs<0, 2>, SDTCisVT<3, i64>]>>;
  60
  61 //===----------------------------------------------------------------------===//
  62 // Multiclasses
  63 //===----------------------------------------------------------------------===//
  64
  65 multiclass NeonI_3VSame_B_sizes<bit u, bits<2> size,  bits<5> opcode,
  66                                 string asmop, SDPatternOperator opnode8B,
  67                                 SDPatternOperator opnode16B,
  68                                 bit Commutable = 0> {
  69   let isCommutable = Commutable in {
  70     def _8B :  NeonI_3VSame<0b0, u, size, opcode,
  71                (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
  72                asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
  73                [(set (v8i8 VPR64:$Rd),
  74                   (v8i8 (opnode8B (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
  75                NoItinerary>;
  76
  77     def _16B : NeonI_3VSame<0b1, u, size, opcode,
  78                (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
  79                asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
  80                [(set (v16i8 VPR128:$Rd),
  81                   (v16i8 (opnode16B (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
  82                NoItinerary>;
  83   }
  84
  85 }
  86
  87 multiclass NeonI_3VSame_HS_sizes<bit u, bits<5> opcode,
  88                                   string asmop, SDPatternOperator opnode,
  89                                   bit Commutable = 0> {
  90   let isCommutable = Commutable in {
  91     def _4H : NeonI_3VSame<0b0, u, 0b01, opcode,
  92               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
  93               asmop # "\t$Rd.4h, $Rn.4h, $Rm.4h",
  94               [(set (v4i16 VPR64:$Rd),
  95                  (v4i16 (opnode (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))))],
  96               NoItinerary>;
  97
  98     def _8H : NeonI_3VSame<0b1, u, 0b01, opcode,
  99               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 100               asmop # "\t$Rd.8h, $Rn.8h, $Rm.8h",
 101               [(set (v8i16 VPR128:$Rd),
 102                  (v8i16 (opnode (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))))],
 103               NoItinerary>;
 104
 105     def _2S : NeonI_3VSame<0b0, u, 0b10, opcode,
 106               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 107               asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
 108               [(set (v2i32 VPR64:$Rd),
 109                  (v2i32 (opnode (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))))],
 110               NoItinerary>;
 111
 112     def _4S : NeonI_3VSame<0b1, u, 0b10, opcode,
 113               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 114               asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
 115               [(set (v4i32 VPR128:$Rd),
 116                  (v4i32 (opnode (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))))],
 117               NoItinerary>;
 118   }
 119 }
 120 multiclass NeonI_3VSame_BHS_sizes<bit u, bits<5> opcode,
 121                                   string asmop, SDPatternOperator opnode,
 122                                   bit Commutable = 0>
 123    : NeonI_3VSame_HS_sizes<u, opcode,  asmop, opnode, Commutable> {
 124   let isCommutable = Commutable in {
 125     def _8B :  NeonI_3VSame<0b0, u, 0b00, opcode,
 126                (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 127                asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
 128                [(set (v8i8 VPR64:$Rd),
 129                   (v8i8 (opnode (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
 130                NoItinerary>;
 131
 132     def _16B : NeonI_3VSame<0b1, u, 0b00, opcode,
 133                (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 134                asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
 135                [(set (v16i8 VPR128:$Rd),
 136                   (v16i8 (opnode (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
 137                NoItinerary>;
 138   }
 139 }
 140
 141 multiclass NeonI_3VSame_BHSD_sizes<bit u, bits<5> opcode,
 142                                    string asmop, SDPatternOperator opnode,
 143                                    bit Commutable = 0>
 144    : NeonI_3VSame_BHS_sizes<u, opcode,  asmop, opnode, Commutable> {
 145   let isCommutable = Commutable in {
 146     def _2D : NeonI_3VSame<0b1, u, 0b11, opcode,
 147               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 148               asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
 149               [(set (v2i64 VPR128:$Rd),
 150                  (v2i64 (opnode (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))))],
 151               NoItinerary>;
 152   }
 153 }
 154
 155 // Multiclass NeonI_3VSame_SD_sizes: Operand types are floating point types,
 156 // but Result types can be integer or floating point types.
 157 multiclass NeonI_3VSame_SD_sizes<bit u, bit size, bits<5> opcode,
 158                                  string asmop, SDPatternOperator opnode2S,
 159                                  SDPatternOperator opnode4S,
 160                                  SDPatternOperator opnode2D,
 161                                  ValueType ResTy2S, ValueType ResTy4S,
 162                                  ValueType ResTy2D, bit Commutable = 0> {
 163   let isCommutable = Commutable in {
 164     def _2S : NeonI_3VSame<0b0, u, {size, 0b0}, opcode,
 165               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 166               asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
 167               [(set (ResTy2S VPR64:$Rd),
 168                  (ResTy2S (opnode2S (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
 169               NoItinerary>;
 170
 171     def _4S : NeonI_3VSame<0b1, u, {size, 0b0}, opcode,
 172               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 173               asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
 174               [(set (ResTy4S VPR128:$Rd),
 175                  (ResTy4S (opnode4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
 176               NoItinerary>;
 177
 178     def _2D : NeonI_3VSame<0b1, u, {size, 0b1}, opcode,
 179               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 180               asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
 181               [(set (ResTy2D VPR128:$Rd),
 182                  (ResTy2D (opnode2D (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))))],
 183                NoItinerary>;
 184   }
 185 }
 186
 187 //===----------------------------------------------------------------------===//
 188 // Instruction Definitions
 189 //===----------------------------------------------------------------------===//
 190
 191 // Vector Arithmetic Instructions
 192
 193 // Vector Add (Integer and Floating-Point)
 194
 195 defm ADDvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b10000, "add", add, 1>;
 196 defm FADDvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11010, "fadd", fadd, fadd, fadd,
 197                                      v2f32, v4f32, v2f64, 1>;
 198
 199 // Vector Sub (Integer and Floating-Point)
 200
 201 defm SUBvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b10000, "sub", sub, 0>;
 202 defm FSUBvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11010, "fsub", fsub, fsub, fsub,
 203                                      v2f32, v4f32, v2f64, 0>;
 204
 205 // Vector Multiply (Integer and Floating-Point)
 206
 207 defm MULvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b10011, "mul", mul, 1>;
 208 defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul, fmul, fmul,
 209                                      v2f32, v4f32, v2f64, 1>;
 210
 211 // Vector Multiply (Polynomial)
 212
 213 defm PMULvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b10011, "pmul",
 214                                     int_arm_neon_vmulp, int_arm_neon_vmulp, 1>;
 215
 216 // Vector Multiply-accumulate and Multiply-subtract (Integer)
 217
 218 // class NeonI_3VSame_Constraint_impl: NeonI_3VSame with no data type and
 219 // two operands constraints.
 220 class NeonI_3VSame_Constraint_impl<string asmop, string asmlane,
 221   RegisterOperand VPRC, ValueType OpTy, bit q, bit u, bits<2> size,
 222   bits<5> opcode, SDPatternOperator opnode>
 223   : NeonI_3VSame<q, u, size, opcode,
 224     (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, VPRC:$Rm),
 225     asmop # "\t$Rd" # asmlane # ", $Rn" # asmlane # ", $Rm" # asmlane,
 226     [(set (OpTy VPRC:$Rd),
 227        (OpTy (opnode (OpTy VPRC:$src), (OpTy VPRC:$Rn), (OpTy VPRC:$Rm))))],
 228     NoItinerary> {
 229   let Constraints = "$src = $Rd";
 230 }
 231
 232 def Neon_mla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 233                        (add node:$Ra, (mul node:$Rn, node:$Rm))>;
 234
 235 def Neon_mls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 236                        (sub node:$Ra, (mul node:$Rn, node:$Rm))>;
 237
 238
 239 def MLAvvv_8B:  NeonI_3VSame_Constraint_impl<"mla", ".8b",  VPR64,  v8i8,
 240                                              0b0, 0b0, 0b00, 0b10010, Neon_mla>;
 241 def MLAvvv_16B: NeonI_3VSame_Constraint_impl<"mla", ".16b", VPR128, v16i8,
 242                                              0b1, 0b0, 0b00, 0b10010, Neon_mla>;
 243 def MLAvvv_4H:  NeonI_3VSame_Constraint_impl<"mla", ".4h",  VPR64,  v4i16,
 244                                              0b0, 0b0, 0b01, 0b10010, Neon_mla>;
 245 def MLAvvv_8H:  NeonI_3VSame_Constraint_impl<"mla", ".8h",  VPR128, v8i16,
 246                                              0b1, 0b0, 0b01, 0b10010, Neon_mla>;
 247 def MLAvvv_2S:  NeonI_3VSame_Constraint_impl<"mla", ".2s",  VPR64,  v2i32,
 248                                              0b0, 0b0, 0b10, 0b10010, Neon_mla>;
 249 def MLAvvv_4S:  NeonI_3VSame_Constraint_impl<"mla", ".4s",  VPR128, v4i32,
 250                                              0b1, 0b0, 0b10, 0b10010, Neon_mla>;
 251
 252 def MLSvvv_8B:  NeonI_3VSame_Constraint_impl<"mls", ".8b",  VPR64,  v8i8,
 253                                              0b0, 0b1, 0b00, 0b10010, Neon_mls>;
 254 def MLSvvv_16B: NeonI_3VSame_Constraint_impl<"mls", ".16b", VPR128, v16i8,
 255                                              0b1, 0b1, 0b00, 0b10010, Neon_mls>;
 256 def MLSvvv_4H:  NeonI_3VSame_Constraint_impl<"mls", ".4h",  VPR64,  v4i16,
 257                                              0b0, 0b1, 0b01, 0b10010, Neon_mls>;
 258 def MLSvvv_8H:  NeonI_3VSame_Constraint_impl<"mls", ".8h",  VPR128, v8i16,
 259                                              0b1, 0b1, 0b01, 0b10010, Neon_mls>;
 260 def MLSvvv_2S:  NeonI_3VSame_Constraint_impl<"mls", ".2s",  VPR64,  v2i32,
 261                                              0b0, 0b1, 0b10, 0b10010, Neon_mls>;
 262 def MLSvvv_4S:  NeonI_3VSame_Constraint_impl<"mls", ".4s",  VPR128, v4i32,
 263                                              0b1, 0b1, 0b10, 0b10010, Neon_mls>;
 264
 265 // Vector Multiply-accumulate and Multiply-subtract (Floating Point)
 266
 267 def Neon_fmla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 268                         (fadd node:$Ra, (fmul node:$Rn, node:$Rm))>;
 269
 270 def Neon_fmls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 271                         (fsub node:$Ra, (fmul node:$Rn, node:$Rm))>;
 272
 273 let Predicates = [HasNEON, UseFusedMAC] in {
 274 def FMLAvvv_2S: NeonI_3VSame_Constraint_impl<"fmla", ".2s",  VPR64,  v2f32,
 275                                              0b0, 0b0, 0b00, 0b11001, Neon_fmla>;
 276 def FMLAvvv_4S: NeonI_3VSame_Constraint_impl<"fmla", ".4s",  VPR128, v4f32,
 277                                              0b1, 0b0, 0b00, 0b11001, Neon_fmla>;
 278 def FMLAvvv_2D: NeonI_3VSame_Constraint_impl<"fmla", ".2d",  VPR128, v2f64,
 279                                              0b1, 0b0, 0b01, 0b11001, Neon_fmla>;
 280
 281 def FMLSvvv_2S: NeonI_3VSame_Constraint_impl<"fmls", ".2s",  VPR64,  v2f32,
 282                                               0b0, 0b0, 0b10, 0b11001, Neon_fmls>;
 283 def FMLSvvv_4S: NeonI_3VSame_Constraint_impl<"fmls", ".4s",  VPR128, v4f32,
 284                                              0b1, 0b0, 0b10, 0b11001, Neon_fmls>;
 285 def FMLSvvv_2D: NeonI_3VSame_Constraint_impl<"fmls", ".2d",  VPR128, v2f64,
 286                                              0b1, 0b0, 0b11, 0b11001, Neon_fmls>;
 287 }
 288
 289 // We're also allowed to match the fma instruction regardless of compile
 290 // options.
 291 def : Pat<(v2f32 (fma VPR64:$Rn, VPR64:$Rm, VPR64:$Ra)),
 292           (FMLAvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
 293 def : Pat<(v4f32 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
 294           (FMLAvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 295 def : Pat<(v2f64 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
 296           (FMLAvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 297
 298 def : Pat<(v2f32 (fma (fneg VPR64:$Rn), VPR64:$Rm, VPR64:$Ra)),
 299           (FMLSvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
 300 def : Pat<(v4f32 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
 301           (FMLSvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 302 def : Pat<(v2f64 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
 303           (FMLSvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 304
 305 // Vector Divide (Floating-Point)
 306
 307 defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv, fdiv, fdiv,
 308                                      v2f32, v4f32, v2f64, 0>;
 309
 310 // Vector Bitwise Operations
 311
 312 // Vector Bitwise AND
 313
 314 defm ANDvvv : NeonI_3VSame_B_sizes<0b0, 0b00, 0b00011, "and", and, and, 1>;
 315
 316 // Vector Bitwise Exclusive OR
 317
 318 defm EORvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b00011, "eor", xor, xor, 1>;
 319
 320 // Vector Bitwise OR
 321
 322 defm ORRvvv : NeonI_3VSame_B_sizes<0b0, 0b10, 0b00011, "orr", or, or, 1>;
 323
 324 // ORR disassembled as MOV if Vn==Vm
 325
 326 // Vector Move - register
 327 // Alias for ORR if Vn=Vm.
 328 // FIXME: This is actually the preferred syntax but TableGen can't deal with
 329 // custom printing of aliases.
 330 def : NeonInstAlias<"mov $Rd.8b, $Rn.8b",
 331                     (ORRvvv_8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rn), 0>;
 332 def : NeonInstAlias<"mov $Rd.16b, $Rn.16b",
 333                     (ORRvvv_16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rn), 0>;
 334
 335 // The MOVI instruction takes two immediate operands.  The first is the
 336 // immediate encoding, while the second is the cmode.  A cmode of 14, or
 337 // 0b1110, produces a MOVI operation, rather than a MVNI, ORR, or BIC.
 338 def Neon_AllZero : PatFrag<(ops), (Neon_movi (i32 0), (i32 14))>;
 339 def Neon_AllOne : PatFrag<(ops), (Neon_movi (i32 255), (i32 14))>;
 340
 341 def Neon_not8B  : PatFrag<(ops node:$in),
 342                           (xor node:$in, (bitconvert (v8i8 Neon_AllOne)))>;
 343 def Neon_not16B : PatFrag<(ops node:$in),
 344                           (xor node:$in, (bitconvert (v16i8 Neon_AllOne)))>;
 345
 346 def Neon_orn8B : PatFrag<(ops node:$Rn, node:$Rm),
 347                          (or node:$Rn, (Neon_not8B node:$Rm))>;
 348
 349 def Neon_orn16B : PatFrag<(ops node:$Rn, node:$Rm),
 350                           (or node:$Rn, (Neon_not16B node:$Rm))>;
 351
 352 def Neon_bic8B : PatFrag<(ops node:$Rn, node:$Rm),
 353                          (and node:$Rn, (Neon_not8B node:$Rm))>;
 354
 355 def Neon_bic16B : PatFrag<(ops node:$Rn, node:$Rm),
 356                           (and node:$Rn, (Neon_not16B node:$Rm))>;
 357
 358
 359 // Vector Bitwise OR NOT - register
 360
 361 defm ORNvvv : NeonI_3VSame_B_sizes<0b0, 0b11, 0b00011, "orn",
 362                                    Neon_orn8B, Neon_orn16B, 0>;
 363
 364 // Vector Bitwise Bit Clear (AND NOT) - register
 365
 366 defm BICvvv : NeonI_3VSame_B_sizes<0b0, 0b01, 0b00011, "bic",
 367                                    Neon_bic8B, Neon_bic16B, 0>;
 368
 369 multiclass Neon_bitwise2V_patterns<SDPatternOperator opnode8B,
 370                                    SDPatternOperator opnode16B,
 371                                    Instruction INST8B,
 372                                    Instruction INST16B> {
 373   def : Pat<(v2i32 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 374             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 375   def : Pat<(v4i16 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 376             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 377   def : Pat<(v1i64 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 378             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 379   def : Pat<(v4i32 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 380             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 381   def : Pat<(v8i16 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 382             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 383   def : Pat<(v2i64 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 384             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 385 }
 386
 387 // Additional patterns for bitwise instructions AND, EOR, ORR, BIC, ORN
 388 defm : Neon_bitwise2V_patterns<and, and, ANDvvv_8B, ANDvvv_16B>;
 389 defm : Neon_bitwise2V_patterns<or,  or,  ORRvvv_8B, ORRvvv_16B>;
 390 defm : Neon_bitwise2V_patterns<xor, xor, EORvvv_8B, EORvvv_16B>;
 391 defm : Neon_bitwise2V_patterns<Neon_bic8B, Neon_bic16B, BICvvv_8B, BICvvv_16B>;
 392 defm : Neon_bitwise2V_patterns<Neon_orn8B, Neon_orn16B, ORNvvv_8B, ORNvvv_16B>;
 393
 394 //   Vector Bitwise Select
 395 def BSLvvv_8B  : NeonI_3VSame_Constraint_impl<"bsl", ".8b",  VPR64, v8i8,
 396                                               0b0, 0b1, 0b01, 0b00011, Neon_bsl>;
 397
 398 def BSLvvv_16B : NeonI_3VSame_Constraint_impl<"bsl", ".16b", VPR128, v16i8,
 399                                               0b1, 0b1, 0b01, 0b00011, Neon_bsl>;
 400
 401 multiclass Neon_bitwise3V_patterns<SDPatternOperator opnode,
 402                                    Instruction INST8B,
 403                                    Instruction INST16B> {
 404   // Disassociate type from instruction definition
 405   def : Pat<(v2i32 (opnode VPR64:$src,VPR64:$Rn, VPR64:$Rm)),
 406             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 407   def : Pat<(v4i16 (opnode VPR64:$src, VPR64:$Rn, VPR64:$Rm)),
 408             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 409   def : Pat<(v1i64 (opnode VPR64:$src, VPR64:$Rn, VPR64:$Rm)),
 410             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 411   def : Pat<(v4i32 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
 412             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 413   def : Pat<(v8i16 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
 414             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 415   def : Pat<(v2i64 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
 416             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 417
 418   // Allow to match BSL instruction pattern with non-constant operand
 419   def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
 420                     (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 421           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 422   def : Pat<(v4i16 (or (and VPR64:$Rn, VPR64:$Rd),
 423                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 424           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 425   def : Pat<(v2i32 (or (and VPR64:$Rn, VPR64:$Rd),
 426                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 427           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 428   def : Pat<(v1i64 (or (and VPR64:$Rn, VPR64:$Rd),
 429                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 430           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 431   def : Pat<(v16i8 (or (and VPR128:$Rn, VPR128:$Rd),
 432                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 433           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 434   def : Pat<(v8i16 (or (and VPR128:$Rn, VPR128:$Rd),
 435                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 436           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 437   def : Pat<(v4i32 (or (and VPR128:$Rn, VPR128:$Rd),
 438                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 439           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 440   def : Pat<(v2i64 (or (and VPR128:$Rn, VPR128:$Rd),
 441                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 442           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 443
 444   // Allow to match llvm.arm.* intrinsics.
 445   def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 VPR64:$src),
 446                     (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
 447             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 448   def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 VPR64:$src),
 449                     (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
 450             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 451   def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 VPR64:$src),
 452                     (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
 453             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 454   def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 VPR64:$src),
 455                     (v1i64 VPR64:$Rn), (v1i64 VPR64:$Rm))),
 456             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 457   def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 VPR64:$src),
 458                     (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
 459             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 460   def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 VPR128:$src),
 461                     (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
 462             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 463   def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 VPR128:$src),
 464                     (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
 465             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 466   def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 VPR128:$src),
 467                     (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
 468             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 469   def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 VPR128:$src),
 470                     (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
 471             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 472   def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 VPR128:$src),
 473                     (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
 474             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 475   def : Pat<(v2f64 (int_arm_neon_vbsl (v2f64 VPR128:$src),
 476                     (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
 477             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 478 }
 479
 480 // Additional patterns for bitwise instruction BSL
 481 defm: Neon_bitwise3V_patterns<Neon_bsl, BSLvvv_8B, BSLvvv_16B>;
 482
 483 def Neon_NoBSLop : PatFrag<(ops node:$src, node:$Rn, node:$Rm),
 484                            (Neon_bsl node:$src, node:$Rn, node:$Rm),
 485                            [{ (void)N; return false; }]>;
 486
 487 // Vector Bitwise Insert if True
 488
 489 def BITvvv_8B  : NeonI_3VSame_Constraint_impl<"bit", ".8b", VPR64,   v8i8,
 490                    0b0, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
 491 def BITvvv_16B : NeonI_3VSame_Constraint_impl<"bit", ".16b", VPR128, v16i8,
 492                    0b1, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
 493
 494 // Vector Bitwise Insert if False
 495
 496 def BIFvvv_8B  : NeonI_3VSame_Constraint_impl<"bif", ".8b", VPR64,  v8i8,
 497                                 0b0, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
 498 def BIFvvv_16B : NeonI_3VSame_Constraint_impl<"bif", ".16b", VPR128, v16i8,
 499                                 0b1, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
 500
 501 // Vector Absolute Difference and Accumulate (Signed, Unsigned)
 502
 503 def Neon_uaba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 504                        (add node:$Ra, (int_arm_neon_vabdu node:$Rn, node:$Rm))>;
 505 def Neon_saba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 506                        (add node:$Ra, (int_arm_neon_vabds node:$Rn, node:$Rm))>;
 507
 508 // Vector Absolute Difference and Accumulate (Unsigned)
 509 def UABAvvv_8B :  NeonI_3VSame_Constraint_impl<"uaba", ".8b",  VPR64,  v8i8,
 510                     0b0, 0b1, 0b00, 0b01111, Neon_uaba>;
 511 def UABAvvv_16B : NeonI_3VSame_Constraint_impl<"uaba", ".16b", VPR128, v16i8,
 512                     0b1, 0b1, 0b00, 0b01111, Neon_uaba>;
 513 def UABAvvv_4H :  NeonI_3VSame_Constraint_impl<"uaba", ".4h",  VPR64,  v4i16,
 514                     0b0, 0b1, 0b01, 0b01111, Neon_uaba>;
 515 def UABAvvv_8H :  NeonI_3VSame_Constraint_impl<"uaba", ".8h",  VPR128, v8i16,
 516                     0b1, 0b1, 0b01, 0b01111, Neon_uaba>;
 517 def UABAvvv_2S :  NeonI_3VSame_Constraint_impl<"uaba", ".2s",  VPR64,  v2i32,
 518                     0b0, 0b1, 0b10, 0b01111, Neon_uaba>;
 519 def UABAvvv_4S :  NeonI_3VSame_Constraint_impl<"uaba", ".4s",  VPR128, v4i32,
 520                     0b1, 0b1, 0b10, 0b01111, Neon_uaba>;
 521
 522 // Vector Absolute Difference and Accumulate (Signed)
 523 def SABAvvv_8B :  NeonI_3VSame_Constraint_impl<"saba", ".8b",  VPR64,  v8i8,
 524                     0b0, 0b0, 0b00, 0b01111, Neon_saba>;
 525 def SABAvvv_16B : NeonI_3VSame_Constraint_impl<"saba", ".16b", VPR128, v16i8,
 526                     0b1, 0b0, 0b00, 0b01111, Neon_saba>;
 527 def SABAvvv_4H :  NeonI_3VSame_Constraint_impl<"saba", ".4h",  VPR64,  v4i16,
 528                     0b0, 0b0, 0b01, 0b01111, Neon_saba>;
 529 def SABAvvv_8H :  NeonI_3VSame_Constraint_impl<"saba", ".8h",  VPR128, v8i16,
 530                     0b1, 0b0, 0b01, 0b01111, Neon_saba>;
 531 def SABAvvv_2S :  NeonI_3VSame_Constraint_impl<"saba", ".2s",  VPR64,  v2i32,
 532                     0b0, 0b0, 0b10, 0b01111, Neon_saba>;
 533 def SABAvvv_4S :  NeonI_3VSame_Constraint_impl<"saba", ".4s",  VPR128, v4i32,
 534                     0b1, 0b0, 0b10, 0b01111, Neon_saba>;
 535
 536
 537 // Vector Absolute Difference (Signed, Unsigned)
 538 defm UABDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01110, "uabd", int_arm_neon_vabdu, 0>;
 539 defm SABDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01110, "sabd", int_arm_neon_vabds, 0>;
 540
 541 // Vector Absolute Difference (Floating Point)
 542 defm FABDvvv: NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11010, "fabd",
 543                                     int_arm_neon_vabds, int_arm_neon_vabds,
 544                                     int_arm_neon_vabds, v2f32, v4f32, v2f64, 0>;
 545
 546 // Vector Reciprocal Step (Floating Point)
 547 defm FRECPSvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11111, "frecps",
 548                                        int_arm_neon_vrecps, int_arm_neon_vrecps,
 549                                        int_arm_neon_vrecps,
 550                                        v2f32, v4f32, v2f64, 0>;
 551
 552 // Vector Reciprocal Square Root Step (Floating Point)
 553 defm FRSQRTSvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11111, "frsqrts",
 554                                         int_arm_neon_vrsqrts,
 555                                         int_arm_neon_vrsqrts,
 556                                         int_arm_neon_vrsqrts,
 557                                         v2f32, v4f32, v2f64, 0>;
 558
 559 // Vector Comparisons
 560
 561 def Neon_cmeq : PatFrag<(ops node:$lhs, node:$rhs),
 562                         (Neon_cmp node:$lhs, node:$rhs, SETEQ)>;
 563 def Neon_cmphs : PatFrag<(ops node:$lhs, node:$rhs),
 564                          (Neon_cmp node:$lhs, node:$rhs, SETUGE)>;
 565 def Neon_cmge : PatFrag<(ops node:$lhs, node:$rhs),
 566                         (Neon_cmp node:$lhs, node:$rhs, SETGE)>;
 567 def Neon_cmhi : PatFrag<(ops node:$lhs, node:$rhs),
 568                         (Neon_cmp node:$lhs, node:$rhs, SETUGT)>;
 569 def Neon_cmgt : PatFrag<(ops node:$lhs, node:$rhs),
 570                         (Neon_cmp node:$lhs, node:$rhs, SETGT)>;
 571
 572 // NeonI_compare_aliases class: swaps register operands to implement
 573 // comparison aliases, e.g., CMLE is alias for CMGE with operands reversed.
 574 class NeonI_compare_aliases<string asmop, string asmlane,
 575                             Instruction inst, RegisterOperand VPRC>
 576   : NeonInstAlias<asmop # "\t$Rd" # asmlane #", $Rn" # asmlane #
 577                     ", $Rm" # asmlane,
 578                   (inst VPRC:$Rd, VPRC:$Rm, VPRC:$Rn), 0b0>;
 579
 580 // Vector Comparisons (Integer)
 581
 582 // Vector Compare Mask Equal (Integer)
 583 let isCommutable =1 in {
 584 defm CMEQvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10001, "cmeq", Neon_cmeq, 0>;
 585 }
 586
 587 // Vector Compare Mask Higher or Same (Unsigned Integer)
 588 defm CMHSvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00111, "cmhs", Neon_cmphs, 0>;
 589
 590 // Vector Compare Mask Greater Than or Equal (Integer)
 591 defm CMGEvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00111, "cmge", Neon_cmge, 0>;
 592
 593 // Vector Compare Mask Higher (Unsigned Integer)
 594 defm CMHIvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00110, "cmhi", Neon_cmhi, 0>;
 595
 596 // Vector Compare Mask Greater Than (Integer)
 597 defm CMGTvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00110, "cmgt", Neon_cmgt, 0>;
 598
 599 // Vector Compare Mask Bitwise Test (Integer)
 600 defm CMTSTvvv:  NeonI_3VSame_BHSD_sizes<0b0, 0b10001, "cmtst", Neon_tst, 0>;
 601
 602 // Vector Compare Mask Less or Same (Unsigned Integer)
 603 // CMLS is alias for CMHS with operands reversed.
 604 def CMLSvvv_8B  : NeonI_compare_aliases<"cmls", ".8b",  CMHSvvv_8B,  VPR64>;
 605 def CMLSvvv_16B : NeonI_compare_aliases<"cmls", ".16b", CMHSvvv_16B, VPR128>;
 606 def CMLSvvv_4H  : NeonI_compare_aliases<"cmls", ".4h",  CMHSvvv_4H,  VPR64>;
 607 def CMLSvvv_8H  : NeonI_compare_aliases<"cmls", ".8h",  CMHSvvv_8H,  VPR128>;
 608 def CMLSvvv_2S  : NeonI_compare_aliases<"cmls", ".2s",  CMHSvvv_2S,  VPR64>;
 609 def CMLSvvv_4S  : NeonI_compare_aliases<"cmls", ".4s",  CMHSvvv_4S,  VPR128>;
 610 def CMLSvvv_2D  : NeonI_compare_aliases<"cmls", ".2d",  CMHSvvv_2D,  VPR128>;
 611
 612 // Vector Compare Mask Less Than or Equal (Integer)
 613 // CMLE is alias for CMGE with operands reversed.
 614 def CMLEvvv_8B  : NeonI_compare_aliases<"cmle", ".8b",  CMGEvvv_8B,  VPR64>;
 615 def CMLEvvv_16B : NeonI_compare_aliases<"cmle", ".16b", CMGEvvv_16B, VPR128>;
 616 def CMLEvvv_4H  : NeonI_compare_aliases<"cmle", ".4h",  CMGEvvv_4H,  VPR64>;
 617 def CMLEvvv_8H  : NeonI_compare_aliases<"cmle", ".8h",  CMGEvvv_8H,  VPR128>;
 618 def CMLEvvv_2S  : NeonI_compare_aliases<"cmle", ".2s",  CMGEvvv_2S,  VPR64>;
 619 def CMLEvvv_4S  : NeonI_compare_aliases<"cmle", ".4s",  CMGEvvv_4S,  VPR128>;
 620 def CMLEvvv_2D  : NeonI_compare_aliases<"cmle", ".2d",  CMGEvvv_2D,  VPR128>;
 621
 622 // Vector Compare Mask Lower (Unsigned Integer)
 623 // CMLO is alias for CMHI with operands reversed.
 624 def CMLOvvv_8B  : NeonI_compare_aliases<"cmlo", ".8b",  CMHIvvv_8B,  VPR64>;
 625 def CMLOvvv_16B : NeonI_compare_aliases<"cmlo", ".16b", CMHIvvv_16B, VPR128>;
 626 def CMLOvvv_4H  : NeonI_compare_aliases<"cmlo", ".4h",  CMHIvvv_4H,  VPR64>;
 627 def CMLOvvv_8H  : NeonI_compare_aliases<"cmlo", ".8h",  CMHIvvv_8H,  VPR128>;
 628 def CMLOvvv_2S  : NeonI_compare_aliases<"cmlo", ".2s",  CMHIvvv_2S,  VPR64>;
 629 def CMLOvvv_4S  : NeonI_compare_aliases<"cmlo", ".4s",  CMHIvvv_4S,  VPR128>;
 630 def CMLOvvv_2D  : NeonI_compare_aliases<"cmlo", ".2d",  CMHIvvv_2D,  VPR128>;
 631
 632 // Vector Compare Mask Less Than (Integer)
 633 // CMLT is alias for CMGT with operands reversed.
 634 def CMLTvvv_8B  : NeonI_compare_aliases<"cmlt", ".8b",  CMGTvvv_8B,  VPR64>;
 635 def CMLTvvv_16B : NeonI_compare_aliases<"cmlt", ".16b", CMGTvvv_16B, VPR128>;
 636 def CMLTvvv_4H  : NeonI_compare_aliases<"cmlt", ".4h",  CMGTvvv_4H,  VPR64>;
 637 def CMLTvvv_8H  : NeonI_compare_aliases<"cmlt", ".8h",  CMGTvvv_8H,  VPR128>;
 638 def CMLTvvv_2S  : NeonI_compare_aliases<"cmlt", ".2s",  CMGTvvv_2S,  VPR64>;
 639 def CMLTvvv_4S  : NeonI_compare_aliases<"cmlt", ".4s",  CMGTvvv_4S,  VPR128>;
 640 def CMLTvvv_2D  : NeonI_compare_aliases<"cmlt", ".2d",  CMGTvvv_2D,  VPR128>;
 641
 642
 643 def neon_uimm0_asmoperand : AsmOperandClass
 644 {
 645   let Name = "UImm0";
 646   let PredicateMethod = "isUImm<0>";
 647   let RenderMethod = "addImmOperands";
 648 }
 649
 650 def neon_uimm0 : Operand<i32>, ImmLeaf<i32, [{return Imm == 0;}]> {
 651   let ParserMatchClass = neon_uimm0_asmoperand;
 652   let PrintMethod = "printNeonUImm0Operand";
 653
 654 }
 655
 656 multiclass NeonI_cmpz_sizes<bit u, bits<5> opcode, string asmop, CondCode CC>
 657 {
 658   def _8B :  NeonI_2VMisc<0b0, u, 0b00, opcode,
 659              (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 660              asmop # "\t$Rd.8b, $Rn.8b, $Imm",
 661              [(set (v8i8 VPR64:$Rd),
 662                 (v8i8 (Neon_cmpz (v8i8 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 663              NoItinerary>;
 664
 665   def _16B : NeonI_2VMisc<0b1, u, 0b00, opcode,
 666              (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 667              asmop # "\t$Rd.16b, $Rn.16b, $Imm",
 668              [(set (v16i8 VPR128:$Rd),
 669                 (v16i8 (Neon_cmpz (v16i8 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 670              NoItinerary>;
 671
 672   def _4H : NeonI_2VMisc<0b0, u, 0b01, opcode,
 673             (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 674             asmop # "\t$Rd.4h, $Rn.4h, $Imm",
 675             [(set (v4i16 VPR64:$Rd),
 676                (v4i16 (Neon_cmpz (v4i16 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 677             NoItinerary>;
 678
 679   def _8H : NeonI_2VMisc<0b1, u, 0b01, opcode,
 680             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 681             asmop # "\t$Rd.8h, $Rn.8h, $Imm",
 682             [(set (v8i16 VPR128:$Rd),
 683                (v8i16 (Neon_cmpz (v8i16 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 684             NoItinerary>;
 685
 686   def _2S : NeonI_2VMisc<0b0, u, 0b10, opcode,
 687             (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 688             asmop # "\t$Rd.2s, $Rn.2s, $Imm",
 689             [(set (v2i32 VPR64:$Rd),
 690                (v2i32 (Neon_cmpz (v2i32 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 691             NoItinerary>;
 692
 693   def _4S : NeonI_2VMisc<0b1, u, 0b10, opcode,
 694             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 695             asmop # "\t$Rd.4s, $Rn.4s, $Imm",
 696             [(set (v4i32 VPR128:$Rd),
 697                (v4i32 (Neon_cmpz (v4i32 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 698             NoItinerary>;
 699
 700   def _2D : NeonI_2VMisc<0b1, u, 0b11, opcode,
 701             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 702             asmop # "\t$Rd.2d, $Rn.2d, $Imm",
 703             [(set (v2i64 VPR128:$Rd),
 704                (v2i64 (Neon_cmpz (v2i64 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 705             NoItinerary>;
 706 }
 707
 708 // Vector Compare Mask Equal to Zero (Integer)
 709 defm CMEQvvi : NeonI_cmpz_sizes<0b0, 0b01001, "cmeq", SETEQ>;
 710
 711 // Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
 712 defm CMGEvvi : NeonI_cmpz_sizes<0b1, 0b01000, "cmge", SETGE>;
 713
 714 // Vector Compare Mask Greater Than Zero (Signed Integer)
 715 defm CMGTvvi : NeonI_cmpz_sizes<0b0, 0b01000, "cmgt", SETGT>;
 716
 717 // Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
 718 defm CMLEvvi : NeonI_cmpz_sizes<0b1, 0b01001, "cmle", SETLE>;
 719
 720 // Vector Compare Mask Less Than Zero (Signed Integer)
 721 defm CMLTvvi : NeonI_cmpz_sizes<0b0, 0b01010, "cmlt", SETLT>;
 722
 723 // Vector Comparisons (Floating Point)
 724
 725 // Vector Compare Mask Equal (Floating Point)
 726 let isCommutable =1 in {
 727 defm FCMEQvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11100, "fcmeq", Neon_cmeq,
 728                                       Neon_cmeq, Neon_cmeq,
 729                                       v2i32, v4i32, v2i64, 0>;
 730 }
 731
 732 // Vector Compare Mask Greater Than Or Equal (Floating Point)
 733 defm FCMGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11100, "fcmge", Neon_cmge,
 734                                       Neon_cmge, Neon_cmge,
 735                                       v2i32, v4i32, v2i64, 0>;
 736
 737 // Vector Compare Mask Greater Than (Floating Point)
 738 defm FCMGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11100, "fcmgt", Neon_cmgt,
 739                                       Neon_cmgt, Neon_cmgt,
 740                                       v2i32, v4i32, v2i64, 0>;
 741
 742 // Vector Compare Mask Less Than Or Equal (Floating Point)
 743 // FCMLE is alias for FCMGE with operands reversed.
 744 def FCMLEvvv_2S  : NeonI_compare_aliases<"fcmle", ".2s",  FCMGEvvv_2S,  VPR64>;
 745 def FCMLEvvv_4S  : NeonI_compare_aliases<"fcmle", ".4s",  FCMGEvvv_4S,  VPR128>;
 746 def FCMLEvvv_2D  : NeonI_compare_aliases<"fcmle", ".2d",  FCMGEvvv_2D,  VPR128>;
 747
 748 // Vector Compare Mask Less Than (Floating Point)
 749 // FCMLT is alias for FCMGT with operands reversed.
 750 def FCMLTvvv_2S  : NeonI_compare_aliases<"fcmlt", ".2s",  FCMGTvvv_2S,  VPR64>;
 751 def FCMLTvvv_4S  : NeonI_compare_aliases<"fcmlt", ".4s",  FCMGTvvv_4S,  VPR128>;
 752 def FCMLTvvv_2D  : NeonI_compare_aliases<"fcmlt", ".2d",  FCMGTvvv_2D,  VPR128>;
 753
 754
 755 multiclass NeonI_fpcmpz_sizes<bit u, bit size, bits<5> opcode,
 756                               string asmop, CondCode CC>
 757 {
 758   def _2S : NeonI_2VMisc<0b0, u, {size, 0b0}, opcode,
 759             (outs VPR64:$Rd), (ins VPR64:$Rn, fpz32:$FPImm),
 760             asmop # "\t$Rd.2s, $Rn.2s, $FPImm",
 761             [(set (v2i32 VPR64:$Rd),
 762                (v2i32 (Neon_cmpz (v2f32 VPR64:$Rn), (f32 fpimm:$FPImm), CC)))],
 763             NoItinerary>;
 764
 765   def _4S : NeonI_2VMisc<0b1, u, {size, 0b0}, opcode,
 766             (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
 767             asmop # "\t$Rd.4s, $Rn.4s, $FPImm",
 768             [(set (v4i32 VPR128:$Rd),
 769                (v4i32 (Neon_cmpz (v4f32 VPR128:$Rn), (f32 fpimm:$FPImm), CC)))],
 770             NoItinerary>;
 771
 772   def _2D : NeonI_2VMisc<0b1, u, {size, 0b1}, opcode,
 773             (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
 774             asmop # "\t$Rd.2d, $Rn.2d, $FPImm",
 775             [(set (v2i64 VPR128:$Rd),
 776                (v2i64 (Neon_cmpz (v2f64 VPR128:$Rn), (f32 fpimm:$FPImm), CC)))],
 777             NoItinerary>;
 778 }
 779
 780 // Vector Compare Mask Equal to Zero (Floating Point)
 781 defm FCMEQvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01101, "fcmeq", SETEQ>;
 782
 783 // Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
 784 defm FCMGEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01100, "fcmge", SETGE>;
 785
 786 // Vector Compare Mask Greater Than Zero (Floating Point)
 787 defm FCMGTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01100, "fcmgt", SETGT>;
 788
 789 // Vector Compare Mask Less Than or Equal To Zero (Floating Point)
 790 defm FCMLEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01101, "fcmle", SETLE>;
 791
 792 // Vector Compare Mask Less Than Zero (Floating Point)
 793 defm FCMLTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01110, "fcmlt", SETLT>;
 794
 795 // Vector Absolute Comparisons (Floating Point)
 796
 797 // Vector Absolute Compare Mask Greater Than Or Equal (Floating Point)
 798 defm FACGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11101, "facge",
 799                                       int_arm_neon_vacged, int_arm_neon_vacgeq,
 800                                       int_aarch64_neon_vacgeq,
 801                                       v2i32, v4i32, v2i64, 0>;
 802
 803 // Vector Absolute Compare Mask Greater Than (Floating Point)
 804 defm FACGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11101, "facgt",
 805                                       int_arm_neon_vacgtd, int_arm_neon_vacgtq,
 806                                       int_aarch64_neon_vacgtq,
 807                                       v2i32, v4i32, v2i64, 0>;
 808
 809 // Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
 810 // FACLE is alias for FACGE with operands reversed.
 811 def FACLEvvv_2S  : NeonI_compare_aliases<"facle", ".2s",  FACGEvvv_2S,  VPR64>;
 812 def FACLEvvv_4S  : NeonI_compare_aliases<"facle", ".4s",  FACGEvvv_4S,  VPR128>;
 813 def FACLEvvv_2D  : NeonI_compare_aliases<"facle", ".2d",  FACGEvvv_2D,  VPR128>;
 814
 815 // Vector Absolute Compare Mask Less Than (Floating Point)
 816 // FACLT is alias for FACGT with operands reversed.
 817 def FACLTvvv_2S  : NeonI_compare_aliases<"faclt", ".2s",  FACGTvvv_2S,  VPR64>;
 818 def FACLTvvv_4S  : NeonI_compare_aliases<"faclt", ".4s",  FACGTvvv_4S,  VPR128>;
 819 def FACLTvvv_2D  : NeonI_compare_aliases<"faclt", ".2d",  FACGTvvv_2D,  VPR128>;
 820
 821 // Vector halving add (Integer Signed, Unsigned)
 822 defm SHADDvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00000, "shadd",
 823                                         int_arm_neon_vhadds, 1>;
 824 defm UHADDvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00000, "uhadd",
 825                                         int_arm_neon_vhaddu, 1>;
 826
 827 // Vector halving sub (Integer Signed, Unsigned)
 828 defm SHSUBvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00100, "shsub",
 829                                         int_arm_neon_vhsubs, 0>;
 830 defm UHSUBvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00100, "uhsub",
 831                                         int_arm_neon_vhsubu, 0>;
 832
 833 // Vector rouding halving add (Integer Signed, Unsigned)
 834 defm SRHADDvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00010, "srhadd",
 835                                          int_arm_neon_vrhadds, 1>;
 836 defm URHADDvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00010, "urhadd",
 837                                          int_arm_neon_vrhaddu, 1>;
 838
 839 // Vector Saturating add (Integer Signed, Unsigned)
 840 defm SQADDvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b00001, "sqadd",
 841                    int_arm_neon_vqadds, 1>;
 842 defm UQADDvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b00001, "uqadd",
 843                    int_arm_neon_vqaddu, 1>;
 844
 845 // Vector Saturating sub (Integer Signed, Unsigned)
 846 defm SQSUBvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b00101, "sqsub",
 847                    int_arm_neon_vqsubs, 1>;
 848 defm UQSUBvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b00101, "uqsub",
 849                    int_arm_neon_vqsubu, 1>;
 850
 851 // Vector Shift Left (Signed and Unsigned Integer)
 852 defm SSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01000, "sshl",
 853                  int_arm_neon_vshifts, 1>;
 854 defm USHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01000, "ushl",
 855                  int_arm_neon_vshiftu, 1>;
 856
 857 // Vector Saturating Shift Left (Signed and Unsigned Integer)
 858 defm SQSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01001, "sqshl",
 859                   int_arm_neon_vqshifts, 1>;
 860 defm UQSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01001, "uqshl",
 861                   int_arm_neon_vqshiftu, 1>;
 862
 863 // Vector Rouding Shift Left (Signed and Unsigned Integer)
 864 defm SRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01010, "srshl",
 865                   int_arm_neon_vrshifts, 1>;
 866 defm URSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01010, "urshl",
 867                   int_arm_neon_vrshiftu, 1>;
 868
 869 // Vector Saturating Rouding Shift Left (Signed and Unsigned Integer)
 870 defm SQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01011, "sqrshl",
 871                    int_arm_neon_vqrshifts, 1>;
 872 defm UQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01011, "uqrshl",
 873                    int_arm_neon_vqrshiftu, 1>;
 874
 875 // Vector Maximum (Signed and Unsigned Integer)
 876 defm SMAXvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01100, "smax", int_arm_neon_vmaxs, 1>;
 877 defm UMAXvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01100, "umax", int_arm_neon_vmaxu, 1>;
 878
 879 // Vector Minimum (Signed and Unsigned Integer)
 880 defm SMINvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01101, "smin", int_arm_neon_vmins, 1>;
 881 defm UMINvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01101, "umin", int_arm_neon_vminu, 1>;
 882
 883 // Vector Maximum (Floating Point)
 884 defm FMAXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11110, "fmax",
 885                                      int_arm_neon_vmaxs, int_arm_neon_vmaxs,
 886                                      int_arm_neon_vmaxs, v2f32, v4f32, v2f64, 1>;
 887
 888 // Vector Minimum (Floating Point)
 889 defm FMINvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11110, "fmin",
 890                                      int_arm_neon_vmins, int_arm_neon_vmins,
 891                                      int_arm_neon_vmins, v2f32, v4f32, v2f64, 1>;
 892
 893 // Vector maxNum (Floating Point) -  prefer a number over a quiet NaN)
 894 defm FMAXNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11000, "fmaxnm",
 895                                        int_aarch64_neon_vmaxnm,
 896                                        int_aarch64_neon_vmaxnm,
 897                                        int_aarch64_neon_vmaxnm,
 898                                        v2f32, v4f32, v2f64, 1>;
 899
 900 // Vector minNum (Floating Point) - prefer a number over a quiet NaN)
 901 defm FMINNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11000, "fminnm",
 902                                        int_aarch64_neon_vminnm,
 903                                        int_aarch64_neon_vminnm,
 904                                        int_aarch64_neon_vminnm,
 905                                        v2f32, v4f32, v2f64, 1>;
 906
 907 // Vector Maximum Pairwise (Signed and Unsigned Integer)
 908 defm SMAXPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10100, "smaxp", int_arm_neon_vpmaxs, 1>;
 909 defm UMAXPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10100, "umaxp", int_arm_neon_vpmaxu, 1>;
 910
 911 // Vector Minimum Pairwise (Signed and Unsigned Integer)
 912 defm SMINPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10101, "sminp", int_arm_neon_vpmins, 1>;
 913 defm UMINPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10101, "uminp", int_arm_neon_vpminu, 1>;
 914
 915 // Vector Maximum Pairwise (Floating Point)
 916 defm FMAXPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11110, "fmaxp",
 917                                      int_arm_neon_vpmaxs, int_arm_neon_vpmaxs,
 918                                      int_arm_neon_vpmaxs, v2f32, v4f32, v2f64, 1>;
 919
 920 // Vector Minimum Pairwise (Floating Point)
 921 defm FMINPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11110, "fminp",
 922                                      int_arm_neon_vpmins, int_arm_neon_vpmins,
 923                                      int_arm_neon_vpmins, v2f32, v4f32, v2f64, 1>;
 924
 925 // Vector maxNum Pairwise (Floating Point) -  prefer a number over a quiet NaN)
 926 defm FMAXNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11000, "fmaxnmp",
 927                                        int_aarch64_neon_vpmaxnm,
 928                                        int_aarch64_neon_vpmaxnm,
 929                                        int_aarch64_neon_vpmaxnm,
 930                                        v2f32, v4f32, v2f64, 1>;
 931
 932 // Vector minNum Pairwise (Floating Point) -  prefer a number over a quiet NaN)
 933 defm FMINNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11000, "fminnmp",
 934                                        int_aarch64_neon_vpminnm,
 935                                        int_aarch64_neon_vpminnm,
 936                                        int_aarch64_neon_vpminnm,
 937                                        v2f32, v4f32, v2f64, 1>;
 938
 939 // Vector Addition Pairwise (Integer)
 940 defm ADDP : NeonI_3VSame_BHSD_sizes<0b0, 0b10111, "addp", int_arm_neon_vpadd, 1>;
 941
 942 // Vector Addition Pairwise (Floating Point)
 943 defm FADDP : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11010, "faddp",
 944                                        int_arm_neon_vpadd,
 945                                        int_arm_neon_vpadd,
 946                                        int_arm_neon_vpadd,
 947                                        v2f32, v4f32, v2f64, 1>;
 948
 949 // Vector Saturating Doubling Multiply High
 950 defm SQDMULHvvv : NeonI_3VSame_HS_sizes<0b0, 0b10110, "sqdmulh",
 951                     int_arm_neon_vqdmulh, 1>;
 952
 953 // Vector Saturating Rouding Doubling Multiply High
 954 defm SQRDMULHvvv : NeonI_3VSame_HS_sizes<0b1, 0b10110, "sqrdmulh",
 955                      int_arm_neon_vqrdmulh, 1>;
 956
 957 // Vector Multiply Extended (Floating Point)
 958 defm FMULXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11011, "fmulx",
 959                                       int_aarch64_neon_vmulx,
 960                                       int_aarch64_neon_vmulx,
 961                                       int_aarch64_neon_vmulx,
 962                                       v2f32, v4f32, v2f64, 1>;
 963
 964 // Vector Immediate Instructions
 965
 966 multiclass neon_mov_imm_shift_asmoperands<string PREFIX>
 967 {
 968   def _asmoperand : AsmOperandClass
 969     {
 970       let Name = "NeonMovImmShift" # PREFIX;
 971       let RenderMethod = "addNeonMovImmShift" # PREFIX # "Operands";
 972       let PredicateMethod = "isNeonMovImmShift" # PREFIX;
 973     }
 974 }
 975
 976 // Definition of vector immediates shift operands
 977
 978 // The selectable use-cases extract the shift operation
 979 // information from the OpCmode fields encoded in the immediate.
 980 def neon_mod_shift_imm_XFORM : SDNodeXForm<imm, [{
 981   uint64_t OpCmode = N->getZExtValue();
 982   unsigned ShiftImm;
 983   unsigned ShiftOnesIn;
 984   unsigned HasShift =
 985     A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
 986   if (!HasShift) return SDValue();
 987   return CurDAG->getTargetConstant(ShiftImm, MVT::i32);
 988 }]>;
 989
 990 // Vector immediates shift operands which accept LSL and MSL
 991 // shift operators with shift value in the range of 0, 8, 16, 24 (LSL),
 992 // or 0, 8 (LSLH) or 8, 16 (MSL).
 993 defm neon_mov_imm_LSL : neon_mov_imm_shift_asmoperands<"LSL">;
 994 defm neon_mov_imm_MSL : neon_mov_imm_shift_asmoperands<"MSL">;
 995 // LSLH restricts shift amount to  0, 8 out of 0, 8, 16, 24
 996 defm neon_mov_imm_LSLH : neon_mov_imm_shift_asmoperands<"LSLH">;
 997
 998 multiclass neon_mov_imm_shift_operands<string PREFIX,
 999                                        string HALF, string ISHALF, code pred>
1000 {
1001    def _operand : Operand<i32>, ImmLeaf<i32, pred, neon_mod_shift_imm_XFORM>
1002     {
1003       let PrintMethod =
1004         "printNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1005       let DecoderMethod =
1006         "DecodeNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1007       let ParserMatchClass =
1008         !cast<AsmOperandClass>("neon_mov_imm_" # PREFIX # HALF # "_asmoperand");
1009     }
1010 }
1011
1012 defm neon_mov_imm_LSL  : neon_mov_imm_shift_operands<"LSL", "", "false", [{
1013   unsigned ShiftImm;
1014   unsigned ShiftOnesIn;
1015   unsigned HasShift =
1016     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1017   return (HasShift && !ShiftOnesIn);
1018 }]>;
1019
1020 defm neon_mov_imm_MSL  : neon_mov_imm_shift_operands<"MSL", "", "false", [{
1021   unsigned ShiftImm;
1022   unsigned ShiftOnesIn;
1023   unsigned HasShift =
1024     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1025   return (HasShift && ShiftOnesIn);
1026 }]>;
1027
1028 defm neon_mov_imm_LSLH  : neon_mov_imm_shift_operands<"LSL", "H", "true", [{
1029   unsigned ShiftImm;
1030   unsigned ShiftOnesIn;
1031   unsigned HasShift =
1032     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1033   return (HasShift && !ShiftOnesIn);
1034 }]>;
1035
1036 def neon_uimm1_asmoperand : AsmOperandClass
1037 {
1038   let Name = "UImm1";
1039   let PredicateMethod = "isUImm<1>";
1040   let RenderMethod = "addImmOperands";
1041 }
1042
1043 def neon_uimm2_asmoperand : AsmOperandClass
1044 {
1045   let Name = "UImm2";
1046   let PredicateMethod = "isUImm<2>";
1047   let RenderMethod = "addImmOperands";
1048 }
1049
1050 def neon_uimm8_asmoperand : AsmOperandClass
1051 {
1052   let Name = "UImm8";
1053   let PredicateMethod = "isUImm<8>";
1054   let RenderMethod = "addImmOperands";
1055 }
1056
1057 def neon_uimm8 : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1058   let ParserMatchClass = neon_uimm8_asmoperand;
1059   let PrintMethod = "printUImmHexOperand";
1060 }
1061
1062 def neon_uimm64_mask_asmoperand : AsmOperandClass
1063 {
1064   let Name = "NeonUImm64Mask";
1065   let PredicateMethod = "isNeonUImm64Mask";
1066   let RenderMethod = "addNeonUImm64MaskOperands";
1067 }
1068
1069 // MCOperand for 64-bit bytemask with each byte having only the
1070 // value 0x00 and 0xff is encoded as an unsigned 8-bit value
1071 def neon_uimm64_mask : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1072   let ParserMatchClass = neon_uimm64_mask_asmoperand;
1073   let PrintMethod = "printNeonUImm64MaskOperand";
1074 }
1075
1076 multiclass NeonI_mov_imm_lsl_sizes<string asmop, bit op,
1077                                    SDPatternOperator opnode>
1078 {
1079     // shift zeros, per word
1080     def _2S  : NeonI_1VModImm<0b0, op,
1081                               (outs VPR64:$Rd),
1082                               (ins neon_uimm8:$Imm,
1083                                 neon_mov_imm_LSL_operand:$Simm),
1084                               !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1085                               [(set (v2i32 VPR64:$Rd),
1086                                  (v2i32 (opnode (timm:$Imm),
1087                                    (neon_mov_imm_LSL_operand:$Simm))))],
1088                               NoItinerary> {
1089        bits<2> Simm;
1090        let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1091      }
1092
1093     def _4S  : NeonI_1VModImm<0b1, op,
1094                               (outs VPR128:$Rd),
1095                               (ins neon_uimm8:$Imm,
1096                                 neon_mov_imm_LSL_operand:$Simm),
1097                               !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1098                               [(set (v4i32 VPR128:$Rd),
1099                                  (v4i32 (opnode (timm:$Imm),
1100                                    (neon_mov_imm_LSL_operand:$Simm))))],
1101                               NoItinerary> {
1102       bits<2> Simm;
1103       let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1104     }
1105
1106     // shift zeros, per halfword
1107     def _4H  : NeonI_1VModImm<0b0, op,
1108                               (outs VPR64:$Rd),
1109                               (ins neon_uimm8:$Imm,
1110                                 neon_mov_imm_LSLH_operand:$Simm),
1111                               !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1112                               [(set (v4i16 VPR64:$Rd),
1113                                  (v4i16 (opnode (timm:$Imm),
1114                                    (neon_mov_imm_LSLH_operand:$Simm))))],
1115                               NoItinerary> {
1116       bit  Simm;
1117       let cmode = {0b1, 0b0, Simm, 0b0};
1118     }
1119
1120     def _8H  : NeonI_1VModImm<0b1, op,
1121                               (outs VPR128:$Rd),
1122                               (ins neon_uimm8:$Imm,
1123                                 neon_mov_imm_LSLH_operand:$Simm),
1124                               !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1125                               [(set (v8i16 VPR128:$Rd),
1126                                  (v8i16 (opnode (timm:$Imm),
1127                                    (neon_mov_imm_LSLH_operand:$Simm))))],
1128                               NoItinerary> {
1129       bit Simm;
1130       let cmode = {0b1, 0b0, Simm, 0b0};
1131      }
1132 }
1133
1134 multiclass NeonI_mov_imm_with_constraint_lsl_sizes<string asmop, bit op,
1135                                                    SDPatternOperator opnode,
1136                                                    SDPatternOperator neonopnode>
1137 {
1138   let Constraints = "$src = $Rd" in {
1139     // shift zeros, per word
1140     def _2S  : NeonI_1VModImm<0b0, op,
1141                  (outs VPR64:$Rd),
1142                  (ins VPR64:$src, neon_uimm8:$Imm,
1143                    neon_mov_imm_LSL_operand:$Simm),
1144                  !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1145                  [(set (v2i32 VPR64:$Rd),
1146                     (v2i32 (opnode (v2i32 VPR64:$src),
1147                       (v2i32 (bitconvert (v2i32 (neonopnode timm:$Imm,
1148                         neon_mov_imm_LSL_operand:$Simm)))))))],
1149                  NoItinerary> {
1150       bits<2> Simm;
1151       let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1152     }
1153
1154     def _4S  : NeonI_1VModImm<0b1, op,
1155                  (outs VPR128:$Rd),
1156                  (ins VPR128:$src, neon_uimm8:$Imm,
1157                    neon_mov_imm_LSL_operand:$Simm),
1158                  !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1159                  [(set (v4i32 VPR128:$Rd),
1160                     (v4i32 (opnode (v4i32 VPR128:$src),
1161                       (v4i32 (bitconvert (v4i32 (neonopnode timm:$Imm,
1162                         neon_mov_imm_LSL_operand:$Simm)))))))],
1163                  NoItinerary> {
1164       bits<2> Simm;
1165       let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1166     }
1167
1168     // shift zeros, per halfword
1169     def _4H  : NeonI_1VModImm<0b0, op,
1170                  (outs VPR64:$Rd),
1171                  (ins VPR64:$src, neon_uimm8:$Imm,
1172                    neon_mov_imm_LSLH_operand:$Simm),
1173                  !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1174                  [(set (v4i16 VPR64:$Rd),
1175                     (v4i16 (opnode (v4i16 VPR64:$src),
1176                        (v4i16 (bitconvert (v4i16 (neonopnode timm:$Imm,
1177                           neon_mov_imm_LSL_operand:$Simm)))))))],
1178                  NoItinerary> {
1179       bit  Simm;
1180       let cmode = {0b1, 0b0, Simm, 0b1};
1181     }
1182
1183     def _8H  : NeonI_1VModImm<0b1, op,
1184                  (outs VPR128:$Rd),
1185                  (ins VPR128:$src, neon_uimm8:$Imm,
1186                    neon_mov_imm_LSLH_operand:$Simm),
1187                  !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1188                  [(set (v8i16 VPR128:$Rd),
1189                     (v8i16 (opnode (v8i16 VPR128:$src),
1190                       (v8i16 (bitconvert (v8i16 (neonopnode timm:$Imm,
1191                         neon_mov_imm_LSL_operand:$Simm)))))))],
1192                  NoItinerary> {
1193       bit Simm;
1194       let cmode = {0b1, 0b0, Simm, 0b1};
1195     }
1196   }
1197 }
1198
1199 multiclass NeonI_mov_imm_msl_sizes<string asmop, bit op,
1200                                    SDPatternOperator opnode>
1201 {
1202     // shift ones, per word
1203     def _2S  : NeonI_1VModImm<0b0, op,
1204                              (outs VPR64:$Rd),
1205                              (ins neon_uimm8:$Imm,
1206                                neon_mov_imm_MSL_operand:$Simm),
1207                              !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1208                               [(set (v2i32 VPR64:$Rd),
1209                                  (v2i32 (opnode (timm:$Imm),
1210                                    (neon_mov_imm_MSL_operand:$Simm))))],
1211                              NoItinerary> {
1212        bit Simm;
1213        let cmode = {0b1, 0b1, 0b0, Simm};
1214      }
1215
1216    def _4S  : NeonI_1VModImm<0b1, op,
1217                               (outs VPR128:$Rd),
1218                               (ins neon_uimm8:$Imm,
1219                                 neon_mov_imm_MSL_operand:$Simm),
1220                               !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1221                               [(set (v4i32 VPR128:$Rd),
1222                                  (v4i32 (opnode (timm:$Imm),
1223                                    (neon_mov_imm_MSL_operand:$Simm))))],
1224                               NoItinerary> {
1225      bit Simm;
1226      let cmode = {0b1, 0b1, 0b0, Simm};
1227    }
1228 }
1229
1230 // Vector Move Immediate Shifted
1231 let isReMaterializable = 1 in {
1232 defm MOVIvi_lsl : NeonI_mov_imm_lsl_sizes<"movi", 0b0, Neon_movi>;
1233 }
1234
1235 // Vector Move Inverted Immediate Shifted
1236 let isReMaterializable = 1 in {
1237 defm MVNIvi_lsl : NeonI_mov_imm_lsl_sizes<"mvni", 0b1, Neon_mvni>;
1238 }
1239
1240 // Vector Bitwise Bit Clear (AND NOT) - immediate
1241 let isReMaterializable = 1 in {
1242 defm BICvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"bic", 0b1,
1243                                                          and, Neon_mvni>;
1244 }
1245
1246 // Vector Bitwise OR - immedidate
1247
1248 let isReMaterializable = 1 in {
1249 defm ORRvi_lsl   : NeonI_mov_imm_with_constraint_lsl_sizes<"orr", 0b0,
1250                                                            or, Neon_movi>;
1251 }
1252
1253 // Additional patterns for Vector Bitwise Bit Clear (AND NOT) - immedidate
1254 // LowerBUILD_VECTOR favors lowering MOVI over MVNI.
1255 // BIC immediate instructions selection requires additional patterns to
1256 // transform Neon_movi operands into BIC immediate operands
1257
1258 def neon_mov_imm_LSLH_transform_XFORM : SDNodeXForm<imm, [{
1259   uint64_t OpCmode = N->getZExtValue();
1260   unsigned ShiftImm;
1261   unsigned ShiftOnesIn;
1262   (void)A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1263   // LSLH restricts shift amount to  0, 8 which are encoded as 0 and 1
1264   // Transform encoded shift amount 0 to 1 and 1 to 0.
1265   return CurDAG->getTargetConstant(!ShiftImm, MVT::i32);
1266 }]>;
1267
1268 def neon_mov_imm_LSLH_transform_operand
1269   : ImmLeaf<i32, [{
1270     unsigned ShiftImm;
1271     unsigned ShiftOnesIn;
1272     unsigned HasShift =
1273       A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1274     return (HasShift && !ShiftOnesIn); }],
1275   neon_mov_imm_LSLH_transform_XFORM>;
1276
1277 // Transform (and A, (4h Neon_movi 0xff)) -> BIC 4h (A, 0x00, LSL 8)
1278 // Transform (and A, (4h Neon_movi 0xff LSL #8)) -> BIC 4h (A, 0x00)
1279 def : Pat<(v4i16 (and VPR64:$src,
1280             (v4i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1281           (BICvi_lsl_4H VPR64:$src, 0,
1282             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1283
1284 // Transform (and A, (8h Neon_movi 8h 0xff)) -> BIC 8h (A, 0x00, LSL 8)
1285 // Transform (and A, (8h Neon_movi 0xff LSL #8)) -> BIC 8h (A, 0x00)
1286 def : Pat<(v8i16 (and VPR128:$src,
1287             (v8i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1288           (BICvi_lsl_8H VPR128:$src, 0,
1289             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1290
1291
1292 multiclass Neon_bitwiseVi_patterns<SDPatternOperator opnode,
1293                                    SDPatternOperator neonopnode,
1294                                    Instruction INST4H,
1295                                    Instruction INST8H> {
1296   def : Pat<(v8i8 (opnode VPR64:$src,
1297                     (bitconvert(v4i16 (neonopnode timm:$Imm,
1298                       neon_mov_imm_LSLH_operand:$Simm))))),
1299             (INST4H VPR64:$src, neon_uimm8:$Imm,
1300               neon_mov_imm_LSLH_operand:$Simm)>;
1301   def : Pat<(v1i64 (opnode VPR64:$src,
1302                   (bitconvert(v4i16 (neonopnode timm:$Imm,
1303                     neon_mov_imm_LSLH_operand:$Simm))))),
1304           (INST4H VPR64:$src, neon_uimm8:$Imm,
1305             neon_mov_imm_LSLH_operand:$Simm)>;
1306
1307   def : Pat<(v16i8 (opnode VPR128:$src,
1308                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1309                      neon_mov_imm_LSLH_operand:$Simm))))),
1310           (INST8H VPR128:$src, neon_uimm8:$Imm,
1311             neon_mov_imm_LSLH_operand:$Simm)>;
1312   def : Pat<(v4i32 (opnode VPR128:$src,
1313                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1314                      neon_mov_imm_LSLH_operand:$Simm))))),
1315           (INST8H VPR128:$src, neon_uimm8:$Imm,
1316             neon_mov_imm_LSLH_operand:$Simm)>;
1317   def : Pat<(v2i64 (opnode VPR128:$src,
1318                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1319                      neon_mov_imm_LSLH_operand:$Simm))))),
1320           (INST8H VPR128:$src, neon_uimm8:$Imm,
1321             neon_mov_imm_LSLH_operand:$Simm)>;
1322 }
1323
1324 // Additional patterns for Vector Vector Bitwise Bit Clear (AND NOT) - immediate
1325 defm : Neon_bitwiseVi_patterns<or, Neon_mvni, BICvi_lsl_4H, BICvi_lsl_8H>;
1326
1327 // Additional patterns for Vector Bitwise OR - immedidate
1328 defm : Neon_bitwiseVi_patterns<or, Neon_movi, ORRvi_lsl_4H, ORRvi_lsl_8H>;
1329
1330
1331 // Vector Move Immediate Masked
1332 let isReMaterializable = 1 in {
1333 defm MOVIvi_msl : NeonI_mov_imm_msl_sizes<"movi", 0b0, Neon_movi>;
1334 }
1335
1336 // Vector Move Inverted Immediate Masked
1337 let isReMaterializable = 1 in {
1338 defm MVNIvi_msl : NeonI_mov_imm_msl_sizes<"mvni", 0b1, Neon_mvni>;
1339 }
1340
1341 class NeonI_mov_imm_lsl_aliases<string asmop, string asmlane,
1342                                 Instruction inst, RegisterOperand VPRC>
1343   : NeonInstAlias<!strconcat(asmop, "\t$Rd," # asmlane # ", $Imm"),
1344                         (inst VPRC:$Rd, neon_uimm8:$Imm,  0), 0b0>;
1345
1346 // Aliases for Vector Move Immediate Shifted
1347 def : NeonI_mov_imm_lsl_aliases<"movi", ".2s", MOVIvi_lsl_2S, VPR64>;
1348 def : NeonI_mov_imm_lsl_aliases<"movi", ".4s", MOVIvi_lsl_4S, VPR128>;
1349 def : NeonI_mov_imm_lsl_aliases<"movi", ".4h", MOVIvi_lsl_4H, VPR64>;
1350 def : NeonI_mov_imm_lsl_aliases<"movi", ".8h", MOVIvi_lsl_8H, VPR128>;
1351
1352 // Aliases for Vector Move Inverted Immediate Shifted
1353 def : NeonI_mov_imm_lsl_aliases<"mvni", ".2s", MVNIvi_lsl_2S, VPR64>;
1354 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4s", MVNIvi_lsl_4S, VPR128>;
1355 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4h", MVNIvi_lsl_4H, VPR64>;
1356 def : NeonI_mov_imm_lsl_aliases<"mvni", ".8h", MVNIvi_lsl_8H, VPR128>;
1357
1358 // Aliases for Vector Bitwise Bit Clear (AND NOT) - immediate
1359 def : NeonI_mov_imm_lsl_aliases<"bic", ".2s", BICvi_lsl_2S, VPR64>;
1360 def : NeonI_mov_imm_lsl_aliases<"bic", ".4s", BICvi_lsl_4S, VPR128>;
1361 def : NeonI_mov_imm_lsl_aliases<"bic", ".4h", BICvi_lsl_4H, VPR64>;
1362 def : NeonI_mov_imm_lsl_aliases<"bic", ".8h", BICvi_lsl_8H, VPR128>;
1363
1364 // Aliases for Vector Bitwise OR - immedidate
1365 def : NeonI_mov_imm_lsl_aliases<"orr", ".2s", ORRvi_lsl_2S, VPR64>;
1366 def : NeonI_mov_imm_lsl_aliases<"orr", ".4s", ORRvi_lsl_4S, VPR128>;
1367 def : NeonI_mov_imm_lsl_aliases<"orr", ".4h", ORRvi_lsl_4H, VPR64>;
1368 def : NeonI_mov_imm_lsl_aliases<"orr", ".8h", ORRvi_lsl_8H, VPR128>;
1369
1370 //  Vector Move Immediate - per byte
1371 let isReMaterializable = 1 in {
1372 def MOVIvi_8B : NeonI_1VModImm<0b0, 0b0,
1373                                (outs VPR64:$Rd), (ins neon_uimm8:$Imm),
1374                                "movi\t$Rd.8b, $Imm",
1375                                [(set (v8i8 VPR64:$Rd),
1376                                   (v8i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1377                                 NoItinerary> {
1378   let cmode = 0b1110;
1379 }
1380
1381 def MOVIvi_16B : NeonI_1VModImm<0b1, 0b0,
1382                                 (outs VPR128:$Rd), (ins neon_uimm8:$Imm),
1383                                 "movi\t$Rd.16b, $Imm",
1384                                 [(set (v16i8 VPR128:$Rd),
1385                                    (v16i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1386                                  NoItinerary> {
1387   let cmode = 0b1110;
1388 }
1389 }
1390
1391 // Vector Move Immediate - bytemask, per double word
1392 let isReMaterializable = 1 in {
1393 def MOVIvi_2D : NeonI_1VModImm<0b1, 0b1,
1394                                (outs VPR128:$Rd), (ins neon_uimm64_mask:$Imm),
1395                                "movi\t $Rd.2d, $Imm",
1396                                [(set (v2i64 VPR128:$Rd),
1397                                   (v2i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1398                                NoItinerary> {
1399   let cmode = 0b1110;
1400 }
1401 }
1402
1403 // Vector Move Immediate - bytemask, one doubleword
1404
1405 let isReMaterializable = 1 in {
1406 def MOVIdi : NeonI_1VModImm<0b0, 0b1,
1407                            (outs FPR64:$Rd), (ins neon_uimm64_mask:$Imm),
1408                            "movi\t $Rd, $Imm",
1409                            [(set (f64 FPR64:$Rd),
1410                               (f64 (bitconvert
1411                                 (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))))],
1412                            NoItinerary> {
1413   let cmode = 0b1110;
1414 }
1415 }
1416
1417 // Vector Floating Point Move Immediate
1418
1419 class NeonI_FMOV_impl<string asmlane, RegisterOperand VPRC, ValueType OpTy,
1420                       Operand immOpType, bit q, bit op>
1421   : NeonI_1VModImm<q, op,
1422                    (outs VPRC:$Rd), (ins immOpType:$Imm),
1423                    "fmov\t$Rd" # asmlane # ", $Imm",
1424                    [(set (OpTy VPRC:$Rd),
1425                       (OpTy (Neon_fmovi (timm:$Imm))))],
1426                    NoItinerary> {
1427      let cmode = 0b1111;
1428    }
1429
1430 let isReMaterializable = 1 in {
1431 def FMOVvi_2S : NeonI_FMOV_impl<".2s", VPR64,  v2f32, fmov32_operand, 0b0, 0b0>;
1432 def FMOVvi_4S : NeonI_FMOV_impl<".4s", VPR128, v4f32, fmov32_operand, 0b1, 0b0>;
1433 def FMOVvi_2D : NeonI_FMOV_impl<".2d", VPR128, v2f64, fmov64_operand, 0b1, 0b1>;
1434 }
1435
1436 // Vector Shift (Immediate)
1437 // Immediate in [0, 63]
1438 def imm0_63 : Operand<i32> {
1439   let ParserMatchClass = uimm6_asmoperand;
1440 }
1441
1442 // Shift Right/Left Immediate - The immh:immb field of these shifts are encoded
1443 // as follows:
1444 //
1445 //    Offset    Encoding
1446 //     8        immh:immb<6:3> = '0001xxx', <imm> is encoded in immh:immb<2:0>
1447 //     16       immh:immb<6:4> = '001xxxx', <imm> is encoded in immh:immb<3:0>
1448 //     32       immh:immb<6:5> = '01xxxxx', <imm> is encoded in immh:immb<4:0>
1449 //     64       immh:immb<6>   = '1xxxxxx', <imm> is encoded in immh:immb<5:0>
1450 //
1451 // The shift right immediate amount, in the range 1 to element bits, is computed
1452 // as Offset - UInt(immh:immb).  The shift left immediate amount, in the range 0
1453 // to element bits - 1, is computed as UInt(immh:immb) - Offset.
1454
1455 class shr_imm_asmoperands<string OFFSET> : AsmOperandClass {
1456   let Name = "ShrImm" # OFFSET;
1457   let RenderMethod = "addImmOperands";
1458   let DiagnosticType = "ShrImm" # OFFSET;
1459 }
1460
1461 class shr_imm<string OFFSET> : Operand<i32> {
1462   let EncoderMethod = "getShiftRightImm" # OFFSET;
1463   let DecoderMethod = "DecodeShiftRightImm" # OFFSET;
1464   let ParserMatchClass =
1465     !cast<AsmOperandClass>("shr_imm" # OFFSET # "_asmoperand");
1466 }
1467
1468 def shr_imm8_asmoperand : shr_imm_asmoperands<"8">;
1469 def shr_imm16_asmoperand : shr_imm_asmoperands<"16">;
1470 def shr_imm32_asmoperand : shr_imm_asmoperands<"32">;
1471 def shr_imm64_asmoperand : shr_imm_asmoperands<"64">;
1472
1473 def shr_imm8 : shr_imm<"8">;
1474 def shr_imm16 : shr_imm<"16">;
1475 def shr_imm32 : shr_imm<"32">;
1476 def shr_imm64 : shr_imm<"64">;
1477
1478 class shl_imm_asmoperands<string OFFSET> : AsmOperandClass {
1479   let Name = "ShlImm" # OFFSET;
1480   let RenderMethod = "addImmOperands";
1481   let DiagnosticType = "ShlImm" # OFFSET;
1482 }
1483
1484 class shl_imm<string OFFSET> : Operand<i32> {
1485   let EncoderMethod = "getShiftLeftImm" # OFFSET;
1486   let DecoderMethod = "DecodeShiftLeftImm" # OFFSET;
1487   let ParserMatchClass =
1488     !cast<AsmOperandClass>("shl_imm" # OFFSET # "_asmoperand");
1489 }
1490
1491 def shl_imm8_asmoperand : shl_imm_asmoperands<"8">;
1492 def shl_imm16_asmoperand : shl_imm_asmoperands<"16">;
1493 def shl_imm32_asmoperand : shl_imm_asmoperands<"32">;
1494 def shl_imm64_asmoperand : shl_imm_asmoperands<"64">;
1495
1496 def shl_imm8 : shl_imm<"8">;
1497 def shl_imm16 : shl_imm<"16">;
1498 def shl_imm32 : shl_imm<"32">;
1499 def shl_imm64 : shl_imm<"64">;
1500
1501 class N2VShift<bit q, bit u, bits<5> opcode, string asmop, string T,
1502                RegisterOperand VPRC, ValueType Ty, Operand ImmTy, SDNode OpNode>
1503   : NeonI_2VShiftImm<q, u, opcode,
1504                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1505                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1506                      [(set (Ty VPRC:$Rd),
1507                         (Ty (OpNode (Ty VPRC:$Rn),
1508                           (Ty (Neon_vdup (i32 imm:$Imm))))))],
1509                      NoItinerary>;
1510
1511 multiclass NeonI_N2VShL<bit u, bits<5> opcode, string asmop> {
1512   // 64-bit vector types.
1513   def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, uimm3, shl> {
1514     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1515   }
1516
1517   def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, uimm4, shl> {
1518     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1519   }
1520
1521   def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, uimm5, shl> {
1522     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1523   }
1524
1525   // 128-bit vector types.
1526   def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, uimm3, shl> {
1527     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1528   }
1529
1530   def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, uimm4, shl> {
1531     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1532   }
1533
1534   def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, uimm5, shl> {
1535     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1536   }
1537
1538   def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, imm0_63, shl> {
1539     let Inst{22} = 0b1;        // immh:immb = 1xxxxxx
1540   }
1541 }
1542
1543 multiclass NeonI_N2VShR<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1544   def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1545                      OpNode> {
1546     let Inst{22-19} = 0b0001;
1547   }
1548
1549   def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1550                      OpNode> {
1551     let Inst{22-20} = 0b001;
1552   }
1553
1554   def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1555                      OpNode> {
1556      let Inst{22-21} = 0b01;
1557   }
1558
1559   def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1560                       OpNode> {
1561                       let Inst{22-19} = 0b0001;
1562                     }
1563
1564   def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1565                      OpNode> {
1566                      let Inst{22-20} = 0b001;
1567                     }
1568
1569   def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1570                      OpNode> {
1571                       let Inst{22-21} = 0b01;
1572                     }
1573
1574   def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1575                      OpNode> {
1576                       let Inst{22} = 0b1;
1577                     }
1578 }
1579
1580 // Shift left
1581 defm SHLvvi : NeonI_N2VShL<0b0, 0b01010, "shl">;
1582
1583 // Shift right
1584 defm SSHRvvi : NeonI_N2VShR<0b0, 0b00000, "sshr", sra>;
1585 defm USHRvvi : NeonI_N2VShR<0b1, 0b00000, "ushr", srl>;
1586
1587 def Neon_High16B : PatFrag<(ops node:$in),
1588                            (extract_subvector (v16i8 node:$in), (iPTR 8))>;
1589 def Neon_High8H  : PatFrag<(ops node:$in),
1590                            (extract_subvector (v8i16 node:$in), (iPTR 4))>;
1591 def Neon_High4S  : PatFrag<(ops node:$in),
1592                            (extract_subvector (v4i32 node:$in), (iPTR 2))>;
1593 def Neon_High2D  : PatFrag<(ops node:$in),
1594                            (extract_subvector (v2i64 node:$in), (iPTR 1))>;
1595 def Neon_High4f  : PatFrag<(ops node:$in),
1596                            (extract_subvector (v4f32 node:$in), (iPTR 2))>;
1597 def Neon_High2d  : PatFrag<(ops node:$in),
1598                            (extract_subvector (v2f64 node:$in), (iPTR 1))>;
1599
1600 def Neon_low16B : PatFrag<(ops node:$in),
1601                           (v8i8 (extract_subvector (v16i8 node:$in),
1602                                                    (iPTR 0)))>;
1603 def Neon_low8H : PatFrag<(ops node:$in),
1604                          (v4i16 (extract_subvector (v8i16 node:$in),
1605                                                    (iPTR 0)))>;
1606 def Neon_low4S : PatFrag<(ops node:$in),
1607                          (v2i32 (extract_subvector (v4i32 node:$in),
1608                                                    (iPTR 0)))>;
1609 def Neon_low2D : PatFrag<(ops node:$in),
1610                          (v1i64 (extract_subvector (v2i64 node:$in),
1611                                                    (iPTR 0)))>;
1612 def Neon_low4f : PatFrag<(ops node:$in),
1613                          (v2f32 (extract_subvector (v4f32 node:$in),
1614                                                    (iPTR 0)))>;
1615 def Neon_low2d : PatFrag<(ops node:$in),
1616                          (v1f64 (extract_subvector (v2f64 node:$in),
1617                                                    (iPTR 0)))>;
1618
1619 def neon_uimm3_shift : Operand<i32>,
1620                          ImmLeaf<i32, [{return Imm < 8;}]> {
1621   let ParserMatchClass = uimm3_asmoperand;
1622 }
1623
1624 def neon_uimm4_shift : Operand<i32>,
1625                          ImmLeaf<i32, [{return Imm < 16;}]> {
1626   let ParserMatchClass = uimm4_asmoperand;
1627 }
1628
1629 def neon_uimm5_shift : Operand<i32>,
1630                          ImmLeaf<i32, [{return Imm < 32;}]> {
1631   let ParserMatchClass = uimm5_asmoperand;
1632 }
1633
1634 class N2VShiftLong<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1635                    string SrcT, ValueType DestTy, ValueType SrcTy,
1636                    Operand ImmTy, SDPatternOperator ExtOp>
1637   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1638                      (ins VPR64:$Rn, ImmTy:$Imm),
1639                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1640                      [(set (DestTy VPR128:$Rd),
1641                         (DestTy (shl
1642                           (DestTy (ExtOp (SrcTy VPR64:$Rn))),
1643                             (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1644                      NoItinerary>;
1645
1646 class N2VShiftLongHigh<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1647                        string SrcT, ValueType DestTy, ValueType SrcTy,
1648                        int StartIndex, Operand ImmTy,
1649                        SDPatternOperator ExtOp, PatFrag getTop>
1650   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1651                      (ins VPR128:$Rn, ImmTy:$Imm),
1652                      asmop # "2\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1653                      [(set (DestTy VPR128:$Rd),
1654                         (DestTy (shl
1655                           (DestTy (ExtOp
1656                             (SrcTy (getTop VPR128:$Rn)))),
1657                               (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1658                      NoItinerary>;
1659
1660 multiclass NeonI_N2VShLL<string prefix, bit u, bits<5> opcode, string asmop,
1661                          SDNode ExtOp> {
1662   // 64-bit vector types.
1663   def _8B : N2VShiftLong<0b0, u, opcode, asmop, "8h", "8b", v8i16, v8i8,
1664                          neon_uimm3_shift, ExtOp> {
1665     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1666   }
1667
1668   def _4H : N2VShiftLong<0b0, u, opcode, asmop, "4s", "4h", v4i32, v4i16,
1669                          neon_uimm4_shift, ExtOp> {
1670     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1671   }
1672
1673   def _2S : N2VShiftLong<0b0, u, opcode, asmop, "2d", "2s", v2i64, v2i32,
1674                          neon_uimm5_shift, ExtOp> {
1675     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1676   }
1677
1678   // 128-bit vector types
1679   def _16B : N2VShiftLongHigh<0b1, u, opcode, asmop, "8h", "16b", v8i16, v8i8,
1680                               8, neon_uimm3_shift, ExtOp, Neon_High16B> {
1681     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1682   }
1683
1684   def _8H : N2VShiftLongHigh<0b1, u, opcode, asmop, "4s", "8h", v4i32, v4i16,
1685                              4, neon_uimm4_shift, ExtOp, Neon_High8H> {
1686     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1687   }
1688
1689   def _4S : N2VShiftLongHigh<0b1, u, opcode, asmop, "2d", "4s", v2i64, v2i32,
1690                              2, neon_uimm5_shift, ExtOp, Neon_High4S> {
1691     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1692   }
1693
1694   // Use other patterns to match when the immediate is 0.
1695   def : Pat<(v8i16 (ExtOp (v8i8 VPR64:$Rn))),
1696             (!cast<Instruction>(prefix # "_8B") VPR64:$Rn, 0)>;
1697
1698   def : Pat<(v4i32 (ExtOp (v4i16 VPR64:$Rn))),
1699             (!cast<Instruction>(prefix # "_4H") VPR64:$Rn, 0)>;
1700
1701   def : Pat<(v2i64 (ExtOp (v2i32 VPR64:$Rn))),
1702             (!cast<Instruction>(prefix # "_2S") VPR64:$Rn, 0)>;
1703
1704   def : Pat<(v8i16 (ExtOp (v8i8 (Neon_High16B VPR128:$Rn)))),
1705             (!cast<Instruction>(prefix # "_16B") VPR128:$Rn, 0)>;
1706
1707   def : Pat<(v4i32 (ExtOp (v4i16 (Neon_High8H VPR128:$Rn)))),
1708             (!cast<Instruction>(prefix # "_8H") VPR128:$Rn, 0)>;
1709
1710   def : Pat<(v2i64 (ExtOp (v2i32 (Neon_High4S VPR128:$Rn)))),
1711             (!cast<Instruction>(prefix # "_4S") VPR128:$Rn, 0)>;
1712 }
1713
1714 // Shift left long
1715 defm SSHLLvvi : NeonI_N2VShLL<"SSHLLvvi", 0b0, 0b10100, "sshll", sext>;
1716 defm USHLLvvi : NeonI_N2VShLL<"USHLLvvi", 0b1, 0b10100, "ushll", zext>;
1717
1718 // Rounding/Saturating shift
1719 class N2VShift_RQ<bit q, bit u, bits<5> opcode, string asmop, string T,
1720                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1721                   SDPatternOperator OpNode>
1722   : NeonI_2VShiftImm<q, u, opcode,
1723                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1724                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1725                      [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$Rn),
1726                         (i32 imm:$Imm))))],
1727                      NoItinerary>;
1728
1729 // shift right (vector by immediate)
1730 multiclass NeonI_N2VShR_RQ<bit u, bits<5> opcode, string asmop,
1731                            SDPatternOperator OpNode> {
1732   def _8B  : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1733                          OpNode> {
1734     let Inst{22-19} = 0b0001;
1735   }
1736
1737   def _4H  : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1738                          OpNode> {
1739     let Inst{22-20} = 0b001;
1740   }
1741
1742   def _2S  : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1743                          OpNode> {
1744     let Inst{22-21} = 0b01;
1745   }
1746
1747   def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1748                          OpNode> {
1749     let Inst{22-19} = 0b0001;
1750   }
1751
1752   def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1753                         OpNode> {
1754     let Inst{22-20} = 0b001;
1755   }
1756
1757   def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1758                         OpNode> {
1759     let Inst{22-21} = 0b01;
1760   }
1761
1762   def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1763                         OpNode> {
1764     let Inst{22} = 0b1;
1765   }
1766 }
1767
1768 multiclass NeonI_N2VShL_Q<bit u, bits<5> opcode, string asmop,
1769                           SDPatternOperator OpNode> {
1770   // 64-bit vector types.
1771   def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, uimm3,
1772                         OpNode> {
1773     let Inst{22-19} = 0b0001;
1774   }
1775
1776   def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, uimm4,
1777                         OpNode> {
1778     let Inst{22-20} = 0b001;
1779   }
1780
1781   def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, uimm5,
1782                         OpNode> {
1783     let Inst{22-21} = 0b01;
1784   }
1785
1786   // 128-bit vector types.
1787   def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, uimm3,
1788                          OpNode> {
1789     let Inst{22-19} = 0b0001;
1790   }
1791
1792   def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, uimm4,
1793                         OpNode> {
1794     let Inst{22-20} = 0b001;
1795   }
1796
1797   def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, uimm5,
1798                         OpNode> {
1799     let Inst{22-21} = 0b01;
1800   }
1801
1802   def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, imm0_63,
1803                         OpNode> {
1804     let Inst{22} = 0b1;
1805   }
1806 }
1807
1808 // Rounding shift right
1809 defm SRSHRvvi : NeonI_N2VShR_RQ<0b0, 0b00100, "srshr",
1810                                 int_aarch64_neon_vsrshr>;
1811 defm URSHRvvi : NeonI_N2VShR_RQ<0b1, 0b00100, "urshr",
1812                                 int_aarch64_neon_vurshr>;
1813
1814 // Saturating shift left unsigned
1815 defm SQSHLUvvi : NeonI_N2VShL_Q<0b1, 0b01100, "sqshlu", int_aarch64_neon_vsqshlu>;
1816
1817 // Saturating shift left
1818 defm SQSHLvvi : NeonI_N2VShL_Q<0b0, 0b01110, "sqshl", Neon_sqrshlImm>;
1819 defm UQSHLvvi : NeonI_N2VShL_Q<0b1, 0b01110, "uqshl", Neon_uqrshlImm>;
1820
1821 class N2VShiftAdd<bit q, bit u, bits<5> opcode, string asmop, string T,
1822                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1823                   SDNode OpNode>
1824   : NeonI_2VShiftImm<q, u, opcode,
1825            (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1826            asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1827            [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1828               (Ty (OpNode (Ty VPRC:$Rn),
1829                 (Ty (Neon_vdup (i32 imm:$Imm))))))))],
1830            NoItinerary> {
1831   let Constraints = "$src = $Rd";
1832 }
1833
1834 // Shift Right accumulate
1835 multiclass NeonI_N2VShRAdd<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1836   def _8B : N2VShiftAdd<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1837                         OpNode> {
1838     let Inst{22-19} = 0b0001;
1839   }
1840
1841   def _4H : N2VShiftAdd<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1842                         OpNode> {
1843     let Inst{22-20} = 0b001;
1844   }
1845
1846   def _2S : N2VShiftAdd<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1847                         OpNode> {
1848     let Inst{22-21} = 0b01;
1849   }
1850
1851   def _16B : N2VShiftAdd<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1852                          OpNode> {
1853     let Inst{22-19} = 0b0001;
1854   }
1855
1856   def _8H : N2VShiftAdd<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1857                         OpNode> {
1858     let Inst{22-20} = 0b001;
1859   }
1860
1861   def _4S : N2VShiftAdd<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1862                         OpNode> {
1863     let Inst{22-21} = 0b01;
1864   }
1865
1866   def _2D : N2VShiftAdd<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1867                         OpNode> {
1868     let Inst{22} = 0b1;
1869   }
1870 }
1871
1872 // Shift right and accumulate
1873 defm SSRAvvi    : NeonI_N2VShRAdd<0, 0b00010, "ssra", sra>;
1874 defm USRAvvi    : NeonI_N2VShRAdd<1, 0b00010, "usra", srl>;
1875
1876 // Rounding shift accumulate
1877 class N2VShiftAdd_R<bit q, bit u, bits<5> opcode, string asmop, string T,
1878                     RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1879                     SDPatternOperator OpNode>
1880   : NeonI_2VShiftImm<q, u, opcode,
1881                      (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1882                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1883                      [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1884                         (Ty (OpNode (Ty VPRC:$Rn), (i32 imm:$Imm))))))],
1885                      NoItinerary> {
1886   let Constraints = "$src = $Rd";
1887 }
1888
1889 multiclass NeonI_N2VShRAdd_R<bit u, bits<5> opcode, string asmop,
1890                              SDPatternOperator OpNode> {
1891   def _8B : N2VShiftAdd_R<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1892                           OpNode> {
1893     let Inst{22-19} = 0b0001;
1894   }
1895
1896   def _4H : N2VShiftAdd_R<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1897                           OpNode> {
1898     let Inst{22-20} = 0b001;
1899   }
1900
1901   def _2S : N2VShiftAdd_R<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1902                           OpNode> {
1903     let Inst{22-21} = 0b01;
1904   }
1905
1906   def _16B : N2VShiftAdd_R<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1907                            OpNode> {
1908     let Inst{22-19} = 0b0001;
1909   }
1910
1911   def _8H : N2VShiftAdd_R<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1912                           OpNode> {
1913     let Inst{22-20} = 0b001;
1914   }
1915
1916   def _4S : N2VShiftAdd_R<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1917                           OpNode> {
1918     let Inst{22-21} = 0b01;
1919   }
1920
1921   def _2D : N2VShiftAdd_R<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1922                           OpNode> {
1923     let Inst{22} = 0b1;
1924   }
1925 }
1926
1927 // Rounding shift right and accumulate
1928 defm SRSRAvvi : NeonI_N2VShRAdd_R<0, 0b00110, "srsra", int_aarch64_neon_vsrshr>;
1929 defm URSRAvvi : NeonI_N2VShRAdd_R<1, 0b00110, "ursra", int_aarch64_neon_vurshr>;
1930
1931 // Shift insert by immediate
1932 class N2VShiftIns<bit q, bit u, bits<5> opcode, string asmop, string T,
1933                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1934                   SDPatternOperator OpNode>
1935     : NeonI_2VShiftImm<q, u, opcode,
1936            (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1937            asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1938            [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$src), (Ty VPRC:$Rn),
1939              (i32 imm:$Imm))))],
1940            NoItinerary> {
1941   let Constraints = "$src = $Rd";
1942 }
1943
1944 // shift left insert (vector by immediate)
1945 multiclass NeonI_N2VShLIns<bit u, bits<5> opcode, string asmop> {
1946   def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, uimm3,
1947                         int_aarch64_neon_vsli> {
1948     let Inst{22-19} = 0b0001;
1949   }
1950
1951   def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, uimm4,
1952                         int_aarch64_neon_vsli> {
1953     let Inst{22-20} = 0b001;
1954   }
1955
1956   def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, uimm5,
1957                         int_aarch64_neon_vsli> {
1958     let Inst{22-21} = 0b01;
1959   }
1960
1961     // 128-bit vector types
1962   def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, uimm3,
1963                          int_aarch64_neon_vsli> {
1964     let Inst{22-19} = 0b0001;
1965   }
1966
1967   def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, uimm4,
1968                         int_aarch64_neon_vsli> {
1969     let Inst{22-20} = 0b001;
1970   }
1971
1972   def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, uimm5,
1973                         int_aarch64_neon_vsli> {
1974     let Inst{22-21} = 0b01;
1975   }
1976
1977   def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, imm0_63,
1978                         int_aarch64_neon_vsli> {
1979     let Inst{22} = 0b1;
1980   }
1981 }
1982
1983 // shift right insert (vector by immediate)
1984 multiclass NeonI_N2VShRIns<bit u, bits<5> opcode, string asmop> {
1985     // 64-bit vector types.
1986   def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1987                         int_aarch64_neon_vsri> {
1988     let Inst{22-19} = 0b0001;
1989   }
1990
1991   def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1992                         int_aarch64_neon_vsri> {
1993     let Inst{22-20} = 0b001;
1994   }
1995
1996   def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1997                         int_aarch64_neon_vsri> {
1998     let Inst{22-21} = 0b01;
1999   }
2000
2001     // 128-bit vector types
2002   def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2003                          int_aarch64_neon_vsri> {
2004     let Inst{22-19} = 0b0001;
2005   }
2006
2007   def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2008                         int_aarch64_neon_vsri> {
2009     let Inst{22-20} = 0b001;
2010   }
2011
2012   def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2013                         int_aarch64_neon_vsri> {
2014     let Inst{22-21} = 0b01;
2015   }
2016
2017   def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2018                         int_aarch64_neon_vsri> {
2019     let Inst{22} = 0b1;
2020   }
2021 }
2022
2023 // Shift left and insert
2024 defm SLIvvi   : NeonI_N2VShLIns<0b1, 0b01010, "sli">;
2025
2026 // Shift right and insert
2027 defm SRIvvi   : NeonI_N2VShRIns<0b1, 0b01000, "sri">;
2028
2029 class N2VShR_Narrow<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2030                     string SrcT, Operand ImmTy>
2031   : NeonI_2VShiftImm<q, u, opcode,
2032                      (outs VPR64:$Rd), (ins VPR128:$Rn, ImmTy:$Imm),
2033                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2034                      [], NoItinerary>;
2035
2036 class N2VShR_Narrow_Hi<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2037                        string SrcT, Operand ImmTy>
2038   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
2039                      (ins VPR128:$src, VPR128:$Rn, ImmTy:$Imm),
2040                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2041                      [], NoItinerary> {
2042   let Constraints = "$src = $Rd";
2043 }
2044
2045 // left long shift by immediate
2046 multiclass NeonI_N2VShR_Narrow<bit u, bits<5> opcode, string asmop> {
2047   def _8B : N2VShR_Narrow<0b0, u, opcode, asmop, "8b", "8h", shr_imm8> {
2048     let Inst{22-19} = 0b0001;
2049   }
2050
2051   def _4H : N2VShR_Narrow<0b0, u, opcode, asmop, "4h", "4s", shr_imm16> {
2052     let Inst{22-20} = 0b001;
2053   }
2054
2055   def _2S : N2VShR_Narrow<0b0, u, opcode, asmop, "2s", "2d", shr_imm32> {
2056     let Inst{22-21} = 0b01;
2057   }
2058
2059   // Shift Narrow High
2060   def _16B : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "16b", "8h",
2061                               shr_imm8> {
2062     let Inst{22-19} = 0b0001;
2063   }
2064
2065   def _8H : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "8h", "4s",
2066                              shr_imm16> {
2067     let Inst{22-20} = 0b001;
2068   }
2069
2070   def _4S : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "4s", "2d",
2071                              shr_imm32> {
2072     let Inst{22-21} = 0b01;
2073   }
2074 }
2075
2076 // Shift right narrow
2077 defm SHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10000, "shrn">;
2078
2079 // Shift right narrow (prefix Q is saturating, prefix R is rounding)
2080 defm QSHRUNvvi :NeonI_N2VShR_Narrow<0b1, 0b10000, "sqshrun">;
2081 defm RSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10001, "rshrn">;
2082 defm QRSHRUNvvi : NeonI_N2VShR_Narrow<0b1, 0b10001, "sqrshrun">;
2083 defm SQSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10010, "sqshrn">;
2084 defm UQSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10010, "uqshrn">;
2085 defm SQRSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10011, "sqrshrn">;
2086 defm UQRSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10011, "uqrshrn">;
2087
2088 def Neon_combine_2D : PatFrag<(ops node:$Rm, node:$Rn),
2089                               (v2i64 (concat_vectors (v1i64 node:$Rm),
2090                                                      (v1i64 node:$Rn)))>;
2091 def Neon_combine_8H : PatFrag<(ops node:$Rm, node:$Rn),
2092                               (v8i16 (concat_vectors (v4i16 node:$Rm),
2093                                                      (v4i16 node:$Rn)))>;
2094 def Neon_combine_4S : PatFrag<(ops node:$Rm, node:$Rn),
2095                               (v4i32 (concat_vectors (v2i32 node:$Rm),
2096                                                      (v2i32 node:$Rn)))>;
2097 def Neon_combine_4f : PatFrag<(ops node:$Rm, node:$Rn),
2098                               (v4f32 (concat_vectors (v2f32 node:$Rm),
2099                                                      (v2f32 node:$Rn)))>;
2100 def Neon_combine_2d : PatFrag<(ops node:$Rm, node:$Rn),
2101                               (v2f64 (concat_vectors (v1f64 node:$Rm),
2102                                                      (v1f64 node:$Rn)))>;
2103
2104 def Neon_lshrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2105                              (v8i16 (srl (v8i16 node:$lhs),
2106                                (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2107 def Neon_lshrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2108                              (v4i32 (srl (v4i32 node:$lhs),
2109                                (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2110 def Neon_lshrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2111                              (v2i64 (srl (v2i64 node:$lhs),
2112                                (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2113 def Neon_ashrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2114                              (v8i16 (sra (v8i16 node:$lhs),
2115                                (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2116 def Neon_ashrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2117                              (v4i32 (sra (v4i32 node:$lhs),
2118                                (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2119 def Neon_ashrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2120                              (v2i64 (sra (v2i64 node:$lhs),
2121                                (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2122
2123 // Normal shift right narrow is matched by IR (srl/sra, trunc, concat_vectors)
2124 multiclass Neon_shiftNarrow_patterns<string shr> {
2125   def : Pat<(v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H") VPR128:$Rn,
2126               (i32 imm:$Imm)))),
2127             (SHRNvvi_8B VPR128:$Rn, imm:$Imm)>;
2128   def : Pat<(v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S") VPR128:$Rn,
2129               (i32 imm:$Imm)))),
2130             (SHRNvvi_4H VPR128:$Rn, imm:$Imm)>;
2131   def : Pat<(v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D") VPR128:$Rn,
2132               (i32 imm:$Imm)))),
2133             (SHRNvvi_2S VPR128:$Rn, imm:$Imm)>;
2134
2135   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2136               (v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H")
2137                 VPR128:$Rn, (i32 imm:$Imm))))))),
2138             (SHRNvvi_16B (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
2139                          VPR128:$Rn, imm:$Imm)>;
2140   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2141               (v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S")
2142                 VPR128:$Rn, (i32 imm:$Imm))))))),
2143             (SHRNvvi_8H (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2144                         VPR128:$Rn, imm:$Imm)>;
2145   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2146               (v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D")
2147                 VPR128:$Rn, (i32 imm:$Imm))))))),
2148             (SHRNvvi_4S (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2149                         VPR128:$Rn, imm:$Imm)>;
2150 }
2151
2152 multiclass Neon_shiftNarrow_QR_patterns<SDPatternOperator op, string prefix> {
2153   def : Pat<(v8i8 (op (v8i16 VPR128:$Rn), imm:$Imm)),
2154             (!cast<Instruction>(prefix # "_8B") VPR128:$Rn, imm:$Imm)>;
2155   def : Pat<(v4i16 (op (v4i32 VPR128:$Rn), imm:$Imm)),
2156             (!cast<Instruction>(prefix # "_4H") VPR128:$Rn, imm:$Imm)>;
2157   def : Pat<(v2i32 (op (v2i64 VPR128:$Rn), imm:$Imm)),
2158             (!cast<Instruction>(prefix # "_2S") VPR128:$Rn, imm:$Imm)>;
2159
2160   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2161                 (v1i64 (bitconvert (v8i8 (op (v8i16 VPR128:$Rn), imm:$Imm))))),
2162             (!cast<Instruction>(prefix # "_16B")
2163                 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2164                 VPR128:$Rn, imm:$Imm)>;
2165   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2166                 (v1i64 (bitconvert (v4i16 (op (v4i32 VPR128:$Rn), imm:$Imm))))),
2167             (!cast<Instruction>(prefix # "_8H")
2168                 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2169                 VPR128:$Rn, imm:$Imm)>;
2170   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2171                 (v1i64 (bitconvert (v2i32 (op (v2i64 VPR128:$Rn), imm:$Imm))))),
2172             (!cast<Instruction>(prefix # "_4S")
2173                   (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2174                   VPR128:$Rn, imm:$Imm)>;
2175 }
2176
2177 defm : Neon_shiftNarrow_patterns<"lshr">;
2178 defm : Neon_shiftNarrow_patterns<"ashr">;
2179
2180 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrun, "QSHRUNvvi">;
2181 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vrshrn, "RSHRNvvi">;
2182 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrun, "QRSHRUNvvi">;
2183 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrn, "SQSHRNvvi">;
2184 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqshrn, "UQSHRNvvi">;
2185 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrn, "SQRSHRNvvi">;
2186 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqrshrn, "UQRSHRNvvi">;
2187
2188 // Convert fix-point and float-pointing
2189 class N2VCvt_Fx<bit q, bit u, bits<5> opcode, string asmop, string T,
2190                 RegisterOperand VPRC, ValueType DestTy, ValueType SrcTy,
2191                 Operand ImmTy, SDPatternOperator IntOp>
2192   : NeonI_2VShiftImm<q, u, opcode,
2193                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
2194                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2195                      [(set (DestTy VPRC:$Rd), (DestTy (IntOp (SrcTy VPRC:$Rn),
2196                        (i32 imm:$Imm))))],
2197                      NoItinerary>;
2198
2199 multiclass NeonI_N2VCvt_Fx2fp<bit u, bits<5> opcode, string asmop,
2200                               SDPatternOperator IntOp> {
2201   def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2f32, v2i32,
2202                       shr_imm32, IntOp> {
2203     let Inst{22-21} = 0b01;
2204   }
2205
2206   def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4f32, v4i32,
2207                       shr_imm32, IntOp> {
2208     let Inst{22-21} = 0b01;
2209   }
2210
2211   def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2f64, v2i64,
2212                       shr_imm64, IntOp> {
2213     let Inst{22} = 0b1;
2214   }
2215 }
2216
2217 multiclass NeonI_N2VCvt_Fp2fx<bit u, bits<5> opcode, string asmop,
2218                               SDPatternOperator IntOp> {
2219   def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2i32, v2f32,
2220                       shr_imm32, IntOp> {
2221     let Inst{22-21} = 0b01;
2222   }
2223
2224   def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4i32, v4f32,
2225                       shr_imm32, IntOp> {
2226     let Inst{22-21} = 0b01;
2227   }
2228
2229   def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2i64, v2f64,
2230                       shr_imm64, IntOp> {
2231     let Inst{22} = 0b1;
2232   }
2233 }
2234
2235 // Convert fixed-point to floating-point
2236 defm VCVTxs2f : NeonI_N2VCvt_Fx2fp<0, 0b11100, "scvtf",
2237                                    int_arm_neon_vcvtfxs2fp>;
2238 defm VCVTxu2f : NeonI_N2VCvt_Fx2fp<1, 0b11100, "ucvtf",
2239                                    int_arm_neon_vcvtfxu2fp>;
2240
2241 // Convert floating-point to fixed-point
2242 defm VCVTf2xs : NeonI_N2VCvt_Fp2fx<0, 0b11111, "fcvtzs",
2243                                    int_arm_neon_vcvtfp2fxs>;
2244 defm VCVTf2xu : NeonI_N2VCvt_Fp2fx<1, 0b11111, "fcvtzu",
2245                                    int_arm_neon_vcvtfp2fxu>;
2246
2247 multiclass Neon_sshll2_0<SDNode ext>
2248 {
2249   def _v8i8  : PatFrag<(ops node:$Rn),
2250                        (v8i16 (ext (v8i8 (Neon_High16B node:$Rn))))>;
2251   def _v4i16 : PatFrag<(ops node:$Rn),
2252                        (v4i32 (ext (v4i16 (Neon_High8H node:$Rn))))>;
2253   def _v2i32 : PatFrag<(ops node:$Rn),
2254                        (v2i64 (ext (v2i32 (Neon_High4S node:$Rn))))>;
2255 }
2256
2257 defm NI_sext_high : Neon_sshll2_0<sext>;
2258 defm NI_zext_high : Neon_sshll2_0<zext>;
2259
2260
2261 //===----------------------------------------------------------------------===//
2262 // Multiclasses for NeonI_Across
2263 //===----------------------------------------------------------------------===//
2264
2265 // Variant 1
2266
2267 multiclass NeonI_2VAcross_1<bit u, bits<5> opcode,
2268                             string asmop, SDPatternOperator opnode>
2269 {
2270     def _1h8b:  NeonI_2VAcross<0b0, u, 0b00, opcode,
2271                 (outs FPR16:$Rd), (ins VPR64:$Rn),
2272                 asmop # "\t$Rd, $Rn.8b",
2273                 [(set (v1i16 FPR16:$Rd),
2274                     (v1i16 (opnode (v8i8 VPR64:$Rn))))],
2275                 NoItinerary>;
2276
2277     def _1h16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2278                 (outs FPR16:$Rd), (ins VPR128:$Rn),
2279                 asmop # "\t$Rd, $Rn.16b",
2280                 [(set (v1i16 FPR16:$Rd),
2281                     (v1i16 (opnode (v16i8 VPR128:$Rn))))],
2282                 NoItinerary>;
2283
2284     def _1s4h:  NeonI_2VAcross<0b0, u, 0b01, opcode,
2285                 (outs FPR32:$Rd), (ins VPR64:$Rn),
2286                 asmop # "\t$Rd, $Rn.4h",
2287                 [(set (v1i32 FPR32:$Rd),
2288                     (v1i32 (opnode (v4i16 VPR64:$Rn))))],
2289                 NoItinerary>;
2290
2291     def _1s8h:  NeonI_2VAcross<0b1, u, 0b01, opcode,
2292                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2293                 asmop # "\t$Rd, $Rn.8h",
2294                 [(set (v1i32 FPR32:$Rd),
2295                     (v1i32 (opnode (v8i16 VPR128:$Rn))))],
2296                 NoItinerary>;
2297
2298     // _1d2s doesn't exist!
2299
2300     def _1d4s:  NeonI_2VAcross<0b1, u, 0b10, opcode,
2301                 (outs FPR64:$Rd), (ins VPR128:$Rn),
2302                 asmop # "\t$Rd, $Rn.4s",
2303                 [(set (v1i64 FPR64:$Rd),
2304                     (v1i64 (opnode (v4i32 VPR128:$Rn))))],
2305                 NoItinerary>;
2306 }
2307
2308 defm SADDLV : NeonI_2VAcross_1<0b0, 0b00011, "saddlv", int_aarch64_neon_saddlv>;
2309 defm UADDLV : NeonI_2VAcross_1<0b1, 0b00011, "uaddlv", int_aarch64_neon_uaddlv>;
2310
2311 // Variant 2
2312
2313 multiclass NeonI_2VAcross_2<bit u, bits<5> opcode,
2314                             string asmop, SDPatternOperator opnode>
2315 {
2316     def _1b8b:  NeonI_2VAcross<0b0, u, 0b00, opcode,
2317                 (outs FPR8:$Rd), (ins VPR64:$Rn),
2318                 asmop # "\t$Rd, $Rn.8b",
2319                 [(set (v1i8 FPR8:$Rd),
2320                     (v1i8 (opnode (v8i8 VPR64:$Rn))))],
2321                 NoItinerary>;
2322
2323     def _1b16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2324                 (outs FPR8:$Rd), (ins VPR128:$Rn),
2325                 asmop # "\t$Rd, $Rn.16b",
2326                 [(set (v1i8 FPR8:$Rd),
2327                     (v1i8 (opnode (v16i8 VPR128:$Rn))))],
2328                 NoItinerary>;
2329
2330     def _1h4h:  NeonI_2VAcross<0b0, u, 0b01, opcode,
2331                 (outs FPR16:$Rd), (ins VPR64:$Rn),
2332                 asmop # "\t$Rd, $Rn.4h",
2333                 [(set (v1i16 FPR16:$Rd),
2334                     (v1i16 (opnode (v4i16 VPR64:$Rn))))],
2335                 NoItinerary>;
2336
2337     def _1h8h:  NeonI_2VAcross<0b1, u, 0b01, opcode,
2338                 (outs FPR16:$Rd), (ins VPR128:$Rn),
2339                 asmop # "\t$Rd, $Rn.8h",
2340                 [(set (v1i16 FPR16:$Rd),
2341                     (v1i16 (opnode (v8i16 VPR128:$Rn))))],
2342                 NoItinerary>;
2343
2344     // _1s2s doesn't exist!
2345
2346     def _1s4s:  NeonI_2VAcross<0b1, u, 0b10, opcode,
2347                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2348                 asmop # "\t$Rd, $Rn.4s",
2349                 [(set (v1i32 FPR32:$Rd),
2350                     (v1i32 (opnode (v4i32 VPR128:$Rn))))],
2351                 NoItinerary>;
2352 }
2353
2354 defm SMAXV : NeonI_2VAcross_2<0b0, 0b01010, "smaxv", int_aarch64_neon_smaxv>;
2355 defm UMAXV : NeonI_2VAcross_2<0b1, 0b01010, "umaxv", int_aarch64_neon_umaxv>;
2356
2357 defm SMINV : NeonI_2VAcross_2<0b0, 0b11010, "sminv", int_aarch64_neon_sminv>;
2358 defm UMINV : NeonI_2VAcross_2<0b1, 0b11010, "uminv", int_aarch64_neon_uminv>;
2359
2360 defm ADDV : NeonI_2VAcross_2<0b0, 0b11011, "addv", int_aarch64_neon_vaddv>;
2361
2362 // Variant 3
2363
2364 multiclass NeonI_2VAcross_3<bit u, bits<5> opcode, bits<2> size,
2365                             string asmop, SDPatternOperator opnode> {
2366     def _1s4s:  NeonI_2VAcross<0b1, u, size, opcode,
2367                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2368                 asmop # "\t$Rd, $Rn.4s",
2369                 [(set (v1f32 FPR32:$Rd),
2370                     (v1f32 (opnode (v4f32 VPR128:$Rn))))],
2371                 NoItinerary>;
2372 }
2373
2374 defm FMAXNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b00, "fmaxnmv",
2375                                 int_aarch64_neon_vmaxnmv>;
2376 defm FMINNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b10, "fminnmv",
2377                                 int_aarch64_neon_vminnmv>;
2378
2379 defm FMAXV : NeonI_2VAcross_3<0b1, 0b01111, 0b00, "fmaxv",
2380                               int_aarch64_neon_vmaxv>;
2381 defm FMINV : NeonI_2VAcross_3<0b1, 0b01111, 0b10, "fminv",
2382                               int_aarch64_neon_vminv>;
2383
2384 // The followings are for instruction class (Perm)
2385
2386 class NeonI_Permute<bit q, bits<2> size, bits<3> opcode,
2387                     string asmop, RegisterOperand OpVPR, string OpS>
2388   : NeonI_Perm<q, size, opcode,
2389                (outs OpVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2390                asmop # "\t$Rd." # OpS # ", $Rn." # OpS # ", $Rm." # OpS,
2391                [], NoItinerary>;
2392
2393 multiclass NeonI_Perm_pat<bits<3> opcode, string asmop> {
2394    def _8b  : NeonI_Permute<0b0, 0b00, opcode, asmop, VPR64,  "8b">;
2395    def _16b : NeonI_Permute<0b1, 0b00, opcode, asmop, VPR128, "16b">;
2396    def _4h  : NeonI_Permute<0b0, 0b01, opcode, asmop, VPR64,  "4h">;
2397    def _8h  : NeonI_Permute<0b1, 0b01, opcode, asmop, VPR128, "8h">;
2398    def _2s  : NeonI_Permute<0b0, 0b10, opcode, asmop, VPR64,  "2s">;
2399    def _4s  : NeonI_Permute<0b1, 0b10, opcode, asmop, VPR128, "4s">;
2400    def _2d  : NeonI_Permute<0b1, 0b11, opcode, asmop, VPR128, "2d">;
2401 }
2402
2403 defm UZP1vvv : NeonI_Perm_pat<0b001, "uzp1">;
2404 defm TRN1vvv : NeonI_Perm_pat<0b010, "trn1">;
2405 defm ZIP1vvv : NeonI_Perm_pat<0b011, "zip1">;
2406 defm UZP2vvv : NeonI_Perm_pat<0b101, "uzp2">;
2407 defm TRN2vvv : NeonI_Perm_pat<0b110, "trn2">;
2408 defm ZIP2vvv : NeonI_Perm_pat<0b111, "zip2">;
2409
2410 // Extract and Insert
2411 def NI_ei_i32 : PatFrag<(ops node:$Rn, node:$Rm, node:$Ext, node:$Ins),
2412                         (vector_insert node:$Rn,
2413                           (i32 (vector_extract node:$Rm, node:$Ext)),
2414                           node:$Ins)>;
2415
2416 def NI_ei_f32 : PatFrag<(ops node:$Rn, node:$Rm, node:$Ext, node:$Ins),
2417                         (vector_insert node:$Rn,
2418                           (f32 (vector_extract node:$Rm, node:$Ext)),
2419                           node:$Ins)>;
2420
2421 // uzp1
2422 def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2423           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2424           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2425           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2426           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2427           (v16i8 VPR128:$Rn),
2428           (v16i8 VPR128:$Rn), 2,  1)),
2429           (v16i8 VPR128:$Rn), 4,  2)),
2430           (v16i8 VPR128:$Rn), 6,  3)),
2431           (v16i8 VPR128:$Rn), 8,  4)),
2432           (v16i8 VPR128:$Rn), 10, 5)),
2433           (v16i8 VPR128:$Rn), 12, 6)),
2434           (v16i8 VPR128:$Rn), 14, 7)),
2435           (v16i8 VPR128:$Rm), 0,  8)),
2436           (v16i8 VPR128:$Rm), 2,  9)),
2437           (v16i8 VPR128:$Rm), 4,  10)),
2438           (v16i8 VPR128:$Rm), 6,  11)),
2439           (v16i8 VPR128:$Rm), 8,  12)),
2440           (v16i8 VPR128:$Rm), 10, 13)),
2441           (v16i8 VPR128:$Rm), 12, 14)),
2442           (v16i8 VPR128:$Rm), 14, 15)),
2443           (UZP1vvv_16b VPR128:$Rn, VPR128:$Rm)>;
2444
2445 class NI_Uzp1_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
2446   : Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2447         (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2448         (Ty VPR:$Rn),
2449         (Ty VPR:$Rn), 2, 1)),
2450         (Ty VPR:$Rn), 4, 2)),
2451         (Ty VPR:$Rn), 6, 3)),
2452         (Ty VPR:$Rm), 0, 4)),
2453         (Ty VPR:$Rm), 2, 5)),
2454         (Ty VPR:$Rm), 4, 6)),
2455         (Ty VPR:$Rm), 6, 7)),
2456         (INST VPR:$Rn, VPR:$Rm)>;
2457
2458 def : NI_Uzp1_v8<v8i8, VPR64, UZP1vvv_8b>;
2459 def : NI_Uzp1_v8<v8i16, VPR128, UZP1vvv_8h>;
2460
2461 class NI_Uzp1_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
2462                  PatFrag ei>
2463   : Pat<(Ty (ei (Ty (ei (Ty (ei
2464         (Ty VPR:$Rn),
2465         (Ty VPR:$Rn), 2, 1)),
2466         (Ty VPR:$Rm), 0, 2)),
2467         (Ty VPR:$Rm), 2, 3)),
2468         (INST VPR:$Rn, VPR:$Rm)>;
2469
2470 def : NI_Uzp1_v4<v4i16, VPR64, UZP1vvv_4h, NI_ei_i32>;
2471 def : NI_Uzp1_v4<v4i32, VPR128, UZP1vvv_4s, NI_ei_i32>;
2472 def : NI_Uzp1_v4<v4f32, VPR128, UZP1vvv_4s, NI_ei_f32>;
2473
2474 // uzp2
2475 def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2476           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2477           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2478           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2479           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2480           (v16i8 VPR128:$Rm),
2481           (v16i8 VPR128:$Rn), 1,  0)),
2482           (v16i8 VPR128:$Rn), 3,  1)),
2483           (v16i8 VPR128:$Rn), 5,  2)),
2484           (v16i8 VPR128:$Rn), 7,  3)),
2485           (v16i8 VPR128:$Rn), 9,  4)),
2486           (v16i8 VPR128:$Rn), 11, 5)),
2487           (v16i8 VPR128:$Rn), 13, 6)),
2488           (v16i8 VPR128:$Rn), 15, 7)),
2489           (v16i8 VPR128:$Rm), 1,  8)),
2490           (v16i8 VPR128:$Rm), 3,  9)),
2491           (v16i8 VPR128:$Rm), 5,  10)),
2492           (v16i8 VPR128:$Rm), 7,  11)),
2493           (v16i8 VPR128:$Rm), 9,  12)),
2494           (v16i8 VPR128:$Rm), 11, 13)),
2495           (v16i8 VPR128:$Rm), 13, 14)),
2496           (UZP2vvv_16b VPR128:$Rn, VPR128:$Rm)>;
2497
2498 class NI_Uzp2_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
2499   : Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2500         (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2501         (Ty VPR:$Rm),
2502         (Ty VPR:$Rn), 1, 0)),
2503         (Ty VPR:$Rn), 3, 1)),
2504         (Ty VPR:$Rn), 5, 2)),
2505         (Ty VPR:$Rn), 7, 3)),
2506         (Ty VPR:$Rm), 1, 4)),
2507         (Ty VPR:$Rm), 3, 5)),
2508         (Ty VPR:$Rm), 5, 6)),
2509         (INST VPR:$Rn, VPR:$Rm)>;
2510
2511 def : NI_Uzp2_v8<v8i8, VPR64, UZP2vvv_8b>;
2512 def : NI_Uzp2_v8<v8i16, VPR128, UZP2vvv_8h>;
2513
2514 class NI_Uzp2_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
2515                  PatFrag ei>
2516   : Pat<(Ty (ei (Ty (ei (Ty (ei
2517         (Ty VPR:$Rm),
2518         (Ty VPR:$Rn), 1, 0)),
2519         (Ty VPR:$Rn), 3, 1)),
2520         (Ty VPR:$Rm), 1, 2)),
2521         (INST VPR:$Rn, VPR:$Rm)>;
2522
2523 def : NI_Uzp2_v4<v4i16, VPR64, UZP2vvv_4h, NI_ei_i32>;
2524 def : NI_Uzp2_v4<v4i32, VPR128, UZP2vvv_4s, NI_ei_i32>;
2525 def : NI_Uzp2_v4<v4f32, VPR128, UZP2vvv_4s, NI_ei_f32>;
2526
2527 // zip1
2528 def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2529           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2530           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2531           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2532           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2533           (v16i8 VPR128:$Rn),
2534           (v16i8 VPR128:$Rm), 0, 1)),
2535           (v16i8 VPR128:$Rn), 1, 2)),
2536           (v16i8 VPR128:$Rm), 1, 3)),
2537           (v16i8 VPR128:$Rn), 2, 4)),
2538           (v16i8 VPR128:$Rm), 2, 5)),
2539           (v16i8 VPR128:$Rn), 3, 6)),
2540           (v16i8 VPR128:$Rm), 3, 7)),
2541           (v16i8 VPR128:$Rn), 4, 8)),
2542           (v16i8 VPR128:$Rm), 4, 9)),
2543           (v16i8 VPR128:$Rn), 5, 10)),
2544           (v16i8 VPR128:$Rm), 5, 11)),
2545           (v16i8 VPR128:$Rn), 6, 12)),
2546           (v16i8 VPR128:$Rm), 6, 13)),
2547           (v16i8 VPR128:$Rn), 7, 14)),
2548           (v16i8 VPR128:$Rm), 7, 15)),
2549           (ZIP1vvv_16b VPR128:$Rn, VPR128:$Rm)>;
2550
2551 class NI_Zip1_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
2552   : Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2553         (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2554         (Ty VPR:$Rn),
2555         (Ty VPR:$Rm), 0, 1)),
2556         (Ty VPR:$Rn), 1, 2)),
2557         (Ty VPR:$Rm), 1, 3)),
2558         (Ty VPR:$Rn), 2, 4)),
2559         (Ty VPR:$Rm), 2, 5)),
2560         (Ty VPR:$Rn), 3, 6)),
2561         (Ty VPR:$Rm), 3, 7)),
2562         (INST VPR:$Rn, VPR:$Rm)>;
2563
2564 def : NI_Zip1_v8<v8i8, VPR64, ZIP1vvv_8b>;
2565 def : NI_Zip1_v8<v8i16, VPR128, ZIP1vvv_8h>;
2566
2567 class NI_Zip1_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
2568                  PatFrag ei>
2569   : Pat<(Ty (ei (Ty (ei (Ty (ei
2570         (Ty VPR:$Rn),
2571         (Ty VPR:$Rm), 0, 1)),
2572         (Ty VPR:$Rn), 1, 2)),
2573         (Ty VPR:$Rm), 1, 3)),
2574         (INST VPR:$Rn, VPR:$Rm)>;
2575
2576 def : NI_Zip1_v4<v4i16, VPR64, ZIP1vvv_4h, NI_ei_i32>;
2577 def : NI_Zip1_v4<v4i32, VPR128, ZIP1vvv_4s, NI_ei_i32>;
2578 def : NI_Zip1_v4<v4f32, VPR128, ZIP1vvv_4s, NI_ei_f32>;
2579
2580 // zip2
2581 def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2582           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2583           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2584           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2585           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2586           (v16i8 VPR128:$Rm),
2587           (v16i8 VPR128:$Rn), 8, 0)),
2588           (v16i8 VPR128:$Rm), 8, 1)),
2589           (v16i8 VPR128:$Rn), 9, 2)),
2590           (v16i8 VPR128:$Rm), 9, 3)),
2591           (v16i8 VPR128:$Rn), 10, 4)),
2592           (v16i8 VPR128:$Rm), 10, 5)),
2593           (v16i8 VPR128:$Rn), 11, 6)),
2594           (v16i8 VPR128:$Rm), 11, 7)),
2595           (v16i8 VPR128:$Rn), 12, 8)),
2596           (v16i8 VPR128:$Rm), 12, 9)),
2597           (v16i8 VPR128:$Rn), 13, 10)),
2598           (v16i8 VPR128:$Rm), 13, 11)),
2599           (v16i8 VPR128:$Rn), 14, 12)),
2600           (v16i8 VPR128:$Rm), 14, 13)),
2601           (v16i8 VPR128:$Rn), 15, 14)),
2602           (ZIP2vvv_16b VPR128:$Rn, VPR128:$Rm)>;
2603
2604 class NI_Zip2_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
2605   : Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2606         (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2607         (Ty VPR:$Rm),
2608         (Ty VPR:$Rn), 4, 0)),
2609         (Ty VPR:$Rm), 4, 1)),
2610         (Ty VPR:$Rn), 5, 2)),
2611         (Ty VPR:$Rm), 5, 3)),
2612         (Ty VPR:$Rn), 6, 4)),
2613         (Ty VPR:$Rm), 6, 5)),
2614         (Ty VPR:$Rn), 7, 6)),
2615         (INST VPR:$Rn, VPR:$Rm)>;
2616
2617 def : NI_Zip2_v8<v8i8, VPR64, ZIP2vvv_8b>;
2618 def : NI_Zip2_v8<v8i16, VPR128, ZIP2vvv_8h>;
2619
2620 class NI_Zip2_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
2621                  PatFrag ei>
2622   : Pat<(Ty (ei (Ty (ei (Ty (ei
2623         (Ty VPR:$Rm),
2624         (Ty VPR:$Rn), 2, 0)),
2625         (Ty VPR:$Rm), 2, 1)),
2626         (Ty VPR:$Rn), 3, 2)),
2627         (INST VPR:$Rn, VPR:$Rm)>;
2628
2629 def : NI_Zip2_v4<v4i16, VPR64, ZIP2vvv_4h, NI_ei_i32>;
2630 def : NI_Zip2_v4<v4i32, VPR128, ZIP2vvv_4s, NI_ei_i32>;
2631 def : NI_Zip2_v4<v4f32, VPR128, ZIP2vvv_4s, NI_ei_f32>;
2632
2633 // trn1
2634 def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2635           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2636           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2637           (v16i8 VPR128:$Rn),
2638           (v16i8 VPR128:$Rm), 0,  1)),
2639           (v16i8 VPR128:$Rm), 2,  3)),
2640           (v16i8 VPR128:$Rm), 4,  5)),
2641           (v16i8 VPR128:$Rm), 6,  7)),
2642           (v16i8 VPR128:$Rm), 8,  9)),
2643           (v16i8 VPR128:$Rm), 10, 11)),
2644           (v16i8 VPR128:$Rm), 12, 13)),
2645           (v16i8 VPR128:$Rm), 14, 15)),
2646           (TRN1vvv_16b VPR128:$Rn, VPR128:$Rm)>;
2647
2648 class NI_Trn1_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
2649   : Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2650         (Ty VPR:$Rn),
2651         (Ty VPR:$Rm), 0, 1)),
2652         (Ty VPR:$Rm), 2, 3)),
2653         (Ty VPR:$Rm), 4, 5)),
2654         (Ty VPR:$Rm), 6, 7)),
2655         (INST VPR:$Rn, VPR:$Rm)>;
2656
2657 def : NI_Trn1_v8<v8i8, VPR64, TRN1vvv_8b>;
2658 def : NI_Trn1_v8<v8i16, VPR128, TRN1vvv_8h>;
2659
2660 class NI_Trn1_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
2661                  PatFrag ei>
2662   : Pat<(Ty (ei (Ty (ei
2663         (Ty VPR:$Rn),
2664         (Ty VPR:$Rm), 0, 1)),
2665         (Ty VPR:$Rm), 2, 3)),
2666         (INST VPR:$Rn, VPR:$Rm)>;
2667
2668 def : NI_Trn1_v4<v4i16, VPR64, TRN1vvv_4h, NI_ei_i32>;
2669 def : NI_Trn1_v4<v4i32, VPR128, TRN1vvv_4s, NI_ei_i32>;
2670 def : NI_Trn1_v4<v4f32, VPR128, TRN1vvv_4s, NI_ei_f32>;
2671
2672 // trn2
2673 def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2674           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2675           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2676           (v16i8 VPR128:$Rm),
2677           (v16i8 VPR128:$Rn), 1,  0)),
2678           (v16i8 VPR128:$Rn), 3,  2)),
2679           (v16i8 VPR128:$Rn), 5,  4)),
2680           (v16i8 VPR128:$Rn), 7,  6)),
2681           (v16i8 VPR128:$Rn), 9,  8)),
2682           (v16i8 VPR128:$Rn), 11, 10)),
2683           (v16i8 VPR128:$Rn), 13, 12)),
2684           (v16i8 VPR128:$Rn), 15, 14)),
2685           (TRN2vvv_16b VPR128:$Rn, VPR128:$Rm)>;
2686
2687 class NI_Trn2_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
2688   : Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2689         (Ty VPR:$Rm),
2690         (Ty VPR:$Rn), 1, 0)),
2691         (Ty VPR:$Rn), 3, 2)),
2692         (Ty VPR:$Rn), 5, 4)),
2693         (Ty VPR:$Rn), 7, 6)),
2694         (INST VPR:$Rn, VPR:$Rm)>;
2695
2696 def : NI_Trn2_v8<v8i8, VPR64, TRN2vvv_8b>;
2697 def : NI_Trn2_v8<v8i16, VPR128, TRN2vvv_8h>;
2698
2699 class NI_Trn2_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
2700                  PatFrag ei>
2701   : Pat<(Ty (ei (Ty (ei
2702         (Ty VPR:$Rm),
2703         (Ty VPR:$Rn), 1, 0)),
2704         (Ty VPR:$Rn), 3, 2)),
2705         (INST VPR:$Rn, VPR:$Rm)>;
2706
2707 def : NI_Trn2_v4<v4i16, VPR64, TRN2vvv_4h, NI_ei_i32>;
2708 def : NI_Trn2_v4<v4i32, VPR128, TRN2vvv_4s, NI_ei_i32>;
2709 def : NI_Trn2_v4<v4f32, VPR128, TRN2vvv_4s, NI_ei_f32>;
2710
2711 // End of implementation for instruction class (Perm)
2712
2713 // The followings are for instruction class (3V Diff)
2714
2715 // normal long/long2 pattern
2716 class NeonI_3VDL<bit q, bit u, bits<2> size, bits<4> opcode,
2717                  string asmop, string ResS, string OpS,
2718                  SDPatternOperator opnode, SDPatternOperator ext,
2719                  RegisterOperand OpVPR,
2720                  ValueType ResTy, ValueType OpTy>
2721   : NeonI_3VDiff<q, u, size, opcode,
2722                  (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2723                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2724                  [(set (ResTy VPR128:$Rd),
2725                     (ResTy (opnode (ResTy (ext (OpTy OpVPR:$Rn))),
2726                                    (ResTy (ext (OpTy OpVPR:$Rm))))))],
2727                  NoItinerary>;
2728
2729 multiclass NeonI_3VDL_s<bit u, bits<4> opcode,
2730                         string asmop, SDPatternOperator opnode,
2731                         bit Commutable = 0> {
2732   let isCommutable = Commutable in {
2733     def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2734                            opnode, sext, VPR64, v8i16, v8i8>;
2735     def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2736                            opnode, sext, VPR64, v4i32, v4i16>;
2737     def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2738                            opnode, sext, VPR64, v2i64, v2i32>;
2739   }
2740 }
2741
2742 multiclass NeonI_3VDL2_s<bit u, bits<4> opcode, string asmop,
2743                          SDPatternOperator opnode, bit Commutable = 0> {
2744   let isCommutable = Commutable in {
2745     def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2746                             opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2747     def _4s8h  : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2748                             opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2749     def _2d4s  : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2750                             opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2751   }
2752 }
2753
2754 multiclass NeonI_3VDL_u<bit u, bits<4> opcode, string asmop,
2755                         SDPatternOperator opnode, bit Commutable = 0> {
2756   let isCommutable = Commutable in {
2757     def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2758                            opnode, zext, VPR64, v8i16, v8i8>;
2759     def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2760                            opnode, zext, VPR64, v4i32, v4i16>;
2761     def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2762                            opnode, zext, VPR64, v2i64, v2i32>;
2763   }
2764 }
2765
2766 multiclass NeonI_3VDL2_u<bit u, bits<4> opcode, string asmop,
2767                          SDPatternOperator opnode, bit Commutable = 0> {
2768   let isCommutable = Commutable in {
2769     def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2770                             opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2771     def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2772                            opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2773     def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2774                            opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2775   }
2776 }
2777
2778 defm SADDLvvv :  NeonI_3VDL_s<0b0, 0b0000, "saddl", add, 1>;
2779 defm UADDLvvv :  NeonI_3VDL_u<0b1, 0b0000, "uaddl", add, 1>;
2780
2781 defm SADDL2vvv :  NeonI_3VDL2_s<0b0, 0b0000, "saddl2", add, 1>;
2782 defm UADDL2vvv :  NeonI_3VDL2_u<0b1, 0b0000, "uaddl2", add, 1>;
2783
2784 defm SSUBLvvv :  NeonI_3VDL_s<0b0, 0b0010, "ssubl", sub, 0>;
2785 defm USUBLvvv :  NeonI_3VDL_u<0b1, 0b0010, "usubl", sub, 0>;
2786
2787 defm SSUBL2vvv :  NeonI_3VDL2_s<0b0, 0b0010, "ssubl2", sub, 0>;
2788 defm USUBL2vvv :  NeonI_3VDL2_u<0b1, 0b0010, "usubl2", sub, 0>;
2789
2790 // normal wide/wide2 pattern
2791 class NeonI_3VDW<bit q, bit u, bits<2> size, bits<4> opcode,
2792                  string asmop, string ResS, string OpS,
2793                  SDPatternOperator opnode, SDPatternOperator ext,
2794                  RegisterOperand OpVPR,
2795                  ValueType ResTy, ValueType OpTy>
2796   : NeonI_3VDiff<q, u, size, opcode,
2797                  (outs VPR128:$Rd), (ins VPR128:$Rn, OpVPR:$Rm),
2798                  asmop # "\t$Rd." # ResS # ", $Rn." # ResS # ", $Rm." # OpS,
2799                  [(set (ResTy VPR128:$Rd),
2800                     (ResTy (opnode (ResTy VPR128:$Rn),
2801                                    (ResTy (ext (OpTy OpVPR:$Rm))))))],
2802                  NoItinerary>;
2803
2804 multiclass NeonI_3VDW_s<bit u, bits<4> opcode, string asmop,
2805                         SDPatternOperator opnode> {
2806   def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2807                          opnode, sext, VPR64, v8i16, v8i8>;
2808   def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2809                          opnode, sext, VPR64, v4i32, v4i16>;
2810   def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2811                          opnode, sext, VPR64, v2i64, v2i32>;
2812 }
2813
2814 defm SADDWvvv :  NeonI_3VDW_s<0b0, 0b0001, "saddw", add>;
2815 defm SSUBWvvv :  NeonI_3VDW_s<0b0, 0b0011, "ssubw", sub>;
2816
2817 multiclass NeonI_3VDW2_s<bit u, bits<4> opcode, string asmop,
2818                          SDPatternOperator opnode> {
2819   def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2820                           opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2821   def _4s8h  : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2822                           opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2823   def _2d4s  : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2824                           opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2825 }
2826
2827 defm SADDW2vvv :  NeonI_3VDW2_s<0b0, 0b0001, "saddw2", add>;
2828 defm SSUBW2vvv :  NeonI_3VDW2_s<0b0, 0b0011, "ssubw2", sub>;
2829
2830 multiclass NeonI_3VDW_u<bit u, bits<4> opcode, string asmop,
2831                         SDPatternOperator opnode> {
2832   def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2833                          opnode, zext, VPR64, v8i16, v8i8>;
2834   def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2835                          opnode, zext, VPR64, v4i32, v4i16>;
2836   def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2837                          opnode, zext, VPR64, v2i64, v2i32>;
2838 }
2839
2840 defm UADDWvvv :  NeonI_3VDW_u<0b1, 0b0001, "uaddw", add>;
2841 defm USUBWvvv :  NeonI_3VDW_u<0b1, 0b0011, "usubw", sub>;
2842
2843 multiclass NeonI_3VDW2_u<bit u, bits<4> opcode, string asmop,
2844                          SDPatternOperator opnode> {
2845   def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2846                           opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2847   def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2848                          opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2849   def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2850                          opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2851 }
2852
2853 defm UADDW2vvv :  NeonI_3VDW2_u<0b1, 0b0001, "uaddw2", add>;
2854 defm USUBW2vvv :  NeonI_3VDW2_u<0b1, 0b0011, "usubw2", sub>;
2855
2856 // Get the high half part of the vector element.
2857 multiclass NeonI_get_high {
2858   def _8h : PatFrag<(ops node:$Rn),
2859                     (v8i8 (trunc (v8i16 (srl (v8i16 node:$Rn),
2860                                              (v8i16 (Neon_vdup (i32 8)))))))>;
2861   def _4s : PatFrag<(ops node:$Rn),
2862                     (v4i16 (trunc (v4i32 (srl (v4i32 node:$Rn),
2863                                               (v4i32 (Neon_vdup (i32 16)))))))>;
2864   def _2d : PatFrag<(ops node:$Rn),
2865                     (v2i32 (trunc (v2i64 (srl (v2i64 node:$Rn),
2866                                               (v2i64 (Neon_vdup (i32 32)))))))>;
2867 }
2868
2869 defm NI_get_hi : NeonI_get_high;
2870
2871 // pattern for addhn/subhn with 2 operands
2872 class NeonI_3VDN_addhn_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2873                            string asmop, string ResS, string OpS,
2874                            SDPatternOperator opnode, SDPatternOperator get_hi,
2875                            ValueType ResTy, ValueType OpTy>
2876   : NeonI_3VDiff<q, u, size, opcode,
2877                  (outs VPR64:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2878                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2879                  [(set (ResTy VPR64:$Rd),
2880                     (ResTy (get_hi
2881                       (OpTy (opnode (OpTy VPR128:$Rn),
2882                                     (OpTy VPR128:$Rm))))))],
2883                  NoItinerary>;
2884
2885 multiclass NeonI_3VDN_addhn_2Op<bit u, bits<4> opcode, string asmop,
2886                                 SDPatternOperator opnode, bit Commutable = 0> {
2887   let isCommutable = Commutable in {
2888     def _8b8h : NeonI_3VDN_addhn_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2889                                      opnode, NI_get_hi_8h, v8i8, v8i16>;
2890     def _4h4s : NeonI_3VDN_addhn_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2891                                      opnode, NI_get_hi_4s, v4i16, v4i32>;
2892     def _2s2d : NeonI_3VDN_addhn_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2893                                      opnode, NI_get_hi_2d, v2i32, v2i64>;
2894   }
2895 }
2896
2897 defm ADDHNvvv  : NeonI_3VDN_addhn_2Op<0b0, 0b0100, "addhn", add, 1>;
2898 defm SUBHNvvv  : NeonI_3VDN_addhn_2Op<0b0, 0b0110, "subhn", sub, 0>;
2899
2900 // pattern for operation with 2 operands
2901 class NeonI_3VD_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2902                     string asmop, string ResS, string OpS,
2903                     SDPatternOperator opnode,
2904                     RegisterOperand ResVPR, RegisterOperand OpVPR,
2905                     ValueType ResTy, ValueType OpTy>
2906   : NeonI_3VDiff<q, u, size, opcode,
2907                  (outs ResVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2908                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2909                  [(set (ResTy ResVPR:$Rd),
2910                     (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))],
2911                  NoItinerary>;
2912
2913 // normal narrow pattern
2914 multiclass NeonI_3VDN_2Op<bit u, bits<4> opcode, string asmop,
2915                           SDPatternOperator opnode, bit Commutable = 0> {
2916   let isCommutable = Commutable in {
2917     def _8b8h : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2918                               opnode, VPR64, VPR128, v8i8, v8i16>;
2919     def _4h4s : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2920                               opnode, VPR64, VPR128, v4i16, v4i32>;
2921     def _2s2d : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2922                               opnode, VPR64, VPR128, v2i32, v2i64>;
2923   }
2924 }
2925
2926 defm RADDHNvvv : NeonI_3VDN_2Op<0b1, 0b0100, "raddhn", int_arm_neon_vraddhn, 1>;
2927 defm RSUBHNvvv : NeonI_3VDN_2Op<0b1, 0b0110, "rsubhn", int_arm_neon_vrsubhn, 0>;
2928
2929 // pattern for acle intrinsic with 3 operands
2930 class NeonI_3VDN_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2931                      string asmop, string ResS, string OpS>
2932   : NeonI_3VDiff<q, u, size, opcode,
2933                  (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
2934                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2935                  [], NoItinerary> {
2936   let Constraints = "$src = $Rd";
2937   let neverHasSideEffects = 1;
2938 }
2939
2940 multiclass NeonI_3VDN_3Op_v1<bit u, bits<4> opcode, string asmop> {
2941   def _16b8h : NeonI_3VDN_3Op<0b1, u, 0b00, opcode, asmop, "16b", "8h">;
2942   def _8h4s : NeonI_3VDN_3Op<0b1, u, 0b01, opcode, asmop, "8h", "4s">;
2943   def _4s2d : NeonI_3VDN_3Op<0b1, u, 0b10, opcode, asmop, "4s", "2d">;
2944 }
2945
2946 defm ADDHN2vvv  : NeonI_3VDN_3Op_v1<0b0, 0b0100, "addhn2">;
2947 defm SUBHN2vvv  : NeonI_3VDN_3Op_v1<0b0, 0b0110, "subhn2">;
2948
2949 defm RADDHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0100, "raddhn2">;
2950 defm RSUBHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0110, "rsubhn2">;
2951
2952 // Patterns have to be separate because there's a SUBREG_TO_REG in the output
2953 // part.
2954 class NarrowHighHalfPat<Instruction INST, ValueType DstTy, ValueType SrcTy,
2955                         SDPatternOperator coreop>
2956   : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2957                       (v1i64 (bitconvert (DstTy (coreop (SrcTy VPR128:$Rn),
2958                                                         (SrcTy VPR128:$Rm)))))),
2959         (INST (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2960               VPR128:$Rn, VPR128:$Rm)>;
2961
2962 // addhn2 patterns
2963 def : NarrowHighHalfPat<ADDHN2vvv_16b8h, v8i8,  v8i16,
2964           BinOpFrag<(NI_get_hi_8h (add node:$LHS, node:$RHS))>>;
2965 def : NarrowHighHalfPat<ADDHN2vvv_8h4s,  v4i16, v4i32,
2966           BinOpFrag<(NI_get_hi_4s (add node:$LHS, node:$RHS))>>;
2967 def : NarrowHighHalfPat<ADDHN2vvv_4s2d,  v2i32, v2i64,
2968           BinOpFrag<(NI_get_hi_2d (add node:$LHS, node:$RHS))>>;
2969
2970 // subhn2 patterns
2971 def : NarrowHighHalfPat<SUBHN2vvv_16b8h, v8i8,  v8i16,
2972           BinOpFrag<(NI_get_hi_8h (sub node:$LHS, node:$RHS))>>;
2973 def : NarrowHighHalfPat<SUBHN2vvv_8h4s,  v4i16, v4i32,
2974           BinOpFrag<(NI_get_hi_4s (sub node:$LHS, node:$RHS))>>;
2975 def : NarrowHighHalfPat<SUBHN2vvv_4s2d,  v2i32, v2i64,
2976           BinOpFrag<(NI_get_hi_2d (sub node:$LHS, node:$RHS))>>;
2977
2978 // raddhn2 patterns
2979 def : NarrowHighHalfPat<RADDHN2vvv_16b8h, v8i8,  v8i16, int_arm_neon_vraddhn>;
2980 def : NarrowHighHalfPat<RADDHN2vvv_8h4s,  v4i16, v4i32, int_arm_neon_vraddhn>;
2981 def : NarrowHighHalfPat<RADDHN2vvv_4s2d,  v2i32, v2i64, int_arm_neon_vraddhn>;
2982
2983 // rsubhn2 patterns
2984 def : NarrowHighHalfPat<RSUBHN2vvv_16b8h, v8i8,  v8i16, int_arm_neon_vrsubhn>;
2985 def : NarrowHighHalfPat<RSUBHN2vvv_8h4s,  v4i16, v4i32, int_arm_neon_vrsubhn>;
2986 def : NarrowHighHalfPat<RSUBHN2vvv_4s2d,  v2i32, v2i64, int_arm_neon_vrsubhn>;
2987
2988 // pattern that need to extend result
2989 class NeonI_3VDL_Ext<bit q, bit u, bits<2> size, bits<4> opcode,
2990                      string asmop, string ResS, string OpS,
2991                      SDPatternOperator opnode,
2992                      RegisterOperand OpVPR,
2993                      ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2994   : NeonI_3VDiff<q, u, size, opcode,
2995                  (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2996                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2997                  [(set (ResTy VPR128:$Rd),
2998                     (ResTy (zext (OpSTy (opnode (OpTy OpVPR:$Rn),
2999                                                 (OpTy OpVPR:$Rm))))))],
3000                  NoItinerary>;
3001
3002 multiclass NeonI_3VDL_zext<bit u, bits<4> opcode, string asmop,
3003                            SDPatternOperator opnode, bit Commutable = 0> {
3004   let isCommutable = Commutable in {
3005     def _8h8b : NeonI_3VDL_Ext<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3006                                opnode, VPR64, v8i16, v8i8, v8i8>;
3007     def _4s4h : NeonI_3VDL_Ext<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3008                                opnode, VPR64, v4i32, v4i16, v4i16>;
3009     def _2d2s : NeonI_3VDL_Ext<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3010                                opnode, VPR64, v2i64, v2i32, v2i32>;
3011   }
3012 }
3013
3014 defm SABDLvvv : NeonI_3VDL_zext<0b0, 0b0111, "sabdl", int_arm_neon_vabds, 1>;
3015 defm UABDLvvv : NeonI_3VDL_zext<0b1, 0b0111, "uabdl", int_arm_neon_vabdu, 1>;
3016
3017 multiclass NeonI_Op_High<SDPatternOperator op> {
3018   def _16B : PatFrag<(ops node:$Rn, node:$Rm),
3019                      (op (v8i8 (Neon_High16B node:$Rn)),
3020                          (v8i8 (Neon_High16B node:$Rm)))>;
3021   def _8H  : PatFrag<(ops node:$Rn, node:$Rm),
3022                      (op (v4i16 (Neon_High8H node:$Rn)),
3023                          (v4i16 (Neon_High8H node:$Rm)))>;
3024   def _4S  : PatFrag<(ops node:$Rn, node:$Rm),
3025                      (op (v2i32 (Neon_High4S node:$Rn)),
3026                          (v2i32 (Neon_High4S node:$Rm)))>;
3027 }
3028
3029 defm NI_sabdl_hi : NeonI_Op_High<int_arm_neon_vabds>;
3030 defm NI_uabdl_hi : NeonI_Op_High<int_arm_neon_vabdu>;
3031 defm NI_smull_hi : NeonI_Op_High<int_arm_neon_vmulls>;
3032 defm NI_umull_hi : NeonI_Op_High<int_arm_neon_vmullu>;
3033 defm NI_qdmull_hi : NeonI_Op_High<int_arm_neon_vqdmull>;
3034 defm NI_pmull_hi : NeonI_Op_High<int_arm_neon_vmullp>;
3035
3036 multiclass NeonI_3VDL_Abd_u<bit u, bits<4> opcode, string asmop, string opnode,
3037                             bit Commutable = 0> {
3038   let isCommutable = Commutable in {
3039     def _8h8b  : NeonI_3VDL_Ext<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3040                                 !cast<PatFrag>(opnode # "_16B"),
3041                                 VPR128, v8i16, v16i8, v8i8>;
3042     def _4s4h  : NeonI_3VDL_Ext<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3043                                 !cast<PatFrag>(opnode # "_8H"),
3044                                 VPR128, v4i32, v8i16, v4i16>;
3045     def _2d2s  : NeonI_3VDL_Ext<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3046                                 !cast<PatFrag>(opnode # "_4S"),
3047                                 VPR128, v2i64, v4i32, v2i32>;
3048   }
3049 }
3050
3051 defm SABDL2vvv : NeonI_3VDL_Abd_u<0b0, 0b0111, "sabdl2", "NI_sabdl_hi", 1>;
3052 defm UABDL2vvv : NeonI_3VDL_Abd_u<0b1, 0b0111, "uabdl2", "NI_uabdl_hi", 1>;
3053
3054 // For pattern that need two operators being chained.
3055 class NeonI_3VDL_Aba<bit q, bit u, bits<2> size, bits<4> opcode,
3056                      string asmop, string ResS, string OpS,
3057                      SDPatternOperator opnode, SDPatternOperator subop,
3058                      RegisterOperand OpVPR,
3059                      ValueType ResTy, ValueType OpTy, ValueType OpSTy>
3060   : NeonI_3VDiff<q, u, size, opcode,
3061                  (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
3062                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3063                  [(set (ResTy VPR128:$Rd),
3064                     (ResTy (opnode
3065                       (ResTy VPR128:$src),
3066                       (ResTy (zext (OpSTy (subop (OpTy OpVPR:$Rn),
3067                                                  (OpTy OpVPR:$Rm))))))))],
3068                  NoItinerary> {
3069   let Constraints = "$src = $Rd";
3070 }
3071
3072 multiclass NeonI_3VDL_Aba_v1<bit u, bits<4> opcode, string asmop,
3073                              SDPatternOperator opnode, SDPatternOperator subop>{
3074   def _8h8b : NeonI_3VDL_Aba<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3075                              opnode, subop, VPR64, v8i16, v8i8, v8i8>;
3076   def _4s4h : NeonI_3VDL_Aba<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3077                              opnode, subop, VPR64, v4i32, v4i16, v4i16>;
3078   def _2d2s : NeonI_3VDL_Aba<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3079                              opnode, subop, VPR64, v2i64, v2i32, v2i32>;
3080 }
3081
3082 defm SABALvvv :  NeonI_3VDL_Aba_v1<0b0, 0b0101, "sabal",
3083                                    add, int_arm_neon_vabds>;
3084 defm UABALvvv :  NeonI_3VDL_Aba_v1<0b1, 0b0101, "uabal",
3085                                    add, int_arm_neon_vabdu>;
3086
3087 multiclass NeonI_3VDL2_Aba_v1<bit u, bits<4> opcode, string asmop,
3088                               SDPatternOperator opnode, string subop> {
3089   def _8h8b : NeonI_3VDL_Aba<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3090                              opnode, !cast<PatFrag>(subop # "_16B"),
3091                              VPR128, v8i16, v16i8, v8i8>;
3092   def _4s4h : NeonI_3VDL_Aba<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3093                              opnode, !cast<PatFrag>(subop # "_8H"),
3094                              VPR128, v4i32, v8i16, v4i16>;
3095   def _2d2s : NeonI_3VDL_Aba<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3096                              opnode, !cast<PatFrag>(subop # "_4S"),
3097                              VPR128, v2i64, v4i32, v2i32>;
3098 }
3099
3100 defm SABAL2vvv :  NeonI_3VDL2_Aba_v1<0b0, 0b0101, "sabal2", add,
3101                                      "NI_sabdl_hi">;
3102 defm UABAL2vvv :  NeonI_3VDL2_Aba_v1<0b1, 0b0101, "uabal2", add,
3103                                      "NI_uabdl_hi">;
3104
3105 // Long pattern with 2 operands
3106 multiclass NeonI_3VDL_2Op<bit u, bits<4> opcode, string asmop,
3107                           SDPatternOperator opnode, bit Commutable = 0> {
3108   let isCommutable = Commutable in {
3109     def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3110                               opnode, VPR128, VPR64, v8i16, v8i8>;
3111     def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3112                               opnode, VPR128, VPR64, v4i32, v4i16>;
3113     def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3114                               opnode, VPR128, VPR64, v2i64, v2i32>;
3115   }
3116 }
3117
3118 defm SMULLvvv :  NeonI_3VDL_2Op<0b0, 0b1100, "smull", int_arm_neon_vmulls, 1>;
3119 defm UMULLvvv :  NeonI_3VDL_2Op<0b1, 0b1100, "umull", int_arm_neon_vmullu, 1>;
3120
3121 class NeonI_3VDL2_2Op_mull<bit q, bit u, bits<2> size, bits<4> opcode,
3122                            string asmop, string ResS, string OpS,
3123                            SDPatternOperator opnode,
3124                            ValueType ResTy, ValueType OpTy>
3125   : NeonI_3VDiff<q, u, size, opcode,
3126                  (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3127                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3128                  [(set (ResTy VPR128:$Rd),
3129                     (ResTy (opnode (OpTy VPR128:$Rn), (OpTy VPR128:$Rm))))],
3130                  NoItinerary>;
3131
3132 multiclass NeonI_3VDL2_2Op_mull_v1<bit u, bits<4> opcode, string asmop,
3133                                    string opnode, bit Commutable = 0> {
3134   let isCommutable = Commutable in {
3135     def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3136                                       !cast<PatFrag>(opnode # "_16B"),
3137                                       v8i16, v16i8>;
3138     def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3139                                      !cast<PatFrag>(opnode # "_8H"),
3140                                      v4i32, v8i16>;
3141     def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3142                                      !cast<PatFrag>(opnode # "_4S"),
3143                                      v2i64, v4i32>;
3144   }
3145 }
3146
3147 defm SMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b0, 0b1100, "smull2",
3148                                          "NI_smull_hi", 1>;
3149 defm UMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b1, 0b1100, "umull2",
3150                                          "NI_umull_hi", 1>;
3151
3152 // Long pattern with 3 operands
3153 class NeonI_3VDL_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
3154                      string asmop, string ResS, string OpS,
3155                      SDPatternOperator opnode,
3156                      ValueType ResTy, ValueType OpTy>
3157   : NeonI_3VDiff<q, u, size, opcode,
3158                  (outs VPR128:$Rd), (ins VPR128:$src, VPR64:$Rn, VPR64:$Rm),
3159                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3160                  [(set (ResTy VPR128:$Rd),
3161                     (ResTy (opnode
3162                       (ResTy VPR128:$src),
3163                       (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))))],
3164                NoItinerary> {
3165   let Constraints = "$src = $Rd";
3166 }
3167
3168 multiclass NeonI_3VDL_3Op_v1<bit u, bits<4> opcode, string asmop,
3169                              SDPatternOperator opnode> {
3170   def _8h8b : NeonI_3VDL_3Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3171                              opnode, v8i16, v8i8>;
3172   def _4s4h : NeonI_3VDL_3Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3173                              opnode, v4i32, v4i16>;
3174   def _2d2s : NeonI_3VDL_3Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3175                              opnode, v2i64, v2i32>;
3176 }
3177
3178 def Neon_smlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3179                          (add node:$Rd,
3180                             (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
3181
3182 def Neon_umlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3183                          (add node:$Rd,
3184                             (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
3185
3186 def Neon_smlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3187                          (sub node:$Rd,
3188                             (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
3189
3190 def Neon_umlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3191                          (sub node:$Rd,
3192                             (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
3193
3194 defm SMLALvvv :  NeonI_3VDL_3Op_v1<0b0, 0b1000, "smlal", Neon_smlal>;
3195 defm UMLALvvv :  NeonI_3VDL_3Op_v1<0b1, 0b1000, "umlal", Neon_umlal>;
3196
3197 defm SMLSLvvv :  NeonI_3VDL_3Op_v1<0b0, 0b1010, "smlsl", Neon_smlsl>;
3198 defm UMLSLvvv :  NeonI_3VDL_3Op_v1<0b1, 0b1010, "umlsl", Neon_umlsl>;
3199
3200 class NeonI_3VDL2_3Op_mlas<bit q, bit u, bits<2> size, bits<4> opcode,
3201                            string asmop, string ResS, string OpS,
3202                            SDPatternOperator subop, SDPatternOperator opnode,
3203                            RegisterOperand OpVPR,
3204                            ValueType ResTy, ValueType OpTy>
3205   : NeonI_3VDiff<q, u, size, opcode,
3206                (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
3207                asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3208                [(set (ResTy VPR128:$Rd),
3209                   (ResTy (subop
3210                     (ResTy VPR128:$src),
3211                     (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))))],
3212                NoItinerary> {
3213   let Constraints = "$src = $Rd";
3214 }
3215
3216 multiclass NeonI_3VDL2_3Op_mlas_v1<bit u, bits<4> opcode, string asmop,
3217                                    SDPatternOperator subop, string opnode> {
3218   def _8h16b : NeonI_3VDL2_3Op_mlas<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3219                                     subop, !cast<PatFrag>(opnode # "_16B"),
3220                                     VPR128, v8i16, v16i8>;
3221   def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3222                                    subop, !cast<PatFrag>(opnode # "_8H"),
3223                                    VPR128, v4i32, v8i16>;
3224   def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3225                                    subop, !cast<PatFrag>(opnode # "_4S"),
3226                                    VPR128, v2i64, v4i32>;
3227 }
3228
3229 defm SMLAL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1000, "smlal2",
3230                                           add, "NI_smull_hi">;
3231 defm UMLAL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1000, "umlal2",
3232                                           add, "NI_umull_hi">;
3233
3234 defm SMLSL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1010, "smlsl2",
3235                                           sub, "NI_smull_hi">;
3236 defm UMLSL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1010, "umlsl2",
3237                                           sub, "NI_umull_hi">;
3238
3239 multiclass NeonI_3VDL_qdmlal_3Op_v2<bit u, bits<4> opcode, string asmop,
3240                                     SDPatternOperator opnode> {
3241   def _4s4h : NeonI_3VDL2_3Op_mlas<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3242                                    opnode, int_arm_neon_vqdmull,
3243                                    VPR64, v4i32, v4i16>;
3244   def _2d2s : NeonI_3VDL2_3Op_mlas<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3245                                    opnode, int_arm_neon_vqdmull,
3246                                    VPR64, v2i64, v2i32>;
3247 }
3248
3249 defm SQDMLALvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1001, "sqdmlal",
3250                                            int_arm_neon_vqadds>;
3251 defm SQDMLSLvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1011, "sqdmlsl",
3252                                            int_arm_neon_vqsubs>;
3253
3254 multiclass NeonI_3VDL_v2<bit u, bits<4> opcode, string asmop,
3255                          SDPatternOperator opnode, bit Commutable = 0> {
3256   let isCommutable = Commutable in {
3257     def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3258                               opnode, VPR128, VPR64, v4i32, v4i16>;
3259     def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3260                               opnode, VPR128, VPR64, v2i64, v2i32>;
3261   }
3262 }
3263
3264 defm SQDMULLvvv : NeonI_3VDL_v2<0b0, 0b1101, "sqdmull",
3265                                 int_arm_neon_vqdmull, 1>;
3266
3267 multiclass NeonI_3VDL2_2Op_mull_v2<bit u, bits<4> opcode, string asmop,
3268                                    string opnode, bit Commutable = 0> {
3269   let isCommutable = Commutable in {
3270     def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3271                                      !cast<PatFrag>(opnode # "_8H"),
3272                                      v4i32, v8i16>;
3273     def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3274                                      !cast<PatFrag>(opnode # "_4S"),
3275                                      v2i64, v4i32>;
3276   }
3277 }
3278
3279 defm SQDMULL2vvv : NeonI_3VDL2_2Op_mull_v2<0b0, 0b1101, "sqdmull2",
3280                                            "NI_qdmull_hi", 1>;
3281
3282 multiclass NeonI_3VDL2_3Op_qdmlal_v2<bit u, bits<4> opcode, string asmop,
3283                                      SDPatternOperator opnode> {
3284   def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3285                                    opnode, NI_qdmull_hi_8H,
3286                                    VPR128, v4i32, v8i16>;
3287   def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3288                                    opnode, NI_qdmull_hi_4S,
3289                                    VPR128, v2i64, v4i32>;
3290 }
3291
3292 defm SQDMLAL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1001, "sqdmlal2",
3293                                              int_arm_neon_vqadds>;
3294 defm SQDMLSL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1011, "sqdmlsl2",
3295                                              int_arm_neon_vqsubs>;
3296
3297 multiclass NeonI_3VDL_v3<bit u, bits<4> opcode, string asmop,
3298                          SDPatternOperator opnode, bit Commutable = 0> {
3299   let isCommutable = Commutable in {
3300     def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3301                               opnode, VPR128, VPR64, v8i16, v8i8>;
3302
3303     def _1q1d : NeonI_3VDiff<0b0, u, 0b11, opcode,
3304                              (outs VPR128:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
3305                              asmop # "\t$Rd.1q, $Rn.1d, $Rm.1d",
3306                              [], NoItinerary>;
3307   }
3308 }
3309
3310 defm PMULLvvv : NeonI_3VDL_v3<0b0, 0b1110, "pmull", int_arm_neon_vmullp, 1>;
3311
3312 multiclass NeonI_3VDL2_2Op_mull_v3<bit u, bits<4> opcode, string asmop,
3313                                    string opnode, bit Commutable = 0> {
3314   let isCommutable = Commutable in {
3315     def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3316                                       !cast<PatFrag>(opnode # "_16B"),
3317                                       v8i16, v16i8>;
3318
3319     def _1q2d : NeonI_3VDiff<0b1, u, 0b11, opcode,
3320                              (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3321                              asmop # "\t$Rd.1q, $Rn.2d, $Rm.2d",
3322                              [], NoItinerary>;
3323   }
3324 }
3325
3326 defm PMULL2vvv : NeonI_3VDL2_2Op_mull_v3<0b0, 0b1110, "pmull2", "NI_pmull_hi",
3327                                          1>;
3328
3329 // End of implementation for instruction class (3V Diff)
3330
3331 // The followings are vector load/store multiple N-element structure
3332 // (class SIMD lselem).
3333
3334 // ld1:         load multiple 1-element structure to 1/2/3/4 registers.
3335 // ld2/ld3/ld4: load multiple N-element structure to N registers (N = 2, 3, 4).
3336 //              The structure consists of a sequence of sets of N values.
3337 //              The first element of the structure is placed in the first lane
3338 //              of the first first vector, the second element in the first lane
3339 //              of the second vector, and so on.
3340 // E.g. LD1_3V_2S will load 32-bit elements {A, B, C, D, E, F} sequentially into
3341 // the three 64-bit vectors list {BA, DC, FE}.
3342 // E.g. LD3_2S will load 32-bit elements {A, B, C, D, E, F} into the three
3343 // 64-bit vectors list {DA, EB, FC}.
3344 // Store instructions store multiple structure to N registers like load.
3345
3346
3347 class NeonI_LDVList<bit q, bits<4> opcode, bits<2> size,
3348                     RegisterOperand VecList, string asmop>
3349   : NeonI_LdStMult<q, 1, opcode, size,
3350                  (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3351                  asmop # "\t$Rt, [$Rn]",
3352                  [],
3353                  NoItinerary> {
3354   let mayLoad = 1;
3355   let neverHasSideEffects = 1;
3356 }
3357
3358 multiclass LDVList_BHSD<bits<4> opcode, string List, string asmop> {
3359   def _8B : NeonI_LDVList<0, opcode, 0b00,
3360                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3361
3362   def _4H : NeonI_LDVList<0, opcode, 0b01,
3363                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3364
3365   def _2S : NeonI_LDVList<0, opcode, 0b10,
3366                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3367
3368   def _16B : NeonI_LDVList<1, opcode, 0b00,
3369                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3370
3371   def _8H : NeonI_LDVList<1, opcode, 0b01,
3372                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3373
3374   def _4S : NeonI_LDVList<1, opcode, 0b10,
3375                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3376
3377   def _2D : NeonI_LDVList<1, opcode, 0b11,
3378                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3379 }
3380
3381 // Load multiple N-element structure to N consecutive registers (N = 1,2,3,4)
3382 defm LD1 : LDVList_BHSD<0b0111, "VOne", "ld1">;
3383 def LD1_1D : NeonI_LDVList<0, 0b0111, 0b11, VOne1D_operand, "ld1">;
3384
3385 defm LD2 : LDVList_BHSD<0b1000, "VPair", "ld2">;
3386
3387 defm LD3 : LDVList_BHSD<0b0100, "VTriple", "ld3">;
3388
3389 defm LD4 : LDVList_BHSD<0b0000, "VQuad", "ld4">;
3390
3391 // Load multiple 1-element structure to N consecutive registers (N = 2,3,4)
3392 defm LD1x2 : LDVList_BHSD<0b1010, "VPair", "ld1">;
3393 def LD1x2_1D : NeonI_LDVList<0, 0b1010, 0b11, VPair1D_operand, "ld1">;
3394
3395 defm LD1x3 : LDVList_BHSD<0b0110, "VTriple", "ld1">;
3396 def LD1x3_1D : NeonI_LDVList<0, 0b0110, 0b11, VTriple1D_operand, "ld1">;
3397
3398 defm LD1x4 : LDVList_BHSD<0b0010, "VQuad", "ld1">;
3399 def LD1x4_1D : NeonI_LDVList<0, 0b0010, 0b11, VQuad1D_operand, "ld1">;
3400
3401 class NeonI_STVList<bit q, bits<4> opcode, bits<2> size,
3402                     RegisterOperand VecList, string asmop>
3403   : NeonI_LdStMult<q, 0, opcode, size,
3404                  (outs), (ins GPR64xsp:$Rn, VecList:$Rt),
3405                  asmop # "\t$Rt, [$Rn]",
3406                  [],
3407                  NoItinerary> {
3408   let mayStore = 1;
3409   let neverHasSideEffects = 1;
3410 }
3411
3412 multiclass STVList_BHSD<bits<4> opcode, string List, string asmop> {
3413   def _8B : NeonI_STVList<0, opcode, 0b00,
3414                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3415
3416   def _4H : NeonI_STVList<0, opcode, 0b01,
3417                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3418
3419   def _2S : NeonI_STVList<0, opcode, 0b10,
3420                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3421
3422   def _16B : NeonI_STVList<1, opcode, 0b00,
3423                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3424
3425   def _8H : NeonI_STVList<1, opcode, 0b01,
3426                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3427
3428   def _4S : NeonI_STVList<1, opcode, 0b10,
3429                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3430
3431   def _2D : NeonI_STVList<1, opcode, 0b11,
3432                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3433 }
3434
3435 // Store multiple N-element structures from N registers (N = 1,2,3,4)
3436 defm ST1 : STVList_BHSD<0b0111, "VOne", "st1">;
3437 def ST1_1D : NeonI_STVList<0, 0b0111, 0b11, VOne1D_operand, "st1">;
3438
3439 defm ST2 : STVList_BHSD<0b1000, "VPair", "st2">;
3440
3441 defm ST3 : STVList_BHSD<0b0100, "VTriple", "st3">;
3442
3443 defm ST4 : STVList_BHSD<0b0000, "VQuad", "st4">;
3444
3445 // Store multiple 1-element structures from N consecutive registers (N = 2,3,4)
3446 defm ST1x2 : STVList_BHSD<0b1010, "VPair", "st1">;
3447 def ST1x2_1D : NeonI_STVList<0, 0b1010, 0b11, VPair1D_operand, "st1">;
3448
3449 defm ST1x3 : STVList_BHSD<0b0110, "VTriple", "st1">;
3450 def ST1x3_1D : NeonI_STVList<0, 0b0110, 0b11, VTriple1D_operand, "st1">;
3451
3452 defm ST1x4 : STVList_BHSD<0b0010, "VQuad", "st1">;
3453 def ST1x4_1D : NeonI_STVList<0, 0b0010, 0b11, VQuad1D_operand, "st1">;
3454
3455 // End of vector load/store multiple N-element structure(class SIMD lselem)
3456
3457 // The followings are post-index vector load/store multiple N-element
3458 // structure(class SIMD lselem-post)
3459 def exact1_asmoperand : AsmOperandClass {
3460   let Name = "Exact1";
3461   let PredicateMethod = "isExactImm<1>";
3462   let RenderMethod = "addImmOperands";
3463 }
3464 def uimm_exact1 : Operand<i32>, ImmLeaf<i32, [{return Imm == 1;}]> {
3465   let ParserMatchClass = exact1_asmoperand;
3466 }
3467
3468 def exact2_asmoperand : AsmOperandClass {
3469   let Name = "Exact2";
3470   let PredicateMethod = "isExactImm<2>";
3471   let RenderMethod = "addImmOperands";
3472 }
3473 def uimm_exact2 : Operand<i32>, ImmLeaf<i32, [{return Imm == 2;}]> {
3474   let ParserMatchClass = exact2_asmoperand;
3475 }
3476
3477 def exact3_asmoperand : AsmOperandClass {
3478   let Name = "Exact3";
3479   let PredicateMethod = "isExactImm<3>";
3480   let RenderMethod = "addImmOperands";
3481 }
3482 def uimm_exact3 : Operand<i32>, ImmLeaf<i32, [{return Imm == 3;}]> {
3483   let ParserMatchClass = exact3_asmoperand;
3484 }
3485
3486 def exact4_asmoperand : AsmOperandClass {
3487   let Name = "Exact4";
3488   let PredicateMethod = "isExactImm<4>";
3489   let RenderMethod = "addImmOperands";
3490 }
3491 def uimm_exact4 : Operand<i32>, ImmLeaf<i32, [{return Imm == 4;}]> {
3492   let ParserMatchClass = exact4_asmoperand;
3493 }
3494
3495 def exact6_asmoperand : AsmOperandClass {
3496   let Name = "Exact6";
3497   let PredicateMethod = "isExactImm<6>";
3498   let RenderMethod = "addImmOperands";
3499 }
3500 def uimm_exact6 : Operand<i32>, ImmLeaf<i32, [{return Imm == 6;}]> {
3501   let ParserMatchClass = exact6_asmoperand;
3502 }
3503
3504 def exact8_asmoperand : AsmOperandClass {
3505   let Name = "Exact8";
3506   let PredicateMethod = "isExactImm<8>";
3507   let RenderMethod = "addImmOperands";
3508 }
3509 def uimm_exact8 : Operand<i32>, ImmLeaf<i32, [{return Imm == 8;}]> {
3510   let ParserMatchClass = exact8_asmoperand;
3511 }
3512
3513 def exact12_asmoperand : AsmOperandClass {
3514   let Name = "Exact12";
3515   let PredicateMethod = "isExactImm<12>";
3516   let RenderMethod = "addImmOperands";
3517 }
3518 def uimm_exact12 : Operand<i32>, ImmLeaf<i32, [{return Imm == 12;}]> {
3519   let ParserMatchClass = exact12_asmoperand;
3520 }
3521
3522 def exact16_asmoperand : AsmOperandClass {
3523   let Name = "Exact16";
3524   let PredicateMethod = "isExactImm<16>";
3525   let RenderMethod = "addImmOperands";
3526 }
3527 def uimm_exact16 : Operand<i32>, ImmLeaf<i32, [{return Imm == 16;}]> {
3528   let ParserMatchClass = exact16_asmoperand;
3529 }
3530
3531 def exact24_asmoperand : AsmOperandClass {
3532   let Name = "Exact24";
3533   let PredicateMethod = "isExactImm<24>";
3534   let RenderMethod = "addImmOperands";
3535 }
3536 def uimm_exact24 : Operand<i32>, ImmLeaf<i32, [{return Imm == 24;}]> {
3537   let ParserMatchClass = exact24_asmoperand;
3538 }
3539
3540 def exact32_asmoperand : AsmOperandClass {
3541   let Name = "Exact32";
3542   let PredicateMethod = "isExactImm<32>";
3543   let RenderMethod = "addImmOperands";
3544 }
3545 def uimm_exact32 : Operand<i32>, ImmLeaf<i32, [{return Imm == 32;}]> {
3546   let ParserMatchClass = exact32_asmoperand;
3547 }
3548
3549 def exact48_asmoperand : AsmOperandClass {
3550   let Name = "Exact48";
3551   let PredicateMethod = "isExactImm<48>";
3552   let RenderMethod = "addImmOperands";
3553 }
3554 def uimm_exact48 : Operand<i32>, ImmLeaf<i32, [{return Imm == 48;}]> {
3555   let ParserMatchClass = exact48_asmoperand;
3556 }
3557
3558 def exact64_asmoperand : AsmOperandClass {
3559   let Name = "Exact64";
3560   let PredicateMethod = "isExactImm<64>";
3561   let RenderMethod = "addImmOperands";
3562 }
3563 def uimm_exact64 : Operand<i32>, ImmLeaf<i32, [{return Imm == 64;}]> {
3564   let ParserMatchClass = exact64_asmoperand;
3565 }
3566
3567 multiclass NeonI_LDWB_VList<bit q, bits<4> opcode, bits<2> size,
3568                            RegisterOperand VecList, Operand ImmTy,
3569                            string asmop> {
3570   let Constraints = "$Rn = $wb", mayLoad = 1, neverHasSideEffects = 1,
3571       DecoderMethod = "DecodeVLDSTPostInstruction" in {
3572     def _fixed : NeonI_LdStMult_Post<q, 1, opcode, size,
3573                      (outs VecList:$Rt, GPR64xsp:$wb),
3574                      (ins GPR64xsp:$Rn, ImmTy:$amt),
3575                      asmop # "\t$Rt, [$Rn], $amt",
3576                      [],
3577                      NoItinerary> {
3578       let Rm = 0b11111;
3579     }
3580
3581     def _register : NeonI_LdStMult_Post<q, 1, opcode, size,
3582                         (outs VecList:$Rt, GPR64xsp:$wb),
3583                         (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3584                         asmop # "\t$Rt, [$Rn], $Rm",
3585                         [],
3586                         NoItinerary>;
3587   }
3588 }
3589
3590 multiclass LDWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3591     Operand ImmTy2, string asmop> {
3592   defm _8B : NeonI_LDWB_VList<0, opcode, 0b00,
3593                               !cast<RegisterOperand>(List # "8B_operand"),
3594                               ImmTy, asmop>;
3595
3596   defm _4H : NeonI_LDWB_VList<0, opcode, 0b01,
3597                               !cast<RegisterOperand>(List # "4H_operand"),
3598                               ImmTy, asmop>;
3599
3600   defm _2S : NeonI_LDWB_VList<0, opcode, 0b10,
3601                               !cast<RegisterOperand>(List # "2S_operand"),
3602                               ImmTy, asmop>;
3603
3604   defm _16B : NeonI_LDWB_VList<1, opcode, 0b00,
3605                                !cast<RegisterOperand>(List # "16B_operand"),
3606                                ImmTy2, asmop>;
3607
3608   defm _8H : NeonI_LDWB_VList<1, opcode, 0b01,
3609                               !cast<RegisterOperand>(List # "8H_operand"),
3610                               ImmTy2, asmop>;
3611
3612   defm _4S : NeonI_LDWB_VList<1, opcode, 0b10,
3613                               !cast<RegisterOperand>(List # "4S_operand"),
3614                               ImmTy2, asmop>;
3615
3616   defm _2D : NeonI_LDWB_VList<1, opcode, 0b11,
3617                               !cast<RegisterOperand>(List # "2D_operand"),
3618                               ImmTy2, asmop>;
3619 }
3620
3621 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3622 defm LD1WB : LDWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "ld1">;
3623 defm LD1WB_1D : NeonI_LDWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3624                                  "ld1">;
3625
3626 defm LD2WB : LDWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "ld2">;
3627
3628 defm LD3WB : LDWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3629                              "ld3">;
3630
3631 defm LD4WB : LDWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "ld4">;
3632
3633 // Post-index load multiple 1-element structures from N consecutive registers
3634 // (N = 2,3,4)
3635 defm LD1x2WB : LDWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3636                                "ld1">;
3637 defm LD1x2WB_1D : NeonI_LDWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3638                                    uimm_exact16, "ld1">;
3639
3640 defm LD1x3WB : LDWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3641                                "ld1">;
3642 defm LD1x3WB_1D : NeonI_LDWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3643                                    uimm_exact24, "ld1">;
3644
3645 defm LD1x4WB : LDWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3646                                 "ld1">;
3647 defm LD1x4WB_1D : NeonI_LDWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3648                                    uimm_exact32, "ld1">;
3649
3650 multiclass NeonI_STWB_VList<bit q, bits<4> opcode, bits<2> size,
3651                             RegisterOperand VecList, Operand ImmTy,
3652                             string asmop> {
3653   let Constraints = "$Rn = $wb", mayStore = 1, neverHasSideEffects = 1,
3654       DecoderMethod = "DecodeVLDSTPostInstruction" in {
3655     def _fixed : NeonI_LdStMult_Post<q, 0, opcode, size,
3656                      (outs GPR64xsp:$wb),
3657                      (ins GPR64xsp:$Rn, ImmTy:$amt, VecList:$Rt),
3658                      asmop # "\t$Rt, [$Rn], $amt",
3659                      [],
3660                      NoItinerary> {
3661       let Rm = 0b11111;
3662     }
3663
3664     def _register : NeonI_LdStMult_Post<q, 0, opcode, size,
3665                       (outs GPR64xsp:$wb),
3666                       (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VecList:$Rt),
3667                       asmop # "\t$Rt, [$Rn], $Rm",
3668                       [],
3669                       NoItinerary>;
3670   }
3671 }
3672
3673 multiclass STWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3674                            Operand ImmTy2, string asmop> {
3675   defm _8B : NeonI_STWB_VList<0, opcode, 0b00,
3676                  !cast<RegisterOperand>(List # "8B_operand"), ImmTy, asmop>;
3677
3678   defm _4H : NeonI_STWB_VList<0, opcode, 0b01,
3679                               !cast<RegisterOperand>(List # "4H_operand"),
3680                               ImmTy, asmop>;
3681
3682   defm _2S : NeonI_STWB_VList<0, opcode, 0b10,
3683                               !cast<RegisterOperand>(List # "2S_operand"),
3684                               ImmTy, asmop>;
3685
3686   defm _16B : NeonI_STWB_VList<1, opcode, 0b00,
3687                                !cast<RegisterOperand>(List # "16B_operand"),
3688                                ImmTy2, asmop>;
3689
3690   defm _8H : NeonI_STWB_VList<1, opcode, 0b01,
3691                               !cast<RegisterOperand>(List # "8H_operand"),
3692                               ImmTy2, asmop>;
3693
3694   defm _4S : NeonI_STWB_VList<1, opcode, 0b10,
3695                               !cast<RegisterOperand>(List # "4S_operand"),
3696                               ImmTy2, asmop>;
3697
3698   defm _2D : NeonI_STWB_VList<1, opcode, 0b11,
3699                               !cast<RegisterOperand>(List # "2D_operand"),
3700                               ImmTy2, asmop>;
3701 }
3702
3703 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3704 defm ST1WB : STWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "st1">;
3705 defm ST1WB_1D : NeonI_STWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3706                                  "st1">;
3707
3708 defm ST2WB : STWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "st2">;
3709
3710 defm ST3WB : STWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3711                              "st3">;
3712
3713 defm ST4WB : STWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "st4">;
3714
3715 // Post-index load multiple 1-element structures from N consecutive registers
3716 // (N = 2,3,4)
3717 defm ST1x2WB : STWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3718                                "st1">;
3719 defm ST1x2WB_1D : NeonI_STWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3720                                    uimm_exact16, "st1">;
3721
3722 defm ST1x3WB : STWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3723                                "st1">;
3724 defm ST1x3WB_1D : NeonI_STWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3725                                    uimm_exact24, "st1">;
3726
3727 defm ST1x4WB : STWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3728                                "st1">;
3729 defm ST1x4WB_1D : NeonI_STWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3730                                    uimm_exact32, "st1">;
3731
3732 // End of post-index vector load/store multiple N-element structure
3733 // (class SIMD lselem-post)
3734
3735 // The followings are vector load/store single N-element structure
3736 // (class SIMD lsone).
3737 def neon_uimm0_bare : Operand<i64>,
3738                         ImmLeaf<i64, [{return Imm == 0;}]> {
3739   let ParserMatchClass = neon_uimm0_asmoperand;
3740   let PrintMethod = "printUImmBareOperand";
3741 }
3742
3743 def neon_uimm1_bare : Operand<i64>,
3744                         ImmLeaf<i64, [{return Imm < 2;}]> {
3745   let ParserMatchClass = neon_uimm1_asmoperand;
3746   let PrintMethod = "printUImmBareOperand";
3747 }
3748
3749 def neon_uimm2_bare : Operand<i64>,
3750                         ImmLeaf<i64, [{return Imm < 4;}]> {
3751   let ParserMatchClass = neon_uimm2_asmoperand;
3752   let PrintMethod = "printUImmBareOperand";
3753 }
3754
3755 def neon_uimm3_bare : Operand<i64>,
3756                         ImmLeaf<i64, [{return Imm < 8;}]> {
3757   let ParserMatchClass = uimm3_asmoperand;
3758   let PrintMethod = "printUImmBareOperand";
3759 }
3760
3761 def neon_uimm4_bare : Operand<i64>,
3762                         ImmLeaf<i64, [{return Imm < 16;}]> {
3763   let ParserMatchClass = uimm4_asmoperand;
3764   let PrintMethod = "printUImmBareOperand";
3765 }
3766
3767 class NeonI_LDN_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3768                     RegisterOperand VecList, string asmop>
3769     : NeonI_LdOne_Dup<q, r, opcode, size,
3770                       (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3771                       asmop # "\t$Rt, [$Rn]",
3772                       [],
3773                       NoItinerary> {
3774   let mayLoad = 1;
3775   let neverHasSideEffects = 1;
3776 }
3777
3778 multiclass LDN_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop> {
3779   def _8B : NeonI_LDN_Dup<0, r, opcode, 0b00,
3780                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3781
3782   def _4H : NeonI_LDN_Dup<0, r, opcode, 0b01,
3783                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3784
3785   def _2S : NeonI_LDN_Dup<0, r, opcode, 0b10,
3786                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3787
3788   def _1D : NeonI_LDN_Dup<0, r, opcode, 0b11,
3789                           !cast<RegisterOperand>(List # "1D_operand"), asmop>;
3790
3791   def _16B : NeonI_LDN_Dup<1, r, opcode, 0b00,
3792                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3793
3794   def _8H : NeonI_LDN_Dup<1, r, opcode, 0b01,
3795                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3796
3797   def _4S : NeonI_LDN_Dup<1, r, opcode, 0b10,
3798                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3799
3800   def _2D : NeonI_LDN_Dup<1, r, opcode, 0b11,
3801                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3802 }
3803
3804 // Load single 1-element structure to all lanes of 1 register
3805 defm LD1R : LDN_Dup_BHSD<0b0, 0b110, "VOne", "ld1r">;
3806
3807 // Load single N-element structure to all lanes of N consecutive
3808 // registers (N = 2,3,4)
3809 defm LD2R : LDN_Dup_BHSD<0b1, 0b110, "VPair", "ld2r">;
3810 defm LD3R : LDN_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r">;
3811 defm LD4R : LDN_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r">;
3812
3813
3814 class LD1R_pattern <ValueType VTy, ValueType DTy, PatFrag LoadOp,
3815                     Instruction INST>
3816     : Pat<(VTy (Neon_vdup (DTy (LoadOp GPR64xsp:$Rn)))),
3817           (VTy (INST GPR64xsp:$Rn))>;
3818
3819 // Match all LD1R instructions
3820 def : LD1R_pattern<v8i8, i32, extloadi8, LD1R_8B>;
3821
3822 def : LD1R_pattern<v16i8, i32, extloadi8, LD1R_16B>;
3823
3824 def : LD1R_pattern<v4i16, i32, extloadi16, LD1R_4H>;
3825
3826 def : LD1R_pattern<v8i16, i32, extloadi16, LD1R_8H>;
3827
3828 def : LD1R_pattern<v2i32, i32, load, LD1R_2S>;
3829 def : LD1R_pattern<v2f32, f32, load, LD1R_2S>;
3830
3831 def : LD1R_pattern<v4i32, i32, load, LD1R_4S>;
3832 def : LD1R_pattern<v4f32, f32, load, LD1R_4S>;
3833
3834 def : LD1R_pattern<v1i64, i64, load, LD1R_1D>;
3835 def : LD1R_pattern<v1f64, f64, load, LD1R_1D>;
3836
3837 def : LD1R_pattern<v2i64, i64, load, LD1R_2D>;
3838 def : LD1R_pattern<v2f64, f64, load, LD1R_2D>;
3839
3840
3841 multiclass VectorList_Bare_BHSD<string PREFIX, int Count,
3842                                 RegisterClass RegList> {
3843   defm B : VectorList_operands<PREFIX, "B", Count, RegList>;
3844   defm H : VectorList_operands<PREFIX, "H", Count, RegList>;
3845   defm S : VectorList_operands<PREFIX, "S", Count, RegList>;
3846   defm D : VectorList_operands<PREFIX, "D", Count, RegList>;
3847 }
3848
3849 // Special vector list operand of 128-bit vectors with bare layout.
3850 // i.e. only show ".b", ".h", ".s", ".d"
3851 defm VOne : VectorList_Bare_BHSD<"VOne", 1, FPR128>;
3852 defm VPair : VectorList_Bare_BHSD<"VPair", 2, QPair>;
3853 defm VTriple : VectorList_Bare_BHSD<"VTriple", 3, QTriple>;
3854 defm VQuad : VectorList_Bare_BHSD<"VQuad", 4, QQuad>;
3855
3856 class NeonI_LDN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3857                      Operand ImmOp, string asmop>
3858     : NeonI_LdStOne_Lane<1, r, op2_1, op0,
3859                          (outs VList:$Rt),
3860                          (ins GPR64xsp:$Rn, VList:$src, ImmOp:$lane),
3861                          asmop # "\t$Rt[$lane], [$Rn]",
3862                          [],
3863                          NoItinerary> {
3864   let mayLoad = 1;
3865   let neverHasSideEffects = 1;
3866   let hasExtraDefRegAllocReq = 1;
3867   let Constraints = "$src = $Rt";
3868 }
3869
3870 multiclass LDN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3871   def _B : NeonI_LDN_Lane<r, 0b00, op0,
3872                           !cast<RegisterOperand>(List # "B_operand"),
3873                           neon_uimm4_bare, asmop> {
3874     let Inst{12-10} = lane{2-0};
3875     let Inst{30} = lane{3};
3876   }
3877
3878   def _H : NeonI_LDN_Lane<r, 0b01, op0,
3879                           !cast<RegisterOperand>(List # "H_operand"),
3880                           neon_uimm3_bare, asmop> {
3881     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3882     let Inst{30} = lane{2};
3883   }
3884
3885   def _S : NeonI_LDN_Lane<r, 0b10, op0,
3886                           !cast<RegisterOperand>(List # "S_operand"),
3887                           neon_uimm2_bare, asmop> {
3888     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3889     let Inst{30} = lane{1};
3890   }
3891
3892   def _D : NeonI_LDN_Lane<r, 0b10, op0,
3893                           !cast<RegisterOperand>(List # "D_operand"),
3894                           neon_uimm1_bare, asmop> {
3895     let Inst{12-10} = 0b001;
3896     let Inst{30} = lane{0};
3897   }
3898 }
3899
3900 // Load single 1-element structure to one lane of 1 register.
3901 defm LD1LN : LDN_Lane_BHSD<0b0, 0b0, "VOne", "ld1">;
3902
3903 // Load single N-element structure to one lane of N consecutive registers
3904 // (N = 2,3,4)
3905 defm LD2LN : LDN_Lane_BHSD<0b1, 0b0, "VPair", "ld2">;
3906 defm LD3LN : LDN_Lane_BHSD<0b0, 0b1, "VTriple", "ld3">;
3907 defm LD4LN : LDN_Lane_BHSD<0b1, 0b1, "VQuad", "ld4">;
3908
3909 multiclass LD1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3910                           Operand ImmOp, Operand ImmOp2, PatFrag LoadOp,
3911                           Instruction INST> {
3912   def : Pat<(VTy (vector_insert (VTy VPR64:$src),
3913                      (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp:$lane))),
3914             (VTy (EXTRACT_SUBREG
3915                      (INST GPR64xsp:$Rn,
3916                            (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
3917                            ImmOp:$lane),
3918                      sub_64))>;
3919
3920   def : Pat<(VTy2 (vector_insert (VTy2 VPR128:$src),
3921                       (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp2:$lane))),
3922             (VTy2 (INST GPR64xsp:$Rn, VPR128:$src, ImmOp2:$lane))>;
3923 }
3924
3925 // Match all LD1LN instructions
3926 defm : LD1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3927                       extloadi8, LD1LN_B>;
3928
3929 defm : LD1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3930                       extloadi16, LD1LN_H>;
3931
3932 defm : LD1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3933                       load, LD1LN_S>;
3934 defm : LD1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3935                       load, LD1LN_S>;
3936
3937 defm : LD1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3938                       load, LD1LN_D>;
3939 defm : LD1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3940                       load, LD1LN_D>;
3941
3942 class NeonI_STN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3943                      Operand ImmOp, string asmop>
3944     : NeonI_LdStOne_Lane<0, r, op2_1, op0,
3945                          (outs), (ins GPR64xsp:$Rn, VList:$Rt, ImmOp:$lane),
3946                          asmop # "\t$Rt[$lane], [$Rn]",
3947                          [],
3948                          NoItinerary> {
3949   let mayStore = 1;
3950   let neverHasSideEffects = 1;
3951   let hasExtraDefRegAllocReq = 1;
3952 }
3953
3954 multiclass STN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3955   def _B : NeonI_STN_Lane<r, 0b00, op0,
3956                           !cast<RegisterOperand>(List # "B_operand"),
3957                           neon_uimm4_bare, asmop> {
3958     let Inst{12-10} = lane{2-0};
3959     let Inst{30} = lane{3};
3960   }
3961
3962   def _H : NeonI_STN_Lane<r, 0b01, op0,
3963                           !cast<RegisterOperand>(List # "H_operand"),
3964                           neon_uimm3_bare, asmop> {
3965     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3966     let Inst{30} = lane{2};
3967   }
3968
3969   def _S : NeonI_STN_Lane<r, 0b10, op0,
3970                           !cast<RegisterOperand>(List # "S_operand"),
3971                            neon_uimm2_bare, asmop> {
3972     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3973     let Inst{30} = lane{1};
3974   }
3975
3976   def _D : NeonI_STN_Lane<r, 0b10, op0,
3977                           !cast<RegisterOperand>(List # "D_operand"),
3978                           neon_uimm1_bare, asmop>{
3979     let Inst{12-10} = 0b001;
3980     let Inst{30} = lane{0};
3981   }
3982 }
3983
3984 // Store single 1-element structure from one lane of 1 register.
3985 defm ST1LN : STN_Lane_BHSD<0b0, 0b0, "VOne", "st1">;
3986
3987 // Store single N-element structure from one lane of N consecutive registers
3988 // (N = 2,3,4)
3989 defm ST2LN : STN_Lane_BHSD<0b1, 0b0, "VPair", "st2">;
3990 defm ST3LN : STN_Lane_BHSD<0b0, 0b1, "VTriple", "st3">;
3991 defm ST4LN : STN_Lane_BHSD<0b1, 0b1, "VQuad", "st4">;
3992
3993 multiclass ST1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3994                           Operand ImmOp, Operand ImmOp2, PatFrag StoreOp,
3995                           Instruction INST> {
3996   def : Pat<(StoreOp (DTy (vector_extract (VTy VPR64:$Rt), ImmOp:$lane)),
3997                      GPR64xsp:$Rn),
3998             (INST GPR64xsp:$Rn,
3999                   (SUBREG_TO_REG (i64 0), VPR64:$Rt, sub_64),
4000                   ImmOp:$lane)>;
4001
4002   def : Pat<(StoreOp (DTy (vector_extract (VTy2 VPR128:$Rt), ImmOp2:$lane)),
4003                      GPR64xsp:$Rn),
4004             (INST GPR64xsp:$Rn, VPR128:$Rt, ImmOp2:$lane)>;
4005 }
4006
4007 // Match all ST1LN instructions
4008 defm : ST1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
4009                       truncstorei8, ST1LN_B>;
4010
4011 defm : ST1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
4012                       truncstorei16, ST1LN_H>;
4013
4014 defm : ST1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
4015                       store, ST1LN_S>;
4016 defm : ST1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
4017                       store, ST1LN_S>;
4018
4019 defm : ST1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
4020                       store, ST1LN_D>;
4021 defm : ST1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
4022                       store, ST1LN_D>;
4023
4024 // End of vector load/store single N-element structure (class SIMD lsone).
4025
4026
4027 // The following are post-index load/store single N-element instructions
4028 // (class SIMD lsone-post)
4029
4030 multiclass NeonI_LDN_WB_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
4031                             RegisterOperand VecList, Operand ImmTy,
4032                             string asmop> {
4033   let mayLoad = 1, neverHasSideEffects = 1, Constraints = "$wb = $Rn",
4034   DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4035     def _fixed : NeonI_LdOne_Dup_Post<q, r, opcode, size,
4036                       (outs VecList:$Rt, GPR64xsp:$wb),
4037                       (ins GPR64xsp:$Rn, ImmTy:$amt),
4038                       asmop # "\t$Rt, [$Rn], $amt",
4039                       [],
4040                       NoItinerary> {
4041                         let Rm = 0b11111;
4042                       }
4043
4044     def _register : NeonI_LdOne_Dup_Post<q, r, opcode, size,
4045                       (outs VecList:$Rt, GPR64xsp:$wb),
4046                       (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
4047                       asmop # "\t$Rt, [$Rn], $Rm",
4048                       [],
4049                       NoItinerary>;
4050   }
4051 }
4052
4053 multiclass LDWB_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop,
4054                          Operand uimm_b, Operand uimm_h,
4055                          Operand uimm_s, Operand uimm_d> {
4056   defm _8B : NeonI_LDN_WB_Dup<0, r, opcode, 0b00,
4057                               !cast<RegisterOperand>(List # "8B_operand"),
4058                               uimm_b, asmop>;
4059
4060   defm _4H : NeonI_LDN_WB_Dup<0, r, opcode, 0b01,
4061                               !cast<RegisterOperand>(List # "4H_operand"),
4062                               uimm_h, asmop>;
4063
4064   defm _2S : NeonI_LDN_WB_Dup<0, r, opcode, 0b10,
4065                               !cast<RegisterOperand>(List # "2S_operand"),
4066                               uimm_s, asmop>;
4067
4068   defm _1D : NeonI_LDN_WB_Dup<0, r, opcode, 0b11,
4069                               !cast<RegisterOperand>(List # "1D_operand"),
4070                               uimm_d, asmop>;
4071
4072   defm _16B : NeonI_LDN_WB_Dup<1, r, opcode, 0b00,
4073                                !cast<RegisterOperand>(List # "16B_operand"),
4074                                uimm_b, asmop>;
4075
4076   defm _8H : NeonI_LDN_WB_Dup<1, r, opcode, 0b01,
4077                               !cast<RegisterOperand>(List # "8H_operand"),
4078                               uimm_h, asmop>;
4079
4080   defm _4S : NeonI_LDN_WB_Dup<1, r, opcode, 0b10,
4081                               !cast<RegisterOperand>(List # "4S_operand"),
4082                               uimm_s, asmop>;
4083
4084   defm _2D : NeonI_LDN_WB_Dup<1, r, opcode, 0b11,
4085                               !cast<RegisterOperand>(List # "2D_operand"),
4086                               uimm_d, asmop>;
4087 }
4088
4089 // Post-index load single 1-element structure to all lanes of 1 register
4090 defm LD1R_WB : LDWB_Dup_BHSD<0b0, 0b110, "VOne", "ld1r", uimm_exact1,
4091                              uimm_exact2, uimm_exact4, uimm_exact8>;
4092
4093 // Post-index load single N-element structure to all lanes of N consecutive
4094 // registers (N = 2,3,4)
4095 defm LD2R_WB : LDWB_Dup_BHSD<0b1, 0b110, "VPair", "ld2r", uimm_exact2,
4096                              uimm_exact4, uimm_exact8, uimm_exact16>;
4097 defm LD3R_WB : LDWB_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r", uimm_exact3,
4098                              uimm_exact6, uimm_exact12, uimm_exact24>;
4099 defm LD4R_WB : LDWB_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r", uimm_exact4,
4100                              uimm_exact8, uimm_exact16, uimm_exact32>;
4101
4102 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
4103     Constraints = "$Rn = $wb, $Rt = $src",
4104     DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4105   class LDN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4106                                 Operand ImmTy, Operand ImmOp, string asmop>
4107       : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
4108                                 (outs VList:$Rt, GPR64xsp:$wb),
4109                                 (ins GPR64xsp:$Rn, ImmTy:$amt,
4110                                     VList:$src, ImmOp:$lane),
4111                                 asmop # "\t$Rt[$lane], [$Rn], $amt",
4112                                 [],
4113                                 NoItinerary> {
4114     let Rm = 0b11111;
4115   }
4116
4117   class LDN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4118                                  Operand ImmTy, Operand ImmOp, string asmop>
4119       : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
4120                                 (outs VList:$Rt, GPR64xsp:$wb),
4121                                 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm,
4122                                     VList:$src, ImmOp:$lane),
4123                                 asmop # "\t$Rt[$lane], [$Rn], $Rm",
4124                                 [],
4125                                 NoItinerary>;
4126 }
4127
4128 multiclass LD_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4129                            Operand uimm_b, Operand uimm_h,
4130                            Operand uimm_s, Operand uimm_d> {
4131   def _B_fixed : LDN_WBFx_Lane<r, 0b00, op0,
4132                                !cast<RegisterOperand>(List # "B_operand"),
4133                                uimm_b, neon_uimm4_bare, asmop> {
4134     let Inst{12-10} = lane{2-0};
4135     let Inst{30} = lane{3};
4136   }
4137
4138   def _B_register : LDN_WBReg_Lane<r, 0b00, op0,
4139                                    !cast<RegisterOperand>(List # "B_operand"),
4140                                    uimm_b, neon_uimm4_bare, asmop> {
4141     let Inst{12-10} = lane{2-0};
4142     let Inst{30} = lane{3};
4143   }
4144
4145   def _H_fixed : LDN_WBFx_Lane<r, 0b01, op0,
4146                                !cast<RegisterOperand>(List # "H_operand"),
4147                                uimm_h, neon_uimm3_bare, asmop> {
4148     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4149     let Inst{30} = lane{2};
4150   }
4151
4152   def _H_register : LDN_WBReg_Lane<r, 0b01, op0,
4153                                    !cast<RegisterOperand>(List # "H_operand"),
4154                                    uimm_h, neon_uimm3_bare, asmop> {
4155     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4156     let Inst{30} = lane{2};
4157   }
4158
4159   def _S_fixed : LDN_WBFx_Lane<r, 0b10, op0,
4160                                !cast<RegisterOperand>(List # "S_operand"),
4161                                uimm_s, neon_uimm2_bare, asmop> {
4162     let Inst{12-10} = {lane{0}, 0b0, 0b0};
4163     let Inst{30} = lane{1};
4164   }
4165
4166   def _S_register : LDN_WBReg_Lane<r, 0b10, op0,
4167                                    !cast<RegisterOperand>(List # "S_operand"),
4168                                    uimm_s, neon_uimm2_bare, asmop> {
4169     let Inst{12-10} = {lane{0}, 0b0, 0b0};
4170     let Inst{30} = lane{1};
4171   }
4172
4173   def _D_fixed : LDN_WBFx_Lane<r, 0b10, op0,
4174                                !cast<RegisterOperand>(List # "D_operand"),
4175                                uimm_d, neon_uimm1_bare, asmop> {
4176     let Inst{12-10} = 0b001;
4177     let Inst{30} = lane{0};
4178   }
4179
4180   def _D_register : LDN_WBReg_Lane<r, 0b10, op0,
4181                                    !cast<RegisterOperand>(List # "D_operand"),
4182                                    uimm_d, neon_uimm1_bare, asmop> {
4183     let Inst{12-10} = 0b001;
4184     let Inst{30} = lane{0};
4185   }
4186 }
4187
4188 // Post-index load single 1-element structure to one lane of 1 register.
4189 defm LD1LN_WB : LD_Lane_WB_BHSD<0b0, 0b0, "VOne", "ld1", uimm_exact1,
4190                                 uimm_exact2, uimm_exact4, uimm_exact8>;
4191
4192 // Post-index load single N-element structure to one lane of N consecutive
4193 // registers
4194 // (N = 2,3,4)
4195 defm LD2LN_WB : LD_Lane_WB_BHSD<0b1, 0b0, "VPair", "ld2", uimm_exact2,
4196                                 uimm_exact4, uimm_exact8, uimm_exact16>;
4197 defm LD3LN_WB : LD_Lane_WB_BHSD<0b0, 0b1, "VTriple", "ld3", uimm_exact3,
4198                                 uimm_exact6, uimm_exact12, uimm_exact24>;
4199 defm LD4LN_WB : LD_Lane_WB_BHSD<0b1, 0b1, "VQuad", "ld4", uimm_exact4,
4200                                 uimm_exact8, uimm_exact16, uimm_exact32>;
4201
4202 let mayStore = 1, neverHasSideEffects = 1,
4203     hasExtraDefRegAllocReq = 1, Constraints = "$Rn = $wb",
4204     DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4205   class STN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4206                       Operand ImmTy, Operand ImmOp, string asmop>
4207       : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4208                                 (outs GPR64xsp:$wb),
4209                                 (ins GPR64xsp:$Rn, ImmTy:$amt,
4210                                     VList:$Rt, ImmOp:$lane),
4211                                 asmop # "\t$Rt[$lane], [$Rn], $amt",
4212                                 [],
4213                                 NoItinerary> {
4214     let Rm = 0b11111;
4215   }
4216
4217   class STN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4218                        Operand ImmTy, Operand ImmOp, string asmop>
4219       : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4220                                 (outs GPR64xsp:$wb),
4221                                 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VList:$Rt,
4222                                     ImmOp:$lane),
4223                                 asmop # "\t$Rt[$lane], [$Rn], $Rm",
4224                                 [],
4225                                 NoItinerary>;
4226 }
4227
4228 multiclass ST_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4229                            Operand uimm_b, Operand uimm_h,
4230                            Operand uimm_s, Operand uimm_d> {
4231   def _B_fixed : STN_WBFx_Lane<r, 0b00, op0,
4232                                !cast<RegisterOperand>(List # "B_operand"),
4233                                uimm_b, neon_uimm4_bare, asmop> {
4234     let Inst{12-10} = lane{2-0};
4235     let Inst{30} = lane{3};
4236   }
4237
4238   def _B_register : STN_WBReg_Lane<r, 0b00, op0,
4239                                    !cast<RegisterOperand>(List # "B_operand"),
4240                                    uimm_b, neon_uimm4_bare, asmop> {
4241     let Inst{12-10} = lane{2-0};
4242     let Inst{30} = lane{3};
4243   }
4244
4245   def _H_fixed : STN_WBFx_Lane<r, 0b01, op0,
4246                                !cast<RegisterOperand>(List # "H_operand"),
4247                                uimm_h, neon_uimm3_bare, asmop> {
4248     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4249     let Inst{30} = lane{2};
4250   }
4251
4252   def _H_register : STN_WBReg_Lane<r, 0b01, op0,
4253                                    !cast<RegisterOperand>(List # "H_operand"),
4254                                    uimm_h, neon_uimm3_bare, asmop> {
4255     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4256     let Inst{30} = lane{2};
4257   }
4258
4259   def _S_fixed : STN_WBFx_Lane<r, 0b10, op0,
4260                                !cast<RegisterOperand>(List # "S_operand"),
4261                                uimm_s, neon_uimm2_bare, asmop> {
4262     let Inst{12-10} = {lane{0}, 0b0, 0b0};
4263     let Inst{30} = lane{1};
4264   }
4265
4266   def _S_register : STN_WBReg_Lane<r, 0b10, op0,
4267                                    !cast<RegisterOperand>(List # "S_operand"),
4268                                    uimm_s, neon_uimm2_bare, asmop> {
4269     let Inst{12-10} = {lane{0}, 0b0, 0b0};
4270     let Inst{30} = lane{1};
4271   }
4272
4273   def _D_fixed : STN_WBFx_Lane<r, 0b10, op0,
4274                                !cast<RegisterOperand>(List # "D_operand"),
4275                                uimm_d, neon_uimm1_bare, asmop> {
4276     let Inst{12-10} = 0b001;
4277     let Inst{30} = lane{0};
4278   }
4279
4280   def _D_register : STN_WBReg_Lane<r, 0b10, op0,
4281                                    !cast<RegisterOperand>(List # "D_operand"),
4282                                    uimm_d, neon_uimm1_bare, asmop> {
4283     let Inst{12-10} = 0b001;
4284     let Inst{30} = lane{0};
4285   }
4286 }
4287
4288 // Post-index store single 1-element structure from one lane of 1 register.
4289 defm ST1LN_WB : ST_Lane_WB_BHSD<0b0, 0b0, "VOne", "st1", uimm_exact1,
4290                                 uimm_exact2, uimm_exact4, uimm_exact8>;
4291
4292 // Post-index store single N-element structure from one lane of N consecutive
4293 // registers (N = 2,3,4)
4294 defm ST2LN_WB : ST_Lane_WB_BHSD<0b1, 0b0, "VPair", "st2", uimm_exact2,
4295                                 uimm_exact4, uimm_exact8, uimm_exact16>;
4296 defm ST3LN_WB : ST_Lane_WB_BHSD<0b0, 0b1, "VTriple", "st3", uimm_exact3,
4297                                 uimm_exact6, uimm_exact12, uimm_exact24>;
4298 defm ST4LN_WB : ST_Lane_WB_BHSD<0b1, 0b1, "VQuad", "st4", uimm_exact4,
4299                                 uimm_exact8, uimm_exact16, uimm_exact32>;
4300
4301 // End of post-index load/store single N-element instructions
4302 // (class SIMD lsone-post)
4303
4304 // Neon Scalar instructions implementation
4305 // Scalar Three Same
4306
4307 class NeonI_Scalar3Same_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4308                              RegisterClass FPRC>
4309   : NeonI_Scalar3Same<u, size, opcode,
4310                       (outs FPRC:$Rd), (ins FPRC:$Rn, FPRC:$Rm),
4311                       !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4312                       [],
4313                       NoItinerary>;
4314
4315 class NeonI_Scalar3Same_D_size<bit u, bits<5> opcode, string asmop>
4316   : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4317
4318 multiclass NeonI_Scalar3Same_HS_sizes<bit u, bits<5> opcode, string asmop,
4319                                       bit Commutable = 0> {
4320   let isCommutable = Commutable in {
4321     def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4322     def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4323   }
4324 }
4325
4326 multiclass NeonI_Scalar3Same_SD_sizes<bit u, bit size_high, bits<5> opcode,
4327                                       string asmop, bit Commutable = 0> {
4328   let isCommutable = Commutable in {
4329     def sss : NeonI_Scalar3Same_size<u, {size_high, 0b0}, opcode, asmop, FPR32>;
4330     def ddd : NeonI_Scalar3Same_size<u, {size_high, 0b1}, opcode, asmop, FPR64>;
4331   }
4332 }
4333
4334 multiclass NeonI_Scalar3Same_BHSD_sizes<bit u, bits<5> opcode,
4335                                         string asmop, bit Commutable = 0> {
4336   let isCommutable = Commutable in {
4337     def bbb : NeonI_Scalar3Same_size<u, 0b00, opcode, asmop, FPR8>;
4338     def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4339     def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4340     def ddd : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4341   }
4342 }
4343
4344 multiclass Neon_Scalar3Same_D_size_patterns<SDPatternOperator opnode,
4345                                             Instruction INSTD> {
4346   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4347             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4348 }
4349
4350 multiclass Neon_Scalar3Same_BHSD_size_patterns<SDPatternOperator opnode,
4351                                                Instruction INSTB,
4352                                                Instruction INSTH,
4353                                                Instruction INSTS,
4354                                                Instruction INSTD>
4355   : Neon_Scalar3Same_D_size_patterns<opnode, INSTD> {
4356   def: Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (v1i8 FPR8:$Rm))),
4357            (INSTB FPR8:$Rn, FPR8:$Rm)>;
4358
4359   def: Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4360            (INSTH FPR16:$Rn, FPR16:$Rm)>;
4361
4362   def: Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4363            (INSTS FPR32:$Rn, FPR32:$Rm)>;
4364 }
4365
4366 class Neon_Scalar3Same_cmp_D_size_patterns<SDPatternOperator opnode,
4367                                            Instruction INSTD>
4368   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4369         (INSTD FPR64:$Rn, FPR64:$Rm)>;
4370
4371 multiclass Neon_Scalar3Same_HS_size_patterns<SDPatternOperator opnode,
4372                                              Instruction INSTH,
4373                                              Instruction INSTS> {
4374   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4375             (INSTH FPR16:$Rn, FPR16:$Rm)>;
4376   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4377             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4378 }
4379
4380 multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
4381                                              Instruction INSTS,
4382                                              Instruction INSTD> {
4383   def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
4384             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4385   def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
4386             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4387 }
4388
4389 multiclass Neon_Scalar3Same_cmp_SD_size_patterns<SDPatternOperator opnode,
4390                                                  Instruction INSTS,
4391                                                  Instruction INSTD> {
4392   def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
4393             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4394   def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
4395             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4396 }
4397
4398 // Scalar Three Different
4399
4400 class NeonI_Scalar3Diff_size<bit u, bits<2> size, bits<4> opcode, string asmop,
4401                              RegisterClass FPRCD, RegisterClass FPRCS>
4402   : NeonI_Scalar3Diff<u, size, opcode,
4403                       (outs FPRCD:$Rd), (ins FPRCS:$Rn, FPRCS:$Rm),
4404                       !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4405                       [],
4406                       NoItinerary>;
4407
4408 multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> {
4409   def shh : NeonI_Scalar3Diff_size<u, 0b01, opcode, asmop, FPR32, FPR16>;
4410   def dss : NeonI_Scalar3Diff_size<u, 0b10, opcode, asmop, FPR64, FPR32>;
4411 }
4412
4413 multiclass NeonI_Scalar3Diff_ml_HS_size<bit u, bits<4> opcode, string asmop> {
4414   let Constraints = "$Src = $Rd" in {
4415     def shh : NeonI_Scalar3Diff<u, 0b01, opcode,
4416                        (outs FPR32:$Rd), (ins FPR32:$Src, FPR16:$Rn, FPR16:$Rm),
4417                        !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4418                        [],
4419                        NoItinerary>;
4420     def dss : NeonI_Scalar3Diff<u, 0b10, opcode,
4421                        (outs FPR64:$Rd), (ins FPR64:$Src, FPR32:$Rn, FPR32:$Rm),
4422                        !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4423                        [],
4424                        NoItinerary>;
4425   }
4426 }
4427
4428 multiclass Neon_Scalar3Diff_HS_size_patterns<SDPatternOperator opnode,
4429                                              Instruction INSTH,
4430                                              Instruction INSTS> {
4431   def : Pat<(v1i32 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4432             (INSTH FPR16:$Rn, FPR16:$Rm)>;
4433   def : Pat<(v1i64 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4434             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4435 }
4436
4437 multiclass Neon_Scalar3Diff_ml_HS_size_patterns<SDPatternOperator opnode,
4438                                              Instruction INSTH,
4439                                              Instruction INSTS> {
4440   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4441             (INSTH FPR32:$Src, FPR16:$Rn, FPR16:$Rm)>;
4442   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4443             (INSTS FPR64:$Src, FPR32:$Rn, FPR32:$Rm)>;
4444 }
4445
4446 // Scalar Two Registers Miscellaneous
4447
4448 class NeonI_Scalar2SameMisc_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4449                              RegisterClass FPRCD, RegisterClass FPRCS>
4450   : NeonI_Scalar2SameMisc<u, size, opcode,
4451                           (outs FPRCD:$Rd), (ins FPRCS:$Rn),
4452                           !strconcat(asmop, "\t$Rd, $Rn"),
4453                           [],
4454                           NoItinerary>;
4455
4456 multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
4457                                          string asmop> {
4458   def ss : NeonI_Scalar2SameMisc_size<u, {size_high, 0b0}, opcode, asmop, FPR32,
4459                                       FPR32>;
4460   def dd : NeonI_Scalar2SameMisc_size<u, {size_high, 0b1}, opcode, asmop, FPR64,
4461                                       FPR64>;
4462 }
4463
4464 multiclass NeonI_Scalar2SameMisc_D_size<bit u, bits<5> opcode, string asmop> {
4465   def dd: NeonI_Scalar2SameMisc_size<u, 0b11, opcode, asmop, FPR64, FPR64>;
4466 }
4467
4468 multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>
4469   : NeonI_Scalar2SameMisc_D_size<u, opcode, asmop> {
4470   def bb : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR8>;
4471   def hh : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR16>;
4472   def ss : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR32>;
4473 }
4474
4475 multiclass NeonI_Scalar2SameMisc_narrow_HSD_size<bit u, bits<5> opcode,
4476                                                  string asmop> {
4477   def bh : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR16>;
4478   def hs : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR32>;
4479   def sd : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR64>;
4480 }
4481
4482 class NeonI_Scalar2SameMisc_accum_size<bit u, bits<2> size, bits<5> opcode,
4483                                        string asmop, RegisterClass FPRC>
4484   : NeonI_Scalar2SameMisc<u, size, opcode,
4485                           (outs FPRC:$Rd), (ins FPRC:$Src, FPRC:$Rn),
4486                           !strconcat(asmop, "\t$Rd, $Rn"),
4487                           [],
4488                           NoItinerary>;
4489
4490 multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
4491                                                  string asmop> {
4492
4493   let Constraints = "$Src = $Rd" in {
4494     def bb : NeonI_Scalar2SameMisc_accum_size<u, 0b00, opcode, asmop, FPR8>;
4495     def hh : NeonI_Scalar2SameMisc_accum_size<u, 0b01, opcode, asmop, FPR16>;
4496     def ss : NeonI_Scalar2SameMisc_accum_size<u, 0b10, opcode, asmop, FPR32>;
4497     def dd : NeonI_Scalar2SameMisc_accum_size<u, 0b11, opcode, asmop, FPR64>;
4498   }
4499 }
4500
4501 multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator Sopnode,
4502                                                      SDPatternOperator Dopnode,
4503                                                      Instruction INSTS,
4504                                                      Instruction INSTD> {
4505   def : Pat<(f32 (Sopnode (v1i32 FPR32:$Rn))),
4506             (INSTS FPR32:$Rn)>;
4507   def : Pat<(f64 (Dopnode (v1i64 FPR64:$Rn))),
4508             (INSTD FPR64:$Rn)>;
4509 }
4510
4511 multiclass Neon_Scalar2SameMisc_SD_size_patterns<SDPatternOperator opnode,
4512                                                  Instruction INSTS,
4513                                                  Instruction INSTD> {
4514   def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn))),
4515             (INSTS FPR32:$Rn)>;
4516   def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))),
4517             (INSTD FPR64:$Rn)>;
4518 }
4519
4520 class NeonI_Scalar2SameMisc_cmpz_D_size<bit u, bits<5> opcode, string asmop>
4521   : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4522                           (outs FPR64:$Rd), (ins FPR64:$Rn, neon_uimm0:$Imm),
4523                           !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4524                           [],
4525                           NoItinerary>;
4526
4527 multiclass NeonI_Scalar2SameMisc_cmpz_SD_size<bit u, bits<5> opcode,
4528                                               string asmop> {
4529   def ssi : NeonI_Scalar2SameMisc<u, 0b10, opcode,
4530                            (outs FPR32:$Rd), (ins FPR32:$Rn, fpz32:$FPImm),
4531                            !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4532                            [],
4533                            NoItinerary>;
4534   def ddi : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4535                            (outs FPR64:$Rd), (ins FPR64:$Rn, fpz64movi:$FPImm),
4536                            !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4537                            [],
4538                            NoItinerary>;
4539 }
4540
4541 class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode,
4542                                                 Instruction INSTD>
4543   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4544                        (v1i64 (bitconvert (v8i8 Neon_AllZero))))),
4545         (INSTD FPR64:$Rn, 0)>;
4546
4547 multiclass Neon_Scalar2SameMisc_cmpz_SD_size_patterns<SDPatternOperator opnode,
4548                                                       Instruction INSTS,
4549                                                       Instruction INSTD> {
4550   def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn),
4551                            (v1f32 (scalar_to_vector (f32 fpimm:$FPImm))))),
4552             (INSTS FPR32:$Rn, fpimm:$FPImm)>;
4553   def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn),
4554                            (v1f64 (bitconvert (v8i8 Neon_AllZero))))),
4555             (INSTD FPR64:$Rn, 0)>;
4556 }
4557
4558 multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode,
4559                                                 Instruction INSTD> {
4560   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))),
4561             (INSTD FPR64:$Rn)>;
4562 }
4563
4564 multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
4565                                                    Instruction INSTB,
4566                                                    Instruction INSTH,
4567                                                    Instruction INSTS,
4568                                                    Instruction INSTD>
4569   : Neon_Scalar2SameMisc_D_size_patterns<opnode, INSTD> {
4570   def : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn))),
4571             (INSTB FPR8:$Rn)>;
4572   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn))),
4573             (INSTH FPR16:$Rn)>;
4574   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn))),
4575             (INSTS FPR32:$Rn)>;
4576 }
4577
4578 multiclass Neon_Scalar2SameMisc_narrow_HSD_size_patterns<
4579                                                        SDPatternOperator opnode,
4580                                                        Instruction INSTH,
4581                                                        Instruction INSTS,
4582                                                        Instruction INSTD> {
4583   def : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn))),
4584             (INSTH FPR16:$Rn)>;
4585   def : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn))),
4586             (INSTS FPR32:$Rn)>;
4587   def : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn))),
4588             (INSTD FPR64:$Rn)>;
4589
4590 }
4591
4592 multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns<
4593                                                        SDPatternOperator opnode,
4594                                                        Instruction INSTB,
4595                                                        Instruction INSTH,
4596                                                        Instruction INSTS,
4597                                                        Instruction INSTD> {
4598   def : Pat<(v1i8 (opnode (v1i8 FPR8:$Src), (v1i8 FPR8:$Rn))),
4599             (INSTB FPR8:$Src, FPR8:$Rn)>;
4600   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Src), (v1i16 FPR16:$Rn))),
4601             (INSTH FPR16:$Src, FPR16:$Rn)>;
4602   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i32 FPR32:$Rn))),
4603             (INSTS FPR32:$Src, FPR32:$Rn)>;
4604   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn))),
4605             (INSTD FPR64:$Src, FPR64:$Rn)>;
4606 }
4607
4608 // Scalar Shift By Immediate
4609
4610 class NeonI_ScalarShiftImm_size<bit u, bits<5> opcode, string asmop,
4611                                 RegisterClass FPRC, Operand ImmTy>
4612   : NeonI_ScalarShiftImm<u, opcode,
4613                          (outs FPRC:$Rd), (ins FPRC:$Rn, ImmTy:$Imm),
4614                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4615                          [], NoItinerary>;
4616
4617 multiclass NeonI_ScalarShiftRightImm_D_size<bit u, bits<5> opcode,
4618                                             string asmop> {
4619   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4620     bits<6> Imm;
4621     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4622     let Inst{21-16} = Imm;
4623   }
4624 }
4625
4626 multiclass NeonI_ScalarShiftRightImm_BHSD_size<bit u, bits<5> opcode,
4627                                                string asmop>
4628   : NeonI_ScalarShiftRightImm_D_size<u, opcode, asmop> {
4629   def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shr_imm8> {
4630     bits<3> Imm;
4631     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4632     let Inst{18-16} = Imm;
4633   }
4634   def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shr_imm16> {
4635     bits<4> Imm;
4636     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4637     let Inst{19-16} = Imm;
4638   }
4639   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4640     bits<5> Imm;
4641     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4642     let Inst{20-16} = Imm;
4643   }
4644 }
4645
4646 multiclass NeonI_ScalarShiftLeftImm_D_size<bit u, bits<5> opcode,
4647                                             string asmop> {
4648   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shl_imm64> {
4649     bits<6> Imm;
4650     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4651     let Inst{21-16} = Imm;
4652   }
4653 }
4654
4655 multiclass NeonI_ScalarShiftLeftImm_BHSD_size<bit u, bits<5> opcode,
4656                                               string asmop>
4657   : NeonI_ScalarShiftLeftImm_D_size<u, opcode, asmop> {
4658   def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shl_imm8> {
4659     bits<3> Imm;
4660     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4661     let Inst{18-16} = Imm;
4662   }
4663   def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shl_imm16> {
4664     bits<4> Imm;
4665     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4666     let Inst{19-16} = Imm;
4667   }
4668   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shl_imm32> {
4669     bits<5> Imm;
4670     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4671     let Inst{20-16} = Imm;
4672   }
4673 }
4674
4675 class NeonI_ScalarShiftRightImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4676   : NeonI_ScalarShiftImm<u, opcode,
4677                          (outs FPR64:$Rd), (ins FPR64:$Src, FPR64:$Rn, shr_imm64:$Imm),
4678                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4679                          [], NoItinerary> {
4680     bits<6> Imm;
4681     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4682     let Inst{21-16} = Imm;
4683     let Constraints = "$Src = $Rd";
4684 }
4685
4686 class NeonI_ScalarShiftLeftImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4687   : NeonI_ScalarShiftImm<u, opcode,
4688                          (outs FPR64:$Rd), (ins FPR64:$Src, FPR64:$Rn, shl_imm64:$Imm),
4689                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4690                          [], NoItinerary> {
4691     bits<6> Imm;
4692     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4693     let Inst{21-16} = Imm;
4694     let Constraints = "$Src = $Rd";
4695 }
4696
4697 class NeonI_ScalarShiftImm_narrow_size<bit u, bits<5> opcode, string asmop,
4698                                        RegisterClass FPRCD, RegisterClass FPRCS,
4699                                        Operand ImmTy>
4700   : NeonI_ScalarShiftImm<u, opcode,
4701                          (outs FPRCD:$Rd), (ins FPRCS:$Rn, ImmTy:$Imm),
4702                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4703                          [], NoItinerary>;
4704
4705 multiclass NeonI_ScalarShiftImm_narrow_HSD_size<bit u, bits<5> opcode,
4706                                                 string asmop> {
4707   def bhi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR8, FPR16,
4708                                              shr_imm8> {
4709     bits<3> Imm;
4710     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4711     let Inst{18-16} = Imm;
4712   }
4713   def hsi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR16, FPR32,
4714                                              shr_imm16> {
4715     bits<4> Imm;
4716     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4717     let Inst{19-16} = Imm;
4718   }
4719   def sdi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR32, FPR64,
4720                                              shr_imm32> {
4721     bits<5> Imm;
4722     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4723     let Inst{20-16} = Imm;
4724   }
4725 }
4726
4727 multiclass NeonI_ScalarShiftImm_cvt_SD_size<bit u, bits<5> opcode, string asmop> {
4728   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4729     bits<5> Imm;
4730     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4731     let Inst{20-16} = Imm;
4732   }
4733   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4734     bits<6> Imm;
4735     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4736     let Inst{21-16} = Imm;
4737   }
4738 }
4739
4740 multiclass Neon_ScalarShiftImm_D_size_patterns<SDPatternOperator opnode,
4741                                                Instruction INSTD> {
4742   def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
4743                 (INSTD FPR64:$Rn, imm:$Imm)>;
4744 }
4745
4746 class Neon_ScalarShiftImm_arm_D_size_patterns<SDPatternOperator opnode,
4747                                               Instruction INSTD>
4748   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 (Neon_vdup (i32 imm:$Imm))))),
4749         (INSTD FPR64:$Rn, imm:$Imm)>;
4750
4751 multiclass Neon_ScalarShiftImm_BHSD_size_patterns<SDPatternOperator opnode,
4752                                                   Instruction INSTB,
4753                                                   Instruction INSTH,
4754                                                   Instruction INSTS,
4755                                                   Instruction INSTD>
4756   : Neon_ScalarShiftImm_D_size_patterns<opnode, INSTD> {
4757   def bbi : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (i32 imm:$Imm))),
4758                 (INSTB FPR8:$Rn, imm:$Imm)>;
4759   def hhi : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (i32 imm:$Imm))),
4760                 (INSTH FPR16:$Rn, imm:$Imm)>;
4761   def ssi : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (i32 imm:$Imm))),
4762                 (INSTS FPR32:$Rn, imm:$Imm)>;
4763 }
4764
4765 class Neon_ScalarShiftImm_accum_D_size_patterns<SDPatternOperator opnode,
4766                                                 Instruction INSTD>
4767   : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
4768         (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4769
4770 multiclass Neon_ScalarShiftImm_narrow_HSD_size_patterns<
4771                                                        SDPatternOperator opnode,
4772                                                        Instruction INSTH,
4773                                                        Instruction INSTS,
4774                                                        Instruction INSTD> {
4775   def bhi : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn), (i32 imm:$Imm))),
4776                 (INSTH FPR16:$Rn, imm:$Imm)>;
4777   def hsi : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn), (i32 imm:$Imm))),
4778                 (INSTS FPR32:$Rn, imm:$Imm)>;
4779   def sdi : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
4780                 (INSTD FPR64:$Rn, imm:$Imm)>;
4781 }
4782
4783 multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns<SDPatternOperator Sopnode,
4784                                                       SDPatternOperator Dopnode,
4785                                                       Instruction INSTS,
4786                                                       Instruction INSTD> {
4787   def ssi : Pat<(f32 (Sopnode (v1i32 FPR32:$Rn), (i32 imm:$Imm))),
4788                 (INSTS FPR32:$Rn, imm:$Imm)>;
4789   def ddi : Pat<(f64 (Dopnode (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
4790                 (INSTD FPR64:$Rn, imm:$Imm)>;
4791 }
4792
4793 multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns<SDPatternOperator Sopnode,
4794                                                       SDPatternOperator Dopnode,
4795                                                       Instruction INSTS,
4796                                                       Instruction INSTD> {
4797   def ssi : Pat<(v1i32 (Sopnode (v1f32 FPR32:$Rn), (i32 imm:$Imm))),
4798                 (INSTS FPR32:$Rn, imm:$Imm)>;
4799   def ddi : Pat<(v1i64 (Dopnode (v1f64 FPR64:$Rn), (i32 imm:$Imm))),
4800                 (INSTD FPR64:$Rn, imm:$Imm)>;
4801 }
4802
4803 // Scalar Signed Shift Right (Immediate)
4804 defm SSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00000, "sshr">;
4805 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vshrds_n, SSHRddi>;
4806 // Pattern to match llvm.arm.* intrinsic.
4807 def : Neon_ScalarShiftImm_arm_D_size_patterns<sra, SSHRddi>;
4808
4809 // Scalar Unsigned Shift Right (Immediate)
4810 defm USHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00000, "ushr">;
4811 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vshrdu_n, USHRddi>;
4812 // Pattern to match llvm.arm.* intrinsic.
4813 def : Neon_ScalarShiftImm_arm_D_size_patterns<srl, USHRddi>;
4814
4815 // Scalar Signed Rounding Shift Right (Immediate)
4816 defm SRSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00100, "srshr">;
4817 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vsrshr, SRSHRddi>;
4818
4819 // Scalar Unigned Rounding Shift Right (Immediate)
4820 defm URSHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00100, "urshr">;
4821 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vurshr, URSHRddi>;
4822
4823 // Scalar Signed Shift Right and Accumulate (Immediate)
4824 def SSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00010, "ssra">;
4825 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vsrads_n, SSRA>;
4826
4827 // Scalar Unsigned Shift Right and Accumulate (Immediate)
4828 def USRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00010, "usra">;
4829 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vsradu_n, USRA>;
4830
4831 // Scalar Signed Rounding Shift Right and Accumulate (Immediate)
4832 def SRSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00110, "srsra">;
4833 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vrsrads_n, SRSRA>;
4834
4835 // Scalar Unsigned Rounding Shift Right and Accumulate (Immediate)
4836 def URSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00110, "ursra">;
4837 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vrsradu_n, URSRA>;
4838
4839 // Scalar Shift Left (Immediate)
4840 defm SHL : NeonI_ScalarShiftLeftImm_D_size<0b0, 0b01010, "shl">;
4841 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vshld_n, SHLddi>;
4842 // Pattern to match llvm.arm.* intrinsic.
4843 def : Neon_ScalarShiftImm_arm_D_size_patterns<shl, SHLddi>;
4844
4845 // Signed Saturating Shift Left (Immediate)
4846 defm SQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b0, 0b01110, "sqshl">;
4847 defm : Neon_ScalarShiftImm_BHSD_size_patterns<int_aarch64_neon_vqshls_n,
4848                                               SQSHLbbi, SQSHLhhi,
4849                                               SQSHLssi, SQSHLddi>;
4850 // Pattern to match llvm.arm.* intrinsic.
4851 defm : Neon_ScalarShiftImm_D_size_patterns<Neon_sqrshlImm, SQSHLddi>;
4852
4853 // Unsigned Saturating Shift Left (Immediate)
4854 defm UQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01110, "uqshl">;
4855 defm : Neon_ScalarShiftImm_BHSD_size_patterns<int_aarch64_neon_vqshlu_n,
4856                                               UQSHLbbi, UQSHLhhi,
4857                                               UQSHLssi, UQSHLddi>;
4858 // Pattern to match llvm.arm.* intrinsic.
4859 defm : Neon_ScalarShiftImm_D_size_patterns<Neon_uqrshlImm, UQSHLddi>;
4860
4861 // Signed Saturating Shift Left Unsigned (Immediate)
4862 defm SQSHLU : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01100, "sqshlu">;
4863 defm : Neon_ScalarShiftImm_BHSD_size_patterns<int_aarch64_neon_vsqshlu,
4864                                               SQSHLUbbi, SQSHLUhhi,
4865                                               SQSHLUssi, SQSHLUddi>;
4866
4867 // Shift Right And Insert (Immediate)
4868 def SRI : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b01000, "sri">;
4869 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vsri, SRI>;
4870
4871 // Shift Left And Insert (Immediate)
4872 def SLI : NeonI_ScalarShiftLeftImm_accum_D_size<0b1, 0b01010, "sli">;
4873 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vsli, SLI>;
4874
4875 // Signed Saturating Shift Right Narrow (Immediate)
4876 defm SQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10010, "sqshrn">;
4877 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrn,
4878                                                     SQSHRNbhi, SQSHRNhsi,
4879                                                     SQSHRNsdi>;
4880
4881 // Unsigned Saturating Shift Right Narrow (Immediate)
4882 defm UQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10010, "uqshrn">;
4883 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqshrn,
4884                                                     UQSHRNbhi, UQSHRNhsi,
4885                                                     UQSHRNsdi>;
4886
4887 // Signed Saturating Rounded Shift Right Narrow (Immediate)
4888 defm SQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10011, "sqrshrn">;
4889 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrn,
4890                                                     SQRSHRNbhi, SQRSHRNhsi,
4891                                                     SQRSHRNsdi>;
4892
4893 // Unsigned Saturating Rounded Shift Right Narrow (Immediate)
4894 defm UQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10011, "uqrshrn">;
4895 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqrshrn,
4896                                                     UQRSHRNbhi, UQRSHRNhsi,
4897                                                     UQRSHRNsdi>;
4898
4899 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
4900 defm SQSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10000, "sqshrun">;
4901 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrun,
4902                                                     SQSHRUNbhi, SQSHRUNhsi,
4903                                                     SQSHRUNsdi>;
4904
4905 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
4906 defm SQRSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10001, "sqrshrun">;
4907 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrun,
4908                                                     SQRSHRUNbhi, SQRSHRUNhsi,
4909                                                     SQRSHRUNsdi>;
4910
4911 // Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
4912 defm SCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11100, "scvtf">;
4913 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtf32_n_s32,
4914                                                   int_aarch64_neon_vcvtf64_n_s64,
4915                                                   SCVTF_Nssi, SCVTF_Nddi>;
4916
4917 // Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
4918 defm UCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11100, "ucvtf">;
4919 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtf32_n_u32,
4920                                                   int_aarch64_neon_vcvtf64_n_u64,
4921                                                   UCVTF_Nssi, UCVTF_Nddi>;
4922
4923 // Scalar Floating-point Convert To Signed Fixed-point (Immediate)
4924 defm FCVTZS_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11111, "fcvtzs">;
4925 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvts_n_s32_f32,
4926                                                   int_aarch64_neon_vcvtd_n_s64_f64,
4927                                                   FCVTZS_Nssi, FCVTZS_Nddi>;
4928
4929 // Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
4930 defm FCVTZU_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11111, "fcvtzu">;
4931 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvts_n_u32_f32,
4932                                                   int_aarch64_neon_vcvtd_n_u64_f64,
4933                                                   FCVTZU_Nssi, FCVTZU_Nddi>;
4934
4935 // Scalar Integer Add
4936 let isCommutable = 1 in {
4937 def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
4938 }
4939
4940 // Scalar Integer Sub
4941 def SUBddd : NeonI_Scalar3Same_D_size<0b1, 0b10000, "sub">;
4942
4943 // Pattern for Scalar Integer Add and Sub with D register only
4944 defm : Neon_Scalar3Same_D_size_patterns<add, ADDddd>;
4945 defm : Neon_Scalar3Same_D_size_patterns<sub, SUBddd>;
4946
4947 // Patterns to match llvm.aarch64.* intrinsic for Scalar Add, Sub
4948 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vaddds, ADDddd>;
4949 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vadddu, ADDddd>;
4950 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubds, SUBddd>;
4951 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubdu, SUBddd>;
4952
4953 // Scalar Integer Saturating Add (Signed, Unsigned)
4954 defm SQADD : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00001, "sqadd", 1>;
4955 defm UQADD : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00001, "uqadd", 1>;
4956
4957 // Scalar Integer Saturating Sub (Signed, Unsigned)
4958 defm SQSUB : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00101, "sqsub", 0>;
4959 defm UQSUB : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00101, "uqsub", 0>;
4960
4961
4962 // Patterns to match llvm.aarch64.* intrinsic for
4963 // Scalar Integer Saturating Add, Sub  (Signed, Unsigned)
4964 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqadds, SQADDbbb,
4965                                            SQADDhhh, SQADDsss, SQADDddd>;
4966 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqaddu, UQADDbbb,
4967                                            UQADDhhh, UQADDsss, UQADDddd>;
4968 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubs, SQSUBbbb,
4969                                            SQSUBhhh, SQSUBsss, SQSUBddd>;
4970 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubu, UQSUBbbb,
4971                                            UQSUBhhh, UQSUBsss, UQSUBddd>;
4972
4973 // Scalar Integer Saturating Doubling Multiply Half High
4974 defm SQDMULH : NeonI_Scalar3Same_HS_sizes<0b0, 0b10110, "sqdmulh", 1>;
4975
4976 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4977 defm SQRDMULH : NeonI_Scalar3Same_HS_sizes<0b1, 0b10110, "sqrdmulh", 1>;
4978
4979 // Patterns to match llvm.arm.* intrinsic for
4980 // Scalar Integer Saturating Doubling Multiply Half High and
4981 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4982 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqdmulh, SQDMULHhhh,
4983                                                                SQDMULHsss>;
4984 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqrdmulh, SQRDMULHhhh,
4985                                                                 SQRDMULHsss>;
4986
4987 // Scalar Floating-point Multiply Extended
4988 defm FMULX : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11011, "fmulx", 1>;
4989
4990 // Scalar Floating-point Reciprocal Step
4991 defm FRECPS : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11111, "frecps", 0>;
4992
4993 // Scalar Floating-point Reciprocal Square Root Step
4994 defm FRSQRTS : NeonI_Scalar3Same_SD_sizes<0b0, 0b1, 0b11111, "frsqrts", 0>;
4995
4996 // Patterns to match llvm.arm.* intrinsic for
4997 // Scalar Floating-point Reciprocal Step and
4998 // Scalar Floating-point Reciprocal Square Root Step
4999 defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrecps, FRECPSsss,
5000                                                               FRECPSddd>;
5001 defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrsqrts, FRSQRTSsss,
5002                                                                FRSQRTSddd>;
5003
5004 // Patterns to match llvm.aarch64.* intrinsic for
5005 // Scalar Floating-point Multiply Extended,
5006 multiclass Neon_Scalar3Same_MULX_SD_size_patterns<SDPatternOperator opnode,
5007                                                   Instruction INSTS,
5008                                                   Instruction INSTD> {
5009   def : Pat<(f32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
5010             (INSTS FPR32:$Rn, FPR32:$Rm)>;
5011   def : Pat<(f64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
5012             (INSTD FPR64:$Rn, FPR64:$Rm)>;
5013 }
5014
5015 defm : Neon_Scalar3Same_MULX_SD_size_patterns<int_aarch64_neon_vmulx,
5016                                               FMULXsss,FMULXddd>;
5017
5018 // Scalar Integer Shift Left (Signed, Unsigned)
5019 def SSHLddd : NeonI_Scalar3Same_D_size<0b0, 0b01000, "sshl">;
5020 def USHLddd : NeonI_Scalar3Same_D_size<0b1, 0b01000, "ushl">;
5021
5022 // Patterns to match llvm.arm.* intrinsic for
5023 // Scalar Integer Shift Left (Signed, Unsigned)
5024 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshifts, SSHLddd>;
5025 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshiftu, USHLddd>;
5026
5027 // Patterns to match llvm.aarch64.* intrinsic for
5028 // Scalar Integer Shift Left (Signed, Unsigned)
5029 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshlds, SSHLddd>;
5030 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshldu, USHLddd>;
5031
5032 // Scalar Integer Saturating Shift Left (Signed, Unsigned)
5033 defm SQSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01001, "sqshl", 0>;
5034 defm UQSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01001, "uqshl", 0>;
5035
5036 // Patterns to match llvm.aarch64.* intrinsic for
5037 // Scalar  Integer Saturating Shift Letf (Signed, Unsigned)
5038 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshls, SQSHLbbb,
5039                                            SQSHLhhh, SQSHLsss, SQSHLddd>;
5040 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshlu, UQSHLbbb,
5041                                            UQSHLhhh, UQSHLsss, UQSHLddd>;
5042
5043 // Patterns to match llvm.arm.* intrinsic for
5044 // Scalar  Integer Saturating Shift Letf (Signed, Unsigned)
5045 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshifts, SQSHLddd>;
5046 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshiftu, UQSHLddd>;
5047
5048 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
5049 def SRSHLddd: NeonI_Scalar3Same_D_size<0b0, 0b01010, "srshl">;
5050 def URSHLddd: NeonI_Scalar3Same_D_size<0b1, 0b01010, "urshl">;
5051
5052 // Patterns to match llvm.aarch64.* intrinsic for
5053 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
5054 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshlds, SRSHLddd>;
5055 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshldu, URSHLddd>;
5056
5057 // Patterns to match llvm.arm.* intrinsic for
5058 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
5059 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshifts, SRSHLddd>;
5060 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshiftu, URSHLddd>;
5061
5062 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
5063 defm SQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01011, "sqrshl", 0>;
5064 defm UQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01011, "uqrshl", 0>;
5065
5066 // Patterns to match llvm.aarch64.* intrinsic for
5067 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
5068 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshls, SQRSHLbbb,
5069                                            SQRSHLhhh, SQRSHLsss, SQRSHLddd>;
5070 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb,
5071                                            UQRSHLhhh, UQRSHLsss, UQRSHLddd>;
5072
5073 // Patterns to match llvm.arm.* intrinsic for
5074 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
5075 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
5076 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
5077
5078 // Signed Saturating Doubling Multiply-Add Long
5079 defm SQDMLAL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1001, "sqdmlal">;
5080 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlal,
5081                                             SQDMLALshh, SQDMLALdss>;
5082
5083 // Signed Saturating Doubling Multiply-Subtract Long
5084 defm SQDMLSL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1011, "sqdmlsl">;
5085 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlsl,
5086                                             SQDMLSLshh, SQDMLSLdss>;
5087
5088 // Signed Saturating Doubling Multiply Long
5089 defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">;
5090 defm : Neon_Scalar3Diff_HS_size_patterns<int_arm_neon_vqdmull,
5091                                          SQDMULLshh, SQDMULLdss>;
5092
5093 // Scalar Signed Integer Convert To Floating-point
5094 defm SCVTF  : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">;
5095 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_s32,
5096                                                  int_aarch64_neon_vcvtf64_s64,
5097                                                  SCVTFss, SCVTFdd>;
5098
5099 // Scalar Unsigned Integer Convert To Floating-point
5100 defm UCVTF  : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11101, "ucvtf">;
5101 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_u32,
5102                                                  int_aarch64_neon_vcvtf64_u64,
5103                                                  UCVTFss, UCVTFdd>;
5104
5105 // Scalar Floating-point Reciprocal Estimate
5106 defm FRECPE : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11101, "frecpe">;
5107 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrecpe,
5108                                              FRECPEss, FRECPEdd>;
5109
5110 // Scalar Floating-point Reciprocal Exponent
5111 defm FRECPX : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11111, "frecpx">;
5112 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpx,
5113                                              FRECPXss, FRECPXdd>;
5114
5115 // Scalar Floating-point Reciprocal Square Root Estimate
5116 defm FRSQRTE: NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11101, "frsqrte">;
5117 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrsqrte,
5118                                              FRSQRTEss, FRSQRTEdd>;
5119
5120 // Scalar Integer Compare
5121
5122 // Scalar Compare Bitwise Equal
5123 def CMEQddd: NeonI_Scalar3Same_D_size<0b1, 0b10001, "cmeq">;
5124 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vceq, CMEQddd>;
5125
5126 class Neon_Scalar3Same_cmp_D_size_v1_patterns<SDPatternOperator opnode,
5127                                               Instruction INSTD,
5128                                               CondCode CC>
5129   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm), CC)),
5130         (INSTD FPR64:$Rn, FPR64:$Rm)>;
5131
5132 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMEQddd, SETEQ>;
5133
5134 // Scalar Compare Signed Greather Than Or Equal
5135 def CMGEddd: NeonI_Scalar3Same_D_size<0b0, 0b00111, "cmge">;
5136 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcge, CMGEddd>;
5137
5138 // Scalar Compare Unsigned Higher Or Same
5139 def CMHSddd: NeonI_Scalar3Same_D_size<0b1, 0b00111, "cmhs">;
5140 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchs, CMHSddd>;
5141
5142 // Scalar Compare Unsigned Higher
5143 def CMHIddd: NeonI_Scalar3Same_D_size<0b1, 0b00110, "cmhi">;
5144 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchi, CMHIddd>;
5145
5146 // Scalar Compare Signed Greater Than
5147 def CMGTddd: NeonI_Scalar3Same_D_size<0b0, 0b00110, "cmgt">;
5148 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcgt, CMGTddd>;
5149
5150 // Scalar Compare Bitwise Test Bits
5151 def CMTSTddd: NeonI_Scalar3Same_D_size<0b0, 0b10001, "cmtst">;
5152 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vtstd, CMTSTddd>;
5153 def : Neon_Scalar3Same_cmp_D_size_patterns<Neon_tst, CMTSTddd>;
5154
5155 // Scalar Compare Bitwise Equal To Zero
5156 def CMEQddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01001, "cmeq">;
5157 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vceq,
5158                                                 CMEQddi>;
5159
5160 // Scalar Compare Signed Greather Than Or Equal To Zero
5161 def CMGEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01000, "cmge">;
5162 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcge,
5163                                                 CMGEddi>;
5164
5165 // Scalar Compare Signed Greater Than Zero
5166 def CMGTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01000, "cmgt">;
5167 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcgt,
5168                                                 CMGTddi>;
5169
5170 // Scalar Compare Signed Less Than Or Equal To Zero
5171 def CMLEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01001, "cmle">;
5172 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vclez,
5173                                                 CMLEddi>;
5174
5175 // Scalar Compare Less Than Zero
5176 def CMLTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01010, "cmlt">;
5177 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcltz,
5178                                                 CMLTddi>;
5179
5180 // Scalar Floating-point Compare
5181
5182 // Scalar Floating-point Compare Mask Equal
5183 defm FCMEQ: NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11100, "fcmeq">;
5184 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vceq,
5185                                              FCMEQsss, FCMEQddd>;
5186
5187 // Scalar Floating-point Compare Mask Equal To Zero
5188 defm FCMEQZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01101, "fcmeq">;
5189 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vceq,
5190                                                   FCMEQZssi, FCMEQZddi>;
5191
5192 // Scalar Floating-point Compare Mask Greater Than Or Equal
5193 defm FCMGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11100, "fcmge">;
5194 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcge,
5195                                              FCMGEsss, FCMGEddd>;
5196
5197 // Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
5198 defm FCMGEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01100, "fcmge">;
5199 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcge,
5200                                                   FCMGEZssi, FCMGEZddi>;
5201
5202 // Scalar Floating-point Compare Mask Greather Than
5203 defm FCMGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11100, "fcmgt">;
5204 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcgt,
5205                                              FCMGTsss, FCMGTddd>;
5206
5207 // Scalar Floating-point Compare Mask Greather Than Zero
5208 defm FCMGTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01100, "fcmgt">;
5209 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcgt,
5210                                                   FCMGTZssi, FCMGTZddi>;
5211
5212 // Scalar Floating-point Compare Mask Less Than Or Equal To Zero
5213 defm FCMLEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01101, "fcmle">;
5214 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vclez,
5215                                                   FCMLEZssi, FCMLEZddi>;
5216
5217 // Scalar Floating-point Compare Mask Less Than Zero
5218 defm FCMLTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01110, "fcmlt">;
5219 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcltz,
5220                                                   FCMLTZssi, FCMLTZddi>;
5221
5222 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
5223 defm FACGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11101, "facge">;
5224 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcage,
5225                                              FACGEsss, FACGEddd>;
5226
5227 // Scalar Floating-point Absolute Compare Mask Greater Than
5228 defm FACGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11101, "facgt">;
5229 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcagt,
5230                                              FACGTsss, FACGTddd>;
5231
5232 // Scalar Absolute Value
5233 defm ABS : NeonI_Scalar2SameMisc_D_size<0b0, 0b01011, "abs">;
5234 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vabs, ABSdd>;
5235
5236 // Scalar Signed Saturating Absolute Value
5237 defm SQABS : NeonI_Scalar2SameMisc_BHSD_size<0b0, 0b00111, "sqabs">;
5238 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqabs,
5239                                                SQABSbb, SQABShh, SQABSss, SQABSdd>;
5240
5241 // Scalar Negate
5242 defm NEG : NeonI_Scalar2SameMisc_D_size<0b1, 0b01011, "neg">;
5243 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vneg, NEGdd>;
5244
5245 // Scalar Signed Saturating Negate
5246 defm SQNEG : NeonI_Scalar2SameMisc_BHSD_size<0b1, 0b00111, "sqneg">;
5247 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqneg,
5248                                                SQNEGbb, SQNEGhh, SQNEGss, SQNEGdd>;
5249
5250 // Scalar Signed Saturating Accumulated of Unsigned Value
5251 defm SUQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b0, 0b00011, "suqadd">;
5252 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vuqadd,
5253                                                      SUQADDbb, SUQADDhh,
5254                                                      SUQADDss, SUQADDdd>;
5255
5256 // Scalar Unsigned Saturating Accumulated of Signed Value
5257 defm USQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b1, 0b00011, "usqadd">;
5258 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vsqadd,
5259                                                      USQADDbb, USQADDhh,
5260                                                      USQADDss, USQADDdd>;
5261
5262 // Scalar Signed Saturating Extract Unsigned Narrow
5263 defm SQXTUN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10010, "sqxtun">;
5264 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnsu,
5265                                                      SQXTUNbh, SQXTUNhs,
5266                                                      SQXTUNsd>;
5267
5268 // Scalar Signed Saturating Extract Narrow
5269 defm SQXTN  : NeonI_Scalar2SameMisc_narrow_HSD_size<0b0, 0b10100, "sqxtn">;
5270 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovns,
5271                                                      SQXTNbh, SQXTNhs,
5272                                                      SQXTNsd>;
5273
5274 // Scalar Unsigned Saturating Extract Narrow
5275 defm UQXTN  : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10100, "uqxtn">;
5276 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnu,
5277                                                      UQXTNbh, UQXTNhs,
5278                                                      UQXTNsd>;
5279
5280 // Scalar Reduce Pairwise
5281
5282 multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode,
5283                                      string asmop, bit Commutable = 0> {
5284   let isCommutable = Commutable in {
5285     def _D_2D : NeonI_ScalarPair<u, {size, 0b1}, opcode,
5286                                 (outs FPR64:$Rd), (ins VPR128:$Rn),
5287                                 !strconcat(asmop, "\t$Rd, $Rn.2d"),
5288                                 [],
5289                                 NoItinerary>;
5290   }
5291 }
5292
5293 multiclass NeonI_ScalarPair_SD_sizes<bit u, bit size, bits<5> opcode,
5294                                      string asmop, bit Commutable = 0>
5295   : NeonI_ScalarPair_D_sizes<u, size, opcode, asmop, Commutable> {
5296   let isCommutable = Commutable in {
5297     def _S_2S : NeonI_ScalarPair<u, {size, 0b0}, opcode,
5298                                 (outs FPR32:$Rd), (ins VPR64:$Rn),
5299                                 !strconcat(asmop, "\t$Rd, $Rn.2s"),
5300                                 [],
5301                                 NoItinerary>;
5302   }
5303 }
5304
5305 // Scalar Reduce Addition Pairwise (Integer) with
5306 // Pattern to match llvm.arm.* intrinsic
5307 defm ADDPvv : NeonI_ScalarPair_D_sizes<0b0, 0b1, 0b11011, "addp", 0>;
5308
5309 // Pattern to match llvm.aarch64.* intrinsic for
5310 // Scalar Reduce Addition Pairwise (Integer)
5311 def : Pat<(v1i64 (int_aarch64_neon_vpadd (v2i64 VPR128:$Rn))),
5312           (ADDPvv_D_2D VPR128:$Rn)>;
5313
5314 // Scalar Reduce Addition Pairwise (Floating Point)
5315 defm FADDPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01101, "faddp", 0>;
5316
5317 // Scalar Reduce Maximum Pairwise (Floating Point)
5318 defm FMAXPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01111, "fmaxp", 0>;
5319
5320 // Scalar Reduce Minimum Pairwise (Floating Point)
5321 defm FMINPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01111, "fminp", 0>;
5322
5323 // Scalar Reduce maxNum Pairwise (Floating Point)
5324 defm FMAXNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01100, "fmaxnmp", 0>;
5325
5326 // Scalar Reduce minNum Pairwise (Floating Point)
5327 defm FMINNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01100, "fminnmp", 0>;
5328
5329 multiclass Neon_ScalarPair_SD_size_patterns<SDPatternOperator opnodeS,
5330                                             SDPatternOperator opnodeD,
5331                                             Instruction INSTS,
5332                                             Instruction INSTD> {
5333   def : Pat<(v1f32 (opnodeS (v2f32 VPR64:$Rn))),
5334             (INSTS VPR64:$Rn)>;
5335   def : Pat<(v1f64 (opnodeD (v2f64 VPR128:$Rn))),
5336             (INSTD VPR128:$Rn)>;
5337 }
5338
5339 // Patterns to match llvm.aarch64.* intrinsic for
5340 // Scalar Reduce Add, Max, Min, MaxiNum, MinNum Pairwise (Floating Point)
5341 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfadd,
5342   int_aarch64_neon_vpfaddq, FADDPvv_S_2S, FADDPvv_D_2D>;
5343
5344 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmax,
5345   int_aarch64_neon_vpmaxq, FMAXPvv_S_2S, FMAXPvv_D_2D>;
5346
5347 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmin,
5348   int_aarch64_neon_vpminq, FMINPvv_S_2S, FMINPvv_D_2D>;
5349
5350 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfmaxnm,
5351   int_aarch64_neon_vpfmaxnmq, FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
5352
5353 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfminnm,
5354   int_aarch64_neon_vpfminnmq, FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
5355
5356
5357 // Scalar by element Arithmetic
5358
5359 class NeonI_ScalarXIndexedElemArith<string asmop, bits<4> opcode,
5360                                     string rmlane, bit u, bit szhi, bit szlo,
5361                                     RegisterClass ResFPR, RegisterClass OpFPR,
5362                                     RegisterOperand OpVPR, Operand OpImm>
5363   : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5364                              (outs ResFPR:$Rd),
5365                              (ins OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5366                              asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5367                              [],
5368                              NoItinerary> {
5369   bits<3> Imm;
5370   bits<5> MRm;
5371 }
5372
5373 class NeonI_ScalarXIndexedElemArith_Constraint_Impl<string asmop, bits<4> opcode,
5374                                                     string rmlane,
5375                                                     bit u, bit szhi, bit szlo,
5376                                                     RegisterClass ResFPR,
5377                                                     RegisterClass OpFPR,
5378                                                     RegisterOperand OpVPR,
5379                                                     Operand OpImm>
5380   : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5381                              (outs ResFPR:$Rd),
5382                              (ins ResFPR:$src, OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5383                              asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5384                              [],
5385                              NoItinerary> {
5386   let Constraints = "$src = $Rd";
5387   bits<3> Imm;
5388   bits<5> MRm;
5389 }
5390
5391 // Scalar Floating Point  multiply (scalar, by element)
5392 def FMULssv_4S : NeonI_ScalarXIndexedElemArith<"fmul",
5393   0b1001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5394   let Inst{11} = Imm{1}; // h
5395   let Inst{21} = Imm{0}; // l
5396   let Inst{20-16} = MRm;
5397 }
5398 def FMULddv_2D : NeonI_ScalarXIndexedElemArith<"fmul",
5399   0b1001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5400   let Inst{11} = Imm{0}; // h
5401   let Inst{21} = 0b0;    // l
5402   let Inst{20-16} = MRm;
5403 }
5404
5405 // Scalar Floating Point  multiply extended (scalar, by element)
5406 def FMULXssv_4S : NeonI_ScalarXIndexedElemArith<"fmulx",
5407   0b1001, ".s", 0b1, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5408   let Inst{11} = Imm{1}; // h
5409   let Inst{21} = Imm{0}; // l
5410   let Inst{20-16} = MRm;
5411 }
5412 def FMULXddv_2D : NeonI_ScalarXIndexedElemArith<"fmulx",
5413   0b1001, ".d", 0b1, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5414   let Inst{11} = Imm{0}; // h
5415   let Inst{21} = 0b0;    // l
5416   let Inst{20-16} = MRm;
5417 }
5418
5419 multiclass Neon_ScalarXIndexedElem_MUL_MULX_Patterns<
5420   SDPatternOperator opnode,
5421   Instruction INST,
5422   ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5423   ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5424
5425   def  : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5426                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)))),
5427              (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5428
5429   def  : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5430                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)))),
5431              (ResTy (INST (ResTy FPRC:$Rn),
5432                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5433                OpNImm:$Imm))>;
5434
5435   // swapped operands
5436   def  : Pat<(ResTy (opnode
5437                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5438                (ResTy FPRC:$Rn))),
5439              (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5440
5441   def  : Pat<(ResTy (opnode
5442                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5443                (ResTy FPRC:$Rn))),
5444              (ResTy (INST (ResTy FPRC:$Rn),
5445                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5446                OpNImm:$Imm))>;
5447 }
5448
5449 // Patterns for Scalar Floating Point  multiply (scalar, by element)
5450 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULssv_4S,
5451   f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5452 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULddv_2D,
5453   f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5454
5455 // Patterns for Scalar Floating Point  multiply extended (scalar, by element)
5456 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5457   FMULXssv_4S, f32, FPR32, v4f32, neon_uimm2_bare,
5458   v2f32, v4f32, neon_uimm1_bare>;
5459 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5460   FMULXddv_2D, f64, FPR64, v2f64, neon_uimm1_bare,
5461   v1f64, v2f64, neon_uimm0_bare>;
5462
5463
5464 // Scalar Floating Point fused multiply-add (scalar, by element)
5465 def FMLAssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5466   0b0001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5467   let Inst{11} = Imm{1}; // h
5468   let Inst{21} = Imm{0}; // l
5469   let Inst{20-16} = MRm;
5470 }
5471 def FMLAddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5472   0b0001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5473   let Inst{11} = Imm{0}; // h
5474   let Inst{21} = 0b0;    // l
5475   let Inst{20-16} = MRm;
5476 }
5477
5478 // Scalar Floating Point fused multiply-subtract (scalar, by element)
5479 def FMLSssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5480   0b0101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5481   let Inst{11} = Imm{1}; // h
5482   let Inst{21} = Imm{0}; // l
5483   let Inst{20-16} = MRm;
5484 }
5485 def FMLSddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5486   0b0101, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5487   let Inst{11} = Imm{0}; // h
5488   let Inst{21} = 0b0;    // l
5489   let Inst{20-16} = MRm;
5490 }
5491 // We are allowed to match the fma instruction regardless of compile options.
5492 multiclass Neon_ScalarXIndexedElem_FMA_Patterns<
5493   Instruction FMLAI, Instruction FMLSI,
5494   ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5495   ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5496   // fmla
5497   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5498                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5499                (ResTy FPRC:$Ra))),
5500              (ResTy (FMLAI (ResTy FPRC:$Ra),
5501                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5502
5503   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5504                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5505                (ResTy FPRC:$Ra))),
5506              (ResTy (FMLAI (ResTy FPRC:$Ra),
5507                (ResTy FPRC:$Rn),
5508                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5509                OpNImm:$Imm))>;
5510
5511   // swapped fmla operands
5512   def  : Pat<(ResTy (fma
5513                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5514                (ResTy FPRC:$Rn),
5515                (ResTy FPRC:$Ra))),
5516              (ResTy (FMLAI (ResTy FPRC:$Ra),
5517                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5518
5519   def  : Pat<(ResTy (fma
5520                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5521                (ResTy FPRC:$Rn),
5522                (ResTy FPRC:$Ra))),
5523              (ResTy (FMLAI (ResTy FPRC:$Ra),
5524                (ResTy FPRC:$Rn),
5525                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5526                OpNImm:$Imm))>;
5527
5528   // fmls
5529   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5530                (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5531                (ResTy FPRC:$Ra))),
5532              (ResTy (FMLSI (ResTy FPRC:$Ra),
5533                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5534
5535   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5536                (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5537                (ResTy FPRC:$Ra))),
5538              (ResTy (FMLSI (ResTy FPRC:$Ra),
5539                (ResTy FPRC:$Rn),
5540                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5541                OpNImm:$Imm))>;
5542
5543   // swapped fmls operands
5544   def  : Pat<(ResTy (fma
5545                (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5546                (ResTy FPRC:$Rn),
5547                (ResTy FPRC:$Ra))),
5548              (ResTy (FMLSI (ResTy FPRC:$Ra),
5549                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5550
5551   def  : Pat<(ResTy (fma
5552                (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5553                (ResTy FPRC:$Rn),
5554                (ResTy FPRC:$Ra))),
5555              (ResTy (FMLSI (ResTy FPRC:$Ra),
5556                (ResTy FPRC:$Rn),
5557                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5558                OpNImm:$Imm))>;
5559 }
5560
5561 // Scalar Floating Point fused multiply-add and
5562 // multiply-subtract (scalar, by element)
5563 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAssv_4S, FMLSssv_4S,
5564   f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5565 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5566   f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5567 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5568   f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5569
5570 // Scalar Signed saturating doubling multiply long (scalar, by element)
5571 def SQDMULLshv_4H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5572   0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5573   let Inst{11} = 0b0; // h
5574   let Inst{21} = Imm{1}; // l
5575   let Inst{20} = Imm{0}; // m
5576   let Inst{19-16} = MRm{3-0};
5577 }
5578 def SQDMULLshv_8H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5579   0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5580   let Inst{11} = Imm{2}; // h
5581   let Inst{21} = Imm{1}; // l
5582   let Inst{20} = Imm{0}; // m
5583   let Inst{19-16} = MRm{3-0};
5584 }
5585 def SQDMULLdsv_2S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5586   0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5587   let Inst{11} = 0b0;    // h
5588   let Inst{21} = Imm{0}; // l
5589   let Inst{20-16} = MRm;
5590 }
5591 def SQDMULLdsv_4S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5592   0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5593   let Inst{11} = Imm{1};    // h
5594   let Inst{21} = Imm{0};    // l
5595   let Inst{20-16} = MRm;
5596 }
5597
5598 multiclass Neon_ScalarXIndexedElem_MUL_Patterns<
5599   SDPatternOperator opnode,
5600   Instruction INST,
5601   ValueType ResTy, RegisterClass FPRC,
5602   ValueType OpVTy, ValueType OpTy,
5603   ValueType VecOpTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5604
5605   def  : Pat<(ResTy (opnode (OpVTy FPRC:$Rn),
5606                (OpVTy (scalar_to_vector
5607                  (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))))),
5608              (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5609
5610   //swapped operands
5611   def  : Pat<(ResTy (opnode
5612                (OpVTy (scalar_to_vector
5613                  (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))),
5614                  (OpVTy FPRC:$Rn))),
5615              (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5616 }
5617
5618
5619 // Patterns for Scalar Signed saturating doubling
5620 // multiply long (scalar, by element)
5621 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5622   SQDMULLshv_4H, v1i32, FPR16, v1i16, i16, v4i16,
5623   i32, VPR64Lo, neon_uimm2_bare>;
5624 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5625   SQDMULLshv_8H, v1i32, FPR16, v1i16, i16, v8i16,
5626   i32, VPR128Lo, neon_uimm3_bare>;
5627 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5628   SQDMULLdsv_2S, v1i64, FPR32, v1i32, i32, v2i32,
5629   i32, VPR64Lo, neon_uimm1_bare>;
5630 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5631   SQDMULLdsv_4S, v1i64, FPR32, v1i32, i32, v4i32,
5632   i32, VPR128Lo, neon_uimm2_bare>;
5633
5634 // Scalar Signed saturating doubling multiply-add long (scalar, by element)
5635 def SQDMLALshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5636   0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5637   let Inst{11} = 0b0; // h
5638   let Inst{21} = Imm{1}; // l
5639   let Inst{20} = Imm{0}; // m
5640   let Inst{19-16} = MRm{3-0};
5641 }
5642 def SQDMLALshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5643   0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5644   let Inst{11} = Imm{2}; // h
5645   let Inst{21} = Imm{1}; // l
5646   let Inst{20} = Imm{0}; // m
5647   let Inst{19-16} = MRm{3-0};
5648 }
5649 def SQDMLALdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5650   0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5651   let Inst{11} = 0b0;    // h
5652   let Inst{21} = Imm{0}; // l
5653   let Inst{20-16} = MRm;
5654 }
5655 def SQDMLALdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5656   0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5657   let Inst{11} = Imm{1};    // h
5658   let Inst{21} = Imm{0};    // l
5659   let Inst{20-16} = MRm;
5660 }
5661
5662 // Scalar Signed saturating doubling
5663 // multiply-subtract long (scalar, by element)
5664 def SQDMLSLshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5665   0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5666   let Inst{11} = 0b0; // h
5667   let Inst{21} = Imm{1}; // l
5668   let Inst{20} = Imm{0}; // m
5669   let Inst{19-16} = MRm{3-0};
5670 }
5671 def SQDMLSLshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5672   0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5673   let Inst{11} = Imm{2}; // h
5674   let Inst{21} = Imm{1}; // l
5675   let Inst{20} = Imm{0}; // m
5676   let Inst{19-16} = MRm{3-0};
5677 }
5678 def SQDMLSLdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5679   0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5680   let Inst{11} = 0b0;    // h
5681   let Inst{21} = Imm{0}; // l
5682   let Inst{20-16} = MRm;
5683 }
5684 def SQDMLSLdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5685   0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5686   let Inst{11} = Imm{1};    // h
5687   let Inst{21} = Imm{0};    // l
5688   let Inst{20-16} = MRm;
5689 }
5690
5691 multiclass Neon_ScalarXIndexedElem_MLAL_Patterns<
5692   SDPatternOperator opnode,
5693   SDPatternOperator coreopnode,
5694   Instruction INST,
5695   ValueType ResTy, RegisterClass ResFPRC, RegisterClass FPRC,
5696   ValueType OpTy,
5697   ValueType OpVTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5698
5699   def  : Pat<(ResTy (opnode
5700                (ResTy ResFPRC:$Ra),
5701                (ResTy (coreopnode (OpTy FPRC:$Rn),
5702                  (OpTy (scalar_to_vector
5703                    (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))))))),
5704              (ResTy (INST (ResTy ResFPRC:$Ra),
5705                (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5706
5707   // swapped operands
5708   def  : Pat<(ResTy (opnode
5709                (ResTy ResFPRC:$Ra),
5710                (ResTy (coreopnode
5711                  (OpTy (scalar_to_vector
5712                    (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))),
5713                  (OpTy FPRC:$Rn))))),
5714              (ResTy (INST (ResTy ResFPRC:$Ra),
5715                (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5716 }
5717
5718 // Patterns for Scalar Signed saturating
5719 // doubling multiply-add long (scalar, by element)
5720 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5721   int_arm_neon_vqdmull, SQDMLALshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5722   i32, VPR64Lo, neon_uimm2_bare>;
5723 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5724   int_arm_neon_vqdmull, SQDMLALshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5725   i32, VPR128Lo, neon_uimm3_bare>;
5726 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5727   int_arm_neon_vqdmull, SQDMLALdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5728   i32, VPR64Lo, neon_uimm1_bare>;
5729 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5730   int_arm_neon_vqdmull, SQDMLALdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5731   i32, VPR128Lo, neon_uimm2_bare>;
5732
5733 // Patterns for Scalar Signed saturating
5734 // doubling multiply-sub long (scalar, by element)
5735 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5736   int_arm_neon_vqdmull, SQDMLSLshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5737   i32, VPR64Lo, neon_uimm2_bare>;
5738 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5739   int_arm_neon_vqdmull, SQDMLSLshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5740   i32, VPR128Lo, neon_uimm3_bare>;
5741 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5742   int_arm_neon_vqdmull, SQDMLSLdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5743   i32, VPR64Lo, neon_uimm1_bare>;
5744 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5745   int_arm_neon_vqdmull, SQDMLSLdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5746   i32, VPR128Lo, neon_uimm2_bare>;
5747
5748
5749 // Scalar Signed saturating doubling multiply returning
5750 // high half (scalar, by element)
5751 def SQDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5752   0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5753   let Inst{11} = 0b0; // h
5754   let Inst{21} = Imm{1}; // l
5755   let Inst{20} = Imm{0}; // m
5756   let Inst{19-16} = MRm{3-0};
5757 }
5758 def SQDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5759   0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5760   let Inst{11} = Imm{2}; // h
5761   let Inst{21} = Imm{1}; // l
5762   let Inst{20} = Imm{0}; // m
5763   let Inst{19-16} = MRm{3-0};
5764 }
5765 def SQDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5766   0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5767   let Inst{11} = 0b0;    // h
5768   let Inst{21} = Imm{0}; // l
5769   let Inst{20-16} = MRm;
5770 }
5771 def SQDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5772   0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5773   let Inst{11} = Imm{1};    // h
5774   let Inst{21} = Imm{0};    // l
5775   let Inst{20-16} = MRm;
5776 }
5777
5778 // Patterns for Scalar Signed saturating doubling multiply returning
5779 // high half (scalar, by element)
5780 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5781   SQDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16,
5782   i32, VPR64Lo, neon_uimm2_bare>;
5783 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5784   SQDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16,
5785   i32, VPR128Lo, neon_uimm3_bare>;
5786 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5787   SQDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32,
5788   i32, VPR64Lo, neon_uimm1_bare>;
5789 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5790   SQDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32,
5791   i32, VPR128Lo, neon_uimm2_bare>;
5792
5793 // Scalar Signed saturating rounding doubling multiply
5794 // returning high half (scalar, by element)
5795 def SQRDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5796   0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5797   let Inst{11} = 0b0; // h
5798   let Inst{21} = Imm{1}; // l
5799   let Inst{20} = Imm{0}; // m
5800   let Inst{19-16} = MRm{3-0};
5801 }
5802 def SQRDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5803   0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5804   let Inst{11} = Imm{2}; // h
5805   let Inst{21} = Imm{1}; // l
5806   let Inst{20} = Imm{0}; // m
5807   let Inst{19-16} = MRm{3-0};
5808 }
5809 def SQRDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5810   0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5811   let Inst{11} = 0b0;    // h
5812   let Inst{21} = Imm{0}; // l
5813   let Inst{20-16} = MRm;
5814 }
5815 def SQRDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5816   0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5817   let Inst{11} = Imm{1};    // h
5818   let Inst{21} = Imm{0};    // l
5819   let Inst{20-16} = MRm;
5820 }
5821
5822 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5823   SQRDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16, i32,
5824   VPR64Lo, neon_uimm2_bare>;
5825 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5826   SQRDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16, i32,
5827   VPR128Lo, neon_uimm3_bare>;
5828 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5829   SQRDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32, i32,
5830   VPR64Lo, neon_uimm1_bare>;
5831 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5832   SQRDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32, i32,
5833   VPR128Lo, neon_uimm2_bare>;
5834
5835 // Scalar Copy - DUP element to scalar
5836 class NeonI_Scalar_DUP<string asmop, string asmlane,
5837                        RegisterClass ResRC, RegisterOperand VPRC,
5838                        Operand OpImm>
5839   : NeonI_ScalarCopy<(outs ResRC:$Rd), (ins VPRC:$Rn, OpImm:$Imm),
5840                      asmop # "\t$Rd, $Rn." # asmlane # "[$Imm]",
5841                      [],
5842                      NoItinerary> {
5843   bits<4> Imm;
5844 }
5845
5846 def DUPbv_B : NeonI_Scalar_DUP<"dup", "b", FPR8, VPR128, neon_uimm4_bare> {
5847   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
5848 }
5849 def DUPhv_H : NeonI_Scalar_DUP<"dup", "h", FPR16, VPR128, neon_uimm3_bare> {
5850   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
5851 }
5852 def DUPsv_S : NeonI_Scalar_DUP<"dup", "s", FPR32, VPR128, neon_uimm2_bare> {
5853   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
5854 }
5855 def DUPdv_D : NeonI_Scalar_DUP<"dup", "d", FPR64, VPR128, neon_uimm1_bare> {
5856   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
5857 }
5858
5859 multiclass NeonI_Scalar_DUP_Elt_pattern<Instruction DUPI, ValueType ResTy,
5860   ValueType OpTy, Operand OpImm,
5861   ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5862   def : Pat<(ResTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
5863             (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5864
5865   def : Pat<(ResTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
5866             (ResTy (DUPI
5867               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5868                 OpNImm:$Imm))>;
5869 }
5870
5871 multiclass NeonI_SDUP<PatFrag GetLow, PatFrag GetHigh,
5872                  ValueType ResTy, ValueType OpTy> {
5873   def : Pat<(ResTy (GetLow VPR128:$Rn)),
5874             (ResTy (DUPdv_D (OpTy VPR128:$Rn), 0))>;
5875   def : Pat<(ResTy (GetHigh VPR128:$Rn)),
5876             (ResTy (DUPdv_D (OpTy VPR128:$Rn), 1))>;
5877 }
5878
5879 defm : NeonI_SDUP<Neon_low16B, Neon_High16B, v8i8, v16i8>;
5880 defm : NeonI_SDUP<Neon_low8H, Neon_High8H, v4i16, v8i16>;
5881 defm : NeonI_SDUP<Neon_low4S, Neon_High4S, v2i32, v4i32>;
5882 defm : NeonI_SDUP<Neon_low2D, Neon_High2D, v1i64, v2i64>;
5883 defm : NeonI_SDUP<Neon_low4f, Neon_High4f, v2f32, v4f32>;
5884 defm : NeonI_SDUP<Neon_low2d, Neon_High2d, v1f64, v2f64>;
5885
5886 // Patterns  for vector extract of FP data using scalar DUP instructions
5887 defm : NeonI_Scalar_DUP_Elt_pattern<DUPsv_S, f32,
5888   v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5889 defm : NeonI_Scalar_DUP_Elt_pattern<DUPdv_D, f64,
5890   v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5891
5892 multiclass NeonI_Scalar_DUP_alias<string asmop, string asmlane,
5893                                   Instruction DUPI, Operand OpImm,
5894                                   RegisterClass ResRC> {
5895   def : NeonInstAlias<!strconcat(asmop, "$Rd, $Rn." # asmlane # "[$Imm]"),
5896           (DUPI ResRC:$Rd, VPR128:$Rn, OpImm:$Imm), 0b0>;
5897 }
5898
5899 // Aliases for Scalar copy - DUP element (scalar)
5900 // FIXME: This is actually the preferred syntax but TableGen can't deal with
5901 // custom printing of aliases.
5902 defm : NeonI_Scalar_DUP_alias<"mov", ".b", DUPbv_B, neon_uimm4_bare, FPR8>;
5903 defm : NeonI_Scalar_DUP_alias<"mov", ".h", DUPhv_H, neon_uimm3_bare, FPR16>;
5904 defm : NeonI_Scalar_DUP_alias<"mov", ".s", DUPsv_S, neon_uimm2_bare, FPR32>;
5905 defm : NeonI_Scalar_DUP_alias<"mov", ".d", DUPdv_D, neon_uimm1_bare, FPR64>;
5906
5907
5908 //===----------------------------------------------------------------------===//
5909 // Non-Instruction Patterns
5910 //===----------------------------------------------------------------------===//
5911
5912 // 64-bit vector bitcasts...
5913
5914 def : Pat<(v1i64 (bitconvert (v8i8  VPR64:$src))), (v1i64 VPR64:$src)>;
5915 def : Pat<(v2f32 (bitconvert (v8i8  VPR64:$src))), (v2f32 VPR64:$src)>;
5916 def : Pat<(v2i32 (bitconvert (v8i8  VPR64:$src))), (v2i32 VPR64:$src)>;
5917 def : Pat<(v4i16 (bitconvert (v8i8  VPR64:$src))), (v4i16 VPR64:$src)>;
5918
5919 def : Pat<(v1i64 (bitconvert (v4i16  VPR64:$src))), (v1i64 VPR64:$src)>;
5920 def : Pat<(v2i32 (bitconvert (v4i16  VPR64:$src))), (v2i32 VPR64:$src)>;
5921 def : Pat<(v2f32 (bitconvert (v4i16  VPR64:$src))), (v2f32 VPR64:$src)>;
5922 def : Pat<(v8i8  (bitconvert (v4i16  VPR64:$src))), (v8i8 VPR64:$src)>;
5923
5924 def : Pat<(v1i64 (bitconvert (v2i32  VPR64:$src))), (v1i64 VPR64:$src)>;
5925 def : Pat<(v2f32 (bitconvert (v2i32  VPR64:$src))), (v2f32 VPR64:$src)>;
5926 def : Pat<(v4i16 (bitconvert (v2i32  VPR64:$src))), (v4i16 VPR64:$src)>;
5927 def : Pat<(v8i8  (bitconvert (v2i32  VPR64:$src))), (v8i8 VPR64:$src)>;
5928
5929 def : Pat<(v1i64 (bitconvert (v2f32  VPR64:$src))), (v1i64 VPR64:$src)>;
5930 def : Pat<(v2i32 (bitconvert (v2f32  VPR64:$src))), (v2i32 VPR64:$src)>;
5931 def : Pat<(v4i16 (bitconvert (v2f32  VPR64:$src))), (v4i16 VPR64:$src)>;
5932 def : Pat<(v8i8  (bitconvert (v2f32  VPR64:$src))), (v8i8 VPR64:$src)>;
5933
5934 def : Pat<(v2f32 (bitconvert (v1i64  VPR64:$src))), (v2f32 VPR64:$src)>;
5935 def : Pat<(v2i32 (bitconvert (v1i64  VPR64:$src))), (v2i32 VPR64:$src)>;
5936 def : Pat<(v4i16 (bitconvert (v1i64  VPR64:$src))), (v4i16 VPR64:$src)>;
5937 def : Pat<(v8i8  (bitconvert (v1i64  VPR64:$src))), (v8i8 VPR64:$src)>;
5938
5939 // ..and 128-bit vector bitcasts...
5940
5941 def : Pat<(v2f64 (bitconvert (v16i8  VPR128:$src))), (v2f64 VPR128:$src)>;
5942 def : Pat<(v2i64 (bitconvert (v16i8  VPR128:$src))), (v2i64 VPR128:$src)>;
5943 def : Pat<(v4f32 (bitconvert (v16i8  VPR128:$src))), (v4f32 VPR128:$src)>;
5944 def : Pat<(v4i32 (bitconvert (v16i8  VPR128:$src))), (v4i32 VPR128:$src)>;
5945 def : Pat<(v8i16 (bitconvert (v16i8  VPR128:$src))), (v8i16 VPR128:$src)>;
5946
5947 def : Pat<(v2f64 (bitconvert (v8i16  VPR128:$src))), (v2f64 VPR128:$src)>;
5948 def : Pat<(v2i64 (bitconvert (v8i16  VPR128:$src))), (v2i64 VPR128:$src)>;
5949 def : Pat<(v4i32 (bitconvert (v8i16  VPR128:$src))), (v4i32 VPR128:$src)>;
5950 def : Pat<(v4f32 (bitconvert (v8i16  VPR128:$src))), (v4f32 VPR128:$src)>;
5951 def : Pat<(v16i8 (bitconvert (v8i16  VPR128:$src))), (v16i8 VPR128:$src)>;
5952
5953 def : Pat<(v2f64 (bitconvert (v4i32  VPR128:$src))), (v2f64 VPR128:$src)>;
5954 def : Pat<(v2i64 (bitconvert (v4i32  VPR128:$src))), (v2i64 VPR128:$src)>;
5955 def : Pat<(v4f32 (bitconvert (v4i32  VPR128:$src))), (v4f32 VPR128:$src)>;
5956 def : Pat<(v8i16 (bitconvert (v4i32  VPR128:$src))), (v8i16 VPR128:$src)>;
5957 def : Pat<(v16i8 (bitconvert (v4i32  VPR128:$src))), (v16i8 VPR128:$src)>;
5958
5959 def : Pat<(v2f64 (bitconvert (v4f32  VPR128:$src))), (v2f64 VPR128:$src)>;
5960 def : Pat<(v2i64 (bitconvert (v4f32  VPR128:$src))), (v2i64 VPR128:$src)>;
5961 def : Pat<(v4i32 (bitconvert (v4f32  VPR128:$src))), (v4i32 VPR128:$src)>;
5962 def : Pat<(v8i16 (bitconvert (v4f32  VPR128:$src))), (v8i16 VPR128:$src)>;
5963 def : Pat<(v16i8 (bitconvert (v4f32  VPR128:$src))), (v16i8 VPR128:$src)>;
5964
5965 def : Pat<(v2f64 (bitconvert (v2i64  VPR128:$src))), (v2f64 VPR128:$src)>;
5966 def : Pat<(v4f32 (bitconvert (v2i64  VPR128:$src))), (v4f32 VPR128:$src)>;
5967 def : Pat<(v4i32 (bitconvert (v2i64  VPR128:$src))), (v4i32 VPR128:$src)>;
5968 def : Pat<(v8i16 (bitconvert (v2i64  VPR128:$src))), (v8i16 VPR128:$src)>;
5969 def : Pat<(v16i8 (bitconvert (v2i64  VPR128:$src))), (v16i8 VPR128:$src)>;
5970
5971 def : Pat<(v2i64 (bitconvert (v2f64  VPR128:$src))), (v2i64 VPR128:$src)>;
5972 def : Pat<(v4f32 (bitconvert (v2f64  VPR128:$src))), (v4f32 VPR128:$src)>;
5973 def : Pat<(v4i32 (bitconvert (v2f64  VPR128:$src))), (v4i32 VPR128:$src)>;
5974 def : Pat<(v8i16 (bitconvert (v2f64  VPR128:$src))), (v8i16 VPR128:$src)>;
5975 def : Pat<(v16i8 (bitconvert (v2f64  VPR128:$src))), (v16i8 VPR128:$src)>;
5976
5977
5978 // ...and scalar bitcasts...
5979 def : Pat<(f16 (bitconvert (v1i16  FPR16:$src))), (f16 FPR16:$src)>;
5980 def : Pat<(f32 (bitconvert (v1i32  FPR32:$src))), (f32 FPR32:$src)>;
5981 def : Pat<(f64 (bitconvert (v1i64  FPR64:$src))), (f64 FPR64:$src)>;
5982 def : Pat<(f32 (bitconvert (v1f32  FPR32:$src))), (f32 FPR32:$src)>;
5983 def : Pat<(f64 (bitconvert (v1f64  FPR64:$src))), (f64 FPR64:$src)>;
5984
5985 def : Pat<(i64 (bitconvert (v1i64  FPR64:$src))), (FMOVxd $src)>;
5986 def : Pat<(i32 (bitconvert (v1i32  FPR32:$src))), (FMOVws $src)>;
5987
5988 def : Pat<(v8i8  (bitconvert (v1i64  VPR64:$src))), (v8i8 VPR64:$src)>;
5989 def : Pat<(v4i16 (bitconvert (v1i64  VPR64:$src))), (v4i16 VPR64:$src)>;
5990 def : Pat<(v2i32 (bitconvert (v1i64  VPR64:$src))), (v2i32 VPR64:$src)>;
5991
5992 def : Pat<(f64   (bitconvert (v8i8  VPR64:$src))), (f64 VPR64:$src)>;
5993 def : Pat<(f64   (bitconvert (v4i16  VPR64:$src))), (f64 VPR64:$src)>;
5994 def : Pat<(f64   (bitconvert (v2i32  VPR64:$src))), (f64 VPR64:$src)>;
5995 def : Pat<(f64   (bitconvert (v2f32  VPR64:$src))), (f64 VPR64:$src)>;
5996 def : Pat<(f64   (bitconvert (v1i64  VPR64:$src))), (f64 VPR64:$src)>;
5997
5998 def : Pat<(f128  (bitconvert (v16i8  VPR128:$src))), (f128 VPR128:$src)>;
5999 def : Pat<(f128  (bitconvert (v8i16  VPR128:$src))), (f128 VPR128:$src)>;
6000 def : Pat<(f128  (bitconvert (v4i32  VPR128:$src))), (f128 VPR128:$src)>;
6001 def : Pat<(f128  (bitconvert (v2i64  VPR128:$src))), (f128 VPR128:$src)>;
6002 def : Pat<(f128  (bitconvert (v4f32  VPR128:$src))), (f128 VPR128:$src)>;
6003 def : Pat<(f128  (bitconvert (v2f64  VPR128:$src))), (f128 VPR128:$src)>;
6004
6005 def : Pat<(v1i16 (bitconvert (f16  FPR16:$src))), (v1i16 FPR16:$src)>;
6006 def : Pat<(v1i32 (bitconvert (f32  FPR32:$src))), (v1i32 FPR32:$src)>;
6007 def : Pat<(v1i64 (bitconvert (f64  FPR64:$src))), (v1i64 FPR64:$src)>;
6008 def : Pat<(v1f32 (bitconvert (f32  FPR32:$src))), (v1f32 FPR32:$src)>;
6009 def : Pat<(v1f64 (bitconvert (f64  FPR64:$src))), (v1f64 FPR64:$src)>;
6010
6011 def : Pat<(v1i64 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6012 def : Pat<(v1i32 (bitconvert (i32  GPR32:$src))), (FMOVsw $src)>;
6013
6014 def : Pat<(v8i8   (bitconvert (f64   FPR64:$src))), (v8i8 FPR64:$src)>;
6015 def : Pat<(v4i16  (bitconvert (f64   FPR64:$src))), (v4i16 FPR64:$src)>;
6016 def : Pat<(v2i32  (bitconvert (f64   FPR64:$src))), (v2i32 FPR64:$src)>;
6017 def : Pat<(v2f32  (bitconvert (f64   FPR64:$src))), (v2f32 FPR64:$src)>;
6018 def : Pat<(v1i64  (bitconvert (f64   FPR64:$src))), (v1i64 FPR64:$src)>;
6019
6020 def : Pat<(v16i8  (bitconvert (f128   FPR128:$src))), (v16i8 FPR128:$src)>;
6021 def : Pat<(v8i16  (bitconvert (f128   FPR128:$src))), (v8i16 FPR128:$src)>;
6022 def : Pat<(v4i32  (bitconvert (f128   FPR128:$src))), (v4i32 FPR128:$src)>;
6023 def : Pat<(v2i64  (bitconvert (f128   FPR128:$src))), (v2i64 FPR128:$src)>;
6024 def : Pat<(v4f32  (bitconvert (f128   FPR128:$src))), (v4f32 FPR128:$src)>;
6025 def : Pat<(v2f64  (bitconvert (f128   FPR128:$src))), (v2f64 FPR128:$src)>;
6026
6027 // Scalar Three Same
6028
6029 def neon_uimm3 : Operand<i64>,
6030                    ImmLeaf<i64, [{return Imm < 8;}]> {
6031   let ParserMatchClass = uimm3_asmoperand;
6032   let PrintMethod = "printUImmHexOperand";
6033 }
6034
6035 def neon_uimm4 : Operand<i64>,
6036                    ImmLeaf<i64, [{return Imm < 16;}]> {
6037   let ParserMatchClass = uimm4_asmoperand;
6038   let PrintMethod = "printUImmHexOperand";
6039 }
6040
6041 // Bitwise Extract
6042 class NeonI_Extract<bit q, bits<2> op2, string asmop,
6043                     string OpS, RegisterOperand OpVPR, Operand OpImm>
6044   : NeonI_BitExtract<q, op2, (outs OpVPR:$Rd),
6045                      (ins OpVPR:$Rn, OpVPR:$Rm, OpImm:$Index),
6046                      asmop # "\t$Rd." # OpS # ", $Rn." # OpS #
6047                      ", $Rm." # OpS # ", $Index",
6048                      [],
6049                      NoItinerary>{
6050   bits<4> Index;
6051 }
6052
6053 def EXTvvvi_8b : NeonI_Extract<0b0, 0b00, "ext", "8b",
6054                                VPR64, neon_uimm3> {
6055   let Inst{14-11} = {0b0, Index{2}, Index{1}, Index{0}};
6056 }
6057
6058 def EXTvvvi_16b: NeonI_Extract<0b1, 0b00, "ext", "16b",
6059                                VPR128, neon_uimm4> {
6060   let Inst{14-11} = Index;
6061 }
6062
6063 class NI_Extract<ValueType OpTy, RegisterOperand OpVPR, Instruction INST,
6064                  Operand OpImm>
6065   : Pat<(OpTy (Neon_vextract (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm),
6066                                  (i64 OpImm:$Imm))),
6067               (INST OpVPR:$Rn, OpVPR:$Rm, OpImm:$Imm)>;
6068
6069 def : NI_Extract<v8i8,  VPR64,  EXTvvvi_8b,  neon_uimm3>;
6070 def : NI_Extract<v4i16, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6071 def : NI_Extract<v2i32, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6072 def : NI_Extract<v1i64, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6073 def : NI_Extract<v2f32, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6074 def : NI_Extract<v1f64, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6075 def : NI_Extract<v16i8, VPR128, EXTvvvi_16b, neon_uimm4>;
6076 def : NI_Extract<v8i16, VPR128, EXTvvvi_16b, neon_uimm4>;
6077 def : NI_Extract<v4i32, VPR128, EXTvvvi_16b, neon_uimm4>;
6078 def : NI_Extract<v2i64, VPR128, EXTvvvi_16b, neon_uimm4>;
6079 def : NI_Extract<v4f32, VPR128, EXTvvvi_16b, neon_uimm4>;
6080 def : NI_Extract<v2f64, VPR128, EXTvvvi_16b, neon_uimm4>;
6081
6082 // Table lookup
6083 class NI_TBL<bit q, bits<2> op2, bits<2> len, bit op,
6084              string asmop, string OpS, RegisterOperand OpVPR,
6085              RegisterOperand VecList>
6086   : NeonI_TBL<q, op2, len, op,
6087               (outs OpVPR:$Rd), (ins VecList:$Rn, OpVPR:$Rm),
6088               asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6089               [],
6090               NoItinerary>;
6091
6092 // The vectors in look up table are always 16b
6093 multiclass NI_TBL_pat<bits<2> len, bit op, string asmop, string List> {
6094   def _8b  : NI_TBL<0, 0b00, len, op, asmop, "8b", VPR64,
6095                     !cast<RegisterOperand>(List # "16B_operand")>;
6096
6097   def _16b : NI_TBL<1, 0b00, len, op, asmop, "16b", VPR128,
6098                     !cast<RegisterOperand>(List # "16B_operand")>;
6099 }
6100
6101 defm TBL1 : NI_TBL_pat<0b00, 0b0, "tbl", "VOne">;
6102 defm TBL2 : NI_TBL_pat<0b01, 0b0, "tbl", "VPair">;
6103 defm TBL3 : NI_TBL_pat<0b10, 0b0, "tbl", "VTriple">;
6104 defm TBL4 : NI_TBL_pat<0b11, 0b0, "tbl", "VQuad">;
6105
6106 // Table lookup extention
6107 class NI_TBX<bit q, bits<2> op2, bits<2> len, bit op,
6108              string asmop, string OpS, RegisterOperand OpVPR,
6109              RegisterOperand VecList>
6110   : NeonI_TBL<q, op2, len, op,
6111               (outs OpVPR:$Rd), (ins OpVPR:$src, VecList:$Rn, OpVPR:$Rm),
6112               asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6113               [],
6114               NoItinerary> {
6115   let Constraints = "$src = $Rd";
6116 }
6117
6118 // The vectors in look up table are always 16b
6119 multiclass NI_TBX_pat<bits<2> len, bit op, string asmop, string List> {
6120   def _8b  : NI_TBX<0, 0b00, len, op, asmop, "8b", VPR64,
6121                     !cast<RegisterOperand>(List # "16B_operand")>;
6122
6123   def _16b : NI_TBX<1, 0b00, len, op, asmop, "16b", VPR128,
6124                     !cast<RegisterOperand>(List # "16B_operand")>;
6125 }
6126
6127 defm TBX1 : NI_TBX_pat<0b00, 0b1, "tbx", "VOne">;
6128 defm TBX2 : NI_TBX_pat<0b01, 0b1, "tbx", "VPair">;
6129 defm TBX3 : NI_TBX_pat<0b10, 0b1, "tbx", "VTriple">;
6130 defm TBX4 : NI_TBX_pat<0b11, 0b1, "tbx", "VQuad">;
6131
6132 // The followings are for instruction class (3V Elem)
6133
6134 // Variant 1
6135
6136 class NI_2VE<bit q, bit u, bits<2> size, bits<4> opcode,
6137              string asmop, string ResS, string OpS, string EleOpS,
6138              Operand OpImm, RegisterOperand ResVPR,
6139              RegisterOperand OpVPR, RegisterOperand EleOpVPR>
6140   : NeonI_2VElem<q, u, size, opcode,
6141                  (outs ResVPR:$Rd), (ins ResVPR:$src, OpVPR:$Rn,
6142                                          EleOpVPR:$Re, OpImm:$Index),
6143                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
6144                  ", $Re." # EleOpS # "[$Index]",
6145                  [],
6146                  NoItinerary> {
6147   bits<3> Index;
6148   bits<5> Re;
6149
6150   let Constraints = "$src = $Rd";
6151 }
6152
6153 multiclass NI_2VE_v1<bit u, bits<4> opcode, string asmop> {
6154   // vector register class for element is always 128-bit to cover the max index
6155   def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6156                      neon_uimm2_bare, VPR64, VPR64, VPR128> {
6157     let Inst{11} = {Index{1}};
6158     let Inst{21} = {Index{0}};
6159     let Inst{20-16} = Re;
6160   }
6161
6162   def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6163                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
6164     let Inst{11} = {Index{1}};
6165     let Inst{21} = {Index{0}};
6166     let Inst{20-16} = Re;
6167   }
6168
6169   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6170   def _4h8h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
6171                      neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
6172     let Inst{11} = {Index{2}};
6173     let Inst{21} = {Index{1}};
6174     let Inst{20} = {Index{0}};
6175     let Inst{19-16} = Re{3-0};
6176   }
6177
6178   def _8h8h : NI_2VE<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
6179                      neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
6180     let Inst{11} = {Index{2}};
6181     let Inst{21} = {Index{1}};
6182     let Inst{20} = {Index{0}};
6183     let Inst{19-16} = Re{3-0};
6184   }
6185 }
6186
6187 defm MLAvve : NI_2VE_v1<0b1, 0b0000, "mla">;
6188 defm MLSvve : NI_2VE_v1<0b1, 0b0100, "mls">;
6189
6190 // Pattern for lane in 128-bit vector
6191 class NI_2VE_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6192                    RegisterOperand ResVPR, RegisterOperand OpVPR,
6193                    RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
6194                    ValueType EleOpTy, SDPatternOperator coreop>
6195   : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
6196           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6197         (INST ResVPR:$src, OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
6198
6199 // Pattern for lane in 64-bit vector
6200 class NI_2VE_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6201                   RegisterOperand ResVPR, RegisterOperand OpVPR,
6202                   RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
6203                   ValueType EleOpTy, SDPatternOperator coreop>
6204   : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
6205           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6206         (INST ResVPR:$src, OpVPR:$Rn,
6207           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
6208
6209 multiclass NI_2VE_v1_pat<string subop, SDPatternOperator op>
6210 {
6211   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
6212                      op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32,
6213                      BinOpFrag<(Neon_vduplane
6214                                  (Neon_low4S node:$LHS), node:$RHS)>>;
6215
6216   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
6217                      op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32,
6218                      BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6219
6220   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
6221                      op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16,
6222                      BinOpFrag<(Neon_vduplane
6223                                  (Neon_low8H node:$LHS), node:$RHS)>>;
6224
6225   def : NI_2VE_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
6226                      op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16,
6227                      BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6228
6229   // Index can only be half of the max value for lane in 64-bit vector
6230
6231   def : NI_2VE_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
6232                     op, VPR64, VPR64, VPR64, v2i32, v2i32, v2i32,
6233                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6234
6235   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4s"), neon_uimm1_bare,
6236                     op, VPR128, VPR128, VPR64, v4i32, v4i32, v2i32,
6237                     BinOpFrag<(Neon_vduplane
6238                                 (Neon_combine_4S node:$LHS, undef),
6239                                  node:$RHS)>>;
6240
6241   def : NI_2VE_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
6242                     op, VPR64, VPR64, VPR64Lo, v4i16, v4i16, v4i16,
6243                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6244
6245   def : NI_2VE_lane<!cast<Instruction>(subop # "_8h8h"), neon_uimm2_bare,
6246                     op, VPR128, VPR128, VPR64Lo, v8i16, v8i16, v4i16,
6247                     BinOpFrag<(Neon_vduplane
6248                                 (Neon_combine_8H node:$LHS, undef),
6249                                 node:$RHS)>>;
6250 }
6251
6252 defm MLA_lane_v1 : NI_2VE_v1_pat<"MLAvve", Neon_mla>;
6253 defm MLS_lane_v1 : NI_2VE_v1_pat<"MLSvve", Neon_mls>;
6254
6255 class NI_2VE_2op<bit q, bit u, bits<2> size, bits<4> opcode,
6256                  string asmop, string ResS, string OpS, string EleOpS,
6257                  Operand OpImm, RegisterOperand ResVPR,
6258                  RegisterOperand OpVPR, RegisterOperand EleOpVPR>
6259   : NeonI_2VElem<q, u, size, opcode,
6260                  (outs ResVPR:$Rd), (ins OpVPR:$Rn,
6261                                          EleOpVPR:$Re, OpImm:$Index),
6262                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
6263                  ", $Re." # EleOpS # "[$Index]",
6264                  [],
6265                  NoItinerary> {
6266   bits<3> Index;
6267   bits<5> Re;
6268 }
6269
6270 multiclass NI_2VE_v1_2op<bit u, bits<4> opcode, string asmop> {
6271   // vector register class for element is always 128-bit to cover the max index
6272   def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6273                          neon_uimm2_bare, VPR64, VPR64, VPR128> {
6274     let Inst{11} = {Index{1}};
6275     let Inst{21} = {Index{0}};
6276     let Inst{20-16} = Re;
6277   }
6278
6279   def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6280                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
6281     let Inst{11} = {Index{1}};
6282     let Inst{21} = {Index{0}};
6283     let Inst{20-16} = Re;
6284   }
6285
6286   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6287   def _4h8h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
6288                          neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
6289     let Inst{11} = {Index{2}};
6290     let Inst{21} = {Index{1}};
6291     let Inst{20} = {Index{0}};
6292     let Inst{19-16} = Re{3-0};
6293   }
6294
6295   def _8h8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
6296                          neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
6297     let Inst{11} = {Index{2}};
6298     let Inst{21} = {Index{1}};
6299     let Inst{20} = {Index{0}};
6300     let Inst{19-16} = Re{3-0};
6301   }
6302 }
6303
6304 defm MULve : NI_2VE_v1_2op<0b0, 0b1000, "mul">;
6305 defm SQDMULHve : NI_2VE_v1_2op<0b0, 0b1100, "sqdmulh">;
6306 defm SQRDMULHve : NI_2VE_v1_2op<0b0, 0b1101, "sqrdmulh">;
6307
6308 // Pattern for lane in 128-bit vector
6309 class NI_2VE_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6310                        RegisterOperand OpVPR, RegisterOperand EleOpVPR,
6311                        ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
6312                        SDPatternOperator coreop>
6313   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
6314           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6315         (INST OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
6316
6317 // Pattern for lane in 64-bit vector
6318 class NI_2VE_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6319                       RegisterOperand OpVPR, RegisterOperand EleOpVPR,
6320                       ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
6321                       SDPatternOperator coreop>
6322   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
6323           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6324         (INST OpVPR:$Rn,
6325           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
6326
6327 multiclass NI_2VE_mul_v1_pat<string subop, SDPatternOperator op> {
6328   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
6329                          op, VPR64, VPR128, v2i32, v2i32, v4i32,
6330                          BinOpFrag<(Neon_vduplane
6331                                      (Neon_low4S node:$LHS), node:$RHS)>>;
6332
6333   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
6334                          op, VPR128, VPR128, v4i32, v4i32, v4i32,
6335                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6336
6337   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
6338                          op, VPR64, VPR128Lo, v4i16, v4i16, v8i16,
6339                          BinOpFrag<(Neon_vduplane
6340                                     (Neon_low8H node:$LHS), node:$RHS)>>;
6341
6342   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
6343                          op, VPR128, VPR128Lo, v8i16, v8i16, v8i16,
6344                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6345
6346   // Index can only be half of the max value for lane in 64-bit vector
6347
6348   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
6349                         op, VPR64, VPR64, v2i32, v2i32, v2i32,
6350                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6351
6352   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4s"), neon_uimm1_bare,
6353                         op, VPR128, VPR64, v4i32, v4i32, v2i32,
6354                         BinOpFrag<(Neon_vduplane
6355                                     (Neon_combine_4S node:$LHS, undef),
6356                                      node:$RHS)>>;
6357
6358   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
6359                         op, VPR64, VPR64Lo, v4i16, v4i16, v4i16,
6360                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6361
6362   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_8h8h"), neon_uimm2_bare,
6363                         op, VPR128, VPR64Lo, v8i16, v8i16, v4i16,
6364                         BinOpFrag<(Neon_vduplane
6365                                     (Neon_combine_8H node:$LHS, undef),
6366                                     node:$RHS)>>;
6367 }
6368
6369 defm MUL_lane_v1 : NI_2VE_mul_v1_pat<"MULve", mul>;
6370 defm SQDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQDMULHve", int_arm_neon_vqdmulh>;
6371 defm SQRDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQRDMULHve", int_arm_neon_vqrdmulh>;
6372
6373 // Variant 2
6374
6375 multiclass NI_2VE_v2_2op<bit u, bits<4> opcode, string asmop> {
6376   // vector register class for element is always 128-bit to cover the max index
6377   def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6378                          neon_uimm2_bare, VPR64, VPR64, VPR128> {
6379     let Inst{11} = {Index{1}};
6380     let Inst{21} = {Index{0}};
6381     let Inst{20-16} = Re;
6382   }
6383
6384   def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6385                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
6386     let Inst{11} = {Index{1}};
6387     let Inst{21} = {Index{0}};
6388     let Inst{20-16} = Re;
6389   }
6390
6391   // _1d2d doesn't exist!
6392
6393   def _2d2d : NI_2VE_2op<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
6394                          neon_uimm1_bare, VPR128, VPR128, VPR128> {
6395     let Inst{11} = {Index{0}};
6396     let Inst{21} = 0b0;
6397     let Inst{20-16} = Re;
6398   }
6399 }
6400
6401 defm FMULve : NI_2VE_v2_2op<0b0, 0b1001, "fmul">;
6402 defm FMULXve : NI_2VE_v2_2op<0b1, 0b1001, "fmulx">;
6403
6404 class NI_2VE_mul_lane_2d<Instruction INST, Operand OpImm, SDPatternOperator op,
6405                          RegisterOperand OpVPR, RegisterOperand EleOpVPR,
6406                          ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
6407                          SDPatternOperator coreop>
6408   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
6409           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (EleOpTy EleOpVPR:$Re))))),
6410         (INST OpVPR:$Rn,
6411           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), 0)>;
6412
6413 multiclass NI_2VE_mul_v2_pat<string subop, SDPatternOperator op> {
6414   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
6415                          op, VPR64, VPR128, v2f32, v2f32, v4f32,
6416                          BinOpFrag<(Neon_vduplane
6417                                      (Neon_low4f node:$LHS), node:$RHS)>>;
6418
6419   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
6420                          op, VPR128, VPR128, v4f32, v4f32, v4f32,
6421                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6422
6423   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
6424                          op, VPR128, VPR128, v2f64, v2f64, v2f64,
6425                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6426
6427   // Index can only be half of the max value for lane in 64-bit vector
6428
6429   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
6430                         op, VPR64, VPR64, v2f32, v2f32, v2f32,
6431                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6432
6433   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4s"), neon_uimm1_bare,
6434                         op, VPR128, VPR64, v4f32, v4f32, v2f32,
6435                         BinOpFrag<(Neon_vduplane
6436                                     (Neon_combine_4f node:$LHS, undef),
6437                                     node:$RHS)>>;
6438
6439   def : NI_2VE_mul_lane_2d<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
6440                            op, VPR128, VPR64, v2f64, v2f64, v1f64,
6441                            BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
6442 }
6443
6444 defm FMUL_lane_v2 : NI_2VE_mul_v2_pat<"FMULve", fmul>;
6445 defm FMULX_lane_v2 : NI_2VE_mul_v2_pat<"FMULXve", int_aarch64_neon_vmulx>;
6446
6447 // The followings are patterns using fma
6448 // -ffp-contract=fast generates fma
6449
6450 multiclass NI_2VE_v2<bit u, bits<4> opcode, string asmop> {
6451   // vector register class for element is always 128-bit to cover the max index
6452   def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6453                      neon_uimm2_bare, VPR64, VPR64, VPR128> {
6454     let Inst{11} = {Index{1}};
6455     let Inst{21} = {Index{0}};
6456     let Inst{20-16} = Re;
6457   }
6458
6459   def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6460                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
6461     let Inst{11} = {Index{1}};
6462     let Inst{21} = {Index{0}};
6463     let Inst{20-16} = Re;
6464   }
6465
6466   // _1d2d doesn't exist!
6467
6468   def _2d2d : NI_2VE<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
6469                      neon_uimm1_bare, VPR128, VPR128, VPR128> {
6470     let Inst{11} = {Index{0}};
6471     let Inst{21} = 0b0;
6472     let Inst{20-16} = Re;
6473   }
6474 }
6475
6476 defm FMLAvve : NI_2VE_v2<0b0, 0b0001, "fmla">;
6477 defm FMLSvve : NI_2VE_v2<0b0, 0b0101, "fmls">;
6478
6479 // Pattern for lane in 128-bit vector
6480 class NI_2VEswap_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6481                        RegisterOperand ResVPR, RegisterOperand OpVPR,
6482                        ValueType ResTy, ValueType OpTy,
6483                        SDPatternOperator coreop>
6484   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
6485                    (ResTy ResVPR:$src), (ResTy ResVPR:$Rn))),
6486         (INST ResVPR:$src, ResVPR:$Rn, OpVPR:$Re, OpImm:$Index)>;
6487
6488 // Pattern for lane in 64-bit vector
6489 class NI_2VEswap_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6490                       RegisterOperand ResVPR, RegisterOperand OpVPR,
6491                       ValueType ResTy, ValueType OpTy,
6492                       SDPatternOperator coreop>
6493   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
6494                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
6495         (INST ResVPR:$src, ResVPR:$Rn,
6496           (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), OpImm:$Index)>;
6497
6498 // Pattern for lane in 64-bit vector
6499 class NI_2VEswap_lane_2d2d<Instruction INST, Operand OpImm,
6500                            SDPatternOperator op,
6501                            RegisterOperand ResVPR, RegisterOperand OpVPR,
6502                            ValueType ResTy, ValueType OpTy,
6503                            SDPatternOperator coreop>
6504   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (OpTy OpVPR:$Re))),
6505                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
6506         (INST ResVPR:$src, ResVPR:$Rn,
6507           (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), 0)>;
6508
6509
6510 multiclass NI_2VE_fma_v2_pat<string subop, SDPatternOperator op> {
6511   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
6512                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
6513                          BinOpFrag<(Neon_vduplane
6514                                      (Neon_low4f node:$LHS), node:$RHS)>>;
6515
6516   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
6517                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
6518                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6519
6520   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
6521                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
6522                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6523
6524   // Index can only be half of the max value for lane in 64-bit vector
6525
6526   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
6527                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
6528                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6529
6530   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
6531                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
6532                         BinOpFrag<(Neon_vduplane
6533                                     (Neon_combine_4f node:$LHS, undef),
6534                                     node:$RHS)>>;
6535
6536   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
6537                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
6538                              BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
6539 }
6540
6541 defm FMLA_lane_v2_s : NI_2VE_fma_v2_pat<"FMLAvve", fma>;
6542
6543 multiclass NI_2VE_fms_v2_pat<string subop, SDPatternOperator op>
6544 {
6545   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
6546                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
6547                          BinOpFrag<(fneg (Neon_vduplane
6548                                      (Neon_low4f node:$LHS), node:$RHS))>>;
6549
6550   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
6551                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
6552                          BinOpFrag<(Neon_vduplane
6553                                      (Neon_low4f (fneg node:$LHS)),
6554                                      node:$RHS)>>;
6555
6556   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
6557                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
6558                          BinOpFrag<(fneg (Neon_vduplane
6559                                      node:$LHS, node:$RHS))>>;
6560
6561   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
6562                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
6563                          BinOpFrag<(Neon_vduplane
6564                                      (fneg node:$LHS), node:$RHS)>>;
6565
6566   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
6567                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
6568                          BinOpFrag<(fneg (Neon_vduplane
6569                                      node:$LHS, node:$RHS))>>;
6570
6571   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
6572                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
6573                          BinOpFrag<(Neon_vduplane
6574                                      (fneg node:$LHS), node:$RHS)>>;
6575
6576   // Index can only be half of the max value for lane in 64-bit vector
6577
6578   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
6579                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
6580                         BinOpFrag<(fneg (Neon_vduplane
6581                                     node:$LHS, node:$RHS))>>;
6582
6583   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
6584                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
6585                         BinOpFrag<(Neon_vduplane
6586                                     (fneg node:$LHS), node:$RHS)>>;
6587
6588   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
6589                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
6590                         BinOpFrag<(fneg (Neon_vduplane
6591                                     (Neon_combine_4f node:$LHS, undef),
6592                                     node:$RHS))>>;
6593
6594   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
6595                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
6596                         BinOpFrag<(Neon_vduplane
6597                                     (Neon_combine_4f (fneg node:$LHS), undef),
6598                                     node:$RHS)>>;
6599
6600   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
6601                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
6602                              BinOpFrag<(fneg (Neon_combine_2d
6603                                          node:$LHS, node:$RHS))>>;
6604
6605   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
6606                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
6607                              BinOpFrag<(Neon_combine_2d
6608                                          (fneg node:$LHS), (fneg node:$RHS))>>;
6609 }
6610
6611 defm FMLS_lane_v2_s : NI_2VE_fms_v2_pat<"FMLSvve", fma>;
6612
6613 // Variant 3: Long type
6614 // E.g. SMLAL : 4S/4H/H (v0-v15), 2D/2S/S
6615 //      SMLAL2: 4S/8H/H (v0-v15), 2D/4S/S
6616
6617 multiclass NI_2VE_v3<bit u, bits<4> opcode, string asmop> {
6618   // vector register class for element is always 128-bit to cover the max index
6619   def _2d2s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
6620                      neon_uimm2_bare, VPR128, VPR64, VPR128> {
6621     let Inst{11} = {Index{1}};
6622     let Inst{21} = {Index{0}};
6623     let Inst{20-16} = Re;
6624   }
6625
6626   def _2d4s : NI_2VE<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
6627                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
6628     let Inst{11} = {Index{1}};
6629     let Inst{21} = {Index{0}};
6630     let Inst{20-16} = Re;
6631   }
6632
6633   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6634   def _4s8h : NI_2VE<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
6635                      neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
6636     let Inst{11} = {Index{2}};
6637     let Inst{21} = {Index{1}};
6638     let Inst{20} = {Index{0}};
6639     let Inst{19-16} = Re{3-0};
6640   }
6641
6642   def _4s4h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
6643                      neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
6644     let Inst{11} = {Index{2}};
6645     let Inst{21} = {Index{1}};
6646     let Inst{20} = {Index{0}};
6647     let Inst{19-16} = Re{3-0};
6648   }
6649 }
6650
6651 defm SMLALvve : NI_2VE_v3<0b0, 0b0010, "smlal">;
6652 defm UMLALvve : NI_2VE_v3<0b1, 0b0010, "umlal">;
6653 defm SMLSLvve : NI_2VE_v3<0b0, 0b0110, "smlsl">;
6654 defm UMLSLvve : NI_2VE_v3<0b1, 0b0110, "umlsl">;
6655 defm SQDMLALvve : NI_2VE_v3<0b0, 0b0011, "sqdmlal">;
6656 defm SQDMLSLvve : NI_2VE_v3<0b0, 0b0111, "sqdmlsl">;
6657
6658 multiclass NI_2VE_v3_2op<bit u, bits<4> opcode, string asmop> {
6659   // vector register class for element is always 128-bit to cover the max index
6660   def _2d2s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
6661                          neon_uimm2_bare, VPR128, VPR64, VPR128> {
6662     let Inst{11} = {Index{1}};
6663     let Inst{21} = {Index{0}};
6664     let Inst{20-16} = Re;
6665   }
6666
6667   def _2d4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
6668                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
6669     let Inst{11} = {Index{1}};
6670     let Inst{21} = {Index{0}};
6671     let Inst{20-16} = Re;
6672   }
6673
6674   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6675   def _4s8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
6676                          neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
6677     let Inst{11} = {Index{2}};
6678     let Inst{21} = {Index{1}};
6679     let Inst{20} = {Index{0}};
6680     let Inst{19-16} = Re{3-0};
6681   }
6682
6683   def _4s4h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
6684                          neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
6685     let Inst{11} = {Index{2}};
6686     let Inst{21} = {Index{1}};
6687     let Inst{20} = {Index{0}};
6688     let Inst{19-16} = Re{3-0};
6689   }
6690 }
6691
6692 defm SMULLve : NI_2VE_v3_2op<0b0, 0b1010, "smull">;
6693 defm UMULLve : NI_2VE_v3_2op<0b1, 0b1010, "umull">;
6694 defm SQDMULLve : NI_2VE_v3_2op<0b0, 0b1011, "sqdmull">;
6695
6696 // Pattern for lane in 128-bit vector
6697 class NI_2VEL2_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6698                      RegisterOperand EleOpVPR, ValueType ResTy,
6699                      ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
6700                      SDPatternOperator hiop, SDPatternOperator coreop>
6701   : Pat<(ResTy (op (ResTy VPR128:$src),
6702           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
6703           (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6704         (INST VPR128:$src, VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
6705
6706 // Pattern for lane in 64-bit vector
6707 class NI_2VEL2_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6708                     RegisterOperand EleOpVPR, ValueType ResTy,
6709                     ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
6710                     SDPatternOperator hiop, SDPatternOperator coreop>
6711   : Pat<(ResTy (op (ResTy VPR128:$src),
6712           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
6713           (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6714         (INST VPR128:$src, VPR128:$Rn,
6715           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
6716
6717 multiclass NI_2VEL_v3_pat<string subop, SDPatternOperator op> {
6718   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
6719                      op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16,
6720                      BinOpFrag<(Neon_vduplane
6721                                  (Neon_low8H node:$LHS), node:$RHS)>>;
6722
6723   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
6724                      op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32,
6725                      BinOpFrag<(Neon_vduplane
6726                                  (Neon_low4S node:$LHS), node:$RHS)>>;
6727
6728   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
6729                        op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H,
6730                        BinOpFrag<(Neon_vduplane
6731                                    (Neon_low8H node:$LHS), node:$RHS)>>;
6732
6733   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
6734                        op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S,
6735                        BinOpFrag<(Neon_vduplane
6736                                    (Neon_low4S node:$LHS), node:$RHS)>>;
6737
6738   // Index can only be half of the max value for lane in 64-bit vector
6739
6740   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
6741                     op, VPR128, VPR64, VPR64Lo, v4i32, v4i16, v4i16,
6742                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6743
6744   def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
6745                     op, VPR128, VPR64, VPR64, v2i64, v2i32, v2i32,
6746                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6747
6748   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
6749                       op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H,
6750                       BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6751
6752   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
6753                       op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S,
6754                       BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6755 }
6756
6757 defm SMLAL_lane_v3 : NI_2VEL_v3_pat<"SMLALvve", Neon_smlal>;
6758 defm UMLAL_lane_v3 : NI_2VEL_v3_pat<"UMLALvve", Neon_umlal>;
6759 defm SMLSL_lane_v3 : NI_2VEL_v3_pat<"SMLSLvve", Neon_smlsl>;
6760 defm UMLSL_lane_v3 : NI_2VEL_v3_pat<"UMLSLvve", Neon_umlsl>;
6761
6762 // Pattern for lane in 128-bit vector
6763 class NI_2VEL2_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6764                          RegisterOperand EleOpVPR, ValueType ResTy,
6765                          ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
6766                          SDPatternOperator hiop, SDPatternOperator coreop>
6767   : Pat<(ResTy (op
6768           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
6769           (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6770         (INST VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
6771
6772 // Pattern for lane in 64-bit vector
6773 class NI_2VEL2_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6774                         RegisterOperand EleOpVPR, ValueType ResTy,
6775                         ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
6776                         SDPatternOperator hiop, SDPatternOperator coreop>
6777   : Pat<(ResTy (op
6778           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
6779           (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6780         (INST VPR128:$Rn,
6781           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
6782
6783 multiclass NI_2VEL_mul_v3_pat<string subop, SDPatternOperator op> {
6784   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
6785                          op, VPR64, VPR128Lo, v4i32, v4i16, v8i16,
6786                          BinOpFrag<(Neon_vduplane
6787                                      (Neon_low8H node:$LHS), node:$RHS)>>;
6788
6789   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
6790                          op, VPR64, VPR128, v2i64, v2i32, v4i32,
6791                          BinOpFrag<(Neon_vduplane
6792                                      (Neon_low4S node:$LHS), node:$RHS)>>;
6793
6794   def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
6795                            op, VPR128Lo, v4i32, v8i16, v8i16, v4i16,
6796                            Neon_High8H,
6797                            BinOpFrag<(Neon_vduplane
6798                                        (Neon_low8H node:$LHS), node:$RHS)>>;
6799
6800   def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
6801                            op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S,
6802                            BinOpFrag<(Neon_vduplane
6803                                        (Neon_low4S node:$LHS), node:$RHS)>>;
6804
6805   // Index can only be half of the max value for lane in 64-bit vector
6806
6807   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
6808                         op, VPR64, VPR64Lo, v4i32, v4i16, v4i16,
6809                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6810
6811   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
6812                         op, VPR64, VPR64, v2i64, v2i32, v2i32,
6813                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6814
6815   def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
6816                           op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H,
6817                           BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6818
6819   def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
6820                           op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S,
6821                           BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6822 }
6823
6824 defm SMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SMULLve", int_arm_neon_vmulls>;
6825 defm UMULL_lane_v3 : NI_2VEL_mul_v3_pat<"UMULLve", int_arm_neon_vmullu>;
6826 defm SQDMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SQDMULLve", int_arm_neon_vqdmull>;
6827
6828 multiclass NI_qdma<SDPatternOperator op> {
6829   def _4s : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
6830                     (op node:$Ra,
6831                       (v4i32 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
6832
6833   def _2d : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
6834                     (op node:$Ra,
6835                       (v2i64 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
6836 }
6837
6838 defm Neon_qdmlal : NI_qdma<int_arm_neon_vqadds>;
6839 defm Neon_qdmlsl : NI_qdma<int_arm_neon_vqsubs>;
6840
6841 multiclass NI_2VEL_v3_qdma_pat<string subop, string op> {
6842   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
6843                      !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR128Lo,
6844                      v4i32, v4i16, v8i16,
6845                      BinOpFrag<(Neon_vduplane
6846                                  (Neon_low8H node:$LHS), node:$RHS)>>;
6847
6848   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
6849                      !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR128,
6850                      v2i64, v2i32, v4i32,
6851                      BinOpFrag<(Neon_vduplane
6852                                  (Neon_low4S node:$LHS), node:$RHS)>>;
6853
6854   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
6855                        !cast<PatFrag>(op # "_4s"), VPR128Lo,
6856                        v4i32, v8i16, v8i16, v4i16, Neon_High8H,
6857                        BinOpFrag<(Neon_vduplane
6858                                    (Neon_low8H node:$LHS), node:$RHS)>>;
6859
6860   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
6861                        !cast<PatFrag>(op # "_2d"), VPR128,
6862                        v2i64, v4i32, v4i32, v2i32, Neon_High4S,
6863                        BinOpFrag<(Neon_vduplane
6864                                    (Neon_low4S node:$LHS), node:$RHS)>>;
6865
6866   // Index can only be half of the max value for lane in 64-bit vector
6867
6868   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
6869                     !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR64Lo,
6870                     v4i32, v4i16, v4i16,
6871                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6872
6873   def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
6874                     !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR64,
6875                     v2i64, v2i32, v2i32,
6876                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6877
6878   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
6879                       !cast<PatFrag>(op # "_4s"), VPR64Lo,
6880                       v4i32, v8i16, v4i16, v4i16, Neon_High8H,
6881                       BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6882
6883   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
6884                       !cast<PatFrag>(op # "_2d"), VPR64,
6885                       v2i64, v4i32, v2i32, v2i32, Neon_High4S,
6886                       BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
6887 }
6888
6889 defm SQDMLAL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLALvve", "Neon_qdmlal">;
6890 defm SQDMLSL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLSLvve", "Neon_qdmlsl">;
6891
6892 // End of implementation for instruction class (3V Elem)
6893
6894 class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
6895                      RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
6896   : NeonI_copy<0b1, 0b0, 0b0011,
6897                (outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
6898                asmop # "\t$Rd." # Res # "[$Imm], $Rn",
6899                [(set (ResTy VPR128:$Rd),
6900                  (ResTy (vector_insert
6901                    (ResTy VPR128:$src),
6902                    (OpTy OpGPR:$Rn),
6903                    (OpImm:$Imm))))],
6904                NoItinerary> {
6905   bits<4> Imm;
6906   let Constraints = "$src = $Rd";
6907 }
6908
6909 //Insert element (vector, from main)
6910 def INSbw : NeonI_INS_main<"ins", "b", v16i8, GPR32, i32,
6911                            neon_uimm4_bare> {
6912   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6913 }
6914 def INShw : NeonI_INS_main<"ins", "h", v8i16, GPR32, i32,
6915                            neon_uimm3_bare> {
6916   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6917 }
6918 def INSsw : NeonI_INS_main<"ins", "s", v4i32, GPR32, i32,
6919                            neon_uimm2_bare> {
6920   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6921 }
6922 def INSdx : NeonI_INS_main<"ins", "d", v2i64, GPR64, i64,
6923                            neon_uimm1_bare> {
6924   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6925 }
6926
6927 def : NeonInstAlias<"mov $Rd.b[$Imm], $Rn",
6928                     (INSbw VPR128:$Rd, GPR32:$Rn, neon_uimm4_bare:$Imm), 0>;
6929 def : NeonInstAlias<"mov $Rd.h[$Imm], $Rn",
6930                     (INShw VPR128:$Rd, GPR32:$Rn, neon_uimm3_bare:$Imm), 0>;
6931 def : NeonInstAlias<"mov $Rd.s[$Imm], $Rn",
6932                     (INSsw VPR128:$Rd, GPR32:$Rn, neon_uimm2_bare:$Imm), 0>;
6933 def : NeonInstAlias<"mov $Rd.d[$Imm], $Rn",
6934                     (INSdx VPR128:$Rd, GPR64:$Rn, neon_uimm1_bare:$Imm), 0>;
6935
6936 class Neon_INS_main_pattern <ValueType ResTy,ValueType ExtResTy,
6937                              RegisterClass OpGPR, ValueType OpTy,
6938                              Operand OpImm, Instruction INS>
6939   : Pat<(ResTy (vector_insert
6940               (ResTy VPR64:$src),
6941               (OpTy OpGPR:$Rn),
6942               (OpImm:$Imm))),
6943         (ResTy (EXTRACT_SUBREG
6944           (ExtResTy (INS (ExtResTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
6945             OpGPR:$Rn, OpImm:$Imm)), sub_64))>;
6946
6947 def INSbw_pattern : Neon_INS_main_pattern<v8i8, v16i8, GPR32, i32,
6948                                           neon_uimm3_bare, INSbw>;
6949 def INShw_pattern : Neon_INS_main_pattern<v4i16, v8i16, GPR32, i32,
6950                                           neon_uimm2_bare, INShw>;
6951 def INSsw_pattern : Neon_INS_main_pattern<v2i32, v4i32, GPR32, i32,
6952                                           neon_uimm1_bare, INSsw>;
6953 def INSdx_pattern : Neon_INS_main_pattern<v1i64, v2i64, GPR64, i64,
6954                                           neon_uimm0_bare, INSdx>;
6955
6956 class NeonI_INS_element<string asmop, string Res, Operand ResImm>
6957   : NeonI_insert<0b1, 0b1,
6958                  (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn,
6959                  ResImm:$Immd, ResImm:$Immn),
6960                  asmop # "\t$Rd." # Res # "[$Immd], $Rn." # Res # "[$Immn]",
6961                  [],
6962                  NoItinerary> {
6963   let Constraints = "$src = $Rd";
6964   bits<4> Immd;
6965   bits<4> Immn;
6966 }
6967
6968 //Insert element (vector, from element)
6969 def INSELb : NeonI_INS_element<"ins", "b", neon_uimm4_bare> {
6970   let Inst{20-16} = {Immd{3}, Immd{2}, Immd{1}, Immd{0}, 0b1};
6971   let Inst{14-11} = {Immn{3}, Immn{2}, Immn{1}, Immn{0}};
6972 }
6973 def INSELh : NeonI_INS_element<"ins", "h", neon_uimm3_bare> {
6974   let Inst{20-16} = {Immd{2}, Immd{1}, Immd{0}, 0b1, 0b0};
6975   let Inst{14-11} = {Immn{2}, Immn{1}, Immn{0}, 0b0};
6976   // bit 11 is unspecified, but should be set to zero.
6977 }
6978 def INSELs : NeonI_INS_element<"ins", "s", neon_uimm2_bare> {
6979   let Inst{20-16} = {Immd{1}, Immd{0}, 0b1, 0b0, 0b0};
6980   let Inst{14-11} = {Immn{1}, Immn{0}, 0b0, 0b0};
6981   // bits 11-12 are unspecified, but should be set to zero.
6982 }
6983 def INSELd : NeonI_INS_element<"ins", "d", neon_uimm1_bare> {
6984   let Inst{20-16} = {Immd, 0b1, 0b0, 0b0, 0b0};
6985   let Inst{14-11} = {Immn{0}, 0b0, 0b0, 0b0};
6986   // bits 11-13 are unspecified, but should be set to zero.
6987 }
6988
6989 def : NeonInstAlias<"mov $Rd.b[$Immd], $Rn.b[$Immn]",
6990                     (INSELb VPR128:$Rd, VPR128:$Rn,
6991                       neon_uimm4_bare:$Immd, neon_uimm4_bare:$Immn), 0>;
6992 def : NeonInstAlias<"mov $Rd.h[$Immd], $Rn.h[$Immn]",
6993                     (INSELh VPR128:$Rd, VPR128:$Rn,
6994                       neon_uimm3_bare:$Immd, neon_uimm3_bare:$Immn), 0>;
6995 def : NeonInstAlias<"mov $Rd.s[$Immd], $Rn.s[$Immn]",
6996                     (INSELs VPR128:$Rd, VPR128:$Rn,
6997                       neon_uimm2_bare:$Immd, neon_uimm2_bare:$Immn), 0>;
6998 def : NeonInstAlias<"mov $Rd.d[$Immd], $Rn.d[$Immn]",
6999                     (INSELd VPR128:$Rd, VPR128:$Rn,
7000                       neon_uimm1_bare:$Immd, neon_uimm1_bare:$Immn), 0>;
7001
7002 multiclass Neon_INS_elt_pattern<ValueType ResTy, ValueType NaTy,
7003                                 ValueType MidTy, Operand StImm, Operand NaImm,
7004                                 Instruction INS> {
7005 def : Pat<(ResTy (vector_insert
7006             (ResTy VPR128:$src),
7007             (MidTy (vector_extract
7008               (ResTy VPR128:$Rn),
7009               (StImm:$Immn))),
7010             (StImm:$Immd))),
7011           (INS (ResTy VPR128:$src), (ResTy VPR128:$Rn),
7012               StImm:$Immd, StImm:$Immn)>;
7013
7014 def : Pat <(ResTy (vector_insert
7015              (ResTy VPR128:$src),
7016              (MidTy (vector_extract
7017                (NaTy VPR64:$Rn),
7018                (NaImm:$Immn))),
7019              (StImm:$Immd))),
7020            (INS (ResTy VPR128:$src),
7021              (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
7022              StImm:$Immd, NaImm:$Immn)>;
7023
7024 def : Pat <(NaTy (vector_insert
7025              (NaTy VPR64:$src),
7026              (MidTy (vector_extract
7027                (ResTy VPR128:$Rn),
7028                (StImm:$Immn))),
7029              (NaImm:$Immd))),
7030            (NaTy (EXTRACT_SUBREG
7031              (ResTy (INS
7032                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
7033                (ResTy VPR128:$Rn),
7034                NaImm:$Immd, StImm:$Immn)),
7035              sub_64))>;
7036
7037 def : Pat <(NaTy (vector_insert
7038              (NaTy VPR64:$src),
7039              (MidTy (vector_extract
7040                (NaTy VPR64:$Rn),
7041                (NaImm:$Immn))),
7042              (NaImm:$Immd))),
7043            (NaTy (EXTRACT_SUBREG
7044              (ResTy (INS
7045                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
7046                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
7047                NaImm:$Immd, NaImm:$Immn)),
7048              sub_64))>;
7049 }
7050
7051 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, neon_uimm2_bare,
7052                             neon_uimm1_bare, INSELs>;
7053 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, neon_uimm1_bare,
7054                             neon_uimm0_bare, INSELd>;
7055 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
7056                             neon_uimm3_bare, INSELb>;
7057 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
7058                             neon_uimm2_bare, INSELh>;
7059 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
7060                             neon_uimm1_bare, INSELs>;
7061 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, neon_uimm1_bare,
7062                             neon_uimm0_bare, INSELd>;
7063
7064 multiclass Neon_INS_elt_float_pattern<ValueType ResTy, ValueType NaTy,
7065                                       ValueType MidTy,
7066                                       RegisterClass OpFPR, Operand ResImm,
7067                                       SubRegIndex SubIndex, Instruction INS> {
7068 def : Pat <(ResTy (vector_insert
7069              (ResTy VPR128:$src),
7070              (MidTy OpFPR:$Rn),
7071              (ResImm:$Imm))),
7072            (INS (ResTy VPR128:$src),
7073              (ResTy (SUBREG_TO_REG (i64 0), OpFPR:$Rn, SubIndex)),
7074              ResImm:$Imm,
7075              (i64 0))>;
7076
7077 def : Pat <(NaTy (vector_insert
7078              (NaTy VPR64:$src),
7079              (MidTy OpFPR:$Rn),
7080              (ResImm:$Imm))),
7081            (NaTy (EXTRACT_SUBREG
7082              (ResTy (INS
7083                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
7084                (ResTy (SUBREG_TO_REG (i64 0), (MidTy OpFPR:$Rn), SubIndex)),
7085                ResImm:$Imm,
7086                (i64 0))),
7087              sub_64))>;
7088 }
7089
7090 defm : Neon_INS_elt_float_pattern<v4f32, v2f32, f32, FPR32, neon_uimm2_bare,
7091                                   sub_32, INSELs>;
7092 defm : Neon_INS_elt_float_pattern<v2f64, v1f64, f64, FPR64, neon_uimm1_bare,
7093                                   sub_64, INSELd>;
7094
7095 class NeonI_SMOV<string asmop, string Res, bit Q,
7096                  ValueType OpTy, ValueType eleTy,
7097                  Operand OpImm, RegisterClass ResGPR, ValueType ResTy>
7098   : NeonI_copy<Q, 0b0, 0b0101,
7099                (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
7100                asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
7101                [(set (ResTy ResGPR:$Rd),
7102                  (ResTy (sext_inreg
7103                    (ResTy (vector_extract
7104                      (OpTy VPR128:$Rn), (OpImm:$Imm))),
7105                    eleTy)))],
7106                NoItinerary> {
7107   bits<4> Imm;
7108 }
7109
7110 //Signed integer move (main, from element)
7111 def SMOVwb : NeonI_SMOV<"smov", "b", 0b0, v16i8, i8, neon_uimm4_bare,
7112                         GPR32, i32> {
7113   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
7114 }
7115 def SMOVwh : NeonI_SMOV<"smov", "h", 0b0, v8i16, i16, neon_uimm3_bare,
7116                         GPR32, i32> {
7117   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
7118 }
7119 def SMOVxb : NeonI_SMOV<"smov", "b", 0b1, v16i8, i8, neon_uimm4_bare,
7120                         GPR64, i64> {
7121   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
7122 }
7123 def SMOVxh : NeonI_SMOV<"smov", "h", 0b1, v8i16, i16, neon_uimm3_bare,
7124                         GPR64, i64> {
7125   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
7126 }
7127 def SMOVxs : NeonI_SMOV<"smov", "s", 0b1, v4i32, i32, neon_uimm2_bare,
7128                         GPR64, i64> {
7129   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
7130 }
7131
7132 multiclass Neon_SMOVx_pattern <ValueType StTy, ValueType NaTy,
7133                                ValueType eleTy, Operand StImm,  Operand NaImm,
7134                                Instruction SMOVI> {
7135   def : Pat<(i64 (sext_inreg
7136               (i64 (anyext
7137                 (i32 (vector_extract
7138                   (StTy VPR128:$Rn), (StImm:$Imm))))),
7139               eleTy)),
7140             (SMOVI VPR128:$Rn, StImm:$Imm)>;
7141
7142   def : Pat<(i64 (sext
7143               (i32 (vector_extract
7144                 (StTy VPR128:$Rn), (StImm:$Imm))))),
7145             (SMOVI VPR128:$Rn, StImm:$Imm)>;
7146
7147   def : Pat<(i64 (sext_inreg
7148               (i64 (vector_extract
7149                 (NaTy VPR64:$Rn), (NaImm:$Imm))),
7150               eleTy)),
7151             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7152               NaImm:$Imm)>;
7153
7154   def : Pat<(i64 (sext_inreg
7155               (i64 (anyext
7156                 (i32 (vector_extract
7157                   (NaTy VPR64:$Rn), (NaImm:$Imm))))),
7158               eleTy)),
7159             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7160               NaImm:$Imm)>;
7161
7162   def : Pat<(i64 (sext
7163               (i32 (vector_extract
7164                 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
7165             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7166               NaImm:$Imm)>;
7167 }
7168
7169 defm : Neon_SMOVx_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
7170                           neon_uimm3_bare, SMOVxb>;
7171 defm : Neon_SMOVx_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
7172                           neon_uimm2_bare, SMOVxh>;
7173 defm : Neon_SMOVx_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
7174                           neon_uimm1_bare, SMOVxs>;
7175
7176 class Neon_SMOVw_pattern <ValueType StTy, ValueType NaTy,
7177                           ValueType eleTy, Operand StImm,  Operand NaImm,
7178                           Instruction SMOVI>
7179   : Pat<(i32 (sext_inreg
7180           (i32 (vector_extract
7181             (NaTy VPR64:$Rn), (NaImm:$Imm))),
7182           eleTy)),
7183         (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7184           NaImm:$Imm)>;
7185
7186 def : Neon_SMOVw_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
7187                          neon_uimm3_bare, SMOVwb>;
7188 def : Neon_SMOVw_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
7189                          neon_uimm2_bare, SMOVwh>;
7190
7191 class NeonI_UMOV<string asmop, string Res, bit Q,
7192                  ValueType OpTy, Operand OpImm,
7193                  RegisterClass ResGPR, ValueType ResTy>
7194   : NeonI_copy<Q, 0b0, 0b0111,
7195                (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
7196                asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
7197                [(set (ResTy ResGPR:$Rd),
7198                   (ResTy (vector_extract
7199                     (OpTy VPR128:$Rn), (OpImm:$Imm))))],
7200                NoItinerary> {
7201   bits<4> Imm;
7202 }
7203
7204 //Unsigned integer move (main, from element)
7205 def UMOVwb : NeonI_UMOV<"umov", "b", 0b0, v16i8, neon_uimm4_bare,
7206                          GPR32, i32> {
7207   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
7208 }
7209 def UMOVwh : NeonI_UMOV<"umov", "h", 0b0, v8i16, neon_uimm3_bare,
7210                          GPR32, i32> {
7211   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
7212 }
7213 def UMOVws : NeonI_UMOV<"umov", "s", 0b0, v4i32, neon_uimm2_bare,
7214                          GPR32, i32> {
7215   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
7216 }
7217 def UMOVxd : NeonI_UMOV<"umov", "d", 0b1, v2i64, neon_uimm1_bare,
7218                          GPR64, i64> {
7219   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
7220 }
7221
7222 def : NeonInstAlias<"mov $Rd, $Rn.s[$Imm]",
7223                     (UMOVws GPR32:$Rd, VPR128:$Rn, neon_uimm2_bare:$Imm), 0>;
7224 def : NeonInstAlias<"mov $Rd, $Rn.d[$Imm]",
7225                     (UMOVxd GPR64:$Rd, VPR128:$Rn, neon_uimm1_bare:$Imm), 0>;
7226
7227 class Neon_UMOV_pattern <ValueType StTy, ValueType NaTy, ValueType ResTy,
7228                          Operand StImm,  Operand NaImm,
7229                          Instruction SMOVI>
7230   : Pat<(ResTy (vector_extract
7231           (NaTy VPR64:$Rn), NaImm:$Imm)),
7232         (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7233           NaImm:$Imm)>;
7234
7235 def : Neon_UMOV_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
7236                         neon_uimm3_bare, UMOVwb>;
7237 def : Neon_UMOV_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
7238                         neon_uimm2_bare, UMOVwh>;
7239 def : Neon_UMOV_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
7240                         neon_uimm1_bare, UMOVws>;
7241
7242 def : Pat<(i32 (and
7243             (i32 (vector_extract
7244               (v16i8 VPR128:$Rn), (neon_uimm4_bare:$Imm))),
7245             255)),
7246           (UMOVwb VPR128:$Rn, neon_uimm4_bare:$Imm)>;
7247
7248 def : Pat<(i32 (and
7249             (i32 (vector_extract
7250               (v8i16 VPR128:$Rn), (neon_uimm3_bare:$Imm))),
7251             65535)),
7252           (UMOVwh VPR128:$Rn, neon_uimm3_bare:$Imm)>;
7253
7254 def : Pat<(i64 (zext
7255             (i32 (vector_extract
7256               (v2i64 VPR128:$Rn), (neon_uimm1_bare:$Imm))))),
7257           (UMOVxd VPR128:$Rn, neon_uimm1_bare:$Imm)>;
7258
7259 def : Pat<(i32 (and
7260             (i32 (vector_extract
7261               (v8i8 VPR64:$Rn), (neon_uimm3_bare:$Imm))),
7262             255)),
7263           (UMOVwb (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
7264             neon_uimm3_bare:$Imm)>;
7265
7266 def : Pat<(i32 (and
7267             (i32 (vector_extract
7268               (v4i16 VPR64:$Rn), (neon_uimm2_bare:$Imm))),
7269             65535)),
7270           (UMOVwh (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
7271             neon_uimm2_bare:$Imm)>;
7272
7273 def : Pat<(i64 (zext
7274             (i32 (vector_extract
7275               (v1i64 VPR64:$Rn), (neon_uimm0_bare:$Imm))))),
7276           (UMOVxd (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
7277             neon_uimm0_bare:$Imm)>;
7278
7279 // Additional copy patterns for scalar types
7280 def : Pat<(i32 (vector_extract (v1i8 FPR8:$Rn), (i64 0))),
7281           (UMOVwb (v16i8
7282             (SUBREG_TO_REG (i64 0), FPR8:$Rn, sub_8)), (i64 0))>;
7283
7284 def : Pat<(i32 (vector_extract (v1i16 FPR16:$Rn), (i64 0))),
7285           (UMOVwh (v8i16
7286             (SUBREG_TO_REG (i64 0), FPR16:$Rn, sub_16)), (i64 0))>;
7287
7288 def : Pat<(i32 (vector_extract (v1i32 FPR32:$Rn), (i64 0))),
7289           (FMOVws FPR32:$Rn)>;
7290
7291 def : Pat<(i64 (vector_extract (v1i64 FPR64:$Rn), (i64 0))),
7292           (FMOVxd FPR64:$Rn)>;
7293
7294 def : Pat<(f64 (vector_extract (v1f64 FPR64:$Rn), (i64 0))),
7295           (f64 FPR64:$Rn)>;
7296
7297 def : Pat<(f32 (vector_extract (v1f32 FPR32:$Rn), (i64 0))),
7298           (f32 FPR32:$Rn)>;
7299
7300 def : Pat<(v1i8 (scalar_to_vector GPR32:$Rn)),
7301           (v1i8 (EXTRACT_SUBREG (v16i8
7302             (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
7303             sub_8))>;
7304
7305 def : Pat<(v1i16 (scalar_to_vector GPR32:$Rn)),
7306           (v1i16 (EXTRACT_SUBREG (v8i16
7307             (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
7308             sub_16))>;
7309
7310 def : Pat<(v1i32 (scalar_to_vector GPR32:$src)),
7311           (FMOVsw $src)>;
7312
7313 def : Pat<(v1i64 (scalar_to_vector GPR64:$src)),
7314           (FMOVdx $src)>;
7315
7316 def : Pat<(v1f32 (scalar_to_vector (f32 FPR32:$Rn))),
7317           (v1f32 FPR32:$Rn)>;
7318 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
7319           (v1f64 FPR64:$Rn)>;
7320
7321 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
7322           (FMOVdd $src)>;
7323
7324 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$src))),
7325           (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
7326                          (f64 FPR64:$src), sub_64)>;
7327
7328 class NeonI_DUP_Elt<bit Q, string asmop, string rdlane,  string rnlane,
7329                     RegisterOperand ResVPR, Operand OpImm>
7330   : NeonI_copy<Q, 0b0, 0b0000, (outs ResVPR:$Rd),
7331                (ins VPR128:$Rn, OpImm:$Imm),
7332                asmop # "\t$Rd" # rdlane # ", $Rn" # rnlane # "[$Imm]",
7333                [],
7334                NoItinerary> {
7335   bits<4> Imm;
7336 }
7337
7338 def DUPELT16b : NeonI_DUP_Elt<0b1, "dup", ".16b", ".b", VPR128,
7339                               neon_uimm4_bare> {
7340   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
7341 }
7342
7343 def DUPELT8h : NeonI_DUP_Elt<0b1, "dup", ".8h", ".h", VPR128,
7344                               neon_uimm3_bare> {
7345   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
7346 }
7347
7348 def DUPELT4s : NeonI_DUP_Elt<0b1, "dup", ".4s", ".s", VPR128,
7349                               neon_uimm2_bare> {
7350   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
7351 }
7352
7353 def DUPELT2d : NeonI_DUP_Elt<0b1, "dup", ".2d", ".d", VPR128,
7354                               neon_uimm1_bare> {
7355   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
7356 }
7357
7358 def DUPELT8b : NeonI_DUP_Elt<0b0, "dup", ".8b", ".b", VPR64,
7359                               neon_uimm4_bare> {
7360   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
7361 }
7362
7363 def DUPELT4h : NeonI_DUP_Elt<0b0, "dup", ".4h", ".h", VPR64,
7364                               neon_uimm3_bare> {
7365   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
7366 }
7367
7368 def DUPELT2s : NeonI_DUP_Elt<0b0, "dup", ".2s", ".s", VPR64,
7369                               neon_uimm2_bare> {
7370   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
7371 }
7372
7373 multiclass NeonI_DUP_Elt_pattern<Instruction DUPELT, ValueType ResTy,
7374                                        ValueType OpTy,ValueType NaTy,
7375                                        ValueType ExTy, Operand OpLImm,
7376                                        Operand OpNImm> {
7377 def  : Pat<(ResTy (Neon_vduplane (OpTy VPR128:$Rn), OpLImm:$Imm)),
7378         (ResTy (DUPELT (OpTy VPR128:$Rn), OpLImm:$Imm))>;
7379
7380 def : Pat<(ResTy (Neon_vduplane
7381             (NaTy VPR64:$Rn), OpNImm:$Imm)),
7382           (ResTy (DUPELT
7383             (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)), OpNImm:$Imm))>;
7384 }
7385 defm : NeonI_DUP_Elt_pattern<DUPELT16b, v16i8, v16i8, v8i8, v16i8,
7386                              neon_uimm4_bare, neon_uimm3_bare>;
7387 defm : NeonI_DUP_Elt_pattern<DUPELT8b, v8i8, v16i8, v8i8, v16i8,
7388                              neon_uimm4_bare, neon_uimm3_bare>;
7389 defm : NeonI_DUP_Elt_pattern<DUPELT8h, v8i16, v8i16, v4i16, v8i16,
7390                              neon_uimm3_bare, neon_uimm2_bare>;
7391 defm : NeonI_DUP_Elt_pattern<DUPELT4h, v4i16, v8i16, v4i16, v8i16,
7392                              neon_uimm3_bare, neon_uimm2_bare>;
7393 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4i32, v4i32, v2i32, v4i32,
7394                              neon_uimm2_bare, neon_uimm1_bare>;
7395 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2i32, v4i32, v2i32, v4i32,
7396                              neon_uimm2_bare, neon_uimm1_bare>;
7397 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2i64, v2i64, v1i64, v2i64,
7398                              neon_uimm1_bare, neon_uimm0_bare>;
7399 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4f32, v4f32, v2f32, v4f32,
7400                              neon_uimm2_bare, neon_uimm1_bare>;
7401 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2f32, v4f32, v2f32, v4f32,
7402                              neon_uimm2_bare, neon_uimm1_bare>;
7403 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2f64, v2f64, v1f64, v2f64,
7404                              neon_uimm1_bare, neon_uimm0_bare>;
7405
7406 def : Pat<(v2f32 (Neon_vdup (f32 FPR32:$Rn))),
7407           (v2f32 (DUPELT2s
7408             (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
7409             (i64 0)))>;
7410 def : Pat<(v4f32 (Neon_vdup (f32 FPR32:$Rn))),
7411           (v4f32 (DUPELT4s
7412             (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
7413             (i64 0)))>;
7414 def : Pat<(v2f64 (Neon_vdup (f64 FPR64:$Rn))),
7415           (v2f64 (DUPELT2d
7416             (SUBREG_TO_REG (i64 0), FPR64:$Rn, sub_64),
7417             (i64 0)))>;
7418
7419 class NeonI_DUP<bit Q, string asmop, string rdlane,
7420                 RegisterOperand ResVPR, ValueType ResTy,
7421                 RegisterClass OpGPR, ValueType OpTy>
7422   : NeonI_copy<Q, 0b0, 0b0001, (outs ResVPR:$Rd), (ins OpGPR:$Rn),
7423                asmop # "\t$Rd" # rdlane # ", $Rn",
7424                [(set (ResTy ResVPR:$Rd),
7425                  (ResTy (Neon_vdup (OpTy OpGPR:$Rn))))],
7426                NoItinerary>;
7427
7428 def DUP16b : NeonI_DUP<0b1, "dup", ".16b", VPR128, v16i8, GPR32, i32> {
7429   let Inst{20-16} = 0b00001;
7430   // bits 17-20 are unspecified, but should be set to zero.
7431 }
7432
7433 def DUP8h : NeonI_DUP<0b1, "dup", ".8h", VPR128, v8i16, GPR32, i32> {
7434   let Inst{20-16} = 0b00010;
7435   // bits 18-20 are unspecified, but should be set to zero.
7436 }
7437
7438 def DUP4s : NeonI_DUP<0b1, "dup", ".4s", VPR128, v4i32, GPR32, i32> {
7439   let Inst{20-16} = 0b00100;
7440   // bits 19-20 are unspecified, but should be set to zero.
7441 }
7442
7443 def DUP2d : NeonI_DUP<0b1, "dup", ".2d", VPR128, v2i64, GPR64, i64> {
7444   let Inst{20-16} = 0b01000;
7445   // bit 20 is unspecified, but should be set to zero.
7446 }
7447
7448 def DUP8b : NeonI_DUP<0b0, "dup", ".8b", VPR64, v8i8, GPR32, i32> {
7449   let Inst{20-16} = 0b00001;
7450   // bits 17-20 are unspecified, but should be set to zero.
7451 }
7452
7453 def DUP4h : NeonI_DUP<0b0, "dup", ".4h", VPR64, v4i16, GPR32, i32> {
7454   let Inst{20-16} = 0b00010;
7455   // bits 18-20 are unspecified, but should be set to zero.
7456 }
7457
7458 def DUP2s : NeonI_DUP<0b0, "dup", ".2s", VPR64, v2i32, GPR32, i32> {
7459   let Inst{20-16} = 0b00100;
7460   // bits 19-20 are unspecified, but should be set to zero.
7461 }
7462
7463 // patterns for CONCAT_VECTORS
7464 multiclass Concat_Vector_Pattern<ValueType ResTy, ValueType OpTy> {
7465 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), undef)),
7466           (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)>;
7467 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))),
7468           (INSELd
7469             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7470             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rm, sub_64)),
7471             (i64 1),
7472             (i64 0))>;
7473 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rn))),
7474           (DUPELT2d
7475             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7476             (i64 0))> ;
7477 }
7478
7479 defm : Concat_Vector_Pattern<v16i8, v8i8>;
7480 defm : Concat_Vector_Pattern<v8i16, v4i16>;
7481 defm : Concat_Vector_Pattern<v4i32, v2i32>;
7482 defm : Concat_Vector_Pattern<v2i64, v1i64>;
7483 defm : Concat_Vector_Pattern<v4f32, v2f32>;
7484 defm : Concat_Vector_Pattern<v2f64, v1f64>;
7485
7486 //patterns for EXTRACT_SUBVECTOR
7487 def : Pat<(v8i8 (extract_subvector (v16i8 VPR128:$Rn), (i64 0))),
7488           (v8i8 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7489 def : Pat<(v4i16 (extract_subvector (v8i16 VPR128:$Rn), (i64 0))),
7490           (v4i16 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7491 def : Pat<(v2i32 (extract_subvector (v4i32 VPR128:$Rn), (i64 0))),
7492           (v2i32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7493 def : Pat<(v1i64 (extract_subvector (v2i64 VPR128:$Rn), (i64 0))),
7494           (v1i64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7495 def : Pat<(v2f32 (extract_subvector (v4f32 VPR128:$Rn), (i64 0))),
7496           (v2f32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7497 def : Pat<(v1f64 (extract_subvector (v2f64 VPR128:$Rn), (i64 0))),
7498           (v1f64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7499
7500 class NeonI_REV<string asmop, string Res, bits<2> size, bit Q, bit U,
7501                 bits<5> opcode, RegisterOperand ResVPR, ValueType ResTy,
7502                 SDPatternOperator Neon_Rev>
7503   : NeonI_2VMisc<Q, U, size, opcode,
7504                (outs ResVPR:$Rd), (ins ResVPR:$Rn),
7505                asmop # "\t$Rd." # Res # ", $Rn." # Res,
7506                [(set (ResTy ResVPR:$Rd),
7507                   (ResTy (Neon_Rev (ResTy ResVPR:$Rn))))],
7508                NoItinerary> ;
7509
7510 def REV64_16b : NeonI_REV<"rev64", "16b", 0b00, 0b1, 0b0, 0b00000, VPR128,
7511                           v16i8, Neon_rev64>;
7512 def REV64_8h : NeonI_REV<"rev64", "8h", 0b01, 0b1, 0b0, 0b00000, VPR128,
7513                          v8i16, Neon_rev64>;
7514 def REV64_4s : NeonI_REV<"rev64", "4s", 0b10, 0b1, 0b0, 0b00000, VPR128,
7515                          v4i32, Neon_rev64>;
7516 def REV64_8b : NeonI_REV<"rev64", "8b", 0b00, 0b0, 0b0, 0b00000, VPR64,
7517                          v8i8, Neon_rev64>;
7518 def REV64_4h : NeonI_REV<"rev64", "4h", 0b01, 0b0, 0b0, 0b00000, VPR64,
7519                          v4i16, Neon_rev64>;
7520 def REV64_2s : NeonI_REV<"rev64", "2s", 0b10, 0b0, 0b0, 0b00000, VPR64,
7521                          v2i32, Neon_rev64>;
7522
7523 def : Pat<(v4f32 (Neon_rev64 (v4f32 VPR128:$Rn))), (REV64_4s VPR128:$Rn)>;
7524 def : Pat<(v2f32 (Neon_rev64 (v2f32 VPR64:$Rn))), (REV64_2s VPR64:$Rn)>;
7525
7526 def REV32_16b : NeonI_REV<"rev32", "16b", 0b00, 0b1, 0b1, 0b00000, VPR128,
7527                           v16i8, Neon_rev32>;
7528 def REV32_8h : NeonI_REV<"rev32", "8h", 0b01, 0b1, 0b1, 0b00000, VPR128,
7529                           v8i16, Neon_rev32>;
7530 def REV32_8b : NeonI_REV<"rev32", "8b", 0b00, 0b0, 0b1, 0b00000, VPR64,
7531                          v8i8, Neon_rev32>;
7532 def REV32_4h : NeonI_REV<"rev32", "4h", 0b01, 0b0, 0b1, 0b00000, VPR64,
7533                          v4i16, Neon_rev32>;
7534
7535 def REV16_16b : NeonI_REV<"rev16", "16b", 0b00, 0b1, 0b0, 0b00001, VPR128,
7536                           v16i8, Neon_rev16>;
7537 def REV16_8b : NeonI_REV<"rev16", "8b", 0b00, 0b0, 0b0, 0b00001, VPR64,
7538                          v8i8, Neon_rev16>;
7539
7540 multiclass NeonI_PairwiseAdd<string asmop, bit U, bits<5> opcode,
7541                              SDPatternOperator Neon_Padd> {
7542   def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7543                            (outs VPR128:$Rd), (ins VPR128:$Rn),
7544                            asmop # "\t$Rd.8h, $Rn.16b",
7545                            [(set (v8i16 VPR128:$Rd),
7546                               (v8i16 (Neon_Padd (v16i8 VPR128:$Rn))))],
7547                            NoItinerary>;
7548
7549   def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7550                           (outs VPR64:$Rd), (ins VPR64:$Rn),
7551                           asmop # "\t$Rd.4h, $Rn.8b",
7552                           [(set (v4i16 VPR64:$Rd),
7553                              (v4i16 (Neon_Padd (v8i8 VPR64:$Rn))))],
7554                           NoItinerary>;
7555
7556   def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7557                            (outs VPR128:$Rd), (ins VPR128:$Rn),
7558                            asmop # "\t$Rd.4s, $Rn.8h",
7559                            [(set (v4i32 VPR128:$Rd),
7560                               (v4i32 (Neon_Padd (v8i16 VPR128:$Rn))))],
7561                            NoItinerary>;
7562
7563   def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7564                           (outs VPR64:$Rd), (ins VPR64:$Rn),
7565                           asmop # "\t$Rd.2s, $Rn.4h",
7566                           [(set (v2i32 VPR64:$Rd),
7567                              (v2i32 (Neon_Padd (v4i16 VPR64:$Rn))))],
7568                           NoItinerary>;
7569
7570   def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7571                            (outs VPR128:$Rd), (ins VPR128:$Rn),
7572                            asmop # "\t$Rd.2d, $Rn.4s",
7573                            [(set (v2i64 VPR128:$Rd),
7574                               (v2i64 (Neon_Padd (v4i32 VPR128:$Rn))))],
7575                            NoItinerary>;
7576
7577   def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7578                           (outs VPR64:$Rd), (ins VPR64:$Rn),
7579                           asmop # "\t$Rd.1d, $Rn.2s",
7580                           [(set (v1i64 VPR64:$Rd),
7581                              (v1i64 (Neon_Padd (v2i32 VPR64:$Rn))))],
7582                           NoItinerary>;
7583 }
7584
7585 defm SADDLP : NeonI_PairwiseAdd<"saddlp", 0b0, 0b00010,
7586                                 int_arm_neon_vpaddls>;
7587 defm UADDLP : NeonI_PairwiseAdd<"uaddlp", 0b1, 0b00010,
7588                                 int_arm_neon_vpaddlu>;
7589
7590 multiclass NeonI_PairwiseAddAcc<string asmop, bit U, bits<5> opcode,
7591                              SDPatternOperator Neon_Padd> {
7592   let Constraints = "$src = $Rd" in {
7593     def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7594                              (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7595                              asmop # "\t$Rd.8h, $Rn.16b",
7596                              [(set (v8i16 VPR128:$Rd),
7597                                 (v8i16 (Neon_Padd
7598                                   (v8i16 VPR128:$src), (v16i8 VPR128:$Rn))))],
7599                              NoItinerary>;
7600
7601     def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7602                             (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7603                             asmop # "\t$Rd.4h, $Rn.8b",
7604                             [(set (v4i16 VPR64:$Rd),
7605                                (v4i16 (Neon_Padd
7606                                  (v4i16 VPR64:$src), (v8i8 VPR64:$Rn))))],
7607                             NoItinerary>;
7608
7609     def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7610                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7611                             asmop # "\t$Rd.4s, $Rn.8h",
7612                             [(set (v4i32 VPR128:$Rd),
7613                                (v4i32 (Neon_Padd
7614                                  (v4i32 VPR128:$src), (v8i16 VPR128:$Rn))))],
7615                             NoItinerary>;
7616
7617     def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7618                             (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7619                             asmop # "\t$Rd.2s, $Rn.4h",
7620                             [(set (v2i32 VPR64:$Rd),
7621                                (v2i32 (Neon_Padd
7622                                  (v2i32 VPR64:$src), (v4i16 VPR64:$Rn))))],
7623                             NoItinerary>;
7624
7625     def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7626                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7627                             asmop # "\t$Rd.2d, $Rn.4s",
7628                             [(set (v2i64 VPR128:$Rd),
7629                                (v2i64 (Neon_Padd
7630                                  (v2i64 VPR128:$src), (v4i32 VPR128:$Rn))))],
7631                             NoItinerary>;
7632
7633     def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7634                             (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7635                             asmop # "\t$Rd.1d, $Rn.2s",
7636                             [(set (v1i64 VPR64:$Rd),
7637                                (v1i64 (Neon_Padd
7638                                  (v1i64 VPR64:$src), (v2i32 VPR64:$Rn))))],
7639                             NoItinerary>;
7640   }
7641 }
7642
7643 defm SADALP : NeonI_PairwiseAddAcc<"sadalp", 0b0, 0b00110,
7644                                    int_arm_neon_vpadals>;
7645 defm UADALP : NeonI_PairwiseAddAcc<"uadalp", 0b1, 0b00110,
7646                                    int_arm_neon_vpadalu>;
7647
7648 multiclass NeonI_2VMisc_BHSDsize_1Arg<string asmop, bit U, bits<5> opcode> {
7649   def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7650                          (outs VPR128:$Rd), (ins VPR128:$Rn),
7651                          asmop # "\t$Rd.16b, $Rn.16b",
7652                          [], NoItinerary>;
7653
7654   def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7655                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7656                         asmop # "\t$Rd.8h, $Rn.8h",
7657                         [], NoItinerary>;
7658
7659   def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7660                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7661                         asmop # "\t$Rd.4s, $Rn.4s",
7662                         [], NoItinerary>;
7663
7664   def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7665                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7666                         asmop # "\t$Rd.2d, $Rn.2d",
7667                         [], NoItinerary>;
7668
7669   def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7670                          (outs VPR64:$Rd), (ins VPR64:$Rn),
7671                          asmop # "\t$Rd.8b, $Rn.8b",
7672                          [], NoItinerary>;
7673
7674   def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7675                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7676                         asmop # "\t$Rd.4h, $Rn.4h",
7677                         [], NoItinerary>;
7678
7679   def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7680                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7681                         asmop # "\t$Rd.2s, $Rn.2s",
7682                         [], NoItinerary>;
7683 }
7684
7685 defm SQABS : NeonI_2VMisc_BHSDsize_1Arg<"sqabs", 0b0, 0b00111>;
7686 defm SQNEG : NeonI_2VMisc_BHSDsize_1Arg<"sqneg", 0b1, 0b00111>;
7687 defm ABS : NeonI_2VMisc_BHSDsize_1Arg<"abs", 0b0, 0b01011>;
7688 defm NEG : NeonI_2VMisc_BHSDsize_1Arg<"neg", 0b1, 0b01011>;
7689
7690 multiclass NeonI_2VMisc_BHSD_1Arg_Pattern<string Prefix,
7691                                           SDPatternOperator Neon_Op> {
7692   def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$Rn))),
7693             (v16i8 (!cast<Instruction>(Prefix # 16b) (v16i8 VPR128:$Rn)))>;
7694
7695   def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$Rn))),
7696             (v8i16 (!cast<Instruction>(Prefix # 8h) (v8i16 VPR128:$Rn)))>;
7697
7698   def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$Rn))),
7699             (v4i32 (!cast<Instruction>(Prefix # 4s) (v4i32 VPR128:$Rn)))>;
7700
7701   def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$Rn))),
7702             (v2i64 (!cast<Instruction>(Prefix # 2d) (v2i64 VPR128:$Rn)))>;
7703
7704   def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$Rn))),
7705             (v8i8 (!cast<Instruction>(Prefix # 8b) (v8i8 VPR64:$Rn)))>;
7706
7707   def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$Rn))),
7708             (v4i16 (!cast<Instruction>(Prefix # 4h) (v4i16 VPR64:$Rn)))>;
7709
7710   def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$Rn))),
7711             (v2i32 (!cast<Instruction>(Prefix # 2s) (v2i32 VPR64:$Rn)))>;
7712 }
7713
7714 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQABS", int_arm_neon_vqabs>;
7715 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQNEG", int_arm_neon_vqneg>;
7716 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"ABS", int_arm_neon_vabs>;
7717
7718 def : Pat<(v16i8 (sub
7719             (v16i8 Neon_AllZero),
7720             (v16i8 VPR128:$Rn))),
7721           (v16i8 (NEG16b (v16i8 VPR128:$Rn)))>;
7722 def : Pat<(v8i8 (sub
7723             (v8i8 Neon_AllZero),
7724             (v8i8 VPR64:$Rn))),
7725           (v8i8 (NEG8b (v8i8 VPR64:$Rn)))>;
7726 def : Pat<(v8i16 (sub
7727             (v8i16 (bitconvert (v16i8 Neon_AllZero))),
7728             (v8i16 VPR128:$Rn))),
7729           (v8i16 (NEG8h (v8i16 VPR128:$Rn)))>;
7730 def : Pat<(v4i16 (sub
7731             (v4i16 (bitconvert (v8i8 Neon_AllZero))),
7732             (v4i16 VPR64:$Rn))),
7733           (v4i16 (NEG4h (v4i16 VPR64:$Rn)))>;
7734 def : Pat<(v4i32 (sub
7735             (v4i32 (bitconvert (v16i8 Neon_AllZero))),
7736             (v4i32 VPR128:$Rn))),
7737           (v4i32 (NEG4s (v4i32 VPR128:$Rn)))>;
7738 def : Pat<(v2i32 (sub
7739             (v2i32 (bitconvert (v8i8 Neon_AllZero))),
7740             (v2i32 VPR64:$Rn))),
7741           (v2i32 (NEG2s (v2i32 VPR64:$Rn)))>;
7742 def : Pat<(v2i64 (sub
7743             (v2i64 (bitconvert (v16i8 Neon_AllZero))),
7744             (v2i64 VPR128:$Rn))),
7745           (v2i64 (NEG2d (v2i64 VPR128:$Rn)))>;
7746
7747 multiclass NeonI_2VMisc_BHSDsize_2Args<string asmop, bit U, bits<5> opcode> {
7748   let Constraints = "$src = $Rd" in {
7749     def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7750                            (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7751                            asmop # "\t$Rd.16b, $Rn.16b",
7752                            [], NoItinerary>;
7753
7754     def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7755                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7756                           asmop # "\t$Rd.8h, $Rn.8h",
7757                           [], NoItinerary>;
7758
7759     def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7760                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7761                           asmop # "\t$Rd.4s, $Rn.4s",
7762                           [], NoItinerary>;
7763
7764     def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7765                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7766                           asmop # "\t$Rd.2d, $Rn.2d",
7767                           [], NoItinerary>;
7768
7769     def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7770                           (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7771                           asmop # "\t$Rd.8b, $Rn.8b",
7772                           [], NoItinerary>;
7773
7774     def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7775                           (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7776                           asmop # "\t$Rd.4h, $Rn.4h",
7777                           [], NoItinerary>;
7778
7779     def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7780                           (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7781                           asmop # "\t$Rd.2s, $Rn.2s",
7782                           [], NoItinerary>;
7783   }
7784 }
7785
7786 defm SUQADD : NeonI_2VMisc_BHSDsize_2Args<"suqadd", 0b0, 0b00011>;
7787 defm USQADD : NeonI_2VMisc_BHSDsize_2Args<"usqadd", 0b1, 0b00011>;
7788
7789 multiclass NeonI_2VMisc_BHSD_2Args_Pattern<string Prefix,
7790                                            SDPatternOperator Neon_Op> {
7791   def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$src), (v16i8 VPR128:$Rn))),
7792             (v16i8 (!cast<Instruction>(Prefix # 16b)
7793               (v16i8 VPR128:$src), (v16i8 VPR128:$Rn)))>;
7794
7795   def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$src), (v8i16 VPR128:$Rn))),
7796             (v8i16 (!cast<Instruction>(Prefix # 8h)
7797               (v8i16 VPR128:$src), (v8i16 VPR128:$Rn)))>;
7798
7799   def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$src), (v4i32 VPR128:$Rn))),
7800             (v4i32 (!cast<Instruction>(Prefix # 4s)
7801               (v4i32 VPR128:$src), (v4i32 VPR128:$Rn)))>;
7802
7803   def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$src), (v2i64 VPR128:$Rn))),
7804             (v2i64 (!cast<Instruction>(Prefix # 2d)
7805               (v2i64 VPR128:$src), (v2i64 VPR128:$Rn)))>;
7806
7807   def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$src), (v8i8 VPR64:$Rn))),
7808             (v8i8 (!cast<Instruction>(Prefix # 8b)
7809               (v8i8 VPR64:$src), (v8i8 VPR64:$Rn)))>;
7810
7811   def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$src), (v4i16 VPR64:$Rn))),
7812             (v4i16 (!cast<Instruction>(Prefix # 4h)
7813               (v4i16 VPR64:$src), (v4i16 VPR64:$Rn)))>;
7814
7815   def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$src), (v2i32 VPR64:$Rn))),
7816             (v2i32 (!cast<Instruction>(Prefix # 2s)
7817               (v2i32 VPR64:$src), (v2i32 VPR64:$Rn)))>;
7818 }
7819
7820 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"SUQADD", int_aarch64_neon_suqadd>;
7821 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"USQADD", int_aarch64_neon_usqadd>;
7822
7823 multiclass NeonI_2VMisc_BHSsizes<string asmop, bit U,
7824                           SDPatternOperator Neon_Op> {
7825   def 16b : NeonI_2VMisc<0b1, U, 0b00, 0b00100,
7826                          (outs VPR128:$Rd), (ins VPR128:$Rn),
7827                          asmop # "\t$Rd.16b, $Rn.16b",
7828                          [(set (v16i8 VPR128:$Rd),
7829                             (v16i8 (Neon_Op (v16i8 VPR128:$Rn))))],
7830                          NoItinerary>;
7831
7832   def 8h : NeonI_2VMisc<0b1, U, 0b01, 0b00100,
7833                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7834                         asmop # "\t$Rd.8h, $Rn.8h",
7835                         [(set (v8i16 VPR128:$Rd),
7836                            (v8i16 (Neon_Op (v8i16 VPR128:$Rn))))],
7837                         NoItinerary>;
7838
7839   def 4s : NeonI_2VMisc<0b1, U, 0b10, 0b00100,
7840                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7841                         asmop # "\t$Rd.4s, $Rn.4s",
7842                         [(set (v4i32 VPR128:$Rd),
7843                            (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
7844                         NoItinerary>;
7845
7846   def 8b : NeonI_2VMisc<0b0, U, 0b00, 0b00100,
7847                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7848                         asmop # "\t$Rd.8b, $Rn.8b",
7849                         [(set (v8i8 VPR64:$Rd),
7850                            (v8i8 (Neon_Op (v8i8 VPR64:$Rn))))],
7851                         NoItinerary>;
7852
7853   def 4h : NeonI_2VMisc<0b0, U, 0b01, 0b00100,
7854                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7855                         asmop # "\t$Rd.4h, $Rn.4h",
7856                         [(set (v4i16 VPR64:$Rd),
7857                            (v4i16 (Neon_Op (v4i16 VPR64:$Rn))))],
7858                         NoItinerary>;
7859
7860   def 2s : NeonI_2VMisc<0b0, U, 0b10, 0b00100,
7861                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7862                         asmop # "\t$Rd.2s, $Rn.2s",
7863                         [(set (v2i32 VPR64:$Rd),
7864                            (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
7865                         NoItinerary>;
7866 }
7867
7868 defm CLS : NeonI_2VMisc_BHSsizes<"cls", 0b0, int_arm_neon_vcls>;
7869 defm CLZ : NeonI_2VMisc_BHSsizes<"clz", 0b1, ctlz>;
7870
7871 multiclass NeonI_2VMisc_Bsize<string asmop, bit U, bits<2> size,
7872                               bits<5> Opcode> {
7873   def 16b : NeonI_2VMisc<0b1, U, size, Opcode,
7874                          (outs VPR128:$Rd), (ins VPR128:$Rn),
7875                          asmop # "\t$Rd.16b, $Rn.16b",
7876                          [], NoItinerary>;
7877
7878   def 8b : NeonI_2VMisc<0b0, U, size, Opcode,
7879                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7880                         asmop # "\t$Rd.8b, $Rn.8b",
7881                         [], NoItinerary>;
7882 }
7883
7884 defm CNT : NeonI_2VMisc_Bsize<"cnt", 0b0, 0b00, 0b00101>;
7885 defm NOT : NeonI_2VMisc_Bsize<"not", 0b1, 0b00, 0b00101>;
7886 defm RBIT : NeonI_2VMisc_Bsize<"rbit", 0b1, 0b01, 0b00101>;
7887
7888 def : NeonInstAlias<"mvn $Rd.16b, $Rn.16b",
7889                     (NOT16b VPR128:$Rd, VPR128:$Rn), 0>;
7890 def : NeonInstAlias<"mvn $Rd.8b, $Rn.8b",
7891                     (NOT8b VPR64:$Rd, VPR64:$Rn), 0>;
7892
7893 def : Pat<(v16i8 (ctpop (v16i8 VPR128:$Rn))),
7894           (v16i8 (CNT16b (v16i8 VPR128:$Rn)))>;
7895 def : Pat<(v8i8 (ctpop (v8i8 VPR64:$Rn))),
7896           (v8i8 (CNT8b (v8i8 VPR64:$Rn)))>;
7897
7898 def : Pat<(v16i8 (xor
7899             (v16i8 VPR128:$Rn),
7900             (v16i8 Neon_AllOne))),
7901           (v16i8 (NOT16b (v16i8 VPR128:$Rn)))>;
7902 def : Pat<(v8i8 (xor
7903             (v8i8 VPR64:$Rn),
7904             (v8i8 Neon_AllOne))),
7905           (v8i8 (NOT8b (v8i8 VPR64:$Rn)))>;
7906 def : Pat<(v8i16 (xor
7907             (v8i16 VPR128:$Rn),
7908             (v8i16 (bitconvert (v16i8 Neon_AllOne))))),
7909           (NOT16b VPR128:$Rn)>;
7910 def : Pat<(v4i16 (xor
7911             (v4i16 VPR64:$Rn),
7912             (v4i16 (bitconvert (v8i8 Neon_AllOne))))),
7913           (NOT8b VPR64:$Rn)>;
7914 def : Pat<(v4i32 (xor
7915             (v4i32 VPR128:$Rn),
7916             (v4i32 (bitconvert (v16i8 Neon_AllOne))))),
7917           (NOT16b VPR128:$Rn)>;
7918 def : Pat<(v2i32 (xor
7919             (v2i32 VPR64:$Rn),
7920             (v2i32 (bitconvert (v8i8 Neon_AllOne))))),
7921           (NOT8b VPR64:$Rn)>;
7922 def : Pat<(v2i64 (xor
7923             (v2i64 VPR128:$Rn),
7924             (v2i64 (bitconvert (v16i8 Neon_AllOne))))),
7925           (NOT16b VPR128:$Rn)>;
7926
7927 def : Pat<(v16i8 (int_aarch64_neon_rbit (v16i8 VPR128:$Rn))),
7928           (v16i8 (RBIT16b (v16i8 VPR128:$Rn)))>;
7929 def : Pat<(v8i8 (int_aarch64_neon_rbit (v8i8 VPR64:$Rn))),
7930           (v8i8 (RBIT8b (v8i8 VPR64:$Rn)))>;
7931
7932 multiclass NeonI_2VMisc_SDsizes<string asmop, bit U, bits<5> opcode,
7933                                 SDPatternOperator Neon_Op> {
7934   def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7935                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7936                         asmop # "\t$Rd.4s, $Rn.4s",
7937                         [(set (v4f32 VPR128:$Rd),
7938                            (v4f32 (Neon_Op (v4f32 VPR128:$Rn))))],
7939                         NoItinerary>;
7940
7941   def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7942                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7943                         asmop # "\t$Rd.2d, $Rn.2d",
7944                         [(set (v2f64 VPR128:$Rd),
7945                            (v2f64 (Neon_Op (v2f64 VPR128:$Rn))))],
7946                         NoItinerary>;
7947
7948   def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7949                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7950                         asmop # "\t$Rd.2s, $Rn.2s",
7951                         [(set (v2f32 VPR64:$Rd),
7952                            (v2f32 (Neon_Op (v2f32 VPR64:$Rn))))],
7953                         NoItinerary>;
7954 }
7955
7956 defm FABS : NeonI_2VMisc_SDsizes<"fabs", 0b0, 0b01111, fabs>;
7957 defm FNEG : NeonI_2VMisc_SDsizes<"fneg", 0b1, 0b01111, fneg>;
7958
7959 multiclass NeonI_2VMisc_HSD_Narrow<string asmop, bit U, bits<5> opcode> {
7960   def 8h8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7961                           (outs VPR64:$Rd), (ins VPR128:$Rn),
7962                           asmop # "\t$Rd.8b, $Rn.8h",
7963                           [], NoItinerary>;
7964
7965   def 4s4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7966                           (outs VPR64:$Rd), (ins VPR128:$Rn),
7967                           asmop # "\t$Rd.4h, $Rn.4s",
7968                           [], NoItinerary>;
7969
7970   def 2d2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7971                           (outs VPR64:$Rd), (ins VPR128:$Rn),
7972                           asmop # "\t$Rd.2s, $Rn.2d",
7973                           [], NoItinerary>;
7974
7975   let Constraints = "$Rd = $src" in {
7976     def 8h16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7977                              (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7978                              asmop # "2\t$Rd.16b, $Rn.8h",
7979                              [], NoItinerary>;
7980
7981     def 4s8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7982                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7983                             asmop # "2\t$Rd.8h, $Rn.4s",
7984                             [], NoItinerary>;
7985
7986     def 2d4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7987                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7988                             asmop # "2\t$Rd.4s, $Rn.2d",
7989                             [], NoItinerary>;
7990   }
7991 }
7992
7993 defm XTN : NeonI_2VMisc_HSD_Narrow<"xtn", 0b0, 0b10010>;
7994 defm SQXTUN : NeonI_2VMisc_HSD_Narrow<"sqxtun", 0b1, 0b10010>;
7995 defm SQXTN : NeonI_2VMisc_HSD_Narrow<"sqxtn", 0b0, 0b10100>;
7996 defm UQXTN : NeonI_2VMisc_HSD_Narrow<"uqxtn", 0b1, 0b10100>;
7997
7998 multiclass NeonI_2VMisc_Narrow_Patterns<string Prefix,
7999                                         SDPatternOperator Neon_Op> {
8000   def : Pat<(v8i8 (Neon_Op (v8i16 VPR128:$Rn))),
8001             (v8i8 (!cast<Instruction>(Prefix # 8h8b) (v8i16 VPR128:$Rn)))>;
8002
8003   def : Pat<(v4i16 (Neon_Op (v4i32 VPR128:$Rn))),
8004             (v4i16 (!cast<Instruction>(Prefix # 4s4h) (v4i32 VPR128:$Rn)))>;
8005
8006   def : Pat<(v2i32 (Neon_Op (v2i64 VPR128:$Rn))),
8007             (v2i32 (!cast<Instruction>(Prefix # 2d2s) (v2i64 VPR128:$Rn)))>;
8008
8009   def : Pat<(v16i8 (concat_vectors
8010               (v8i8 VPR64:$src),
8011               (v8i8 (Neon_Op (v8i16 VPR128:$Rn))))),
8012             (!cast<Instruction>(Prefix # 8h16b)
8013               (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8014               VPR128:$Rn)>;
8015
8016   def : Pat<(v8i16 (concat_vectors
8017               (v4i16 VPR64:$src),
8018               (v4i16 (Neon_Op (v4i32 VPR128:$Rn))))),
8019             (!cast<Instruction>(Prefix # 4s8h)
8020               (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8021               VPR128:$Rn)>;
8022
8023   def : Pat<(v4i32 (concat_vectors
8024               (v2i32 VPR64:$src),
8025               (v2i32 (Neon_Op (v2i64 VPR128:$Rn))))),
8026             (!cast<Instruction>(Prefix # 2d4s)
8027               (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8028               VPR128:$Rn)>;
8029 }
8030
8031 defm : NeonI_2VMisc_Narrow_Patterns<"XTN", trunc>;
8032 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTUN", int_arm_neon_vqmovnsu>;
8033 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTN", int_arm_neon_vqmovns>;
8034 defm : NeonI_2VMisc_Narrow_Patterns<"UQXTN", int_arm_neon_vqmovnu>;
8035
8036 multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> {
8037   def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8038                           (outs VPR128:$Rd),
8039                           (ins VPR64:$Rn, uimm_exact8:$Imm),
8040                           asmop # "\t$Rd.8h, $Rn.8b, $Imm",
8041                           [], NoItinerary>;
8042
8043   def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8044                           (outs VPR128:$Rd),
8045                           (ins VPR64:$Rn, uimm_exact16:$Imm),
8046                           asmop # "\t$Rd.4s, $Rn.4h, $Imm",
8047                           [], NoItinerary>;
8048
8049   def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
8050                           (outs VPR128:$Rd),
8051                           (ins VPR64:$Rn, uimm_exact32:$Imm),
8052                           asmop # "\t$Rd.2d, $Rn.2s, $Imm",
8053                           [], NoItinerary>;
8054
8055   def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8056                           (outs VPR128:$Rd),
8057                           (ins VPR128:$Rn, uimm_exact8:$Imm),
8058                           asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
8059                           [], NoItinerary>;
8060
8061   def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8062                           (outs VPR128:$Rd),
8063                           (ins VPR128:$Rn, uimm_exact16:$Imm),
8064                           asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
8065                           [], NoItinerary>;
8066
8067   def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
8068                           (outs VPR128:$Rd),
8069                           (ins VPR128:$Rn, uimm_exact32:$Imm),
8070                           asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
8071                           [], NoItinerary>;
8072 }
8073
8074 defm SHLL : NeonI_2VMisc_SHIFT<"shll", 0b1, 0b10011>;
8075
8076 class NeonI_SHLL_Patterns<ValueType OpTy, ValueType DesTy,
8077                           SDPatternOperator ExtOp, Operand Neon_Imm,
8078                           string suffix>
8079   : Pat<(DesTy (shl
8080           (DesTy (ExtOp (OpTy VPR64:$Rn))),
8081             (DesTy (Neon_vdup
8082               (i32 Neon_Imm:$Imm))))),
8083         (!cast<Instruction>("SHLL" # suffix) VPR64:$Rn, Neon_Imm:$Imm)>;
8084
8085 class NeonI_SHLL_High_Patterns<ValueType OpTy, ValueType DesTy,
8086                                SDPatternOperator ExtOp, Operand Neon_Imm,
8087                                string suffix, PatFrag GetHigh>
8088   : Pat<(DesTy (shl
8089           (DesTy (ExtOp
8090             (OpTy (GetHigh VPR128:$Rn)))),
8091               (DesTy (Neon_vdup
8092                 (i32 Neon_Imm:$Imm))))),
8093         (!cast<Instruction>("SHLL" # suffix) VPR128:$Rn, Neon_Imm:$Imm)>;
8094
8095 def : NeonI_SHLL_Patterns<v8i8, v8i16, zext, uimm_exact8, "8b8h">;
8096 def : NeonI_SHLL_Patterns<v8i8, v8i16, sext, uimm_exact8, "8b8h">;
8097 def : NeonI_SHLL_Patterns<v4i16, v4i32, zext, uimm_exact16, "4h4s">;
8098 def : NeonI_SHLL_Patterns<v4i16, v4i32, sext, uimm_exact16, "4h4s">;
8099 def : NeonI_SHLL_Patterns<v2i32, v2i64, zext, uimm_exact32, "2s2d">;
8100 def : NeonI_SHLL_Patterns<v2i32, v2i64, sext, uimm_exact32, "2s2d">;
8101 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, zext, uimm_exact8, "16b8h",
8102                                Neon_High16B>;
8103 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, sext, uimm_exact8, "16b8h",
8104                                Neon_High16B>;
8105 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, zext, uimm_exact16, "8h4s",
8106                                Neon_High8H>;
8107 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, sext, uimm_exact16, "8h4s",
8108                                Neon_High8H>;
8109 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, zext, uimm_exact32, "4s2d",
8110                                Neon_High4S>;
8111 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, sext, uimm_exact32, "4s2d",
8112                                Neon_High4S>;
8113
8114 multiclass NeonI_2VMisc_SD_Narrow<string asmop, bit U, bits<5> opcode> {
8115   def 4s4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8116                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8117                           asmop # "\t$Rd.4h, $Rn.4s",
8118                           [], NoItinerary>;
8119
8120   def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8121                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8122                           asmop # "\t$Rd.2s, $Rn.2d",
8123                           [], NoItinerary>;
8124
8125   let Constraints = "$src = $Rd" in {
8126     def 4s8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8127                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8128                             asmop # "2\t$Rd.8h, $Rn.4s",
8129                             [], NoItinerary>;
8130
8131     def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8132                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8133                             asmop # "2\t$Rd.4s, $Rn.2d",
8134                             [], NoItinerary>;
8135   }
8136 }
8137
8138 defm FCVTN : NeonI_2VMisc_SD_Narrow<"fcvtn", 0b0, 0b10110>;
8139
8140 multiclass NeonI_2VMisc_Narrow_Pattern<string prefix,
8141                                        SDPatternOperator f32_to_f16_Op,
8142                                        SDPatternOperator f64_to_f32_Op> {
8143
8144   def : Pat<(v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))),
8145               (!cast<Instruction>(prefix # "4s4h") (v4f32 VPR128:$Rn))>;
8146
8147   def : Pat<(v8i16 (concat_vectors
8148                 (v4i16 VPR64:$src),
8149                 (v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))))),
8150                   (!cast<Instruction>(prefix # "4s8h")
8151                     (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8152                     (v4f32 VPR128:$Rn))>;
8153
8154   def : Pat<(v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))),
8155             (!cast<Instruction>(prefix # "2d2s") (v2f64 VPR128:$Rn))>;
8156
8157   def : Pat<(v4f32 (concat_vectors
8158               (v2f32 VPR64:$src),
8159               (v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))))),
8160                 (!cast<Instruction>(prefix # "2d4s")
8161                   (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8162                   (v2f64 VPR128:$Rn))>;
8163 }
8164
8165 defm : NeonI_2VMisc_Narrow_Pattern<"FCVTN", int_arm_neon_vcvtfp2hf, fround>;
8166
8167 multiclass NeonI_2VMisc_D_Narrow<string asmop, string prefix, bit U,
8168                                  bits<5> opcode> {
8169   def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8170                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8171                           asmop # "\t$Rd.2s, $Rn.2d",
8172                           [], NoItinerary>;
8173
8174   def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8175                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8176                           asmop # "2\t$Rd.4s, $Rn.2d",
8177                           [], NoItinerary> {
8178     let Constraints = "$src = $Rd";
8179   }
8180
8181   def : Pat<(v2f32 (int_aarch64_neon_fcvtxn (v2f64 VPR128:$Rn))),
8182             (!cast<Instruction>(prefix # "2d2s") VPR128:$Rn)>;
8183
8184   def : Pat<(v4f32 (concat_vectors
8185               (v2f32 VPR64:$src),
8186               (v2f32 (int_aarch64_neon_fcvtxn (v2f64 VPR128:$Rn))))),
8187             (!cast<Instruction>(prefix # "2d4s")
8188                (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8189                VPR128:$Rn)>;
8190 }
8191
8192 defm FCVTXN : NeonI_2VMisc_D_Narrow<"fcvtxn","FCVTXN", 0b1, 0b10110>;
8193
8194 def Neon_High4Float : PatFrag<(ops node:$in),
8195                               (extract_subvector (v4f32 node:$in), (iPTR 2))>;
8196
8197 multiclass NeonI_2VMisc_HS_Extend<string asmop, bit U, bits<5> opcode> {
8198   def 4h4s : NeonI_2VMisc<0b0, U, 0b00, opcode,
8199                           (outs VPR128:$Rd), (ins VPR64:$Rn),
8200                           asmop # "\t$Rd.4s, $Rn.4h",
8201                           [], NoItinerary>;
8202
8203   def 2s2d : NeonI_2VMisc<0b0, U, 0b01, opcode,
8204                           (outs VPR128:$Rd), (ins VPR64:$Rn),
8205                           asmop # "\t$Rd.2d, $Rn.2s",
8206                           [], NoItinerary>;
8207
8208   def 8h4s : NeonI_2VMisc<0b1, U, 0b00, opcode,
8209                           (outs VPR128:$Rd), (ins VPR128:$Rn),
8210                           asmop # "2\t$Rd.4s, $Rn.8h",
8211                           [], NoItinerary>;
8212
8213   def 4s2d : NeonI_2VMisc<0b1, U, 0b01, opcode,
8214                           (outs VPR128:$Rd), (ins VPR128:$Rn),
8215                           asmop # "2\t$Rd.2d, $Rn.4s",
8216                           [], NoItinerary>;
8217 }
8218
8219 defm FCVTL : NeonI_2VMisc_HS_Extend<"fcvtl", 0b0, 0b10111>;
8220
8221 multiclass NeonI_2VMisc_Extend_Pattern<string prefix> {
8222   def : Pat<(v4f32 (int_arm_neon_vcvthf2fp (v4i16 VPR64:$Rn))),
8223             (!cast<Instruction>(prefix # "4h4s") VPR64:$Rn)>;
8224
8225   def : Pat<(v4f32 (int_arm_neon_vcvthf2fp
8226               (v4i16 (Neon_High8H
8227                 (v8i16 VPR128:$Rn))))),
8228             (!cast<Instruction>(prefix # "8h4s") VPR128:$Rn)>;
8229
8230   def : Pat<(v2f64 (fextend (v2f32 VPR64:$Rn))),
8231             (!cast<Instruction>(prefix # "2s2d") VPR64:$Rn)>;
8232
8233   def : Pat<(v2f64 (fextend
8234               (v2f32 (Neon_High4Float
8235                 (v4f32 VPR128:$Rn))))),
8236             (!cast<Instruction>(prefix # "4s2d") VPR128:$Rn)>;
8237 }
8238
8239 defm : NeonI_2VMisc_Extend_Pattern<"FCVTL">;
8240
8241 multiclass NeonI_2VMisc_SD_Conv<string asmop, bit Size, bit U, bits<5> opcode,
8242                                 ValueType ResTy4s, ValueType OpTy4s,
8243                                 ValueType ResTy2d, ValueType OpTy2d,
8244                                 ValueType ResTy2s, ValueType OpTy2s,
8245                                 SDPatternOperator Neon_Op> {
8246
8247   def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8248                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8249                         asmop # "\t$Rd.4s, $Rn.4s",
8250                         [(set (ResTy4s VPR128:$Rd),
8251                            (ResTy4s (Neon_Op (OpTy4s VPR128:$Rn))))],
8252                         NoItinerary>;
8253
8254   def 2d : NeonI_2VMisc<0b1, U, {Size, 0b1}, opcode,
8255                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8256                         asmop # "\t$Rd.2d, $Rn.2d",
8257                         [(set (ResTy2d VPR128:$Rd),
8258                            (ResTy2d (Neon_Op (OpTy2d VPR128:$Rn))))],
8259                         NoItinerary>;
8260
8261   def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8262                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8263                         asmop # "\t$Rd.2s, $Rn.2s",
8264                         [(set (ResTy2s VPR64:$Rd),
8265                            (ResTy2s (Neon_Op (OpTy2s VPR64:$Rn))))],
8266                         NoItinerary>;
8267 }
8268
8269 multiclass NeonI_2VMisc_fp_to_int<string asmop, bit Size, bit U,
8270                                   bits<5> opcode, SDPatternOperator Neon_Op> {
8271   defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4i32, v4f32, v2i64,
8272                                 v2f64, v2i32, v2f32, Neon_Op>;
8273 }
8274
8275 defm FCVTNS : NeonI_2VMisc_fp_to_int<"fcvtns", 0b0, 0b0, 0b11010,
8276                                      int_aarch64_neon_fcvtns>;
8277 defm FCVTNU : NeonI_2VMisc_fp_to_int<"fcvtnu", 0b0, 0b1, 0b11010,
8278                                      int_aarch64_neon_fcvtnu>;
8279 defm FCVTPS : NeonI_2VMisc_fp_to_int<"fcvtps", 0b1, 0b0, 0b11010,
8280                                      int_aarch64_neon_fcvtps>;
8281 defm FCVTPU : NeonI_2VMisc_fp_to_int<"fcvtpu", 0b1, 0b1, 0b11010,
8282                                      int_aarch64_neon_fcvtpu>;
8283 defm FCVTMS : NeonI_2VMisc_fp_to_int<"fcvtms", 0b0, 0b0, 0b11011,
8284                                      int_aarch64_neon_fcvtms>;
8285 defm FCVTMU : NeonI_2VMisc_fp_to_int<"fcvtmu", 0b0, 0b1, 0b11011,
8286                                      int_aarch64_neon_fcvtmu>;
8287 defm FCVTZS : NeonI_2VMisc_fp_to_int<"fcvtzs", 0b1, 0b0, 0b11011, fp_to_sint>;
8288 defm FCVTZU : NeonI_2VMisc_fp_to_int<"fcvtzu", 0b1, 0b1, 0b11011, fp_to_uint>;
8289 defm FCVTAS : NeonI_2VMisc_fp_to_int<"fcvtas", 0b0, 0b0, 0b11100,
8290                                      int_aarch64_neon_fcvtas>;
8291 defm FCVTAU : NeonI_2VMisc_fp_to_int<"fcvtau", 0b0, 0b1, 0b11100,
8292                                      int_aarch64_neon_fcvtau>;
8293
8294 multiclass NeonI_2VMisc_int_to_fp<string asmop, bit Size, bit U,
8295                                   bits<5> opcode, SDPatternOperator Neon_Op> {
8296   defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4i32, v2f64,
8297                                 v2i64, v2f32, v2i32, Neon_Op>;
8298 }
8299
8300 defm SCVTF : NeonI_2VMisc_int_to_fp<"scvtf", 0b0, 0b0, 0b11101, sint_to_fp>;
8301 defm UCVTF : NeonI_2VMisc_int_to_fp<"ucvtf", 0b0, 0b1, 0b11101, uint_to_fp>;
8302
8303 multiclass NeonI_2VMisc_fp_to_fp<string asmop, bit Size, bit U,
8304                                  bits<5> opcode, SDPatternOperator Neon_Op> {
8305   defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4f32, v2f64,
8306                                 v2f64, v2f32, v2f32, Neon_Op>;
8307 }
8308
8309 defm FRINTN : NeonI_2VMisc_fp_to_fp<"frintn", 0b0, 0b0, 0b11000,
8310                                      int_aarch64_neon_frintn>;
8311 defm FRINTA : NeonI_2VMisc_fp_to_fp<"frinta", 0b0, 0b1, 0b11000, frnd>;
8312 defm FRINTP : NeonI_2VMisc_fp_to_fp<"frintp", 0b1, 0b0, 0b11000, fceil>;
8313 defm FRINTM : NeonI_2VMisc_fp_to_fp<"frintm", 0b0, 0b0, 0b11001, ffloor>;
8314 defm FRINTX : NeonI_2VMisc_fp_to_fp<"frintx", 0b0, 0b1, 0b11001, frint>;
8315 defm FRINTZ : NeonI_2VMisc_fp_to_fp<"frintz", 0b1, 0b0, 0b11001, ftrunc>;
8316 defm FRINTI : NeonI_2VMisc_fp_to_fp<"frinti", 0b1, 0b1, 0b11001, fnearbyint>;
8317 defm FRECPE : NeonI_2VMisc_fp_to_fp<"frecpe", 0b1, 0b0, 0b11101,
8318                                     int_arm_neon_vrecpe>;
8319 defm FRSQRTE : NeonI_2VMisc_fp_to_fp<"frsqrte", 0b1, 0b1, 0b11101,
8320                                      int_arm_neon_vrsqrte>;
8321 defm FSQRT : NeonI_2VMisc_fp_to_fp<"fsqrt", 0b1, 0b1, 0b11111,
8322                                    int_aarch64_neon_fsqrt>;
8323
8324 multiclass NeonI_2VMisc_S_Conv<string asmop, bit Size, bit U,
8325                                bits<5> opcode, SDPatternOperator Neon_Op> {
8326   def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8327                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8328                         asmop # "\t$Rd.4s, $Rn.4s",
8329                         [(set (v4i32 VPR128:$Rd),
8330                            (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
8331                         NoItinerary>;
8332
8333   def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8334                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8335                         asmop # "\t$Rd.2s, $Rn.2s",
8336                         [(set (v2i32 VPR64:$Rd),
8337                            (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8338                         NoItinerary>;
8339 }
8340
8341 defm URECPE : NeonI_2VMisc_S_Conv<"urecpe", 0b1, 0b0, 0b11100,
8342                                   int_arm_neon_vrecpe>;
8343 defm URSQRTE : NeonI_2VMisc_S_Conv<"ursqrte", 0b1, 0b1, 0b11100,
8344                                    int_arm_neon_vrsqrte>;
8345
8346 // Crypto Class
8347 class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
8348                          string asmop, SDPatternOperator opnode>
8349   : NeonI_Crypto_AES<size, opcode,
8350                      (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8351                      asmop # "\t$Rd.16b, $Rn.16b",
8352                      [(set (v16i8 VPR128:$Rd),
8353                         (v16i8 (opnode (v16i8 VPR128:$src),
8354                                        (v16i8 VPR128:$Rn))))],
8355                      NoItinerary>{
8356   let Constraints = "$src = $Rd";
8357   let Predicates = [HasNEON, HasCrypto];
8358 }
8359
8360 def AESE : NeonI_Cryptoaes_2v<0b00, 0b00100, "aese", int_arm_neon_aese>;
8361 def AESD : NeonI_Cryptoaes_2v<0b00, 0b00101, "aesd", int_arm_neon_aesd>;
8362
8363 class NeonI_Cryptoaes<bits<2> size, bits<5> opcode,
8364                       string asmop, SDPatternOperator opnode>
8365   : NeonI_Crypto_AES<size, opcode,
8366                      (outs VPR128:$Rd), (ins VPR128:$Rn),
8367                      asmop # "\t$Rd.16b, $Rn.16b",
8368                      [(set (v16i8 VPR128:$Rd),
8369                         (v16i8 (opnode (v16i8 VPR128:$Rn))))],
8370                      NoItinerary>;
8371
8372 def AESMC : NeonI_Cryptoaes<0b00, 0b00110, "aesmc", int_arm_neon_aesmc>;
8373 def AESIMC : NeonI_Cryptoaes<0b00, 0b00111, "aesimc", int_arm_neon_aesimc>;
8374
8375 class NeonI_Cryptosha_vv<bits<2> size, bits<5> opcode,
8376                          string asmop, SDPatternOperator opnode>
8377   : NeonI_Crypto_SHA<size, opcode,
8378                      (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8379                      asmop # "\t$Rd.4s, $Rn.4s",
8380                      [(set (v4i32 VPR128:$Rd),
8381                         (v4i32 (opnode (v4i32 VPR128:$src),
8382                                        (v4i32 VPR128:$Rn))))],
8383                      NoItinerary> {
8384   let Constraints = "$src = $Rd";
8385   let Predicates = [HasNEON, HasCrypto];
8386 }
8387
8388 def SHA1SU1 : NeonI_Cryptosha_vv<0b00, 0b00001, "sha1su1",
8389                                  int_arm_neon_sha1su1>;
8390 def SHA256SU0 : NeonI_Cryptosha_vv<0b00, 0b00010, "sha256su0",
8391                                    int_arm_neon_sha256su0>;
8392
8393 class NeonI_Cryptosha_ss<bits<2> size, bits<5> opcode,
8394                          string asmop, SDPatternOperator opnode>
8395   : NeonI_Crypto_SHA<size, opcode,
8396                      (outs FPR32:$Rd), (ins FPR32:$Rn),
8397                      asmop # "\t$Rd, $Rn",
8398                      [(set (v1i32 FPR32:$Rd),
8399                         (v1i32 (opnode (v1i32 FPR32:$Rn))))],
8400                      NoItinerary> {
8401   let Predicates = [HasNEON, HasCrypto];
8402 }
8403
8404 def SHA1H : NeonI_Cryptosha_ss<0b00, 0b00000, "sha1h", int_arm_neon_sha1h>;
8405
8406 class NeonI_Cryptosha3_vvv<bits<2> size, bits<3> opcode, string asmop,
8407                            SDPatternOperator opnode>
8408   : NeonI_Crypto_3VSHA<size, opcode,
8409                        (outs VPR128:$Rd),
8410                        (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
8411                        asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
8412                        [(set (v4i32 VPR128:$Rd),
8413                           (v4i32 (opnode (v4i32 VPR128:$src),
8414                                          (v4i32 VPR128:$Rn),
8415                                          (v4i32 VPR128:$Rm))))],
8416                        NoItinerary> {
8417   let Constraints = "$src = $Rd";
8418   let Predicates = [HasNEON, HasCrypto];
8419 }
8420
8421 def SHA1SU0 : NeonI_Cryptosha3_vvv<0b00, 0b011, "sha1su0",
8422                                    int_arm_neon_sha1su0>;
8423 def SHA256SU1 : NeonI_Cryptosha3_vvv<0b00, 0b110, "sha256su1",
8424                                      int_arm_neon_sha256su1>;
8425
8426 class NeonI_Cryptosha3_qqv<bits<2> size, bits<3> opcode, string asmop,
8427                            SDPatternOperator opnode>
8428   : NeonI_Crypto_3VSHA<size, opcode,
8429                        (outs FPR128:$Rd),
8430                        (ins FPR128:$src, FPR128:$Rn, VPR128:$Rm),
8431                        asmop # "\t$Rd, $Rn, $Rm.4s",
8432                        [(set (v4i32 FPR128:$Rd),
8433                           (v4i32 (opnode (v4i32 FPR128:$src),
8434                                          (v4i32 FPR128:$Rn),
8435                                          (v4i32 VPR128:$Rm))))],
8436                        NoItinerary> {
8437   let Constraints = "$src = $Rd";
8438   let Predicates = [HasNEON, HasCrypto];
8439 }
8440
8441 def SHA256H : NeonI_Cryptosha3_qqv<0b00, 0b100, "sha256h",
8442                                    int_arm_neon_sha256h>;
8443 def SHA256H2 : NeonI_Cryptosha3_qqv<0b00, 0b101, "sha256h2",
8444                                     int_arm_neon_sha256h2>;
8445
8446 class NeonI_Cryptosha3_qsv<bits<2> size, bits<3> opcode, string asmop,
8447                            SDPatternOperator opnode>
8448   : NeonI_Crypto_3VSHA<size, opcode,
8449                        (outs FPR128:$Rd),
8450                        (ins FPR128:$src, FPR32:$Rn, VPR128:$Rm),
8451                        asmop # "\t$Rd, $Rn, $Rm.4s",
8452                        [(set (v4i32 FPR128:$Rd),
8453                           (v4i32 (opnode (v4i32 FPR128:$src),
8454                                          (v1i32 FPR32:$Rn),
8455                                          (v4i32 VPR128:$Rm))))],
8456                        NoItinerary> {
8457   let Constraints = "$src = $Rd";
8458   let Predicates = [HasNEON, HasCrypto];
8459 }
8460
8461 def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
8462 def SHA1P : NeonI_Cryptosha3_qsv<0b00, 0b001, "sha1p", int_aarch64_neon_sha1p>;
8463 def SHA1M : NeonI_Cryptosha3_qsv<0b00, 0b010, "sha1m", int_aarch64_neon_sha1m>;
8464