1 //===-- AArch64InstrNEON.td - NEON support for AArch64 -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the AArch64 NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // (outs Result), (ins Imm, OpCmode)
19 def SDT_Neon_movi : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
21 def Neon_movi : SDNode<"AArch64ISD::NEON_MOVIMM", SDT_Neon_movi>;
23 def Neon_mvni : SDNode<"AArch64ISD::NEON_MVNIMM", SDT_Neon_movi>;
25 // (outs Result), (ins Imm)
26 def Neon_fmovi : SDNode<"AArch64ISD::NEON_FMOVIMM", SDTypeProfile<1, 1,
27 [SDTCisVec<0>, SDTCisVT<1, i32>]>>;
29 // (outs Result), (ins LHS, RHS, CondCode)
30 def Neon_cmp : SDNode<"AArch64ISD::NEON_CMP", SDTypeProfile<1, 3,
31 [SDTCisVec<0>, SDTCisSameAs<1, 2>]>>;
33 // (outs Result), (ins LHS, 0/0.0 constant, CondCode)
34 def Neon_cmpz : SDNode<"AArch64ISD::NEON_CMPZ", SDTypeProfile<1, 3,
35 [SDTCisVec<0>, SDTCisVec<1>]>>;
37 // (outs Result), (ins LHS, RHS)
38 def Neon_tst : SDNode<"AArch64ISD::NEON_TST", SDTypeProfile<1, 2,
39 [SDTCisVec<0>, SDTCisSameAs<1, 2>]>>;
41 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
43 def Neon_sqrshlImm : SDNode<"AArch64ISD::NEON_QSHLs", SDTARMVSH>;
44 def Neon_uqrshlImm : SDNode<"AArch64ISD::NEON_QSHLu", SDTARMVSH>;
46 def SDTPERMUTE : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
48 def Neon_uzp1 : SDNode<"AArch64ISD::NEON_UZP1", SDTPERMUTE>;
49 def Neon_uzp2 : SDNode<"AArch64ISD::NEON_UZP2", SDTPERMUTE>;
50 def Neon_zip1 : SDNode<"AArch64ISD::NEON_ZIP1", SDTPERMUTE>;
51 def Neon_zip2 : SDNode<"AArch64ISD::NEON_ZIP2", SDTPERMUTE>;
52 def Neon_trn1 : SDNode<"AArch64ISD::NEON_TRN1", SDTPERMUTE>;
53 def Neon_trn2 : SDNode<"AArch64ISD::NEON_TRN2", SDTPERMUTE>;
55 def SDTVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
56 def Neon_rev64 : SDNode<"AArch64ISD::NEON_REV64", SDTVSHUF>;
57 def Neon_rev32 : SDNode<"AArch64ISD::NEON_REV32", SDTVSHUF>;
58 def Neon_rev16 : SDNode<"AArch64ISD::NEON_REV16", SDTVSHUF>;
59 def Neon_vdup : SDNode<"AArch64ISD::NEON_VDUP", SDTypeProfile<1, 1,
61 def Neon_vduplane : SDNode<"AArch64ISD::NEON_VDUPLANE", SDTypeProfile<1, 2,
62 [SDTCisVec<0>, SDTCisVec<1>, SDTCisVT<2, i64>]>>;
63 def Neon_vextract : SDNode<"AArch64ISD::NEON_VEXTRACT", SDTypeProfile<1, 3,
64 [SDTCisVec<0>, SDTCisSameAs<0, 1>,
65 SDTCisSameAs<0, 2>, SDTCisVT<3, i64>]>>;
67 def SDT_assertext : SDTypeProfile<1, 1,
68 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
69 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
70 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
72 //===----------------------------------------------------------------------===//
73 // Addressing-mode instantiations
74 //===----------------------------------------------------------------------===//
76 multiclass ls_64_pats<dag address, dag Base, dag Offset, ValueType Ty> {
77 defm : ls_neutral_pats<LSFP64_LDR, LSFP64_STR, Base,
78 !foreach(decls.pattern, Offset,
79 !subst(OFFSET, dword_uimm12, decls.pattern)),
80 !foreach(decls.pattern, address,
81 !subst(OFFSET, dword_uimm12,
82 !subst(ALIGN, min_align8, decls.pattern))),
86 multiclass ls_128_pats<dag address, dag Base, dag Offset, ValueType Ty> {
87 defm : ls_neutral_pats<LSFP128_LDR, LSFP128_STR, Base,
88 !foreach(decls.pattern, Offset,
89 !subst(OFFSET, qword_uimm12, decls.pattern)),
90 !foreach(decls.pattern, address,
91 !subst(OFFSET, qword_uimm12,
92 !subst(ALIGN, min_align16, decls.pattern))),
96 multiclass uimm12_neon_pats<dag address, dag Base, dag Offset> {
97 defm : ls_64_pats<address, Base, Offset, v8i8>;
98 defm : ls_64_pats<address, Base, Offset, v4i16>;
99 defm : ls_64_pats<address, Base, Offset, v2i32>;
100 defm : ls_64_pats<address, Base, Offset, v1i64>;
101 defm : ls_64_pats<address, Base, Offset, v2f32>;
102 defm : ls_64_pats<address, Base, Offset, v1f64>;
104 defm : ls_128_pats<address, Base, Offset, v16i8>;
105 defm : ls_128_pats<address, Base, Offset, v8i16>;
106 defm : ls_128_pats<address, Base, Offset, v4i32>;
107 defm : ls_128_pats<address, Base, Offset, v2i64>;
108 defm : ls_128_pats<address, Base, Offset, v4f32>;
109 defm : ls_128_pats<address, Base, Offset, v2f64>;
112 defm : uimm12_neon_pats<(A64WrapperSmall
113 tconstpool:$Hi, tconstpool:$Lo12, ALIGN),
114 (ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>;
116 //===----------------------------------------------------------------------===//
118 //===----------------------------------------------------------------------===//
120 multiclass NeonI_3VSame_B_sizes<bit u, bits<2> size, bits<5> opcode,
121 string asmop, SDPatternOperator opnode8B,
122 SDPatternOperator opnode16B,
123 bit Commutable = 0> {
124 let isCommutable = Commutable in {
125 def _8B : NeonI_3VSame<0b0, u, size, opcode,
126 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
127 asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
128 [(set (v8i8 VPR64:$Rd),
129 (v8i8 (opnode8B (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
132 def _16B : NeonI_3VSame<0b1, u, size, opcode,
133 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
134 asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
135 [(set (v16i8 VPR128:$Rd),
136 (v16i8 (opnode16B (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
142 multiclass NeonI_3VSame_HS_sizes<bit u, bits<5> opcode,
143 string asmop, SDPatternOperator opnode,
144 bit Commutable = 0> {
145 let isCommutable = Commutable in {
146 def _4H : NeonI_3VSame<0b0, u, 0b01, opcode,
147 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
148 asmop # "\t$Rd.4h, $Rn.4h, $Rm.4h",
149 [(set (v4i16 VPR64:$Rd),
150 (v4i16 (opnode (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))))],
153 def _8H : NeonI_3VSame<0b1, u, 0b01, opcode,
154 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
155 asmop # "\t$Rd.8h, $Rn.8h, $Rm.8h",
156 [(set (v8i16 VPR128:$Rd),
157 (v8i16 (opnode (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))))],
160 def _2S : NeonI_3VSame<0b0, u, 0b10, opcode,
161 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
162 asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
163 [(set (v2i32 VPR64:$Rd),
164 (v2i32 (opnode (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))))],
167 def _4S : NeonI_3VSame<0b1, u, 0b10, opcode,
168 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
169 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
170 [(set (v4i32 VPR128:$Rd),
171 (v4i32 (opnode (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))))],
175 multiclass NeonI_3VSame_BHS_sizes<bit u, bits<5> opcode,
176 string asmop, SDPatternOperator opnode,
178 : NeonI_3VSame_HS_sizes<u, opcode, asmop, opnode, Commutable> {
179 let isCommutable = Commutable in {
180 def _8B : NeonI_3VSame<0b0, u, 0b00, opcode,
181 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
182 asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
183 [(set (v8i8 VPR64:$Rd),
184 (v8i8 (opnode (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
187 def _16B : NeonI_3VSame<0b1, u, 0b00, opcode,
188 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
189 asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
190 [(set (v16i8 VPR128:$Rd),
191 (v16i8 (opnode (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
196 multiclass NeonI_3VSame_BHSD_sizes<bit u, bits<5> opcode,
197 string asmop, SDPatternOperator opnode,
199 : NeonI_3VSame_BHS_sizes<u, opcode, asmop, opnode, Commutable> {
200 let isCommutable = Commutable in {
201 def _2D : NeonI_3VSame<0b1, u, 0b11, opcode,
202 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
203 asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
204 [(set (v2i64 VPR128:$Rd),
205 (v2i64 (opnode (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))))],
210 // Multiclass NeonI_3VSame_SD_sizes: Operand types are floating point types,
211 // but Result types can be integer or floating point types.
212 multiclass NeonI_3VSame_SD_sizes<bit u, bit size, bits<5> opcode,
213 string asmop, SDPatternOperator opnode2S,
214 SDPatternOperator opnode4S,
215 SDPatternOperator opnode2D,
216 ValueType ResTy2S, ValueType ResTy4S,
217 ValueType ResTy2D, bit Commutable = 0> {
218 let isCommutable = Commutable in {
219 def _2S : NeonI_3VSame<0b0, u, {size, 0b0}, opcode,
220 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
221 asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
222 [(set (ResTy2S VPR64:$Rd),
223 (ResTy2S (opnode2S (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
226 def _4S : NeonI_3VSame<0b1, u, {size, 0b0}, opcode,
227 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
228 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
229 [(set (ResTy4S VPR128:$Rd),
230 (ResTy4S (opnode4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
233 def _2D : NeonI_3VSame<0b1, u, {size, 0b1}, opcode,
234 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
235 asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
236 [(set (ResTy2D VPR128:$Rd),
237 (ResTy2D (opnode2D (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))))],
242 //===----------------------------------------------------------------------===//
243 // Instruction Definitions
244 //===----------------------------------------------------------------------===//
246 // Vector Arithmetic Instructions
248 // Vector Add (Integer and Floating-Point)
250 defm ADDvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b10000, "add", add, 1>;
251 defm FADDvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11010, "fadd", fadd, fadd, fadd,
252 v2f32, v4f32, v2f64, 1>;
254 // Vector Sub (Integer and Floating-Point)
256 defm SUBvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10000, "sub", sub, 0>;
257 defm FSUBvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11010, "fsub", fsub, fsub, fsub,
258 v2f32, v4f32, v2f64, 0>;
260 // Vector Multiply (Integer and Floating-Point)
262 defm MULvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10011, "mul", mul, 1>;
263 defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul, fmul, fmul,
264 v2f32, v4f32, v2f64, 1>;
266 // Vector Multiply (Polynomial)
268 defm PMULvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b10011, "pmul",
269 int_arm_neon_vmulp, int_arm_neon_vmulp, 1>;
271 // Vector Multiply-accumulate and Multiply-subtract (Integer)
273 // class NeonI_3VSame_Constraint_impl: NeonI_3VSame with no data type and
274 // two operands constraints.
275 class NeonI_3VSame_Constraint_impl<string asmop, string asmlane,
276 RegisterOperand VPRC, ValueType OpTy, bit q, bit u, bits<2> size,
277 bits<5> opcode, SDPatternOperator opnode>
278 : NeonI_3VSame<q, u, size, opcode,
279 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, VPRC:$Rm),
280 asmop # "\t$Rd" # asmlane # ", $Rn" # asmlane # ", $Rm" # asmlane,
281 [(set (OpTy VPRC:$Rd),
282 (OpTy (opnode (OpTy VPRC:$src), (OpTy VPRC:$Rn), (OpTy VPRC:$Rm))))],
284 let Constraints = "$src = $Rd";
287 def Neon_mla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
288 (add node:$Ra, (mul node:$Rn, node:$Rm))>;
290 def Neon_mls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
291 (sub node:$Ra, (mul node:$Rn, node:$Rm))>;
294 def MLAvvv_8B: NeonI_3VSame_Constraint_impl<"mla", ".8b", VPR64, v8i8,
295 0b0, 0b0, 0b00, 0b10010, Neon_mla>;
296 def MLAvvv_16B: NeonI_3VSame_Constraint_impl<"mla", ".16b", VPR128, v16i8,
297 0b1, 0b0, 0b00, 0b10010, Neon_mla>;
298 def MLAvvv_4H: NeonI_3VSame_Constraint_impl<"mla", ".4h", VPR64, v4i16,
299 0b0, 0b0, 0b01, 0b10010, Neon_mla>;
300 def MLAvvv_8H: NeonI_3VSame_Constraint_impl<"mla", ".8h", VPR128, v8i16,
301 0b1, 0b0, 0b01, 0b10010, Neon_mla>;
302 def MLAvvv_2S: NeonI_3VSame_Constraint_impl<"mla", ".2s", VPR64, v2i32,
303 0b0, 0b0, 0b10, 0b10010, Neon_mla>;
304 def MLAvvv_4S: NeonI_3VSame_Constraint_impl<"mla", ".4s", VPR128, v4i32,
305 0b1, 0b0, 0b10, 0b10010, Neon_mla>;
307 def MLSvvv_8B: NeonI_3VSame_Constraint_impl<"mls", ".8b", VPR64, v8i8,
308 0b0, 0b1, 0b00, 0b10010, Neon_mls>;
309 def MLSvvv_16B: NeonI_3VSame_Constraint_impl<"mls", ".16b", VPR128, v16i8,
310 0b1, 0b1, 0b00, 0b10010, Neon_mls>;
311 def MLSvvv_4H: NeonI_3VSame_Constraint_impl<"mls", ".4h", VPR64, v4i16,
312 0b0, 0b1, 0b01, 0b10010, Neon_mls>;
313 def MLSvvv_8H: NeonI_3VSame_Constraint_impl<"mls", ".8h", VPR128, v8i16,
314 0b1, 0b1, 0b01, 0b10010, Neon_mls>;
315 def MLSvvv_2S: NeonI_3VSame_Constraint_impl<"mls", ".2s", VPR64, v2i32,
316 0b0, 0b1, 0b10, 0b10010, Neon_mls>;
317 def MLSvvv_4S: NeonI_3VSame_Constraint_impl<"mls", ".4s", VPR128, v4i32,
318 0b1, 0b1, 0b10, 0b10010, Neon_mls>;
320 // Vector Multiply-accumulate and Multiply-subtract (Floating Point)
322 def Neon_fmla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
323 (fadd node:$Ra, (fmul_su node:$Rn, node:$Rm))>;
325 def Neon_fmls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
326 (fsub node:$Ra, (fmul_su node:$Rn, node:$Rm))>;
328 let Predicates = [HasNEON, UseFusedMAC] in {
329 def FMLAvvv_2S: NeonI_3VSame_Constraint_impl<"fmla", ".2s", VPR64, v2f32,
330 0b0, 0b0, 0b00, 0b11001, Neon_fmla>;
331 def FMLAvvv_4S: NeonI_3VSame_Constraint_impl<"fmla", ".4s", VPR128, v4f32,
332 0b1, 0b0, 0b00, 0b11001, Neon_fmla>;
333 def FMLAvvv_2D: NeonI_3VSame_Constraint_impl<"fmla", ".2d", VPR128, v2f64,
334 0b1, 0b0, 0b01, 0b11001, Neon_fmla>;
336 def FMLSvvv_2S: NeonI_3VSame_Constraint_impl<"fmls", ".2s", VPR64, v2f32,
337 0b0, 0b0, 0b10, 0b11001, Neon_fmls>;
338 def FMLSvvv_4S: NeonI_3VSame_Constraint_impl<"fmls", ".4s", VPR128, v4f32,
339 0b1, 0b0, 0b10, 0b11001, Neon_fmls>;
340 def FMLSvvv_2D: NeonI_3VSame_Constraint_impl<"fmls", ".2d", VPR128, v2f64,
341 0b1, 0b0, 0b11, 0b11001, Neon_fmls>;
344 // We're also allowed to match the fma instruction regardless of compile
346 def : Pat<(v2f32 (fma VPR64:$Rn, VPR64:$Rm, VPR64:$Ra)),
347 (FMLAvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
348 def : Pat<(v4f32 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
349 (FMLAvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
350 def : Pat<(v2f64 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
351 (FMLAvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
353 def : Pat<(v2f32 (fma (fneg VPR64:$Rn), VPR64:$Rm, VPR64:$Ra)),
354 (FMLSvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
355 def : Pat<(v4f32 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
356 (FMLSvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
357 def : Pat<(v2f64 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
358 (FMLSvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
360 // Vector Divide (Floating-Point)
362 defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv, fdiv, fdiv,
363 v2f32, v4f32, v2f64, 0>;
365 // Vector Bitwise Operations
367 // Vector Bitwise AND
369 defm ANDvvv : NeonI_3VSame_B_sizes<0b0, 0b00, 0b00011, "and", and, and, 1>;
371 // Vector Bitwise Exclusive OR
373 defm EORvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b00011, "eor", xor, xor, 1>;
377 defm ORRvvv : NeonI_3VSame_B_sizes<0b0, 0b10, 0b00011, "orr", or, or, 1>;
379 // ORR disassembled as MOV if Vn==Vm
381 // Vector Move - register
382 // Alias for ORR if Vn=Vm.
383 // FIXME: This is actually the preferred syntax but TableGen can't deal with
384 // custom printing of aliases.
385 def : NeonInstAlias<"mov $Rd.8b, $Rn.8b",
386 (ORRvvv_8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rn), 0>;
387 def : NeonInstAlias<"mov $Rd.16b, $Rn.16b",
388 (ORRvvv_16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rn), 0>;
390 // The MOVI instruction takes two immediate operands. The first is the
391 // immediate encoding, while the second is the cmode. A cmode of 14, or
392 // 0b1110, produces a MOVI operation, rather than a MVNI, ORR, or BIC.
393 def Neon_AllZero : PatFrag<(ops), (Neon_movi (i32 0), (i32 14))>;
394 def Neon_AllOne : PatFrag<(ops), (Neon_movi (i32 255), (i32 14))>;
396 def Neon_not8B : PatFrag<(ops node:$in),
397 (xor node:$in, (bitconvert (v8i8 Neon_AllOne)))>;
398 def Neon_not16B : PatFrag<(ops node:$in),
399 (xor node:$in, (bitconvert (v16i8 Neon_AllOne)))>;
401 def Neon_orn8B : PatFrag<(ops node:$Rn, node:$Rm),
402 (or node:$Rn, (Neon_not8B node:$Rm))>;
404 def Neon_orn16B : PatFrag<(ops node:$Rn, node:$Rm),
405 (or node:$Rn, (Neon_not16B node:$Rm))>;
407 def Neon_bic8B : PatFrag<(ops node:$Rn, node:$Rm),
408 (and node:$Rn, (Neon_not8B node:$Rm))>;
410 def Neon_bic16B : PatFrag<(ops node:$Rn, node:$Rm),
411 (and node:$Rn, (Neon_not16B node:$Rm))>;
414 // Vector Bitwise OR NOT - register
416 defm ORNvvv : NeonI_3VSame_B_sizes<0b0, 0b11, 0b00011, "orn",
417 Neon_orn8B, Neon_orn16B, 0>;
419 // Vector Bitwise Bit Clear (AND NOT) - register
421 defm BICvvv : NeonI_3VSame_B_sizes<0b0, 0b01, 0b00011, "bic",
422 Neon_bic8B, Neon_bic16B, 0>;
424 multiclass Neon_bitwise2V_patterns<SDPatternOperator opnode8B,
425 SDPatternOperator opnode16B,
427 Instruction INST16B> {
428 def : Pat<(v2i32 (opnode8B VPR64:$Rn, VPR64:$Rm)),
429 (INST8B VPR64:$Rn, VPR64:$Rm)>;
430 def : Pat<(v4i16 (opnode8B VPR64:$Rn, VPR64:$Rm)),
431 (INST8B VPR64:$Rn, VPR64:$Rm)>;
432 def : Pat<(v1i64 (opnode8B VPR64:$Rn, VPR64:$Rm)),
433 (INST8B VPR64:$Rn, VPR64:$Rm)>;
434 def : Pat<(v4i32 (opnode16B VPR128:$Rn, VPR128:$Rm)),
435 (INST16B VPR128:$Rn, VPR128:$Rm)>;
436 def : Pat<(v8i16 (opnode16B VPR128:$Rn, VPR128:$Rm)),
437 (INST16B VPR128:$Rn, VPR128:$Rm)>;
438 def : Pat<(v2i64 (opnode16B VPR128:$Rn, VPR128:$Rm)),
439 (INST16B VPR128:$Rn, VPR128:$Rm)>;
442 // Additional patterns for bitwise instructions AND, EOR, ORR, BIC, ORN
443 defm : Neon_bitwise2V_patterns<and, and, ANDvvv_8B, ANDvvv_16B>;
444 defm : Neon_bitwise2V_patterns<or, or, ORRvvv_8B, ORRvvv_16B>;
445 defm : Neon_bitwise2V_patterns<xor, xor, EORvvv_8B, EORvvv_16B>;
446 defm : Neon_bitwise2V_patterns<Neon_bic8B, Neon_bic16B, BICvvv_8B, BICvvv_16B>;
447 defm : Neon_bitwise2V_patterns<Neon_orn8B, Neon_orn16B, ORNvvv_8B, ORNvvv_16B>;
449 // Vector Bitwise Select
450 def BSLvvv_8B : NeonI_3VSame_Constraint_impl<"bsl", ".8b", VPR64, v8i8,
451 0b0, 0b1, 0b01, 0b00011, vselect>;
453 def BSLvvv_16B : NeonI_3VSame_Constraint_impl<"bsl", ".16b", VPR128, v16i8,
454 0b1, 0b1, 0b01, 0b00011, vselect>;
456 multiclass Neon_bitwise3V_patterns<SDPatternOperator opnode,
458 Instruction INST16B> {
459 // Disassociate type from instruction definition
460 def : Pat<(v8i8 (opnode (v8i8 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
461 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
462 def : Pat<(v2i32 (opnode (v2i32 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
463 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
464 def : Pat<(v4i16 (opnode (v4i16 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
465 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
466 def : Pat<(v1i64 (opnode (v1i64 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
467 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
468 def : Pat<(v16i8 (opnode (v16i8 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
469 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
470 def : Pat<(v4i32 (opnode (v4i32 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
471 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
472 def : Pat<(v8i16 (opnode (v8i16 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
473 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
474 def : Pat<(v2i64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
475 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
476 def : Pat<(v2f64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
477 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
478 def : Pat<(v4f32 (opnode (v4i32 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
479 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
481 // Allow to match BSL instruction pattern with non-constant operand
482 def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
483 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
484 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
485 def : Pat<(v4i16 (or (and VPR64:$Rn, VPR64:$Rd),
486 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
487 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
488 def : Pat<(v2i32 (or (and VPR64:$Rn, VPR64:$Rd),
489 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
490 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
491 def : Pat<(v1i64 (or (and VPR64:$Rn, VPR64:$Rd),
492 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
493 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
494 def : Pat<(v16i8 (or (and VPR128:$Rn, VPR128:$Rd),
495 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
496 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
497 def : Pat<(v8i16 (or (and VPR128:$Rn, VPR128:$Rd),
498 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
499 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
500 def : Pat<(v4i32 (or (and VPR128:$Rn, VPR128:$Rd),
501 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
502 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
503 def : Pat<(v2i64 (or (and VPR128:$Rn, VPR128:$Rd),
504 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
505 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
507 // Allow to match llvm.arm.* intrinsics.
508 def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 VPR64:$src),
509 (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
510 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
511 def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 VPR64:$src),
512 (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
513 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
514 def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 VPR64:$src),
515 (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
516 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
517 def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 VPR64:$src),
518 (v1i64 VPR64:$Rn), (v1i64 VPR64:$Rm))),
519 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
520 def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 VPR64:$src),
521 (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
522 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
523 def : Pat<(v1f64 (int_arm_neon_vbsl (v1f64 VPR64:$src),
524 (v1f64 VPR64:$Rn), (v1f64 VPR64:$Rm))),
525 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
526 def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 VPR128:$src),
527 (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
528 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
529 def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 VPR128:$src),
530 (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
531 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
532 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 VPR128:$src),
533 (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
534 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
535 def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 VPR128:$src),
536 (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
537 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
538 def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 VPR128:$src),
539 (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
540 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
541 def : Pat<(v2f64 (int_arm_neon_vbsl (v2f64 VPR128:$src),
542 (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
543 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
546 // Additional patterns for bitwise instruction BSL
547 defm: Neon_bitwise3V_patterns<vselect, BSLvvv_8B, BSLvvv_16B>;
549 def Neon_NoBSLop : PatFrag<(ops node:$src, node:$Rn, node:$Rm),
550 (vselect node:$src, node:$Rn, node:$Rm),
551 [{ (void)N; return false; }]>;
553 // Vector Bitwise Insert if True
555 def BITvvv_8B : NeonI_3VSame_Constraint_impl<"bit", ".8b", VPR64, v8i8,
556 0b0, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
557 def BITvvv_16B : NeonI_3VSame_Constraint_impl<"bit", ".16b", VPR128, v16i8,
558 0b1, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
560 // Vector Bitwise Insert if False
562 def BIFvvv_8B : NeonI_3VSame_Constraint_impl<"bif", ".8b", VPR64, v8i8,
563 0b0, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
564 def BIFvvv_16B : NeonI_3VSame_Constraint_impl<"bif", ".16b", VPR128, v16i8,
565 0b1, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
567 // Vector Absolute Difference and Accumulate (Signed, Unsigned)
569 def Neon_uaba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
570 (add node:$Ra, (int_arm_neon_vabdu node:$Rn, node:$Rm))>;
571 def Neon_saba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
572 (add node:$Ra, (int_arm_neon_vabds node:$Rn, node:$Rm))>;
574 // Vector Absolute Difference and Accumulate (Unsigned)
575 def UABAvvv_8B : NeonI_3VSame_Constraint_impl<"uaba", ".8b", VPR64, v8i8,
576 0b0, 0b1, 0b00, 0b01111, Neon_uaba>;
577 def UABAvvv_16B : NeonI_3VSame_Constraint_impl<"uaba", ".16b", VPR128, v16i8,
578 0b1, 0b1, 0b00, 0b01111, Neon_uaba>;
579 def UABAvvv_4H : NeonI_3VSame_Constraint_impl<"uaba", ".4h", VPR64, v4i16,
580 0b0, 0b1, 0b01, 0b01111, Neon_uaba>;
581 def UABAvvv_8H : NeonI_3VSame_Constraint_impl<"uaba", ".8h", VPR128, v8i16,
582 0b1, 0b1, 0b01, 0b01111, Neon_uaba>;
583 def UABAvvv_2S : NeonI_3VSame_Constraint_impl<"uaba", ".2s", VPR64, v2i32,
584 0b0, 0b1, 0b10, 0b01111, Neon_uaba>;
585 def UABAvvv_4S : NeonI_3VSame_Constraint_impl<"uaba", ".4s", VPR128, v4i32,
586 0b1, 0b1, 0b10, 0b01111, Neon_uaba>;
588 // Vector Absolute Difference and Accumulate (Signed)
589 def SABAvvv_8B : NeonI_3VSame_Constraint_impl<"saba", ".8b", VPR64, v8i8,
590 0b0, 0b0, 0b00, 0b01111, Neon_saba>;
591 def SABAvvv_16B : NeonI_3VSame_Constraint_impl<"saba", ".16b", VPR128, v16i8,
592 0b1, 0b0, 0b00, 0b01111, Neon_saba>;
593 def SABAvvv_4H : NeonI_3VSame_Constraint_impl<"saba", ".4h", VPR64, v4i16,
594 0b0, 0b0, 0b01, 0b01111, Neon_saba>;
595 def SABAvvv_8H : NeonI_3VSame_Constraint_impl<"saba", ".8h", VPR128, v8i16,
596 0b1, 0b0, 0b01, 0b01111, Neon_saba>;
597 def SABAvvv_2S : NeonI_3VSame_Constraint_impl<"saba", ".2s", VPR64, v2i32,
598 0b0, 0b0, 0b10, 0b01111, Neon_saba>;
599 def SABAvvv_4S : NeonI_3VSame_Constraint_impl<"saba", ".4s", VPR128, v4i32,
600 0b1, 0b0, 0b10, 0b01111, Neon_saba>;
603 // Vector Absolute Difference (Signed, Unsigned)
604 defm UABDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01110, "uabd", int_arm_neon_vabdu, 0>;
605 defm SABDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01110, "sabd", int_arm_neon_vabds, 0>;
607 // Vector Absolute Difference (Floating Point)
608 defm FABDvvv: NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11010, "fabd",
609 int_arm_neon_vabds, int_arm_neon_vabds,
610 int_arm_neon_vabds, v2f32, v4f32, v2f64, 0>;
612 // Vector Reciprocal Step (Floating Point)
613 defm FRECPSvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11111, "frecps",
614 int_arm_neon_vrecps, int_arm_neon_vrecps,
616 v2f32, v4f32, v2f64, 0>;
618 // Vector Reciprocal Square Root Step (Floating Point)
619 defm FRSQRTSvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11111, "frsqrts",
620 int_arm_neon_vrsqrts,
621 int_arm_neon_vrsqrts,
622 int_arm_neon_vrsqrts,
623 v2f32, v4f32, v2f64, 0>;
625 // Vector Comparisons
627 def Neon_cmeq : PatFrag<(ops node:$lhs, node:$rhs),
628 (Neon_cmp node:$lhs, node:$rhs, SETEQ)>;
629 def Neon_cmphs : PatFrag<(ops node:$lhs, node:$rhs),
630 (Neon_cmp node:$lhs, node:$rhs, SETUGE)>;
631 def Neon_cmge : PatFrag<(ops node:$lhs, node:$rhs),
632 (Neon_cmp node:$lhs, node:$rhs, SETGE)>;
633 def Neon_cmhi : PatFrag<(ops node:$lhs, node:$rhs),
634 (Neon_cmp node:$lhs, node:$rhs, SETUGT)>;
635 def Neon_cmgt : PatFrag<(ops node:$lhs, node:$rhs),
636 (Neon_cmp node:$lhs, node:$rhs, SETGT)>;
638 // NeonI_compare_aliases class: swaps register operands to implement
639 // comparison aliases, e.g., CMLE is alias for CMGE with operands reversed.
640 class NeonI_compare_aliases<string asmop, string asmlane,
641 Instruction inst, RegisterOperand VPRC>
642 : NeonInstAlias<asmop # "\t$Rd" # asmlane #", $Rn" # asmlane #
644 (inst VPRC:$Rd, VPRC:$Rm, VPRC:$Rn), 0b0>;
646 // Vector Comparisons (Integer)
648 // Vector Compare Mask Equal (Integer)
649 let isCommutable =1 in {
650 defm CMEQvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10001, "cmeq", Neon_cmeq, 0>;
653 // Vector Compare Mask Higher or Same (Unsigned Integer)
654 defm CMHSvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00111, "cmhs", Neon_cmphs, 0>;
656 // Vector Compare Mask Greater Than or Equal (Integer)
657 defm CMGEvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00111, "cmge", Neon_cmge, 0>;
659 // Vector Compare Mask Higher (Unsigned Integer)
660 defm CMHIvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00110, "cmhi", Neon_cmhi, 0>;
662 // Vector Compare Mask Greater Than (Integer)
663 defm CMGTvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00110, "cmgt", Neon_cmgt, 0>;
665 // Vector Compare Mask Bitwise Test (Integer)
666 defm CMTSTvvv: NeonI_3VSame_BHSD_sizes<0b0, 0b10001, "cmtst", Neon_tst, 0>;
668 // Vector Compare Mask Less or Same (Unsigned Integer)
669 // CMLS is alias for CMHS with operands reversed.
670 def CMLSvvv_8B : NeonI_compare_aliases<"cmls", ".8b", CMHSvvv_8B, VPR64>;
671 def CMLSvvv_16B : NeonI_compare_aliases<"cmls", ".16b", CMHSvvv_16B, VPR128>;
672 def CMLSvvv_4H : NeonI_compare_aliases<"cmls", ".4h", CMHSvvv_4H, VPR64>;
673 def CMLSvvv_8H : NeonI_compare_aliases<"cmls", ".8h", CMHSvvv_8H, VPR128>;
674 def CMLSvvv_2S : NeonI_compare_aliases<"cmls", ".2s", CMHSvvv_2S, VPR64>;
675 def CMLSvvv_4S : NeonI_compare_aliases<"cmls", ".4s", CMHSvvv_4S, VPR128>;
676 def CMLSvvv_2D : NeonI_compare_aliases<"cmls", ".2d", CMHSvvv_2D, VPR128>;
678 // Vector Compare Mask Less Than or Equal (Integer)
679 // CMLE is alias for CMGE with operands reversed.
680 def CMLEvvv_8B : NeonI_compare_aliases<"cmle", ".8b", CMGEvvv_8B, VPR64>;
681 def CMLEvvv_16B : NeonI_compare_aliases<"cmle", ".16b", CMGEvvv_16B, VPR128>;
682 def CMLEvvv_4H : NeonI_compare_aliases<"cmle", ".4h", CMGEvvv_4H, VPR64>;
683 def CMLEvvv_8H : NeonI_compare_aliases<"cmle", ".8h", CMGEvvv_8H, VPR128>;
684 def CMLEvvv_2S : NeonI_compare_aliases<"cmle", ".2s", CMGEvvv_2S, VPR64>;
685 def CMLEvvv_4S : NeonI_compare_aliases<"cmle", ".4s", CMGEvvv_4S, VPR128>;
686 def CMLEvvv_2D : NeonI_compare_aliases<"cmle", ".2d", CMGEvvv_2D, VPR128>;
688 // Vector Compare Mask Lower (Unsigned Integer)
689 // CMLO is alias for CMHI with operands reversed.
690 def CMLOvvv_8B : NeonI_compare_aliases<"cmlo", ".8b", CMHIvvv_8B, VPR64>;
691 def CMLOvvv_16B : NeonI_compare_aliases<"cmlo", ".16b", CMHIvvv_16B, VPR128>;
692 def CMLOvvv_4H : NeonI_compare_aliases<"cmlo", ".4h", CMHIvvv_4H, VPR64>;
693 def CMLOvvv_8H : NeonI_compare_aliases<"cmlo", ".8h", CMHIvvv_8H, VPR128>;
694 def CMLOvvv_2S : NeonI_compare_aliases<"cmlo", ".2s", CMHIvvv_2S, VPR64>;
695 def CMLOvvv_4S : NeonI_compare_aliases<"cmlo", ".4s", CMHIvvv_4S, VPR128>;
696 def CMLOvvv_2D : NeonI_compare_aliases<"cmlo", ".2d", CMHIvvv_2D, VPR128>;
698 // Vector Compare Mask Less Than (Integer)
699 // CMLT is alias for CMGT with operands reversed.
700 def CMLTvvv_8B : NeonI_compare_aliases<"cmlt", ".8b", CMGTvvv_8B, VPR64>;
701 def CMLTvvv_16B : NeonI_compare_aliases<"cmlt", ".16b", CMGTvvv_16B, VPR128>;
702 def CMLTvvv_4H : NeonI_compare_aliases<"cmlt", ".4h", CMGTvvv_4H, VPR64>;
703 def CMLTvvv_8H : NeonI_compare_aliases<"cmlt", ".8h", CMGTvvv_8H, VPR128>;
704 def CMLTvvv_2S : NeonI_compare_aliases<"cmlt", ".2s", CMGTvvv_2S, VPR64>;
705 def CMLTvvv_4S : NeonI_compare_aliases<"cmlt", ".4s", CMGTvvv_4S, VPR128>;
706 def CMLTvvv_2D : NeonI_compare_aliases<"cmlt", ".2d", CMGTvvv_2D, VPR128>;
709 def neon_uimm0_asmoperand : AsmOperandClass
712 let PredicateMethod = "isUImm<0>";
713 let RenderMethod = "addImmOperands";
716 def neon_uimm0 : Operand<i32>, ImmLeaf<i32, [{return Imm == 0;}]> {
717 let ParserMatchClass = neon_uimm0_asmoperand;
718 let PrintMethod = "printNeonUImm0Operand";
722 multiclass NeonI_cmpz_sizes<bit u, bits<5> opcode, string asmop, CondCode CC>
724 def _8B : NeonI_2VMisc<0b0, u, 0b00, opcode,
725 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
726 asmop # "\t$Rd.8b, $Rn.8b, $Imm",
727 [(set (v8i8 VPR64:$Rd),
728 (v8i8 (Neon_cmpz (v8i8 VPR64:$Rn), (i32 imm:$Imm), CC)))],
731 def _16B : NeonI_2VMisc<0b1, u, 0b00, opcode,
732 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
733 asmop # "\t$Rd.16b, $Rn.16b, $Imm",
734 [(set (v16i8 VPR128:$Rd),
735 (v16i8 (Neon_cmpz (v16i8 VPR128:$Rn), (i32 imm:$Imm), CC)))],
738 def _4H : NeonI_2VMisc<0b0, u, 0b01, opcode,
739 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
740 asmop # "\t$Rd.4h, $Rn.4h, $Imm",
741 [(set (v4i16 VPR64:$Rd),
742 (v4i16 (Neon_cmpz (v4i16 VPR64:$Rn), (i32 imm:$Imm), CC)))],
745 def _8H : NeonI_2VMisc<0b1, u, 0b01, opcode,
746 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
747 asmop # "\t$Rd.8h, $Rn.8h, $Imm",
748 [(set (v8i16 VPR128:$Rd),
749 (v8i16 (Neon_cmpz (v8i16 VPR128:$Rn), (i32 imm:$Imm), CC)))],
752 def _2S : NeonI_2VMisc<0b0, u, 0b10, opcode,
753 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
754 asmop # "\t$Rd.2s, $Rn.2s, $Imm",
755 [(set (v2i32 VPR64:$Rd),
756 (v2i32 (Neon_cmpz (v2i32 VPR64:$Rn), (i32 imm:$Imm), CC)))],
759 def _4S : NeonI_2VMisc<0b1, u, 0b10, opcode,
760 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
761 asmop # "\t$Rd.4s, $Rn.4s, $Imm",
762 [(set (v4i32 VPR128:$Rd),
763 (v4i32 (Neon_cmpz (v4i32 VPR128:$Rn), (i32 imm:$Imm), CC)))],
766 def _2D : NeonI_2VMisc<0b1, u, 0b11, opcode,
767 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
768 asmop # "\t$Rd.2d, $Rn.2d, $Imm",
769 [(set (v2i64 VPR128:$Rd),
770 (v2i64 (Neon_cmpz (v2i64 VPR128:$Rn), (i32 imm:$Imm), CC)))],
774 // Vector Compare Mask Equal to Zero (Integer)
775 defm CMEQvvi : NeonI_cmpz_sizes<0b0, 0b01001, "cmeq", SETEQ>;
777 // Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
778 defm CMGEvvi : NeonI_cmpz_sizes<0b1, 0b01000, "cmge", SETGE>;
780 // Vector Compare Mask Greater Than Zero (Signed Integer)
781 defm CMGTvvi : NeonI_cmpz_sizes<0b0, 0b01000, "cmgt", SETGT>;
783 // Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
784 defm CMLEvvi : NeonI_cmpz_sizes<0b1, 0b01001, "cmle", SETLE>;
786 // Vector Compare Mask Less Than Zero (Signed Integer)
787 defm CMLTvvi : NeonI_cmpz_sizes<0b0, 0b01010, "cmlt", SETLT>;
789 // Vector Comparisons (Floating Point)
791 // Vector Compare Mask Equal (Floating Point)
792 let isCommutable =1 in {
793 defm FCMEQvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11100, "fcmeq", Neon_cmeq,
794 Neon_cmeq, Neon_cmeq,
795 v2i32, v4i32, v2i64, 0>;
798 // Vector Compare Mask Greater Than Or Equal (Floating Point)
799 defm FCMGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11100, "fcmge", Neon_cmge,
800 Neon_cmge, Neon_cmge,
801 v2i32, v4i32, v2i64, 0>;
803 // Vector Compare Mask Greater Than (Floating Point)
804 defm FCMGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11100, "fcmgt", Neon_cmgt,
805 Neon_cmgt, Neon_cmgt,
806 v2i32, v4i32, v2i64, 0>;
808 // Vector Compare Mask Less Than Or Equal (Floating Point)
809 // FCMLE is alias for FCMGE with operands reversed.
810 def FCMLEvvv_2S : NeonI_compare_aliases<"fcmle", ".2s", FCMGEvvv_2S, VPR64>;
811 def FCMLEvvv_4S : NeonI_compare_aliases<"fcmle", ".4s", FCMGEvvv_4S, VPR128>;
812 def FCMLEvvv_2D : NeonI_compare_aliases<"fcmle", ".2d", FCMGEvvv_2D, VPR128>;
814 // Vector Compare Mask Less Than (Floating Point)
815 // FCMLT is alias for FCMGT with operands reversed.
816 def FCMLTvvv_2S : NeonI_compare_aliases<"fcmlt", ".2s", FCMGTvvv_2S, VPR64>;
817 def FCMLTvvv_4S : NeonI_compare_aliases<"fcmlt", ".4s", FCMGTvvv_4S, VPR128>;
818 def FCMLTvvv_2D : NeonI_compare_aliases<"fcmlt", ".2d", FCMGTvvv_2D, VPR128>;
820 def fpzero_izero_asmoperand : AsmOperandClass {
821 let Name = "FPZeroIZero";
822 let ParserMethod = "ParseFPImm0AndImm0Operand";
823 let DiagnosticType = "FPZero";
826 def fpzz32 : Operand<f32>,
827 ComplexPattern<f32, 1, "SelectFPZeroOperand", [fpimm]> {
828 let ParserMatchClass = fpzero_izero_asmoperand;
829 let PrintMethod = "printFPZeroOperand";
830 let DecoderMethod = "DecodeFPZeroOperand";
833 multiclass NeonI_fpcmpz_sizes<bit u, bit size, bits<5> opcode,
834 string asmop, CondCode CC>
836 def _2S : NeonI_2VMisc<0b0, u, {size, 0b0}, opcode,
837 (outs VPR64:$Rd), (ins VPR64:$Rn, fpzz32:$FPImm),
838 asmop # "\t$Rd.2s, $Rn.2s, $FPImm",
839 [(set (v2i32 VPR64:$Rd),
840 (v2i32 (Neon_cmpz (v2f32 VPR64:$Rn), (f32 fpzz32:$FPImm), CC)))],
843 def _4S : NeonI_2VMisc<0b1, u, {size, 0b0}, opcode,
844 (outs VPR128:$Rd), (ins VPR128:$Rn, fpzz32:$FPImm),
845 asmop # "\t$Rd.4s, $Rn.4s, $FPImm",
846 [(set (v4i32 VPR128:$Rd),
847 (v4i32 (Neon_cmpz (v4f32 VPR128:$Rn), (f32 fpzz32:$FPImm), CC)))],
850 def _2D : NeonI_2VMisc<0b1, u, {size, 0b1}, opcode,
851 (outs VPR128:$Rd), (ins VPR128:$Rn, fpzz32:$FPImm),
852 asmop # "\t$Rd.2d, $Rn.2d, $FPImm",
853 [(set (v2i64 VPR128:$Rd),
854 (v2i64 (Neon_cmpz (v2f64 VPR128:$Rn), (f32 fpzz32:$FPImm), CC)))],
858 // Vector Compare Mask Equal to Zero (Floating Point)
859 defm FCMEQvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01101, "fcmeq", SETEQ>;
861 // Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
862 defm FCMGEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01100, "fcmge", SETGE>;
864 // Vector Compare Mask Greater Than Zero (Floating Point)
865 defm FCMGTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01100, "fcmgt", SETGT>;
867 // Vector Compare Mask Less Than or Equal To Zero (Floating Point)
868 defm FCMLEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01101, "fcmle", SETLE>;
870 // Vector Compare Mask Less Than Zero (Floating Point)
871 defm FCMLTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01110, "fcmlt", SETLT>;
873 // Vector Absolute Comparisons (Floating Point)
875 // Vector Absolute Compare Mask Greater Than Or Equal (Floating Point)
876 defm FACGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11101, "facge",
877 int_arm_neon_vacged, int_arm_neon_vacgeq,
878 int_aarch64_neon_vacgeq,
879 v2i32, v4i32, v2i64, 0>;
881 // Vector Absolute Compare Mask Greater Than (Floating Point)
882 defm FACGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11101, "facgt",
883 int_arm_neon_vacgtd, int_arm_neon_vacgtq,
884 int_aarch64_neon_vacgtq,
885 v2i32, v4i32, v2i64, 0>;
887 // Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
888 // FACLE is alias for FACGE with operands reversed.
889 def FACLEvvv_2S : NeonI_compare_aliases<"facle", ".2s", FACGEvvv_2S, VPR64>;
890 def FACLEvvv_4S : NeonI_compare_aliases<"facle", ".4s", FACGEvvv_4S, VPR128>;
891 def FACLEvvv_2D : NeonI_compare_aliases<"facle", ".2d", FACGEvvv_2D, VPR128>;
893 // Vector Absolute Compare Mask Less Than (Floating Point)
894 // FACLT is alias for FACGT with operands reversed.
895 def FACLTvvv_2S : NeonI_compare_aliases<"faclt", ".2s", FACGTvvv_2S, VPR64>;
896 def FACLTvvv_4S : NeonI_compare_aliases<"faclt", ".4s", FACGTvvv_4S, VPR128>;
897 def FACLTvvv_2D : NeonI_compare_aliases<"faclt", ".2d", FACGTvvv_2D, VPR128>;
899 // Vector halving add (Integer Signed, Unsigned)
900 defm SHADDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00000, "shadd",
901 int_arm_neon_vhadds, 1>;
902 defm UHADDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00000, "uhadd",
903 int_arm_neon_vhaddu, 1>;
905 // Vector halving sub (Integer Signed, Unsigned)
906 defm SHSUBvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00100, "shsub",
907 int_arm_neon_vhsubs, 0>;
908 defm UHSUBvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00100, "uhsub",
909 int_arm_neon_vhsubu, 0>;
911 // Vector rouding halving add (Integer Signed, Unsigned)
912 defm SRHADDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00010, "srhadd",
913 int_arm_neon_vrhadds, 1>;
914 defm URHADDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00010, "urhadd",
915 int_arm_neon_vrhaddu, 1>;
917 // Vector Saturating add (Integer Signed, Unsigned)
918 defm SQADDvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00001, "sqadd",
919 int_arm_neon_vqadds, 1>;
920 defm UQADDvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00001, "uqadd",
921 int_arm_neon_vqaddu, 1>;
923 // Vector Saturating sub (Integer Signed, Unsigned)
924 defm SQSUBvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00101, "sqsub",
925 int_arm_neon_vqsubs, 1>;
926 defm UQSUBvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00101, "uqsub",
927 int_arm_neon_vqsubu, 1>;
929 // Vector Shift Left (Signed and Unsigned Integer)
930 defm SSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01000, "sshl",
931 int_arm_neon_vshifts, 1>;
932 defm USHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01000, "ushl",
933 int_arm_neon_vshiftu, 1>;
935 // Vector Saturating Shift Left (Signed and Unsigned Integer)
936 defm SQSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01001, "sqshl",
937 int_arm_neon_vqshifts, 1>;
938 defm UQSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01001, "uqshl",
939 int_arm_neon_vqshiftu, 1>;
941 // Vector Rouding Shift Left (Signed and Unsigned Integer)
942 defm SRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01010, "srshl",
943 int_arm_neon_vrshifts, 1>;
944 defm URSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01010, "urshl",
945 int_arm_neon_vrshiftu, 1>;
947 // Vector Saturating Rouding Shift Left (Signed and Unsigned Integer)
948 defm SQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01011, "sqrshl",
949 int_arm_neon_vqrshifts, 1>;
950 defm UQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01011, "uqrshl",
951 int_arm_neon_vqrshiftu, 1>;
953 // Vector Maximum (Signed and Unsigned Integer)
954 defm SMAXvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01100, "smax", int_arm_neon_vmaxs, 1>;
955 defm UMAXvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01100, "umax", int_arm_neon_vmaxu, 1>;
957 // Vector Minimum (Signed and Unsigned Integer)
958 defm SMINvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01101, "smin", int_arm_neon_vmins, 1>;
959 defm UMINvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01101, "umin", int_arm_neon_vminu, 1>;
961 // Vector Maximum (Floating Point)
962 defm FMAXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11110, "fmax",
963 int_arm_neon_vmaxs, int_arm_neon_vmaxs,
964 int_arm_neon_vmaxs, v2f32, v4f32, v2f64, 1>;
966 // Vector Minimum (Floating Point)
967 defm FMINvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11110, "fmin",
968 int_arm_neon_vmins, int_arm_neon_vmins,
969 int_arm_neon_vmins, v2f32, v4f32, v2f64, 1>;
971 // Vector maxNum (Floating Point) - prefer a number over a quiet NaN)
972 defm FMAXNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11000, "fmaxnm",
973 int_aarch64_neon_vmaxnm,
974 int_aarch64_neon_vmaxnm,
975 int_aarch64_neon_vmaxnm,
976 v2f32, v4f32, v2f64, 1>;
978 // Vector minNum (Floating Point) - prefer a number over a quiet NaN)
979 defm FMINNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11000, "fminnm",
980 int_aarch64_neon_vminnm,
981 int_aarch64_neon_vminnm,
982 int_aarch64_neon_vminnm,
983 v2f32, v4f32, v2f64, 1>;
985 // Vector Maximum Pairwise (Signed and Unsigned Integer)
986 defm SMAXPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10100, "smaxp", int_arm_neon_vpmaxs, 1>;
987 defm UMAXPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10100, "umaxp", int_arm_neon_vpmaxu, 1>;
989 // Vector Minimum Pairwise (Signed and Unsigned Integer)
990 defm SMINPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10101, "sminp", int_arm_neon_vpmins, 1>;
991 defm UMINPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10101, "uminp", int_arm_neon_vpminu, 1>;
993 // Vector Maximum Pairwise (Floating Point)
994 defm FMAXPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11110, "fmaxp",
995 int_arm_neon_vpmaxs, int_arm_neon_vpmaxs,
996 int_arm_neon_vpmaxs, v2f32, v4f32, v2f64, 1>;
998 // Vector Minimum Pairwise (Floating Point)
999 defm FMINPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11110, "fminp",
1000 int_arm_neon_vpmins, int_arm_neon_vpmins,
1001 int_arm_neon_vpmins, v2f32, v4f32, v2f64, 1>;
1003 // Vector maxNum Pairwise (Floating Point) - prefer a number over a quiet NaN)
1004 defm FMAXNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11000, "fmaxnmp",
1005 int_aarch64_neon_vpmaxnm,
1006 int_aarch64_neon_vpmaxnm,
1007 int_aarch64_neon_vpmaxnm,
1008 v2f32, v4f32, v2f64, 1>;
1010 // Vector minNum Pairwise (Floating Point) - prefer a number over a quiet NaN)
1011 defm FMINNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11000, "fminnmp",
1012 int_aarch64_neon_vpminnm,
1013 int_aarch64_neon_vpminnm,
1014 int_aarch64_neon_vpminnm,
1015 v2f32, v4f32, v2f64, 1>;
1017 // Vector Addition Pairwise (Integer)
1018 defm ADDP : NeonI_3VSame_BHSD_sizes<0b0, 0b10111, "addp", int_arm_neon_vpadd, 1>;
1020 // Vector Addition Pairwise (Floating Point)
1021 defm FADDP : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11010, "faddp",
1025 v2f32, v4f32, v2f64, 1>;
1027 // Vector Saturating Doubling Multiply High
1028 defm SQDMULHvvv : NeonI_3VSame_HS_sizes<0b0, 0b10110, "sqdmulh",
1029 int_arm_neon_vqdmulh, 1>;
1031 // Vector Saturating Rouding Doubling Multiply High
1032 defm SQRDMULHvvv : NeonI_3VSame_HS_sizes<0b1, 0b10110, "sqrdmulh",
1033 int_arm_neon_vqrdmulh, 1>;
1035 // Vector Multiply Extended (Floating Point)
1036 defm FMULXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11011, "fmulx",
1037 int_aarch64_neon_vmulx,
1038 int_aarch64_neon_vmulx,
1039 int_aarch64_neon_vmulx,
1040 v2f32, v4f32, v2f64, 1>;
1042 // Patterns to match llvm.aarch64.* intrinsic for
1043 // ADDP, SMINP, UMINP, SMAXP, UMAXP having i32 as output
1044 class Neon_VectorPair_v2i32_pattern<SDPatternOperator opnode, Instruction INST>
1045 : Pat<(v1i32 (opnode (v2i32 VPR64:$Rn))),
1047 (v2i32 (INST (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rn))),
1050 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_sminv, SMINPvvv_2S>;
1051 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_uminv, UMINPvvv_2S>;
1052 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_smaxv, SMAXPvvv_2S>;
1053 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_umaxv, UMAXPvvv_2S>;
1054 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_vaddv, ADDP_2S>;
1056 // Vector Immediate Instructions
1058 multiclass neon_mov_imm_shift_asmoperands<string PREFIX>
1060 def _asmoperand : AsmOperandClass
1062 let Name = "NeonMovImmShift" # PREFIX;
1063 let RenderMethod = "addNeonMovImmShift" # PREFIX # "Operands";
1064 let PredicateMethod = "isNeonMovImmShift" # PREFIX;
1068 // Definition of vector immediates shift operands
1070 // The selectable use-cases extract the shift operation
1071 // information from the OpCmode fields encoded in the immediate.
1072 def neon_mod_shift_imm_XFORM : SDNodeXForm<imm, [{
1073 uint64_t OpCmode = N->getZExtValue();
1075 unsigned ShiftOnesIn;
1077 A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1078 if (!HasShift) return SDValue();
1079 return CurDAG->getTargetConstant(ShiftImm, MVT::i32);
1082 // Vector immediates shift operands which accept LSL and MSL
1083 // shift operators with shift value in the range of 0, 8, 16, 24 (LSL),
1084 // or 0, 8 (LSLH) or 8, 16 (MSL).
1085 defm neon_mov_imm_LSL : neon_mov_imm_shift_asmoperands<"LSL">;
1086 defm neon_mov_imm_MSL : neon_mov_imm_shift_asmoperands<"MSL">;
1087 // LSLH restricts shift amount to 0, 8 out of 0, 8, 16, 24
1088 defm neon_mov_imm_LSLH : neon_mov_imm_shift_asmoperands<"LSLH">;
1090 multiclass neon_mov_imm_shift_operands<string PREFIX,
1091 string HALF, string ISHALF, code pred>
1093 def _operand : Operand<i32>, ImmLeaf<i32, pred, neon_mod_shift_imm_XFORM>
1096 "printNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1098 "DecodeNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1099 let ParserMatchClass =
1100 !cast<AsmOperandClass>("neon_mov_imm_" # PREFIX # HALF # "_asmoperand");
1104 defm neon_mov_imm_LSL : neon_mov_imm_shift_operands<"LSL", "", "false", [{
1106 unsigned ShiftOnesIn;
1108 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1109 return (HasShift && !ShiftOnesIn);
1112 defm neon_mov_imm_MSL : neon_mov_imm_shift_operands<"MSL", "", "false", [{
1114 unsigned ShiftOnesIn;
1116 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1117 return (HasShift && ShiftOnesIn);
1120 defm neon_mov_imm_LSLH : neon_mov_imm_shift_operands<"LSL", "H", "true", [{
1122 unsigned ShiftOnesIn;
1124 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1125 return (HasShift && !ShiftOnesIn);
1128 def neon_uimm1_asmoperand : AsmOperandClass
1131 let PredicateMethod = "isUImm<1>";
1132 let RenderMethod = "addImmOperands";
1135 def neon_uimm2_asmoperand : AsmOperandClass
1138 let PredicateMethod = "isUImm<2>";
1139 let RenderMethod = "addImmOperands";
1142 def neon_uimm8_asmoperand : AsmOperandClass
1145 let PredicateMethod = "isUImm<8>";
1146 let RenderMethod = "addImmOperands";
1149 def neon_uimm8 : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1150 let ParserMatchClass = neon_uimm8_asmoperand;
1151 let PrintMethod = "printUImmHexOperand";
1154 def neon_uimm64_mask_asmoperand : AsmOperandClass
1156 let Name = "NeonUImm64Mask";
1157 let PredicateMethod = "isNeonUImm64Mask";
1158 let RenderMethod = "addNeonUImm64MaskOperands";
1161 // MCOperand for 64-bit bytemask with each byte having only the
1162 // value 0x00 and 0xff is encoded as an unsigned 8-bit value
1163 def neon_uimm64_mask : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1164 let ParserMatchClass = neon_uimm64_mask_asmoperand;
1165 let PrintMethod = "printNeonUImm64MaskOperand";
1168 multiclass NeonI_mov_imm_lsl_sizes<string asmop, bit op,
1169 SDPatternOperator opnode>
1171 // shift zeros, per word
1172 def _2S : NeonI_1VModImm<0b0, op,
1174 (ins neon_uimm8:$Imm,
1175 neon_mov_imm_LSL_operand:$Simm),
1176 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1177 [(set (v2i32 VPR64:$Rd),
1178 (v2i32 (opnode (timm:$Imm),
1179 (neon_mov_imm_LSL_operand:$Simm))))],
1182 let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1185 def _4S : NeonI_1VModImm<0b1, op,
1187 (ins neon_uimm8:$Imm,
1188 neon_mov_imm_LSL_operand:$Simm),
1189 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1190 [(set (v4i32 VPR128:$Rd),
1191 (v4i32 (opnode (timm:$Imm),
1192 (neon_mov_imm_LSL_operand:$Simm))))],
1195 let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1198 // shift zeros, per halfword
1199 def _4H : NeonI_1VModImm<0b0, op,
1201 (ins neon_uimm8:$Imm,
1202 neon_mov_imm_LSLH_operand:$Simm),
1203 !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1204 [(set (v4i16 VPR64:$Rd),
1205 (v4i16 (opnode (timm:$Imm),
1206 (neon_mov_imm_LSLH_operand:$Simm))))],
1209 let cmode = {0b1, 0b0, Simm, 0b0};
1212 def _8H : NeonI_1VModImm<0b1, op,
1214 (ins neon_uimm8:$Imm,
1215 neon_mov_imm_LSLH_operand:$Simm),
1216 !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1217 [(set (v8i16 VPR128:$Rd),
1218 (v8i16 (opnode (timm:$Imm),
1219 (neon_mov_imm_LSLH_operand:$Simm))))],
1222 let cmode = {0b1, 0b0, Simm, 0b0};
1226 multiclass NeonI_mov_imm_with_constraint_lsl_sizes<string asmop, bit op,
1227 SDPatternOperator opnode,
1228 SDPatternOperator neonopnode>
1230 let Constraints = "$src = $Rd" in {
1231 // shift zeros, per word
1232 def _2S : NeonI_1VModImm<0b0, op,
1234 (ins VPR64:$src, neon_uimm8:$Imm,
1235 neon_mov_imm_LSL_operand:$Simm),
1236 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1237 [(set (v2i32 VPR64:$Rd),
1238 (v2i32 (opnode (v2i32 VPR64:$src),
1239 (v2i32 (neonopnode timm:$Imm,
1240 neon_mov_imm_LSL_operand:$Simm)))))],
1243 let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1246 def _4S : NeonI_1VModImm<0b1, op,
1248 (ins VPR128:$src, neon_uimm8:$Imm,
1249 neon_mov_imm_LSL_operand:$Simm),
1250 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1251 [(set (v4i32 VPR128:$Rd),
1252 (v4i32 (opnode (v4i32 VPR128:$src),
1253 (v4i32 (neonopnode timm:$Imm,
1254 neon_mov_imm_LSL_operand:$Simm)))))],
1257 let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1260 // shift zeros, per halfword
1261 def _4H : NeonI_1VModImm<0b0, op,
1263 (ins VPR64:$src, neon_uimm8:$Imm,
1264 neon_mov_imm_LSLH_operand:$Simm),
1265 !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1266 [(set (v4i16 VPR64:$Rd),
1267 (v4i16 (opnode (v4i16 VPR64:$src),
1268 (v4i16 (neonopnode timm:$Imm,
1269 neon_mov_imm_LSL_operand:$Simm)))))],
1272 let cmode = {0b1, 0b0, Simm, 0b1};
1275 def _8H : NeonI_1VModImm<0b1, op,
1277 (ins VPR128:$src, neon_uimm8:$Imm,
1278 neon_mov_imm_LSLH_operand:$Simm),
1279 !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1280 [(set (v8i16 VPR128:$Rd),
1281 (v8i16 (opnode (v8i16 VPR128:$src),
1282 (v8i16 (neonopnode timm:$Imm,
1283 neon_mov_imm_LSL_operand:$Simm)))))],
1286 let cmode = {0b1, 0b0, Simm, 0b1};
1291 multiclass NeonI_mov_imm_msl_sizes<string asmop, bit op,
1292 SDPatternOperator opnode>
1294 // shift ones, per word
1295 def _2S : NeonI_1VModImm<0b0, op,
1297 (ins neon_uimm8:$Imm,
1298 neon_mov_imm_MSL_operand:$Simm),
1299 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1300 [(set (v2i32 VPR64:$Rd),
1301 (v2i32 (opnode (timm:$Imm),
1302 (neon_mov_imm_MSL_operand:$Simm))))],
1305 let cmode = {0b1, 0b1, 0b0, Simm};
1308 def _4S : NeonI_1VModImm<0b1, op,
1310 (ins neon_uimm8:$Imm,
1311 neon_mov_imm_MSL_operand:$Simm),
1312 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1313 [(set (v4i32 VPR128:$Rd),
1314 (v4i32 (opnode (timm:$Imm),
1315 (neon_mov_imm_MSL_operand:$Simm))))],
1318 let cmode = {0b1, 0b1, 0b0, Simm};
1322 // Vector Move Immediate Shifted
1323 let isReMaterializable = 1 in {
1324 defm MOVIvi_lsl : NeonI_mov_imm_lsl_sizes<"movi", 0b0, Neon_movi>;
1327 // Vector Move Inverted Immediate Shifted
1328 let isReMaterializable = 1 in {
1329 defm MVNIvi_lsl : NeonI_mov_imm_lsl_sizes<"mvni", 0b1, Neon_mvni>;
1332 // Vector Bitwise Bit Clear (AND NOT) - immediate
1333 let isReMaterializable = 1 in {
1334 defm BICvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"bic", 0b1,
1338 // Vector Bitwise OR - immedidate
1340 let isReMaterializable = 1 in {
1341 defm ORRvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"orr", 0b0,
1345 // Additional patterns for Vector Bitwise Bit Clear (AND NOT) - immedidate
1346 // LowerBUILD_VECTOR favors lowering MOVI over MVNI.
1347 // BIC immediate instructions selection requires additional patterns to
1348 // transform Neon_movi operands into BIC immediate operands
1350 def neon_mov_imm_LSLH_transform_XFORM : SDNodeXForm<imm, [{
1351 uint64_t OpCmode = N->getZExtValue();
1353 unsigned ShiftOnesIn;
1354 (void)A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1355 // LSLH restricts shift amount to 0, 8 which are encoded as 0 and 1
1356 // Transform encoded shift amount 0 to 1 and 1 to 0.
1357 return CurDAG->getTargetConstant(!ShiftImm, MVT::i32);
1360 def neon_mov_imm_LSLH_transform_operand
1363 unsigned ShiftOnesIn;
1365 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1366 return (HasShift && !ShiftOnesIn); }],
1367 neon_mov_imm_LSLH_transform_XFORM>;
1369 // Transform (and A, (4h Neon_movi 0xff)) -> BIC 4h (A, 0xff, LSL 8)
1370 // Transform (and A, (4h Neon_movi 0xff LSL #8)) -> BIC 4h (A, 0xff)
1371 def : Pat<(v4i16 (and VPR64:$src,
1372 (v4i16 (Neon_movi 255,
1373 neon_mov_imm_LSLH_transform_operand:$Simm)))),
1374 (BICvi_lsl_4H VPR64:$src, 255,
1375 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1377 // Transform (and A, (8h Neon_movi 8h 0xff)) -> BIC 8h (A, 0xff, LSL 8)
1378 // Transform (and A, (8h Neon_movi 0xff LSL #8)) -> BIC 8h (A, 0xff)
1379 def : Pat<(v8i16 (and VPR128:$src,
1380 (v8i16 (Neon_movi 255,
1381 neon_mov_imm_LSLH_transform_operand:$Simm)))),
1382 (BICvi_lsl_8H VPR128:$src, 255,
1383 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1385 def : Pat<(v8i8 (and VPR64:$src,
1386 (bitconvert(v4i16 (Neon_movi 255,
1387 neon_mov_imm_LSLH_transform_operand:$Simm))))),
1388 (BICvi_lsl_4H VPR64:$src, 255,
1389 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1390 def : Pat<(v2i32 (and VPR64:$src,
1391 (bitconvert(v4i16 (Neon_movi 255,
1392 neon_mov_imm_LSLH_transform_operand:$Simm))))),
1393 (BICvi_lsl_4H VPR64:$src, 255,
1394 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1395 def : Pat<(v1i64 (and VPR64:$src,
1396 (bitconvert(v4i16 (Neon_movi 255,
1397 neon_mov_imm_LSLH_transform_operand:$Simm))))),
1398 (BICvi_lsl_4H VPR64:$src, 255,
1399 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1401 def : Pat<(v16i8 (and VPR128:$src,
1402 (bitconvert(v8i16 (Neon_movi 255,
1403 neon_mov_imm_LSLH_transform_operand:$Simm))))),
1404 (BICvi_lsl_8H VPR128:$src, 255,
1405 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1406 def : Pat<(v4i32 (and VPR128:$src,
1407 (bitconvert(v8i16 (Neon_movi 255,
1408 neon_mov_imm_LSLH_transform_operand:$Simm))))),
1409 (BICvi_lsl_8H VPR128:$src, 255,
1410 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1411 def : Pat<(v2i64 (and VPR128:$src,
1412 (bitconvert(v8i16 (Neon_movi 255,
1413 neon_mov_imm_LSLH_transform_operand:$Simm))))),
1414 (BICvi_lsl_8H VPR128:$src, 255,
1415 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1417 multiclass Neon_bitwiseVi_patterns<SDPatternOperator opnode,
1418 SDPatternOperator neonopnode,
1422 Instruction INST4S> {
1423 def : Pat<(v8i8 (opnode VPR64:$src,
1424 (bitconvert(v4i16 (neonopnode timm:$Imm,
1425 neon_mov_imm_LSLH_operand:$Simm))))),
1426 (INST4H VPR64:$src, neon_uimm8:$Imm,
1427 neon_mov_imm_LSLH_operand:$Simm)>;
1428 def : Pat<(v2i32 (opnode VPR64:$src,
1429 (bitconvert(v4i16 (neonopnode timm:$Imm,
1430 neon_mov_imm_LSLH_operand:$Simm))))),
1431 (INST4H VPR64:$src, neon_uimm8:$Imm,
1432 neon_mov_imm_LSLH_operand:$Simm)>;
1433 def : Pat<(v1i64 (opnode VPR64:$src,
1434 (bitconvert(v4i16 (neonopnode timm:$Imm,
1435 neon_mov_imm_LSLH_operand:$Simm))))),
1436 (INST4H VPR64:$src, neon_uimm8:$Imm,
1437 neon_mov_imm_LSLH_operand:$Simm)>;
1439 def : Pat<(v16i8 (opnode VPR128:$src,
1440 (bitconvert(v8i16 (neonopnode timm:$Imm,
1441 neon_mov_imm_LSLH_operand:$Simm))))),
1442 (INST8H VPR128:$src, neon_uimm8:$Imm,
1443 neon_mov_imm_LSLH_operand:$Simm)>;
1444 def : Pat<(v4i32 (opnode VPR128:$src,
1445 (bitconvert(v8i16 (neonopnode timm:$Imm,
1446 neon_mov_imm_LSLH_operand:$Simm))))),
1447 (INST8H VPR128:$src, neon_uimm8:$Imm,
1448 neon_mov_imm_LSLH_operand:$Simm)>;
1449 def : Pat<(v2i64 (opnode VPR128:$src,
1450 (bitconvert(v8i16 (neonopnode timm:$Imm,
1451 neon_mov_imm_LSLH_operand:$Simm))))),
1452 (INST8H VPR128:$src, neon_uimm8:$Imm,
1453 neon_mov_imm_LSLH_operand:$Simm)>;
1455 def : Pat<(v8i8 (opnode VPR64:$src,
1456 (bitconvert(v2i32 (neonopnode timm:$Imm,
1457 neon_mov_imm_LSLH_operand:$Simm))))),
1458 (INST2S VPR64:$src, neon_uimm8:$Imm,
1459 neon_mov_imm_LSLH_operand:$Simm)>;
1460 def : Pat<(v4i16 (opnode VPR64:$src,
1461 (bitconvert(v2i32 (neonopnode timm:$Imm,
1462 neon_mov_imm_LSLH_operand:$Simm))))),
1463 (INST2S VPR64:$src, neon_uimm8:$Imm,
1464 neon_mov_imm_LSLH_operand:$Simm)>;
1465 def : Pat<(v1i64 (opnode VPR64:$src,
1466 (bitconvert(v2i32 (neonopnode timm:$Imm,
1467 neon_mov_imm_LSLH_operand:$Simm))))),
1468 (INST2S VPR64:$src, neon_uimm8:$Imm,
1469 neon_mov_imm_LSLH_operand:$Simm)>;
1471 def : Pat<(v16i8 (opnode VPR128:$src,
1472 (bitconvert(v4i32 (neonopnode timm:$Imm,
1473 neon_mov_imm_LSLH_operand:$Simm))))),
1474 (INST4S VPR128:$src, neon_uimm8:$Imm,
1475 neon_mov_imm_LSLH_operand:$Simm)>;
1476 def : Pat<(v8i16 (opnode VPR128:$src,
1477 (bitconvert(v4i32 (neonopnode timm:$Imm,
1478 neon_mov_imm_LSLH_operand:$Simm))))),
1479 (INST4S VPR128:$src, neon_uimm8:$Imm,
1480 neon_mov_imm_LSLH_operand:$Simm)>;
1481 def : Pat<(v2i64 (opnode VPR128:$src,
1482 (bitconvert(v4i32 (neonopnode timm:$Imm,
1483 neon_mov_imm_LSLH_operand:$Simm))))),
1484 (INST4S VPR128:$src, neon_uimm8:$Imm,
1485 neon_mov_imm_LSLH_operand:$Simm)>;
1488 // Additional patterns for Vector Vector Bitwise Bit Clear (AND NOT) - immediate
1489 defm : Neon_bitwiseVi_patterns<and, Neon_mvni, BICvi_lsl_4H, BICvi_lsl_8H,
1490 BICvi_lsl_2S, BICvi_lsl_4S>;
1492 // Additional patterns for Vector Bitwise OR - immedidate
1493 defm : Neon_bitwiseVi_patterns<or, Neon_movi, ORRvi_lsl_4H, ORRvi_lsl_8H,
1494 ORRvi_lsl_2S, ORRvi_lsl_4S>;
1497 // Vector Move Immediate Masked
1498 let isReMaterializable = 1 in {
1499 defm MOVIvi_msl : NeonI_mov_imm_msl_sizes<"movi", 0b0, Neon_movi>;
1502 // Vector Move Inverted Immediate Masked
1503 let isReMaterializable = 1 in {
1504 defm MVNIvi_msl : NeonI_mov_imm_msl_sizes<"mvni", 0b1, Neon_mvni>;
1507 class NeonI_mov_imm_lsl_aliases<string asmop, string asmlane,
1508 Instruction inst, RegisterOperand VPRC>
1509 : NeonInstAlias<!strconcat(asmop, "\t$Rd," # asmlane # ", $Imm"),
1510 (inst VPRC:$Rd, neon_uimm8:$Imm, 0), 0b0>;
1512 // Aliases for Vector Move Immediate Shifted
1513 def : NeonI_mov_imm_lsl_aliases<"movi", ".2s", MOVIvi_lsl_2S, VPR64>;
1514 def : NeonI_mov_imm_lsl_aliases<"movi", ".4s", MOVIvi_lsl_4S, VPR128>;
1515 def : NeonI_mov_imm_lsl_aliases<"movi", ".4h", MOVIvi_lsl_4H, VPR64>;
1516 def : NeonI_mov_imm_lsl_aliases<"movi", ".8h", MOVIvi_lsl_8H, VPR128>;
1518 // Aliases for Vector Move Inverted Immediate Shifted
1519 def : NeonI_mov_imm_lsl_aliases<"mvni", ".2s", MVNIvi_lsl_2S, VPR64>;
1520 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4s", MVNIvi_lsl_4S, VPR128>;
1521 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4h", MVNIvi_lsl_4H, VPR64>;
1522 def : NeonI_mov_imm_lsl_aliases<"mvni", ".8h", MVNIvi_lsl_8H, VPR128>;
1524 // Aliases for Vector Bitwise Bit Clear (AND NOT) - immediate
1525 def : NeonI_mov_imm_lsl_aliases<"bic", ".2s", BICvi_lsl_2S, VPR64>;
1526 def : NeonI_mov_imm_lsl_aliases<"bic", ".4s", BICvi_lsl_4S, VPR128>;
1527 def : NeonI_mov_imm_lsl_aliases<"bic", ".4h", BICvi_lsl_4H, VPR64>;
1528 def : NeonI_mov_imm_lsl_aliases<"bic", ".8h", BICvi_lsl_8H, VPR128>;
1530 // Aliases for Vector Bitwise OR - immedidate
1531 def : NeonI_mov_imm_lsl_aliases<"orr", ".2s", ORRvi_lsl_2S, VPR64>;
1532 def : NeonI_mov_imm_lsl_aliases<"orr", ".4s", ORRvi_lsl_4S, VPR128>;
1533 def : NeonI_mov_imm_lsl_aliases<"orr", ".4h", ORRvi_lsl_4H, VPR64>;
1534 def : NeonI_mov_imm_lsl_aliases<"orr", ".8h", ORRvi_lsl_8H, VPR128>;
1536 // Vector Move Immediate - per byte
1537 let isReMaterializable = 1 in {
1538 def MOVIvi_8B : NeonI_1VModImm<0b0, 0b0,
1539 (outs VPR64:$Rd), (ins neon_uimm8:$Imm),
1540 "movi\t$Rd.8b, $Imm",
1541 [(set (v8i8 VPR64:$Rd),
1542 (v8i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1547 def MOVIvi_16B : NeonI_1VModImm<0b1, 0b0,
1548 (outs VPR128:$Rd), (ins neon_uimm8:$Imm),
1549 "movi\t$Rd.16b, $Imm",
1550 [(set (v16i8 VPR128:$Rd),
1551 (v16i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1557 // Vector Move Immediate - bytemask, per double word
1558 let isReMaterializable = 1 in {
1559 def MOVIvi_2D : NeonI_1VModImm<0b1, 0b1,
1560 (outs VPR128:$Rd), (ins neon_uimm64_mask:$Imm),
1561 "movi\t $Rd.2d, $Imm",
1562 [(set (v2i64 VPR128:$Rd),
1563 (v2i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1569 // Vector Move Immediate - bytemask, one doubleword
1571 let isReMaterializable = 1 in {
1572 def MOVIdi : NeonI_1VModImm<0b0, 0b1,
1573 (outs FPR64:$Rd), (ins neon_uimm64_mask:$Imm),
1575 [(set (v1i64 FPR64:$Rd),
1576 (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1582 // Vector Floating Point Move Immediate
1584 class NeonI_FMOV_impl<string asmlane, RegisterOperand VPRC, ValueType OpTy,
1585 Operand immOpType, bit q, bit op>
1586 : NeonI_1VModImm<q, op,
1587 (outs VPRC:$Rd), (ins immOpType:$Imm),
1588 "fmov\t$Rd" # asmlane # ", $Imm",
1589 [(set (OpTy VPRC:$Rd),
1590 (OpTy (Neon_fmovi (timm:$Imm))))],
1595 let isReMaterializable = 1 in {
1596 def FMOVvi_2S : NeonI_FMOV_impl<".2s", VPR64, v2f32, fmov32_operand, 0b0, 0b0>;
1597 def FMOVvi_4S : NeonI_FMOV_impl<".4s", VPR128, v4f32, fmov32_operand, 0b1, 0b0>;
1598 def FMOVvi_2D : NeonI_FMOV_impl<".2d", VPR128, v2f64, fmov64_operand, 0b1, 0b1>;
1601 // Vector Shift (Immediate)
1602 // Immediate in [0, 63]
1603 def imm0_63 : Operand<i32> {
1604 let ParserMatchClass = uimm6_asmoperand;
1607 // Shift Right/Left Immediate - The immh:immb field of these shifts are encoded
1611 // 8 immh:immb<6:3> = '0001xxx', <imm> is encoded in immh:immb<2:0>
1612 // 16 immh:immb<6:4> = '001xxxx', <imm> is encoded in immh:immb<3:0>
1613 // 32 immh:immb<6:5> = '01xxxxx', <imm> is encoded in immh:immb<4:0>
1614 // 64 immh:immb<6> = '1xxxxxx', <imm> is encoded in immh:immb<5:0>
1616 // The shift right immediate amount, in the range 1 to element bits, is computed
1617 // as Offset - UInt(immh:immb). The shift left immediate amount, in the range 0
1618 // to element bits - 1, is computed as UInt(immh:immb) - Offset.
1620 class shr_imm_asmoperands<string OFFSET> : AsmOperandClass {
1621 let Name = "ShrImm" # OFFSET;
1622 let RenderMethod = "addImmOperands";
1623 let DiagnosticType = "ShrImm" # OFFSET;
1626 class shr_imm<string OFFSET> : Operand<i32> {
1627 let EncoderMethod = "getShiftRightImm" # OFFSET;
1628 let DecoderMethod = "DecodeShiftRightImm" # OFFSET;
1629 let ParserMatchClass =
1630 !cast<AsmOperandClass>("shr_imm" # OFFSET # "_asmoperand");
1633 def shr_imm8_asmoperand : shr_imm_asmoperands<"8">;
1634 def shr_imm16_asmoperand : shr_imm_asmoperands<"16">;
1635 def shr_imm32_asmoperand : shr_imm_asmoperands<"32">;
1636 def shr_imm64_asmoperand : shr_imm_asmoperands<"64">;
1638 def shr_imm8 : shr_imm<"8">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 8;}]>;
1639 def shr_imm16 : shr_imm<"16">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 16;}]>;
1640 def shr_imm32 : shr_imm<"32">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 32;}]>;
1641 def shr_imm64 : shr_imm<"64">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 64;}]>;
1643 class shl_imm_asmoperands<string OFFSET> : AsmOperandClass {
1644 let Name = "ShlImm" # OFFSET;
1645 let RenderMethod = "addImmOperands";
1646 let DiagnosticType = "ShlImm" # OFFSET;
1649 class shl_imm<string OFFSET> : Operand<i32> {
1650 let EncoderMethod = "getShiftLeftImm" # OFFSET;
1651 let DecoderMethod = "DecodeShiftLeftImm" # OFFSET;
1652 let ParserMatchClass =
1653 !cast<AsmOperandClass>("shl_imm" # OFFSET # "_asmoperand");
1656 def shl_imm8_asmoperand : shl_imm_asmoperands<"8">;
1657 def shl_imm16_asmoperand : shl_imm_asmoperands<"16">;
1658 def shl_imm32_asmoperand : shl_imm_asmoperands<"32">;
1659 def shl_imm64_asmoperand : shl_imm_asmoperands<"64">;
1661 def shl_imm8 : shl_imm<"8">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 8;}]>;
1662 def shl_imm16 : shl_imm<"16">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 16;}]>;
1663 def shl_imm32 : shl_imm<"32">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 32;}]>;
1664 def shl_imm64 : shl_imm<"64">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 64;}]>;
1666 class N2VShift<bit q, bit u, bits<5> opcode, string asmop, string T,
1667 RegisterOperand VPRC, ValueType Ty, Operand ImmTy, SDNode OpNode>
1668 : NeonI_2VShiftImm<q, u, opcode,
1669 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1670 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1671 [(set (Ty VPRC:$Rd),
1672 (Ty (OpNode (Ty VPRC:$Rn),
1673 (Ty (Neon_vdup (i32 ImmTy:$Imm))))))],
1676 multiclass NeonI_N2VShL<bit u, bits<5> opcode, string asmop> {
1677 // 64-bit vector types.
1678 def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8, shl> {
1679 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1682 def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16, shl> {
1683 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1686 def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32, shl> {
1687 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1690 // 128-bit vector types.
1691 def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8, shl> {
1692 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1695 def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16, shl> {
1696 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1699 def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32, shl> {
1700 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1703 def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64, shl> {
1704 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
1708 multiclass NeonI_N2VShR<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1709 def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1711 let Inst{22-19} = 0b0001;
1714 def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1716 let Inst{22-20} = 0b001;
1719 def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1721 let Inst{22-21} = 0b01;
1724 def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1726 let Inst{22-19} = 0b0001;
1729 def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1731 let Inst{22-20} = 0b001;
1734 def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1736 let Inst{22-21} = 0b01;
1739 def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1746 defm SHLvvi : NeonI_N2VShL<0b0, 0b01010, "shl">;
1749 defm SSHRvvi : NeonI_N2VShR<0b0, 0b00000, "sshr", sra>;
1750 defm USHRvvi : NeonI_N2VShR<0b1, 0b00000, "ushr", srl>;
1752 def Neon_High16B : PatFrag<(ops node:$in),
1753 (extract_subvector (v16i8 node:$in), (iPTR 8))>;
1754 def Neon_High8H : PatFrag<(ops node:$in),
1755 (extract_subvector (v8i16 node:$in), (iPTR 4))>;
1756 def Neon_High4S : PatFrag<(ops node:$in),
1757 (extract_subvector (v4i32 node:$in), (iPTR 2))>;
1758 def Neon_High2D : PatFrag<(ops node:$in),
1759 (extract_subvector (v2i64 node:$in), (iPTR 1))>;
1760 def Neon_High4float : PatFrag<(ops node:$in),
1761 (extract_subvector (v4f32 node:$in), (iPTR 2))>;
1762 def Neon_High2double : PatFrag<(ops node:$in),
1763 (extract_subvector (v2f64 node:$in), (iPTR 1))>;
1765 def Neon_Low16B : PatFrag<(ops node:$in),
1766 (v8i8 (extract_subvector (v16i8 node:$in),
1768 def Neon_Low8H : PatFrag<(ops node:$in),
1769 (v4i16 (extract_subvector (v8i16 node:$in),
1771 def Neon_Low4S : PatFrag<(ops node:$in),
1772 (v2i32 (extract_subvector (v4i32 node:$in),
1774 def Neon_Low2D : PatFrag<(ops node:$in),
1775 (v1i64 (extract_subvector (v2i64 node:$in),
1777 def Neon_Low4float : PatFrag<(ops node:$in),
1778 (v2f32 (extract_subvector (v4f32 node:$in),
1780 def Neon_Low2double : PatFrag<(ops node:$in),
1781 (v1f64 (extract_subvector (v2f64 node:$in),
1784 class N2VShiftLong<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1785 string SrcT, ValueType DestTy, ValueType SrcTy,
1786 Operand ImmTy, SDPatternOperator ExtOp>
1787 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1788 (ins VPR64:$Rn, ImmTy:$Imm),
1789 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1790 [(set (DestTy VPR128:$Rd),
1792 (DestTy (ExtOp (SrcTy VPR64:$Rn))),
1793 (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1796 class N2VShiftLongHigh<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1797 string SrcT, ValueType DestTy, ValueType SrcTy,
1798 int StartIndex, Operand ImmTy,
1799 SDPatternOperator ExtOp, PatFrag getTop>
1800 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1801 (ins VPR128:$Rn, ImmTy:$Imm),
1802 asmop # "2\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1803 [(set (DestTy VPR128:$Rd),
1806 (SrcTy (getTop VPR128:$Rn)))),
1807 (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1810 multiclass NeonI_N2VShLL<string prefix, bit u, bits<5> opcode, string asmop,
1812 // 64-bit vector types.
1813 def _8B : N2VShiftLong<0b0, u, opcode, asmop, "8h", "8b", v8i16, v8i8,
1815 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1818 def _4H : N2VShiftLong<0b0, u, opcode, asmop, "4s", "4h", v4i32, v4i16,
1820 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1823 def _2S : N2VShiftLong<0b0, u, opcode, asmop, "2d", "2s", v2i64, v2i32,
1825 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1828 // 128-bit vector types
1829 def _16B : N2VShiftLongHigh<0b1, u, opcode, asmop, "8h", "16b", v8i16, v8i8,
1830 8, shl_imm8, ExtOp, Neon_High16B> {
1831 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1834 def _8H : N2VShiftLongHigh<0b1, u, opcode, asmop, "4s", "8h", v4i32, v4i16,
1835 4, shl_imm16, ExtOp, Neon_High8H> {
1836 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1839 def _4S : N2VShiftLongHigh<0b1, u, opcode, asmop, "2d", "4s", v2i64, v2i32,
1840 2, shl_imm32, ExtOp, Neon_High4S> {
1841 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1844 // Use other patterns to match when the immediate is 0.
1845 def : Pat<(v8i16 (ExtOp (v8i8 VPR64:$Rn))),
1846 (!cast<Instruction>(prefix # "_8B") VPR64:$Rn, 0)>;
1848 def : Pat<(v4i32 (ExtOp (v4i16 VPR64:$Rn))),
1849 (!cast<Instruction>(prefix # "_4H") VPR64:$Rn, 0)>;
1851 def : Pat<(v2i64 (ExtOp (v2i32 VPR64:$Rn))),
1852 (!cast<Instruction>(prefix # "_2S") VPR64:$Rn, 0)>;
1854 def : Pat<(v8i16 (ExtOp (v8i8 (Neon_High16B VPR128:$Rn)))),
1855 (!cast<Instruction>(prefix # "_16B") VPR128:$Rn, 0)>;
1857 def : Pat<(v4i32 (ExtOp (v4i16 (Neon_High8H VPR128:$Rn)))),
1858 (!cast<Instruction>(prefix # "_8H") VPR128:$Rn, 0)>;
1860 def : Pat<(v2i64 (ExtOp (v2i32 (Neon_High4S VPR128:$Rn)))),
1861 (!cast<Instruction>(prefix # "_4S") VPR128:$Rn, 0)>;
1865 defm SSHLLvvi : NeonI_N2VShLL<"SSHLLvvi", 0b0, 0b10100, "sshll", sext>;
1866 defm USHLLvvi : NeonI_N2VShLL<"USHLLvvi", 0b1, 0b10100, "ushll", zext>;
1868 class NeonI_ext_len_alias<string asmop, string lane, string laneOp,
1869 Instruction inst, RegisterOperand VPRC,
1870 RegisterOperand VPRCOp>
1871 : NeonInstAlias<asmop # "\t$Rd" # lane #", $Rn" # laneOp,
1872 (inst VPRC:$Rd, VPRCOp:$Rn, 0), 0b0>;
1874 // Signed integer lengthen (vector) is alias for SSHLL Vd, Vn, #0
1875 // Signed integer lengthen (vector, second part) is alias for SSHLL2 Vd, Vn, #0
1876 // FIXME: This is actually the preferred syntax but TableGen can't deal with
1877 // custom printing of aliases.
1878 def SXTLvv_8B : NeonI_ext_len_alias<"sxtl", ".8h", ".8b", SSHLLvvi_8B, VPR128, VPR64>;
1879 def SXTLvv_4H : NeonI_ext_len_alias<"sxtl", ".4s", ".4h", SSHLLvvi_4H, VPR128, VPR64>;
1880 def SXTLvv_2S : NeonI_ext_len_alias<"sxtl", ".2d", ".2s", SSHLLvvi_2S, VPR128, VPR64>;
1881 def SXTL2vv_16B : NeonI_ext_len_alias<"sxtl2", ".8h", ".16b", SSHLLvvi_16B, VPR128, VPR128>;
1882 def SXTL2vv_8H : NeonI_ext_len_alias<"sxtl2", ".4s", ".8h", SSHLLvvi_8H, VPR128, VPR128>;
1883 def SXTL2vv_4S : NeonI_ext_len_alias<"sxtl2", ".2d", ".4s", SSHLLvvi_4S, VPR128, VPR128>;
1885 // Unsigned integer lengthen (vector) is alias for USHLL Vd, Vn, #0
1886 // Unsigned integer lengthen (vector, second part) is alias for USHLL2 Vd, Vn, #0
1887 // FIXME: This is actually the preferred syntax but TableGen can't deal with
1888 // custom printing of aliases.
1889 def UXTLvv_8B : NeonI_ext_len_alias<"uxtl", ".8h", ".8b", USHLLvvi_8B, VPR128, VPR64>;
1890 def UXTLvv_4H : NeonI_ext_len_alias<"uxtl", ".4s", ".4h", USHLLvvi_4H, VPR128, VPR64>;
1891 def UXTLvv_2S : NeonI_ext_len_alias<"uxtl", ".2d", ".2s", USHLLvvi_2S, VPR128, VPR64>;
1892 def UXTL2vv_16B : NeonI_ext_len_alias<"uxtl2", ".8h", ".16b", USHLLvvi_16B, VPR128, VPR128>;
1893 def UXTL2vv_8H : NeonI_ext_len_alias<"uxtl2", ".4s", ".8h", USHLLvvi_8H, VPR128, VPR128>;
1894 def UXTL2vv_4S : NeonI_ext_len_alias<"uxtl2", ".2d", ".4s", USHLLvvi_4S, VPR128, VPR128>;
1896 def : Pat<(v8i16 (anyext (v8i8 VPR64:$Rn))), (USHLLvvi_8B VPR64:$Rn, 0)>;
1897 def : Pat<(v4i32 (anyext (v4i16 VPR64:$Rn))), (USHLLvvi_4H VPR64:$Rn, 0)>;
1898 def : Pat<(v2i64 (anyext (v2i32 VPR64:$Rn))), (USHLLvvi_2S VPR64:$Rn, 0)>;
1900 // Rounding/Saturating shift
1901 class N2VShift_RQ<bit q, bit u, bits<5> opcode, string asmop, string T,
1902 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1903 SDPatternOperator OpNode>
1904 : NeonI_2VShiftImm<q, u, opcode,
1905 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1906 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1907 [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$Rn),
1908 (i32 ImmTy:$Imm))))],
1911 // shift right (vector by immediate)
1912 multiclass NeonI_N2VShR_RQ<bit u, bits<5> opcode, string asmop,
1913 SDPatternOperator OpNode> {
1914 def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1916 let Inst{22-19} = 0b0001;
1919 def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1921 let Inst{22-20} = 0b001;
1924 def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1926 let Inst{22-21} = 0b01;
1929 def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1931 let Inst{22-19} = 0b0001;
1934 def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1936 let Inst{22-20} = 0b001;
1939 def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1941 let Inst{22-21} = 0b01;
1944 def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1950 multiclass NeonI_N2VShL_Q<bit u, bits<5> opcode, string asmop,
1951 SDPatternOperator OpNode> {
1952 // 64-bit vector types.
1953 def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
1955 let Inst{22-19} = 0b0001;
1958 def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
1960 let Inst{22-20} = 0b001;
1963 def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
1965 let Inst{22-21} = 0b01;
1968 // 128-bit vector types.
1969 def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
1971 let Inst{22-19} = 0b0001;
1974 def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
1976 let Inst{22-20} = 0b001;
1979 def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
1981 let Inst{22-21} = 0b01;
1984 def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
1990 // Rounding shift right
1991 defm SRSHRvvi : NeonI_N2VShR_RQ<0b0, 0b00100, "srshr",
1992 int_aarch64_neon_vsrshr>;
1993 defm URSHRvvi : NeonI_N2VShR_RQ<0b1, 0b00100, "urshr",
1994 int_aarch64_neon_vurshr>;
1996 // Saturating shift left unsigned
1997 defm SQSHLUvvi : NeonI_N2VShL_Q<0b1, 0b01100, "sqshlu", int_aarch64_neon_vsqshlu>;
1999 // Saturating shift left
2000 defm SQSHLvvi : NeonI_N2VShL_Q<0b0, 0b01110, "sqshl", Neon_sqrshlImm>;
2001 defm UQSHLvvi : NeonI_N2VShL_Q<0b1, 0b01110, "uqshl", Neon_uqrshlImm>;
2003 class N2VShiftAdd<bit q, bit u, bits<5> opcode, string asmop, string T,
2004 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
2006 : NeonI_2VShiftImm<q, u, opcode,
2007 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
2008 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2009 [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
2010 (Ty (OpNode (Ty VPRC:$Rn),
2011 (Ty (Neon_vdup (i32 ImmTy:$Imm))))))))],
2013 let Constraints = "$src = $Rd";
2016 // Shift Right accumulate
2017 multiclass NeonI_N2VShRAdd<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
2018 def _8B : N2VShiftAdd<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
2020 let Inst{22-19} = 0b0001;
2023 def _4H : N2VShiftAdd<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
2025 let Inst{22-20} = 0b001;
2028 def _2S : N2VShiftAdd<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
2030 let Inst{22-21} = 0b01;
2033 def _16B : N2VShiftAdd<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2035 let Inst{22-19} = 0b0001;
2038 def _8H : N2VShiftAdd<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2040 let Inst{22-20} = 0b001;
2043 def _4S : N2VShiftAdd<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2045 let Inst{22-21} = 0b01;
2048 def _2D : N2VShiftAdd<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2054 // Shift right and accumulate
2055 defm SSRAvvi : NeonI_N2VShRAdd<0, 0b00010, "ssra", sra>;
2056 defm USRAvvi : NeonI_N2VShRAdd<1, 0b00010, "usra", srl>;
2058 // Rounding shift accumulate
2059 class N2VShiftAdd_R<bit q, bit u, bits<5> opcode, string asmop, string T,
2060 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
2061 SDPatternOperator OpNode>
2062 : NeonI_2VShiftImm<q, u, opcode,
2063 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
2064 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2065 [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
2066 (Ty (OpNode (Ty VPRC:$Rn), (i32 ImmTy:$Imm))))))],
2068 let Constraints = "$src = $Rd";
2071 multiclass NeonI_N2VShRAdd_R<bit u, bits<5> opcode, string asmop,
2072 SDPatternOperator OpNode> {
2073 def _8B : N2VShiftAdd_R<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
2075 let Inst{22-19} = 0b0001;
2078 def _4H : N2VShiftAdd_R<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
2080 let Inst{22-20} = 0b001;
2083 def _2S : N2VShiftAdd_R<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
2085 let Inst{22-21} = 0b01;
2088 def _16B : N2VShiftAdd_R<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2090 let Inst{22-19} = 0b0001;
2093 def _8H : N2VShiftAdd_R<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2095 let Inst{22-20} = 0b001;
2098 def _4S : N2VShiftAdd_R<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2100 let Inst{22-21} = 0b01;
2103 def _2D : N2VShiftAdd_R<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2109 // Rounding shift right and accumulate
2110 defm SRSRAvvi : NeonI_N2VShRAdd_R<0, 0b00110, "srsra", int_aarch64_neon_vsrshr>;
2111 defm URSRAvvi : NeonI_N2VShRAdd_R<1, 0b00110, "ursra", int_aarch64_neon_vurshr>;
2113 // Shift insert by immediate
2114 class N2VShiftIns<bit q, bit u, bits<5> opcode, string asmop, string T,
2115 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
2116 SDPatternOperator OpNode>
2117 : NeonI_2VShiftImm<q, u, opcode,
2118 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
2119 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2120 [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$src), (Ty VPRC:$Rn),
2121 (i32 ImmTy:$Imm))))],
2123 let Constraints = "$src = $Rd";
2126 // shift left insert (vector by immediate)
2127 multiclass NeonI_N2VShLIns<bit u, bits<5> opcode, string asmop> {
2128 def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
2129 int_aarch64_neon_vsli> {
2130 let Inst{22-19} = 0b0001;
2133 def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
2134 int_aarch64_neon_vsli> {
2135 let Inst{22-20} = 0b001;
2138 def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
2139 int_aarch64_neon_vsli> {
2140 let Inst{22-21} = 0b01;
2143 // 128-bit vector types
2144 def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
2145 int_aarch64_neon_vsli> {
2146 let Inst{22-19} = 0b0001;
2149 def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
2150 int_aarch64_neon_vsli> {
2151 let Inst{22-20} = 0b001;
2154 def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
2155 int_aarch64_neon_vsli> {
2156 let Inst{22-21} = 0b01;
2159 def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
2160 int_aarch64_neon_vsli> {
2165 // shift right insert (vector by immediate)
2166 multiclass NeonI_N2VShRIns<bit u, bits<5> opcode, string asmop> {
2167 // 64-bit vector types.
2168 def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
2169 int_aarch64_neon_vsri> {
2170 let Inst{22-19} = 0b0001;
2173 def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
2174 int_aarch64_neon_vsri> {
2175 let Inst{22-20} = 0b001;
2178 def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
2179 int_aarch64_neon_vsri> {
2180 let Inst{22-21} = 0b01;
2183 // 128-bit vector types
2184 def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2185 int_aarch64_neon_vsri> {
2186 let Inst{22-19} = 0b0001;
2189 def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2190 int_aarch64_neon_vsri> {
2191 let Inst{22-20} = 0b001;
2194 def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2195 int_aarch64_neon_vsri> {
2196 let Inst{22-21} = 0b01;
2199 def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2200 int_aarch64_neon_vsri> {
2205 // Shift left and insert
2206 defm SLIvvi : NeonI_N2VShLIns<0b1, 0b01010, "sli">;
2208 // Shift right and insert
2209 defm SRIvvi : NeonI_N2VShRIns<0b1, 0b01000, "sri">;
2211 class N2VShR_Narrow<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2212 string SrcT, Operand ImmTy>
2213 : NeonI_2VShiftImm<q, u, opcode,
2214 (outs VPR64:$Rd), (ins VPR128:$Rn, ImmTy:$Imm),
2215 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2218 class N2VShR_Narrow_Hi<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2219 string SrcT, Operand ImmTy>
2220 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
2221 (ins VPR128:$src, VPR128:$Rn, ImmTy:$Imm),
2222 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2224 let Constraints = "$src = $Rd";
2227 // left long shift by immediate
2228 multiclass NeonI_N2VShR_Narrow<bit u, bits<5> opcode, string asmop> {
2229 def _8B : N2VShR_Narrow<0b0, u, opcode, asmop, "8b", "8h", shr_imm8> {
2230 let Inst{22-19} = 0b0001;
2233 def _4H : N2VShR_Narrow<0b0, u, opcode, asmop, "4h", "4s", shr_imm16> {
2234 let Inst{22-20} = 0b001;
2237 def _2S : N2VShR_Narrow<0b0, u, opcode, asmop, "2s", "2d", shr_imm32> {
2238 let Inst{22-21} = 0b01;
2241 // Shift Narrow High
2242 def _16B : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "16b", "8h",
2244 let Inst{22-19} = 0b0001;
2247 def _8H : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "8h", "4s",
2249 let Inst{22-20} = 0b001;
2252 def _4S : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "4s", "2d",
2254 let Inst{22-21} = 0b01;
2258 // Shift right narrow
2259 defm SHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10000, "shrn">;
2261 // Shift right narrow (prefix Q is saturating, prefix R is rounding)
2262 defm QSHRUNvvi :NeonI_N2VShR_Narrow<0b1, 0b10000, "sqshrun">;
2263 defm RSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10001, "rshrn">;
2264 defm QRSHRUNvvi : NeonI_N2VShR_Narrow<0b1, 0b10001, "sqrshrun">;
2265 defm SQSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10010, "sqshrn">;
2266 defm UQSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10010, "uqshrn">;
2267 defm SQRSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10011, "sqrshrn">;
2268 defm UQRSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10011, "uqrshrn">;
2270 def Neon_combine_2D : PatFrag<(ops node:$Rm, node:$Rn),
2271 (v2i64 (concat_vectors (v1i64 node:$Rm),
2272 (v1i64 node:$Rn)))>;
2273 def Neon_combine_8H : PatFrag<(ops node:$Rm, node:$Rn),
2274 (v8i16 (concat_vectors (v4i16 node:$Rm),
2275 (v4i16 node:$Rn)))>;
2276 def Neon_combine_4S : PatFrag<(ops node:$Rm, node:$Rn),
2277 (v4i32 (concat_vectors (v2i32 node:$Rm),
2278 (v2i32 node:$Rn)))>;
2279 def Neon_combine_4f : PatFrag<(ops node:$Rm, node:$Rn),
2280 (v4f32 (concat_vectors (v2f32 node:$Rm),
2281 (v2f32 node:$Rn)))>;
2282 def Neon_combine_2d : PatFrag<(ops node:$Rm, node:$Rn),
2283 (v2f64 (concat_vectors (v1f64 node:$Rm),
2284 (v1f64 node:$Rn)))>;
2286 def Neon_lshrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2287 (v8i16 (srl (v8i16 node:$lhs),
2288 (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2289 def Neon_lshrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2290 (v4i32 (srl (v4i32 node:$lhs),
2291 (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2292 def Neon_lshrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2293 (v2i64 (srl (v2i64 node:$lhs),
2294 (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2295 def Neon_ashrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2296 (v8i16 (sra (v8i16 node:$lhs),
2297 (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2298 def Neon_ashrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2299 (v4i32 (sra (v4i32 node:$lhs),
2300 (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2301 def Neon_ashrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2302 (v2i64 (sra (v2i64 node:$lhs),
2303 (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2305 // Normal shift right narrow is matched by IR (srl/sra, trunc, concat_vectors)
2306 multiclass Neon_shiftNarrow_patterns<string shr> {
2307 def : Pat<(v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H") VPR128:$Rn,
2308 (i32 shr_imm8:$Imm)))),
2309 (SHRNvvi_8B VPR128:$Rn, imm:$Imm)>;
2310 def : Pat<(v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S") VPR128:$Rn,
2311 (i32 shr_imm16:$Imm)))),
2312 (SHRNvvi_4H VPR128:$Rn, imm:$Imm)>;
2313 def : Pat<(v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D") VPR128:$Rn,
2314 (i32 shr_imm32:$Imm)))),
2315 (SHRNvvi_2S VPR128:$Rn, imm:$Imm)>;
2317 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2318 (v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H")
2319 VPR128:$Rn, (i32 shr_imm8:$Imm))))))),
2320 (SHRNvvi_16B (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
2321 VPR128:$Rn, imm:$Imm)>;
2322 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2323 (v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S")
2324 VPR128:$Rn, (i32 shr_imm16:$Imm))))))),
2325 (SHRNvvi_8H (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2326 VPR128:$Rn, imm:$Imm)>;
2327 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2328 (v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D")
2329 VPR128:$Rn, (i32 shr_imm32:$Imm))))))),
2330 (SHRNvvi_4S (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2331 VPR128:$Rn, imm:$Imm)>;
2334 multiclass Neon_shiftNarrow_QR_patterns<SDPatternOperator op, string prefix> {
2335 def : Pat<(v8i8 (op (v8i16 VPR128:$Rn), shr_imm8:$Imm)),
2336 (!cast<Instruction>(prefix # "_8B") VPR128:$Rn, imm:$Imm)>;
2337 def : Pat<(v4i16 (op (v4i32 VPR128:$Rn), shr_imm16:$Imm)),
2338 (!cast<Instruction>(prefix # "_4H") VPR128:$Rn, imm:$Imm)>;
2339 def : Pat<(v2i32 (op (v2i64 VPR128:$Rn), shr_imm32:$Imm)),
2340 (!cast<Instruction>(prefix # "_2S") VPR128:$Rn, imm:$Imm)>;
2342 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2343 (v1i64 (bitconvert (v8i8
2344 (op (v8i16 VPR128:$Rn), shr_imm8:$Imm))))),
2345 (!cast<Instruction>(prefix # "_16B")
2346 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2347 VPR128:$Rn, imm:$Imm)>;
2348 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2349 (v1i64 (bitconvert (v4i16
2350 (op (v4i32 VPR128:$Rn), shr_imm16:$Imm))))),
2351 (!cast<Instruction>(prefix # "_8H")
2352 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2353 VPR128:$Rn, imm:$Imm)>;
2354 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2355 (v1i64 (bitconvert (v2i32
2356 (op (v2i64 VPR128:$Rn), shr_imm32:$Imm))))),
2357 (!cast<Instruction>(prefix # "_4S")
2358 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2359 VPR128:$Rn, imm:$Imm)>;
2362 defm : Neon_shiftNarrow_patterns<"lshr">;
2363 defm : Neon_shiftNarrow_patterns<"ashr">;
2365 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrun, "QSHRUNvvi">;
2366 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vrshrn, "RSHRNvvi">;
2367 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrun, "QRSHRUNvvi">;
2368 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrn, "SQSHRNvvi">;
2369 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqshrn, "UQSHRNvvi">;
2370 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrn, "SQRSHRNvvi">;
2371 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqrshrn, "UQRSHRNvvi">;
2373 // Convert fix-point and float-pointing
2374 class N2VCvt_Fx<bit q, bit u, bits<5> opcode, string asmop, string T,
2375 RegisterOperand VPRC, ValueType DestTy, ValueType SrcTy,
2376 Operand ImmTy, SDPatternOperator IntOp>
2377 : NeonI_2VShiftImm<q, u, opcode,
2378 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
2379 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2380 [(set (DestTy VPRC:$Rd), (DestTy (IntOp (SrcTy VPRC:$Rn),
2381 (i32 ImmTy:$Imm))))],
2384 multiclass NeonI_N2VCvt_Fx2fp<bit u, bits<5> opcode, string asmop,
2385 SDPatternOperator IntOp> {
2386 def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2f32, v2i32,
2388 let Inst{22-21} = 0b01;
2391 def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4f32, v4i32,
2393 let Inst{22-21} = 0b01;
2396 def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2f64, v2i64,
2402 multiclass NeonI_N2VCvt_Fp2fx<bit u, bits<5> opcode, string asmop,
2403 SDPatternOperator IntOp> {
2404 def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2i32, v2f32,
2406 let Inst{22-21} = 0b01;
2409 def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4i32, v4f32,
2411 let Inst{22-21} = 0b01;
2414 def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2i64, v2f64,
2420 // Convert fixed-point to floating-point
2421 defm VCVTxs2f : NeonI_N2VCvt_Fx2fp<0, 0b11100, "scvtf",
2422 int_arm_neon_vcvtfxs2fp>;
2423 defm VCVTxu2f : NeonI_N2VCvt_Fx2fp<1, 0b11100, "ucvtf",
2424 int_arm_neon_vcvtfxu2fp>;
2426 // Convert floating-point to fixed-point
2427 defm VCVTf2xs : NeonI_N2VCvt_Fp2fx<0, 0b11111, "fcvtzs",
2428 int_arm_neon_vcvtfp2fxs>;
2429 defm VCVTf2xu : NeonI_N2VCvt_Fp2fx<1, 0b11111, "fcvtzu",
2430 int_arm_neon_vcvtfp2fxu>;
2432 multiclass Neon_sshll2_0<SDNode ext>
2434 def _v8i8 : PatFrag<(ops node:$Rn),
2435 (v8i16 (ext (v8i8 (Neon_High16B node:$Rn))))>;
2436 def _v4i16 : PatFrag<(ops node:$Rn),
2437 (v4i32 (ext (v4i16 (Neon_High8H node:$Rn))))>;
2438 def _v2i32 : PatFrag<(ops node:$Rn),
2439 (v2i64 (ext (v2i32 (Neon_High4S node:$Rn))))>;
2442 defm NI_sext_high : Neon_sshll2_0<sext>;
2443 defm NI_zext_high : Neon_sshll2_0<zext>;
2446 //===----------------------------------------------------------------------===//
2447 // Multiclasses for NeonI_Across
2448 //===----------------------------------------------------------------------===//
2452 multiclass NeonI_2VAcross_1<bit u, bits<5> opcode,
2453 string asmop, SDPatternOperator opnode>
2455 def _1h8b: NeonI_2VAcross<0b0, u, 0b00, opcode,
2456 (outs FPR16:$Rd), (ins VPR64:$Rn),
2457 asmop # "\t$Rd, $Rn.8b",
2458 [(set (v1i16 FPR16:$Rd),
2459 (v1i16 (opnode (v8i8 VPR64:$Rn))))],
2462 def _1h16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2463 (outs FPR16:$Rd), (ins VPR128:$Rn),
2464 asmop # "\t$Rd, $Rn.16b",
2465 [(set (v1i16 FPR16:$Rd),
2466 (v1i16 (opnode (v16i8 VPR128:$Rn))))],
2469 def _1s4h: NeonI_2VAcross<0b0, u, 0b01, opcode,
2470 (outs FPR32:$Rd), (ins VPR64:$Rn),
2471 asmop # "\t$Rd, $Rn.4h",
2472 [(set (v1i32 FPR32:$Rd),
2473 (v1i32 (opnode (v4i16 VPR64:$Rn))))],
2476 def _1s8h: NeonI_2VAcross<0b1, u, 0b01, opcode,
2477 (outs FPR32:$Rd), (ins VPR128:$Rn),
2478 asmop # "\t$Rd, $Rn.8h",
2479 [(set (v1i32 FPR32:$Rd),
2480 (v1i32 (opnode (v8i16 VPR128:$Rn))))],
2483 // _1d2s doesn't exist!
2485 def _1d4s: NeonI_2VAcross<0b1, u, 0b10, opcode,
2486 (outs FPR64:$Rd), (ins VPR128:$Rn),
2487 asmop # "\t$Rd, $Rn.4s",
2488 [(set (v1i64 FPR64:$Rd),
2489 (v1i64 (opnode (v4i32 VPR128:$Rn))))],
2493 defm SADDLV : NeonI_2VAcross_1<0b0, 0b00011, "saddlv", int_aarch64_neon_saddlv>;
2494 defm UADDLV : NeonI_2VAcross_1<0b1, 0b00011, "uaddlv", int_aarch64_neon_uaddlv>;
2498 multiclass NeonI_2VAcross_2<bit u, bits<5> opcode,
2499 string asmop, SDPatternOperator opnode>
2501 def _1b8b: NeonI_2VAcross<0b0, u, 0b00, opcode,
2502 (outs FPR8:$Rd), (ins VPR64:$Rn),
2503 asmop # "\t$Rd, $Rn.8b",
2504 [(set (v1i8 FPR8:$Rd),
2505 (v1i8 (opnode (v8i8 VPR64:$Rn))))],
2508 def _1b16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2509 (outs FPR8:$Rd), (ins VPR128:$Rn),
2510 asmop # "\t$Rd, $Rn.16b",
2511 [(set (v1i8 FPR8:$Rd),
2512 (v1i8 (opnode (v16i8 VPR128:$Rn))))],
2515 def _1h4h: NeonI_2VAcross<0b0, u, 0b01, opcode,
2516 (outs FPR16:$Rd), (ins VPR64:$Rn),
2517 asmop # "\t$Rd, $Rn.4h",
2518 [(set (v1i16 FPR16:$Rd),
2519 (v1i16 (opnode (v4i16 VPR64:$Rn))))],
2522 def _1h8h: NeonI_2VAcross<0b1, u, 0b01, opcode,
2523 (outs FPR16:$Rd), (ins VPR128:$Rn),
2524 asmop # "\t$Rd, $Rn.8h",
2525 [(set (v1i16 FPR16:$Rd),
2526 (v1i16 (opnode (v8i16 VPR128:$Rn))))],
2529 // _1s2s doesn't exist!
2531 def _1s4s: NeonI_2VAcross<0b1, u, 0b10, opcode,
2532 (outs FPR32:$Rd), (ins VPR128:$Rn),
2533 asmop # "\t$Rd, $Rn.4s",
2534 [(set (v1i32 FPR32:$Rd),
2535 (v1i32 (opnode (v4i32 VPR128:$Rn))))],
2539 defm SMAXV : NeonI_2VAcross_2<0b0, 0b01010, "smaxv", int_aarch64_neon_smaxv>;
2540 defm UMAXV : NeonI_2VAcross_2<0b1, 0b01010, "umaxv", int_aarch64_neon_umaxv>;
2542 defm SMINV : NeonI_2VAcross_2<0b0, 0b11010, "sminv", int_aarch64_neon_sminv>;
2543 defm UMINV : NeonI_2VAcross_2<0b1, 0b11010, "uminv", int_aarch64_neon_uminv>;
2545 defm ADDV : NeonI_2VAcross_2<0b0, 0b11011, "addv", int_aarch64_neon_vaddv>;
2549 multiclass NeonI_2VAcross_3<bit u, bits<5> opcode, bits<2> size,
2550 string asmop, SDPatternOperator opnode> {
2551 def _1s4s: NeonI_2VAcross<0b1, u, size, opcode,
2552 (outs FPR32:$Rd), (ins VPR128:$Rn),
2553 asmop # "\t$Rd, $Rn.4s",
2554 [(set (f32 FPR32:$Rd),
2555 (f32 (opnode (v4f32 VPR128:$Rn))))],
2559 defm FMAXNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b00, "fmaxnmv",
2560 int_aarch64_neon_vmaxnmv>;
2561 defm FMINNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b10, "fminnmv",
2562 int_aarch64_neon_vminnmv>;
2564 defm FMAXV : NeonI_2VAcross_3<0b1, 0b01111, 0b00, "fmaxv",
2565 int_aarch64_neon_vmaxv>;
2566 defm FMINV : NeonI_2VAcross_3<0b1, 0b01111, 0b10, "fminv",
2567 int_aarch64_neon_vminv>;
2569 // The followings are for instruction class (Perm)
2571 class NeonI_Permute<bit q, bits<2> size, bits<3> opcode,
2572 string asmop, RegisterOperand OpVPR, string OpS,
2573 SDPatternOperator opnode, ValueType Ty>
2574 : NeonI_Perm<q, size, opcode,
2575 (outs OpVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2576 asmop # "\t$Rd." # OpS # ", $Rn." # OpS # ", $Rm." # OpS,
2577 [(set (Ty OpVPR:$Rd),
2578 (Ty (opnode (Ty OpVPR:$Rn), (Ty OpVPR:$Rm))))],
2581 multiclass NeonI_Perm_pat<bits<3> opcode, string asmop,
2582 SDPatternOperator opnode> {
2583 def _8b : NeonI_Permute<0b0, 0b00, opcode, asmop,
2584 VPR64, "8b", opnode, v8i8>;
2585 def _16b : NeonI_Permute<0b1, 0b00, opcode, asmop,
2586 VPR128, "16b",opnode, v16i8>;
2587 def _4h : NeonI_Permute<0b0, 0b01, opcode, asmop,
2588 VPR64, "4h", opnode, v4i16>;
2589 def _8h : NeonI_Permute<0b1, 0b01, opcode, asmop,
2590 VPR128, "8h", opnode, v8i16>;
2591 def _2s : NeonI_Permute<0b0, 0b10, opcode, asmop,
2592 VPR64, "2s", opnode, v2i32>;
2593 def _4s : NeonI_Permute<0b1, 0b10, opcode, asmop,
2594 VPR128, "4s", opnode, v4i32>;
2595 def _2d : NeonI_Permute<0b1, 0b11, opcode, asmop,
2596 VPR128, "2d", opnode, v2i64>;
2599 defm UZP1vvv : NeonI_Perm_pat<0b001, "uzp1", Neon_uzp1>;
2600 defm TRN1vvv : NeonI_Perm_pat<0b010, "trn1", Neon_trn1>;
2601 defm ZIP1vvv : NeonI_Perm_pat<0b011, "zip1", Neon_zip1>;
2602 defm UZP2vvv : NeonI_Perm_pat<0b101, "uzp2", Neon_uzp2>;
2603 defm TRN2vvv : NeonI_Perm_pat<0b110, "trn2", Neon_trn2>;
2604 defm ZIP2vvv : NeonI_Perm_pat<0b111, "zip2", Neon_zip2>;
2606 multiclass NeonI_Perm_float_pat<string INS, SDPatternOperator opnode> {
2607 def : Pat<(v2f32 (opnode (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
2608 (!cast<Instruction>(INS # "_2s") VPR64:$Rn, VPR64:$Rm)>;
2610 def : Pat<(v4f32 (opnode (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
2611 (!cast<Instruction>(INS # "_4s") VPR128:$Rn, VPR128:$Rm)>;
2613 def : Pat<(v2f64 (opnode (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
2614 (!cast<Instruction>(INS # "_2d") VPR128:$Rn, VPR128:$Rm)>;
2617 defm : NeonI_Perm_float_pat<"UZP1vvv", Neon_uzp1>;
2618 defm : NeonI_Perm_float_pat<"UZP2vvv", Neon_uzp2>;
2619 defm : NeonI_Perm_float_pat<"ZIP1vvv", Neon_zip1>;
2620 defm : NeonI_Perm_float_pat<"ZIP2vvv", Neon_zip2>;
2621 defm : NeonI_Perm_float_pat<"TRN1vvv", Neon_trn1>;
2622 defm : NeonI_Perm_float_pat<"TRN2vvv", Neon_trn2>;
2624 // The followings are for instruction class (3V Diff)
2626 // normal long/long2 pattern
2627 class NeonI_3VDL<bit q, bit u, bits<2> size, bits<4> opcode,
2628 string asmop, string ResS, string OpS,
2629 SDPatternOperator opnode, SDPatternOperator ext,
2630 RegisterOperand OpVPR,
2631 ValueType ResTy, ValueType OpTy>
2632 : NeonI_3VDiff<q, u, size, opcode,
2633 (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2634 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2635 [(set (ResTy VPR128:$Rd),
2636 (ResTy (opnode (ResTy (ext (OpTy OpVPR:$Rn))),
2637 (ResTy (ext (OpTy OpVPR:$Rm))))))],
2640 multiclass NeonI_3VDL_s<bit u, bits<4> opcode,
2641 string asmop, SDPatternOperator opnode,
2642 bit Commutable = 0> {
2643 let isCommutable = Commutable in {
2644 def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2645 opnode, sext, VPR64, v8i16, v8i8>;
2646 def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2647 opnode, sext, VPR64, v4i32, v4i16>;
2648 def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2649 opnode, sext, VPR64, v2i64, v2i32>;
2653 multiclass NeonI_3VDL2_s<bit u, bits<4> opcode, string asmop,
2654 SDPatternOperator opnode, bit Commutable = 0> {
2655 let isCommutable = Commutable in {
2656 def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2657 opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2658 def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2659 opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2660 def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2661 opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2665 multiclass NeonI_3VDL_u<bit u, bits<4> opcode, string asmop,
2666 SDPatternOperator opnode, bit Commutable = 0> {
2667 let isCommutable = Commutable in {
2668 def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2669 opnode, zext, VPR64, v8i16, v8i8>;
2670 def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2671 opnode, zext, VPR64, v4i32, v4i16>;
2672 def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2673 opnode, zext, VPR64, v2i64, v2i32>;
2677 multiclass NeonI_3VDL2_u<bit u, bits<4> opcode, string asmop,
2678 SDPatternOperator opnode, bit Commutable = 0> {
2679 let isCommutable = Commutable in {
2680 def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2681 opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2682 def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2683 opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2684 def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2685 opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2689 defm SADDLvvv : NeonI_3VDL_s<0b0, 0b0000, "saddl", add, 1>;
2690 defm UADDLvvv : NeonI_3VDL_u<0b1, 0b0000, "uaddl", add, 1>;
2692 defm SADDL2vvv : NeonI_3VDL2_s<0b0, 0b0000, "saddl2", add, 1>;
2693 defm UADDL2vvv : NeonI_3VDL2_u<0b1, 0b0000, "uaddl2", add, 1>;
2695 defm SSUBLvvv : NeonI_3VDL_s<0b0, 0b0010, "ssubl", sub, 0>;
2696 defm USUBLvvv : NeonI_3VDL_u<0b1, 0b0010, "usubl", sub, 0>;
2698 defm SSUBL2vvv : NeonI_3VDL2_s<0b0, 0b0010, "ssubl2", sub, 0>;
2699 defm USUBL2vvv : NeonI_3VDL2_u<0b1, 0b0010, "usubl2", sub, 0>;
2701 // normal wide/wide2 pattern
2702 class NeonI_3VDW<bit q, bit u, bits<2> size, bits<4> opcode,
2703 string asmop, string ResS, string OpS,
2704 SDPatternOperator opnode, SDPatternOperator ext,
2705 RegisterOperand OpVPR,
2706 ValueType ResTy, ValueType OpTy>
2707 : NeonI_3VDiff<q, u, size, opcode,
2708 (outs VPR128:$Rd), (ins VPR128:$Rn, OpVPR:$Rm),
2709 asmop # "\t$Rd." # ResS # ", $Rn." # ResS # ", $Rm." # OpS,
2710 [(set (ResTy VPR128:$Rd),
2711 (ResTy (opnode (ResTy VPR128:$Rn),
2712 (ResTy (ext (OpTy OpVPR:$Rm))))))],
2715 multiclass NeonI_3VDW_s<bit u, bits<4> opcode, string asmop,
2716 SDPatternOperator opnode> {
2717 def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2718 opnode, sext, VPR64, v8i16, v8i8>;
2719 def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2720 opnode, sext, VPR64, v4i32, v4i16>;
2721 def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2722 opnode, sext, VPR64, v2i64, v2i32>;
2725 defm SADDWvvv : NeonI_3VDW_s<0b0, 0b0001, "saddw", add>;
2726 defm SSUBWvvv : NeonI_3VDW_s<0b0, 0b0011, "ssubw", sub>;
2728 multiclass NeonI_3VDW2_s<bit u, bits<4> opcode, string asmop,
2729 SDPatternOperator opnode> {
2730 def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2731 opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2732 def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2733 opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2734 def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2735 opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2738 defm SADDW2vvv : NeonI_3VDW2_s<0b0, 0b0001, "saddw2", add>;
2739 defm SSUBW2vvv : NeonI_3VDW2_s<0b0, 0b0011, "ssubw2", sub>;
2741 multiclass NeonI_3VDW_u<bit u, bits<4> opcode, string asmop,
2742 SDPatternOperator opnode> {
2743 def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2744 opnode, zext, VPR64, v8i16, v8i8>;
2745 def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2746 opnode, zext, VPR64, v4i32, v4i16>;
2747 def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2748 opnode, zext, VPR64, v2i64, v2i32>;
2751 defm UADDWvvv : NeonI_3VDW_u<0b1, 0b0001, "uaddw", add>;
2752 defm USUBWvvv : NeonI_3VDW_u<0b1, 0b0011, "usubw", sub>;
2754 multiclass NeonI_3VDW2_u<bit u, bits<4> opcode, string asmop,
2755 SDPatternOperator opnode> {
2756 def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2757 opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2758 def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2759 opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2760 def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2761 opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2764 defm UADDW2vvv : NeonI_3VDW2_u<0b1, 0b0001, "uaddw2", add>;
2765 defm USUBW2vvv : NeonI_3VDW2_u<0b1, 0b0011, "usubw2", sub>;
2767 // Get the high half part of the vector element.
2768 multiclass NeonI_get_high {
2769 def _8h : PatFrag<(ops node:$Rn),
2770 (v8i8 (trunc (v8i16 (srl (v8i16 node:$Rn),
2771 (v8i16 (Neon_vdup (i32 8)))))))>;
2772 def _4s : PatFrag<(ops node:$Rn),
2773 (v4i16 (trunc (v4i32 (srl (v4i32 node:$Rn),
2774 (v4i32 (Neon_vdup (i32 16)))))))>;
2775 def _2d : PatFrag<(ops node:$Rn),
2776 (v2i32 (trunc (v2i64 (srl (v2i64 node:$Rn),
2777 (v2i64 (Neon_vdup (i32 32)))))))>;
2780 defm NI_get_hi : NeonI_get_high;
2782 // pattern for addhn/subhn with 2 operands
2783 class NeonI_3VDN_addhn_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2784 string asmop, string ResS, string OpS,
2785 SDPatternOperator opnode, SDPatternOperator get_hi,
2786 ValueType ResTy, ValueType OpTy>
2787 : NeonI_3VDiff<q, u, size, opcode,
2788 (outs VPR64:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2789 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2790 [(set (ResTy VPR64:$Rd),
2792 (OpTy (opnode (OpTy VPR128:$Rn),
2793 (OpTy VPR128:$Rm))))))],
2796 multiclass NeonI_3VDN_addhn_2Op<bit u, bits<4> opcode, string asmop,
2797 SDPatternOperator opnode, bit Commutable = 0> {
2798 let isCommutable = Commutable in {
2799 def _8b8h : NeonI_3VDN_addhn_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2800 opnode, NI_get_hi_8h, v8i8, v8i16>;
2801 def _4h4s : NeonI_3VDN_addhn_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2802 opnode, NI_get_hi_4s, v4i16, v4i32>;
2803 def _2s2d : NeonI_3VDN_addhn_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2804 opnode, NI_get_hi_2d, v2i32, v2i64>;
2808 defm ADDHNvvv : NeonI_3VDN_addhn_2Op<0b0, 0b0100, "addhn", add, 1>;
2809 defm SUBHNvvv : NeonI_3VDN_addhn_2Op<0b0, 0b0110, "subhn", sub, 0>;
2811 // pattern for operation with 2 operands
2812 class NeonI_3VD_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2813 string asmop, string ResS, string OpS,
2814 SDPatternOperator opnode,
2815 RegisterOperand ResVPR, RegisterOperand OpVPR,
2816 ValueType ResTy, ValueType OpTy>
2817 : NeonI_3VDiff<q, u, size, opcode,
2818 (outs ResVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2819 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2820 [(set (ResTy ResVPR:$Rd),
2821 (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))],
2824 // normal narrow pattern
2825 multiclass NeonI_3VDN_2Op<bit u, bits<4> opcode, string asmop,
2826 SDPatternOperator opnode, bit Commutable = 0> {
2827 let isCommutable = Commutable in {
2828 def _8b8h : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2829 opnode, VPR64, VPR128, v8i8, v8i16>;
2830 def _4h4s : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2831 opnode, VPR64, VPR128, v4i16, v4i32>;
2832 def _2s2d : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2833 opnode, VPR64, VPR128, v2i32, v2i64>;
2837 defm RADDHNvvv : NeonI_3VDN_2Op<0b1, 0b0100, "raddhn", int_arm_neon_vraddhn, 1>;
2838 defm RSUBHNvvv : NeonI_3VDN_2Op<0b1, 0b0110, "rsubhn", int_arm_neon_vrsubhn, 0>;
2840 // pattern for acle intrinsic with 3 operands
2841 class NeonI_3VDN_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2842 string asmop, string ResS, string OpS>
2843 : NeonI_3VDiff<q, u, size, opcode,
2844 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
2845 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2847 let Constraints = "$src = $Rd";
2848 let neverHasSideEffects = 1;
2851 multiclass NeonI_3VDN_3Op_v1<bit u, bits<4> opcode, string asmop> {
2852 def _16b8h : NeonI_3VDN_3Op<0b1, u, 0b00, opcode, asmop, "16b", "8h">;
2853 def _8h4s : NeonI_3VDN_3Op<0b1, u, 0b01, opcode, asmop, "8h", "4s">;
2854 def _4s2d : NeonI_3VDN_3Op<0b1, u, 0b10, opcode, asmop, "4s", "2d">;
2857 defm ADDHN2vvv : NeonI_3VDN_3Op_v1<0b0, 0b0100, "addhn2">;
2858 defm SUBHN2vvv : NeonI_3VDN_3Op_v1<0b0, 0b0110, "subhn2">;
2860 defm RADDHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0100, "raddhn2">;
2861 defm RSUBHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0110, "rsubhn2">;
2863 // Patterns have to be separate because there's a SUBREG_TO_REG in the output
2865 class NarrowHighHalfPat<Instruction INST, ValueType DstTy, ValueType SrcTy,
2866 SDPatternOperator coreop>
2867 : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2868 (v1i64 (bitconvert (DstTy (coreop (SrcTy VPR128:$Rn),
2869 (SrcTy VPR128:$Rm)))))),
2870 (INST (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2871 VPR128:$Rn, VPR128:$Rm)>;
2874 def : NarrowHighHalfPat<ADDHN2vvv_16b8h, v8i8, v8i16,
2875 BinOpFrag<(NI_get_hi_8h (add node:$LHS, node:$RHS))>>;
2876 def : NarrowHighHalfPat<ADDHN2vvv_8h4s, v4i16, v4i32,
2877 BinOpFrag<(NI_get_hi_4s (add node:$LHS, node:$RHS))>>;
2878 def : NarrowHighHalfPat<ADDHN2vvv_4s2d, v2i32, v2i64,
2879 BinOpFrag<(NI_get_hi_2d (add node:$LHS, node:$RHS))>>;
2882 def : NarrowHighHalfPat<SUBHN2vvv_16b8h, v8i8, v8i16,
2883 BinOpFrag<(NI_get_hi_8h (sub node:$LHS, node:$RHS))>>;
2884 def : NarrowHighHalfPat<SUBHN2vvv_8h4s, v4i16, v4i32,
2885 BinOpFrag<(NI_get_hi_4s (sub node:$LHS, node:$RHS))>>;
2886 def : NarrowHighHalfPat<SUBHN2vvv_4s2d, v2i32, v2i64,
2887 BinOpFrag<(NI_get_hi_2d (sub node:$LHS, node:$RHS))>>;
2890 def : NarrowHighHalfPat<RADDHN2vvv_16b8h, v8i8, v8i16, int_arm_neon_vraddhn>;
2891 def : NarrowHighHalfPat<RADDHN2vvv_8h4s, v4i16, v4i32, int_arm_neon_vraddhn>;
2892 def : NarrowHighHalfPat<RADDHN2vvv_4s2d, v2i32, v2i64, int_arm_neon_vraddhn>;
2895 def : NarrowHighHalfPat<RSUBHN2vvv_16b8h, v8i8, v8i16, int_arm_neon_vrsubhn>;
2896 def : NarrowHighHalfPat<RSUBHN2vvv_8h4s, v4i16, v4i32, int_arm_neon_vrsubhn>;
2897 def : NarrowHighHalfPat<RSUBHN2vvv_4s2d, v2i32, v2i64, int_arm_neon_vrsubhn>;
2899 // pattern that need to extend result
2900 class NeonI_3VDL_Ext<bit q, bit u, bits<2> size, bits<4> opcode,
2901 string asmop, string ResS, string OpS,
2902 SDPatternOperator opnode,
2903 RegisterOperand OpVPR,
2904 ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2905 : NeonI_3VDiff<q, u, size, opcode,
2906 (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2907 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2908 [(set (ResTy VPR128:$Rd),
2909 (ResTy (zext (OpSTy (opnode (OpTy OpVPR:$Rn),
2910 (OpTy OpVPR:$Rm))))))],
2913 multiclass NeonI_3VDL_zext<bit u, bits<4> opcode, string asmop,
2914 SDPatternOperator opnode, bit Commutable = 0> {
2915 let isCommutable = Commutable in {
2916 def _8h8b : NeonI_3VDL_Ext<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2917 opnode, VPR64, v8i16, v8i8, v8i8>;
2918 def _4s4h : NeonI_3VDL_Ext<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2919 opnode, VPR64, v4i32, v4i16, v4i16>;
2920 def _2d2s : NeonI_3VDL_Ext<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2921 opnode, VPR64, v2i64, v2i32, v2i32>;
2925 defm SABDLvvv : NeonI_3VDL_zext<0b0, 0b0111, "sabdl", int_arm_neon_vabds, 1>;
2926 defm UABDLvvv : NeonI_3VDL_zext<0b1, 0b0111, "uabdl", int_arm_neon_vabdu, 1>;
2928 multiclass NeonI_Op_High<SDPatternOperator op> {
2929 def _16B : PatFrag<(ops node:$Rn, node:$Rm),
2930 (op (v8i8 (Neon_High16B node:$Rn)),
2931 (v8i8 (Neon_High16B node:$Rm)))>;
2932 def _8H : PatFrag<(ops node:$Rn, node:$Rm),
2933 (op (v4i16 (Neon_High8H node:$Rn)),
2934 (v4i16 (Neon_High8H node:$Rm)))>;
2935 def _4S : PatFrag<(ops node:$Rn, node:$Rm),
2936 (op (v2i32 (Neon_High4S node:$Rn)),
2937 (v2i32 (Neon_High4S node:$Rm)))>;
2940 defm NI_sabdl_hi : NeonI_Op_High<int_arm_neon_vabds>;
2941 defm NI_uabdl_hi : NeonI_Op_High<int_arm_neon_vabdu>;
2942 defm NI_smull_hi : NeonI_Op_High<int_arm_neon_vmulls>;
2943 defm NI_umull_hi : NeonI_Op_High<int_arm_neon_vmullu>;
2944 defm NI_qdmull_hi : NeonI_Op_High<int_arm_neon_vqdmull>;
2945 defm NI_pmull_hi : NeonI_Op_High<int_arm_neon_vmullp>;
2947 multiclass NeonI_3VDL_Abd_u<bit u, bits<4> opcode, string asmop, string opnode,
2948 bit Commutable = 0> {
2949 let isCommutable = Commutable in {
2950 def _8h8b : NeonI_3VDL_Ext<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2951 !cast<PatFrag>(opnode # "_16B"),
2952 VPR128, v8i16, v16i8, v8i8>;
2953 def _4s4h : NeonI_3VDL_Ext<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2954 !cast<PatFrag>(opnode # "_8H"),
2955 VPR128, v4i32, v8i16, v4i16>;
2956 def _2d2s : NeonI_3VDL_Ext<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2957 !cast<PatFrag>(opnode # "_4S"),
2958 VPR128, v2i64, v4i32, v2i32>;
2962 defm SABDL2vvv : NeonI_3VDL_Abd_u<0b0, 0b0111, "sabdl2", "NI_sabdl_hi", 1>;
2963 defm UABDL2vvv : NeonI_3VDL_Abd_u<0b1, 0b0111, "uabdl2", "NI_uabdl_hi", 1>;
2965 // For pattern that need two operators being chained.
2966 class NeonI_3VDL_Aba<bit q, bit u, bits<2> size, bits<4> opcode,
2967 string asmop, string ResS, string OpS,
2968 SDPatternOperator opnode, SDPatternOperator subop,
2969 RegisterOperand OpVPR,
2970 ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2971 : NeonI_3VDiff<q, u, size, opcode,
2972 (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2973 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2974 [(set (ResTy VPR128:$Rd),
2976 (ResTy VPR128:$src),
2977 (ResTy (zext (OpSTy (subop (OpTy OpVPR:$Rn),
2978 (OpTy OpVPR:$Rm))))))))],
2980 let Constraints = "$src = $Rd";
2983 multiclass NeonI_3VDL_Aba_v1<bit u, bits<4> opcode, string asmop,
2984 SDPatternOperator opnode, SDPatternOperator subop>{
2985 def _8h8b : NeonI_3VDL_Aba<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2986 opnode, subop, VPR64, v8i16, v8i8, v8i8>;
2987 def _4s4h : NeonI_3VDL_Aba<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2988 opnode, subop, VPR64, v4i32, v4i16, v4i16>;
2989 def _2d2s : NeonI_3VDL_Aba<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2990 opnode, subop, VPR64, v2i64, v2i32, v2i32>;
2993 defm SABALvvv : NeonI_3VDL_Aba_v1<0b0, 0b0101, "sabal",
2994 add, int_arm_neon_vabds>;
2995 defm UABALvvv : NeonI_3VDL_Aba_v1<0b1, 0b0101, "uabal",
2996 add, int_arm_neon_vabdu>;
2998 multiclass NeonI_3VDL2_Aba_v1<bit u, bits<4> opcode, string asmop,
2999 SDPatternOperator opnode, string subop> {
3000 def _8h8b : NeonI_3VDL_Aba<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3001 opnode, !cast<PatFrag>(subop # "_16B"),
3002 VPR128, v8i16, v16i8, v8i8>;
3003 def _4s4h : NeonI_3VDL_Aba<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3004 opnode, !cast<PatFrag>(subop # "_8H"),
3005 VPR128, v4i32, v8i16, v4i16>;
3006 def _2d2s : NeonI_3VDL_Aba<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3007 opnode, !cast<PatFrag>(subop # "_4S"),
3008 VPR128, v2i64, v4i32, v2i32>;
3011 defm SABAL2vvv : NeonI_3VDL2_Aba_v1<0b0, 0b0101, "sabal2", add,
3013 defm UABAL2vvv : NeonI_3VDL2_Aba_v1<0b1, 0b0101, "uabal2", add,
3016 // Long pattern with 2 operands
3017 multiclass NeonI_3VDL_2Op<bit u, bits<4> opcode, string asmop,
3018 SDPatternOperator opnode, bit Commutable = 0> {
3019 let isCommutable = Commutable in {
3020 def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3021 opnode, VPR128, VPR64, v8i16, v8i8>;
3022 def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3023 opnode, VPR128, VPR64, v4i32, v4i16>;
3024 def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3025 opnode, VPR128, VPR64, v2i64, v2i32>;
3029 defm SMULLvvv : NeonI_3VDL_2Op<0b0, 0b1100, "smull", int_arm_neon_vmulls, 1>;
3030 defm UMULLvvv : NeonI_3VDL_2Op<0b1, 0b1100, "umull", int_arm_neon_vmullu, 1>;
3032 class NeonI_3VDL2_2Op_mull<bit q, bit u, bits<2> size, bits<4> opcode,
3033 string asmop, string ResS, string OpS,
3034 SDPatternOperator opnode,
3035 ValueType ResTy, ValueType OpTy>
3036 : NeonI_3VDiff<q, u, size, opcode,
3037 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3038 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3039 [(set (ResTy VPR128:$Rd),
3040 (ResTy (opnode (OpTy VPR128:$Rn), (OpTy VPR128:$Rm))))],
3043 multiclass NeonI_3VDL2_2Op_mull_v1<bit u, bits<4> opcode, string asmop,
3044 string opnode, bit Commutable = 0> {
3045 let isCommutable = Commutable in {
3046 def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3047 !cast<PatFrag>(opnode # "_16B"),
3049 def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3050 !cast<PatFrag>(opnode # "_8H"),
3052 def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3053 !cast<PatFrag>(opnode # "_4S"),
3058 defm SMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b0, 0b1100, "smull2",
3060 defm UMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b1, 0b1100, "umull2",
3063 // Long pattern with 3 operands
3064 class NeonI_3VDL_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
3065 string asmop, string ResS, string OpS,
3066 SDPatternOperator opnode,
3067 ValueType ResTy, ValueType OpTy>
3068 : NeonI_3VDiff<q, u, size, opcode,
3069 (outs VPR128:$Rd), (ins VPR128:$src, VPR64:$Rn, VPR64:$Rm),
3070 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3071 [(set (ResTy VPR128:$Rd),
3073 (ResTy VPR128:$src),
3074 (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))))],
3076 let Constraints = "$src = $Rd";
3079 multiclass NeonI_3VDL_3Op_v1<bit u, bits<4> opcode, string asmop,
3080 SDPatternOperator opnode> {
3081 def _8h8b : NeonI_3VDL_3Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3082 opnode, v8i16, v8i8>;
3083 def _4s4h : NeonI_3VDL_3Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3084 opnode, v4i32, v4i16>;
3085 def _2d2s : NeonI_3VDL_3Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3086 opnode, v2i64, v2i32>;
3089 def Neon_smlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3091 (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
3093 def Neon_umlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3095 (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
3097 def Neon_smlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3099 (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
3101 def Neon_umlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3103 (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
3105 defm SMLALvvv : NeonI_3VDL_3Op_v1<0b0, 0b1000, "smlal", Neon_smlal>;
3106 defm UMLALvvv : NeonI_3VDL_3Op_v1<0b1, 0b1000, "umlal", Neon_umlal>;
3108 defm SMLSLvvv : NeonI_3VDL_3Op_v1<0b0, 0b1010, "smlsl", Neon_smlsl>;
3109 defm UMLSLvvv : NeonI_3VDL_3Op_v1<0b1, 0b1010, "umlsl", Neon_umlsl>;
3111 class NeonI_3VDL2_3Op_mlas<bit q, bit u, bits<2> size, bits<4> opcode,
3112 string asmop, string ResS, string OpS,
3113 SDPatternOperator subop, SDPatternOperator opnode,
3114 RegisterOperand OpVPR,
3115 ValueType ResTy, ValueType OpTy>
3116 : NeonI_3VDiff<q, u, size, opcode,
3117 (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
3118 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3119 [(set (ResTy VPR128:$Rd),
3121 (ResTy VPR128:$src),
3122 (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))))],
3124 let Constraints = "$src = $Rd";
3127 multiclass NeonI_3VDL2_3Op_mlas_v1<bit u, bits<4> opcode, string asmop,
3128 SDPatternOperator subop, string opnode> {
3129 def _8h16b : NeonI_3VDL2_3Op_mlas<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3130 subop, !cast<PatFrag>(opnode # "_16B"),
3131 VPR128, v8i16, v16i8>;
3132 def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3133 subop, !cast<PatFrag>(opnode # "_8H"),
3134 VPR128, v4i32, v8i16>;
3135 def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3136 subop, !cast<PatFrag>(opnode # "_4S"),
3137 VPR128, v2i64, v4i32>;
3140 defm SMLAL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1000, "smlal2",
3141 add, "NI_smull_hi">;
3142 defm UMLAL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1000, "umlal2",
3143 add, "NI_umull_hi">;
3145 defm SMLSL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1010, "smlsl2",
3146 sub, "NI_smull_hi">;
3147 defm UMLSL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1010, "umlsl2",
3148 sub, "NI_umull_hi">;
3150 multiclass NeonI_3VDL_qdmlal_3Op_v2<bit u, bits<4> opcode, string asmop,
3151 SDPatternOperator opnode> {
3152 def _4s4h : NeonI_3VDL2_3Op_mlas<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3153 opnode, int_arm_neon_vqdmull,
3154 VPR64, v4i32, v4i16>;
3155 def _2d2s : NeonI_3VDL2_3Op_mlas<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3156 opnode, int_arm_neon_vqdmull,
3157 VPR64, v2i64, v2i32>;
3160 defm SQDMLALvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1001, "sqdmlal",
3161 int_arm_neon_vqadds>;
3162 defm SQDMLSLvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1011, "sqdmlsl",
3163 int_arm_neon_vqsubs>;
3165 multiclass NeonI_3VDL_v2<bit u, bits<4> opcode, string asmop,
3166 SDPatternOperator opnode, bit Commutable = 0> {
3167 let isCommutable = Commutable in {
3168 def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3169 opnode, VPR128, VPR64, v4i32, v4i16>;
3170 def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3171 opnode, VPR128, VPR64, v2i64, v2i32>;
3175 defm SQDMULLvvv : NeonI_3VDL_v2<0b0, 0b1101, "sqdmull",
3176 int_arm_neon_vqdmull, 1>;
3178 multiclass NeonI_3VDL2_2Op_mull_v2<bit u, bits<4> opcode, string asmop,
3179 string opnode, bit Commutable = 0> {
3180 let isCommutable = Commutable in {
3181 def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3182 !cast<PatFrag>(opnode # "_8H"),
3184 def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3185 !cast<PatFrag>(opnode # "_4S"),
3190 defm SQDMULL2vvv : NeonI_3VDL2_2Op_mull_v2<0b0, 0b1101, "sqdmull2",
3193 multiclass NeonI_3VDL2_3Op_qdmlal_v2<bit u, bits<4> opcode, string asmop,
3194 SDPatternOperator opnode> {
3195 def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3196 opnode, NI_qdmull_hi_8H,
3197 VPR128, v4i32, v8i16>;
3198 def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3199 opnode, NI_qdmull_hi_4S,
3200 VPR128, v2i64, v4i32>;
3203 defm SQDMLAL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1001, "sqdmlal2",
3204 int_arm_neon_vqadds>;
3205 defm SQDMLSL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1011, "sqdmlsl2",
3206 int_arm_neon_vqsubs>;
3208 multiclass NeonI_3VDL_v3<bit u, bits<4> opcode, string asmop,
3209 SDPatternOperator opnode_8h8b,
3210 SDPatternOperator opnode_1q1d, bit Commutable = 0> {
3211 let isCommutable = Commutable in {
3212 def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3213 opnode_8h8b, VPR128, VPR64, v8i16, v8i8>;
3215 def _1q1d : NeonI_3VD_2Op<0b0, u, 0b11, opcode, asmop, "1q", "1d",
3216 opnode_1q1d, VPR128, VPR64, v16i8, v1i64>;
3220 defm PMULLvvv : NeonI_3VDL_v3<0b0, 0b1110, "pmull", int_arm_neon_vmullp,
3221 int_aarch64_neon_vmull_p64, 1>;
3223 multiclass NeonI_3VDL2_2Op_mull_v3<bit u, bits<4> opcode, string asmop,
3224 string opnode, bit Commutable = 0> {
3225 let isCommutable = Commutable in {
3226 def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3227 !cast<PatFrag>(opnode # "_16B"),
3231 NeonI_3VDiff<0b1, u, 0b11, opcode,
3232 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3233 asmop # "\t$Rd.1q, $Rn.2d, $Rm.2d",
3234 [(set (v16i8 VPR128:$Rd),
3235 (v16i8 (int_aarch64_neon_vmull_p64
3236 (v1i64 (scalar_to_vector
3237 (i64 (vector_extract (v2i64 VPR128:$Rn), 1)))),
3238 (v1i64 (scalar_to_vector
3239 (i64 (vector_extract (v2i64 VPR128:$Rm), 1)))))))],
3244 defm PMULL2vvv : NeonI_3VDL2_2Op_mull_v3<0b0, 0b1110, "pmull2", "NI_pmull_hi",
3247 // End of implementation for instruction class (3V Diff)
3249 // The followings are vector load/store multiple N-element structure
3250 // (class SIMD lselem).
3252 // ld1: load multiple 1-element structure to 1/2/3/4 registers.
3253 // ld2/ld3/ld4: load multiple N-element structure to N registers (N = 2, 3, 4).
3254 // The structure consists of a sequence of sets of N values.
3255 // The first element of the structure is placed in the first lane
3256 // of the first first vector, the second element in the first lane
3257 // of the second vector, and so on.
3258 // E.g. LD1_3V_2S will load 32-bit elements {A, B, C, D, E, F} sequentially into
3259 // the three 64-bit vectors list {BA, DC, FE}.
3260 // E.g. LD3_2S will load 32-bit elements {A, B, C, D, E, F} into the three
3261 // 64-bit vectors list {DA, EB, FC}.
3262 // Store instructions store multiple structure to N registers like load.
3265 class NeonI_LDVList<bit q, bits<4> opcode, bits<2> size,
3266 RegisterOperand VecList, string asmop>
3267 : NeonI_LdStMult<q, 1, opcode, size,
3268 (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3269 asmop # "\t$Rt, [$Rn]",
3273 let neverHasSideEffects = 1;
3276 multiclass LDVList_BHSD<bits<4> opcode, string List, string asmop> {
3277 def _8B : NeonI_LDVList<0, opcode, 0b00,
3278 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3280 def _4H : NeonI_LDVList<0, opcode, 0b01,
3281 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3283 def _2S : NeonI_LDVList<0, opcode, 0b10,
3284 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3286 def _16B : NeonI_LDVList<1, opcode, 0b00,
3287 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3289 def _8H : NeonI_LDVList<1, opcode, 0b01,
3290 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3292 def _4S : NeonI_LDVList<1, opcode, 0b10,
3293 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3295 def _2D : NeonI_LDVList<1, opcode, 0b11,
3296 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3299 // Load multiple N-element structure to N consecutive registers (N = 1,2,3,4)
3300 defm LD1 : LDVList_BHSD<0b0111, "VOne", "ld1">;
3301 def LD1_1D : NeonI_LDVList<0, 0b0111, 0b11, VOne1D_operand, "ld1">;
3303 defm LD2 : LDVList_BHSD<0b1000, "VPair", "ld2">;
3305 defm LD3 : LDVList_BHSD<0b0100, "VTriple", "ld3">;
3307 defm LD4 : LDVList_BHSD<0b0000, "VQuad", "ld4">;
3309 // Load multiple 1-element structure to N consecutive registers (N = 2,3,4)
3310 defm LD1x2 : LDVList_BHSD<0b1010, "VPair", "ld1">;
3311 def LD1x2_1D : NeonI_LDVList<0, 0b1010, 0b11, VPair1D_operand, "ld1">;
3313 defm LD1x3 : LDVList_BHSD<0b0110, "VTriple", "ld1">;
3314 def LD1x3_1D : NeonI_LDVList<0, 0b0110, 0b11, VTriple1D_operand, "ld1">;
3316 defm LD1x4 : LDVList_BHSD<0b0010, "VQuad", "ld1">;
3317 def LD1x4_1D : NeonI_LDVList<0, 0b0010, 0b11, VQuad1D_operand, "ld1">;
3319 class NeonI_STVList<bit q, bits<4> opcode, bits<2> size,
3320 RegisterOperand VecList, string asmop>
3321 : NeonI_LdStMult<q, 0, opcode, size,
3322 (outs), (ins GPR64xsp:$Rn, VecList:$Rt),
3323 asmop # "\t$Rt, [$Rn]",
3327 let neverHasSideEffects = 1;
3330 multiclass STVList_BHSD<bits<4> opcode, string List, string asmop> {
3331 def _8B : NeonI_STVList<0, opcode, 0b00,
3332 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3334 def _4H : NeonI_STVList<0, opcode, 0b01,
3335 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3337 def _2S : NeonI_STVList<0, opcode, 0b10,
3338 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3340 def _16B : NeonI_STVList<1, opcode, 0b00,
3341 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3343 def _8H : NeonI_STVList<1, opcode, 0b01,
3344 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3346 def _4S : NeonI_STVList<1, opcode, 0b10,
3347 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3349 def _2D : NeonI_STVList<1, opcode, 0b11,
3350 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3353 // Store multiple N-element structures from N registers (N = 1,2,3,4)
3354 defm ST1 : STVList_BHSD<0b0111, "VOne", "st1">;
3355 def ST1_1D : NeonI_STVList<0, 0b0111, 0b11, VOne1D_operand, "st1">;
3357 defm ST2 : STVList_BHSD<0b1000, "VPair", "st2">;
3359 defm ST3 : STVList_BHSD<0b0100, "VTriple", "st3">;
3361 defm ST4 : STVList_BHSD<0b0000, "VQuad", "st4">;
3363 // Store multiple 1-element structures from N consecutive registers (N = 2,3,4)
3364 defm ST1x2 : STVList_BHSD<0b1010, "VPair", "st1">;
3365 def ST1x2_1D : NeonI_STVList<0, 0b1010, 0b11, VPair1D_operand, "st1">;
3367 defm ST1x3 : STVList_BHSD<0b0110, "VTriple", "st1">;
3368 def ST1x3_1D : NeonI_STVList<0, 0b0110, 0b11, VTriple1D_operand, "st1">;
3370 defm ST1x4 : STVList_BHSD<0b0010, "VQuad", "st1">;
3371 def ST1x4_1D : NeonI_STVList<0, 0b0010, 0b11, VQuad1D_operand, "st1">;
3373 def : Pat<(v2f64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3374 def : Pat<(v2i64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3376 def : Pat<(v4f32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3377 def : Pat<(v4i32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3379 def : Pat<(v8i16 (load GPR64xsp:$addr)), (LD1_8H GPR64xsp:$addr)>;
3380 def : Pat<(v16i8 (load GPR64xsp:$addr)), (LD1_16B GPR64xsp:$addr)>;
3382 def : Pat<(v1f64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3383 def : Pat<(v1i64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3385 def : Pat<(v2f32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3386 def : Pat<(v2i32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3388 def : Pat<(v4i16 (load GPR64xsp:$addr)), (LD1_4H GPR64xsp:$addr)>;
3389 def : Pat<(v8i8 (load GPR64xsp:$addr)), (LD1_8B GPR64xsp:$addr)>;
3391 def : Pat<(store (v2i64 VPR128:$value), GPR64xsp:$addr),
3392 (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3393 def : Pat<(store (v2f64 VPR128:$value), GPR64xsp:$addr),
3394 (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3396 def : Pat<(store (v4i32 VPR128:$value), GPR64xsp:$addr),
3397 (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3398 def : Pat<(store (v4f32 VPR128:$value), GPR64xsp:$addr),
3399 (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3401 def : Pat<(store (v8i16 VPR128:$value), GPR64xsp:$addr),
3402 (ST1_8H GPR64xsp:$addr, VPR128:$value)>;
3403 def : Pat<(store (v16i8 VPR128:$value), GPR64xsp:$addr),
3404 (ST1_16B GPR64xsp:$addr, VPR128:$value)>;
3406 def : Pat<(store (v1i64 VPR64:$value), GPR64xsp:$addr),
3407 (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3408 def : Pat<(store (v1f64 VPR64:$value), GPR64xsp:$addr),
3409 (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3411 def : Pat<(store (v2i32 VPR64:$value), GPR64xsp:$addr),
3412 (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3413 def : Pat<(store (v2f32 VPR64:$value), GPR64xsp:$addr),
3414 (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3416 def : Pat<(store (v4i16 VPR64:$value), GPR64xsp:$addr),
3417 (ST1_4H GPR64xsp:$addr, VPR64:$value)>;
3418 def : Pat<(store (v8i8 VPR64:$value), GPR64xsp:$addr),
3419 (ST1_8B GPR64xsp:$addr, VPR64:$value)>;
3421 // Match load/store of v1i8/v1i16/v1i32 type to FPR8/FPR16/FPR32 load/store.
3422 // FIXME: for now we have v1i8, v1i16, v1i32 legal types, if they are illegal,
3423 // these patterns are not needed any more.
3424 def : Pat<(v1i8 (load GPR64xsp:$addr)), (LSFP8_LDR $addr, 0)>;
3425 def : Pat<(v1i16 (load GPR64xsp:$addr)), (LSFP16_LDR $addr, 0)>;
3426 def : Pat<(v1i32 (load GPR64xsp:$addr)), (LSFP32_LDR $addr, 0)>;
3428 def : Pat<(store (v1i8 FPR8:$value), GPR64xsp:$addr),
3429 (LSFP8_STR $value, $addr, 0)>;
3430 def : Pat<(store (v1i16 FPR16:$value), GPR64xsp:$addr),
3431 (LSFP16_STR $value, $addr, 0)>;
3432 def : Pat<(store (v1i32 FPR32:$value), GPR64xsp:$addr),
3433 (LSFP32_STR $value, $addr, 0)>;
3436 // End of vector load/store multiple N-element structure(class SIMD lselem)
3438 // The followings are post-index vector load/store multiple N-element
3439 // structure(class SIMD lselem-post)
3440 def exact1_asmoperand : AsmOperandClass {
3441 let Name = "Exact1";
3442 let PredicateMethod = "isExactImm<1>";
3443 let RenderMethod = "addImmOperands";
3445 def uimm_exact1 : Operand<i32>, ImmLeaf<i32, [{return Imm == 1;}]> {
3446 let ParserMatchClass = exact1_asmoperand;
3449 def exact2_asmoperand : AsmOperandClass {
3450 let Name = "Exact2";
3451 let PredicateMethod = "isExactImm<2>";
3452 let RenderMethod = "addImmOperands";
3454 def uimm_exact2 : Operand<i32>, ImmLeaf<i32, [{return Imm == 2;}]> {
3455 let ParserMatchClass = exact2_asmoperand;
3458 def exact3_asmoperand : AsmOperandClass {
3459 let Name = "Exact3";
3460 let PredicateMethod = "isExactImm<3>";
3461 let RenderMethod = "addImmOperands";
3463 def uimm_exact3 : Operand<i32>, ImmLeaf<i32, [{return Imm == 3;}]> {
3464 let ParserMatchClass = exact3_asmoperand;
3467 def exact4_asmoperand : AsmOperandClass {
3468 let Name = "Exact4";
3469 let PredicateMethod = "isExactImm<4>";
3470 let RenderMethod = "addImmOperands";
3472 def uimm_exact4 : Operand<i32>, ImmLeaf<i32, [{return Imm == 4;}]> {
3473 let ParserMatchClass = exact4_asmoperand;
3476 def exact6_asmoperand : AsmOperandClass {
3477 let Name = "Exact6";
3478 let PredicateMethod = "isExactImm<6>";
3479 let RenderMethod = "addImmOperands";
3481 def uimm_exact6 : Operand<i32>, ImmLeaf<i32, [{return Imm == 6;}]> {
3482 let ParserMatchClass = exact6_asmoperand;
3485 def exact8_asmoperand : AsmOperandClass {
3486 let Name = "Exact8";
3487 let PredicateMethod = "isExactImm<8>";
3488 let RenderMethod = "addImmOperands";
3490 def uimm_exact8 : Operand<i32>, ImmLeaf<i32, [{return Imm == 8;}]> {
3491 let ParserMatchClass = exact8_asmoperand;
3494 def exact12_asmoperand : AsmOperandClass {
3495 let Name = "Exact12";
3496 let PredicateMethod = "isExactImm<12>";
3497 let RenderMethod = "addImmOperands";
3499 def uimm_exact12 : Operand<i32>, ImmLeaf<i32, [{return Imm == 12;}]> {
3500 let ParserMatchClass = exact12_asmoperand;
3503 def exact16_asmoperand : AsmOperandClass {
3504 let Name = "Exact16";
3505 let PredicateMethod = "isExactImm<16>";
3506 let RenderMethod = "addImmOperands";
3508 def uimm_exact16 : Operand<i32>, ImmLeaf<i32, [{return Imm == 16;}]> {
3509 let ParserMatchClass = exact16_asmoperand;
3512 def exact24_asmoperand : AsmOperandClass {
3513 let Name = "Exact24";
3514 let PredicateMethod = "isExactImm<24>";
3515 let RenderMethod = "addImmOperands";
3517 def uimm_exact24 : Operand<i32>, ImmLeaf<i32, [{return Imm == 24;}]> {
3518 let ParserMatchClass = exact24_asmoperand;
3521 def exact32_asmoperand : AsmOperandClass {
3522 let Name = "Exact32";
3523 let PredicateMethod = "isExactImm<32>";
3524 let RenderMethod = "addImmOperands";
3526 def uimm_exact32 : Operand<i32>, ImmLeaf<i32, [{return Imm == 32;}]> {
3527 let ParserMatchClass = exact32_asmoperand;
3530 def exact48_asmoperand : AsmOperandClass {
3531 let Name = "Exact48";
3532 let PredicateMethod = "isExactImm<48>";
3533 let RenderMethod = "addImmOperands";
3535 def uimm_exact48 : Operand<i32>, ImmLeaf<i32, [{return Imm == 48;}]> {
3536 let ParserMatchClass = exact48_asmoperand;
3539 def exact64_asmoperand : AsmOperandClass {
3540 let Name = "Exact64";
3541 let PredicateMethod = "isExactImm<64>";
3542 let RenderMethod = "addImmOperands";
3544 def uimm_exact64 : Operand<i32>, ImmLeaf<i32, [{return Imm == 64;}]> {
3545 let ParserMatchClass = exact64_asmoperand;
3548 multiclass NeonI_LDWB_VList<bit q, bits<4> opcode, bits<2> size,
3549 RegisterOperand VecList, Operand ImmTy,
3551 let Constraints = "$Rn = $wb", mayLoad = 1, neverHasSideEffects = 1,
3552 DecoderMethod = "DecodeVLDSTPostInstruction" in {
3553 def _fixed : NeonI_LdStMult_Post<q, 1, opcode, size,
3554 (outs VecList:$Rt, GPR64xsp:$wb),
3555 (ins GPR64xsp:$Rn, ImmTy:$amt),
3556 asmop # "\t$Rt, [$Rn], $amt",
3562 def _register : NeonI_LdStMult_Post<q, 1, opcode, size,
3563 (outs VecList:$Rt, GPR64xsp:$wb),
3564 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3565 asmop # "\t$Rt, [$Rn], $Rm",
3571 multiclass LDWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3572 Operand ImmTy2, string asmop> {
3573 defm _8B : NeonI_LDWB_VList<0, opcode, 0b00,
3574 !cast<RegisterOperand>(List # "8B_operand"),
3577 defm _4H : NeonI_LDWB_VList<0, opcode, 0b01,
3578 !cast<RegisterOperand>(List # "4H_operand"),
3581 defm _2S : NeonI_LDWB_VList<0, opcode, 0b10,
3582 !cast<RegisterOperand>(List # "2S_operand"),
3585 defm _16B : NeonI_LDWB_VList<1, opcode, 0b00,
3586 !cast<RegisterOperand>(List # "16B_operand"),
3589 defm _8H : NeonI_LDWB_VList<1, opcode, 0b01,
3590 !cast<RegisterOperand>(List # "8H_operand"),
3593 defm _4S : NeonI_LDWB_VList<1, opcode, 0b10,
3594 !cast<RegisterOperand>(List # "4S_operand"),
3597 defm _2D : NeonI_LDWB_VList<1, opcode, 0b11,
3598 !cast<RegisterOperand>(List # "2D_operand"),
3602 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3603 defm LD1WB : LDWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "ld1">;
3604 defm LD1WB_1D : NeonI_LDWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3607 defm LD2WB : LDWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "ld2">;
3609 defm LD3WB : LDWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3612 defm LD4WB : LDWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "ld4">;
3614 // Post-index load multiple 1-element structures from N consecutive registers
3616 defm LD1x2WB : LDWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3618 defm LD1x2WB_1D : NeonI_LDWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3619 uimm_exact16, "ld1">;
3621 defm LD1x3WB : LDWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3623 defm LD1x3WB_1D : NeonI_LDWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3624 uimm_exact24, "ld1">;
3626 defm LD1x4WB : LDWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3628 defm LD1x4WB_1D : NeonI_LDWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3629 uimm_exact32, "ld1">;
3631 multiclass NeonI_STWB_VList<bit q, bits<4> opcode, bits<2> size,
3632 RegisterOperand VecList, Operand ImmTy,
3634 let Constraints = "$Rn = $wb", mayStore = 1, neverHasSideEffects = 1,
3635 DecoderMethod = "DecodeVLDSTPostInstruction" in {
3636 def _fixed : NeonI_LdStMult_Post<q, 0, opcode, size,
3637 (outs GPR64xsp:$wb),
3638 (ins GPR64xsp:$Rn, ImmTy:$amt, VecList:$Rt),
3639 asmop # "\t$Rt, [$Rn], $amt",
3645 def _register : NeonI_LdStMult_Post<q, 0, opcode, size,
3646 (outs GPR64xsp:$wb),
3647 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VecList:$Rt),
3648 asmop # "\t$Rt, [$Rn], $Rm",
3654 multiclass STWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3655 Operand ImmTy2, string asmop> {
3656 defm _8B : NeonI_STWB_VList<0, opcode, 0b00,
3657 !cast<RegisterOperand>(List # "8B_operand"), ImmTy, asmop>;
3659 defm _4H : NeonI_STWB_VList<0, opcode, 0b01,
3660 !cast<RegisterOperand>(List # "4H_operand"),
3663 defm _2S : NeonI_STWB_VList<0, opcode, 0b10,
3664 !cast<RegisterOperand>(List # "2S_operand"),
3667 defm _16B : NeonI_STWB_VList<1, opcode, 0b00,
3668 !cast<RegisterOperand>(List # "16B_operand"),
3671 defm _8H : NeonI_STWB_VList<1, opcode, 0b01,
3672 !cast<RegisterOperand>(List # "8H_operand"),
3675 defm _4S : NeonI_STWB_VList<1, opcode, 0b10,
3676 !cast<RegisterOperand>(List # "4S_operand"),
3679 defm _2D : NeonI_STWB_VList<1, opcode, 0b11,
3680 !cast<RegisterOperand>(List # "2D_operand"),
3684 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3685 defm ST1WB : STWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "st1">;
3686 defm ST1WB_1D : NeonI_STWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3689 defm ST2WB : STWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "st2">;
3691 defm ST3WB : STWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3694 defm ST4WB : STWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "st4">;
3696 // Post-index load multiple 1-element structures from N consecutive registers
3698 defm ST1x2WB : STWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3700 defm ST1x2WB_1D : NeonI_STWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3701 uimm_exact16, "st1">;
3703 defm ST1x3WB : STWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3705 defm ST1x3WB_1D : NeonI_STWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3706 uimm_exact24, "st1">;
3708 defm ST1x4WB : STWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3710 defm ST1x4WB_1D : NeonI_STWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3711 uimm_exact32, "st1">;
3713 // End of post-index vector load/store multiple N-element structure
3714 // (class SIMD lselem-post)
3716 // The followings are vector load/store single N-element structure
3717 // (class SIMD lsone).
3718 def neon_uimm0_bare : Operand<i64>,
3719 ImmLeaf<i64, [{return Imm == 0;}]> {
3720 let ParserMatchClass = neon_uimm0_asmoperand;
3721 let PrintMethod = "printUImmBareOperand";
3724 def neon_uimm1_bare : Operand<i64>,
3725 ImmLeaf<i64, [{return Imm < 2;}]> {
3726 let ParserMatchClass = neon_uimm1_asmoperand;
3727 let PrintMethod = "printUImmBareOperand";
3730 def neon_uimm2_bare : Operand<i64>,
3731 ImmLeaf<i64, [{return Imm < 4;}]> {
3732 let ParserMatchClass = neon_uimm2_asmoperand;
3733 let PrintMethod = "printUImmBareOperand";
3736 def neon_uimm3_bare : Operand<i64>,
3737 ImmLeaf<i64, [{return Imm < 8;}]> {
3738 let ParserMatchClass = uimm3_asmoperand;
3739 let PrintMethod = "printUImmBareOperand";
3742 def neon_uimm4_bare : Operand<i64>,
3743 ImmLeaf<i64, [{return Imm < 16;}]> {
3744 let ParserMatchClass = uimm4_asmoperand;
3745 let PrintMethod = "printUImmBareOperand";
3748 class NeonI_LDN_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3749 RegisterOperand VecList, string asmop>
3750 : NeonI_LdOne_Dup<q, r, opcode, size,
3751 (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3752 asmop # "\t$Rt, [$Rn]",
3756 let neverHasSideEffects = 1;
3759 multiclass LDN_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop> {
3760 def _8B : NeonI_LDN_Dup<0, r, opcode, 0b00,
3761 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3763 def _4H : NeonI_LDN_Dup<0, r, opcode, 0b01,
3764 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3766 def _2S : NeonI_LDN_Dup<0, r, opcode, 0b10,
3767 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3769 def _1D : NeonI_LDN_Dup<0, r, opcode, 0b11,
3770 !cast<RegisterOperand>(List # "1D_operand"), asmop>;
3772 def _16B : NeonI_LDN_Dup<1, r, opcode, 0b00,
3773 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3775 def _8H : NeonI_LDN_Dup<1, r, opcode, 0b01,
3776 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3778 def _4S : NeonI_LDN_Dup<1, r, opcode, 0b10,
3779 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3781 def _2D : NeonI_LDN_Dup<1, r, opcode, 0b11,
3782 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3785 // Load single 1-element structure to all lanes of 1 register
3786 defm LD1R : LDN_Dup_BHSD<0b0, 0b110, "VOne", "ld1r">;
3788 // Load single N-element structure to all lanes of N consecutive
3789 // registers (N = 2,3,4)
3790 defm LD2R : LDN_Dup_BHSD<0b1, 0b110, "VPair", "ld2r">;
3791 defm LD3R : LDN_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r">;
3792 defm LD4R : LDN_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r">;
3795 class LD1R_pattern <ValueType VTy, ValueType DTy, PatFrag LoadOp,
3797 : Pat<(VTy (Neon_vdup (DTy (LoadOp GPR64xsp:$Rn)))),
3798 (VTy (INST GPR64xsp:$Rn))>;
3800 // Match all LD1R instructions
3801 def : LD1R_pattern<v8i8, i32, extloadi8, LD1R_8B>;
3803 def : LD1R_pattern<v16i8, i32, extloadi8, LD1R_16B>;
3805 def : LD1R_pattern<v4i16, i32, extloadi16, LD1R_4H>;
3807 def : LD1R_pattern<v8i16, i32, extloadi16, LD1R_8H>;
3809 def : LD1R_pattern<v2i32, i32, load, LD1R_2S>;
3810 def : LD1R_pattern<v2f32, f32, load, LD1R_2S>;
3812 def : LD1R_pattern<v4i32, i32, load, LD1R_4S>;
3813 def : LD1R_pattern<v4f32, f32, load, LD1R_4S>;
3815 def : LD1R_pattern<v2i64, i64, load, LD1R_2D>;
3816 def : LD1R_pattern<v2f64, f64, load, LD1R_2D>;
3818 class LD1R_pattern_v1 <ValueType VTy, ValueType DTy, PatFrag LoadOp,
3820 : Pat<(VTy (scalar_to_vector (DTy (LoadOp GPR64xsp:$Rn)))),
3821 (VTy (INST GPR64xsp:$Rn))>;
3823 def : LD1R_pattern_v1<v1i64, i64, load, LD1R_1D>;
3824 def : LD1R_pattern_v1<v1f64, f64, load, LD1R_1D>;
3826 multiclass VectorList_Bare_BHSD<string PREFIX, int Count,
3827 RegisterClass RegList> {
3828 defm B : VectorList_operands<PREFIX, "B", Count, RegList>;
3829 defm H : VectorList_operands<PREFIX, "H", Count, RegList>;
3830 defm S : VectorList_operands<PREFIX, "S", Count, RegList>;
3831 defm D : VectorList_operands<PREFIX, "D", Count, RegList>;
3834 // Special vector list operand of 128-bit vectors with bare layout.
3835 // i.e. only show ".b", ".h", ".s", ".d"
3836 defm VOne : VectorList_Bare_BHSD<"VOne", 1, FPR128>;
3837 defm VPair : VectorList_Bare_BHSD<"VPair", 2, QPair>;
3838 defm VTriple : VectorList_Bare_BHSD<"VTriple", 3, QTriple>;
3839 defm VQuad : VectorList_Bare_BHSD<"VQuad", 4, QQuad>;
3841 class NeonI_LDN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3842 Operand ImmOp, string asmop>
3843 : NeonI_LdStOne_Lane<1, r, op2_1, op0,
3845 (ins GPR64xsp:$Rn, VList:$src, ImmOp:$lane),
3846 asmop # "\t$Rt[$lane], [$Rn]",
3850 let neverHasSideEffects = 1;
3851 let hasExtraDefRegAllocReq = 1;
3852 let Constraints = "$src = $Rt";
3855 multiclass LDN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3856 def _B : NeonI_LDN_Lane<r, 0b00, op0,
3857 !cast<RegisterOperand>(List # "B_operand"),
3858 neon_uimm4_bare, asmop> {
3859 let Inst{12-10} = lane{2-0};
3860 let Inst{30} = lane{3};
3863 def _H : NeonI_LDN_Lane<r, 0b01, op0,
3864 !cast<RegisterOperand>(List # "H_operand"),
3865 neon_uimm3_bare, asmop> {
3866 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3867 let Inst{30} = lane{2};
3870 def _S : NeonI_LDN_Lane<r, 0b10, op0,
3871 !cast<RegisterOperand>(List # "S_operand"),
3872 neon_uimm2_bare, asmop> {
3873 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3874 let Inst{30} = lane{1};
3877 def _D : NeonI_LDN_Lane<r, 0b10, op0,
3878 !cast<RegisterOperand>(List # "D_operand"),
3879 neon_uimm1_bare, asmop> {
3880 let Inst{12-10} = 0b001;
3881 let Inst{30} = lane{0};
3885 // Load single 1-element structure to one lane of 1 register.
3886 defm LD1LN : LDN_Lane_BHSD<0b0, 0b0, "VOne", "ld1">;
3888 // Load single N-element structure to one lane of N consecutive registers
3890 defm LD2LN : LDN_Lane_BHSD<0b1, 0b0, "VPair", "ld2">;
3891 defm LD3LN : LDN_Lane_BHSD<0b0, 0b1, "VTriple", "ld3">;
3892 defm LD4LN : LDN_Lane_BHSD<0b1, 0b1, "VQuad", "ld4">;
3894 multiclass LD1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3895 Operand ImmOp, Operand ImmOp2, PatFrag LoadOp,
3897 def : Pat<(VTy (vector_insert (VTy VPR64:$src),
3898 (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp:$lane))),
3899 (VTy (EXTRACT_SUBREG
3901 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
3905 def : Pat<(VTy2 (vector_insert (VTy2 VPR128:$src),
3906 (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp2:$lane))),
3907 (VTy2 (INST GPR64xsp:$Rn, VPR128:$src, ImmOp2:$lane))>;
3910 // Match all LD1LN instructions
3911 defm : LD1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3912 extloadi8, LD1LN_B>;
3914 defm : LD1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3915 extloadi16, LD1LN_H>;
3917 defm : LD1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3919 defm : LD1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3922 defm : LD1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3924 defm : LD1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3927 class NeonI_STN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3928 Operand ImmOp, string asmop>
3929 : NeonI_LdStOne_Lane<0, r, op2_1, op0,
3930 (outs), (ins GPR64xsp:$Rn, VList:$Rt, ImmOp:$lane),
3931 asmop # "\t$Rt[$lane], [$Rn]",
3935 let neverHasSideEffects = 1;
3936 let hasExtraDefRegAllocReq = 1;
3939 multiclass STN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3940 def _B : NeonI_STN_Lane<r, 0b00, op0,
3941 !cast<RegisterOperand>(List # "B_operand"),
3942 neon_uimm4_bare, asmop> {
3943 let Inst{12-10} = lane{2-0};
3944 let Inst{30} = lane{3};
3947 def _H : NeonI_STN_Lane<r, 0b01, op0,
3948 !cast<RegisterOperand>(List # "H_operand"),
3949 neon_uimm3_bare, asmop> {
3950 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3951 let Inst{30} = lane{2};
3954 def _S : NeonI_STN_Lane<r, 0b10, op0,
3955 !cast<RegisterOperand>(List # "S_operand"),
3956 neon_uimm2_bare, asmop> {
3957 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3958 let Inst{30} = lane{1};
3961 def _D : NeonI_STN_Lane<r, 0b10, op0,
3962 !cast<RegisterOperand>(List # "D_operand"),
3963 neon_uimm1_bare, asmop>{
3964 let Inst{12-10} = 0b001;
3965 let Inst{30} = lane{0};
3969 // Store single 1-element structure from one lane of 1 register.
3970 defm ST1LN : STN_Lane_BHSD<0b0, 0b0, "VOne", "st1">;
3972 // Store single N-element structure from one lane of N consecutive registers
3974 defm ST2LN : STN_Lane_BHSD<0b1, 0b0, "VPair", "st2">;
3975 defm ST3LN : STN_Lane_BHSD<0b0, 0b1, "VTriple", "st3">;
3976 defm ST4LN : STN_Lane_BHSD<0b1, 0b1, "VQuad", "st4">;
3978 multiclass ST1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3979 Operand ImmOp, Operand ImmOp2, PatFrag StoreOp,
3981 def : Pat<(StoreOp (DTy (vector_extract (VTy VPR64:$Rt), ImmOp:$lane)),
3984 (SUBREG_TO_REG (i64 0), VPR64:$Rt, sub_64),
3987 def : Pat<(StoreOp (DTy (vector_extract (VTy2 VPR128:$Rt), ImmOp2:$lane)),
3989 (INST GPR64xsp:$Rn, VPR128:$Rt, ImmOp2:$lane)>;
3992 // Match all ST1LN instructions
3993 defm : ST1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3994 truncstorei8, ST1LN_B>;
3996 defm : ST1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3997 truncstorei16, ST1LN_H>;
3999 defm : ST1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
4001 defm : ST1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
4004 defm : ST1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
4006 defm : ST1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
4009 // End of vector load/store single N-element structure (class SIMD lsone).
4012 // The following are post-index load/store single N-element instructions
4013 // (class SIMD lsone-post)
4015 multiclass NeonI_LDN_WB_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
4016 RegisterOperand VecList, Operand ImmTy,
4018 let mayLoad = 1, neverHasSideEffects = 1, Constraints = "$wb = $Rn",
4019 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4020 def _fixed : NeonI_LdOne_Dup_Post<q, r, opcode, size,
4021 (outs VecList:$Rt, GPR64xsp:$wb),
4022 (ins GPR64xsp:$Rn, ImmTy:$amt),
4023 asmop # "\t$Rt, [$Rn], $amt",
4029 def _register : NeonI_LdOne_Dup_Post<q, r, opcode, size,
4030 (outs VecList:$Rt, GPR64xsp:$wb),
4031 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
4032 asmop # "\t$Rt, [$Rn], $Rm",
4038 multiclass LDWB_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop,
4039 Operand uimm_b, Operand uimm_h,
4040 Operand uimm_s, Operand uimm_d> {
4041 defm _8B : NeonI_LDN_WB_Dup<0, r, opcode, 0b00,
4042 !cast<RegisterOperand>(List # "8B_operand"),
4045 defm _4H : NeonI_LDN_WB_Dup<0, r, opcode, 0b01,
4046 !cast<RegisterOperand>(List # "4H_operand"),
4049 defm _2S : NeonI_LDN_WB_Dup<0, r, opcode, 0b10,
4050 !cast<RegisterOperand>(List # "2S_operand"),
4053 defm _1D : NeonI_LDN_WB_Dup<0, r, opcode, 0b11,
4054 !cast<RegisterOperand>(List # "1D_operand"),
4057 defm _16B : NeonI_LDN_WB_Dup<1, r, opcode, 0b00,
4058 !cast<RegisterOperand>(List # "16B_operand"),
4061 defm _8H : NeonI_LDN_WB_Dup<1, r, opcode, 0b01,
4062 !cast<RegisterOperand>(List # "8H_operand"),
4065 defm _4S : NeonI_LDN_WB_Dup<1, r, opcode, 0b10,
4066 !cast<RegisterOperand>(List # "4S_operand"),
4069 defm _2D : NeonI_LDN_WB_Dup<1, r, opcode, 0b11,
4070 !cast<RegisterOperand>(List # "2D_operand"),
4074 // Post-index load single 1-element structure to all lanes of 1 register
4075 defm LD1R_WB : LDWB_Dup_BHSD<0b0, 0b110, "VOne", "ld1r", uimm_exact1,
4076 uimm_exact2, uimm_exact4, uimm_exact8>;
4078 // Post-index load single N-element structure to all lanes of N consecutive
4079 // registers (N = 2,3,4)
4080 defm LD2R_WB : LDWB_Dup_BHSD<0b1, 0b110, "VPair", "ld2r", uimm_exact2,
4081 uimm_exact4, uimm_exact8, uimm_exact16>;
4082 defm LD3R_WB : LDWB_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r", uimm_exact3,
4083 uimm_exact6, uimm_exact12, uimm_exact24>;
4084 defm LD4R_WB : LDWB_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r", uimm_exact4,
4085 uimm_exact8, uimm_exact16, uimm_exact32>;
4087 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
4088 Constraints = "$Rn = $wb, $Rt = $src",
4089 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4090 class LDN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4091 Operand ImmTy, Operand ImmOp, string asmop>
4092 : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
4093 (outs VList:$Rt, GPR64xsp:$wb),
4094 (ins GPR64xsp:$Rn, ImmTy:$amt,
4095 VList:$src, ImmOp:$lane),
4096 asmop # "\t$Rt[$lane], [$Rn], $amt",
4102 class LDN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4103 Operand ImmTy, Operand ImmOp, string asmop>
4104 : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
4105 (outs VList:$Rt, GPR64xsp:$wb),
4106 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm,
4107 VList:$src, ImmOp:$lane),
4108 asmop # "\t$Rt[$lane], [$Rn], $Rm",
4113 multiclass LD_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4114 Operand uimm_b, Operand uimm_h,
4115 Operand uimm_s, Operand uimm_d> {
4116 def _B_fixed : LDN_WBFx_Lane<r, 0b00, op0,
4117 !cast<RegisterOperand>(List # "B_operand"),
4118 uimm_b, neon_uimm4_bare, asmop> {
4119 let Inst{12-10} = lane{2-0};
4120 let Inst{30} = lane{3};
4123 def _B_register : LDN_WBReg_Lane<r, 0b00, op0,
4124 !cast<RegisterOperand>(List # "B_operand"),
4125 uimm_b, neon_uimm4_bare, asmop> {
4126 let Inst{12-10} = lane{2-0};
4127 let Inst{30} = lane{3};
4130 def _H_fixed : LDN_WBFx_Lane<r, 0b01, op0,
4131 !cast<RegisterOperand>(List # "H_operand"),
4132 uimm_h, neon_uimm3_bare, asmop> {
4133 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4134 let Inst{30} = lane{2};
4137 def _H_register : LDN_WBReg_Lane<r, 0b01, op0,
4138 !cast<RegisterOperand>(List # "H_operand"),
4139 uimm_h, neon_uimm3_bare, asmop> {
4140 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4141 let Inst{30} = lane{2};
4144 def _S_fixed : LDN_WBFx_Lane<r, 0b10, op0,
4145 !cast<RegisterOperand>(List # "S_operand"),
4146 uimm_s, neon_uimm2_bare, asmop> {
4147 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4148 let Inst{30} = lane{1};
4151 def _S_register : LDN_WBReg_Lane<r, 0b10, op0,
4152 !cast<RegisterOperand>(List # "S_operand"),
4153 uimm_s, neon_uimm2_bare, asmop> {
4154 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4155 let Inst{30} = lane{1};
4158 def _D_fixed : LDN_WBFx_Lane<r, 0b10, op0,
4159 !cast<RegisterOperand>(List # "D_operand"),
4160 uimm_d, neon_uimm1_bare, asmop> {
4161 let Inst{12-10} = 0b001;
4162 let Inst{30} = lane{0};
4165 def _D_register : LDN_WBReg_Lane<r, 0b10, op0,
4166 !cast<RegisterOperand>(List # "D_operand"),
4167 uimm_d, neon_uimm1_bare, asmop> {
4168 let Inst{12-10} = 0b001;
4169 let Inst{30} = lane{0};
4173 // Post-index load single 1-element structure to one lane of 1 register.
4174 defm LD1LN_WB : LD_Lane_WB_BHSD<0b0, 0b0, "VOne", "ld1", uimm_exact1,
4175 uimm_exact2, uimm_exact4, uimm_exact8>;
4177 // Post-index load single N-element structure to one lane of N consecutive
4180 defm LD2LN_WB : LD_Lane_WB_BHSD<0b1, 0b0, "VPair", "ld2", uimm_exact2,
4181 uimm_exact4, uimm_exact8, uimm_exact16>;
4182 defm LD3LN_WB : LD_Lane_WB_BHSD<0b0, 0b1, "VTriple", "ld3", uimm_exact3,
4183 uimm_exact6, uimm_exact12, uimm_exact24>;
4184 defm LD4LN_WB : LD_Lane_WB_BHSD<0b1, 0b1, "VQuad", "ld4", uimm_exact4,
4185 uimm_exact8, uimm_exact16, uimm_exact32>;
4187 let mayStore = 1, neverHasSideEffects = 1,
4188 hasExtraDefRegAllocReq = 1, Constraints = "$Rn = $wb",
4189 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4190 class STN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4191 Operand ImmTy, Operand ImmOp, string asmop>
4192 : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4193 (outs GPR64xsp:$wb),
4194 (ins GPR64xsp:$Rn, ImmTy:$amt,
4195 VList:$Rt, ImmOp:$lane),
4196 asmop # "\t$Rt[$lane], [$Rn], $amt",
4202 class STN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4203 Operand ImmTy, Operand ImmOp, string asmop>
4204 : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4205 (outs GPR64xsp:$wb),
4206 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VList:$Rt,
4208 asmop # "\t$Rt[$lane], [$Rn], $Rm",
4213 multiclass ST_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4214 Operand uimm_b, Operand uimm_h,
4215 Operand uimm_s, Operand uimm_d> {
4216 def _B_fixed : STN_WBFx_Lane<r, 0b00, op0,
4217 !cast<RegisterOperand>(List # "B_operand"),
4218 uimm_b, neon_uimm4_bare, asmop> {
4219 let Inst{12-10} = lane{2-0};
4220 let Inst{30} = lane{3};
4223 def _B_register : STN_WBReg_Lane<r, 0b00, op0,
4224 !cast<RegisterOperand>(List # "B_operand"),
4225 uimm_b, neon_uimm4_bare, asmop> {
4226 let Inst{12-10} = lane{2-0};
4227 let Inst{30} = lane{3};
4230 def _H_fixed : STN_WBFx_Lane<r, 0b01, op0,
4231 !cast<RegisterOperand>(List # "H_operand"),
4232 uimm_h, neon_uimm3_bare, asmop> {
4233 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4234 let Inst{30} = lane{2};
4237 def _H_register : STN_WBReg_Lane<r, 0b01, op0,
4238 !cast<RegisterOperand>(List # "H_operand"),
4239 uimm_h, neon_uimm3_bare, asmop> {
4240 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4241 let Inst{30} = lane{2};
4244 def _S_fixed : STN_WBFx_Lane<r, 0b10, op0,
4245 !cast<RegisterOperand>(List # "S_operand"),
4246 uimm_s, neon_uimm2_bare, asmop> {
4247 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4248 let Inst{30} = lane{1};
4251 def _S_register : STN_WBReg_Lane<r, 0b10, op0,
4252 !cast<RegisterOperand>(List # "S_operand"),
4253 uimm_s, neon_uimm2_bare, asmop> {
4254 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4255 let Inst{30} = lane{1};
4258 def _D_fixed : STN_WBFx_Lane<r, 0b10, op0,
4259 !cast<RegisterOperand>(List # "D_operand"),
4260 uimm_d, neon_uimm1_bare, asmop> {
4261 let Inst{12-10} = 0b001;
4262 let Inst{30} = lane{0};
4265 def _D_register : STN_WBReg_Lane<r, 0b10, op0,
4266 !cast<RegisterOperand>(List # "D_operand"),
4267 uimm_d, neon_uimm1_bare, asmop> {
4268 let Inst{12-10} = 0b001;
4269 let Inst{30} = lane{0};
4273 // Post-index store single 1-element structure from one lane of 1 register.
4274 defm ST1LN_WB : ST_Lane_WB_BHSD<0b0, 0b0, "VOne", "st1", uimm_exact1,
4275 uimm_exact2, uimm_exact4, uimm_exact8>;
4277 // Post-index store single N-element structure from one lane of N consecutive
4278 // registers (N = 2,3,4)
4279 defm ST2LN_WB : ST_Lane_WB_BHSD<0b1, 0b0, "VPair", "st2", uimm_exact2,
4280 uimm_exact4, uimm_exact8, uimm_exact16>;
4281 defm ST3LN_WB : ST_Lane_WB_BHSD<0b0, 0b1, "VTriple", "st3", uimm_exact3,
4282 uimm_exact6, uimm_exact12, uimm_exact24>;
4283 defm ST4LN_WB : ST_Lane_WB_BHSD<0b1, 0b1, "VQuad", "st4", uimm_exact4,
4284 uimm_exact8, uimm_exact16, uimm_exact32>;
4286 // End of post-index load/store single N-element instructions
4287 // (class SIMD lsone-post)
4289 // Neon Scalar instructions implementation
4290 // Scalar Three Same
4292 class NeonI_Scalar3Same_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4294 : NeonI_Scalar3Same<u, size, opcode,
4295 (outs FPRC:$Rd), (ins FPRC:$Rn, FPRC:$Rm),
4296 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4300 class NeonI_Scalar3Same_D_size<bit u, bits<5> opcode, string asmop>
4301 : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4303 multiclass NeonI_Scalar3Same_HS_sizes<bit u, bits<5> opcode, string asmop,
4304 bit Commutable = 0> {
4305 let isCommutable = Commutable in {
4306 def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4307 def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4311 multiclass NeonI_Scalar3Same_SD_sizes<bit u, bit size_high, bits<5> opcode,
4312 string asmop, bit Commutable = 0> {
4313 let isCommutable = Commutable in {
4314 def sss : NeonI_Scalar3Same_size<u, {size_high, 0b0}, opcode, asmop, FPR32>;
4315 def ddd : NeonI_Scalar3Same_size<u, {size_high, 0b1}, opcode, asmop, FPR64>;
4319 multiclass NeonI_Scalar3Same_BHSD_sizes<bit u, bits<5> opcode,
4320 string asmop, bit Commutable = 0> {
4321 let isCommutable = Commutable in {
4322 def bbb : NeonI_Scalar3Same_size<u, 0b00, opcode, asmop, FPR8>;
4323 def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4324 def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4325 def ddd : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4329 multiclass Neon_Scalar3Same_D_size_patterns<SDPatternOperator opnode,
4330 Instruction INSTD> {
4331 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4332 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4335 multiclass Neon_Scalar3Same_BHSD_size_patterns<SDPatternOperator opnode,
4340 : Neon_Scalar3Same_D_size_patterns<opnode, INSTD> {
4341 def: Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (v1i8 FPR8:$Rm))),
4342 (INSTB FPR8:$Rn, FPR8:$Rm)>;
4343 def: Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4344 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4345 def: Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4346 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4349 multiclass Neon_Scalar3Same_HS_size_patterns<SDPatternOperator opnode,
4351 Instruction INSTS> {
4352 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4353 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4354 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4355 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4358 multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
4359 ValueType SResTy, ValueType STy,
4360 Instruction INSTS, ValueType DResTy,
4361 ValueType DTy, Instruction INSTD> {
4362 def : Pat<(SResTy (opnode (STy FPR32:$Rn), (STy FPR32:$Rm))),
4363 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4364 def : Pat<(DResTy (opnode (DTy FPR64:$Rn), (DTy FPR64:$Rm))),
4365 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4368 class Neon_Scalar3Same_cmp_V1_D_size_patterns<CondCode CC,
4370 : Pat<(v1i64 (Neon_cmp (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm), CC)),
4371 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4373 // Scalar Three Different
4375 class NeonI_Scalar3Diff_size<bit u, bits<2> size, bits<4> opcode, string asmop,
4376 RegisterClass FPRCD, RegisterClass FPRCS>
4377 : NeonI_Scalar3Diff<u, size, opcode,
4378 (outs FPRCD:$Rd), (ins FPRCS:$Rn, FPRCS:$Rm),
4379 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4383 multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> {
4384 def shh : NeonI_Scalar3Diff_size<u, 0b01, opcode, asmop, FPR32, FPR16>;
4385 def dss : NeonI_Scalar3Diff_size<u, 0b10, opcode, asmop, FPR64, FPR32>;
4388 multiclass NeonI_Scalar3Diff_ml_HS_size<bit u, bits<4> opcode, string asmop> {
4389 let Constraints = "$Src = $Rd" in {
4390 def shh : NeonI_Scalar3Diff<u, 0b01, opcode,
4391 (outs FPR32:$Rd), (ins FPR32:$Src, FPR16:$Rn, FPR16:$Rm),
4392 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4395 def dss : NeonI_Scalar3Diff<u, 0b10, opcode,
4396 (outs FPR64:$Rd), (ins FPR64:$Src, FPR32:$Rn, FPR32:$Rm),
4397 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4403 multiclass Neon_Scalar3Diff_HS_size_patterns<SDPatternOperator opnode,
4405 Instruction INSTS> {
4406 def : Pat<(v1i32 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4407 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4408 def : Pat<(v1i64 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4409 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4412 multiclass Neon_Scalar3Diff_ml_HS_size_patterns<SDPatternOperator opnode,
4414 Instruction INSTS> {
4415 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4416 (INSTH FPR32:$Src, FPR16:$Rn, FPR16:$Rm)>;
4417 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4418 (INSTS FPR64:$Src, FPR32:$Rn, FPR32:$Rm)>;
4421 // Scalar Two Registers Miscellaneous
4423 class NeonI_Scalar2SameMisc_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4424 RegisterClass FPRCD, RegisterClass FPRCS>
4425 : NeonI_Scalar2SameMisc<u, size, opcode,
4426 (outs FPRCD:$Rd), (ins FPRCS:$Rn),
4427 !strconcat(asmop, "\t$Rd, $Rn"),
4431 multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
4433 def ss : NeonI_Scalar2SameMisc_size<u, {size_high, 0b0}, opcode, asmop, FPR32,
4435 def dd : NeonI_Scalar2SameMisc_size<u, {size_high, 0b1}, opcode, asmop, FPR64,
4439 multiclass NeonI_Scalar2SameMisc_D_size<bit u, bits<5> opcode, string asmop> {
4440 def dd : NeonI_Scalar2SameMisc_size<u, 0b11, opcode, asmop, FPR64, FPR64>;
4443 multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>
4444 : NeonI_Scalar2SameMisc_D_size<u, opcode, asmop> {
4445 def bb : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR8>;
4446 def hh : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR16>;
4447 def ss : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR32>;
4450 class NeonI_Scalar2SameMisc_fcvtxn_D_size<bit u, bits<5> opcode, string asmop>
4451 : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR32, FPR64>;
4453 multiclass NeonI_Scalar2SameMisc_narrow_HSD_size<bit u, bits<5> opcode,
4455 def bh : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR16>;
4456 def hs : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR32>;
4457 def sd : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR64>;
4460 class NeonI_Scalar2SameMisc_accum_size<bit u, bits<2> size, bits<5> opcode,
4461 string asmop, RegisterClass FPRC>
4462 : NeonI_Scalar2SameMisc<u, size, opcode,
4463 (outs FPRC:$Rd), (ins FPRC:$Src, FPRC:$Rn),
4464 !strconcat(asmop, "\t$Rd, $Rn"),
4468 multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
4471 let Constraints = "$Src = $Rd" in {
4472 def bb : NeonI_Scalar2SameMisc_accum_size<u, 0b00, opcode, asmop, FPR8>;
4473 def hh : NeonI_Scalar2SameMisc_accum_size<u, 0b01, opcode, asmop, FPR16>;
4474 def ss : NeonI_Scalar2SameMisc_accum_size<u, 0b10, opcode, asmop, FPR32>;
4475 def dd : NeonI_Scalar2SameMisc_accum_size<u, 0b11, opcode, asmop, FPR64>;
4479 class Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<SDPatternOperator opnode,
4481 : Pat<(f32 (opnode (f64 FPR64:$Rn))),
4484 multiclass Neon_Scalar2SameMisc_fcvt_SD_size_patterns<SDPatternOperator opnode,
4486 Instruction INSTD> {
4487 def : Pat<(v1i32 (opnode (f32 FPR32:$Rn))),
4489 def : Pat<(v1i64 (opnode (f64 FPR64:$Rn))),
4493 class Neon_Scalar2SameMisc_vcvt_D_size_patterns<SDPatternOperator opnode,
4495 : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))),
4498 multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator opnode,
4500 Instruction INSTD> {
4501 def : Pat<(f32 (opnode (v1i32 FPR32:$Rn))),
4503 def : Pat<(f64 (opnode (v1i64 FPR64:$Rn))),
4507 multiclass Neon_Scalar2SameMisc_SD_size_patterns<SDPatternOperator opnode,
4509 Instruction INSTD> {
4510 def : Pat<(f32 (opnode (f32 FPR32:$Rn))),
4512 def : Pat<(f64 (opnode (f64 FPR64:$Rn))),
4516 class Neon_Scalar2SameMisc_V1_D_size_patterns<SDPatternOperator opnode,
4518 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))),
4521 class NeonI_Scalar2SameMisc_cmpz_D_size<bit u, bits<5> opcode, string asmop>
4522 : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4523 (outs FPR64:$Rd), (ins FPR64:$Rn, neon_uimm0:$Imm),
4524 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4528 multiclass NeonI_Scalar2SameMisc_cmpz_SD_size<bit u, bits<5> opcode,
4530 def ssi : NeonI_Scalar2SameMisc<u, 0b10, opcode,
4531 (outs FPR32:$Rd), (ins FPR32:$Rn, fpzz32:$FPImm),
4532 !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4535 def ddi : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4536 (outs FPR64:$Rd), (ins FPR64:$Rn, fpzz32:$FPImm),
4537 !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4542 class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode,
4544 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4545 (v1i64 (bitconvert (v8i8 Neon_AllZero))))),
4546 (INSTD FPR64:$Rn, 0)>;
4548 class Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<CondCode CC,
4550 : Pat<(v1i64 (Neon_cmpz (v1i64 FPR64:$Rn),
4551 (i32 neon_uimm0:$Imm), CC)),
4552 (INSTD FPR64:$Rn, neon_uimm0:$Imm)>;
4554 multiclass Neon_Scalar2SameMisc_cmpz_SD_size_patterns<SDPatternOperator opnode,
4557 Instruction INSTD> {
4558 def : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (f32 fpzz32:$FPImm))),
4559 (INSTS FPR32:$Rn, fpzz32:$FPImm)>;
4560 def : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (f32 fpzz32:$FPImm))),
4561 (INSTD FPR64:$Rn, fpzz32:$FPImm)>;
4562 def : Pat<(v1i64 (Neon_cmpz (v1f64 FPR64:$Rn), (f32 fpzz32:$FPImm), CC)),
4563 (INSTD FPR64:$Rn, fpzz32:$FPImm)>;
4566 multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode,
4567 Instruction INSTD> {
4568 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))),
4572 multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
4577 : Neon_Scalar2SameMisc_D_size_patterns<opnode, INSTD> {
4578 def : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn))),
4580 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn))),
4582 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn))),
4586 multiclass Neon_Scalar2SameMisc_narrow_HSD_size_patterns<
4587 SDPatternOperator opnode,
4590 Instruction INSTD> {
4591 def : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn))),
4593 def : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn))),
4595 def : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn))),
4600 multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns<
4601 SDPatternOperator opnode,
4605 Instruction INSTD> {
4606 def : Pat<(v1i8 (opnode (v1i8 FPR8:$Src), (v1i8 FPR8:$Rn))),
4607 (INSTB FPR8:$Src, FPR8:$Rn)>;
4608 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Src), (v1i16 FPR16:$Rn))),
4609 (INSTH FPR16:$Src, FPR16:$Rn)>;
4610 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i32 FPR32:$Rn))),
4611 (INSTS FPR32:$Src, FPR32:$Rn)>;
4612 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn))),
4613 (INSTD FPR64:$Src, FPR64:$Rn)>;
4616 // Scalar Shift By Immediate
4618 class NeonI_ScalarShiftImm_size<bit u, bits<5> opcode, string asmop,
4619 RegisterClass FPRC, Operand ImmTy>
4620 : NeonI_ScalarShiftImm<u, opcode,
4621 (outs FPRC:$Rd), (ins FPRC:$Rn, ImmTy:$Imm),
4622 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4625 multiclass NeonI_ScalarShiftRightImm_D_size<bit u, bits<5> opcode,
4627 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4629 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4630 let Inst{21-16} = Imm;
4634 multiclass NeonI_ScalarShiftRightImm_BHSD_size<bit u, bits<5> opcode,
4636 : NeonI_ScalarShiftRightImm_D_size<u, opcode, asmop> {
4637 def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shr_imm8> {
4639 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4640 let Inst{18-16} = Imm;
4642 def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shr_imm16> {
4644 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4645 let Inst{19-16} = Imm;
4647 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4649 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4650 let Inst{20-16} = Imm;
4654 multiclass NeonI_ScalarShiftLeftImm_D_size<bit u, bits<5> opcode,
4656 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shl_imm64> {
4658 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4659 let Inst{21-16} = Imm;
4663 multiclass NeonI_ScalarShiftLeftImm_BHSD_size<bit u, bits<5> opcode,
4665 : NeonI_ScalarShiftLeftImm_D_size<u, opcode, asmop> {
4666 def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shl_imm8> {
4668 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4669 let Inst{18-16} = Imm;
4671 def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shl_imm16> {
4673 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4674 let Inst{19-16} = Imm;
4676 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shl_imm32> {
4678 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4679 let Inst{20-16} = Imm;
4683 class NeonI_ScalarShiftRightImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4684 : NeonI_ScalarShiftImm<u, opcode,
4686 (ins FPR64:$Src, FPR64:$Rn, shr_imm64:$Imm),
4687 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4690 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4691 let Inst{21-16} = Imm;
4692 let Constraints = "$Src = $Rd";
4695 class NeonI_ScalarShiftLeftImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4696 : NeonI_ScalarShiftImm<u, opcode,
4698 (ins FPR64:$Src, FPR64:$Rn, shl_imm64:$Imm),
4699 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4702 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4703 let Inst{21-16} = Imm;
4704 let Constraints = "$Src = $Rd";
4707 class NeonI_ScalarShiftImm_narrow_size<bit u, bits<5> opcode, string asmop,
4708 RegisterClass FPRCD, RegisterClass FPRCS,
4710 : NeonI_ScalarShiftImm<u, opcode,
4711 (outs FPRCD:$Rd), (ins FPRCS:$Rn, ImmTy:$Imm),
4712 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4715 multiclass NeonI_ScalarShiftImm_narrow_HSD_size<bit u, bits<5> opcode,
4717 def bhi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR8, FPR16,
4720 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4721 let Inst{18-16} = Imm;
4723 def hsi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR16, FPR32,
4726 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4727 let Inst{19-16} = Imm;
4729 def sdi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR32, FPR64,
4732 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4733 let Inst{20-16} = Imm;
4737 multiclass NeonI_ScalarShiftImm_cvt_SD_size<bit u, bits<5> opcode, string asmop> {
4738 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4740 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4741 let Inst{20-16} = Imm;
4743 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4745 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4746 let Inst{21-16} = Imm;
4750 multiclass Neon_ScalarShiftRImm_D_size_patterns<SDPatternOperator opnode,
4751 Instruction INSTD> {
4752 def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4753 (INSTD FPR64:$Rn, imm:$Imm)>;
4756 multiclass Neon_ScalarShiftLImm_D_size_patterns<SDPatternOperator opnode,
4757 Instruction INSTD> {
4758 def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shl_imm64:$Imm))),
4759 (INSTD FPR64:$Rn, imm:$Imm)>;
4762 class Neon_ScalarShiftLImm_V1_D_size_patterns<SDPatternOperator opnode,
4764 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4765 (v1i64 (Neon_vdup (i32 shl_imm64:$Imm))))),
4766 (INSTD FPR64:$Rn, imm:$Imm)>;
4768 class Neon_ScalarShiftRImm_V1_D_size_patterns<SDPatternOperator opnode,
4770 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4771 (v1i64 (Neon_vdup (i32 shr_imm64:$Imm))))),
4772 (INSTD FPR64:$Rn, imm:$Imm)>;
4774 multiclass Neon_ScalarShiftLImm_BHSD_size_patterns<SDPatternOperator opnode,
4779 : Neon_ScalarShiftLImm_D_size_patterns<opnode, INSTD> {
4780 def bbi : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (i32 shl_imm8:$Imm))),
4781 (INSTB FPR8:$Rn, imm:$Imm)>;
4782 def hhi : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (i32 shl_imm16:$Imm))),
4783 (INSTH FPR16:$Rn, imm:$Imm)>;
4784 def ssi : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (i32 shl_imm32:$Imm))),
4785 (INSTS FPR32:$Rn, imm:$Imm)>;
4788 class Neon_ScalarShiftLImm_accum_D_size_patterns<SDPatternOperator opnode,
4790 : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4791 (i32 shl_imm64:$Imm))),
4792 (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4794 class Neon_ScalarShiftRImm_accum_D_size_patterns<SDPatternOperator opnode,
4796 : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4797 (i32 shr_imm64:$Imm))),
4798 (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4800 multiclass Neon_ScalarShiftImm_narrow_HSD_size_patterns<
4801 SDPatternOperator opnode,
4804 Instruction INSTD> {
4805 def bhi : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn), (i32 shr_imm16:$Imm))),
4806 (INSTH FPR16:$Rn, imm:$Imm)>;
4807 def hsi : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4808 (INSTS FPR32:$Rn, imm:$Imm)>;
4809 def sdi : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4810 (INSTD FPR64:$Rn, imm:$Imm)>;
4813 multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns<SDPatternOperator opnode,
4815 Instruction INSTD> {
4816 def ssi : Pat<(f32 (opnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4817 (INSTS FPR32:$Rn, imm:$Imm)>;
4818 def ddi : Pat<(f64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4819 (INSTD FPR64:$Rn, imm:$Imm)>;
4822 multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns<SDPatternOperator opnode,
4824 Instruction INSTD> {
4825 def ssi : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4826 (INSTS FPR32:$Rn, imm:$Imm)>;
4827 def ddi : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4828 (INSTD FPR64:$Rn, imm:$Imm)>;
4831 // Scalar Signed Shift Right (Immediate)
4832 defm SSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00000, "sshr">;
4833 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrds_n, SSHRddi>;
4834 // Pattern to match llvm.arm.* intrinsic.
4835 def : Neon_ScalarShiftRImm_V1_D_size_patterns<sra, SSHRddi>;
4837 // Scalar Unsigned Shift Right (Immediate)
4838 defm USHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00000, "ushr">;
4839 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrdu_n, USHRddi>;
4840 // Pattern to match llvm.arm.* intrinsic.
4841 def : Neon_ScalarShiftRImm_V1_D_size_patterns<srl, USHRddi>;
4843 // Scalar Signed Rounding Shift Right (Immediate)
4844 defm SRSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00100, "srshr">;
4845 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vsrshr, SRSHRddi>;
4847 // Scalar Unigned Rounding Shift Right (Immediate)
4848 defm URSHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00100, "urshr">;
4849 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vurshr, URSHRddi>;
4851 // Scalar Signed Shift Right and Accumulate (Immediate)
4852 def SSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00010, "ssra">;
4853 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4854 <int_aarch64_neon_vsrads_n, SSRA>;
4856 // Scalar Unsigned Shift Right and Accumulate (Immediate)
4857 def USRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00010, "usra">;
4858 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4859 <int_aarch64_neon_vsradu_n, USRA>;
4861 // Scalar Signed Rounding Shift Right and Accumulate (Immediate)
4862 def SRSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00110, "srsra">;
4863 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4864 <int_aarch64_neon_vrsrads_n, SRSRA>;
4866 // Scalar Unsigned Rounding Shift Right and Accumulate (Immediate)
4867 def URSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00110, "ursra">;
4868 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4869 <int_aarch64_neon_vrsradu_n, URSRA>;
4871 // Scalar Shift Left (Immediate)
4872 defm SHL : NeonI_ScalarShiftLeftImm_D_size<0b0, 0b01010, "shl">;
4873 defm : Neon_ScalarShiftLImm_D_size_patterns<int_aarch64_neon_vshld_n, SHLddi>;
4874 // Pattern to match llvm.arm.* intrinsic.
4875 def : Neon_ScalarShiftLImm_V1_D_size_patterns<shl, SHLddi>;
4877 // Signed Saturating Shift Left (Immediate)
4878 defm SQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b0, 0b01110, "sqshl">;
4879 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshls_n,
4881 SQSHLssi, SQSHLddi>;
4882 // Pattern to match llvm.arm.* intrinsic.
4883 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_sqrshlImm, SQSHLddi>;
4885 // Unsigned Saturating Shift Left (Immediate)
4886 defm UQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01110, "uqshl">;
4887 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshlu_n,
4889 UQSHLssi, UQSHLddi>;
4890 // Pattern to match llvm.arm.* intrinsic.
4891 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_uqrshlImm, UQSHLddi>;
4893 // Signed Saturating Shift Left Unsigned (Immediate)
4894 defm SQSHLU : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01100, "sqshlu">;
4895 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vsqshlu,
4896 SQSHLUbbi, SQSHLUhhi,
4897 SQSHLUssi, SQSHLUddi>;
4899 // Shift Right And Insert (Immediate)
4900 def SRI : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b01000, "sri">;
4901 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4902 <int_aarch64_neon_vsri, SRI>;
4904 // Shift Left And Insert (Immediate)
4905 def SLI : NeonI_ScalarShiftLeftImm_accum_D_size<0b1, 0b01010, "sli">;
4906 def : Neon_ScalarShiftLImm_accum_D_size_patterns
4907 <int_aarch64_neon_vsli, SLI>;
4909 // Signed Saturating Shift Right Narrow (Immediate)
4910 defm SQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10010, "sqshrn">;
4911 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrn,
4912 SQSHRNbhi, SQSHRNhsi,
4915 // Unsigned Saturating Shift Right Narrow (Immediate)
4916 defm UQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10010, "uqshrn">;
4917 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqshrn,
4918 UQSHRNbhi, UQSHRNhsi,
4921 // Signed Saturating Rounded Shift Right Narrow (Immediate)
4922 defm SQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10011, "sqrshrn">;
4923 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrn,
4924 SQRSHRNbhi, SQRSHRNhsi,
4927 // Unsigned Saturating Rounded Shift Right Narrow (Immediate)
4928 defm UQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10011, "uqrshrn">;
4929 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqrshrn,
4930 UQRSHRNbhi, UQRSHRNhsi,
4933 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
4934 defm SQSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10000, "sqshrun">;
4935 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrun,
4936 SQSHRUNbhi, SQSHRUNhsi,
4939 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
4940 defm SQRSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10001, "sqrshrun">;
4941 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrun,
4942 SQRSHRUNbhi, SQRSHRUNhsi,
4945 // Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
4946 defm SCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11100, "scvtf">;
4947 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtfxs2fp_n,
4948 SCVTF_Nssi, SCVTF_Nddi>;
4950 // Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
4951 defm UCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11100, "ucvtf">;
4952 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtfxu2fp_n,
4953 UCVTF_Nssi, UCVTF_Nddi>;
4955 // Scalar Floating-point Convert To Signed Fixed-point (Immediate)
4956 defm FCVTZS_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11111, "fcvtzs">;
4957 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvtfp2fxs_n,
4958 FCVTZS_Nssi, FCVTZS_Nddi>;
4960 // Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
4961 defm FCVTZU_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11111, "fcvtzu">;
4962 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvtfp2fxu_n,
4963 FCVTZU_Nssi, FCVTZU_Nddi>;
4965 // Patterns For Convert Instructions Between v1f64 and v1i64
4966 class Neon_ScalarShiftImm_cvtf_v1f64_pattern<SDPatternOperator opnode,
4968 : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4969 (INST FPR64:$Rn, imm:$Imm)>;
4971 class Neon_ScalarShiftImm_fcvt_v1f64_pattern<SDPatternOperator opnode,
4973 : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4974 (INST FPR64:$Rn, imm:$Imm)>;
4976 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxs2fp,
4979 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxu2fp,
4982 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxs,
4985 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxu,
4988 // Scalar Integer Add
4989 let isCommutable = 1 in {
4990 def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
4993 // Scalar Integer Sub
4994 def SUBddd : NeonI_Scalar3Same_D_size<0b1, 0b10000, "sub">;
4996 // Pattern for Scalar Integer Add and Sub with D register only
4997 defm : Neon_Scalar3Same_D_size_patterns<add, ADDddd>;
4998 defm : Neon_Scalar3Same_D_size_patterns<sub, SUBddd>;
5000 // Patterns to match llvm.aarch64.* intrinsic for Scalar Add, Sub
5001 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vaddds, ADDddd>;
5002 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vadddu, ADDddd>;
5003 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubds, SUBddd>;
5004 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubdu, SUBddd>;
5006 // Scalar Integer Saturating Add (Signed, Unsigned)
5007 defm SQADD : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00001, "sqadd", 1>;
5008 defm UQADD : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00001, "uqadd", 1>;
5010 // Scalar Integer Saturating Sub (Signed, Unsigned)
5011 defm SQSUB : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00101, "sqsub", 0>;
5012 defm UQSUB : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00101, "uqsub", 0>;
5015 // Patterns to match llvm.aarch64.* intrinsic for
5016 // Scalar Integer Saturating Add, Sub (Signed, Unsigned)
5017 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqadds, SQADDbbb,
5018 SQADDhhh, SQADDsss, SQADDddd>;
5019 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqaddu, UQADDbbb,
5020 UQADDhhh, UQADDsss, UQADDddd>;
5021 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubs, SQSUBbbb,
5022 SQSUBhhh, SQSUBsss, SQSUBddd>;
5023 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubu, UQSUBbbb,
5024 UQSUBhhh, UQSUBsss, UQSUBddd>;
5026 // Scalar Integer Saturating Doubling Multiply Half High
5027 defm SQDMULH : NeonI_Scalar3Same_HS_sizes<0b0, 0b10110, "sqdmulh", 1>;
5029 // Scalar Integer Saturating Rounding Doubling Multiply Half High
5030 defm SQRDMULH : NeonI_Scalar3Same_HS_sizes<0b1, 0b10110, "sqrdmulh", 1>;
5032 // Patterns to match llvm.arm.* intrinsic for
5033 // Scalar Integer Saturating Doubling Multiply Half High and
5034 // Scalar Integer Saturating Rounding Doubling Multiply Half High
5035 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqdmulh, SQDMULHhhh,
5037 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqrdmulh, SQRDMULHhhh,
5040 // Scalar Floating-point Multiply Extended
5041 defm FMULX : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11011, "fmulx", 1>;
5043 // Scalar Floating-point Reciprocal Step
5044 defm FRECPS : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11111, "frecps", 0>;
5045 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vrecps, f32, f32,
5046 FRECPSsss, f64, f64, FRECPSddd>;
5047 def : Pat<(v1f64 (int_arm_neon_vrecps (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5048 (FRECPSddd FPR64:$Rn, FPR64:$Rm)>;
5050 // Scalar Floating-point Reciprocal Square Root Step
5051 defm FRSQRTS : NeonI_Scalar3Same_SD_sizes<0b0, 0b1, 0b11111, "frsqrts", 0>;
5052 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vrsqrts, f32, f32,
5053 FRSQRTSsss, f64, f64, FRSQRTSddd>;
5054 def : Pat<(v1f64 (int_arm_neon_vrsqrts (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5055 (FRSQRTSddd FPR64:$Rn, FPR64:$Rm)>;
5056 def : Pat<(v1f64 (fsqrt (v1f64 FPR64:$Rn))), (FSQRTdd FPR64:$Rn)>;
5058 // Patterns to match llvm.aarch64.* intrinsic for
5059 // Scalar Floating-point Multiply Extended,
5060 multiclass Neon_Scalar3Same_MULX_SD_size_patterns<SDPatternOperator opnode,
5062 Instruction INSTD> {
5063 def : Pat<(f32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
5064 (INSTS FPR32:$Rn, FPR32:$Rm)>;
5065 def : Pat<(f64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
5066 (INSTD FPR64:$Rn, FPR64:$Rm)>;
5069 defm : Neon_Scalar3Same_MULX_SD_size_patterns<int_aarch64_neon_vmulx,
5070 FMULXsss, FMULXddd>;
5071 def : Pat<(v1f64 (int_aarch64_neon_vmulx (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5072 (FMULXddd FPR64:$Rn, FPR64:$Rm)>;
5074 // Scalar Integer Shift Left (Signed, Unsigned)
5075 def SSHLddd : NeonI_Scalar3Same_D_size<0b0, 0b01000, "sshl">;
5076 def USHLddd : NeonI_Scalar3Same_D_size<0b1, 0b01000, "ushl">;
5078 // Patterns to match llvm.arm.* intrinsic for
5079 // Scalar Integer Shift Left (Signed, Unsigned)
5080 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshifts, SSHLddd>;
5081 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshiftu, USHLddd>;
5083 // Patterns to match llvm.aarch64.* intrinsic for
5084 // Scalar Integer Shift Left (Signed, Unsigned)
5085 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshlds, SSHLddd>;
5086 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshldu, USHLddd>;
5088 // Scalar Integer Saturating Shift Left (Signed, Unsigned)
5089 defm SQSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01001, "sqshl", 0>;
5090 defm UQSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01001, "uqshl", 0>;
5092 // Patterns to match llvm.aarch64.* intrinsic for
5093 // Scalar Integer Saturating Shift Letf (Signed, Unsigned)
5094 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshls, SQSHLbbb,
5095 SQSHLhhh, SQSHLsss, SQSHLddd>;
5096 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshlu, UQSHLbbb,
5097 UQSHLhhh, UQSHLsss, UQSHLddd>;
5099 // Patterns to match llvm.arm.* intrinsic for
5100 // Scalar Integer Saturating Shift Letf (Signed, Unsigned)
5101 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshifts, SQSHLddd>;
5102 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshiftu, UQSHLddd>;
5104 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
5105 def SRSHLddd: NeonI_Scalar3Same_D_size<0b0, 0b01010, "srshl">;
5106 def URSHLddd: NeonI_Scalar3Same_D_size<0b1, 0b01010, "urshl">;
5108 // Patterns to match llvm.aarch64.* intrinsic for
5109 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
5110 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshlds, SRSHLddd>;
5111 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshldu, URSHLddd>;
5113 // Patterns to match llvm.arm.* intrinsic for
5114 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
5115 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshifts, SRSHLddd>;
5116 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshiftu, URSHLddd>;
5118 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
5119 defm SQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01011, "sqrshl", 0>;
5120 defm UQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01011, "uqrshl", 0>;
5122 // Patterns to match llvm.aarch64.* intrinsic for
5123 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
5124 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshls, SQRSHLbbb,
5125 SQRSHLhhh, SQRSHLsss, SQRSHLddd>;
5126 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb,
5127 UQRSHLhhh, UQRSHLsss, UQRSHLddd>;
5129 // Patterns to match llvm.arm.* intrinsic for
5130 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
5131 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
5132 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
5134 // Signed Saturating Doubling Multiply-Add Long
5135 defm SQDMLAL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1001, "sqdmlal">;
5136 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlal,
5137 SQDMLALshh, SQDMLALdss>;
5139 // Signed Saturating Doubling Multiply-Subtract Long
5140 defm SQDMLSL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1011, "sqdmlsl">;
5141 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlsl,
5142 SQDMLSLshh, SQDMLSLdss>;
5144 // Signed Saturating Doubling Multiply Long
5145 defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">;
5146 defm : Neon_Scalar3Diff_HS_size_patterns<int_arm_neon_vqdmull,
5147 SQDMULLshh, SQDMULLdss>;
5149 // Scalar Signed Integer Convert To Floating-point
5150 defm SCVTF : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">;
5151 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtint2fps,
5154 // Scalar Unsigned Integer Convert To Floating-point
5155 defm UCVTF : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11101, "ucvtf">;
5156 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtint2fpu,
5159 // Scalar Floating-point Converts
5160 def FCVTXN : NeonI_Scalar2SameMisc_fcvtxn_D_size<0b1, 0b10110, "fcvtxn">;
5161 def : Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<int_aarch64_neon_fcvtxn,
5164 defm FCVTNS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11010, "fcvtns">;
5165 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtns,
5166 FCVTNSss, FCVTNSdd>;
5167 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtns, FCVTNSdd>;
5169 defm FCVTNU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11010, "fcvtnu">;
5170 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtnu,
5171 FCVTNUss, FCVTNUdd>;
5172 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtnu, FCVTNUdd>;
5174 defm FCVTMS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11011, "fcvtms">;
5175 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtms,
5176 FCVTMSss, FCVTMSdd>;
5177 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtms, FCVTMSdd>;
5179 defm FCVTMU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11011, "fcvtmu">;
5180 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtmu,
5181 FCVTMUss, FCVTMUdd>;
5182 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtmu, FCVTMUdd>;
5184 defm FCVTAS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11100, "fcvtas">;
5185 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtas,
5186 FCVTASss, FCVTASdd>;
5187 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtas, FCVTASdd>;
5189 defm FCVTAU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11100, "fcvtau">;
5190 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtau,
5191 FCVTAUss, FCVTAUdd>;
5192 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtau, FCVTAUdd>;
5194 defm FCVTPS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11010, "fcvtps">;
5195 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtps,
5196 FCVTPSss, FCVTPSdd>;
5197 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtps, FCVTPSdd>;
5199 defm FCVTPU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11010, "fcvtpu">;
5200 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtpu,
5201 FCVTPUss, FCVTPUdd>;
5202 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtpu, FCVTPUdd>;
5204 defm FCVTZS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11011, "fcvtzs">;
5205 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzs,
5206 FCVTZSss, FCVTZSdd>;
5207 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_aarch64_neon_vcvtzs,
5210 defm FCVTZU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11011, "fcvtzu">;
5211 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzu,
5212 FCVTZUss, FCVTZUdd>;
5213 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_aarch64_neon_vcvtzu,
5216 // Patterns For Convert Instructions Between v1f64 and v1i64
5217 class Neon_Scalar2SameMisc_cvtf_v1f64_pattern<SDPatternOperator opnode,
5219 : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5221 class Neon_Scalar2SameMisc_fcvt_v1f64_pattern<SDPatternOperator opnode,
5223 : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5225 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<sint_to_fp, SCVTFdd>;
5226 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<uint_to_fp, UCVTFdd>;
5228 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_sint, FCVTZSdd>;
5229 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_uint, FCVTZUdd>;
5231 // Scalar Floating-point Reciprocal Estimate
5232 defm FRECPE : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11101, "frecpe">;
5233 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpe,
5234 FRECPEss, FRECPEdd>;
5235 def : Neon_Scalar2SameMisc_V1_D_size_patterns<int_arm_neon_vrecpe,
5238 // Scalar Floating-point Reciprocal Exponent
5239 defm FRECPX : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11111, "frecpx">;
5240 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpx,
5241 FRECPXss, FRECPXdd>;
5243 // Scalar Floating-point Reciprocal Square Root Estimate
5244 defm FRSQRTE: NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11101, "frsqrte">;
5245 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrsqrte,
5246 FRSQRTEss, FRSQRTEdd>;
5247 def : Neon_Scalar2SameMisc_V1_D_size_patterns<int_arm_neon_vrsqrte,
5250 // Scalar Floating-point Round
5251 class Neon_ScalarFloatRound_pattern<SDPatternOperator opnode, Instruction INST>
5252 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5254 def : Neon_ScalarFloatRound_pattern<fceil, FRINTPdd>;
5255 def : Neon_ScalarFloatRound_pattern<ffloor, FRINTMdd>;
5256 def : Neon_ScalarFloatRound_pattern<ftrunc, FRINTZdd>;
5257 def : Neon_ScalarFloatRound_pattern<frint, FRINTXdd>;
5258 def : Neon_ScalarFloatRound_pattern<fnearbyint, FRINTIdd>;
5259 def : Neon_ScalarFloatRound_pattern<frnd, FRINTAdd>;
5260 def : Neon_ScalarFloatRound_pattern<int_aarch64_neon_frintn, FRINTNdd>;
5262 // Scalar Integer Compare
5264 // Scalar Compare Bitwise Equal
5265 def CMEQddd: NeonI_Scalar3Same_D_size<0b1, 0b10001, "cmeq">;
5266 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vceq, CMEQddd>;
5268 class Neon_Scalar3Same_cmp_D_size_v1_patterns<SDPatternOperator opnode,
5271 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm), CC)),
5272 (INSTD FPR64:$Rn, FPR64:$Rm)>;
5274 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMEQddd, SETEQ>;
5276 // Scalar Compare Signed Greather Than Or Equal
5277 def CMGEddd: NeonI_Scalar3Same_D_size<0b0, 0b00111, "cmge">;
5278 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vcge, CMGEddd>;
5279 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGEddd, SETGE>;
5281 // Scalar Compare Unsigned Higher Or Same
5282 def CMHSddd: NeonI_Scalar3Same_D_size<0b1, 0b00111, "cmhs">;
5283 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vchs, CMHSddd>;
5284 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHSddd, SETUGE>;
5286 // Scalar Compare Unsigned Higher
5287 def CMHIddd: NeonI_Scalar3Same_D_size<0b1, 0b00110, "cmhi">;
5288 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vchi, CMHIddd>;
5289 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHIddd, SETUGT>;
5291 // Scalar Compare Signed Greater Than
5292 def CMGTddd: NeonI_Scalar3Same_D_size<0b0, 0b00110, "cmgt">;
5293 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vcgt, CMGTddd>;
5294 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGTddd, SETGT>;
5296 // Scalar Compare Bitwise Test Bits
5297 def CMTSTddd: NeonI_Scalar3Same_D_size<0b0, 0b10001, "cmtst">;
5298 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vtstd, CMTSTddd>;
5299 defm : Neon_Scalar3Same_D_size_patterns<Neon_tst, CMTSTddd>;
5301 // Scalar Compare Bitwise Equal To Zero
5302 def CMEQddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01001, "cmeq">;
5303 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vceq,
5305 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETEQ, CMEQddi>;
5307 // Scalar Compare Signed Greather Than Or Equal To Zero
5308 def CMGEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01000, "cmge">;
5309 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcge,
5311 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGE, CMGEddi>;
5313 // Scalar Compare Signed Greater Than Zero
5314 def CMGTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01000, "cmgt">;
5315 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcgt,
5317 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGT, CMGTddi>;
5319 // Scalar Compare Signed Less Than Or Equal To Zero
5320 def CMLEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01001, "cmle">;
5321 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vclez,
5323 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLE, CMLEddi>;
5325 // Scalar Compare Less Than Zero
5326 def CMLTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01010, "cmlt">;
5327 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcltz,
5329 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLT, CMLTddi>;
5331 // Scalar Floating-point Compare
5333 // Scalar Floating-point Compare Mask Equal
5334 defm FCMEQ: NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11100, "fcmeq">;
5335 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fceq, v1i32, f32,
5336 FCMEQsss, v1i64, f64, FCMEQddd>;
5337 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETEQ, FCMEQddd>;
5339 // Scalar Floating-point Compare Mask Equal To Zero
5340 defm FCMEQZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01101, "fcmeq">;
5341 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fceq, SETEQ,
5342 FCMEQZssi, FCMEQZddi>;
5344 // Scalar Floating-point Compare Mask Greater Than Or Equal
5345 defm FCMGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11100, "fcmge">;
5346 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcge, v1i32, f32,
5347 FCMGEsss, v1i64, f64, FCMGEddd>;
5348 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGE, FCMGEddd>;
5350 // Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
5351 defm FCMGEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01100, "fcmge">;
5352 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcge, SETGE,
5353 FCMGEZssi, FCMGEZddi>;
5355 // Scalar Floating-point Compare Mask Greather Than
5356 defm FCMGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11100, "fcmgt">;
5357 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcgt, v1i32, f32,
5358 FCMGTsss, v1i64, f64, FCMGTddd>;
5359 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGT, FCMGTddd>;
5361 // Scalar Floating-point Compare Mask Greather Than Zero
5362 defm FCMGTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01100, "fcmgt">;
5363 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcgt, SETGT,
5364 FCMGTZssi, FCMGTZddi>;
5366 // Scalar Floating-point Compare Mask Less Than Or Equal To Zero
5367 defm FCMLEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01101, "fcmle">;
5368 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fclez, SETLE,
5369 FCMLEZssi, FCMLEZddi>;
5371 // Scalar Floating-point Compare Mask Less Than Zero
5372 defm FCMLTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01110, "fcmlt">;
5373 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcltz, SETLT,
5374 FCMLTZssi, FCMLTZddi>;
5376 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
5377 defm FACGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11101, "facge">;
5378 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcage, v1i32, f32,
5379 FACGEsss, v1i64, f64, FACGEddd>;
5380 def : Pat<(v1i64 (int_aarch64_neon_vcage (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5381 (FACGEddd FPR64:$Rn, FPR64:$Rm)>;
5383 // Scalar Floating-point Absolute Compare Mask Greater Than
5384 defm FACGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11101, "facgt">;
5385 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcagt, v1i32, f32,
5386 FACGTsss, v1i64, f64, FACGTddd>;
5387 def : Pat<(v1i64 (int_aarch64_neon_vcagt (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5388 (FACGTddd FPR64:$Rn, FPR64:$Rm)>;
5390 // Scalar Floating-point Absolute Difference
5391 defm FABD: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11010, "fabd">;
5392 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vabd, f32, f32,
5393 FABDsss, f64, f64, FABDddd>;
5395 // Scalar Absolute Value
5396 defm ABS : NeonI_Scalar2SameMisc_D_size<0b0, 0b01011, "abs">;
5397 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vabs, ABSdd>;
5399 // Scalar Signed Saturating Absolute Value
5400 defm SQABS : NeonI_Scalar2SameMisc_BHSD_size<0b0, 0b00111, "sqabs">;
5401 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqabs,
5402 SQABSbb, SQABShh, SQABSss, SQABSdd>;
5405 defm NEG : NeonI_Scalar2SameMisc_D_size<0b1, 0b01011, "neg">;
5406 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vneg, NEGdd>;
5408 // Scalar Signed Saturating Negate
5409 defm SQNEG : NeonI_Scalar2SameMisc_BHSD_size<0b1, 0b00111, "sqneg">;
5410 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqneg,
5411 SQNEGbb, SQNEGhh, SQNEGss, SQNEGdd>;
5413 // Scalar Signed Saturating Accumulated of Unsigned Value
5414 defm SUQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b0, 0b00011, "suqadd">;
5415 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vuqadd,
5417 SUQADDss, SUQADDdd>;
5419 // Scalar Unsigned Saturating Accumulated of Signed Value
5420 defm USQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b1, 0b00011, "usqadd">;
5421 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vsqadd,
5423 USQADDss, USQADDdd>;
5425 def : Pat<(v1i64 (int_aarch64_neon_suqadd (v1i64 FPR64:$Src),
5426 (v1i64 FPR64:$Rn))),
5427 (SUQADDdd FPR64:$Src, FPR64:$Rn)>;
5429 def : Pat<(v1i64 (int_aarch64_neon_usqadd (v1i64 FPR64:$Src),
5430 (v1i64 FPR64:$Rn))),
5431 (USQADDdd FPR64:$Src, FPR64:$Rn)>;
5433 def : Pat<(v1i64 (int_arm_neon_vabs (v1i64 FPR64:$Rn))),
5436 def : Pat<(v1i64 (int_arm_neon_vqabs (v1i64 FPR64:$Rn))),
5437 (SQABSdd FPR64:$Rn)>;
5439 def : Pat<(v1i64 (int_arm_neon_vqneg (v1i64 FPR64:$Rn))),
5440 (SQNEGdd FPR64:$Rn)>;
5442 def : Pat<(v1i64 (sub (v1i64 (bitconvert (v8i8 Neon_AllZero))),
5443 (v1i64 FPR64:$Rn))),
5446 // Scalar Signed Saturating Extract Unsigned Narrow
5447 defm SQXTUN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10010, "sqxtun">;
5448 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnsu,
5452 // Scalar Signed Saturating Extract Narrow
5453 defm SQXTN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b0, 0b10100, "sqxtn">;
5454 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovns,
5458 // Scalar Unsigned Saturating Extract Narrow
5459 defm UQXTN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10100, "uqxtn">;
5460 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnu,
5464 // Scalar Reduce Pairwise
5466 multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode,
5467 string asmop, bit Commutable = 0> {
5468 let isCommutable = Commutable in {
5469 def _D_2D : NeonI_ScalarPair<u, {size, 0b1}, opcode,
5470 (outs FPR64:$Rd), (ins VPR128:$Rn),
5471 !strconcat(asmop, "\t$Rd, $Rn.2d"),
5477 multiclass NeonI_ScalarPair_SD_sizes<bit u, bit size, bits<5> opcode,
5478 string asmop, bit Commutable = 0>
5479 : NeonI_ScalarPair_D_sizes<u, size, opcode, asmop, Commutable> {
5480 let isCommutable = Commutable in {
5481 def _S_2S : NeonI_ScalarPair<u, {size, 0b0}, opcode,
5482 (outs FPR32:$Rd), (ins VPR64:$Rn),
5483 !strconcat(asmop, "\t$Rd, $Rn.2s"),
5489 // Scalar Reduce Addition Pairwise (Integer) with
5490 // Pattern to match llvm.arm.* intrinsic
5491 defm ADDPvv : NeonI_ScalarPair_D_sizes<0b0, 0b1, 0b11011, "addp", 0>;
5493 // Pattern to match llvm.aarch64.* intrinsic for
5494 // Scalar Reduce Addition Pairwise (Integer)
5495 def : Pat<(v1i64 (int_aarch64_neon_vpadd (v2i64 VPR128:$Rn))),
5496 (ADDPvv_D_2D VPR128:$Rn)>;
5497 def : Pat<(v1i64 (int_aarch64_neon_vaddv (v2i64 VPR128:$Rn))),
5498 (ADDPvv_D_2D VPR128:$Rn)>;
5500 // Scalar Reduce Addition Pairwise (Floating Point)
5501 defm FADDPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01101, "faddp", 0>;
5503 // Scalar Reduce Maximum Pairwise (Floating Point)
5504 defm FMAXPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01111, "fmaxp", 0>;
5506 // Scalar Reduce Minimum Pairwise (Floating Point)
5507 defm FMINPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01111, "fminp", 0>;
5509 // Scalar Reduce maxNum Pairwise (Floating Point)
5510 defm FMAXNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01100, "fmaxnmp", 0>;
5512 // Scalar Reduce minNum Pairwise (Floating Point)
5513 defm FMINNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01100, "fminnmp", 0>;
5515 multiclass Neon_ScalarPair_SD_size_patterns<SDPatternOperator opnode,
5517 Instruction INSTD> {
5518 def : Pat<(f32 (opnode (v2f32 VPR64:$Rn))),
5520 def : Pat<(f64 (opnode (v2f64 VPR128:$Rn))),
5521 (INSTD VPR128:$Rn)>;
5524 // Patterns to match llvm.aarch64.* intrinsic for
5525 // Scalar Reduce Add, Max, Min, MaxiNum, MinNum Pairwise (Floating Point)
5526 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfadd,
5527 FADDPvv_S_2S, FADDPvv_D_2D>;
5529 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmax,
5530 FMAXPvv_S_2S, FMAXPvv_D_2D>;
5532 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmin,
5533 FMINPvv_S_2S, FMINPvv_D_2D>;
5535 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfmaxnm,
5536 FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
5538 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfminnm,
5539 FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
5541 def : Pat<(f32 (int_aarch64_neon_vpfadd (v4f32 VPR128:$Rn))),
5542 (FADDPvv_S_2S (v2f32
5544 (v4f32 (FADDP_4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rn))),
5547 // Scalar by element Arithmetic
5549 class NeonI_ScalarXIndexedElemArith<string asmop, bits<4> opcode,
5550 string rmlane, bit u, bit szhi, bit szlo,
5551 RegisterClass ResFPR, RegisterClass OpFPR,
5552 RegisterOperand OpVPR, Operand OpImm>
5553 : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5555 (ins OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5556 asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5563 class NeonI_ScalarXIndexedElemArith_Constraint_Impl<string asmop, bits<4> opcode,
5565 bit u, bit szhi, bit szlo,
5566 RegisterClass ResFPR,
5567 RegisterClass OpFPR,
5568 RegisterOperand OpVPR,
5570 : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5572 (ins ResFPR:$src, OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5573 asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5576 let Constraints = "$src = $Rd";
5581 // Scalar Floating Point multiply (scalar, by element)
5582 def FMULssv_4S : NeonI_ScalarXIndexedElemArith<"fmul",
5583 0b1001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5584 let Inst{11} = Imm{1}; // h
5585 let Inst{21} = Imm{0}; // l
5586 let Inst{20-16} = MRm;
5588 def FMULddv_2D : NeonI_ScalarXIndexedElemArith<"fmul",
5589 0b1001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5590 let Inst{11} = Imm{0}; // h
5591 let Inst{21} = 0b0; // l
5592 let Inst{20-16} = MRm;
5595 // Scalar Floating Point multiply extended (scalar, by element)
5596 def FMULXssv_4S : NeonI_ScalarXIndexedElemArith<"fmulx",
5597 0b1001, ".s", 0b1, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5598 let Inst{11} = Imm{1}; // h
5599 let Inst{21} = Imm{0}; // l
5600 let Inst{20-16} = MRm;
5602 def FMULXddv_2D : NeonI_ScalarXIndexedElemArith<"fmulx",
5603 0b1001, ".d", 0b1, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5604 let Inst{11} = Imm{0}; // h
5605 let Inst{21} = 0b0; // l
5606 let Inst{20-16} = MRm;
5609 multiclass Neon_ScalarXIndexedElem_MUL_MULX_Patterns<
5610 SDPatternOperator opnode,
5612 ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5613 ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5615 def : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5616 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)))),
5617 (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5619 def : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5620 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)))),
5621 (ResTy (INST (ResTy FPRC:$Rn),
5622 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5626 def : Pat<(ResTy (opnode
5627 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5629 (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5631 def : Pat<(ResTy (opnode
5632 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5634 (ResTy (INST (ResTy FPRC:$Rn),
5635 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5639 // Patterns for Scalar Floating Point multiply (scalar, by element)
5640 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULssv_4S,
5641 f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5642 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULddv_2D,
5643 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5645 // Patterns for Scalar Floating Point multiply extended (scalar, by element)
5646 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5647 FMULXssv_4S, f32, FPR32, v4f32, neon_uimm2_bare,
5648 v2f32, v4f32, neon_uimm1_bare>;
5649 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5650 FMULXddv_2D, f64, FPR64, v2f64, neon_uimm1_bare,
5651 v1f64, v2f64, neon_uimm0_bare>;
5653 // Scalar Floating Point fused multiply-add (scalar, by element)
5654 def FMLAssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5655 0b0001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5656 let Inst{11} = Imm{1}; // h
5657 let Inst{21} = Imm{0}; // l
5658 let Inst{20-16} = MRm;
5660 def FMLAddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5661 0b0001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5662 let Inst{11} = Imm{0}; // h
5663 let Inst{21} = 0b0; // l
5664 let Inst{20-16} = MRm;
5667 // Scalar Floating Point fused multiply-subtract (scalar, by element)
5668 def FMLSssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5669 0b0101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5670 let Inst{11} = Imm{1}; // h
5671 let Inst{21} = Imm{0}; // l
5672 let Inst{20-16} = MRm;
5674 def FMLSddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5675 0b0101, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5676 let Inst{11} = Imm{0}; // h
5677 let Inst{21} = 0b0; // l
5678 let Inst{20-16} = MRm;
5680 // We are allowed to match the fma instruction regardless of compile options.
5681 multiclass Neon_ScalarXIndexedElem_FMA_Patterns<
5682 Instruction FMLAI, Instruction FMLSI,
5683 ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5684 ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5686 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5687 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5689 (ResTy (FMLAI (ResTy FPRC:$Ra),
5690 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5692 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5693 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5695 (ResTy (FMLAI (ResTy FPRC:$Ra),
5697 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5700 // swapped fmla operands
5701 def : Pat<(ResTy (fma
5702 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5705 (ResTy (FMLAI (ResTy FPRC:$Ra),
5706 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5708 def : Pat<(ResTy (fma
5709 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5712 (ResTy (FMLAI (ResTy FPRC:$Ra),
5714 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5718 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5719 (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5721 (ResTy (FMLSI (ResTy FPRC:$Ra),
5722 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5724 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5725 (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5727 (ResTy (FMLSI (ResTy FPRC:$Ra),
5729 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5732 // swapped fmls operands
5733 def : Pat<(ResTy (fma
5734 (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5737 (ResTy (FMLSI (ResTy FPRC:$Ra),
5738 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5740 def : Pat<(ResTy (fma
5741 (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5744 (ResTy (FMLSI (ResTy FPRC:$Ra),
5746 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5750 // Scalar Floating Point fused multiply-add and
5751 // multiply-subtract (scalar, by element)
5752 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAssv_4S, FMLSssv_4S,
5753 f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5754 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5755 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5756 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5757 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5759 // Scalar Signed saturating doubling multiply long (scalar, by element)
5760 def SQDMULLshv_4H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5761 0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5762 let Inst{11} = 0b0; // h
5763 let Inst{21} = Imm{1}; // l
5764 let Inst{20} = Imm{0}; // m
5765 let Inst{19-16} = MRm{3-0};
5767 def SQDMULLshv_8H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5768 0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5769 let Inst{11} = Imm{2}; // h
5770 let Inst{21} = Imm{1}; // l
5771 let Inst{20} = Imm{0}; // m
5772 let Inst{19-16} = MRm{3-0};
5774 def SQDMULLdsv_2S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5775 0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5776 let Inst{11} = 0b0; // h
5777 let Inst{21} = Imm{0}; // l
5778 let Inst{20-16} = MRm;
5780 def SQDMULLdsv_4S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5781 0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5782 let Inst{11} = Imm{1}; // h
5783 let Inst{21} = Imm{0}; // l
5784 let Inst{20-16} = MRm;
5787 multiclass Neon_ScalarXIndexedElem_MUL_Patterns<
5788 SDPatternOperator opnode,
5790 ValueType ResTy, RegisterClass FPRC,
5791 ValueType OpVTy, ValueType OpTy,
5792 ValueType VecOpTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5794 def : Pat<(ResTy (opnode (OpVTy FPRC:$Rn),
5795 (OpVTy (scalar_to_vector
5796 (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))))),
5797 (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5800 def : Pat<(ResTy (opnode
5801 (OpVTy (scalar_to_vector
5802 (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))),
5804 (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5808 // Patterns for Scalar Signed saturating doubling
5809 // multiply long (scalar, by element)
5810 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5811 SQDMULLshv_4H, v1i32, FPR16, v1i16, i16, v4i16,
5812 i32, VPR64Lo, neon_uimm2_bare>;
5813 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5814 SQDMULLshv_8H, v1i32, FPR16, v1i16, i16, v8i16,
5815 i32, VPR128Lo, neon_uimm3_bare>;
5816 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5817 SQDMULLdsv_2S, v1i64, FPR32, v1i32, i32, v2i32,
5818 i32, VPR64Lo, neon_uimm1_bare>;
5819 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5820 SQDMULLdsv_4S, v1i64, FPR32, v1i32, i32, v4i32,
5821 i32, VPR128Lo, neon_uimm2_bare>;
5823 // Scalar Signed saturating doubling multiply-add long (scalar, by element)
5824 def SQDMLALshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5825 0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5826 let Inst{11} = 0b0; // h
5827 let Inst{21} = Imm{1}; // l
5828 let Inst{20} = Imm{0}; // m
5829 let Inst{19-16} = MRm{3-0};
5831 def SQDMLALshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5832 0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5833 let Inst{11} = Imm{2}; // h
5834 let Inst{21} = Imm{1}; // l
5835 let Inst{20} = Imm{0}; // m
5836 let Inst{19-16} = MRm{3-0};
5838 def SQDMLALdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5839 0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5840 let Inst{11} = 0b0; // h
5841 let Inst{21} = Imm{0}; // l
5842 let Inst{20-16} = MRm;
5844 def SQDMLALdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5845 0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5846 let Inst{11} = Imm{1}; // h
5847 let Inst{21} = Imm{0}; // l
5848 let Inst{20-16} = MRm;
5851 // Scalar Signed saturating doubling
5852 // multiply-subtract long (scalar, by element)
5853 def SQDMLSLshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5854 0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5855 let Inst{11} = 0b0; // h
5856 let Inst{21} = Imm{1}; // l
5857 let Inst{20} = Imm{0}; // m
5858 let Inst{19-16} = MRm{3-0};
5860 def SQDMLSLshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5861 0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5862 let Inst{11} = Imm{2}; // h
5863 let Inst{21} = Imm{1}; // l
5864 let Inst{20} = Imm{0}; // m
5865 let Inst{19-16} = MRm{3-0};
5867 def SQDMLSLdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5868 0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5869 let Inst{11} = 0b0; // h
5870 let Inst{21} = Imm{0}; // l
5871 let Inst{20-16} = MRm;
5873 def SQDMLSLdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5874 0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5875 let Inst{11} = Imm{1}; // h
5876 let Inst{21} = Imm{0}; // l
5877 let Inst{20-16} = MRm;
5880 multiclass Neon_ScalarXIndexedElem_MLAL_Patterns<
5881 SDPatternOperator opnode,
5882 SDPatternOperator coreopnode,
5884 ValueType ResTy, RegisterClass ResFPRC, RegisterClass FPRC,
5886 ValueType OpVTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5888 def : Pat<(ResTy (opnode
5889 (ResTy ResFPRC:$Ra),
5890 (ResTy (coreopnode (OpTy FPRC:$Rn),
5891 (OpTy (scalar_to_vector
5892 (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))))))),
5893 (ResTy (INST (ResTy ResFPRC:$Ra),
5894 (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5897 def : Pat<(ResTy (opnode
5898 (ResTy ResFPRC:$Ra),
5900 (OpTy (scalar_to_vector
5901 (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))),
5902 (OpTy FPRC:$Rn))))),
5903 (ResTy (INST (ResTy ResFPRC:$Ra),
5904 (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5907 // Patterns for Scalar Signed saturating
5908 // doubling multiply-add long (scalar, by element)
5909 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5910 int_arm_neon_vqdmull, SQDMLALshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5911 i32, VPR64Lo, neon_uimm2_bare>;
5912 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5913 int_arm_neon_vqdmull, SQDMLALshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5914 i32, VPR128Lo, neon_uimm3_bare>;
5915 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5916 int_arm_neon_vqdmull, SQDMLALdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5917 i32, VPR64Lo, neon_uimm1_bare>;
5918 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5919 int_arm_neon_vqdmull, SQDMLALdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5920 i32, VPR128Lo, neon_uimm2_bare>;
5922 // Patterns for Scalar Signed saturating
5923 // doubling multiply-sub long (scalar, by element)
5924 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5925 int_arm_neon_vqdmull, SQDMLSLshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5926 i32, VPR64Lo, neon_uimm2_bare>;
5927 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5928 int_arm_neon_vqdmull, SQDMLSLshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5929 i32, VPR128Lo, neon_uimm3_bare>;
5930 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5931 int_arm_neon_vqdmull, SQDMLSLdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5932 i32, VPR64Lo, neon_uimm1_bare>;
5933 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5934 int_arm_neon_vqdmull, SQDMLSLdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5935 i32, VPR128Lo, neon_uimm2_bare>;
5937 // Scalar Signed saturating doubling multiply returning
5938 // high half (scalar, by element)
5939 def SQDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5940 0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5941 let Inst{11} = 0b0; // h
5942 let Inst{21} = Imm{1}; // l
5943 let Inst{20} = Imm{0}; // m
5944 let Inst{19-16} = MRm{3-0};
5946 def SQDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5947 0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5948 let Inst{11} = Imm{2}; // h
5949 let Inst{21} = Imm{1}; // l
5950 let Inst{20} = Imm{0}; // m
5951 let Inst{19-16} = MRm{3-0};
5953 def SQDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5954 0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5955 let Inst{11} = 0b0; // h
5956 let Inst{21} = Imm{0}; // l
5957 let Inst{20-16} = MRm;
5959 def SQDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5960 0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5961 let Inst{11} = Imm{1}; // h
5962 let Inst{21} = Imm{0}; // l
5963 let Inst{20-16} = MRm;
5966 // Patterns for Scalar Signed saturating doubling multiply returning
5967 // high half (scalar, by element)
5968 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5969 SQDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16,
5970 i32, VPR64Lo, neon_uimm2_bare>;
5971 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5972 SQDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16,
5973 i32, VPR128Lo, neon_uimm3_bare>;
5974 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5975 SQDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32,
5976 i32, VPR64Lo, neon_uimm1_bare>;
5977 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5978 SQDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32,
5979 i32, VPR128Lo, neon_uimm2_bare>;
5981 // Scalar Signed saturating rounding doubling multiply
5982 // returning high half (scalar, by element)
5983 def SQRDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5984 0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5985 let Inst{11} = 0b0; // h
5986 let Inst{21} = Imm{1}; // l
5987 let Inst{20} = Imm{0}; // m
5988 let Inst{19-16} = MRm{3-0};
5990 def SQRDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5991 0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5992 let Inst{11} = Imm{2}; // h
5993 let Inst{21} = Imm{1}; // l
5994 let Inst{20} = Imm{0}; // m
5995 let Inst{19-16} = MRm{3-0};
5997 def SQRDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5998 0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5999 let Inst{11} = 0b0; // h
6000 let Inst{21} = Imm{0}; // l
6001 let Inst{20-16} = MRm;
6003 def SQRDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
6004 0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
6005 let Inst{11} = Imm{1}; // h
6006 let Inst{21} = Imm{0}; // l
6007 let Inst{20-16} = MRm;
6010 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
6011 SQRDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16, i32,
6012 VPR64Lo, neon_uimm2_bare>;
6013 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
6014 SQRDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16, i32,
6015 VPR128Lo, neon_uimm3_bare>;
6016 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
6017 SQRDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32, i32,
6018 VPR64Lo, neon_uimm1_bare>;
6019 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
6020 SQRDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32, i32,
6021 VPR128Lo, neon_uimm2_bare>;
6023 // Scalar general arithmetic operation
6024 class Neon_Scalar_GeneralMath2D_pattern<SDPatternOperator opnode,
6026 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
6028 class Neon_Scalar_GeneralMath3D_pattern<SDPatternOperator opnode,
6030 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
6031 (INST FPR64:$Rn, FPR64:$Rm)>;
6033 class Neon_Scalar_GeneralMath4D_pattern<SDPatternOperator opnode,
6035 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm),
6036 (v1f64 FPR64:$Ra))),
6037 (INST FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
6039 def : Neon_Scalar_GeneralMath3D_pattern<fadd, FADDddd>;
6040 def : Neon_Scalar_GeneralMath3D_pattern<fmul, FMULddd>;
6041 def : Neon_Scalar_GeneralMath3D_pattern<fsub, FSUBddd>;
6042 def : Neon_Scalar_GeneralMath3D_pattern<fdiv, FDIVddd>;
6043 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vabds, FABDddd>;
6044 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmaxs, FMAXddd>;
6045 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmins, FMINddd>;
6046 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vmaxnm, FMAXNMddd>;
6047 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vminnm, FMINNMddd>;
6049 def : Neon_Scalar_GeneralMath2D_pattern<fabs, FABSdd>;
6050 def : Neon_Scalar_GeneralMath2D_pattern<fneg, FNEGdd>;
6052 def : Neon_Scalar_GeneralMath4D_pattern<fma, FMADDdddd>;
6053 def : Neon_Scalar_GeneralMath4D_pattern<fmsub, FMSUBdddd>;
6055 // Scalar Copy - DUP element to scalar
6056 class NeonI_Scalar_DUP<string asmop, string asmlane,
6057 RegisterClass ResRC, RegisterOperand VPRC,
6059 : NeonI_ScalarCopy<(outs ResRC:$Rd), (ins VPRC:$Rn, OpImm:$Imm),
6060 asmop # "\t$Rd, $Rn." # asmlane # "[$Imm]",
6066 def DUPbv_B : NeonI_Scalar_DUP<"dup", "b", FPR8, VPR128, neon_uimm4_bare> {
6067 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6069 def DUPhv_H : NeonI_Scalar_DUP<"dup", "h", FPR16, VPR128, neon_uimm3_bare> {
6070 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6072 def DUPsv_S : NeonI_Scalar_DUP<"dup", "s", FPR32, VPR128, neon_uimm2_bare> {
6073 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6075 def DUPdv_D : NeonI_Scalar_DUP<"dup", "d", FPR64, VPR128, neon_uimm1_bare> {
6076 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6079 def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 0)),
6080 (f32 (EXTRACT_SUBREG (v4f32 VPR128:$Rn), sub_32))>;
6081 def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 1)),
6082 (f32 (DUPsv_S (v4f32 VPR128:$Rn), 1))>;
6083 def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 2)),
6084 (f32 (DUPsv_S (v4f32 VPR128:$Rn), 2))>;
6085 def : Pat<(f32 (vector_extract (v4f32 VPR128:$Rn), 3)),
6086 (f32 (DUPsv_S (v4f32 VPR128:$Rn), 3))>;
6088 def : Pat<(f64 (vector_extract (v2f64 VPR128:$Rn), 0)),
6089 (f64 (EXTRACT_SUBREG (v2f64 VPR128:$Rn), sub_64))>;
6090 def : Pat<(f64 (vector_extract (v2f64 VPR128:$Rn), 1)),
6091 (f64 (DUPdv_D (v2f64 VPR128:$Rn), 1))>;
6093 def : Pat<(f32 (vector_extract (v2f32 VPR64:$Rn), 0)),
6094 (f32 (EXTRACT_SUBREG (v2f32 VPR64:$Rn), sub_32))>;
6095 def : Pat<(f32 (vector_extract (v2f32 VPR64:$Rn), 1)),
6096 (f32 (DUPsv_S (v4f32 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6099 def : Pat<(f64 (vector_extract (v1f64 VPR64:$Rn), 0)),
6100 (f64 (EXTRACT_SUBREG (v1f64 VPR64:$Rn), sub_64))>;
6102 multiclass NeonI_Scalar_DUP_Ext_Vec_pattern<Instruction DUPI,
6103 ValueType ResTy, ValueType OpTy,Operand OpLImm,
6104 ValueType NOpTy, ValueType ExTy, Operand OpNImm> {
6106 def : Pat<(ResTy (extract_subvector (OpTy VPR128:$Rn), OpLImm:$Imm)),
6107 (ResTy (DUPI VPR128:$Rn, OpLImm:$Imm))>;
6109 def : Pat<(ResTy (extract_subvector (NOpTy VPR64:$Rn), OpNImm:$Imm)),
6111 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6115 // Patterns for extract subvectors of v1ix data using scalar DUP instructions.
6116 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPbv_B, v1i8, v16i8, neon_uimm4_bare,
6117 v8i8, v16i8, neon_uimm3_bare>;
6118 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPhv_H, v1i16, v8i16, neon_uimm3_bare,
6119 v4i16, v8i16, neon_uimm2_bare>;
6120 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPsv_S, v1i32, v4i32, neon_uimm2_bare,
6121 v2i32, v4i32, neon_uimm1_bare>;
6123 multiclass NeonI_Scalar_DUP_Copy_pattern1<Instruction DUPI, ValueType ResTy,
6124 ValueType OpTy, ValueType ElemTy,
6125 Operand OpImm, ValueType OpNTy,
6126 ValueType ExTy, Operand OpNImm> {
6128 def : Pat<(ResTy (vector_insert (ResTy undef),
6129 (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
6130 (neon_uimm0_bare:$Imm))),
6131 (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
6133 def : Pat<(ResTy (vector_insert (ResTy undef),
6134 (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
6137 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6141 multiclass NeonI_Scalar_DUP_Copy_pattern2<Instruction DUPI, ValueType ResTy,
6142 ValueType OpTy, ValueType ElemTy,
6143 Operand OpImm, ValueType OpNTy,
6144 ValueType ExTy, Operand OpNImm> {
6146 def : Pat<(ResTy (scalar_to_vector
6147 (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)))),
6148 (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
6150 def : Pat<(ResTy (scalar_to_vector
6151 (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)))),
6153 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6157 // Patterns for vector copy to v1ix and v1fx vectors using scalar DUP
6159 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPdv_D,
6160 v1i64, v2i64, i64, neon_uimm1_bare,
6161 v1i64, v2i64, neon_uimm0_bare>;
6162 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPsv_S,
6163 v1i32, v4i32, i32, neon_uimm2_bare,
6164 v2i32, v4i32, neon_uimm1_bare>;
6165 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPhv_H,
6166 v1i16, v8i16, i32, neon_uimm3_bare,
6167 v4i16, v8i16, neon_uimm2_bare>;
6168 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPbv_B,
6169 v1i8, v16i8, i32, neon_uimm4_bare,
6170 v8i8, v16i8, neon_uimm3_bare>;
6171 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPdv_D,
6172 v1i64, v2i64, i64, neon_uimm1_bare,
6173 v1i64, v2i64, neon_uimm0_bare>;
6174 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPsv_S,
6175 v1i32, v4i32, i32, neon_uimm2_bare,
6176 v2i32, v4i32, neon_uimm1_bare>;
6177 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPhv_H,
6178 v1i16, v8i16, i32, neon_uimm3_bare,
6179 v4i16, v8i16, neon_uimm2_bare>;
6180 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPbv_B,
6181 v1i8, v16i8, i32, neon_uimm4_bare,
6182 v8i8, v16i8, neon_uimm3_bare>;
6184 multiclass NeonI_Scalar_DUP_alias<string asmop, string asmlane,
6185 Instruction DUPI, Operand OpImm,
6186 RegisterClass ResRC> {
6187 def : NeonInstAlias<!strconcat(asmop, "$Rd, $Rn" # asmlane # "[$Imm]"),
6188 (DUPI ResRC:$Rd, VPR128:$Rn, OpImm:$Imm), 0b0>;
6191 // Aliases for Scalar copy - DUP element (scalar)
6192 // FIXME: This is actually the preferred syntax but TableGen can't deal with
6193 // custom printing of aliases.
6194 defm : NeonI_Scalar_DUP_alias<"mov", ".b", DUPbv_B, neon_uimm4_bare, FPR8>;
6195 defm : NeonI_Scalar_DUP_alias<"mov", ".h", DUPhv_H, neon_uimm3_bare, FPR16>;
6196 defm : NeonI_Scalar_DUP_alias<"mov", ".s", DUPsv_S, neon_uimm2_bare, FPR32>;
6197 defm : NeonI_Scalar_DUP_alias<"mov", ".d", DUPdv_D, neon_uimm1_bare, FPR64>;
6199 multiclass NeonI_SDUP<PatFrag GetLow, PatFrag GetHigh, ValueType ResTy,
6201 def : Pat<(ResTy (GetLow VPR128:$Rn)),
6202 (ResTy (EXTRACT_SUBREG (OpTy VPR128:$Rn), sub_64))>;
6203 def : Pat<(ResTy (GetHigh VPR128:$Rn)),
6204 (ResTy (DUPdv_D (OpTy VPR128:$Rn), 1))>;
6207 defm : NeonI_SDUP<Neon_Low16B, Neon_High16B, v8i8, v16i8>;
6208 defm : NeonI_SDUP<Neon_Low8H, Neon_High8H, v4i16, v8i16>;
6209 defm : NeonI_SDUP<Neon_Low4S, Neon_High4S, v2i32, v4i32>;
6210 defm : NeonI_SDUP<Neon_Low2D, Neon_High2D, v1i64, v2i64>;
6211 defm : NeonI_SDUP<Neon_Low4float, Neon_High4float, v2f32, v4f32>;
6212 defm : NeonI_SDUP<Neon_Low2double, Neon_High2double, v1f64, v2f64>;
6214 //===----------------------------------------------------------------------===//
6215 // Non-Instruction Patterns
6216 //===----------------------------------------------------------------------===//
6218 // 64-bit vector bitcasts...
6220 def : Pat<(v1i64 (bitconvert (v8i8 VPR64:$src))), (v1i64 VPR64:$src)>;
6221 def : Pat<(v2f32 (bitconvert (v8i8 VPR64:$src))), (v2f32 VPR64:$src)>;
6222 def : Pat<(v2i32 (bitconvert (v8i8 VPR64:$src))), (v2i32 VPR64:$src)>;
6223 def : Pat<(v4i16 (bitconvert (v8i8 VPR64:$src))), (v4i16 VPR64:$src)>;
6225 def : Pat<(v1i64 (bitconvert (v4i16 VPR64:$src))), (v1i64 VPR64:$src)>;
6226 def : Pat<(v2i32 (bitconvert (v4i16 VPR64:$src))), (v2i32 VPR64:$src)>;
6227 def : Pat<(v2f32 (bitconvert (v4i16 VPR64:$src))), (v2f32 VPR64:$src)>;
6228 def : Pat<(v8i8 (bitconvert (v4i16 VPR64:$src))), (v8i8 VPR64:$src)>;
6230 def : Pat<(v1i64 (bitconvert (v2i32 VPR64:$src))), (v1i64 VPR64:$src)>;
6231 def : Pat<(v2f32 (bitconvert (v2i32 VPR64:$src))), (v2f32 VPR64:$src)>;
6232 def : Pat<(v4i16 (bitconvert (v2i32 VPR64:$src))), (v4i16 VPR64:$src)>;
6233 def : Pat<(v8i8 (bitconvert (v2i32 VPR64:$src))), (v8i8 VPR64:$src)>;
6235 def : Pat<(v1i64 (bitconvert (v2f32 VPR64:$src))), (v1i64 VPR64:$src)>;
6236 def : Pat<(v2i32 (bitconvert (v2f32 VPR64:$src))), (v2i32 VPR64:$src)>;
6237 def : Pat<(v4i16 (bitconvert (v2f32 VPR64:$src))), (v4i16 VPR64:$src)>;
6238 def : Pat<(v8i8 (bitconvert (v2f32 VPR64:$src))), (v8i8 VPR64:$src)>;
6240 def : Pat<(v2f32 (bitconvert (v1i64 VPR64:$src))), (v2f32 VPR64:$src)>;
6241 def : Pat<(v2i32 (bitconvert (v1i64 VPR64:$src))), (v2i32 VPR64:$src)>;
6242 def : Pat<(v4i16 (bitconvert (v1i64 VPR64:$src))), (v4i16 VPR64:$src)>;
6243 def : Pat<(v8i8 (bitconvert (v1i64 VPR64:$src))), (v8i8 VPR64:$src)>;
6245 def : Pat<(v1i64 (bitconvert (v1f64 VPR64:$src))), (v1i64 VPR64:$src)>;
6246 def : Pat<(v2f32 (bitconvert (v1f64 VPR64:$src))), (v2f32 VPR64:$src)>;
6247 def : Pat<(v2i32 (bitconvert (v1f64 VPR64:$src))), (v2i32 VPR64:$src)>;
6248 def : Pat<(v4i16 (bitconvert (v1f64 VPR64:$src))), (v4i16 VPR64:$src)>;
6249 def : Pat<(v8i8 (bitconvert (v1f64 VPR64:$src))), (v8i8 VPR64:$src)>;
6250 def : Pat<(f64 (bitconvert (v1f64 VPR64:$src))), (f64 VPR64:$src)>;
6252 def : Pat<(v1f64 (bitconvert (v1i64 VPR64:$src))), (v1f64 VPR64:$src)>;
6253 def : Pat<(v1f64 (bitconvert (v2f32 VPR64:$src))), (v1f64 VPR64:$src)>;
6254 def : Pat<(v1f64 (bitconvert (v2i32 VPR64:$src))), (v1f64 VPR64:$src)>;
6255 def : Pat<(v1f64 (bitconvert (v4i16 VPR64:$src))), (v1f64 VPR64:$src)>;
6256 def : Pat<(v1f64 (bitconvert (v8i8 VPR64:$src))), (v1f64 VPR64:$src)>;
6257 def : Pat<(v1f64 (bitconvert (f64 VPR64:$src))), (v1f64 VPR64:$src)>;
6259 // ..and 128-bit vector bitcasts...
6261 def : Pat<(v2f64 (bitconvert (v16i8 VPR128:$src))), (v2f64 VPR128:$src)>;
6262 def : Pat<(v2i64 (bitconvert (v16i8 VPR128:$src))), (v2i64 VPR128:$src)>;
6263 def : Pat<(v4f32 (bitconvert (v16i8 VPR128:$src))), (v4f32 VPR128:$src)>;
6264 def : Pat<(v4i32 (bitconvert (v16i8 VPR128:$src))), (v4i32 VPR128:$src)>;
6265 def : Pat<(v8i16 (bitconvert (v16i8 VPR128:$src))), (v8i16 VPR128:$src)>;
6267 def : Pat<(v2f64 (bitconvert (v8i16 VPR128:$src))), (v2f64 VPR128:$src)>;
6268 def : Pat<(v2i64 (bitconvert (v8i16 VPR128:$src))), (v2i64 VPR128:$src)>;
6269 def : Pat<(v4i32 (bitconvert (v8i16 VPR128:$src))), (v4i32 VPR128:$src)>;
6270 def : Pat<(v4f32 (bitconvert (v8i16 VPR128:$src))), (v4f32 VPR128:$src)>;
6271 def : Pat<(v16i8 (bitconvert (v8i16 VPR128:$src))), (v16i8 VPR128:$src)>;
6273 def : Pat<(v2f64 (bitconvert (v4i32 VPR128:$src))), (v2f64 VPR128:$src)>;
6274 def : Pat<(v2i64 (bitconvert (v4i32 VPR128:$src))), (v2i64 VPR128:$src)>;
6275 def : Pat<(v4f32 (bitconvert (v4i32 VPR128:$src))), (v4f32 VPR128:$src)>;
6276 def : Pat<(v8i16 (bitconvert (v4i32 VPR128:$src))), (v8i16 VPR128:$src)>;
6277 def : Pat<(v16i8 (bitconvert (v4i32 VPR128:$src))), (v16i8 VPR128:$src)>;
6279 def : Pat<(v2f64 (bitconvert (v4f32 VPR128:$src))), (v2f64 VPR128:$src)>;
6280 def : Pat<(v2i64 (bitconvert (v4f32 VPR128:$src))), (v2i64 VPR128:$src)>;
6281 def : Pat<(v4i32 (bitconvert (v4f32 VPR128:$src))), (v4i32 VPR128:$src)>;
6282 def : Pat<(v8i16 (bitconvert (v4f32 VPR128:$src))), (v8i16 VPR128:$src)>;
6283 def : Pat<(v16i8 (bitconvert (v4f32 VPR128:$src))), (v16i8 VPR128:$src)>;
6285 def : Pat<(v2f64 (bitconvert (v2i64 VPR128:$src))), (v2f64 VPR128:$src)>;
6286 def : Pat<(v4f32 (bitconvert (v2i64 VPR128:$src))), (v4f32 VPR128:$src)>;
6287 def : Pat<(v4i32 (bitconvert (v2i64 VPR128:$src))), (v4i32 VPR128:$src)>;
6288 def : Pat<(v8i16 (bitconvert (v2i64 VPR128:$src))), (v8i16 VPR128:$src)>;
6289 def : Pat<(v16i8 (bitconvert (v2i64 VPR128:$src))), (v16i8 VPR128:$src)>;
6291 def : Pat<(v2i64 (bitconvert (v2f64 VPR128:$src))), (v2i64 VPR128:$src)>;
6292 def : Pat<(v4f32 (bitconvert (v2f64 VPR128:$src))), (v4f32 VPR128:$src)>;
6293 def : Pat<(v4i32 (bitconvert (v2f64 VPR128:$src))), (v4i32 VPR128:$src)>;
6294 def : Pat<(v8i16 (bitconvert (v2f64 VPR128:$src))), (v8i16 VPR128:$src)>;
6295 def : Pat<(v16i8 (bitconvert (v2f64 VPR128:$src))), (v16i8 VPR128:$src)>;
6297 // ...and scalar bitcasts...
6298 def : Pat<(f16 (bitconvert (v1i16 FPR16:$src))), (f16 FPR16:$src)>;
6299 def : Pat<(f32 (bitconvert (v1i32 FPR32:$src))), (f32 FPR32:$src)>;
6300 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
6301 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
6303 def : Pat<(i64 (bitconvert (v1i64 FPR64:$src))), (FMOVxd $src)>;
6304 def : Pat<(i64 (bitconvert (v1f64 FPR64:$src))), (FMOVxd $src)>;
6305 def : Pat<(i64 (bitconvert (v2i32 FPR64:$src))), (FMOVxd $src)>;
6306 def : Pat<(i64 (bitconvert (v2f32 FPR64:$src))), (FMOVxd $src)>;
6307 def : Pat<(i64 (bitconvert (v4i16 FPR64:$src))), (FMOVxd $src)>;
6308 def : Pat<(i64 (bitconvert (v8i8 FPR64:$src))), (FMOVxd $src)>;
6310 def : Pat<(i32 (bitconvert (v1i32 FPR32:$src))), (FMOVws $src)>;
6312 def : Pat<(v8i8 (bitconvert (v1i64 VPR64:$src))), (v8i8 VPR64:$src)>;
6313 def : Pat<(v4i16 (bitconvert (v1i64 VPR64:$src))), (v4i16 VPR64:$src)>;
6314 def : Pat<(v2i32 (bitconvert (v1i64 VPR64:$src))), (v2i32 VPR64:$src)>;
6316 def : Pat<(f64 (bitconvert (v8i8 VPR64:$src))), (f64 VPR64:$src)>;
6317 def : Pat<(f64 (bitconvert (v4i16 VPR64:$src))), (f64 VPR64:$src)>;
6318 def : Pat<(f64 (bitconvert (v2i32 VPR64:$src))), (f64 VPR64:$src)>;
6319 def : Pat<(f64 (bitconvert (v2f32 VPR64:$src))), (f64 VPR64:$src)>;
6320 def : Pat<(f64 (bitconvert (v1i64 VPR64:$src))), (f64 VPR64:$src)>;
6322 def : Pat<(f128 (bitconvert (v16i8 VPR128:$src))), (f128 VPR128:$src)>;
6323 def : Pat<(f128 (bitconvert (v8i16 VPR128:$src))), (f128 VPR128:$src)>;
6324 def : Pat<(f128 (bitconvert (v4i32 VPR128:$src))), (f128 VPR128:$src)>;
6325 def : Pat<(f128 (bitconvert (v2i64 VPR128:$src))), (f128 VPR128:$src)>;
6326 def : Pat<(f128 (bitconvert (v4f32 VPR128:$src))), (f128 VPR128:$src)>;
6327 def : Pat<(f128 (bitconvert (v2f64 VPR128:$src))), (f128 VPR128:$src)>;
6329 def : Pat<(v1i16 (bitconvert (f16 FPR16:$src))), (v1i16 FPR16:$src)>;
6330 def : Pat<(v1i32 (bitconvert (f32 FPR32:$src))), (v1i32 FPR32:$src)>;
6331 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
6332 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
6334 def : Pat<(v1i64 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6335 def : Pat<(v1f64 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6336 def : Pat<(v2i32 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6337 def : Pat<(v2f32 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6338 def : Pat<(v4i16 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6339 def : Pat<(v8i8 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6341 def : Pat<(v1i32 (bitconvert (i32 GPR32:$src))), (FMOVsw $src)>;
6343 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
6344 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
6345 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
6346 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
6347 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
6349 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
6350 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
6351 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
6352 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
6353 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
6354 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
6356 // Scalar Three Same
6358 def neon_uimm3 : Operand<i64>,
6359 ImmLeaf<i64, [{return Imm < 8;}]> {
6360 let ParserMatchClass = uimm3_asmoperand;
6361 let PrintMethod = "printUImmHexOperand";
6364 def neon_uimm4 : Operand<i64>,
6365 ImmLeaf<i64, [{return Imm < 16;}]> {
6366 let ParserMatchClass = uimm4_asmoperand;
6367 let PrintMethod = "printUImmHexOperand";
6371 class NeonI_Extract<bit q, bits<2> op2, string asmop,
6372 string OpS, RegisterOperand OpVPR, Operand OpImm>
6373 : NeonI_BitExtract<q, op2, (outs OpVPR:$Rd),
6374 (ins OpVPR:$Rn, OpVPR:$Rm, OpImm:$Index),
6375 asmop # "\t$Rd." # OpS # ", $Rn." # OpS #
6376 ", $Rm." # OpS # ", $Index",
6382 def EXTvvvi_8b : NeonI_Extract<0b0, 0b00, "ext", "8b",
6383 VPR64, neon_uimm3> {
6384 let Inst{14-11} = {0b0, Index{2}, Index{1}, Index{0}};
6387 def EXTvvvi_16b: NeonI_Extract<0b1, 0b00, "ext", "16b",
6388 VPR128, neon_uimm4> {
6389 let Inst{14-11} = Index;
6392 class NI_Extract<ValueType OpTy, RegisterOperand OpVPR, Instruction INST,
6394 : Pat<(OpTy (Neon_vextract (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm),
6396 (INST OpVPR:$Rn, OpVPR:$Rm, OpImm:$Imm)>;
6398 def : NI_Extract<v8i8, VPR64, EXTvvvi_8b, neon_uimm3>;
6399 def : NI_Extract<v4i16, VPR64, EXTvvvi_8b, neon_uimm3>;
6400 def : NI_Extract<v2i32, VPR64, EXTvvvi_8b, neon_uimm3>;
6401 def : NI_Extract<v1i64, VPR64, EXTvvvi_8b, neon_uimm3>;
6402 def : NI_Extract<v2f32, VPR64, EXTvvvi_8b, neon_uimm3>;
6403 def : NI_Extract<v1f64, VPR64, EXTvvvi_8b, neon_uimm3>;
6404 def : NI_Extract<v16i8, VPR128, EXTvvvi_16b, neon_uimm4>;
6405 def : NI_Extract<v8i16, VPR128, EXTvvvi_16b, neon_uimm4>;
6406 def : NI_Extract<v4i32, VPR128, EXTvvvi_16b, neon_uimm4>;
6407 def : NI_Extract<v2i64, VPR128, EXTvvvi_16b, neon_uimm4>;
6408 def : NI_Extract<v4f32, VPR128, EXTvvvi_16b, neon_uimm4>;
6409 def : NI_Extract<v2f64, VPR128, EXTvvvi_16b, neon_uimm4>;
6412 class NI_TBL<bit q, bits<2> op2, bits<2> len, bit op,
6413 string asmop, string OpS, RegisterOperand OpVPR,
6414 RegisterOperand VecList>
6415 : NeonI_TBL<q, op2, len, op,
6416 (outs OpVPR:$Rd), (ins VecList:$Rn, OpVPR:$Rm),
6417 asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6421 // The vectors in look up table are always 16b
6422 multiclass NI_TBL_pat<bits<2> len, bit op, string asmop, string List> {
6423 def _8b : NI_TBL<0, 0b00, len, op, asmop, "8b", VPR64,
6424 !cast<RegisterOperand>(List # "16B_operand")>;
6426 def _16b : NI_TBL<1, 0b00, len, op, asmop, "16b", VPR128,
6427 !cast<RegisterOperand>(List # "16B_operand")>;
6430 defm TBL1 : NI_TBL_pat<0b00, 0b0, "tbl", "VOne">;
6431 defm TBL2 : NI_TBL_pat<0b01, 0b0, "tbl", "VPair">;
6432 defm TBL3 : NI_TBL_pat<0b10, 0b0, "tbl", "VTriple">;
6433 defm TBL4 : NI_TBL_pat<0b11, 0b0, "tbl", "VQuad">;
6435 // Table lookup extension
6436 class NI_TBX<bit q, bits<2> op2, bits<2> len, bit op,
6437 string asmop, string OpS, RegisterOperand OpVPR,
6438 RegisterOperand VecList>
6439 : NeonI_TBL<q, op2, len, op,
6440 (outs OpVPR:$Rd), (ins OpVPR:$src, VecList:$Rn, OpVPR:$Rm),
6441 asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6444 let Constraints = "$src = $Rd";
6447 // The vectors in look up table are always 16b
6448 multiclass NI_TBX_pat<bits<2> len, bit op, string asmop, string List> {
6449 def _8b : NI_TBX<0, 0b00, len, op, asmop, "8b", VPR64,
6450 !cast<RegisterOperand>(List # "16B_operand")>;
6452 def _16b : NI_TBX<1, 0b00, len, op, asmop, "16b", VPR128,
6453 !cast<RegisterOperand>(List # "16B_operand")>;
6456 defm TBX1 : NI_TBX_pat<0b00, 0b1, "tbx", "VOne">;
6457 defm TBX2 : NI_TBX_pat<0b01, 0b1, "tbx", "VPair">;
6458 defm TBX3 : NI_TBX_pat<0b10, 0b1, "tbx", "VTriple">;
6459 defm TBX4 : NI_TBX_pat<0b11, 0b1, "tbx", "VQuad">;
6461 class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
6462 RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
6463 : NeonI_copy<0b1, 0b0, 0b0011,
6464 (outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
6465 asmop # "\t$Rd." # Res # "[$Imm], $Rn",
6466 [(set (ResTy VPR128:$Rd),
6467 (ResTy (vector_insert
6468 (ResTy VPR128:$src),
6473 let Constraints = "$src = $Rd";
6476 //Insert element (vector, from main)
6477 def INSbw : NeonI_INS_main<"ins", "b", v16i8, GPR32, i32,
6479 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6481 def INShw : NeonI_INS_main<"ins", "h", v8i16, GPR32, i32,
6483 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6485 def INSsw : NeonI_INS_main<"ins", "s", v4i32, GPR32, i32,
6487 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6489 def INSdx : NeonI_INS_main<"ins", "d", v2i64, GPR64, i64,
6491 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6494 def : NeonInstAlias<"mov $Rd.b[$Imm], $Rn",
6495 (INSbw VPR128:$Rd, GPR32:$Rn, neon_uimm4_bare:$Imm), 0>;
6496 def : NeonInstAlias<"mov $Rd.h[$Imm], $Rn",
6497 (INShw VPR128:$Rd, GPR32:$Rn, neon_uimm3_bare:$Imm), 0>;
6498 def : NeonInstAlias<"mov $Rd.s[$Imm], $Rn",
6499 (INSsw VPR128:$Rd, GPR32:$Rn, neon_uimm2_bare:$Imm), 0>;
6500 def : NeonInstAlias<"mov $Rd.d[$Imm], $Rn",
6501 (INSdx VPR128:$Rd, GPR64:$Rn, neon_uimm1_bare:$Imm), 0>;
6503 class Neon_INS_main_pattern <ValueType ResTy,ValueType ExtResTy,
6504 RegisterClass OpGPR, ValueType OpTy,
6505 Operand OpImm, Instruction INS>
6506 : Pat<(ResTy (vector_insert
6510 (ResTy (EXTRACT_SUBREG
6511 (ExtResTy (INS (ExtResTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
6512 OpGPR:$Rn, OpImm:$Imm)), sub_64))>;
6514 def INSbw_pattern : Neon_INS_main_pattern<v8i8, v16i8, GPR32, i32,
6515 neon_uimm3_bare, INSbw>;
6516 def INShw_pattern : Neon_INS_main_pattern<v4i16, v8i16, GPR32, i32,
6517 neon_uimm2_bare, INShw>;
6518 def INSsw_pattern : Neon_INS_main_pattern<v2i32, v4i32, GPR32, i32,
6519 neon_uimm1_bare, INSsw>;
6520 def INSdx_pattern : Neon_INS_main_pattern<v1i64, v2i64, GPR64, i64,
6521 neon_uimm0_bare, INSdx>;
6523 class NeonI_INS_element<string asmop, string Res, Operand ResImm>
6524 : NeonI_insert<0b1, 0b1,
6525 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn,
6526 ResImm:$Immd, ResImm:$Immn),
6527 asmop # "\t$Rd." # Res # "[$Immd], $Rn." # Res # "[$Immn]",
6530 let Constraints = "$src = $Rd";
6535 //Insert element (vector, from element)
6536 def INSELb : NeonI_INS_element<"ins", "b", neon_uimm4_bare> {
6537 let Inst{20-16} = {Immd{3}, Immd{2}, Immd{1}, Immd{0}, 0b1};
6538 let Inst{14-11} = {Immn{3}, Immn{2}, Immn{1}, Immn{0}};
6540 def INSELh : NeonI_INS_element<"ins", "h", neon_uimm3_bare> {
6541 let Inst{20-16} = {Immd{2}, Immd{1}, Immd{0}, 0b1, 0b0};
6542 let Inst{14-11} = {Immn{2}, Immn{1}, Immn{0}, 0b0};
6543 // bit 11 is unspecified, but should be set to zero.
6545 def INSELs : NeonI_INS_element<"ins", "s", neon_uimm2_bare> {
6546 let Inst{20-16} = {Immd{1}, Immd{0}, 0b1, 0b0, 0b0};
6547 let Inst{14-11} = {Immn{1}, Immn{0}, 0b0, 0b0};
6548 // bits 11-12 are unspecified, but should be set to zero.
6550 def INSELd : NeonI_INS_element<"ins", "d", neon_uimm1_bare> {
6551 let Inst{20-16} = {Immd, 0b1, 0b0, 0b0, 0b0};
6552 let Inst{14-11} = {Immn{0}, 0b0, 0b0, 0b0};
6553 // bits 11-13 are unspecified, but should be set to zero.
6556 def : NeonInstAlias<"mov $Rd.b[$Immd], $Rn.b[$Immn]",
6557 (INSELb VPR128:$Rd, VPR128:$Rn,
6558 neon_uimm4_bare:$Immd, neon_uimm4_bare:$Immn), 0>;
6559 def : NeonInstAlias<"mov $Rd.h[$Immd], $Rn.h[$Immn]",
6560 (INSELh VPR128:$Rd, VPR128:$Rn,
6561 neon_uimm3_bare:$Immd, neon_uimm3_bare:$Immn), 0>;
6562 def : NeonInstAlias<"mov $Rd.s[$Immd], $Rn.s[$Immn]",
6563 (INSELs VPR128:$Rd, VPR128:$Rn,
6564 neon_uimm2_bare:$Immd, neon_uimm2_bare:$Immn), 0>;
6565 def : NeonInstAlias<"mov $Rd.d[$Immd], $Rn.d[$Immn]",
6566 (INSELd VPR128:$Rd, VPR128:$Rn,
6567 neon_uimm1_bare:$Immd, neon_uimm1_bare:$Immn), 0>;
6569 multiclass Neon_INS_elt_pattern<ValueType ResTy, ValueType NaTy,
6570 ValueType MidTy, Operand StImm, Operand NaImm,
6572 def : Pat<(ResTy (vector_insert
6573 (ResTy VPR128:$src),
6574 (MidTy (vector_extract
6578 (INS (ResTy VPR128:$src), (ResTy VPR128:$Rn),
6579 StImm:$Immd, StImm:$Immn)>;
6581 def : Pat <(ResTy (vector_insert
6582 (ResTy VPR128:$src),
6583 (MidTy (vector_extract
6587 (INS (ResTy VPR128:$src),
6588 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6589 StImm:$Immd, NaImm:$Immn)>;
6591 def : Pat <(NaTy (vector_insert
6593 (MidTy (vector_extract
6597 (NaTy (EXTRACT_SUBREG
6599 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6601 NaImm:$Immd, StImm:$Immn)),
6604 def : Pat <(NaTy (vector_insert
6606 (MidTy (vector_extract
6610 (NaTy (EXTRACT_SUBREG
6612 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6613 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6614 NaImm:$Immd, NaImm:$Immn)),
6618 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, neon_uimm2_bare,
6619 neon_uimm1_bare, INSELs>;
6620 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, neon_uimm1_bare,
6621 neon_uimm0_bare, INSELd>;
6622 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6623 neon_uimm3_bare, INSELb>;
6624 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6625 neon_uimm2_bare, INSELh>;
6626 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6627 neon_uimm1_bare, INSELs>;
6628 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, neon_uimm1_bare,
6629 neon_uimm0_bare, INSELd>;
6631 multiclass Neon_INS_elt_float_pattern<ValueType ResTy, ValueType NaTy,
6633 RegisterClass OpFPR, Operand ResImm,
6634 SubRegIndex SubIndex, Instruction INS> {
6635 def : Pat <(ResTy (vector_insert
6636 (ResTy VPR128:$src),
6639 (INS (ResTy VPR128:$src),
6640 (ResTy (SUBREG_TO_REG (i64 0), OpFPR:$Rn, SubIndex)),
6644 def : Pat <(NaTy (vector_insert
6648 (NaTy (EXTRACT_SUBREG
6650 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6651 (ResTy (SUBREG_TO_REG (i64 0), (MidTy OpFPR:$Rn), SubIndex)),
6657 defm : Neon_INS_elt_float_pattern<v4f32, v2f32, f32, FPR32, neon_uimm2_bare,
6659 defm : Neon_INS_elt_float_pattern<v2f64, v1f64, f64, FPR64, neon_uimm1_bare,
6662 class NeonI_SMOV<string asmop, string Res, bit Q,
6663 ValueType OpTy, ValueType eleTy,
6664 Operand OpImm, RegisterClass ResGPR, ValueType ResTy>
6665 : NeonI_copy<Q, 0b0, 0b0101,
6666 (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6667 asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6668 [(set (ResTy ResGPR:$Rd),
6670 (ResTy (vector_extract
6671 (OpTy VPR128:$Rn), (OpImm:$Imm))),
6677 //Signed integer move (main, from element)
6678 def SMOVwb : NeonI_SMOV<"smov", "b", 0b0, v16i8, i8, neon_uimm4_bare,
6680 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6682 def SMOVwh : NeonI_SMOV<"smov", "h", 0b0, v8i16, i16, neon_uimm3_bare,
6684 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6686 def SMOVxb : NeonI_SMOV<"smov", "b", 0b1, v16i8, i8, neon_uimm4_bare,
6688 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6690 def SMOVxh : NeonI_SMOV<"smov", "h", 0b1, v8i16, i16, neon_uimm3_bare,
6692 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6694 def SMOVxs : NeonI_SMOV<"smov", "s", 0b1, v4i32, i32, neon_uimm2_bare,
6696 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6699 multiclass Neon_SMOVx_pattern <ValueType StTy, ValueType NaTy,
6700 ValueType eleTy, Operand StImm, Operand NaImm,
6701 Instruction SMOVI> {
6702 def : Pat<(i64 (sext_inreg
6704 (i32 (vector_extract
6705 (StTy VPR128:$Rn), (StImm:$Imm))))),
6707 (SMOVI VPR128:$Rn, StImm:$Imm)>;
6709 def : Pat<(i64 (sext
6710 (i32 (vector_extract
6711 (StTy VPR128:$Rn), (StImm:$Imm))))),
6712 (SMOVI VPR128:$Rn, StImm:$Imm)>;
6714 def : Pat<(i64 (sext_inreg
6715 (i64 (vector_extract
6716 (NaTy VPR64:$Rn), (NaImm:$Imm))),
6718 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6721 def : Pat<(i64 (sext_inreg
6723 (i32 (vector_extract
6724 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6726 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6729 def : Pat<(i64 (sext
6730 (i32 (vector_extract
6731 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6732 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6736 defm : Neon_SMOVx_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6737 neon_uimm3_bare, SMOVxb>;
6738 defm : Neon_SMOVx_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6739 neon_uimm2_bare, SMOVxh>;
6740 defm : Neon_SMOVx_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6741 neon_uimm1_bare, SMOVxs>;
6743 class Neon_SMOVw_pattern <ValueType StTy, ValueType NaTy,
6744 ValueType eleTy, Operand StImm, Operand NaImm,
6746 : Pat<(i32 (sext_inreg
6747 (i32 (vector_extract
6748 (NaTy VPR64:$Rn), (NaImm:$Imm))),
6750 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6753 def : Neon_SMOVw_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6754 neon_uimm3_bare, SMOVwb>;
6755 def : Neon_SMOVw_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6756 neon_uimm2_bare, SMOVwh>;
6758 class NeonI_UMOV<string asmop, string Res, bit Q,
6759 ValueType OpTy, Operand OpImm,
6760 RegisterClass ResGPR, ValueType ResTy>
6761 : NeonI_copy<Q, 0b0, 0b0111,
6762 (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6763 asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6764 [(set (ResTy ResGPR:$Rd),
6765 (ResTy (vector_extract
6766 (OpTy VPR128:$Rn), (OpImm:$Imm))))],
6771 //Unsigned integer move (main, from element)
6772 def UMOVwb : NeonI_UMOV<"umov", "b", 0b0, v16i8, neon_uimm4_bare,
6774 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6776 def UMOVwh : NeonI_UMOV<"umov", "h", 0b0, v8i16, neon_uimm3_bare,
6778 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6780 def UMOVws : NeonI_UMOV<"umov", "s", 0b0, v4i32, neon_uimm2_bare,
6782 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6784 def UMOVxd : NeonI_UMOV<"umov", "d", 0b1, v2i64, neon_uimm1_bare,
6786 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6789 def : NeonInstAlias<"mov $Rd, $Rn.s[$Imm]",
6790 (UMOVws GPR32:$Rd, VPR128:$Rn, neon_uimm2_bare:$Imm), 0>;
6791 def : NeonInstAlias<"mov $Rd, $Rn.d[$Imm]",
6792 (UMOVxd GPR64:$Rd, VPR128:$Rn, neon_uimm1_bare:$Imm), 0>;
6794 class Neon_UMOV_pattern <ValueType StTy, ValueType NaTy, ValueType ResTy,
6795 Operand StImm, Operand NaImm,
6797 : Pat<(ResTy (vector_extract
6798 (NaTy VPR64:$Rn), NaImm:$Imm)),
6799 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6802 def : Neon_UMOV_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6803 neon_uimm3_bare, UMOVwb>;
6804 def : Neon_UMOV_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6805 neon_uimm2_bare, UMOVwh>;
6806 def : Neon_UMOV_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6807 neon_uimm1_bare, UMOVws>;
6810 (i32 (vector_extract
6811 (v16i8 VPR128:$Rn), (neon_uimm4_bare:$Imm))),
6813 (UMOVwb VPR128:$Rn, neon_uimm4_bare:$Imm)>;
6816 (i32 (vector_extract
6817 (v8i16 VPR128:$Rn), (neon_uimm3_bare:$Imm))),
6819 (UMOVwh VPR128:$Rn, neon_uimm3_bare:$Imm)>;
6821 def : Pat<(i64 (zext
6822 (i32 (vector_extract
6823 (v2i64 VPR128:$Rn), (neon_uimm1_bare:$Imm))))),
6824 (UMOVxd VPR128:$Rn, neon_uimm1_bare:$Imm)>;
6827 (i32 (vector_extract
6828 (v8i8 VPR64:$Rn), (neon_uimm3_bare:$Imm))),
6830 (UMOVwb (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6831 neon_uimm3_bare:$Imm)>;
6834 (i32 (vector_extract
6835 (v4i16 VPR64:$Rn), (neon_uimm2_bare:$Imm))),
6837 (UMOVwh (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6838 neon_uimm2_bare:$Imm)>;
6840 def : Pat<(i64 (zext
6841 (i32 (vector_extract
6842 (v1i64 VPR64:$Rn), (neon_uimm0_bare:$Imm))))),
6843 (UMOVxd (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6844 neon_uimm0_bare:$Imm)>;
6846 // Additional copy patterns for scalar types
6847 def : Pat<(i32 (vector_extract (v1i8 FPR8:$Rn), (i64 0))),
6849 (SUBREG_TO_REG (i64 0), FPR8:$Rn, sub_8)), (i64 0))>;
6851 def : Pat<(i32 (vector_extract (v1i16 FPR16:$Rn), (i64 0))),
6853 (SUBREG_TO_REG (i64 0), FPR16:$Rn, sub_16)), (i64 0))>;
6855 def : Pat<(i32 (vector_extract (v1i32 FPR32:$Rn), (i64 0))),
6856 (FMOVws FPR32:$Rn)>;
6858 def : Pat<(i64 (vector_extract (v1i64 FPR64:$Rn), (i64 0))),
6859 (FMOVxd FPR64:$Rn)>;
6861 def : Pat<(f64 (vector_extract (v1f64 FPR64:$Rn), (i64 0))),
6864 def : Pat<(v1i8 (scalar_to_vector GPR32:$Rn)),
6865 (v1i8 (EXTRACT_SUBREG (v16i8
6866 (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
6869 def : Pat<(v1i16 (scalar_to_vector GPR32:$Rn)),
6870 (v1i16 (EXTRACT_SUBREG (v8i16
6871 (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
6874 def : Pat<(v1i32 (scalar_to_vector GPR32:$src)),
6877 def : Pat<(v1i64 (scalar_to_vector GPR64:$src)),
6880 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
6881 (v8i8 (EXTRACT_SUBREG (v16i8
6882 (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
6885 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
6886 (v4i16 (EXTRACT_SUBREG (v8i16
6887 (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
6890 def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)),
6891 (v2i32 (EXTRACT_SUBREG (v16i8
6892 (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))),
6895 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
6896 (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6898 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
6899 (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6901 def : Pat<(v4i32 (scalar_to_vector GPR32:$Rn)),
6902 (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6904 def : Pat<(v2i64 (scalar_to_vector GPR64:$Rn)),
6905 (INSdx (v2i64 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6907 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
6908 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32)>;
6909 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
6910 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32)>;
6912 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
6915 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$src))),
6916 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
6917 (f64 FPR64:$src), sub_64)>;
6919 class NeonI_DUP_Elt<bit Q, string asmop, string rdlane, string rnlane,
6920 RegisterOperand ResVPR, Operand OpImm>
6921 : NeonI_copy<Q, 0b0, 0b0000, (outs ResVPR:$Rd),
6922 (ins VPR128:$Rn, OpImm:$Imm),
6923 asmop # "\t$Rd" # rdlane # ", $Rn" # rnlane # "[$Imm]",
6929 def DUPELT16b : NeonI_DUP_Elt<0b1, "dup", ".16b", ".b", VPR128,
6931 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6934 def DUPELT8h : NeonI_DUP_Elt<0b1, "dup", ".8h", ".h", VPR128,
6936 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6939 def DUPELT4s : NeonI_DUP_Elt<0b1, "dup", ".4s", ".s", VPR128,
6941 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6944 def DUPELT2d : NeonI_DUP_Elt<0b1, "dup", ".2d", ".d", VPR128,
6946 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6949 def DUPELT8b : NeonI_DUP_Elt<0b0, "dup", ".8b", ".b", VPR64,
6951 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6954 def DUPELT4h : NeonI_DUP_Elt<0b0, "dup", ".4h", ".h", VPR64,
6956 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6959 def DUPELT2s : NeonI_DUP_Elt<0b0, "dup", ".2s", ".s", VPR64,
6961 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6964 multiclass NeonI_DUP_Elt_pattern<Instruction DUPELT, ValueType ResTy,
6965 ValueType OpTy,ValueType NaTy,
6966 ValueType ExTy, Operand OpLImm,
6968 def : Pat<(ResTy (Neon_vduplane (OpTy VPR128:$Rn), OpLImm:$Imm)),
6969 (ResTy (DUPELT (OpTy VPR128:$Rn), OpLImm:$Imm))>;
6971 def : Pat<(ResTy (Neon_vduplane
6972 (NaTy VPR64:$Rn), OpNImm:$Imm)),
6974 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)), OpNImm:$Imm))>;
6976 defm : NeonI_DUP_Elt_pattern<DUPELT16b, v16i8, v16i8, v8i8, v16i8,
6977 neon_uimm4_bare, neon_uimm3_bare>;
6978 defm : NeonI_DUP_Elt_pattern<DUPELT8b, v8i8, v16i8, v8i8, v16i8,
6979 neon_uimm4_bare, neon_uimm3_bare>;
6980 defm : NeonI_DUP_Elt_pattern<DUPELT8h, v8i16, v8i16, v4i16, v8i16,
6981 neon_uimm3_bare, neon_uimm2_bare>;
6982 defm : NeonI_DUP_Elt_pattern<DUPELT4h, v4i16, v8i16, v4i16, v8i16,
6983 neon_uimm3_bare, neon_uimm2_bare>;
6984 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4i32, v4i32, v2i32, v4i32,
6985 neon_uimm2_bare, neon_uimm1_bare>;
6986 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2i32, v4i32, v2i32, v4i32,
6987 neon_uimm2_bare, neon_uimm1_bare>;
6988 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2i64, v2i64, v1i64, v2i64,
6989 neon_uimm1_bare, neon_uimm0_bare>;
6990 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4f32, v4f32, v2f32, v4f32,
6991 neon_uimm2_bare, neon_uimm1_bare>;
6992 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2f32, v4f32, v2f32, v4f32,
6993 neon_uimm2_bare, neon_uimm1_bare>;
6994 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2f64, v2f64, v1f64, v2f64,
6995 neon_uimm1_bare, neon_uimm0_bare>;
6997 def : Pat<(v2f32 (Neon_vdup (f32 FPR32:$Rn))),
6999 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
7001 def : Pat<(v4f32 (Neon_vdup (f32 FPR32:$Rn))),
7003 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
7005 def : Pat<(v2f64 (Neon_vdup (f64 FPR64:$Rn))),
7007 (SUBREG_TO_REG (i64 0), FPR64:$Rn, sub_64),
7010 class NeonI_DUP<bit Q, string asmop, string rdlane,
7011 RegisterOperand ResVPR, ValueType ResTy,
7012 RegisterClass OpGPR, ValueType OpTy>
7013 : NeonI_copy<Q, 0b0, 0b0001, (outs ResVPR:$Rd), (ins OpGPR:$Rn),
7014 asmop # "\t$Rd" # rdlane # ", $Rn",
7015 [(set (ResTy ResVPR:$Rd),
7016 (ResTy (Neon_vdup (OpTy OpGPR:$Rn))))],
7019 def DUP16b : NeonI_DUP<0b1, "dup", ".16b", VPR128, v16i8, GPR32, i32> {
7020 let Inst{20-16} = 0b00001;
7021 // bits 17-20 are unspecified, but should be set to zero.
7024 def DUP8h : NeonI_DUP<0b1, "dup", ".8h", VPR128, v8i16, GPR32, i32> {
7025 let Inst{20-16} = 0b00010;
7026 // bits 18-20 are unspecified, but should be set to zero.
7029 def DUP4s : NeonI_DUP<0b1, "dup", ".4s", VPR128, v4i32, GPR32, i32> {
7030 let Inst{20-16} = 0b00100;
7031 // bits 19-20 are unspecified, but should be set to zero.
7034 def DUP2d : NeonI_DUP<0b1, "dup", ".2d", VPR128, v2i64, GPR64, i64> {
7035 let Inst{20-16} = 0b01000;
7036 // bit 20 is unspecified, but should be set to zero.
7039 def DUP8b : NeonI_DUP<0b0, "dup", ".8b", VPR64, v8i8, GPR32, i32> {
7040 let Inst{20-16} = 0b00001;
7041 // bits 17-20 are unspecified, but should be set to zero.
7044 def DUP4h : NeonI_DUP<0b0, "dup", ".4h", VPR64, v4i16, GPR32, i32> {
7045 let Inst{20-16} = 0b00010;
7046 // bits 18-20 are unspecified, but should be set to zero.
7049 def DUP2s : NeonI_DUP<0b0, "dup", ".2s", VPR64, v2i32, GPR32, i32> {
7050 let Inst{20-16} = 0b00100;
7051 // bits 19-20 are unspecified, but should be set to zero.
7054 // patterns for CONCAT_VECTORS
7055 multiclass Concat_Vector_Pattern<ValueType ResTy, ValueType OpTy> {
7056 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), undef)),
7057 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)>;
7058 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))),
7060 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7061 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rm, sub_64)),
7064 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rn))),
7066 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
7070 defm : Concat_Vector_Pattern<v16i8, v8i8>;
7071 defm : Concat_Vector_Pattern<v8i16, v4i16>;
7072 defm : Concat_Vector_Pattern<v4i32, v2i32>;
7073 defm : Concat_Vector_Pattern<v2i64, v1i64>;
7074 defm : Concat_Vector_Pattern<v4f32, v2f32>;
7075 defm : Concat_Vector_Pattern<v2f64, v1f64>;
7077 def : Pat<(v2i32 (concat_vectors (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rn))),
7078 (DUPELT2s (v4i32 (SUBREG_TO_REG(i64 0), $Rn, sub_32)), 0)>;
7079 def : Pat<(v2i32 (concat_vectors undef, (v1i32 FPR32:$Rn))),
7080 (DUPELT2s (v4i32 (SUBREG_TO_REG(i64 0), $Rn, sub_32)), 0)>;
7082 //patterns for EXTRACT_SUBVECTOR
7083 def : Pat<(v8i8 (extract_subvector (v16i8 VPR128:$Rn), (i64 0))),
7084 (v8i8 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7085 def : Pat<(v4i16 (extract_subvector (v8i16 VPR128:$Rn), (i64 0))),
7086 (v4i16 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7087 def : Pat<(v2i32 (extract_subvector (v4i32 VPR128:$Rn), (i64 0))),
7088 (v2i32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7089 def : Pat<(v1i64 (extract_subvector (v2i64 VPR128:$Rn), (i64 0))),
7090 (v1i64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7091 def : Pat<(v2f32 (extract_subvector (v4f32 VPR128:$Rn), (i64 0))),
7092 (v2f32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7093 def : Pat<(v1f64 (extract_subvector (v2f64 VPR128:$Rn), (i64 0))),
7094 (v1f64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
7096 // The followings are for instruction class (3V Elem)
7100 class NI_2VE<bit q, bit u, bits<2> size, bits<4> opcode,
7101 string asmop, string ResS, string OpS, string EleOpS,
7102 Operand OpImm, RegisterOperand ResVPR,
7103 RegisterOperand OpVPR, RegisterOperand EleOpVPR>
7104 : NeonI_2VElem<q, u, size, opcode,
7105 (outs ResVPR:$Rd), (ins ResVPR:$src, OpVPR:$Rn,
7106 EleOpVPR:$Re, OpImm:$Index),
7107 asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
7108 ", $Re." # EleOpS # "[$Index]",
7114 let Constraints = "$src = $Rd";
7117 multiclass NI_2VE_v1<bit u, bits<4> opcode, string asmop> {
7118 // vector register class for element is always 128-bit to cover the max index
7119 def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7120 neon_uimm2_bare, VPR64, VPR64, VPR128> {
7121 let Inst{11} = {Index{1}};
7122 let Inst{21} = {Index{0}};
7123 let Inst{20-16} = Re;
7126 def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7127 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7128 let Inst{11} = {Index{1}};
7129 let Inst{21} = {Index{0}};
7130 let Inst{20-16} = Re;
7133 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7134 def _4h8h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
7135 neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
7136 let Inst{11} = {Index{2}};
7137 let Inst{21} = {Index{1}};
7138 let Inst{20} = {Index{0}};
7139 let Inst{19-16} = Re{3-0};
7142 def _8h8h : NI_2VE<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
7143 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7144 let Inst{11} = {Index{2}};
7145 let Inst{21} = {Index{1}};
7146 let Inst{20} = {Index{0}};
7147 let Inst{19-16} = Re{3-0};
7151 defm MLAvve : NI_2VE_v1<0b1, 0b0000, "mla">;
7152 defm MLSvve : NI_2VE_v1<0b1, 0b0100, "mls">;
7154 // Pattern for lane in 128-bit vector
7155 class NI_2VE_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7156 RegisterOperand ResVPR, RegisterOperand OpVPR,
7157 RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
7159 : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
7160 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7161 (INST ResVPR:$src, OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7163 // Pattern for lane in 64-bit vector
7164 class NI_2VE_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7165 RegisterOperand ResVPR, RegisterOperand OpVPR,
7166 RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
7168 : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
7169 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7170 (INST ResVPR:$src, OpVPR:$Rn,
7171 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7173 multiclass NI_2VE_v1_pat<string subop, SDPatternOperator op>
7175 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7176 op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32>;
7178 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7179 op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32>;
7181 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
7182 op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
7184 def : NI_2VE_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
7185 op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
7187 // Index can only be half of the max value for lane in 64-bit vector
7189 def : NI_2VE_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7190 op, VPR64, VPR64, VPR64, v2i32, v2i32, v2i32>;
7192 def : NI_2VE_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
7193 op, VPR64, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
7196 defm MLA_lane_v1 : NI_2VE_v1_pat<"MLAvve", Neon_mla>;
7197 defm MLS_lane_v1 : NI_2VE_v1_pat<"MLSvve", Neon_mls>;
7199 class NI_2VE_2op<bit q, bit u, bits<2> size, bits<4> opcode,
7200 string asmop, string ResS, string OpS, string EleOpS,
7201 Operand OpImm, RegisterOperand ResVPR,
7202 RegisterOperand OpVPR, RegisterOperand EleOpVPR>
7203 : NeonI_2VElem<q, u, size, opcode,
7204 (outs ResVPR:$Rd), (ins OpVPR:$Rn,
7205 EleOpVPR:$Re, OpImm:$Index),
7206 asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
7207 ", $Re." # EleOpS # "[$Index]",
7214 multiclass NI_2VE_v1_2op<bit u, bits<4> opcode, string asmop> {
7215 // vector register class for element is always 128-bit to cover the max index
7216 def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7217 neon_uimm2_bare, VPR64, VPR64, VPR128> {
7218 let Inst{11} = {Index{1}};
7219 let Inst{21} = {Index{0}};
7220 let Inst{20-16} = Re;
7223 def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7224 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7225 let Inst{11} = {Index{1}};
7226 let Inst{21} = {Index{0}};
7227 let Inst{20-16} = Re;
7230 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7231 def _4h8h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
7232 neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
7233 let Inst{11} = {Index{2}};
7234 let Inst{21} = {Index{1}};
7235 let Inst{20} = {Index{0}};
7236 let Inst{19-16} = Re{3-0};
7239 def _8h8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
7240 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7241 let Inst{11} = {Index{2}};
7242 let Inst{21} = {Index{1}};
7243 let Inst{20} = {Index{0}};
7244 let Inst{19-16} = Re{3-0};
7248 defm MULve : NI_2VE_v1_2op<0b0, 0b1000, "mul">;
7249 defm SQDMULHve : NI_2VE_v1_2op<0b0, 0b1100, "sqdmulh">;
7250 defm SQRDMULHve : NI_2VE_v1_2op<0b0, 0b1101, "sqrdmulh">;
7252 // Pattern for lane in 128-bit vector
7253 class NI_2VE_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7254 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7255 ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7256 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7257 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7258 (INST OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7260 // Pattern for lane in 64-bit vector
7261 class NI_2VE_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7262 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7263 ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7264 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7265 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7267 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7269 multiclass NI_2VE_mul_v1_pat<string subop, SDPatternOperator op> {
7270 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7271 op, VPR64, VPR128, v2i32, v2i32, v4i32>;
7273 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7274 op, VPR128, VPR128, v4i32, v4i32, v4i32>;
7276 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
7277 op, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
7279 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
7280 op, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
7282 // Index can only be half of the max value for lane in 64-bit vector
7284 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7285 op, VPR64, VPR64, v2i32, v2i32, v2i32>;
7287 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
7288 op, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
7291 defm MUL_lane_v1 : NI_2VE_mul_v1_pat<"MULve", mul>;
7292 defm SQDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQDMULHve", int_arm_neon_vqdmulh>;
7293 defm SQRDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQRDMULHve", int_arm_neon_vqrdmulh>;
7297 multiclass NI_2VE_v2_2op<bit u, bits<4> opcode, string asmop> {
7298 // vector register class for element is always 128-bit to cover the max index
7299 def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7300 neon_uimm2_bare, VPR64, VPR64, VPR128> {
7301 let Inst{11} = {Index{1}};
7302 let Inst{21} = {Index{0}};
7303 let Inst{20-16} = Re;
7306 def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7307 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7308 let Inst{11} = {Index{1}};
7309 let Inst{21} = {Index{0}};
7310 let Inst{20-16} = Re;
7313 // _1d2d doesn't exist!
7315 def _2d2d : NI_2VE_2op<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7316 neon_uimm1_bare, VPR128, VPR128, VPR128> {
7317 let Inst{11} = {Index{0}};
7319 let Inst{20-16} = Re;
7323 defm FMULve : NI_2VE_v2_2op<0b0, 0b1001, "fmul">;
7324 defm FMULXve : NI_2VE_v2_2op<0b1, 0b1001, "fmulx">;
7326 class NI_2VE_mul_lane_2d<Instruction INST, Operand OpImm, SDPatternOperator op,
7327 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7328 ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
7329 SDPatternOperator coreop>
7330 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7331 (OpTy (coreop (EleOpTy EleOpVPR:$Re), (EleOpTy EleOpVPR:$Re))))),
7333 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), 0)>;
7335 multiclass NI_2VE_mul_v2_pat<string subop, SDPatternOperator op> {
7336 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7337 op, VPR64, VPR128, v2f32, v2f32, v4f32>;
7339 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7340 op, VPR128, VPR128, v4f32, v4f32, v4f32>;
7342 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7343 op, VPR128, VPR128, v2f64, v2f64, v2f64>;
7345 // Index can only be half of the max value for lane in 64-bit vector
7347 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7348 op, VPR64, VPR64, v2f32, v2f32, v2f32>;
7350 def : NI_2VE_mul_lane_2d<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7351 op, VPR128, VPR64, v2f64, v2f64, v1f64,
7352 BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7355 defm FMUL_lane_v2 : NI_2VE_mul_v2_pat<"FMULve", fmul>;
7356 defm FMULX_lane_v2 : NI_2VE_mul_v2_pat<"FMULXve", int_aarch64_neon_vmulx>;
7358 def : Pat<(v2f32 (fmul (v2f32 (Neon_vdup (f32 FPR32:$Re))),
7359 (v2f32 VPR64:$Rn))),
7360 (FMULve_2s4s VPR64:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7362 def : Pat<(v4f32 (fmul (v4f32 (Neon_vdup (f32 FPR32:$Re))),
7363 (v4f32 VPR128:$Rn))),
7364 (FMULve_4s4s VPR128:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7366 def : Pat<(v2f64 (fmul (v2f64 (Neon_vdup (f64 FPR64:$Re))),
7367 (v2f64 VPR128:$Rn))),
7368 (FMULve_2d2d VPR128:$Rn, (SUBREG_TO_REG (i64 0), $Re, sub_64), 0)>;
7370 // The followings are patterns using fma
7371 // -ffp-contract=fast generates fma
7373 multiclass NI_2VE_v2<bit u, bits<4> opcode, string asmop> {
7374 // vector register class for element is always 128-bit to cover the max index
7375 def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7376 neon_uimm2_bare, VPR64, VPR64, VPR128> {
7377 let Inst{11} = {Index{1}};
7378 let Inst{21} = {Index{0}};
7379 let Inst{20-16} = Re;
7382 def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7383 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7384 let Inst{11} = {Index{1}};
7385 let Inst{21} = {Index{0}};
7386 let Inst{20-16} = Re;
7389 // _1d2d doesn't exist!
7391 def _2d2d : NI_2VE<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7392 neon_uimm1_bare, VPR128, VPR128, VPR128> {
7393 let Inst{11} = {Index{0}};
7395 let Inst{20-16} = Re;
7399 defm FMLAvve : NI_2VE_v2<0b0, 0b0001, "fmla">;
7400 defm FMLSvve : NI_2VE_v2<0b0, 0b0101, "fmls">;
7402 // Pattern for lane in 128-bit vector
7403 class NI_2VEswap_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7404 RegisterOperand ResVPR, RegisterOperand OpVPR,
7405 ValueType ResTy, ValueType OpTy,
7406 SDPatternOperator coreop>
7407 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7408 (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7409 (INST ResVPR:$src, ResVPR:$Rn, OpVPR:$Re, OpImm:$Index)>;
7411 // Pattern for lane 0
7412 class NI_2VEfma_lane0<Instruction INST, SDPatternOperator op,
7413 RegisterOperand ResVPR, ValueType ResTy>
7414 : Pat<(ResTy (op (ResTy ResVPR:$Rn),
7415 (ResTy (Neon_vdup (f32 FPR32:$Re))),
7416 (ResTy ResVPR:$src))),
7417 (INST ResVPR:$src, ResVPR:$Rn,
7418 (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7420 // Pattern for lane in 64-bit vector
7421 class NI_2VEswap_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7422 RegisterOperand ResVPR, RegisterOperand OpVPR,
7423 ValueType ResTy, ValueType OpTy,
7424 SDPatternOperator coreop>
7425 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7426 (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7427 (INST ResVPR:$src, ResVPR:$Rn,
7428 (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), OpImm:$Index)>;
7430 // Pattern for lane in 64-bit vector
7431 class NI_2VEswap_lane_2d2d<Instruction INST, Operand OpImm,
7432 SDPatternOperator op,
7433 RegisterOperand ResVPR, RegisterOperand OpVPR,
7434 ValueType ResTy, ValueType OpTy,
7435 SDPatternOperator coreop>
7436 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (OpTy OpVPR:$Re))),
7437 (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7438 (INST ResVPR:$src, ResVPR:$Rn,
7439 (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), 0)>;
7442 multiclass NI_2VE_fma_v2_pat<string subop, SDPatternOperator op> {
7443 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7444 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7445 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7447 def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_2s4s"),
7450 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7451 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7452 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7454 def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_4s4s"),
7457 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7458 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7459 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7461 // Index can only be half of the max value for lane in 64-bit vector
7463 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7464 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7465 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7467 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7468 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7469 BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7472 defm FMLA_lane_v2_s : NI_2VE_fma_v2_pat<"FMLAvve", fma>;
7474 // Pattern for lane 0
7475 class NI_2VEfms_lane0<Instruction INST, SDPatternOperator op,
7476 RegisterOperand ResVPR, ValueType ResTy>
7477 : Pat<(ResTy (op (ResTy (fneg ResVPR:$Rn)),
7478 (ResTy (Neon_vdup (f32 FPR32:$Re))),
7479 (ResTy ResVPR:$src))),
7480 (INST ResVPR:$src, ResVPR:$Rn,
7481 (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7483 multiclass NI_2VE_fms_v2_pat<string subop, SDPatternOperator op>
7485 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7486 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7487 BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7489 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7490 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7491 BinOpFrag<(Neon_vduplane
7492 (fneg node:$LHS), node:$RHS)>>;
7494 def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_2s4s"),
7497 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7498 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7499 BinOpFrag<(fneg (Neon_vduplane
7500 node:$LHS, node:$RHS))>>;
7502 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7503 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7504 BinOpFrag<(Neon_vduplane
7505 (fneg node:$LHS), node:$RHS)>>;
7507 def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_4s4s"),
7510 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7511 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7512 BinOpFrag<(fneg (Neon_vduplane
7513 node:$LHS, node:$RHS))>>;
7515 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7516 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7517 BinOpFrag<(Neon_vduplane
7518 (fneg node:$LHS), node:$RHS)>>;
7520 // Index can only be half of the max value for lane in 64-bit vector
7522 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7523 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7524 BinOpFrag<(fneg (Neon_vduplane
7525 node:$LHS, node:$RHS))>>;
7527 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7528 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7529 BinOpFrag<(Neon_vduplane
7530 (fneg node:$LHS), node:$RHS)>>;
7532 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7533 neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7534 BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7536 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7537 neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7538 BinOpFrag<(Neon_vduplane (fneg node:$LHS), node:$RHS)>>;
7540 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7541 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7542 BinOpFrag<(fneg (Neon_combine_2d
7543 node:$LHS, node:$RHS))>>;
7545 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7546 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7547 BinOpFrag<(Neon_combine_2d
7548 (fneg node:$LHS), (fneg node:$RHS))>>;
7551 defm FMLS_lane_v2_s : NI_2VE_fms_v2_pat<"FMLSvve", fma>;
7553 // Variant 3: Long type
7554 // E.g. SMLAL : 4S/4H/H (v0-v15), 2D/2S/S
7555 // SMLAL2: 4S/8H/H (v0-v15), 2D/4S/S
7557 multiclass NI_2VE_v3<bit u, bits<4> opcode, string asmop> {
7558 // vector register class for element is always 128-bit to cover the max index
7559 def _2d2s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7560 neon_uimm2_bare, VPR128, VPR64, VPR128> {
7561 let Inst{11} = {Index{1}};
7562 let Inst{21} = {Index{0}};
7563 let Inst{20-16} = Re;
7566 def _2d4s : NI_2VE<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7567 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7568 let Inst{11} = {Index{1}};
7569 let Inst{21} = {Index{0}};
7570 let Inst{20-16} = Re;
7573 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7574 def _4s8h : NI_2VE<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7575 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7576 let Inst{11} = {Index{2}};
7577 let Inst{21} = {Index{1}};
7578 let Inst{20} = {Index{0}};
7579 let Inst{19-16} = Re{3-0};
7582 def _4s4h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7583 neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7584 let Inst{11} = {Index{2}};
7585 let Inst{21} = {Index{1}};
7586 let Inst{20} = {Index{0}};
7587 let Inst{19-16} = Re{3-0};
7591 defm SMLALvve : NI_2VE_v3<0b0, 0b0010, "smlal">;
7592 defm UMLALvve : NI_2VE_v3<0b1, 0b0010, "umlal">;
7593 defm SMLSLvve : NI_2VE_v3<0b0, 0b0110, "smlsl">;
7594 defm UMLSLvve : NI_2VE_v3<0b1, 0b0110, "umlsl">;
7595 defm SQDMLALvve : NI_2VE_v3<0b0, 0b0011, "sqdmlal">;
7596 defm SQDMLSLvve : NI_2VE_v3<0b0, 0b0111, "sqdmlsl">;
7598 multiclass NI_2VE_v3_2op<bit u, bits<4> opcode, string asmop> {
7599 // vector register class for element is always 128-bit to cover the max index
7600 def _2d2s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7601 neon_uimm2_bare, VPR128, VPR64, VPR128> {
7602 let Inst{11} = {Index{1}};
7603 let Inst{21} = {Index{0}};
7604 let Inst{20-16} = Re;
7607 def _2d4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7608 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7609 let Inst{11} = {Index{1}};
7610 let Inst{21} = {Index{0}};
7611 let Inst{20-16} = Re;
7614 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7615 def _4s8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7616 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7617 let Inst{11} = {Index{2}};
7618 let Inst{21} = {Index{1}};
7619 let Inst{20} = {Index{0}};
7620 let Inst{19-16} = Re{3-0};
7623 def _4s4h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7624 neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7625 let Inst{11} = {Index{2}};
7626 let Inst{21} = {Index{1}};
7627 let Inst{20} = {Index{0}};
7628 let Inst{19-16} = Re{3-0};
7632 defm SMULLve : NI_2VE_v3_2op<0b0, 0b1010, "smull">;
7633 defm UMULLve : NI_2VE_v3_2op<0b1, 0b1010, "umull">;
7634 defm SQDMULLve : NI_2VE_v3_2op<0b0, 0b1011, "sqdmull">;
7636 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
7639 // Pattern for lane in 128-bit vector
7640 class NI_2VEL2_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7641 RegisterOperand EleOpVPR, ValueType ResTy,
7642 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7643 SDPatternOperator hiop>
7644 : Pat<(ResTy (op (ResTy VPR128:$src),
7645 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7646 (HalfOpTy (Neon_vduplane
7647 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7648 (INST VPR128:$src, VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7650 // Pattern for lane in 64-bit vector
7651 class NI_2VEL2_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7652 RegisterOperand EleOpVPR, ValueType ResTy,
7653 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7654 SDPatternOperator hiop>
7655 : Pat<(ResTy (op (ResTy VPR128:$src),
7656 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7657 (HalfOpTy (Neon_vduplane
7658 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7659 (INST VPR128:$src, VPR128:$Rn,
7660 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7662 class NI_2VEL2_lane0<Instruction INST, SDPatternOperator op,
7663 ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7664 SDPatternOperator hiop, Instruction DupInst>
7665 : Pat<(ResTy (op (ResTy VPR128:$src),
7666 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7667 (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7668 (INST VPR128:$src, VPR128:$Rn, (DupInst $Re), 0)>;
7670 multiclass NI_2VEL_v3_pat<string subop, SDPatternOperator op> {
7671 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7672 op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7674 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7675 op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32>;
7677 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7678 op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7680 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7681 op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7683 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7684 op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7686 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7687 op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7689 // Index can only be half of the max value for lane in 64-bit vector
7691 def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7692 op, VPR128, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7694 def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7695 op, VPR128, VPR64, VPR64, v2i64, v2i32, v2i32>;
7697 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7698 op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7700 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7701 op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7704 defm SMLAL_lane_v3 : NI_2VEL_v3_pat<"SMLALvve", Neon_smlal>;
7705 defm UMLAL_lane_v3 : NI_2VEL_v3_pat<"UMLALvve", Neon_umlal>;
7706 defm SMLSL_lane_v3 : NI_2VEL_v3_pat<"SMLSLvve", Neon_smlsl>;
7707 defm UMLSL_lane_v3 : NI_2VEL_v3_pat<"UMLSLvve", Neon_umlsl>;
7709 // Pattern for lane in 128-bit vector
7710 class NI_2VEL2_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7711 RegisterOperand EleOpVPR, ValueType ResTy,
7712 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7713 SDPatternOperator hiop>
7715 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7716 (HalfOpTy (Neon_vduplane
7717 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7718 (INST VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7720 // Pattern for lane in 64-bit vector
7721 class NI_2VEL2_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7722 RegisterOperand EleOpVPR, ValueType ResTy,
7723 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7724 SDPatternOperator hiop>
7726 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7727 (HalfOpTy (Neon_vduplane
7728 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7730 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7732 // Pattern for fixed lane 0
7733 class NI_2VEL2_mul_lane0<Instruction INST, SDPatternOperator op,
7734 ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7735 SDPatternOperator hiop, Instruction DupInst>
7737 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7738 (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7739 (INST VPR128:$Rn, (DupInst $Re), 0)>;
7741 multiclass NI_2VEL_mul_v3_pat<string subop, SDPatternOperator op> {
7742 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7743 op, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7745 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7746 op, VPR64, VPR128, v2i64, v2i32, v4i32>;
7748 def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7749 op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7751 def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7752 op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7754 def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_4s8h"),
7755 op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7757 def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_2d4s"),
7758 op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7760 // Index can only be half of the max value for lane in 64-bit vector
7762 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7763 op, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7765 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7766 op, VPR64, VPR64, v2i64, v2i32, v2i32>;
7768 def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7769 op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7771 def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7772 op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7775 defm SMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SMULLve", int_arm_neon_vmulls>;
7776 defm UMULL_lane_v3 : NI_2VEL_mul_v3_pat<"UMULLve", int_arm_neon_vmullu>;
7777 defm SQDMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SQDMULLve", int_arm_neon_vqdmull>;
7779 multiclass NI_qdma<SDPatternOperator op> {
7780 def _4s : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7782 (v4i32 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7784 def _2d : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7786 (v2i64 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7789 defm Neon_qdmlal : NI_qdma<int_arm_neon_vqadds>;
7790 defm Neon_qdmlsl : NI_qdma<int_arm_neon_vqsubs>;
7792 multiclass NI_2VEL_v3_qdma_pat<string subop, string op> {
7793 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7794 !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR128Lo,
7795 v4i32, v4i16, v8i16>;
7797 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7798 !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR128,
7799 v2i64, v2i32, v4i32>;
7801 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7802 !cast<PatFrag>(op # "_4s"), VPR128Lo,
7803 v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7805 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7806 !cast<PatFrag>(op # "_2d"), VPR128,
7807 v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7809 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7810 !cast<PatFrag>(op # "_4s"),
7811 v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7813 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7814 !cast<PatFrag>(op # "_2d"),
7815 v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7817 // Index can only be half of the max value for lane in 64-bit vector
7819 def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7820 !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR64Lo,
7821 v4i32, v4i16, v4i16>;
7823 def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7824 !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR64,
7825 v2i64, v2i32, v2i32>;
7827 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7828 !cast<PatFrag>(op # "_4s"), VPR64Lo,
7829 v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7831 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7832 !cast<PatFrag>(op # "_2d"), VPR64,
7833 v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7836 defm SQDMLAL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLALvve", "Neon_qdmlal">;
7837 defm SQDMLSL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLSLvve", "Neon_qdmlsl">;
7839 // End of implementation for instruction class (3V Elem)
7841 class NeonI_REV<string asmop, string Res, bits<2> size, bit Q, bit U,
7842 bits<5> opcode, RegisterOperand ResVPR, ValueType ResTy,
7843 SDPatternOperator Neon_Rev>
7844 : NeonI_2VMisc<Q, U, size, opcode,
7845 (outs ResVPR:$Rd), (ins ResVPR:$Rn),
7846 asmop # "\t$Rd." # Res # ", $Rn." # Res,
7847 [(set (ResTy ResVPR:$Rd),
7848 (ResTy (Neon_Rev (ResTy ResVPR:$Rn))))],
7851 def REV64_16b : NeonI_REV<"rev64", "16b", 0b00, 0b1, 0b0, 0b00000, VPR128,
7853 def REV64_8h : NeonI_REV<"rev64", "8h", 0b01, 0b1, 0b0, 0b00000, VPR128,
7855 def REV64_4s : NeonI_REV<"rev64", "4s", 0b10, 0b1, 0b0, 0b00000, VPR128,
7857 def REV64_8b : NeonI_REV<"rev64", "8b", 0b00, 0b0, 0b0, 0b00000, VPR64,
7859 def REV64_4h : NeonI_REV<"rev64", "4h", 0b01, 0b0, 0b0, 0b00000, VPR64,
7861 def REV64_2s : NeonI_REV<"rev64", "2s", 0b10, 0b0, 0b0, 0b00000, VPR64,
7864 def : Pat<(v4f32 (Neon_rev64 (v4f32 VPR128:$Rn))), (REV64_4s VPR128:$Rn)>;
7865 def : Pat<(v2f32 (Neon_rev64 (v2f32 VPR64:$Rn))), (REV64_2s VPR64:$Rn)>;
7867 def REV32_16b : NeonI_REV<"rev32", "16b", 0b00, 0b1, 0b1, 0b00000, VPR128,
7869 def REV32_8h : NeonI_REV<"rev32", "8h", 0b01, 0b1, 0b1, 0b00000, VPR128,
7871 def REV32_8b : NeonI_REV<"rev32", "8b", 0b00, 0b0, 0b1, 0b00000, VPR64,
7873 def REV32_4h : NeonI_REV<"rev32", "4h", 0b01, 0b0, 0b1, 0b00000, VPR64,
7876 def REV16_16b : NeonI_REV<"rev16", "16b", 0b00, 0b1, 0b0, 0b00001, VPR128,
7878 def REV16_8b : NeonI_REV<"rev16", "8b", 0b00, 0b0, 0b0, 0b00001, VPR64,
7881 multiclass NeonI_PairwiseAdd<string asmop, bit U, bits<5> opcode,
7882 SDPatternOperator Neon_Padd> {
7883 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7884 (outs VPR128:$Rd), (ins VPR128:$Rn),
7885 asmop # "\t$Rd.8h, $Rn.16b",
7886 [(set (v8i16 VPR128:$Rd),
7887 (v8i16 (Neon_Padd (v16i8 VPR128:$Rn))))],
7890 def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7891 (outs VPR64:$Rd), (ins VPR64:$Rn),
7892 asmop # "\t$Rd.4h, $Rn.8b",
7893 [(set (v4i16 VPR64:$Rd),
7894 (v4i16 (Neon_Padd (v8i8 VPR64:$Rn))))],
7897 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7898 (outs VPR128:$Rd), (ins VPR128:$Rn),
7899 asmop # "\t$Rd.4s, $Rn.8h",
7900 [(set (v4i32 VPR128:$Rd),
7901 (v4i32 (Neon_Padd (v8i16 VPR128:$Rn))))],
7904 def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7905 (outs VPR64:$Rd), (ins VPR64:$Rn),
7906 asmop # "\t$Rd.2s, $Rn.4h",
7907 [(set (v2i32 VPR64:$Rd),
7908 (v2i32 (Neon_Padd (v4i16 VPR64:$Rn))))],
7911 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7912 (outs VPR128:$Rd), (ins VPR128:$Rn),
7913 asmop # "\t$Rd.2d, $Rn.4s",
7914 [(set (v2i64 VPR128:$Rd),
7915 (v2i64 (Neon_Padd (v4i32 VPR128:$Rn))))],
7918 def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7919 (outs VPR64:$Rd), (ins VPR64:$Rn),
7920 asmop # "\t$Rd.1d, $Rn.2s",
7921 [(set (v1i64 VPR64:$Rd),
7922 (v1i64 (Neon_Padd (v2i32 VPR64:$Rn))))],
7926 defm SADDLP : NeonI_PairwiseAdd<"saddlp", 0b0, 0b00010,
7927 int_arm_neon_vpaddls>;
7928 defm UADDLP : NeonI_PairwiseAdd<"uaddlp", 0b1, 0b00010,
7929 int_arm_neon_vpaddlu>;
7931 def : Pat<(v1i64 (int_aarch64_neon_saddlv (v2i32 VPR64:$Rn))),
7933 def : Pat<(v1i64 (int_aarch64_neon_uaddlv (v2i32 VPR64:$Rn))),
7936 multiclass NeonI_PairwiseAddAcc<string asmop, bit U, bits<5> opcode,
7937 SDPatternOperator Neon_Padd> {
7938 let Constraints = "$src = $Rd" in {
7939 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7940 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7941 asmop # "\t$Rd.8h, $Rn.16b",
7942 [(set (v8i16 VPR128:$Rd),
7944 (v8i16 VPR128:$src), (v16i8 VPR128:$Rn))))],
7947 def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7948 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7949 asmop # "\t$Rd.4h, $Rn.8b",
7950 [(set (v4i16 VPR64:$Rd),
7952 (v4i16 VPR64:$src), (v8i8 VPR64:$Rn))))],
7955 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7956 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7957 asmop # "\t$Rd.4s, $Rn.8h",
7958 [(set (v4i32 VPR128:$Rd),
7960 (v4i32 VPR128:$src), (v8i16 VPR128:$Rn))))],
7963 def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7964 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7965 asmop # "\t$Rd.2s, $Rn.4h",
7966 [(set (v2i32 VPR64:$Rd),
7968 (v2i32 VPR64:$src), (v4i16 VPR64:$Rn))))],
7971 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7972 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7973 asmop # "\t$Rd.2d, $Rn.4s",
7974 [(set (v2i64 VPR128:$Rd),
7976 (v2i64 VPR128:$src), (v4i32 VPR128:$Rn))))],
7979 def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7980 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7981 asmop # "\t$Rd.1d, $Rn.2s",
7982 [(set (v1i64 VPR64:$Rd),
7984 (v1i64 VPR64:$src), (v2i32 VPR64:$Rn))))],
7989 defm SADALP : NeonI_PairwiseAddAcc<"sadalp", 0b0, 0b00110,
7990 int_arm_neon_vpadals>;
7991 defm UADALP : NeonI_PairwiseAddAcc<"uadalp", 0b1, 0b00110,
7992 int_arm_neon_vpadalu>;
7994 multiclass NeonI_2VMisc_BHSDsize_1Arg<string asmop, bit U, bits<5> opcode> {
7995 def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7996 (outs VPR128:$Rd), (ins VPR128:$Rn),
7997 asmop # "\t$Rd.16b, $Rn.16b",
8000 def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
8001 (outs VPR128:$Rd), (ins VPR128:$Rn),
8002 asmop # "\t$Rd.8h, $Rn.8h",
8005 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8006 (outs VPR128:$Rd), (ins VPR128:$Rn),
8007 asmop # "\t$Rd.4s, $Rn.4s",
8010 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
8011 (outs VPR128:$Rd), (ins VPR128:$Rn),
8012 asmop # "\t$Rd.2d, $Rn.2d",
8015 def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
8016 (outs VPR64:$Rd), (ins VPR64:$Rn),
8017 asmop # "\t$Rd.8b, $Rn.8b",
8020 def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
8021 (outs VPR64:$Rd), (ins VPR64:$Rn),
8022 asmop # "\t$Rd.4h, $Rn.4h",
8025 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8026 (outs VPR64:$Rd), (ins VPR64:$Rn),
8027 asmop # "\t$Rd.2s, $Rn.2s",
8031 defm SQABS : NeonI_2VMisc_BHSDsize_1Arg<"sqabs", 0b0, 0b00111>;
8032 defm SQNEG : NeonI_2VMisc_BHSDsize_1Arg<"sqneg", 0b1, 0b00111>;
8033 defm ABS : NeonI_2VMisc_BHSDsize_1Arg<"abs", 0b0, 0b01011>;
8034 defm NEG : NeonI_2VMisc_BHSDsize_1Arg<"neg", 0b1, 0b01011>;
8036 multiclass NeonI_2VMisc_BHSD_1Arg_Pattern<string Prefix,
8037 SDPatternOperator Neon_Op> {
8038 def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$Rn))),
8039 (v16i8 (!cast<Instruction>(Prefix # 16b) (v16i8 VPR128:$Rn)))>;
8041 def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$Rn))),
8042 (v8i16 (!cast<Instruction>(Prefix # 8h) (v8i16 VPR128:$Rn)))>;
8044 def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$Rn))),
8045 (v4i32 (!cast<Instruction>(Prefix # 4s) (v4i32 VPR128:$Rn)))>;
8047 def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$Rn))),
8048 (v2i64 (!cast<Instruction>(Prefix # 2d) (v2i64 VPR128:$Rn)))>;
8050 def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$Rn))),
8051 (v8i8 (!cast<Instruction>(Prefix # 8b) (v8i8 VPR64:$Rn)))>;
8053 def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$Rn))),
8054 (v4i16 (!cast<Instruction>(Prefix # 4h) (v4i16 VPR64:$Rn)))>;
8056 def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$Rn))),
8057 (v2i32 (!cast<Instruction>(Prefix # 2s) (v2i32 VPR64:$Rn)))>;
8060 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQABS", int_arm_neon_vqabs>;
8061 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQNEG", int_arm_neon_vqneg>;
8062 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"ABS", int_arm_neon_vabs>;
8064 def : Pat<(v16i8 (sub
8065 (v16i8 Neon_AllZero),
8066 (v16i8 VPR128:$Rn))),
8067 (v16i8 (NEG16b (v16i8 VPR128:$Rn)))>;
8068 def : Pat<(v8i8 (sub
8069 (v8i8 Neon_AllZero),
8071 (v8i8 (NEG8b (v8i8 VPR64:$Rn)))>;
8072 def : Pat<(v8i16 (sub
8073 (v8i16 (bitconvert (v16i8 Neon_AllZero))),
8074 (v8i16 VPR128:$Rn))),
8075 (v8i16 (NEG8h (v8i16 VPR128:$Rn)))>;
8076 def : Pat<(v4i16 (sub
8077 (v4i16 (bitconvert (v8i8 Neon_AllZero))),
8078 (v4i16 VPR64:$Rn))),
8079 (v4i16 (NEG4h (v4i16 VPR64:$Rn)))>;
8080 def : Pat<(v4i32 (sub
8081 (v4i32 (bitconvert (v16i8 Neon_AllZero))),
8082 (v4i32 VPR128:$Rn))),
8083 (v4i32 (NEG4s (v4i32 VPR128:$Rn)))>;
8084 def : Pat<(v2i32 (sub
8085 (v2i32 (bitconvert (v8i8 Neon_AllZero))),
8086 (v2i32 VPR64:$Rn))),
8087 (v2i32 (NEG2s (v2i32 VPR64:$Rn)))>;
8088 def : Pat<(v2i64 (sub
8089 (v2i64 (bitconvert (v16i8 Neon_AllZero))),
8090 (v2i64 VPR128:$Rn))),
8091 (v2i64 (NEG2d (v2i64 VPR128:$Rn)))>;
8093 multiclass NeonI_2VMisc_BHSDsize_2Args<string asmop, bit U, bits<5> opcode> {
8094 let Constraints = "$src = $Rd" in {
8095 def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
8096 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8097 asmop # "\t$Rd.16b, $Rn.16b",
8100 def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
8101 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8102 asmop # "\t$Rd.8h, $Rn.8h",
8105 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8106 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8107 asmop # "\t$Rd.4s, $Rn.4s",
8110 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
8111 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8112 asmop # "\t$Rd.2d, $Rn.2d",
8115 def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
8116 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
8117 asmop # "\t$Rd.8b, $Rn.8b",
8120 def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
8121 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
8122 asmop # "\t$Rd.4h, $Rn.4h",
8125 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8126 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
8127 asmop # "\t$Rd.2s, $Rn.2s",
8132 defm SUQADD : NeonI_2VMisc_BHSDsize_2Args<"suqadd", 0b0, 0b00011>;
8133 defm USQADD : NeonI_2VMisc_BHSDsize_2Args<"usqadd", 0b1, 0b00011>;
8135 multiclass NeonI_2VMisc_BHSD_2Args_Pattern<string Prefix,
8136 SDPatternOperator Neon_Op> {
8137 def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$src), (v16i8 VPR128:$Rn))),
8138 (v16i8 (!cast<Instruction>(Prefix # 16b)
8139 (v16i8 VPR128:$src), (v16i8 VPR128:$Rn)))>;
8141 def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$src), (v8i16 VPR128:$Rn))),
8142 (v8i16 (!cast<Instruction>(Prefix # 8h)
8143 (v8i16 VPR128:$src), (v8i16 VPR128:$Rn)))>;
8145 def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$src), (v4i32 VPR128:$Rn))),
8146 (v4i32 (!cast<Instruction>(Prefix # 4s)
8147 (v4i32 VPR128:$src), (v4i32 VPR128:$Rn)))>;
8149 def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$src), (v2i64 VPR128:$Rn))),
8150 (v2i64 (!cast<Instruction>(Prefix # 2d)
8151 (v2i64 VPR128:$src), (v2i64 VPR128:$Rn)))>;
8153 def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$src), (v8i8 VPR64:$Rn))),
8154 (v8i8 (!cast<Instruction>(Prefix # 8b)
8155 (v8i8 VPR64:$src), (v8i8 VPR64:$Rn)))>;
8157 def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$src), (v4i16 VPR64:$Rn))),
8158 (v4i16 (!cast<Instruction>(Prefix # 4h)
8159 (v4i16 VPR64:$src), (v4i16 VPR64:$Rn)))>;
8161 def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$src), (v2i32 VPR64:$Rn))),
8162 (v2i32 (!cast<Instruction>(Prefix # 2s)
8163 (v2i32 VPR64:$src), (v2i32 VPR64:$Rn)))>;
8166 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"SUQADD", int_aarch64_neon_suqadd>;
8167 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"USQADD", int_aarch64_neon_usqadd>;
8169 multiclass NeonI_2VMisc_BHSsizes<string asmop, bit U,
8170 SDPatternOperator Neon_Op> {
8171 def 16b : NeonI_2VMisc<0b1, U, 0b00, 0b00100,
8172 (outs VPR128:$Rd), (ins VPR128:$Rn),
8173 asmop # "\t$Rd.16b, $Rn.16b",
8174 [(set (v16i8 VPR128:$Rd),
8175 (v16i8 (Neon_Op (v16i8 VPR128:$Rn))))],
8178 def 8h : NeonI_2VMisc<0b1, U, 0b01, 0b00100,
8179 (outs VPR128:$Rd), (ins VPR128:$Rn),
8180 asmop # "\t$Rd.8h, $Rn.8h",
8181 [(set (v8i16 VPR128:$Rd),
8182 (v8i16 (Neon_Op (v8i16 VPR128:$Rn))))],
8185 def 4s : NeonI_2VMisc<0b1, U, 0b10, 0b00100,
8186 (outs VPR128:$Rd), (ins VPR128:$Rn),
8187 asmop # "\t$Rd.4s, $Rn.4s",
8188 [(set (v4i32 VPR128:$Rd),
8189 (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
8192 def 8b : NeonI_2VMisc<0b0, U, 0b00, 0b00100,
8193 (outs VPR64:$Rd), (ins VPR64:$Rn),
8194 asmop # "\t$Rd.8b, $Rn.8b",
8195 [(set (v8i8 VPR64:$Rd),
8196 (v8i8 (Neon_Op (v8i8 VPR64:$Rn))))],
8199 def 4h : NeonI_2VMisc<0b0, U, 0b01, 0b00100,
8200 (outs VPR64:$Rd), (ins VPR64:$Rn),
8201 asmop # "\t$Rd.4h, $Rn.4h",
8202 [(set (v4i16 VPR64:$Rd),
8203 (v4i16 (Neon_Op (v4i16 VPR64:$Rn))))],
8206 def 2s : NeonI_2VMisc<0b0, U, 0b10, 0b00100,
8207 (outs VPR64:$Rd), (ins VPR64:$Rn),
8208 asmop # "\t$Rd.2s, $Rn.2s",
8209 [(set (v2i32 VPR64:$Rd),
8210 (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8214 defm CLS : NeonI_2VMisc_BHSsizes<"cls", 0b0, int_arm_neon_vcls>;
8215 defm CLZ : NeonI_2VMisc_BHSsizes<"clz", 0b1, ctlz>;
8217 multiclass NeonI_2VMisc_Bsize<string asmop, bit U, bits<2> size,
8219 def 16b : NeonI_2VMisc<0b1, U, size, Opcode,
8220 (outs VPR128:$Rd), (ins VPR128:$Rn),
8221 asmop # "\t$Rd.16b, $Rn.16b",
8224 def 8b : NeonI_2VMisc<0b0, U, size, Opcode,
8225 (outs VPR64:$Rd), (ins VPR64:$Rn),
8226 asmop # "\t$Rd.8b, $Rn.8b",
8230 defm CNT : NeonI_2VMisc_Bsize<"cnt", 0b0, 0b00, 0b00101>;
8231 defm NOT : NeonI_2VMisc_Bsize<"not", 0b1, 0b00, 0b00101>;
8232 defm RBIT : NeonI_2VMisc_Bsize<"rbit", 0b1, 0b01, 0b00101>;
8234 def : NeonInstAlias<"mvn $Rd.16b, $Rn.16b",
8235 (NOT16b VPR128:$Rd, VPR128:$Rn), 0>;
8236 def : NeonInstAlias<"mvn $Rd.8b, $Rn.8b",
8237 (NOT8b VPR64:$Rd, VPR64:$Rn), 0>;
8239 def : Pat<(v16i8 (ctpop (v16i8 VPR128:$Rn))),
8240 (v16i8 (CNT16b (v16i8 VPR128:$Rn)))>;
8241 def : Pat<(v8i8 (ctpop (v8i8 VPR64:$Rn))),
8242 (v8i8 (CNT8b (v8i8 VPR64:$Rn)))>;
8244 def : Pat<(v16i8 (xor
8246 (v16i8 Neon_AllOne))),
8247 (v16i8 (NOT16b (v16i8 VPR128:$Rn)))>;
8248 def : Pat<(v8i8 (xor
8250 (v8i8 Neon_AllOne))),
8251 (v8i8 (NOT8b (v8i8 VPR64:$Rn)))>;
8252 def : Pat<(v8i16 (xor
8254 (v8i16 (bitconvert (v16i8 Neon_AllOne))))),
8255 (NOT16b VPR128:$Rn)>;
8256 def : Pat<(v4i16 (xor
8258 (v4i16 (bitconvert (v8i8 Neon_AllOne))))),
8260 def : Pat<(v4i32 (xor
8262 (v4i32 (bitconvert (v16i8 Neon_AllOne))))),
8263 (NOT16b VPR128:$Rn)>;
8264 def : Pat<(v2i32 (xor
8266 (v2i32 (bitconvert (v8i8 Neon_AllOne))))),
8268 def : Pat<(v2i64 (xor
8270 (v2i64 (bitconvert (v16i8 Neon_AllOne))))),
8271 (NOT16b VPR128:$Rn)>;
8273 def : Pat<(v16i8 (int_aarch64_neon_rbit (v16i8 VPR128:$Rn))),
8274 (v16i8 (RBIT16b (v16i8 VPR128:$Rn)))>;
8275 def : Pat<(v8i8 (int_aarch64_neon_rbit (v8i8 VPR64:$Rn))),
8276 (v8i8 (RBIT8b (v8i8 VPR64:$Rn)))>;
8278 multiclass NeonI_2VMisc_SDsizes<string asmop, bit U, bits<5> opcode,
8279 SDPatternOperator Neon_Op> {
8280 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8281 (outs VPR128:$Rd), (ins VPR128:$Rn),
8282 asmop # "\t$Rd.4s, $Rn.4s",
8283 [(set (v4f32 VPR128:$Rd),
8284 (v4f32 (Neon_Op (v4f32 VPR128:$Rn))))],
8287 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
8288 (outs VPR128:$Rd), (ins VPR128:$Rn),
8289 asmop # "\t$Rd.2d, $Rn.2d",
8290 [(set (v2f64 VPR128:$Rd),
8291 (v2f64 (Neon_Op (v2f64 VPR128:$Rn))))],
8294 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8295 (outs VPR64:$Rd), (ins VPR64:$Rn),
8296 asmop # "\t$Rd.2s, $Rn.2s",
8297 [(set (v2f32 VPR64:$Rd),
8298 (v2f32 (Neon_Op (v2f32 VPR64:$Rn))))],
8302 defm FABS : NeonI_2VMisc_SDsizes<"fabs", 0b0, 0b01111, fabs>;
8303 defm FNEG : NeonI_2VMisc_SDsizes<"fneg", 0b1, 0b01111, fneg>;
8305 multiclass NeonI_2VMisc_HSD_Narrow<string asmop, bit U, bits<5> opcode> {
8306 def 8h8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
8307 (outs VPR64:$Rd), (ins VPR128:$Rn),
8308 asmop # "\t$Rd.8b, $Rn.8h",
8311 def 4s4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
8312 (outs VPR64:$Rd), (ins VPR128:$Rn),
8313 asmop # "\t$Rd.4h, $Rn.4s",
8316 def 2d2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8317 (outs VPR64:$Rd), (ins VPR128:$Rn),
8318 asmop # "\t$Rd.2s, $Rn.2d",
8321 let Constraints = "$Rd = $src" in {
8322 def 8h16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
8323 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8324 asmop # "2\t$Rd.16b, $Rn.8h",
8327 def 4s8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
8328 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8329 asmop # "2\t$Rd.8h, $Rn.4s",
8332 def 2d4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8333 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8334 asmop # "2\t$Rd.4s, $Rn.2d",
8339 defm XTN : NeonI_2VMisc_HSD_Narrow<"xtn", 0b0, 0b10010>;
8340 defm SQXTUN : NeonI_2VMisc_HSD_Narrow<"sqxtun", 0b1, 0b10010>;
8341 defm SQXTN : NeonI_2VMisc_HSD_Narrow<"sqxtn", 0b0, 0b10100>;
8342 defm UQXTN : NeonI_2VMisc_HSD_Narrow<"uqxtn", 0b1, 0b10100>;
8344 multiclass NeonI_2VMisc_Narrow_Patterns<string Prefix,
8345 SDPatternOperator Neon_Op> {
8346 def : Pat<(v8i8 (Neon_Op (v8i16 VPR128:$Rn))),
8347 (v8i8 (!cast<Instruction>(Prefix # 8h8b) (v8i16 VPR128:$Rn)))>;
8349 def : Pat<(v4i16 (Neon_Op (v4i32 VPR128:$Rn))),
8350 (v4i16 (!cast<Instruction>(Prefix # 4s4h) (v4i32 VPR128:$Rn)))>;
8352 def : Pat<(v2i32 (Neon_Op (v2i64 VPR128:$Rn))),
8353 (v2i32 (!cast<Instruction>(Prefix # 2d2s) (v2i64 VPR128:$Rn)))>;
8355 def : Pat<(v16i8 (concat_vectors
8357 (v8i8 (Neon_Op (v8i16 VPR128:$Rn))))),
8358 (!cast<Instruction>(Prefix # 8h16b)
8359 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8362 def : Pat<(v8i16 (concat_vectors
8364 (v4i16 (Neon_Op (v4i32 VPR128:$Rn))))),
8365 (!cast<Instruction>(Prefix # 4s8h)
8366 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8369 def : Pat<(v4i32 (concat_vectors
8371 (v2i32 (Neon_Op (v2i64 VPR128:$Rn))))),
8372 (!cast<Instruction>(Prefix # 2d4s)
8373 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8377 defm : NeonI_2VMisc_Narrow_Patterns<"XTN", trunc>;
8378 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTUN", int_arm_neon_vqmovnsu>;
8379 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTN", int_arm_neon_vqmovns>;
8380 defm : NeonI_2VMisc_Narrow_Patterns<"UQXTN", int_arm_neon_vqmovnu>;
8382 multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> {
8383 let DecoderMethod = "DecodeSHLLInstruction" in {
8384 def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8386 (ins VPR64:$Rn, uimm_exact8:$Imm),
8387 asmop # "\t$Rd.8h, $Rn.8b, $Imm",
8390 def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8392 (ins VPR64:$Rn, uimm_exact16:$Imm),
8393 asmop # "\t$Rd.4s, $Rn.4h, $Imm",
8396 def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
8398 (ins VPR64:$Rn, uimm_exact32:$Imm),
8399 asmop # "\t$Rd.2d, $Rn.2s, $Imm",
8402 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8404 (ins VPR128:$Rn, uimm_exact8:$Imm),
8405 asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
8408 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8410 (ins VPR128:$Rn, uimm_exact16:$Imm),
8411 asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
8414 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
8416 (ins VPR128:$Rn, uimm_exact32:$Imm),
8417 asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
8422 defm SHLL : NeonI_2VMisc_SHIFT<"shll", 0b1, 0b10011>;
8424 class NeonI_SHLL_Patterns<ValueType OpTy, ValueType DesTy,
8425 SDPatternOperator ExtOp, Operand Neon_Imm,
8428 (DesTy (ExtOp (OpTy VPR64:$Rn))),
8430 (i32 Neon_Imm:$Imm))))),
8431 (!cast<Instruction>("SHLL" # suffix) VPR64:$Rn, Neon_Imm:$Imm)>;
8433 class NeonI_SHLL_High_Patterns<ValueType OpTy, ValueType DesTy,
8434 SDPatternOperator ExtOp, Operand Neon_Imm,
8435 string suffix, PatFrag GetHigh>
8438 (OpTy (GetHigh VPR128:$Rn)))),
8440 (i32 Neon_Imm:$Imm))))),
8441 (!cast<Instruction>("SHLL" # suffix) VPR128:$Rn, Neon_Imm:$Imm)>;
8443 def : NeonI_SHLL_Patterns<v8i8, v8i16, zext, uimm_exact8, "8b8h">;
8444 def : NeonI_SHLL_Patterns<v8i8, v8i16, sext, uimm_exact8, "8b8h">;
8445 def : NeonI_SHLL_Patterns<v4i16, v4i32, zext, uimm_exact16, "4h4s">;
8446 def : NeonI_SHLL_Patterns<v4i16, v4i32, sext, uimm_exact16, "4h4s">;
8447 def : NeonI_SHLL_Patterns<v2i32, v2i64, zext, uimm_exact32, "2s2d">;
8448 def : NeonI_SHLL_Patterns<v2i32, v2i64, sext, uimm_exact32, "2s2d">;
8449 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, zext, uimm_exact8, "16b8h",
8451 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, sext, uimm_exact8, "16b8h",
8453 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, zext, uimm_exact16, "8h4s",
8455 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, sext, uimm_exact16, "8h4s",
8457 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, zext, uimm_exact32, "4s2d",
8459 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, sext, uimm_exact32, "4s2d",
8462 multiclass NeonI_2VMisc_SD_Narrow<string asmop, bit U, bits<5> opcode> {
8463 def 4s4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8464 (outs VPR64:$Rd), (ins VPR128:$Rn),
8465 asmop # "\t$Rd.4h, $Rn.4s",
8468 def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8469 (outs VPR64:$Rd), (ins VPR128:$Rn),
8470 asmop # "\t$Rd.2s, $Rn.2d",
8473 let Constraints = "$src = $Rd" in {
8474 def 4s8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8475 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8476 asmop # "2\t$Rd.8h, $Rn.4s",
8479 def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8480 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8481 asmop # "2\t$Rd.4s, $Rn.2d",
8486 defm FCVTN : NeonI_2VMisc_SD_Narrow<"fcvtn", 0b0, 0b10110>;
8488 multiclass NeonI_2VMisc_Narrow_Pattern<string prefix,
8489 SDPatternOperator f32_to_f16_Op,
8490 SDPatternOperator f64_to_f32_Op> {
8492 def : Pat<(v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))),
8493 (!cast<Instruction>(prefix # "4s4h") (v4f32 VPR128:$Rn))>;
8495 def : Pat<(v8i16 (concat_vectors
8497 (v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))))),
8498 (!cast<Instruction>(prefix # "4s8h")
8499 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8500 (v4f32 VPR128:$Rn))>;
8502 def : Pat<(v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))),
8503 (!cast<Instruction>(prefix # "2d2s") (v2f64 VPR128:$Rn))>;
8505 def : Pat<(v4f32 (concat_vectors
8507 (v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))))),
8508 (!cast<Instruction>(prefix # "2d4s")
8509 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8510 (v2f64 VPR128:$Rn))>;
8513 defm : NeonI_2VMisc_Narrow_Pattern<"FCVTN", int_arm_neon_vcvtfp2hf, fround>;
8515 multiclass NeonI_2VMisc_D_Narrow<string asmop, string prefix, bit U,
8517 def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8518 (outs VPR64:$Rd), (ins VPR128:$Rn),
8519 asmop # "\t$Rd.2s, $Rn.2d",
8522 def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8523 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8524 asmop # "2\t$Rd.4s, $Rn.2d",
8526 let Constraints = "$src = $Rd";
8529 def : Pat<(v2f32 (int_aarch64_neon_vcvtxn (v2f64 VPR128:$Rn))),
8530 (!cast<Instruction>(prefix # "2d2s") VPR128:$Rn)>;
8532 def : Pat<(v4f32 (concat_vectors
8534 (v2f32 (int_aarch64_neon_vcvtxn (v2f64 VPR128:$Rn))))),
8535 (!cast<Instruction>(prefix # "2d4s")
8536 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8540 defm FCVTXN : NeonI_2VMisc_D_Narrow<"fcvtxn","FCVTXN", 0b1, 0b10110>;
8542 def Neon_High4Float : PatFrag<(ops node:$in),
8543 (extract_subvector (v4f32 node:$in), (iPTR 2))>;
8545 multiclass NeonI_2VMisc_HS_Extend<string asmop, bit U, bits<5> opcode> {
8546 def 4h4s : NeonI_2VMisc<0b0, U, 0b00, opcode,
8547 (outs VPR128:$Rd), (ins VPR64:$Rn),
8548 asmop # "\t$Rd.4s, $Rn.4h",
8551 def 2s2d : NeonI_2VMisc<0b0, U, 0b01, opcode,
8552 (outs VPR128:$Rd), (ins VPR64:$Rn),
8553 asmop # "\t$Rd.2d, $Rn.2s",
8556 def 8h4s : NeonI_2VMisc<0b1, U, 0b00, opcode,
8557 (outs VPR128:$Rd), (ins VPR128:$Rn),
8558 asmop # "2\t$Rd.4s, $Rn.8h",
8561 def 4s2d : NeonI_2VMisc<0b1, U, 0b01, opcode,
8562 (outs VPR128:$Rd), (ins VPR128:$Rn),
8563 asmop # "2\t$Rd.2d, $Rn.4s",
8567 defm FCVTL : NeonI_2VMisc_HS_Extend<"fcvtl", 0b0, 0b10111>;
8569 multiclass NeonI_2VMisc_Extend_Pattern<string prefix> {
8570 def : Pat<(v4f32 (int_arm_neon_vcvthf2fp (v4i16 VPR64:$Rn))),
8571 (!cast<Instruction>(prefix # "4h4s") VPR64:$Rn)>;
8573 def : Pat<(v4f32 (int_arm_neon_vcvthf2fp
8575 (v8i16 VPR128:$Rn))))),
8576 (!cast<Instruction>(prefix # "8h4s") VPR128:$Rn)>;
8578 def : Pat<(v2f64 (fextend (v2f32 VPR64:$Rn))),
8579 (!cast<Instruction>(prefix # "2s2d") VPR64:$Rn)>;
8581 def : Pat<(v2f64 (fextend
8582 (v2f32 (Neon_High4Float
8583 (v4f32 VPR128:$Rn))))),
8584 (!cast<Instruction>(prefix # "4s2d") VPR128:$Rn)>;
8587 defm : NeonI_2VMisc_Extend_Pattern<"FCVTL">;
8589 multiclass NeonI_2VMisc_SD_Conv<string asmop, bit Size, bit U, bits<5> opcode,
8590 ValueType ResTy4s, ValueType OpTy4s,
8591 ValueType ResTy2d, ValueType OpTy2d,
8592 ValueType ResTy2s, ValueType OpTy2s,
8593 SDPatternOperator Neon_Op> {
8595 def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8596 (outs VPR128:$Rd), (ins VPR128:$Rn),
8597 asmop # "\t$Rd.4s, $Rn.4s",
8598 [(set (ResTy4s VPR128:$Rd),
8599 (ResTy4s (Neon_Op (OpTy4s VPR128:$Rn))))],
8602 def 2d : NeonI_2VMisc<0b1, U, {Size, 0b1}, opcode,
8603 (outs VPR128:$Rd), (ins VPR128:$Rn),
8604 asmop # "\t$Rd.2d, $Rn.2d",
8605 [(set (ResTy2d VPR128:$Rd),
8606 (ResTy2d (Neon_Op (OpTy2d VPR128:$Rn))))],
8609 def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8610 (outs VPR64:$Rd), (ins VPR64:$Rn),
8611 asmop # "\t$Rd.2s, $Rn.2s",
8612 [(set (ResTy2s VPR64:$Rd),
8613 (ResTy2s (Neon_Op (OpTy2s VPR64:$Rn))))],
8617 multiclass NeonI_2VMisc_fp_to_int<string asmop, bit Size, bit U,
8618 bits<5> opcode, SDPatternOperator Neon_Op> {
8619 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4i32, v4f32, v2i64,
8620 v2f64, v2i32, v2f32, Neon_Op>;
8623 defm FCVTNS : NeonI_2VMisc_fp_to_int<"fcvtns", 0b0, 0b0, 0b11010,
8624 int_arm_neon_vcvtns>;
8625 defm FCVTNU : NeonI_2VMisc_fp_to_int<"fcvtnu", 0b0, 0b1, 0b11010,
8626 int_arm_neon_vcvtnu>;
8627 defm FCVTPS : NeonI_2VMisc_fp_to_int<"fcvtps", 0b1, 0b0, 0b11010,
8628 int_arm_neon_vcvtps>;
8629 defm FCVTPU : NeonI_2VMisc_fp_to_int<"fcvtpu", 0b1, 0b1, 0b11010,
8630 int_arm_neon_vcvtpu>;
8631 defm FCVTMS : NeonI_2VMisc_fp_to_int<"fcvtms", 0b0, 0b0, 0b11011,
8632 int_arm_neon_vcvtms>;
8633 defm FCVTMU : NeonI_2VMisc_fp_to_int<"fcvtmu", 0b0, 0b1, 0b11011,
8634 int_arm_neon_vcvtmu>;
8635 defm FCVTZS : NeonI_2VMisc_fp_to_int<"fcvtzs", 0b1, 0b0, 0b11011, fp_to_sint>;
8636 defm FCVTZU : NeonI_2VMisc_fp_to_int<"fcvtzu", 0b1, 0b1, 0b11011, fp_to_uint>;
8637 defm FCVTAS : NeonI_2VMisc_fp_to_int<"fcvtas", 0b0, 0b0, 0b11100,
8638 int_arm_neon_vcvtas>;
8639 defm FCVTAU : NeonI_2VMisc_fp_to_int<"fcvtau", 0b0, 0b1, 0b11100,
8640 int_arm_neon_vcvtau>;
8642 multiclass NeonI_2VMisc_int_to_fp<string asmop, bit Size, bit U,
8643 bits<5> opcode, SDPatternOperator Neon_Op> {
8644 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4i32, v2f64,
8645 v2i64, v2f32, v2i32, Neon_Op>;
8648 defm SCVTF : NeonI_2VMisc_int_to_fp<"scvtf", 0b0, 0b0, 0b11101, sint_to_fp>;
8649 defm UCVTF : NeonI_2VMisc_int_to_fp<"ucvtf", 0b0, 0b1, 0b11101, uint_to_fp>;
8651 multiclass NeonI_2VMisc_fp_to_fp<string asmop, bit Size, bit U,
8652 bits<5> opcode, SDPatternOperator Neon_Op> {
8653 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4f32, v2f64,
8654 v2f64, v2f32, v2f32, Neon_Op>;
8657 defm FRINTN : NeonI_2VMisc_fp_to_fp<"frintn", 0b0, 0b0, 0b11000,
8658 int_aarch64_neon_frintn>;
8659 defm FRINTA : NeonI_2VMisc_fp_to_fp<"frinta", 0b0, 0b1, 0b11000, frnd>;
8660 defm FRINTP : NeonI_2VMisc_fp_to_fp<"frintp", 0b1, 0b0, 0b11000, fceil>;
8661 defm FRINTM : NeonI_2VMisc_fp_to_fp<"frintm", 0b0, 0b0, 0b11001, ffloor>;
8662 defm FRINTX : NeonI_2VMisc_fp_to_fp<"frintx", 0b0, 0b1, 0b11001, frint>;
8663 defm FRINTZ : NeonI_2VMisc_fp_to_fp<"frintz", 0b1, 0b0, 0b11001, ftrunc>;
8664 defm FRINTI : NeonI_2VMisc_fp_to_fp<"frinti", 0b1, 0b1, 0b11001, fnearbyint>;
8665 defm FRECPE : NeonI_2VMisc_fp_to_fp<"frecpe", 0b1, 0b0, 0b11101,
8666 int_arm_neon_vrecpe>;
8667 defm FRSQRTE : NeonI_2VMisc_fp_to_fp<"frsqrte", 0b1, 0b1, 0b11101,
8668 int_arm_neon_vrsqrte>;
8669 defm FSQRT : NeonI_2VMisc_fp_to_fp<"fsqrt", 0b1, 0b1, 0b11111, fsqrt>;
8671 multiclass NeonI_2VMisc_S_Conv<string asmop, bit Size, bit U,
8672 bits<5> opcode, SDPatternOperator Neon_Op> {
8673 def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8674 (outs VPR128:$Rd), (ins VPR128:$Rn),
8675 asmop # "\t$Rd.4s, $Rn.4s",
8676 [(set (v4i32 VPR128:$Rd),
8677 (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
8680 def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8681 (outs VPR64:$Rd), (ins VPR64:$Rn),
8682 asmop # "\t$Rd.2s, $Rn.2s",
8683 [(set (v2i32 VPR64:$Rd),
8684 (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8688 defm URECPE : NeonI_2VMisc_S_Conv<"urecpe", 0b1, 0b0, 0b11100,
8689 int_arm_neon_vrecpe>;
8690 defm URSQRTE : NeonI_2VMisc_S_Conv<"ursqrte", 0b1, 0b1, 0b11100,
8691 int_arm_neon_vrsqrte>;
8694 class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
8695 string asmop, SDPatternOperator opnode>
8696 : NeonI_Crypto_AES<size, opcode,
8697 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8698 asmop # "\t$Rd.16b, $Rn.16b",
8699 [(set (v16i8 VPR128:$Rd),
8700 (v16i8 (opnode (v16i8 VPR128:$src),
8701 (v16i8 VPR128:$Rn))))],
8703 let Constraints = "$src = $Rd";
8704 let Predicates = [HasNEON, HasCrypto];
8707 def AESE : NeonI_Cryptoaes_2v<0b00, 0b00100, "aese", int_arm_neon_aese>;
8708 def AESD : NeonI_Cryptoaes_2v<0b00, 0b00101, "aesd", int_arm_neon_aesd>;
8710 class NeonI_Cryptoaes<bits<2> size, bits<5> opcode,
8711 string asmop, SDPatternOperator opnode>
8712 : NeonI_Crypto_AES<size, opcode,
8713 (outs VPR128:$Rd), (ins VPR128:$Rn),
8714 asmop # "\t$Rd.16b, $Rn.16b",
8715 [(set (v16i8 VPR128:$Rd),
8716 (v16i8 (opnode (v16i8 VPR128:$Rn))))],
8719 def AESMC : NeonI_Cryptoaes<0b00, 0b00110, "aesmc", int_arm_neon_aesmc>;
8720 def AESIMC : NeonI_Cryptoaes<0b00, 0b00111, "aesimc", int_arm_neon_aesimc>;
8722 class NeonI_Cryptosha_vv<bits<2> size, bits<5> opcode,
8723 string asmop, SDPatternOperator opnode>
8724 : NeonI_Crypto_SHA<size, opcode,
8725 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8726 asmop # "\t$Rd.4s, $Rn.4s",
8727 [(set (v4i32 VPR128:$Rd),
8728 (v4i32 (opnode (v4i32 VPR128:$src),
8729 (v4i32 VPR128:$Rn))))],
8731 let Constraints = "$src = $Rd";
8732 let Predicates = [HasNEON, HasCrypto];
8735 def SHA1SU1 : NeonI_Cryptosha_vv<0b00, 0b00001, "sha1su1",
8736 int_arm_neon_sha1su1>;
8737 def SHA256SU0 : NeonI_Cryptosha_vv<0b00, 0b00010, "sha256su0",
8738 int_arm_neon_sha256su0>;
8740 class NeonI_Cryptosha_ss<bits<2> size, bits<5> opcode,
8741 string asmop, SDPatternOperator opnode>
8742 : NeonI_Crypto_SHA<size, opcode,
8743 (outs FPR32:$Rd), (ins FPR32:$Rn),
8744 asmop # "\t$Rd, $Rn",
8745 [(set (v1i32 FPR32:$Rd),
8746 (v1i32 (opnode (v1i32 FPR32:$Rn))))],
8748 let Predicates = [HasNEON, HasCrypto];
8751 def SHA1H : NeonI_Cryptosha_ss<0b00, 0b00000, "sha1h", int_arm_neon_sha1h>;
8753 class NeonI_Cryptosha3_vvv<bits<2> size, bits<3> opcode, string asmop,
8754 SDPatternOperator opnode>
8755 : NeonI_Crypto_3VSHA<size, opcode,
8757 (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
8758 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
8759 [(set (v4i32 VPR128:$Rd),
8760 (v4i32 (opnode (v4i32 VPR128:$src),
8762 (v4i32 VPR128:$Rm))))],
8764 let Constraints = "$src = $Rd";
8765 let Predicates = [HasNEON, HasCrypto];
8768 def SHA1SU0 : NeonI_Cryptosha3_vvv<0b00, 0b011, "sha1su0",
8769 int_arm_neon_sha1su0>;
8770 def SHA256SU1 : NeonI_Cryptosha3_vvv<0b00, 0b110, "sha256su1",
8771 int_arm_neon_sha256su1>;
8773 class NeonI_Cryptosha3_qqv<bits<2> size, bits<3> opcode, string asmop,
8774 SDPatternOperator opnode>
8775 : NeonI_Crypto_3VSHA<size, opcode,
8777 (ins FPR128:$src, FPR128:$Rn, VPR128:$Rm),
8778 asmop # "\t$Rd, $Rn, $Rm.4s",
8779 [(set (v4i32 FPR128:$Rd),
8780 (v4i32 (opnode (v4i32 FPR128:$src),
8782 (v4i32 VPR128:$Rm))))],
8784 let Constraints = "$src = $Rd";
8785 let Predicates = [HasNEON, HasCrypto];
8788 def SHA256H : NeonI_Cryptosha3_qqv<0b00, 0b100, "sha256h",
8789 int_arm_neon_sha256h>;
8790 def SHA256H2 : NeonI_Cryptosha3_qqv<0b00, 0b101, "sha256h2",
8791 int_arm_neon_sha256h2>;
8793 class NeonI_Cryptosha3_qsv<bits<2> size, bits<3> opcode, string asmop,
8794 SDPatternOperator opnode>
8795 : NeonI_Crypto_3VSHA<size, opcode,
8797 (ins FPR128:$src, FPR32:$Rn, VPR128:$Rm),
8798 asmop # "\t$Rd, $Rn, $Rm.4s",
8799 [(set (v4i32 FPR128:$Rd),
8800 (v4i32 (opnode (v4i32 FPR128:$src),
8802 (v4i32 VPR128:$Rm))))],
8804 let Constraints = "$src = $Rd";
8805 let Predicates = [HasNEON, HasCrypto];
8808 def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
8809 def SHA1P : NeonI_Cryptosha3_qsv<0b00, 0b001, "sha1p", int_aarch64_neon_sha1p>;
8810 def SHA1M : NeonI_Cryptosha3_qsv<0b00, 0b010, "sha1m", int_aarch64_neon_sha1m>;
8812 // Additional patterns to match shl to USHL.
8813 def : Pat<(v8i8 (shl (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
8814 (USHLvvv_8B $Rn, $Rm)>;
8815 def : Pat<(v4i16 (shl (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
8816 (USHLvvv_4H $Rn, $Rm)>;
8817 def : Pat<(v2i32 (shl (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
8818 (USHLvvv_2S $Rn, $Rm)>;
8819 def : Pat<(v1i64 (shl (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
8820 (USHLddd $Rn, $Rm)>;
8821 def : Pat<(v16i8 (shl (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
8822 (USHLvvv_16B $Rn, $Rm)>;
8823 def : Pat<(v8i16 (shl (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
8824 (USHLvvv_8H $Rn, $Rm)>;
8825 def : Pat<(v4i32 (shl (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
8826 (USHLvvv_4S $Rn, $Rm)>;
8827 def : Pat<(v2i64 (shl (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
8828 (USHLvvv_2D $Rn, $Rm)>;
8830 // Additional patterns to match sra, srl.
8831 // For a vector right shift by vector, the shift amounts of SSHL/USHL are
8832 // negative. Negate the vector of shift amount first.
8833 def : Pat<(v8i8 (srl (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
8834 (USHLvvv_8B $Rn, (NEG8b $Rm))>;
8835 def : Pat<(v4i16 (srl (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
8836 (USHLvvv_4H $Rn, (NEG4h $Rm))>;
8837 def : Pat<(v2i32 (srl (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
8838 (USHLvvv_2S $Rn, (NEG2s $Rm))>;
8839 def : Pat<(v1i64 (srl (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
8840 (USHLddd $Rn, (NEGdd $Rm))>;
8841 def : Pat<(v16i8 (srl (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
8842 (USHLvvv_16B $Rn, (NEG16b $Rm))>;
8843 def : Pat<(v8i16 (srl (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
8844 (USHLvvv_8H $Rn, (NEG8h $Rm))>;
8845 def : Pat<(v4i32 (srl (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
8846 (USHLvvv_4S $Rn, (NEG4s $Rm))>;
8847 def : Pat<(v2i64 (srl (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
8848 (USHLvvv_2D $Rn, (NEG2d $Rm))>;
8850 def : Pat<(v8i8 (sra (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
8851 (SSHLvvv_8B $Rn, (NEG8b $Rm))>;
8852 def : Pat<(v4i16 (sra (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
8853 (SSHLvvv_4H $Rn, (NEG4h $Rm))>;
8854 def : Pat<(v2i32 (sra (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
8855 (SSHLvvv_2S $Rn, (NEG2s $Rm))>;
8856 def : Pat<(v1i64 (sra (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
8857 (SSHLddd $Rn, (NEGdd $Rm))>;
8858 def : Pat<(v16i8 (sra (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
8859 (SSHLvvv_16B $Rn, (NEG16b $Rm))>;
8860 def : Pat<(v8i16 (sra (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
8861 (SSHLvvv_8H $Rn, (NEG8h $Rm))>;
8862 def : Pat<(v4i32 (sra (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
8863 (SSHLvvv_4S $Rn, (NEG4s $Rm))>;
8864 def : Pat<(v2i64 (sra (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
8865 (SSHLvvv_2D $Rn, (NEG2d $Rm))>;
8868 // Patterns for handling half-precision values
8871 // Convert between f16 value and f32 value
8872 def : Pat<(f32 (f16_to_f32 (i32 GPR32:$Rn))),
8873 (FCVTsh (EXTRACT_SUBREG (FMOVsw $Rn), sub_16))>;
8874 def : Pat<(i32 (f32_to_f16 (f32 FPR32:$Rn))),
8875 (FMOVws (SUBREG_TO_REG (i64 0), (f16 (FCVThs $Rn)), sub_16))>;
8877 // Convert f16 value coming in as i16 value to f32
8878 def : Pat<(f32 (f16_to_f32 (i32 (and (i32 GPR32:$Rn), 65535)))),
8879 (FCVTsh (EXTRACT_SUBREG (FMOVsw GPR32:$Rn), sub_16))>;
8880 def : Pat<(f32 (f16_to_f32 (i32 (assertzext GPR32:$Rn)))),
8881 (FCVTsh (EXTRACT_SUBREG (FMOVsw GPR32:$Rn), sub_16))>;
8883 def : Pat<(f32 (f16_to_f32 (i32 (assertzext (i32 (
8884 f32_to_f16 (f32 FPR32:$Rn))))))),
8887 // Patterns for vector extract of half-precision FP value in i16 storage type
8888 def : Pat<(f32 (f16_to_f32 ( i32 (and (i32 (vector_extract
8889 (v4i16 VPR64:$Rn), neon_uimm2_bare:$Imm)), 65535)))),
8890 (FCVTsh (f16 (DUPhv_H
8891 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8892 neon_uimm2_bare:$Imm)))>;
8894 def : Pat<(f32 (f16_to_f32 ( i32 (and (i32 (vector_extract
8895 (v8i16 VPR128:$Rn), neon_uimm3_bare:$Imm)), 65535)))),
8896 (FCVTsh (f16 (DUPhv_H (v8i16 VPR128:$Rn), neon_uimm3_bare:$Imm)))>;
8898 // Patterns for vector insert of half-precision FP value 0 in i16 storage type
8899 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8900 (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 0))))))),
8901 (neon_uimm3_bare:$Imm))),
8902 (v8i16 (INSELh (v8i16 VPR128:$Rn),
8903 (v8i16 (SUBREG_TO_REG (i64 0),
8904 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 WZR))), sub_16)),
8906 neon_uimm3_bare:$Imm, 0))>;
8908 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8909 (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 0))))))),
8910 (neon_uimm2_bare:$Imm))),
8911 (v4i16 (EXTRACT_SUBREG
8913 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8914 (v8i16 (SUBREG_TO_REG (i64 0),
8915 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 WZR))), sub_16)),
8917 neon_uimm2_bare:$Imm, 0)),
8920 // Patterns for vector insert of half-precision FP value in i16 storage type
8921 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8922 (i32 (assertsext (i32 (fp_to_sint
8923 (f32 (f16_to_f32 (i32 (and (i32 GPR32:$src), 65535)))))))),
8924 (neon_uimm3_bare:$Imm))),
8925 (v8i16 (INSELh (v8i16 VPR128:$Rn),
8926 (v8i16 (SUBREG_TO_REG (i64 0),
8927 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 GPR32:$src))), sub_16)),
8929 neon_uimm3_bare:$Imm, 0))>;
8931 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8932 (i32 (assertsext (i32 (fp_to_sint
8933 (f32 (f16_to_f32 (i32 (and (i32 GPR32:$src), 65535)))))))),
8934 (neon_uimm2_bare:$Imm))),
8935 (v4i16 (EXTRACT_SUBREG
8937 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8938 (v8i16 (SUBREG_TO_REG (i64 0),
8939 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 GPR32:$src))), sub_16)),
8941 neon_uimm2_bare:$Imm, 0)),
8944 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8945 (i32 (vector_extract (v8i16 VPR128:$src), neon_uimm3_bare:$Imm2)),
8946 (neon_uimm3_bare:$Imm1))),
8947 (v8i16 (INSELh (v8i16 VPR128:$Rn), (v8i16 VPR128:$src),
8948 neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2))>;
8950 // Patterns for vector copy of half-precision FP value in i16 storage type
8951 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8952 (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 (and (i32
8953 (vector_extract (v8i16 VPR128:$src), neon_uimm3_bare:$Imm2)),
8955 (neon_uimm3_bare:$Imm1))),
8956 (v8i16 (INSELh (v8i16 VPR128:$Rn), (v8i16 VPR128:$src),
8957 neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2))>;
8959 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8960 (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 (and (i32
8961 (vector_extract (v4i16 VPR64:$src), neon_uimm3_bare:$Imm2)),
8963 (neon_uimm3_bare:$Imm1))),
8964 (v4i16 (EXTRACT_SUBREG
8966 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8967 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
8968 neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2)),