1 //===-- AArch64InstrNEON.td - NEON support for AArch64 -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the AArch64 NEON instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // NEON-specific DAG Nodes.
16 //===----------------------------------------------------------------------===//
18 // (outs Result), (ins Imm, OpCmode)
19 def SDT_Neon_movi : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
21 def Neon_movi : SDNode<"AArch64ISD::NEON_MOVIMM", SDT_Neon_movi>;
23 def Neon_mvni : SDNode<"AArch64ISD::NEON_MVNIMM", SDT_Neon_movi>;
25 // (outs Result), (ins Imm)
26 def Neon_fmovi : SDNode<"AArch64ISD::NEON_FMOVIMM", SDTypeProfile<1, 1,
27 [SDTCisVec<0>, SDTCisVT<1, i32>]>>;
29 // (outs Result), (ins LHS, RHS, CondCode)
30 def Neon_cmp : SDNode<"AArch64ISD::NEON_CMP", SDTypeProfile<1, 3,
31 [SDTCisVec<0>, SDTCisSameAs<1, 2>]>>;
33 // (outs Result), (ins LHS, 0/0.0 constant, CondCode)
34 def Neon_cmpz : SDNode<"AArch64ISD::NEON_CMPZ", SDTypeProfile<1, 3,
35 [SDTCisVec<0>, SDTCisVec<1>]>>;
37 // (outs Result), (ins LHS, RHS)
38 def Neon_tst : SDNode<"AArch64ISD::NEON_TST", SDTypeProfile<1, 2,
39 [SDTCisVec<0>, SDTCisSameAs<1, 2>]>>;
41 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
43 def Neon_sqrshlImm : SDNode<"AArch64ISD::NEON_QSHLs", SDTARMVSH>;
44 def Neon_uqrshlImm : SDNode<"AArch64ISD::NEON_QSHLu", SDTARMVSH>;
46 def SDTPERMUTE : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
48 def Neon_uzp1 : SDNode<"AArch64ISD::NEON_UZP1", SDTPERMUTE>;
49 def Neon_uzp2 : SDNode<"AArch64ISD::NEON_UZP2", SDTPERMUTE>;
50 def Neon_zip1 : SDNode<"AArch64ISD::NEON_ZIP1", SDTPERMUTE>;
51 def Neon_zip2 : SDNode<"AArch64ISD::NEON_ZIP2", SDTPERMUTE>;
52 def Neon_trn1 : SDNode<"AArch64ISD::NEON_TRN1", SDTPERMUTE>;
53 def Neon_trn2 : SDNode<"AArch64ISD::NEON_TRN2", SDTPERMUTE>;
55 def SDTVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
56 def Neon_rev64 : SDNode<"AArch64ISD::NEON_REV64", SDTVSHUF>;
57 def Neon_rev32 : SDNode<"AArch64ISD::NEON_REV32", SDTVSHUF>;
58 def Neon_rev16 : SDNode<"AArch64ISD::NEON_REV16", SDTVSHUF>;
59 def Neon_vdup : SDNode<"AArch64ISD::NEON_VDUP", SDTypeProfile<1, 1,
61 def Neon_vduplane : SDNode<"AArch64ISD::NEON_VDUPLANE", SDTypeProfile<1, 2,
62 [SDTCisVec<0>, SDTCisVec<1>, SDTCisVT<2, i64>]>>;
63 def Neon_vextract : SDNode<"AArch64ISD::NEON_VEXTRACT", SDTypeProfile<1, 3,
64 [SDTCisVec<0>, SDTCisSameAs<0, 1>,
65 SDTCisSameAs<0, 2>, SDTCisVT<3, i64>]>>;
67 def SDT_assertext : SDTypeProfile<1, 1,
68 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
69 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
70 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
72 //===----------------------------------------------------------------------===//
74 //===----------------------------------------------------------------------===//
76 multiclass NeonI_3VSame_B_sizes<bit u, bits<2> size, bits<5> opcode,
77 string asmop, SDPatternOperator opnode8B,
78 SDPatternOperator opnode16B,
80 let isCommutable = Commutable in {
81 def _8B : NeonI_3VSame<0b0, u, size, opcode,
82 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
83 asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
84 [(set (v8i8 VPR64:$Rd),
85 (v8i8 (opnode8B (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
88 def _16B : NeonI_3VSame<0b1, u, size, opcode,
89 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
90 asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
91 [(set (v16i8 VPR128:$Rd),
92 (v16i8 (opnode16B (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
98 multiclass NeonI_3VSame_HS_sizes<bit u, bits<5> opcode,
99 string asmop, SDPatternOperator opnode,
100 bit Commutable = 0> {
101 let isCommutable = Commutable in {
102 def _4H : NeonI_3VSame<0b0, u, 0b01, opcode,
103 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
104 asmop # "\t$Rd.4h, $Rn.4h, $Rm.4h",
105 [(set (v4i16 VPR64:$Rd),
106 (v4i16 (opnode (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))))],
109 def _8H : NeonI_3VSame<0b1, u, 0b01, opcode,
110 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
111 asmop # "\t$Rd.8h, $Rn.8h, $Rm.8h",
112 [(set (v8i16 VPR128:$Rd),
113 (v8i16 (opnode (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))))],
116 def _2S : NeonI_3VSame<0b0, u, 0b10, opcode,
117 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
118 asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
119 [(set (v2i32 VPR64:$Rd),
120 (v2i32 (opnode (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))))],
123 def _4S : NeonI_3VSame<0b1, u, 0b10, opcode,
124 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
125 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
126 [(set (v4i32 VPR128:$Rd),
127 (v4i32 (opnode (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))))],
131 multiclass NeonI_3VSame_BHS_sizes<bit u, bits<5> opcode,
132 string asmop, SDPatternOperator opnode,
134 : NeonI_3VSame_HS_sizes<u, opcode, asmop, opnode, Commutable> {
135 let isCommutable = Commutable in {
136 def _8B : NeonI_3VSame<0b0, u, 0b00, opcode,
137 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
138 asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
139 [(set (v8i8 VPR64:$Rd),
140 (v8i8 (opnode (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
143 def _16B : NeonI_3VSame<0b1, u, 0b00, opcode,
144 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
145 asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
146 [(set (v16i8 VPR128:$Rd),
147 (v16i8 (opnode (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
152 multiclass NeonI_3VSame_BHSD_sizes<bit u, bits<5> opcode,
153 string asmop, SDPatternOperator opnode,
155 : NeonI_3VSame_BHS_sizes<u, opcode, asmop, opnode, Commutable> {
156 let isCommutable = Commutable in {
157 def _2D : NeonI_3VSame<0b1, u, 0b11, opcode,
158 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
159 asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
160 [(set (v2i64 VPR128:$Rd),
161 (v2i64 (opnode (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))))],
166 // Multiclass NeonI_3VSame_SD_sizes: Operand types are floating point types,
167 // but Result types can be integer or floating point types.
168 multiclass NeonI_3VSame_SD_sizes<bit u, bit size, bits<5> opcode,
169 string asmop, SDPatternOperator opnode2S,
170 SDPatternOperator opnode4S,
171 SDPatternOperator opnode2D,
172 ValueType ResTy2S, ValueType ResTy4S,
173 ValueType ResTy2D, bit Commutable = 0> {
174 let isCommutable = Commutable in {
175 def _2S : NeonI_3VSame<0b0, u, {size, 0b0}, opcode,
176 (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
177 asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
178 [(set (ResTy2S VPR64:$Rd),
179 (ResTy2S (opnode2S (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
182 def _4S : NeonI_3VSame<0b1, u, {size, 0b0}, opcode,
183 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
184 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
185 [(set (ResTy4S VPR128:$Rd),
186 (ResTy4S (opnode4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
189 def _2D : NeonI_3VSame<0b1, u, {size, 0b1}, opcode,
190 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
191 asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
192 [(set (ResTy2D VPR128:$Rd),
193 (ResTy2D (opnode2D (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))))],
198 //===----------------------------------------------------------------------===//
199 // Instruction Definitions
200 //===----------------------------------------------------------------------===//
202 // Vector Arithmetic Instructions
204 // Vector Add (Integer and Floating-Point)
206 defm ADDvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b10000, "add", add, 1>;
207 defm FADDvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11010, "fadd", fadd, fadd, fadd,
208 v2f32, v4f32, v2f64, 1>;
210 // Vector Sub (Integer and Floating-Point)
212 defm SUBvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10000, "sub", sub, 0>;
213 defm FSUBvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11010, "fsub", fsub, fsub, fsub,
214 v2f32, v4f32, v2f64, 0>;
216 // Vector Multiply (Integer and Floating-Point)
218 defm MULvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10011, "mul", mul, 1>;
219 defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul, fmul, fmul,
220 v2f32, v4f32, v2f64, 1>;
222 // Vector Multiply (Polynomial)
224 defm PMULvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b10011, "pmul",
225 int_arm_neon_vmulp, int_arm_neon_vmulp, 1>;
227 // Vector Multiply-accumulate and Multiply-subtract (Integer)
229 // class NeonI_3VSame_Constraint_impl: NeonI_3VSame with no data type and
230 // two operands constraints.
231 class NeonI_3VSame_Constraint_impl<string asmop, string asmlane,
232 RegisterOperand VPRC, ValueType OpTy, bit q, bit u, bits<2> size,
233 bits<5> opcode, SDPatternOperator opnode>
234 : NeonI_3VSame<q, u, size, opcode,
235 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, VPRC:$Rm),
236 asmop # "\t$Rd" # asmlane # ", $Rn" # asmlane # ", $Rm" # asmlane,
237 [(set (OpTy VPRC:$Rd),
238 (OpTy (opnode (OpTy VPRC:$src), (OpTy VPRC:$Rn), (OpTy VPRC:$Rm))))],
240 let Constraints = "$src = $Rd";
243 def Neon_mla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
244 (add node:$Ra, (mul node:$Rn, node:$Rm))>;
246 def Neon_mls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
247 (sub node:$Ra, (mul node:$Rn, node:$Rm))>;
250 def MLAvvv_8B: NeonI_3VSame_Constraint_impl<"mla", ".8b", VPR64, v8i8,
251 0b0, 0b0, 0b00, 0b10010, Neon_mla>;
252 def MLAvvv_16B: NeonI_3VSame_Constraint_impl<"mla", ".16b", VPR128, v16i8,
253 0b1, 0b0, 0b00, 0b10010, Neon_mla>;
254 def MLAvvv_4H: NeonI_3VSame_Constraint_impl<"mla", ".4h", VPR64, v4i16,
255 0b0, 0b0, 0b01, 0b10010, Neon_mla>;
256 def MLAvvv_8H: NeonI_3VSame_Constraint_impl<"mla", ".8h", VPR128, v8i16,
257 0b1, 0b0, 0b01, 0b10010, Neon_mla>;
258 def MLAvvv_2S: NeonI_3VSame_Constraint_impl<"mla", ".2s", VPR64, v2i32,
259 0b0, 0b0, 0b10, 0b10010, Neon_mla>;
260 def MLAvvv_4S: NeonI_3VSame_Constraint_impl<"mla", ".4s", VPR128, v4i32,
261 0b1, 0b0, 0b10, 0b10010, Neon_mla>;
263 def MLSvvv_8B: NeonI_3VSame_Constraint_impl<"mls", ".8b", VPR64, v8i8,
264 0b0, 0b1, 0b00, 0b10010, Neon_mls>;
265 def MLSvvv_16B: NeonI_3VSame_Constraint_impl<"mls", ".16b", VPR128, v16i8,
266 0b1, 0b1, 0b00, 0b10010, Neon_mls>;
267 def MLSvvv_4H: NeonI_3VSame_Constraint_impl<"mls", ".4h", VPR64, v4i16,
268 0b0, 0b1, 0b01, 0b10010, Neon_mls>;
269 def MLSvvv_8H: NeonI_3VSame_Constraint_impl<"mls", ".8h", VPR128, v8i16,
270 0b1, 0b1, 0b01, 0b10010, Neon_mls>;
271 def MLSvvv_2S: NeonI_3VSame_Constraint_impl<"mls", ".2s", VPR64, v2i32,
272 0b0, 0b1, 0b10, 0b10010, Neon_mls>;
273 def MLSvvv_4S: NeonI_3VSame_Constraint_impl<"mls", ".4s", VPR128, v4i32,
274 0b1, 0b1, 0b10, 0b10010, Neon_mls>;
276 // Vector Multiply-accumulate and Multiply-subtract (Floating Point)
278 def Neon_fmla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
279 (fadd node:$Ra, (fmul node:$Rn, node:$Rm))>;
281 def Neon_fmls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
282 (fsub node:$Ra, (fmul node:$Rn, node:$Rm))>;
284 let Predicates = [HasNEON, UseFusedMAC] in {
285 def FMLAvvv_2S: NeonI_3VSame_Constraint_impl<"fmla", ".2s", VPR64, v2f32,
286 0b0, 0b0, 0b00, 0b11001, Neon_fmla>;
287 def FMLAvvv_4S: NeonI_3VSame_Constraint_impl<"fmla", ".4s", VPR128, v4f32,
288 0b1, 0b0, 0b00, 0b11001, Neon_fmla>;
289 def FMLAvvv_2D: NeonI_3VSame_Constraint_impl<"fmla", ".2d", VPR128, v2f64,
290 0b1, 0b0, 0b01, 0b11001, Neon_fmla>;
292 def FMLSvvv_2S: NeonI_3VSame_Constraint_impl<"fmls", ".2s", VPR64, v2f32,
293 0b0, 0b0, 0b10, 0b11001, Neon_fmls>;
294 def FMLSvvv_4S: NeonI_3VSame_Constraint_impl<"fmls", ".4s", VPR128, v4f32,
295 0b1, 0b0, 0b10, 0b11001, Neon_fmls>;
296 def FMLSvvv_2D: NeonI_3VSame_Constraint_impl<"fmls", ".2d", VPR128, v2f64,
297 0b1, 0b0, 0b11, 0b11001, Neon_fmls>;
300 // We're also allowed to match the fma instruction regardless of compile
302 def : Pat<(v2f32 (fma VPR64:$Rn, VPR64:$Rm, VPR64:$Ra)),
303 (FMLAvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
304 def : Pat<(v4f32 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
305 (FMLAvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
306 def : Pat<(v2f64 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
307 (FMLAvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
309 def : Pat<(v2f32 (fma (fneg VPR64:$Rn), VPR64:$Rm, VPR64:$Ra)),
310 (FMLSvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
311 def : Pat<(v4f32 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
312 (FMLSvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
313 def : Pat<(v2f64 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
314 (FMLSvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
316 // Vector Divide (Floating-Point)
318 defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv, fdiv, fdiv,
319 v2f32, v4f32, v2f64, 0>;
321 // Vector Bitwise Operations
323 // Vector Bitwise AND
325 defm ANDvvv : NeonI_3VSame_B_sizes<0b0, 0b00, 0b00011, "and", and, and, 1>;
327 // Vector Bitwise Exclusive OR
329 defm EORvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b00011, "eor", xor, xor, 1>;
333 defm ORRvvv : NeonI_3VSame_B_sizes<0b0, 0b10, 0b00011, "orr", or, or, 1>;
335 // ORR disassembled as MOV if Vn==Vm
337 // Vector Move - register
338 // Alias for ORR if Vn=Vm.
339 // FIXME: This is actually the preferred syntax but TableGen can't deal with
340 // custom printing of aliases.
341 def : NeonInstAlias<"mov $Rd.8b, $Rn.8b",
342 (ORRvvv_8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rn), 0>;
343 def : NeonInstAlias<"mov $Rd.16b, $Rn.16b",
344 (ORRvvv_16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rn), 0>;
346 // The MOVI instruction takes two immediate operands. The first is the
347 // immediate encoding, while the second is the cmode. A cmode of 14, or
348 // 0b1110, produces a MOVI operation, rather than a MVNI, ORR, or BIC.
349 def Neon_AllZero : PatFrag<(ops), (Neon_movi (i32 0), (i32 14))>;
350 def Neon_AllOne : PatFrag<(ops), (Neon_movi (i32 255), (i32 14))>;
352 def Neon_not8B : PatFrag<(ops node:$in),
353 (xor node:$in, (bitconvert (v8i8 Neon_AllOne)))>;
354 def Neon_not16B : PatFrag<(ops node:$in),
355 (xor node:$in, (bitconvert (v16i8 Neon_AllOne)))>;
357 def Neon_orn8B : PatFrag<(ops node:$Rn, node:$Rm),
358 (or node:$Rn, (Neon_not8B node:$Rm))>;
360 def Neon_orn16B : PatFrag<(ops node:$Rn, node:$Rm),
361 (or node:$Rn, (Neon_not16B node:$Rm))>;
363 def Neon_bic8B : PatFrag<(ops node:$Rn, node:$Rm),
364 (and node:$Rn, (Neon_not8B node:$Rm))>;
366 def Neon_bic16B : PatFrag<(ops node:$Rn, node:$Rm),
367 (and node:$Rn, (Neon_not16B node:$Rm))>;
370 // Vector Bitwise OR NOT - register
372 defm ORNvvv : NeonI_3VSame_B_sizes<0b0, 0b11, 0b00011, "orn",
373 Neon_orn8B, Neon_orn16B, 0>;
375 // Vector Bitwise Bit Clear (AND NOT) - register
377 defm BICvvv : NeonI_3VSame_B_sizes<0b0, 0b01, 0b00011, "bic",
378 Neon_bic8B, Neon_bic16B, 0>;
380 multiclass Neon_bitwise2V_patterns<SDPatternOperator opnode8B,
381 SDPatternOperator opnode16B,
383 Instruction INST16B> {
384 def : Pat<(v2i32 (opnode8B VPR64:$Rn, VPR64:$Rm)),
385 (INST8B VPR64:$Rn, VPR64:$Rm)>;
386 def : Pat<(v4i16 (opnode8B VPR64:$Rn, VPR64:$Rm)),
387 (INST8B VPR64:$Rn, VPR64:$Rm)>;
388 def : Pat<(v1i64 (opnode8B VPR64:$Rn, VPR64:$Rm)),
389 (INST8B VPR64:$Rn, VPR64:$Rm)>;
390 def : Pat<(v4i32 (opnode16B VPR128:$Rn, VPR128:$Rm)),
391 (INST16B VPR128:$Rn, VPR128:$Rm)>;
392 def : Pat<(v8i16 (opnode16B VPR128:$Rn, VPR128:$Rm)),
393 (INST16B VPR128:$Rn, VPR128:$Rm)>;
394 def : Pat<(v2i64 (opnode16B VPR128:$Rn, VPR128:$Rm)),
395 (INST16B VPR128:$Rn, VPR128:$Rm)>;
398 // Additional patterns for bitwise instructions AND, EOR, ORR, BIC, ORN
399 defm : Neon_bitwise2V_patterns<and, and, ANDvvv_8B, ANDvvv_16B>;
400 defm : Neon_bitwise2V_patterns<or, or, ORRvvv_8B, ORRvvv_16B>;
401 defm : Neon_bitwise2V_patterns<xor, xor, EORvvv_8B, EORvvv_16B>;
402 defm : Neon_bitwise2V_patterns<Neon_bic8B, Neon_bic16B, BICvvv_8B, BICvvv_16B>;
403 defm : Neon_bitwise2V_patterns<Neon_orn8B, Neon_orn16B, ORNvvv_8B, ORNvvv_16B>;
405 // Vector Bitwise Select
406 def BSLvvv_8B : NeonI_3VSame_Constraint_impl<"bsl", ".8b", VPR64, v8i8,
407 0b0, 0b1, 0b01, 0b00011, vselect>;
409 def BSLvvv_16B : NeonI_3VSame_Constraint_impl<"bsl", ".16b", VPR128, v16i8,
410 0b1, 0b1, 0b01, 0b00011, vselect>;
412 multiclass Neon_bitwise3V_patterns<SDPatternOperator opnode,
414 Instruction INST16B> {
415 // Disassociate type from instruction definition
416 def : Pat<(v8i8 (opnode (v8i8 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
417 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
418 def : Pat<(v2i32 (opnode (v2i32 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
419 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
420 def : Pat<(v4i16 (opnode (v4i16 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
421 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
422 def : Pat<(v1i64 (opnode (v1i64 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
423 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
424 def : Pat<(v16i8 (opnode (v16i8 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
425 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
426 def : Pat<(v4i32 (opnode (v4i32 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
427 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
428 def : Pat<(v8i16 (opnode (v8i16 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
429 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
430 def : Pat<(v2i64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
431 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
433 // Allow to match BSL instruction pattern with non-constant operand
434 def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
435 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
436 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
437 def : Pat<(v4i16 (or (and VPR64:$Rn, VPR64:$Rd),
438 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
439 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
440 def : Pat<(v2i32 (or (and VPR64:$Rn, VPR64:$Rd),
441 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
442 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
443 def : Pat<(v1i64 (or (and VPR64:$Rn, VPR64:$Rd),
444 (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
445 (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
446 def : Pat<(v16i8 (or (and VPR128:$Rn, VPR128:$Rd),
447 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
448 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
449 def : Pat<(v8i16 (or (and VPR128:$Rn, VPR128:$Rd),
450 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
451 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
452 def : Pat<(v4i32 (or (and VPR128:$Rn, VPR128:$Rd),
453 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
454 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
455 def : Pat<(v2i64 (or (and VPR128:$Rn, VPR128:$Rd),
456 (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
457 (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
459 // Allow to match llvm.arm.* intrinsics.
460 def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 VPR64:$src),
461 (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
462 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
463 def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 VPR64:$src),
464 (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
465 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
466 def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 VPR64:$src),
467 (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
468 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
469 def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 VPR64:$src),
470 (v1i64 VPR64:$Rn), (v1i64 VPR64:$Rm))),
471 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
472 def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 VPR64:$src),
473 (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
474 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
475 def : Pat<(v1f64 (int_arm_neon_vbsl (v1f64 VPR64:$src),
476 (v1f64 VPR64:$Rn), (v1f64 VPR64:$Rm))),
477 (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
478 def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 VPR128:$src),
479 (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
480 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
481 def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 VPR128:$src),
482 (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
483 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
484 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 VPR128:$src),
485 (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
486 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
487 def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 VPR128:$src),
488 (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
489 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
490 def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 VPR128:$src),
491 (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
492 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
493 def : Pat<(v2f64 (int_arm_neon_vbsl (v2f64 VPR128:$src),
494 (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
495 (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
498 // Additional patterns for bitwise instruction BSL
499 defm: Neon_bitwise3V_patterns<vselect, BSLvvv_8B, BSLvvv_16B>;
501 def Neon_NoBSLop : PatFrag<(ops node:$src, node:$Rn, node:$Rm),
502 (vselect node:$src, node:$Rn, node:$Rm),
503 [{ (void)N; return false; }]>;
505 // Vector Bitwise Insert if True
507 def BITvvv_8B : NeonI_3VSame_Constraint_impl<"bit", ".8b", VPR64, v8i8,
508 0b0, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
509 def BITvvv_16B : NeonI_3VSame_Constraint_impl<"bit", ".16b", VPR128, v16i8,
510 0b1, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
512 // Vector Bitwise Insert if False
514 def BIFvvv_8B : NeonI_3VSame_Constraint_impl<"bif", ".8b", VPR64, v8i8,
515 0b0, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
516 def BIFvvv_16B : NeonI_3VSame_Constraint_impl<"bif", ".16b", VPR128, v16i8,
517 0b1, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
519 // Vector Absolute Difference and Accumulate (Signed, Unsigned)
521 def Neon_uaba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
522 (add node:$Ra, (int_arm_neon_vabdu node:$Rn, node:$Rm))>;
523 def Neon_saba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
524 (add node:$Ra, (int_arm_neon_vabds node:$Rn, node:$Rm))>;
526 // Vector Absolute Difference and Accumulate (Unsigned)
527 def UABAvvv_8B : NeonI_3VSame_Constraint_impl<"uaba", ".8b", VPR64, v8i8,
528 0b0, 0b1, 0b00, 0b01111, Neon_uaba>;
529 def UABAvvv_16B : NeonI_3VSame_Constraint_impl<"uaba", ".16b", VPR128, v16i8,
530 0b1, 0b1, 0b00, 0b01111, Neon_uaba>;
531 def UABAvvv_4H : NeonI_3VSame_Constraint_impl<"uaba", ".4h", VPR64, v4i16,
532 0b0, 0b1, 0b01, 0b01111, Neon_uaba>;
533 def UABAvvv_8H : NeonI_3VSame_Constraint_impl<"uaba", ".8h", VPR128, v8i16,
534 0b1, 0b1, 0b01, 0b01111, Neon_uaba>;
535 def UABAvvv_2S : NeonI_3VSame_Constraint_impl<"uaba", ".2s", VPR64, v2i32,
536 0b0, 0b1, 0b10, 0b01111, Neon_uaba>;
537 def UABAvvv_4S : NeonI_3VSame_Constraint_impl<"uaba", ".4s", VPR128, v4i32,
538 0b1, 0b1, 0b10, 0b01111, Neon_uaba>;
540 // Vector Absolute Difference and Accumulate (Signed)
541 def SABAvvv_8B : NeonI_3VSame_Constraint_impl<"saba", ".8b", VPR64, v8i8,
542 0b0, 0b0, 0b00, 0b01111, Neon_saba>;
543 def SABAvvv_16B : NeonI_3VSame_Constraint_impl<"saba", ".16b", VPR128, v16i8,
544 0b1, 0b0, 0b00, 0b01111, Neon_saba>;
545 def SABAvvv_4H : NeonI_3VSame_Constraint_impl<"saba", ".4h", VPR64, v4i16,
546 0b0, 0b0, 0b01, 0b01111, Neon_saba>;
547 def SABAvvv_8H : NeonI_3VSame_Constraint_impl<"saba", ".8h", VPR128, v8i16,
548 0b1, 0b0, 0b01, 0b01111, Neon_saba>;
549 def SABAvvv_2S : NeonI_3VSame_Constraint_impl<"saba", ".2s", VPR64, v2i32,
550 0b0, 0b0, 0b10, 0b01111, Neon_saba>;
551 def SABAvvv_4S : NeonI_3VSame_Constraint_impl<"saba", ".4s", VPR128, v4i32,
552 0b1, 0b0, 0b10, 0b01111, Neon_saba>;
555 // Vector Absolute Difference (Signed, Unsigned)
556 defm UABDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01110, "uabd", int_arm_neon_vabdu, 0>;
557 defm SABDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01110, "sabd", int_arm_neon_vabds, 0>;
559 // Vector Absolute Difference (Floating Point)
560 defm FABDvvv: NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11010, "fabd",
561 int_arm_neon_vabds, int_arm_neon_vabds,
562 int_arm_neon_vabds, v2f32, v4f32, v2f64, 0>;
564 // Vector Reciprocal Step (Floating Point)
565 defm FRECPSvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11111, "frecps",
566 int_arm_neon_vrecps, int_arm_neon_vrecps,
568 v2f32, v4f32, v2f64, 0>;
570 // Vector Reciprocal Square Root Step (Floating Point)
571 defm FRSQRTSvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11111, "frsqrts",
572 int_arm_neon_vrsqrts,
573 int_arm_neon_vrsqrts,
574 int_arm_neon_vrsqrts,
575 v2f32, v4f32, v2f64, 0>;
577 // Vector Comparisons
579 def Neon_cmeq : PatFrag<(ops node:$lhs, node:$rhs),
580 (Neon_cmp node:$lhs, node:$rhs, SETEQ)>;
581 def Neon_cmphs : PatFrag<(ops node:$lhs, node:$rhs),
582 (Neon_cmp node:$lhs, node:$rhs, SETUGE)>;
583 def Neon_cmge : PatFrag<(ops node:$lhs, node:$rhs),
584 (Neon_cmp node:$lhs, node:$rhs, SETGE)>;
585 def Neon_cmhi : PatFrag<(ops node:$lhs, node:$rhs),
586 (Neon_cmp node:$lhs, node:$rhs, SETUGT)>;
587 def Neon_cmgt : PatFrag<(ops node:$lhs, node:$rhs),
588 (Neon_cmp node:$lhs, node:$rhs, SETGT)>;
590 // NeonI_compare_aliases class: swaps register operands to implement
591 // comparison aliases, e.g., CMLE is alias for CMGE with operands reversed.
592 class NeonI_compare_aliases<string asmop, string asmlane,
593 Instruction inst, RegisterOperand VPRC>
594 : NeonInstAlias<asmop # "\t$Rd" # asmlane #", $Rn" # asmlane #
596 (inst VPRC:$Rd, VPRC:$Rm, VPRC:$Rn), 0b0>;
598 // Vector Comparisons (Integer)
600 // Vector Compare Mask Equal (Integer)
601 let isCommutable =1 in {
602 defm CMEQvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10001, "cmeq", Neon_cmeq, 0>;
605 // Vector Compare Mask Higher or Same (Unsigned Integer)
606 defm CMHSvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00111, "cmhs", Neon_cmphs, 0>;
608 // Vector Compare Mask Greater Than or Equal (Integer)
609 defm CMGEvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00111, "cmge", Neon_cmge, 0>;
611 // Vector Compare Mask Higher (Unsigned Integer)
612 defm CMHIvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00110, "cmhi", Neon_cmhi, 0>;
614 // Vector Compare Mask Greater Than (Integer)
615 defm CMGTvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00110, "cmgt", Neon_cmgt, 0>;
617 // Vector Compare Mask Bitwise Test (Integer)
618 defm CMTSTvvv: NeonI_3VSame_BHSD_sizes<0b0, 0b10001, "cmtst", Neon_tst, 0>;
620 // Vector Compare Mask Less or Same (Unsigned Integer)
621 // CMLS is alias for CMHS with operands reversed.
622 def CMLSvvv_8B : NeonI_compare_aliases<"cmls", ".8b", CMHSvvv_8B, VPR64>;
623 def CMLSvvv_16B : NeonI_compare_aliases<"cmls", ".16b", CMHSvvv_16B, VPR128>;
624 def CMLSvvv_4H : NeonI_compare_aliases<"cmls", ".4h", CMHSvvv_4H, VPR64>;
625 def CMLSvvv_8H : NeonI_compare_aliases<"cmls", ".8h", CMHSvvv_8H, VPR128>;
626 def CMLSvvv_2S : NeonI_compare_aliases<"cmls", ".2s", CMHSvvv_2S, VPR64>;
627 def CMLSvvv_4S : NeonI_compare_aliases<"cmls", ".4s", CMHSvvv_4S, VPR128>;
628 def CMLSvvv_2D : NeonI_compare_aliases<"cmls", ".2d", CMHSvvv_2D, VPR128>;
630 // Vector Compare Mask Less Than or Equal (Integer)
631 // CMLE is alias for CMGE with operands reversed.
632 def CMLEvvv_8B : NeonI_compare_aliases<"cmle", ".8b", CMGEvvv_8B, VPR64>;
633 def CMLEvvv_16B : NeonI_compare_aliases<"cmle", ".16b", CMGEvvv_16B, VPR128>;
634 def CMLEvvv_4H : NeonI_compare_aliases<"cmle", ".4h", CMGEvvv_4H, VPR64>;
635 def CMLEvvv_8H : NeonI_compare_aliases<"cmle", ".8h", CMGEvvv_8H, VPR128>;
636 def CMLEvvv_2S : NeonI_compare_aliases<"cmle", ".2s", CMGEvvv_2S, VPR64>;
637 def CMLEvvv_4S : NeonI_compare_aliases<"cmle", ".4s", CMGEvvv_4S, VPR128>;
638 def CMLEvvv_2D : NeonI_compare_aliases<"cmle", ".2d", CMGEvvv_2D, VPR128>;
640 // Vector Compare Mask Lower (Unsigned Integer)
641 // CMLO is alias for CMHI with operands reversed.
642 def CMLOvvv_8B : NeonI_compare_aliases<"cmlo", ".8b", CMHIvvv_8B, VPR64>;
643 def CMLOvvv_16B : NeonI_compare_aliases<"cmlo", ".16b", CMHIvvv_16B, VPR128>;
644 def CMLOvvv_4H : NeonI_compare_aliases<"cmlo", ".4h", CMHIvvv_4H, VPR64>;
645 def CMLOvvv_8H : NeonI_compare_aliases<"cmlo", ".8h", CMHIvvv_8H, VPR128>;
646 def CMLOvvv_2S : NeonI_compare_aliases<"cmlo", ".2s", CMHIvvv_2S, VPR64>;
647 def CMLOvvv_4S : NeonI_compare_aliases<"cmlo", ".4s", CMHIvvv_4S, VPR128>;
648 def CMLOvvv_2D : NeonI_compare_aliases<"cmlo", ".2d", CMHIvvv_2D, VPR128>;
650 // Vector Compare Mask Less Than (Integer)
651 // CMLT is alias for CMGT with operands reversed.
652 def CMLTvvv_8B : NeonI_compare_aliases<"cmlt", ".8b", CMGTvvv_8B, VPR64>;
653 def CMLTvvv_16B : NeonI_compare_aliases<"cmlt", ".16b", CMGTvvv_16B, VPR128>;
654 def CMLTvvv_4H : NeonI_compare_aliases<"cmlt", ".4h", CMGTvvv_4H, VPR64>;
655 def CMLTvvv_8H : NeonI_compare_aliases<"cmlt", ".8h", CMGTvvv_8H, VPR128>;
656 def CMLTvvv_2S : NeonI_compare_aliases<"cmlt", ".2s", CMGTvvv_2S, VPR64>;
657 def CMLTvvv_4S : NeonI_compare_aliases<"cmlt", ".4s", CMGTvvv_4S, VPR128>;
658 def CMLTvvv_2D : NeonI_compare_aliases<"cmlt", ".2d", CMGTvvv_2D, VPR128>;
661 def neon_uimm0_asmoperand : AsmOperandClass
664 let PredicateMethod = "isUImm<0>";
665 let RenderMethod = "addImmOperands";
668 def neon_uimm0 : Operand<i32>, ImmLeaf<i32, [{return Imm == 0;}]> {
669 let ParserMatchClass = neon_uimm0_asmoperand;
670 let PrintMethod = "printNeonUImm0Operand";
674 multiclass NeonI_cmpz_sizes<bit u, bits<5> opcode, string asmop, CondCode CC>
676 def _8B : NeonI_2VMisc<0b0, u, 0b00, opcode,
677 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
678 asmop # "\t$Rd.8b, $Rn.8b, $Imm",
679 [(set (v8i8 VPR64:$Rd),
680 (v8i8 (Neon_cmpz (v8i8 VPR64:$Rn), (i32 imm:$Imm), CC)))],
683 def _16B : NeonI_2VMisc<0b1, u, 0b00, opcode,
684 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
685 asmop # "\t$Rd.16b, $Rn.16b, $Imm",
686 [(set (v16i8 VPR128:$Rd),
687 (v16i8 (Neon_cmpz (v16i8 VPR128:$Rn), (i32 imm:$Imm), CC)))],
690 def _4H : NeonI_2VMisc<0b0, u, 0b01, opcode,
691 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
692 asmop # "\t$Rd.4h, $Rn.4h, $Imm",
693 [(set (v4i16 VPR64:$Rd),
694 (v4i16 (Neon_cmpz (v4i16 VPR64:$Rn), (i32 imm:$Imm), CC)))],
697 def _8H : NeonI_2VMisc<0b1, u, 0b01, opcode,
698 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
699 asmop # "\t$Rd.8h, $Rn.8h, $Imm",
700 [(set (v8i16 VPR128:$Rd),
701 (v8i16 (Neon_cmpz (v8i16 VPR128:$Rn), (i32 imm:$Imm), CC)))],
704 def _2S : NeonI_2VMisc<0b0, u, 0b10, opcode,
705 (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
706 asmop # "\t$Rd.2s, $Rn.2s, $Imm",
707 [(set (v2i32 VPR64:$Rd),
708 (v2i32 (Neon_cmpz (v2i32 VPR64:$Rn), (i32 imm:$Imm), CC)))],
711 def _4S : NeonI_2VMisc<0b1, u, 0b10, opcode,
712 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
713 asmop # "\t$Rd.4s, $Rn.4s, $Imm",
714 [(set (v4i32 VPR128:$Rd),
715 (v4i32 (Neon_cmpz (v4i32 VPR128:$Rn), (i32 imm:$Imm), CC)))],
718 def _2D : NeonI_2VMisc<0b1, u, 0b11, opcode,
719 (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
720 asmop # "\t$Rd.2d, $Rn.2d, $Imm",
721 [(set (v2i64 VPR128:$Rd),
722 (v2i64 (Neon_cmpz (v2i64 VPR128:$Rn), (i32 imm:$Imm), CC)))],
726 // Vector Compare Mask Equal to Zero (Integer)
727 defm CMEQvvi : NeonI_cmpz_sizes<0b0, 0b01001, "cmeq", SETEQ>;
729 // Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
730 defm CMGEvvi : NeonI_cmpz_sizes<0b1, 0b01000, "cmge", SETGE>;
732 // Vector Compare Mask Greater Than Zero (Signed Integer)
733 defm CMGTvvi : NeonI_cmpz_sizes<0b0, 0b01000, "cmgt", SETGT>;
735 // Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
736 defm CMLEvvi : NeonI_cmpz_sizes<0b1, 0b01001, "cmle", SETLE>;
738 // Vector Compare Mask Less Than Zero (Signed Integer)
739 defm CMLTvvi : NeonI_cmpz_sizes<0b0, 0b01010, "cmlt", SETLT>;
741 // Vector Comparisons (Floating Point)
743 // Vector Compare Mask Equal (Floating Point)
744 let isCommutable =1 in {
745 defm FCMEQvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11100, "fcmeq", Neon_cmeq,
746 Neon_cmeq, Neon_cmeq,
747 v2i32, v4i32, v2i64, 0>;
750 // Vector Compare Mask Greater Than Or Equal (Floating Point)
751 defm FCMGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11100, "fcmge", Neon_cmge,
752 Neon_cmge, Neon_cmge,
753 v2i32, v4i32, v2i64, 0>;
755 // Vector Compare Mask Greater Than (Floating Point)
756 defm FCMGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11100, "fcmgt", Neon_cmgt,
757 Neon_cmgt, Neon_cmgt,
758 v2i32, v4i32, v2i64, 0>;
760 // Vector Compare Mask Less Than Or Equal (Floating Point)
761 // FCMLE is alias for FCMGE with operands reversed.
762 def FCMLEvvv_2S : NeonI_compare_aliases<"fcmle", ".2s", FCMGEvvv_2S, VPR64>;
763 def FCMLEvvv_4S : NeonI_compare_aliases<"fcmle", ".4s", FCMGEvvv_4S, VPR128>;
764 def FCMLEvvv_2D : NeonI_compare_aliases<"fcmle", ".2d", FCMGEvvv_2D, VPR128>;
766 // Vector Compare Mask Less Than (Floating Point)
767 // FCMLT is alias for FCMGT with operands reversed.
768 def FCMLTvvv_2S : NeonI_compare_aliases<"fcmlt", ".2s", FCMGTvvv_2S, VPR64>;
769 def FCMLTvvv_4S : NeonI_compare_aliases<"fcmlt", ".4s", FCMGTvvv_4S, VPR128>;
770 def FCMLTvvv_2D : NeonI_compare_aliases<"fcmlt", ".2d", FCMGTvvv_2D, VPR128>;
773 multiclass NeonI_fpcmpz_sizes<bit u, bit size, bits<5> opcode,
774 string asmop, CondCode CC>
776 def _2S : NeonI_2VMisc<0b0, u, {size, 0b0}, opcode,
777 (outs VPR64:$Rd), (ins VPR64:$Rn, fpz32:$FPImm),
778 asmop # "\t$Rd.2s, $Rn.2s, $FPImm",
779 [(set (v2i32 VPR64:$Rd),
780 (v2i32 (Neon_cmpz (v2f32 VPR64:$Rn), (f32 fpz32:$FPImm), CC)))],
783 def _4S : NeonI_2VMisc<0b1, u, {size, 0b0}, opcode,
784 (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
785 asmop # "\t$Rd.4s, $Rn.4s, $FPImm",
786 [(set (v4i32 VPR128:$Rd),
787 (v4i32 (Neon_cmpz (v4f32 VPR128:$Rn), (f32 fpz32:$FPImm), CC)))],
790 def _2D : NeonI_2VMisc<0b1, u, {size, 0b1}, opcode,
791 (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
792 asmop # "\t$Rd.2d, $Rn.2d, $FPImm",
793 [(set (v2i64 VPR128:$Rd),
794 (v2i64 (Neon_cmpz (v2f64 VPR128:$Rn), (f32 fpz32:$FPImm), CC)))],
798 // Vector Compare Mask Equal to Zero (Floating Point)
799 defm FCMEQvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01101, "fcmeq", SETEQ>;
801 // Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
802 defm FCMGEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01100, "fcmge", SETGE>;
804 // Vector Compare Mask Greater Than Zero (Floating Point)
805 defm FCMGTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01100, "fcmgt", SETGT>;
807 // Vector Compare Mask Less Than or Equal To Zero (Floating Point)
808 defm FCMLEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01101, "fcmle", SETLE>;
810 // Vector Compare Mask Less Than Zero (Floating Point)
811 defm FCMLTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01110, "fcmlt", SETLT>;
813 // Vector Absolute Comparisons (Floating Point)
815 // Vector Absolute Compare Mask Greater Than Or Equal (Floating Point)
816 defm FACGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11101, "facge",
817 int_arm_neon_vacged, int_arm_neon_vacgeq,
818 int_aarch64_neon_vacgeq,
819 v2i32, v4i32, v2i64, 0>;
821 // Vector Absolute Compare Mask Greater Than (Floating Point)
822 defm FACGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11101, "facgt",
823 int_arm_neon_vacgtd, int_arm_neon_vacgtq,
824 int_aarch64_neon_vacgtq,
825 v2i32, v4i32, v2i64, 0>;
827 // Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
828 // FACLE is alias for FACGE with operands reversed.
829 def FACLEvvv_2S : NeonI_compare_aliases<"facle", ".2s", FACGEvvv_2S, VPR64>;
830 def FACLEvvv_4S : NeonI_compare_aliases<"facle", ".4s", FACGEvvv_4S, VPR128>;
831 def FACLEvvv_2D : NeonI_compare_aliases<"facle", ".2d", FACGEvvv_2D, VPR128>;
833 // Vector Absolute Compare Mask Less Than (Floating Point)
834 // FACLT is alias for FACGT with operands reversed.
835 def FACLTvvv_2S : NeonI_compare_aliases<"faclt", ".2s", FACGTvvv_2S, VPR64>;
836 def FACLTvvv_4S : NeonI_compare_aliases<"faclt", ".4s", FACGTvvv_4S, VPR128>;
837 def FACLTvvv_2D : NeonI_compare_aliases<"faclt", ".2d", FACGTvvv_2D, VPR128>;
839 // Vector halving add (Integer Signed, Unsigned)
840 defm SHADDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00000, "shadd",
841 int_arm_neon_vhadds, 1>;
842 defm UHADDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00000, "uhadd",
843 int_arm_neon_vhaddu, 1>;
845 // Vector halving sub (Integer Signed, Unsigned)
846 defm SHSUBvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00100, "shsub",
847 int_arm_neon_vhsubs, 0>;
848 defm UHSUBvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00100, "uhsub",
849 int_arm_neon_vhsubu, 0>;
851 // Vector rouding halving add (Integer Signed, Unsigned)
852 defm SRHADDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b00010, "srhadd",
853 int_arm_neon_vrhadds, 1>;
854 defm URHADDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b00010, "urhadd",
855 int_arm_neon_vrhaddu, 1>;
857 // Vector Saturating add (Integer Signed, Unsigned)
858 defm SQADDvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00001, "sqadd",
859 int_arm_neon_vqadds, 1>;
860 defm UQADDvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00001, "uqadd",
861 int_arm_neon_vqaddu, 1>;
863 // Vector Saturating sub (Integer Signed, Unsigned)
864 defm SQSUBvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00101, "sqsub",
865 int_arm_neon_vqsubs, 1>;
866 defm UQSUBvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00101, "uqsub",
867 int_arm_neon_vqsubu, 1>;
869 // Vector Shift Left (Signed and Unsigned Integer)
870 defm SSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01000, "sshl",
871 int_arm_neon_vshifts, 1>;
872 defm USHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01000, "ushl",
873 int_arm_neon_vshiftu, 1>;
875 // Vector Saturating Shift Left (Signed and Unsigned Integer)
876 defm SQSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01001, "sqshl",
877 int_arm_neon_vqshifts, 1>;
878 defm UQSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01001, "uqshl",
879 int_arm_neon_vqshiftu, 1>;
881 // Vector Rouding Shift Left (Signed and Unsigned Integer)
882 defm SRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01010, "srshl",
883 int_arm_neon_vrshifts, 1>;
884 defm URSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01010, "urshl",
885 int_arm_neon_vrshiftu, 1>;
887 // Vector Saturating Rouding Shift Left (Signed and Unsigned Integer)
888 defm SQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01011, "sqrshl",
889 int_arm_neon_vqrshifts, 1>;
890 defm UQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01011, "uqrshl",
891 int_arm_neon_vqrshiftu, 1>;
893 // Vector Maximum (Signed and Unsigned Integer)
894 defm SMAXvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01100, "smax", int_arm_neon_vmaxs, 1>;
895 defm UMAXvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01100, "umax", int_arm_neon_vmaxu, 1>;
897 // Vector Minimum (Signed and Unsigned Integer)
898 defm SMINvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01101, "smin", int_arm_neon_vmins, 1>;
899 defm UMINvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01101, "umin", int_arm_neon_vminu, 1>;
901 // Vector Maximum (Floating Point)
902 defm FMAXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11110, "fmax",
903 int_arm_neon_vmaxs, int_arm_neon_vmaxs,
904 int_arm_neon_vmaxs, v2f32, v4f32, v2f64, 1>;
906 // Vector Minimum (Floating Point)
907 defm FMINvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11110, "fmin",
908 int_arm_neon_vmins, int_arm_neon_vmins,
909 int_arm_neon_vmins, v2f32, v4f32, v2f64, 1>;
911 // Vector maxNum (Floating Point) - prefer a number over a quiet NaN)
912 defm FMAXNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11000, "fmaxnm",
913 int_aarch64_neon_vmaxnm,
914 int_aarch64_neon_vmaxnm,
915 int_aarch64_neon_vmaxnm,
916 v2f32, v4f32, v2f64, 1>;
918 // Vector minNum (Floating Point) - prefer a number over a quiet NaN)
919 defm FMINNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11000, "fminnm",
920 int_aarch64_neon_vminnm,
921 int_aarch64_neon_vminnm,
922 int_aarch64_neon_vminnm,
923 v2f32, v4f32, v2f64, 1>;
925 // Vector Maximum Pairwise (Signed and Unsigned Integer)
926 defm SMAXPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10100, "smaxp", int_arm_neon_vpmaxs, 1>;
927 defm UMAXPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10100, "umaxp", int_arm_neon_vpmaxu, 1>;
929 // Vector Minimum Pairwise (Signed and Unsigned Integer)
930 defm SMINPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10101, "sminp", int_arm_neon_vpmins, 1>;
931 defm UMINPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10101, "uminp", int_arm_neon_vpminu, 1>;
933 // Vector Maximum Pairwise (Floating Point)
934 defm FMAXPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11110, "fmaxp",
935 int_arm_neon_vpmaxs, int_arm_neon_vpmaxs,
936 int_arm_neon_vpmaxs, v2f32, v4f32, v2f64, 1>;
938 // Vector Minimum Pairwise (Floating Point)
939 defm FMINPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11110, "fminp",
940 int_arm_neon_vpmins, int_arm_neon_vpmins,
941 int_arm_neon_vpmins, v2f32, v4f32, v2f64, 1>;
943 // Vector maxNum Pairwise (Floating Point) - prefer a number over a quiet NaN)
944 defm FMAXNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11000, "fmaxnmp",
945 int_aarch64_neon_vpmaxnm,
946 int_aarch64_neon_vpmaxnm,
947 int_aarch64_neon_vpmaxnm,
948 v2f32, v4f32, v2f64, 1>;
950 // Vector minNum Pairwise (Floating Point) - prefer a number over a quiet NaN)
951 defm FMINNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11000, "fminnmp",
952 int_aarch64_neon_vpminnm,
953 int_aarch64_neon_vpminnm,
954 int_aarch64_neon_vpminnm,
955 v2f32, v4f32, v2f64, 1>;
957 // Vector Addition Pairwise (Integer)
958 defm ADDP : NeonI_3VSame_BHSD_sizes<0b0, 0b10111, "addp", int_arm_neon_vpadd, 1>;
960 // Vector Addition Pairwise (Floating Point)
961 defm FADDP : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11010, "faddp",
965 v2f32, v4f32, v2f64, 1>;
967 // Vector Saturating Doubling Multiply High
968 defm SQDMULHvvv : NeonI_3VSame_HS_sizes<0b0, 0b10110, "sqdmulh",
969 int_arm_neon_vqdmulh, 1>;
971 // Vector Saturating Rouding Doubling Multiply High
972 defm SQRDMULHvvv : NeonI_3VSame_HS_sizes<0b1, 0b10110, "sqrdmulh",
973 int_arm_neon_vqrdmulh, 1>;
975 // Vector Multiply Extended (Floating Point)
976 defm FMULXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11011, "fmulx",
977 int_aarch64_neon_vmulx,
978 int_aarch64_neon_vmulx,
979 int_aarch64_neon_vmulx,
980 v2f32, v4f32, v2f64, 1>;
982 // Patterns to match llvm.aarch64.* intrinsic for
983 // ADDP, SMINP, UMINP, SMAXP, UMAXP having i32 as output
984 class Neon_VectorPair_v2i32_pattern<SDPatternOperator opnode, Instruction INST>
985 : Pat<(v1i32 (opnode (v2i32 VPR64:$Rn))),
987 (v2i32 (INST (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rn))),
990 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_sminv, SMINPvvv_2S>;
991 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_uminv, UMINPvvv_2S>;
992 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_smaxv, SMAXPvvv_2S>;
993 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_umaxv, UMAXPvvv_2S>;
994 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_vaddv, ADDP_2S>;
996 // Vector Immediate Instructions
998 multiclass neon_mov_imm_shift_asmoperands<string PREFIX>
1000 def _asmoperand : AsmOperandClass
1002 let Name = "NeonMovImmShift" # PREFIX;
1003 let RenderMethod = "addNeonMovImmShift" # PREFIX # "Operands";
1004 let PredicateMethod = "isNeonMovImmShift" # PREFIX;
1008 // Definition of vector immediates shift operands
1010 // The selectable use-cases extract the shift operation
1011 // information from the OpCmode fields encoded in the immediate.
1012 def neon_mod_shift_imm_XFORM : SDNodeXForm<imm, [{
1013 uint64_t OpCmode = N->getZExtValue();
1015 unsigned ShiftOnesIn;
1017 A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1018 if (!HasShift) return SDValue();
1019 return CurDAG->getTargetConstant(ShiftImm, MVT::i32);
1022 // Vector immediates shift operands which accept LSL and MSL
1023 // shift operators with shift value in the range of 0, 8, 16, 24 (LSL),
1024 // or 0, 8 (LSLH) or 8, 16 (MSL).
1025 defm neon_mov_imm_LSL : neon_mov_imm_shift_asmoperands<"LSL">;
1026 defm neon_mov_imm_MSL : neon_mov_imm_shift_asmoperands<"MSL">;
1027 // LSLH restricts shift amount to 0, 8 out of 0, 8, 16, 24
1028 defm neon_mov_imm_LSLH : neon_mov_imm_shift_asmoperands<"LSLH">;
1030 multiclass neon_mov_imm_shift_operands<string PREFIX,
1031 string HALF, string ISHALF, code pred>
1033 def _operand : Operand<i32>, ImmLeaf<i32, pred, neon_mod_shift_imm_XFORM>
1036 "printNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1038 "DecodeNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1039 let ParserMatchClass =
1040 !cast<AsmOperandClass>("neon_mov_imm_" # PREFIX # HALF # "_asmoperand");
1044 defm neon_mov_imm_LSL : neon_mov_imm_shift_operands<"LSL", "", "false", [{
1046 unsigned ShiftOnesIn;
1048 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1049 return (HasShift && !ShiftOnesIn);
1052 defm neon_mov_imm_MSL : neon_mov_imm_shift_operands<"MSL", "", "false", [{
1054 unsigned ShiftOnesIn;
1056 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1057 return (HasShift && ShiftOnesIn);
1060 defm neon_mov_imm_LSLH : neon_mov_imm_shift_operands<"LSL", "H", "true", [{
1062 unsigned ShiftOnesIn;
1064 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1065 return (HasShift && !ShiftOnesIn);
1068 def neon_uimm1_asmoperand : AsmOperandClass
1071 let PredicateMethod = "isUImm<1>";
1072 let RenderMethod = "addImmOperands";
1075 def neon_uimm2_asmoperand : AsmOperandClass
1078 let PredicateMethod = "isUImm<2>";
1079 let RenderMethod = "addImmOperands";
1082 def neon_uimm8_asmoperand : AsmOperandClass
1085 let PredicateMethod = "isUImm<8>";
1086 let RenderMethod = "addImmOperands";
1089 def neon_uimm8 : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1090 let ParserMatchClass = neon_uimm8_asmoperand;
1091 let PrintMethod = "printUImmHexOperand";
1094 def neon_uimm64_mask_asmoperand : AsmOperandClass
1096 let Name = "NeonUImm64Mask";
1097 let PredicateMethod = "isNeonUImm64Mask";
1098 let RenderMethod = "addNeonUImm64MaskOperands";
1101 // MCOperand for 64-bit bytemask with each byte having only the
1102 // value 0x00 and 0xff is encoded as an unsigned 8-bit value
1103 def neon_uimm64_mask : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1104 let ParserMatchClass = neon_uimm64_mask_asmoperand;
1105 let PrintMethod = "printNeonUImm64MaskOperand";
1108 multiclass NeonI_mov_imm_lsl_sizes<string asmop, bit op,
1109 SDPatternOperator opnode>
1111 // shift zeros, per word
1112 def _2S : NeonI_1VModImm<0b0, op,
1114 (ins neon_uimm8:$Imm,
1115 neon_mov_imm_LSL_operand:$Simm),
1116 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1117 [(set (v2i32 VPR64:$Rd),
1118 (v2i32 (opnode (timm:$Imm),
1119 (neon_mov_imm_LSL_operand:$Simm))))],
1122 let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1125 def _4S : NeonI_1VModImm<0b1, op,
1127 (ins neon_uimm8:$Imm,
1128 neon_mov_imm_LSL_operand:$Simm),
1129 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1130 [(set (v4i32 VPR128:$Rd),
1131 (v4i32 (opnode (timm:$Imm),
1132 (neon_mov_imm_LSL_operand:$Simm))))],
1135 let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1138 // shift zeros, per halfword
1139 def _4H : NeonI_1VModImm<0b0, op,
1141 (ins neon_uimm8:$Imm,
1142 neon_mov_imm_LSLH_operand:$Simm),
1143 !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1144 [(set (v4i16 VPR64:$Rd),
1145 (v4i16 (opnode (timm:$Imm),
1146 (neon_mov_imm_LSLH_operand:$Simm))))],
1149 let cmode = {0b1, 0b0, Simm, 0b0};
1152 def _8H : NeonI_1VModImm<0b1, op,
1154 (ins neon_uimm8:$Imm,
1155 neon_mov_imm_LSLH_operand:$Simm),
1156 !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1157 [(set (v8i16 VPR128:$Rd),
1158 (v8i16 (opnode (timm:$Imm),
1159 (neon_mov_imm_LSLH_operand:$Simm))))],
1162 let cmode = {0b1, 0b0, Simm, 0b0};
1166 multiclass NeonI_mov_imm_with_constraint_lsl_sizes<string asmop, bit op,
1167 SDPatternOperator opnode,
1168 SDPatternOperator neonopnode>
1170 let Constraints = "$src = $Rd" in {
1171 // shift zeros, per word
1172 def _2S : NeonI_1VModImm<0b0, op,
1174 (ins VPR64:$src, neon_uimm8:$Imm,
1175 neon_mov_imm_LSL_operand:$Simm),
1176 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1177 [(set (v2i32 VPR64:$Rd),
1178 (v2i32 (opnode (v2i32 VPR64:$src),
1179 (v2i32 (bitconvert (v2i32 (neonopnode timm:$Imm,
1180 neon_mov_imm_LSL_operand:$Simm)))))))],
1183 let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1186 def _4S : NeonI_1VModImm<0b1, op,
1188 (ins VPR128:$src, neon_uimm8:$Imm,
1189 neon_mov_imm_LSL_operand:$Simm),
1190 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1191 [(set (v4i32 VPR128:$Rd),
1192 (v4i32 (opnode (v4i32 VPR128:$src),
1193 (v4i32 (bitconvert (v4i32 (neonopnode timm:$Imm,
1194 neon_mov_imm_LSL_operand:$Simm)))))))],
1197 let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1200 // shift zeros, per halfword
1201 def _4H : NeonI_1VModImm<0b0, op,
1203 (ins VPR64:$src, neon_uimm8:$Imm,
1204 neon_mov_imm_LSLH_operand:$Simm),
1205 !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1206 [(set (v4i16 VPR64:$Rd),
1207 (v4i16 (opnode (v4i16 VPR64:$src),
1208 (v4i16 (bitconvert (v4i16 (neonopnode timm:$Imm,
1209 neon_mov_imm_LSL_operand:$Simm)))))))],
1212 let cmode = {0b1, 0b0, Simm, 0b1};
1215 def _8H : NeonI_1VModImm<0b1, op,
1217 (ins VPR128:$src, neon_uimm8:$Imm,
1218 neon_mov_imm_LSLH_operand:$Simm),
1219 !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1220 [(set (v8i16 VPR128:$Rd),
1221 (v8i16 (opnode (v8i16 VPR128:$src),
1222 (v8i16 (bitconvert (v8i16 (neonopnode timm:$Imm,
1223 neon_mov_imm_LSL_operand:$Simm)))))))],
1226 let cmode = {0b1, 0b0, Simm, 0b1};
1231 multiclass NeonI_mov_imm_msl_sizes<string asmop, bit op,
1232 SDPatternOperator opnode>
1234 // shift ones, per word
1235 def _2S : NeonI_1VModImm<0b0, op,
1237 (ins neon_uimm8:$Imm,
1238 neon_mov_imm_MSL_operand:$Simm),
1239 !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1240 [(set (v2i32 VPR64:$Rd),
1241 (v2i32 (opnode (timm:$Imm),
1242 (neon_mov_imm_MSL_operand:$Simm))))],
1245 let cmode = {0b1, 0b1, 0b0, Simm};
1248 def _4S : NeonI_1VModImm<0b1, op,
1250 (ins neon_uimm8:$Imm,
1251 neon_mov_imm_MSL_operand:$Simm),
1252 !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1253 [(set (v4i32 VPR128:$Rd),
1254 (v4i32 (opnode (timm:$Imm),
1255 (neon_mov_imm_MSL_operand:$Simm))))],
1258 let cmode = {0b1, 0b1, 0b0, Simm};
1262 // Vector Move Immediate Shifted
1263 let isReMaterializable = 1 in {
1264 defm MOVIvi_lsl : NeonI_mov_imm_lsl_sizes<"movi", 0b0, Neon_movi>;
1267 // Vector Move Inverted Immediate Shifted
1268 let isReMaterializable = 1 in {
1269 defm MVNIvi_lsl : NeonI_mov_imm_lsl_sizes<"mvni", 0b1, Neon_mvni>;
1272 // Vector Bitwise Bit Clear (AND NOT) - immediate
1273 let isReMaterializable = 1 in {
1274 defm BICvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"bic", 0b1,
1278 // Vector Bitwise OR - immedidate
1280 let isReMaterializable = 1 in {
1281 defm ORRvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"orr", 0b0,
1285 // Additional patterns for Vector Bitwise Bit Clear (AND NOT) - immedidate
1286 // LowerBUILD_VECTOR favors lowering MOVI over MVNI.
1287 // BIC immediate instructions selection requires additional patterns to
1288 // transform Neon_movi operands into BIC immediate operands
1290 def neon_mov_imm_LSLH_transform_XFORM : SDNodeXForm<imm, [{
1291 uint64_t OpCmode = N->getZExtValue();
1293 unsigned ShiftOnesIn;
1294 (void)A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1295 // LSLH restricts shift amount to 0, 8 which are encoded as 0 and 1
1296 // Transform encoded shift amount 0 to 1 and 1 to 0.
1297 return CurDAG->getTargetConstant(!ShiftImm, MVT::i32);
1300 def neon_mov_imm_LSLH_transform_operand
1303 unsigned ShiftOnesIn;
1305 A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1306 return (HasShift && !ShiftOnesIn); }],
1307 neon_mov_imm_LSLH_transform_XFORM>;
1309 // Transform (and A, (4h Neon_movi 0xff)) -> BIC 4h (A, 0x00, LSL 8)
1310 // Transform (and A, (4h Neon_movi 0xff LSL #8)) -> BIC 4h (A, 0x00)
1311 def : Pat<(v4i16 (and VPR64:$src,
1312 (v4i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1313 (BICvi_lsl_4H VPR64:$src, 0,
1314 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1316 // Transform (and A, (8h Neon_movi 8h 0xff)) -> BIC 8h (A, 0x00, LSL 8)
1317 // Transform (and A, (8h Neon_movi 0xff LSL #8)) -> BIC 8h (A, 0x00)
1318 def : Pat<(v8i16 (and VPR128:$src,
1319 (v8i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1320 (BICvi_lsl_8H VPR128:$src, 0,
1321 neon_mov_imm_LSLH_transform_operand:$Simm)>;
1324 multiclass Neon_bitwiseVi_patterns<SDPatternOperator opnode,
1325 SDPatternOperator neonopnode,
1327 Instruction INST8H> {
1328 def : Pat<(v8i8 (opnode VPR64:$src,
1329 (bitconvert(v4i16 (neonopnode timm:$Imm,
1330 neon_mov_imm_LSLH_operand:$Simm))))),
1331 (INST4H VPR64:$src, neon_uimm8:$Imm,
1332 neon_mov_imm_LSLH_operand:$Simm)>;
1333 def : Pat<(v1i64 (opnode VPR64:$src,
1334 (bitconvert(v4i16 (neonopnode timm:$Imm,
1335 neon_mov_imm_LSLH_operand:$Simm))))),
1336 (INST4H VPR64:$src, neon_uimm8:$Imm,
1337 neon_mov_imm_LSLH_operand:$Simm)>;
1339 def : Pat<(v16i8 (opnode VPR128:$src,
1340 (bitconvert(v8i16 (neonopnode timm:$Imm,
1341 neon_mov_imm_LSLH_operand:$Simm))))),
1342 (INST8H VPR128:$src, neon_uimm8:$Imm,
1343 neon_mov_imm_LSLH_operand:$Simm)>;
1344 def : Pat<(v4i32 (opnode VPR128:$src,
1345 (bitconvert(v8i16 (neonopnode timm:$Imm,
1346 neon_mov_imm_LSLH_operand:$Simm))))),
1347 (INST8H VPR128:$src, neon_uimm8:$Imm,
1348 neon_mov_imm_LSLH_operand:$Simm)>;
1349 def : Pat<(v2i64 (opnode VPR128:$src,
1350 (bitconvert(v8i16 (neonopnode timm:$Imm,
1351 neon_mov_imm_LSLH_operand:$Simm))))),
1352 (INST8H VPR128:$src, neon_uimm8:$Imm,
1353 neon_mov_imm_LSLH_operand:$Simm)>;
1356 // Additional patterns for Vector Vector Bitwise Bit Clear (AND NOT) - immediate
1357 defm : Neon_bitwiseVi_patterns<or, Neon_mvni, BICvi_lsl_4H, BICvi_lsl_8H>;
1359 // Additional patterns for Vector Bitwise OR - immedidate
1360 defm : Neon_bitwiseVi_patterns<or, Neon_movi, ORRvi_lsl_4H, ORRvi_lsl_8H>;
1363 // Vector Move Immediate Masked
1364 let isReMaterializable = 1 in {
1365 defm MOVIvi_msl : NeonI_mov_imm_msl_sizes<"movi", 0b0, Neon_movi>;
1368 // Vector Move Inverted Immediate Masked
1369 let isReMaterializable = 1 in {
1370 defm MVNIvi_msl : NeonI_mov_imm_msl_sizes<"mvni", 0b1, Neon_mvni>;
1373 class NeonI_mov_imm_lsl_aliases<string asmop, string asmlane,
1374 Instruction inst, RegisterOperand VPRC>
1375 : NeonInstAlias<!strconcat(asmop, "\t$Rd," # asmlane # ", $Imm"),
1376 (inst VPRC:$Rd, neon_uimm8:$Imm, 0), 0b0>;
1378 // Aliases for Vector Move Immediate Shifted
1379 def : NeonI_mov_imm_lsl_aliases<"movi", ".2s", MOVIvi_lsl_2S, VPR64>;
1380 def : NeonI_mov_imm_lsl_aliases<"movi", ".4s", MOVIvi_lsl_4S, VPR128>;
1381 def : NeonI_mov_imm_lsl_aliases<"movi", ".4h", MOVIvi_lsl_4H, VPR64>;
1382 def : NeonI_mov_imm_lsl_aliases<"movi", ".8h", MOVIvi_lsl_8H, VPR128>;
1384 // Aliases for Vector Move Inverted Immediate Shifted
1385 def : NeonI_mov_imm_lsl_aliases<"mvni", ".2s", MVNIvi_lsl_2S, VPR64>;
1386 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4s", MVNIvi_lsl_4S, VPR128>;
1387 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4h", MVNIvi_lsl_4H, VPR64>;
1388 def : NeonI_mov_imm_lsl_aliases<"mvni", ".8h", MVNIvi_lsl_8H, VPR128>;
1390 // Aliases for Vector Bitwise Bit Clear (AND NOT) - immediate
1391 def : NeonI_mov_imm_lsl_aliases<"bic", ".2s", BICvi_lsl_2S, VPR64>;
1392 def : NeonI_mov_imm_lsl_aliases<"bic", ".4s", BICvi_lsl_4S, VPR128>;
1393 def : NeonI_mov_imm_lsl_aliases<"bic", ".4h", BICvi_lsl_4H, VPR64>;
1394 def : NeonI_mov_imm_lsl_aliases<"bic", ".8h", BICvi_lsl_8H, VPR128>;
1396 // Aliases for Vector Bitwise OR - immedidate
1397 def : NeonI_mov_imm_lsl_aliases<"orr", ".2s", ORRvi_lsl_2S, VPR64>;
1398 def : NeonI_mov_imm_lsl_aliases<"orr", ".4s", ORRvi_lsl_4S, VPR128>;
1399 def : NeonI_mov_imm_lsl_aliases<"orr", ".4h", ORRvi_lsl_4H, VPR64>;
1400 def : NeonI_mov_imm_lsl_aliases<"orr", ".8h", ORRvi_lsl_8H, VPR128>;
1402 // Vector Move Immediate - per byte
1403 let isReMaterializable = 1 in {
1404 def MOVIvi_8B : NeonI_1VModImm<0b0, 0b0,
1405 (outs VPR64:$Rd), (ins neon_uimm8:$Imm),
1406 "movi\t$Rd.8b, $Imm",
1407 [(set (v8i8 VPR64:$Rd),
1408 (v8i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1413 def MOVIvi_16B : NeonI_1VModImm<0b1, 0b0,
1414 (outs VPR128:$Rd), (ins neon_uimm8:$Imm),
1415 "movi\t$Rd.16b, $Imm",
1416 [(set (v16i8 VPR128:$Rd),
1417 (v16i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1423 // Vector Move Immediate - bytemask, per double word
1424 let isReMaterializable = 1 in {
1425 def MOVIvi_2D : NeonI_1VModImm<0b1, 0b1,
1426 (outs VPR128:$Rd), (ins neon_uimm64_mask:$Imm),
1427 "movi\t $Rd.2d, $Imm",
1428 [(set (v2i64 VPR128:$Rd),
1429 (v2i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1435 // Vector Move Immediate - bytemask, one doubleword
1437 let isReMaterializable = 1 in {
1438 def MOVIdi : NeonI_1VModImm<0b0, 0b1,
1439 (outs FPR64:$Rd), (ins neon_uimm64_mask:$Imm),
1441 [(set (v1i64 FPR64:$Rd),
1442 (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1448 // Vector Floating Point Move Immediate
1450 class NeonI_FMOV_impl<string asmlane, RegisterOperand VPRC, ValueType OpTy,
1451 Operand immOpType, bit q, bit op>
1452 : NeonI_1VModImm<q, op,
1453 (outs VPRC:$Rd), (ins immOpType:$Imm),
1454 "fmov\t$Rd" # asmlane # ", $Imm",
1455 [(set (OpTy VPRC:$Rd),
1456 (OpTy (Neon_fmovi (timm:$Imm))))],
1461 let isReMaterializable = 1 in {
1462 def FMOVvi_2S : NeonI_FMOV_impl<".2s", VPR64, v2f32, fmov32_operand, 0b0, 0b0>;
1463 def FMOVvi_4S : NeonI_FMOV_impl<".4s", VPR128, v4f32, fmov32_operand, 0b1, 0b0>;
1464 def FMOVvi_2D : NeonI_FMOV_impl<".2d", VPR128, v2f64, fmov64_operand, 0b1, 0b1>;
1467 // Vector Shift (Immediate)
1468 // Immediate in [0, 63]
1469 def imm0_63 : Operand<i32> {
1470 let ParserMatchClass = uimm6_asmoperand;
1473 // Shift Right/Left Immediate - The immh:immb field of these shifts are encoded
1477 // 8 immh:immb<6:3> = '0001xxx', <imm> is encoded in immh:immb<2:0>
1478 // 16 immh:immb<6:4> = '001xxxx', <imm> is encoded in immh:immb<3:0>
1479 // 32 immh:immb<6:5> = '01xxxxx', <imm> is encoded in immh:immb<4:0>
1480 // 64 immh:immb<6> = '1xxxxxx', <imm> is encoded in immh:immb<5:0>
1482 // The shift right immediate amount, in the range 1 to element bits, is computed
1483 // as Offset - UInt(immh:immb). The shift left immediate amount, in the range 0
1484 // to element bits - 1, is computed as UInt(immh:immb) - Offset.
1486 class shr_imm_asmoperands<string OFFSET> : AsmOperandClass {
1487 let Name = "ShrImm" # OFFSET;
1488 let RenderMethod = "addImmOperands";
1489 let DiagnosticType = "ShrImm" # OFFSET;
1492 class shr_imm<string OFFSET> : Operand<i32> {
1493 let EncoderMethod = "getShiftRightImm" # OFFSET;
1494 let DecoderMethod = "DecodeShiftRightImm" # OFFSET;
1495 let ParserMatchClass =
1496 !cast<AsmOperandClass>("shr_imm" # OFFSET # "_asmoperand");
1499 def shr_imm8_asmoperand : shr_imm_asmoperands<"8">;
1500 def shr_imm16_asmoperand : shr_imm_asmoperands<"16">;
1501 def shr_imm32_asmoperand : shr_imm_asmoperands<"32">;
1502 def shr_imm64_asmoperand : shr_imm_asmoperands<"64">;
1504 def shr_imm8 : shr_imm<"8">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 8;}]>;
1505 def shr_imm16 : shr_imm<"16">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 16;}]>;
1506 def shr_imm32 : shr_imm<"32">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 32;}]>;
1507 def shr_imm64 : shr_imm<"64">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 64;}]>;
1509 class shl_imm_asmoperands<string OFFSET> : AsmOperandClass {
1510 let Name = "ShlImm" # OFFSET;
1511 let RenderMethod = "addImmOperands";
1512 let DiagnosticType = "ShlImm" # OFFSET;
1515 class shl_imm<string OFFSET> : Operand<i32> {
1516 let EncoderMethod = "getShiftLeftImm" # OFFSET;
1517 let DecoderMethod = "DecodeShiftLeftImm" # OFFSET;
1518 let ParserMatchClass =
1519 !cast<AsmOperandClass>("shl_imm" # OFFSET # "_asmoperand");
1522 def shl_imm8_asmoperand : shl_imm_asmoperands<"8">;
1523 def shl_imm16_asmoperand : shl_imm_asmoperands<"16">;
1524 def shl_imm32_asmoperand : shl_imm_asmoperands<"32">;
1525 def shl_imm64_asmoperand : shl_imm_asmoperands<"64">;
1527 def shl_imm8 : shl_imm<"8">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 8;}]>;
1528 def shl_imm16 : shl_imm<"16">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 16;}]>;
1529 def shl_imm32 : shl_imm<"32">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 32;}]>;
1530 def shl_imm64 : shl_imm<"64">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 64;}]>;
1532 class N2VShift<bit q, bit u, bits<5> opcode, string asmop, string T,
1533 RegisterOperand VPRC, ValueType Ty, Operand ImmTy, SDNode OpNode>
1534 : NeonI_2VShiftImm<q, u, opcode,
1535 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1536 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1537 [(set (Ty VPRC:$Rd),
1538 (Ty (OpNode (Ty VPRC:$Rn),
1539 (Ty (Neon_vdup (i32 ImmTy:$Imm))))))],
1542 multiclass NeonI_N2VShL<bit u, bits<5> opcode, string asmop> {
1543 // 64-bit vector types.
1544 def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8, shl> {
1545 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1548 def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16, shl> {
1549 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1552 def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32, shl> {
1553 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1556 // 128-bit vector types.
1557 def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8, shl> {
1558 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1561 def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16, shl> {
1562 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1565 def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32, shl> {
1566 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1569 def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64, shl> {
1570 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
1574 multiclass NeonI_N2VShR<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1575 def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1577 let Inst{22-19} = 0b0001;
1580 def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1582 let Inst{22-20} = 0b001;
1585 def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1587 let Inst{22-21} = 0b01;
1590 def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1592 let Inst{22-19} = 0b0001;
1595 def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1597 let Inst{22-20} = 0b001;
1600 def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1602 let Inst{22-21} = 0b01;
1605 def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1612 defm SHLvvi : NeonI_N2VShL<0b0, 0b01010, "shl">;
1615 defm SSHRvvi : NeonI_N2VShR<0b0, 0b00000, "sshr", sra>;
1616 defm USHRvvi : NeonI_N2VShR<0b1, 0b00000, "ushr", srl>;
1618 def Neon_High16B : PatFrag<(ops node:$in),
1619 (extract_subvector (v16i8 node:$in), (iPTR 8))>;
1620 def Neon_High8H : PatFrag<(ops node:$in),
1621 (extract_subvector (v8i16 node:$in), (iPTR 4))>;
1622 def Neon_High4S : PatFrag<(ops node:$in),
1623 (extract_subvector (v4i32 node:$in), (iPTR 2))>;
1624 def Neon_High2D : PatFrag<(ops node:$in),
1625 (extract_subvector (v2i64 node:$in), (iPTR 1))>;
1626 def Neon_High4float : PatFrag<(ops node:$in),
1627 (extract_subvector (v4f32 node:$in), (iPTR 2))>;
1628 def Neon_High2double : PatFrag<(ops node:$in),
1629 (extract_subvector (v2f64 node:$in), (iPTR 1))>;
1631 def Neon_Low16B : PatFrag<(ops node:$in),
1632 (v8i8 (extract_subvector (v16i8 node:$in),
1634 def Neon_Low8H : PatFrag<(ops node:$in),
1635 (v4i16 (extract_subvector (v8i16 node:$in),
1637 def Neon_Low4S : PatFrag<(ops node:$in),
1638 (v2i32 (extract_subvector (v4i32 node:$in),
1640 def Neon_Low2D : PatFrag<(ops node:$in),
1641 (v1i64 (extract_subvector (v2i64 node:$in),
1643 def Neon_Low4float : PatFrag<(ops node:$in),
1644 (v2f32 (extract_subvector (v4f32 node:$in),
1646 def Neon_Low2double : PatFrag<(ops node:$in),
1647 (v1f64 (extract_subvector (v2f64 node:$in),
1650 class N2VShiftLong<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1651 string SrcT, ValueType DestTy, ValueType SrcTy,
1652 Operand ImmTy, SDPatternOperator ExtOp>
1653 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1654 (ins VPR64:$Rn, ImmTy:$Imm),
1655 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1656 [(set (DestTy VPR128:$Rd),
1658 (DestTy (ExtOp (SrcTy VPR64:$Rn))),
1659 (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1662 class N2VShiftLongHigh<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1663 string SrcT, ValueType DestTy, ValueType SrcTy,
1664 int StartIndex, Operand ImmTy,
1665 SDPatternOperator ExtOp, PatFrag getTop>
1666 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1667 (ins VPR128:$Rn, ImmTy:$Imm),
1668 asmop # "2\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1669 [(set (DestTy VPR128:$Rd),
1672 (SrcTy (getTop VPR128:$Rn)))),
1673 (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1676 multiclass NeonI_N2VShLL<string prefix, bit u, bits<5> opcode, string asmop,
1678 // 64-bit vector types.
1679 def _8B : N2VShiftLong<0b0, u, opcode, asmop, "8h", "8b", v8i16, v8i8,
1681 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1684 def _4H : N2VShiftLong<0b0, u, opcode, asmop, "4s", "4h", v4i32, v4i16,
1686 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1689 def _2S : N2VShiftLong<0b0, u, opcode, asmop, "2d", "2s", v2i64, v2i32,
1691 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1694 // 128-bit vector types
1695 def _16B : N2VShiftLongHigh<0b1, u, opcode, asmop, "8h", "16b", v8i16, v8i8,
1696 8, shl_imm8, ExtOp, Neon_High16B> {
1697 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
1700 def _8H : N2VShiftLongHigh<0b1, u, opcode, asmop, "4s", "8h", v4i32, v4i16,
1701 4, shl_imm16, ExtOp, Neon_High8H> {
1702 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
1705 def _4S : N2VShiftLongHigh<0b1, u, opcode, asmop, "2d", "4s", v2i64, v2i32,
1706 2, shl_imm32, ExtOp, Neon_High4S> {
1707 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
1710 // Use other patterns to match when the immediate is 0.
1711 def : Pat<(v8i16 (ExtOp (v8i8 VPR64:$Rn))),
1712 (!cast<Instruction>(prefix # "_8B") VPR64:$Rn, 0)>;
1714 def : Pat<(v4i32 (ExtOp (v4i16 VPR64:$Rn))),
1715 (!cast<Instruction>(prefix # "_4H") VPR64:$Rn, 0)>;
1717 def : Pat<(v2i64 (ExtOp (v2i32 VPR64:$Rn))),
1718 (!cast<Instruction>(prefix # "_2S") VPR64:$Rn, 0)>;
1720 def : Pat<(v8i16 (ExtOp (v8i8 (Neon_High16B VPR128:$Rn)))),
1721 (!cast<Instruction>(prefix # "_16B") VPR128:$Rn, 0)>;
1723 def : Pat<(v4i32 (ExtOp (v4i16 (Neon_High8H VPR128:$Rn)))),
1724 (!cast<Instruction>(prefix # "_8H") VPR128:$Rn, 0)>;
1726 def : Pat<(v2i64 (ExtOp (v2i32 (Neon_High4S VPR128:$Rn)))),
1727 (!cast<Instruction>(prefix # "_4S") VPR128:$Rn, 0)>;
1731 defm SSHLLvvi : NeonI_N2VShLL<"SSHLLvvi", 0b0, 0b10100, "sshll", sext>;
1732 defm USHLLvvi : NeonI_N2VShLL<"USHLLvvi", 0b1, 0b10100, "ushll", zext>;
1734 // Rounding/Saturating shift
1735 class N2VShift_RQ<bit q, bit u, bits<5> opcode, string asmop, string T,
1736 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1737 SDPatternOperator OpNode>
1738 : NeonI_2VShiftImm<q, u, opcode,
1739 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1740 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1741 [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$Rn),
1742 (i32 ImmTy:$Imm))))],
1745 // shift right (vector by immediate)
1746 multiclass NeonI_N2VShR_RQ<bit u, bits<5> opcode, string asmop,
1747 SDPatternOperator OpNode> {
1748 def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1750 let Inst{22-19} = 0b0001;
1753 def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1755 let Inst{22-20} = 0b001;
1758 def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1760 let Inst{22-21} = 0b01;
1763 def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1765 let Inst{22-19} = 0b0001;
1768 def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1770 let Inst{22-20} = 0b001;
1773 def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1775 let Inst{22-21} = 0b01;
1778 def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1784 multiclass NeonI_N2VShL_Q<bit u, bits<5> opcode, string asmop,
1785 SDPatternOperator OpNode> {
1786 // 64-bit vector types.
1787 def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
1789 let Inst{22-19} = 0b0001;
1792 def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
1794 let Inst{22-20} = 0b001;
1797 def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
1799 let Inst{22-21} = 0b01;
1802 // 128-bit vector types.
1803 def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
1805 let Inst{22-19} = 0b0001;
1808 def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
1810 let Inst{22-20} = 0b001;
1813 def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
1815 let Inst{22-21} = 0b01;
1818 def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
1824 // Rounding shift right
1825 defm SRSHRvvi : NeonI_N2VShR_RQ<0b0, 0b00100, "srshr",
1826 int_aarch64_neon_vsrshr>;
1827 defm URSHRvvi : NeonI_N2VShR_RQ<0b1, 0b00100, "urshr",
1828 int_aarch64_neon_vurshr>;
1830 // Saturating shift left unsigned
1831 defm SQSHLUvvi : NeonI_N2VShL_Q<0b1, 0b01100, "sqshlu", int_aarch64_neon_vsqshlu>;
1833 // Saturating shift left
1834 defm SQSHLvvi : NeonI_N2VShL_Q<0b0, 0b01110, "sqshl", Neon_sqrshlImm>;
1835 defm UQSHLvvi : NeonI_N2VShL_Q<0b1, 0b01110, "uqshl", Neon_uqrshlImm>;
1837 class N2VShiftAdd<bit q, bit u, bits<5> opcode, string asmop, string T,
1838 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1840 : NeonI_2VShiftImm<q, u, opcode,
1841 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1842 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1843 [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1844 (Ty (OpNode (Ty VPRC:$Rn),
1845 (Ty (Neon_vdup (i32 ImmTy:$Imm))))))))],
1847 let Constraints = "$src = $Rd";
1850 // Shift Right accumulate
1851 multiclass NeonI_N2VShRAdd<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1852 def _8B : N2VShiftAdd<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1854 let Inst{22-19} = 0b0001;
1857 def _4H : N2VShiftAdd<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1859 let Inst{22-20} = 0b001;
1862 def _2S : N2VShiftAdd<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1864 let Inst{22-21} = 0b01;
1867 def _16B : N2VShiftAdd<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1869 let Inst{22-19} = 0b0001;
1872 def _8H : N2VShiftAdd<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1874 let Inst{22-20} = 0b001;
1877 def _4S : N2VShiftAdd<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1879 let Inst{22-21} = 0b01;
1882 def _2D : N2VShiftAdd<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1888 // Shift right and accumulate
1889 defm SSRAvvi : NeonI_N2VShRAdd<0, 0b00010, "ssra", sra>;
1890 defm USRAvvi : NeonI_N2VShRAdd<1, 0b00010, "usra", srl>;
1892 // Rounding shift accumulate
1893 class N2VShiftAdd_R<bit q, bit u, bits<5> opcode, string asmop, string T,
1894 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1895 SDPatternOperator OpNode>
1896 : NeonI_2VShiftImm<q, u, opcode,
1897 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1898 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1899 [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1900 (Ty (OpNode (Ty VPRC:$Rn), (i32 ImmTy:$Imm))))))],
1902 let Constraints = "$src = $Rd";
1905 multiclass NeonI_N2VShRAdd_R<bit u, bits<5> opcode, string asmop,
1906 SDPatternOperator OpNode> {
1907 def _8B : N2VShiftAdd_R<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1909 let Inst{22-19} = 0b0001;
1912 def _4H : N2VShiftAdd_R<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1914 let Inst{22-20} = 0b001;
1917 def _2S : N2VShiftAdd_R<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1919 let Inst{22-21} = 0b01;
1922 def _16B : N2VShiftAdd_R<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1924 let Inst{22-19} = 0b0001;
1927 def _8H : N2VShiftAdd_R<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1929 let Inst{22-20} = 0b001;
1932 def _4S : N2VShiftAdd_R<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1934 let Inst{22-21} = 0b01;
1937 def _2D : N2VShiftAdd_R<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1943 // Rounding shift right and accumulate
1944 defm SRSRAvvi : NeonI_N2VShRAdd_R<0, 0b00110, "srsra", int_aarch64_neon_vsrshr>;
1945 defm URSRAvvi : NeonI_N2VShRAdd_R<1, 0b00110, "ursra", int_aarch64_neon_vurshr>;
1947 // Shift insert by immediate
1948 class N2VShiftIns<bit q, bit u, bits<5> opcode, string asmop, string T,
1949 RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1950 SDPatternOperator OpNode>
1951 : NeonI_2VShiftImm<q, u, opcode,
1952 (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1953 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1954 [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$src), (Ty VPRC:$Rn),
1955 (i32 ImmTy:$Imm))))],
1957 let Constraints = "$src = $Rd";
1960 // shift left insert (vector by immediate)
1961 multiclass NeonI_N2VShLIns<bit u, bits<5> opcode, string asmop> {
1962 def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
1963 int_aarch64_neon_vsli> {
1964 let Inst{22-19} = 0b0001;
1967 def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
1968 int_aarch64_neon_vsli> {
1969 let Inst{22-20} = 0b001;
1972 def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
1973 int_aarch64_neon_vsli> {
1974 let Inst{22-21} = 0b01;
1977 // 128-bit vector types
1978 def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
1979 int_aarch64_neon_vsli> {
1980 let Inst{22-19} = 0b0001;
1983 def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
1984 int_aarch64_neon_vsli> {
1985 let Inst{22-20} = 0b001;
1988 def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
1989 int_aarch64_neon_vsli> {
1990 let Inst{22-21} = 0b01;
1993 def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
1994 int_aarch64_neon_vsli> {
1999 // shift right insert (vector by immediate)
2000 multiclass NeonI_N2VShRIns<bit u, bits<5> opcode, string asmop> {
2001 // 64-bit vector types.
2002 def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
2003 int_aarch64_neon_vsri> {
2004 let Inst{22-19} = 0b0001;
2007 def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
2008 int_aarch64_neon_vsri> {
2009 let Inst{22-20} = 0b001;
2012 def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
2013 int_aarch64_neon_vsri> {
2014 let Inst{22-21} = 0b01;
2017 // 128-bit vector types
2018 def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2019 int_aarch64_neon_vsri> {
2020 let Inst{22-19} = 0b0001;
2023 def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2024 int_aarch64_neon_vsri> {
2025 let Inst{22-20} = 0b001;
2028 def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2029 int_aarch64_neon_vsri> {
2030 let Inst{22-21} = 0b01;
2033 def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2034 int_aarch64_neon_vsri> {
2039 // Shift left and insert
2040 defm SLIvvi : NeonI_N2VShLIns<0b1, 0b01010, "sli">;
2042 // Shift right and insert
2043 defm SRIvvi : NeonI_N2VShRIns<0b1, 0b01000, "sri">;
2045 class N2VShR_Narrow<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2046 string SrcT, Operand ImmTy>
2047 : NeonI_2VShiftImm<q, u, opcode,
2048 (outs VPR64:$Rd), (ins VPR128:$Rn, ImmTy:$Imm),
2049 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2052 class N2VShR_Narrow_Hi<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2053 string SrcT, Operand ImmTy>
2054 : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
2055 (ins VPR128:$src, VPR128:$Rn, ImmTy:$Imm),
2056 asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2058 let Constraints = "$src = $Rd";
2061 // left long shift by immediate
2062 multiclass NeonI_N2VShR_Narrow<bit u, bits<5> opcode, string asmop> {
2063 def _8B : N2VShR_Narrow<0b0, u, opcode, asmop, "8b", "8h", shr_imm8> {
2064 let Inst{22-19} = 0b0001;
2067 def _4H : N2VShR_Narrow<0b0, u, opcode, asmop, "4h", "4s", shr_imm16> {
2068 let Inst{22-20} = 0b001;
2071 def _2S : N2VShR_Narrow<0b0, u, opcode, asmop, "2s", "2d", shr_imm32> {
2072 let Inst{22-21} = 0b01;
2075 // Shift Narrow High
2076 def _16B : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "16b", "8h",
2078 let Inst{22-19} = 0b0001;
2081 def _8H : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "8h", "4s",
2083 let Inst{22-20} = 0b001;
2086 def _4S : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "4s", "2d",
2088 let Inst{22-21} = 0b01;
2092 // Shift right narrow
2093 defm SHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10000, "shrn">;
2095 // Shift right narrow (prefix Q is saturating, prefix R is rounding)
2096 defm QSHRUNvvi :NeonI_N2VShR_Narrow<0b1, 0b10000, "sqshrun">;
2097 defm RSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10001, "rshrn">;
2098 defm QRSHRUNvvi : NeonI_N2VShR_Narrow<0b1, 0b10001, "sqrshrun">;
2099 defm SQSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10010, "sqshrn">;
2100 defm UQSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10010, "uqshrn">;
2101 defm SQRSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10011, "sqrshrn">;
2102 defm UQRSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10011, "uqrshrn">;
2104 def Neon_combine_2D : PatFrag<(ops node:$Rm, node:$Rn),
2105 (v2i64 (concat_vectors (v1i64 node:$Rm),
2106 (v1i64 node:$Rn)))>;
2107 def Neon_combine_8H : PatFrag<(ops node:$Rm, node:$Rn),
2108 (v8i16 (concat_vectors (v4i16 node:$Rm),
2109 (v4i16 node:$Rn)))>;
2110 def Neon_combine_4S : PatFrag<(ops node:$Rm, node:$Rn),
2111 (v4i32 (concat_vectors (v2i32 node:$Rm),
2112 (v2i32 node:$Rn)))>;
2113 def Neon_combine_4f : PatFrag<(ops node:$Rm, node:$Rn),
2114 (v4f32 (concat_vectors (v2f32 node:$Rm),
2115 (v2f32 node:$Rn)))>;
2116 def Neon_combine_2d : PatFrag<(ops node:$Rm, node:$Rn),
2117 (v2f64 (concat_vectors (v1f64 node:$Rm),
2118 (v1f64 node:$Rn)))>;
2120 def Neon_lshrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2121 (v8i16 (srl (v8i16 node:$lhs),
2122 (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2123 def Neon_lshrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2124 (v4i32 (srl (v4i32 node:$lhs),
2125 (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2126 def Neon_lshrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2127 (v2i64 (srl (v2i64 node:$lhs),
2128 (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2129 def Neon_ashrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2130 (v8i16 (sra (v8i16 node:$lhs),
2131 (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2132 def Neon_ashrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2133 (v4i32 (sra (v4i32 node:$lhs),
2134 (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2135 def Neon_ashrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2136 (v2i64 (sra (v2i64 node:$lhs),
2137 (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2139 // Normal shift right narrow is matched by IR (srl/sra, trunc, concat_vectors)
2140 multiclass Neon_shiftNarrow_patterns<string shr> {
2141 def : Pat<(v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H") VPR128:$Rn,
2142 (i32 shr_imm8:$Imm)))),
2143 (SHRNvvi_8B VPR128:$Rn, imm:$Imm)>;
2144 def : Pat<(v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S") VPR128:$Rn,
2145 (i32 shr_imm16:$Imm)))),
2146 (SHRNvvi_4H VPR128:$Rn, imm:$Imm)>;
2147 def : Pat<(v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D") VPR128:$Rn,
2148 (i32 shr_imm32:$Imm)))),
2149 (SHRNvvi_2S VPR128:$Rn, imm:$Imm)>;
2151 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2152 (v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H")
2153 VPR128:$Rn, (i32 shr_imm8:$Imm))))))),
2154 (SHRNvvi_16B (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
2155 VPR128:$Rn, imm:$Imm)>;
2156 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2157 (v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S")
2158 VPR128:$Rn, (i32 shr_imm16:$Imm))))))),
2159 (SHRNvvi_8H (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2160 VPR128:$Rn, imm:$Imm)>;
2161 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2162 (v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D")
2163 VPR128:$Rn, (i32 shr_imm32:$Imm))))))),
2164 (SHRNvvi_4S (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2165 VPR128:$Rn, imm:$Imm)>;
2168 multiclass Neon_shiftNarrow_QR_patterns<SDPatternOperator op, string prefix> {
2169 def : Pat<(v8i8 (op (v8i16 VPR128:$Rn), shr_imm8:$Imm)),
2170 (!cast<Instruction>(prefix # "_8B") VPR128:$Rn, imm:$Imm)>;
2171 def : Pat<(v4i16 (op (v4i32 VPR128:$Rn), shr_imm16:$Imm)),
2172 (!cast<Instruction>(prefix # "_4H") VPR128:$Rn, imm:$Imm)>;
2173 def : Pat<(v2i32 (op (v2i64 VPR128:$Rn), shr_imm32:$Imm)),
2174 (!cast<Instruction>(prefix # "_2S") VPR128:$Rn, imm:$Imm)>;
2176 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2177 (v1i64 (bitconvert (v8i8
2178 (op (v8i16 VPR128:$Rn), shr_imm8:$Imm))))),
2179 (!cast<Instruction>(prefix # "_16B")
2180 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2181 VPR128:$Rn, imm:$Imm)>;
2182 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2183 (v1i64 (bitconvert (v4i16
2184 (op (v4i32 VPR128:$Rn), shr_imm16:$Imm))))),
2185 (!cast<Instruction>(prefix # "_8H")
2186 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2187 VPR128:$Rn, imm:$Imm)>;
2188 def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2189 (v1i64 (bitconvert (v2i32
2190 (op (v2i64 VPR128:$Rn), shr_imm32:$Imm))))),
2191 (!cast<Instruction>(prefix # "_4S")
2192 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2193 VPR128:$Rn, imm:$Imm)>;
2196 defm : Neon_shiftNarrow_patterns<"lshr">;
2197 defm : Neon_shiftNarrow_patterns<"ashr">;
2199 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrun, "QSHRUNvvi">;
2200 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vrshrn, "RSHRNvvi">;
2201 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrun, "QRSHRUNvvi">;
2202 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrn, "SQSHRNvvi">;
2203 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqshrn, "UQSHRNvvi">;
2204 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrn, "SQRSHRNvvi">;
2205 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqrshrn, "UQRSHRNvvi">;
2207 // Convert fix-point and float-pointing
2208 class N2VCvt_Fx<bit q, bit u, bits<5> opcode, string asmop, string T,
2209 RegisterOperand VPRC, ValueType DestTy, ValueType SrcTy,
2210 Operand ImmTy, SDPatternOperator IntOp>
2211 : NeonI_2VShiftImm<q, u, opcode,
2212 (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
2213 asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2214 [(set (DestTy VPRC:$Rd), (DestTy (IntOp (SrcTy VPRC:$Rn),
2215 (i32 ImmTy:$Imm))))],
2218 multiclass NeonI_N2VCvt_Fx2fp<bit u, bits<5> opcode, string asmop,
2219 SDPatternOperator IntOp> {
2220 def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2f32, v2i32,
2222 let Inst{22-21} = 0b01;
2225 def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4f32, v4i32,
2227 let Inst{22-21} = 0b01;
2230 def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2f64, v2i64,
2236 multiclass NeonI_N2VCvt_Fp2fx<bit u, bits<5> opcode, string asmop,
2237 SDPatternOperator IntOp> {
2238 def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2i32, v2f32,
2240 let Inst{22-21} = 0b01;
2243 def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4i32, v4f32,
2245 let Inst{22-21} = 0b01;
2248 def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2i64, v2f64,
2254 // Convert fixed-point to floating-point
2255 defm VCVTxs2f : NeonI_N2VCvt_Fx2fp<0, 0b11100, "scvtf",
2256 int_arm_neon_vcvtfxs2fp>;
2257 defm VCVTxu2f : NeonI_N2VCvt_Fx2fp<1, 0b11100, "ucvtf",
2258 int_arm_neon_vcvtfxu2fp>;
2260 // Convert floating-point to fixed-point
2261 defm VCVTf2xs : NeonI_N2VCvt_Fp2fx<0, 0b11111, "fcvtzs",
2262 int_arm_neon_vcvtfp2fxs>;
2263 defm VCVTf2xu : NeonI_N2VCvt_Fp2fx<1, 0b11111, "fcvtzu",
2264 int_arm_neon_vcvtfp2fxu>;
2266 multiclass Neon_sshll2_0<SDNode ext>
2268 def _v8i8 : PatFrag<(ops node:$Rn),
2269 (v8i16 (ext (v8i8 (Neon_High16B node:$Rn))))>;
2270 def _v4i16 : PatFrag<(ops node:$Rn),
2271 (v4i32 (ext (v4i16 (Neon_High8H node:$Rn))))>;
2272 def _v2i32 : PatFrag<(ops node:$Rn),
2273 (v2i64 (ext (v2i32 (Neon_High4S node:$Rn))))>;
2276 defm NI_sext_high : Neon_sshll2_0<sext>;
2277 defm NI_zext_high : Neon_sshll2_0<zext>;
2280 //===----------------------------------------------------------------------===//
2281 // Multiclasses for NeonI_Across
2282 //===----------------------------------------------------------------------===//
2286 multiclass NeonI_2VAcross_1<bit u, bits<5> opcode,
2287 string asmop, SDPatternOperator opnode>
2289 def _1h8b: NeonI_2VAcross<0b0, u, 0b00, opcode,
2290 (outs FPR16:$Rd), (ins VPR64:$Rn),
2291 asmop # "\t$Rd, $Rn.8b",
2292 [(set (v1i16 FPR16:$Rd),
2293 (v1i16 (opnode (v8i8 VPR64:$Rn))))],
2296 def _1h16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2297 (outs FPR16:$Rd), (ins VPR128:$Rn),
2298 asmop # "\t$Rd, $Rn.16b",
2299 [(set (v1i16 FPR16:$Rd),
2300 (v1i16 (opnode (v16i8 VPR128:$Rn))))],
2303 def _1s4h: NeonI_2VAcross<0b0, u, 0b01, opcode,
2304 (outs FPR32:$Rd), (ins VPR64:$Rn),
2305 asmop # "\t$Rd, $Rn.4h",
2306 [(set (v1i32 FPR32:$Rd),
2307 (v1i32 (opnode (v4i16 VPR64:$Rn))))],
2310 def _1s8h: NeonI_2VAcross<0b1, u, 0b01, opcode,
2311 (outs FPR32:$Rd), (ins VPR128:$Rn),
2312 asmop # "\t$Rd, $Rn.8h",
2313 [(set (v1i32 FPR32:$Rd),
2314 (v1i32 (opnode (v8i16 VPR128:$Rn))))],
2317 // _1d2s doesn't exist!
2319 def _1d4s: NeonI_2VAcross<0b1, u, 0b10, opcode,
2320 (outs FPR64:$Rd), (ins VPR128:$Rn),
2321 asmop # "\t$Rd, $Rn.4s",
2322 [(set (v1i64 FPR64:$Rd),
2323 (v1i64 (opnode (v4i32 VPR128:$Rn))))],
2327 defm SADDLV : NeonI_2VAcross_1<0b0, 0b00011, "saddlv", int_aarch64_neon_saddlv>;
2328 defm UADDLV : NeonI_2VAcross_1<0b1, 0b00011, "uaddlv", int_aarch64_neon_uaddlv>;
2332 multiclass NeonI_2VAcross_2<bit u, bits<5> opcode,
2333 string asmop, SDPatternOperator opnode>
2335 def _1b8b: NeonI_2VAcross<0b0, u, 0b00, opcode,
2336 (outs FPR8:$Rd), (ins VPR64:$Rn),
2337 asmop # "\t$Rd, $Rn.8b",
2338 [(set (v1i8 FPR8:$Rd),
2339 (v1i8 (opnode (v8i8 VPR64:$Rn))))],
2342 def _1b16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2343 (outs FPR8:$Rd), (ins VPR128:$Rn),
2344 asmop # "\t$Rd, $Rn.16b",
2345 [(set (v1i8 FPR8:$Rd),
2346 (v1i8 (opnode (v16i8 VPR128:$Rn))))],
2349 def _1h4h: NeonI_2VAcross<0b0, u, 0b01, opcode,
2350 (outs FPR16:$Rd), (ins VPR64:$Rn),
2351 asmop # "\t$Rd, $Rn.4h",
2352 [(set (v1i16 FPR16:$Rd),
2353 (v1i16 (opnode (v4i16 VPR64:$Rn))))],
2356 def _1h8h: NeonI_2VAcross<0b1, u, 0b01, opcode,
2357 (outs FPR16:$Rd), (ins VPR128:$Rn),
2358 asmop # "\t$Rd, $Rn.8h",
2359 [(set (v1i16 FPR16:$Rd),
2360 (v1i16 (opnode (v8i16 VPR128:$Rn))))],
2363 // _1s2s doesn't exist!
2365 def _1s4s: NeonI_2VAcross<0b1, u, 0b10, opcode,
2366 (outs FPR32:$Rd), (ins VPR128:$Rn),
2367 asmop # "\t$Rd, $Rn.4s",
2368 [(set (v1i32 FPR32:$Rd),
2369 (v1i32 (opnode (v4i32 VPR128:$Rn))))],
2373 defm SMAXV : NeonI_2VAcross_2<0b0, 0b01010, "smaxv", int_aarch64_neon_smaxv>;
2374 defm UMAXV : NeonI_2VAcross_2<0b1, 0b01010, "umaxv", int_aarch64_neon_umaxv>;
2376 defm SMINV : NeonI_2VAcross_2<0b0, 0b11010, "sminv", int_aarch64_neon_sminv>;
2377 defm UMINV : NeonI_2VAcross_2<0b1, 0b11010, "uminv", int_aarch64_neon_uminv>;
2379 defm ADDV : NeonI_2VAcross_2<0b0, 0b11011, "addv", int_aarch64_neon_vaddv>;
2383 multiclass NeonI_2VAcross_3<bit u, bits<5> opcode, bits<2> size,
2384 string asmop, SDPatternOperator opnode> {
2385 def _1s4s: NeonI_2VAcross<0b1, u, size, opcode,
2386 (outs FPR32:$Rd), (ins VPR128:$Rn),
2387 asmop # "\t$Rd, $Rn.4s",
2388 [(set (v1f32 FPR32:$Rd),
2389 (v1f32 (opnode (v4f32 VPR128:$Rn))))],
2393 defm FMAXNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b00, "fmaxnmv",
2394 int_aarch64_neon_vmaxnmv>;
2395 defm FMINNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b10, "fminnmv",
2396 int_aarch64_neon_vminnmv>;
2398 defm FMAXV : NeonI_2VAcross_3<0b1, 0b01111, 0b00, "fmaxv",
2399 int_aarch64_neon_vmaxv>;
2400 defm FMINV : NeonI_2VAcross_3<0b1, 0b01111, 0b10, "fminv",
2401 int_aarch64_neon_vminv>;
2403 // The followings are for instruction class (Perm)
2405 class NeonI_Permute<bit q, bits<2> size, bits<3> opcode,
2406 string asmop, RegisterOperand OpVPR, string OpS,
2407 SDPatternOperator opnode, ValueType Ty>
2408 : NeonI_Perm<q, size, opcode,
2409 (outs OpVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2410 asmop # "\t$Rd." # OpS # ", $Rn." # OpS # ", $Rm." # OpS,
2411 [(set (Ty OpVPR:$Rd),
2412 (Ty (opnode (Ty OpVPR:$Rn), (Ty OpVPR:$Rm))))],
2415 multiclass NeonI_Perm_pat<bits<3> opcode, string asmop,
2416 SDPatternOperator opnode> {
2417 def _8b : NeonI_Permute<0b0, 0b00, opcode, asmop,
2418 VPR64, "8b", opnode, v8i8>;
2419 def _16b : NeonI_Permute<0b1, 0b00, opcode, asmop,
2420 VPR128, "16b",opnode, v16i8>;
2421 def _4h : NeonI_Permute<0b0, 0b01, opcode, asmop,
2422 VPR64, "4h", opnode, v4i16>;
2423 def _8h : NeonI_Permute<0b1, 0b01, opcode, asmop,
2424 VPR128, "8h", opnode, v8i16>;
2425 def _2s : NeonI_Permute<0b0, 0b10, opcode, asmop,
2426 VPR64, "2s", opnode, v2i32>;
2427 def _4s : NeonI_Permute<0b1, 0b10, opcode, asmop,
2428 VPR128, "4s", opnode, v4i32>;
2429 def _2d : NeonI_Permute<0b1, 0b11, opcode, asmop,
2430 VPR128, "2d", opnode, v2i64>;
2433 defm UZP1vvv : NeonI_Perm_pat<0b001, "uzp1", Neon_uzp1>;
2434 defm TRN1vvv : NeonI_Perm_pat<0b010, "trn1", Neon_trn1>;
2435 defm ZIP1vvv : NeonI_Perm_pat<0b011, "zip1", Neon_zip1>;
2436 defm UZP2vvv : NeonI_Perm_pat<0b101, "uzp2", Neon_uzp2>;
2437 defm TRN2vvv : NeonI_Perm_pat<0b110, "trn2", Neon_trn2>;
2438 defm ZIP2vvv : NeonI_Perm_pat<0b111, "zip2", Neon_zip2>;
2440 multiclass NeonI_Perm_float_pat<string INS, SDPatternOperator opnode> {
2441 def : Pat<(v2f32 (opnode (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
2442 (!cast<Instruction>(INS # "_2s") VPR64:$Rn, VPR64:$Rm)>;
2444 def : Pat<(v4f32 (opnode (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
2445 (!cast<Instruction>(INS # "_4s") VPR128:$Rn, VPR128:$Rm)>;
2447 def : Pat<(v2f64 (opnode (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
2448 (!cast<Instruction>(INS # "_2d") VPR128:$Rn, VPR128:$Rm)>;
2451 defm : NeonI_Perm_float_pat<"UZP1vvv", Neon_uzp1>;
2452 defm : NeonI_Perm_float_pat<"UZP2vvv", Neon_uzp2>;
2453 defm : NeonI_Perm_float_pat<"ZIP1vvv", Neon_zip1>;
2454 defm : NeonI_Perm_float_pat<"ZIP2vvv", Neon_zip2>;
2455 defm : NeonI_Perm_float_pat<"TRN1vvv", Neon_trn1>;
2456 defm : NeonI_Perm_float_pat<"TRN2vvv", Neon_trn2>;
2458 // The followings are for instruction class (3V Diff)
2460 // normal long/long2 pattern
2461 class NeonI_3VDL<bit q, bit u, bits<2> size, bits<4> opcode,
2462 string asmop, string ResS, string OpS,
2463 SDPatternOperator opnode, SDPatternOperator ext,
2464 RegisterOperand OpVPR,
2465 ValueType ResTy, ValueType OpTy>
2466 : NeonI_3VDiff<q, u, size, opcode,
2467 (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2468 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2469 [(set (ResTy VPR128:$Rd),
2470 (ResTy (opnode (ResTy (ext (OpTy OpVPR:$Rn))),
2471 (ResTy (ext (OpTy OpVPR:$Rm))))))],
2474 multiclass NeonI_3VDL_s<bit u, bits<4> opcode,
2475 string asmop, SDPatternOperator opnode,
2476 bit Commutable = 0> {
2477 let isCommutable = Commutable in {
2478 def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2479 opnode, sext, VPR64, v8i16, v8i8>;
2480 def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2481 opnode, sext, VPR64, v4i32, v4i16>;
2482 def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2483 opnode, sext, VPR64, v2i64, v2i32>;
2487 multiclass NeonI_3VDL2_s<bit u, bits<4> opcode, string asmop,
2488 SDPatternOperator opnode, bit Commutable = 0> {
2489 let isCommutable = Commutable in {
2490 def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2491 opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2492 def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2493 opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2494 def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2495 opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2499 multiclass NeonI_3VDL_u<bit u, bits<4> opcode, string asmop,
2500 SDPatternOperator opnode, bit Commutable = 0> {
2501 let isCommutable = Commutable in {
2502 def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2503 opnode, zext, VPR64, v8i16, v8i8>;
2504 def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2505 opnode, zext, VPR64, v4i32, v4i16>;
2506 def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2507 opnode, zext, VPR64, v2i64, v2i32>;
2511 multiclass NeonI_3VDL2_u<bit u, bits<4> opcode, string asmop,
2512 SDPatternOperator opnode, bit Commutable = 0> {
2513 let isCommutable = Commutable in {
2514 def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2515 opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2516 def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2517 opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2518 def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2519 opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2523 defm SADDLvvv : NeonI_3VDL_s<0b0, 0b0000, "saddl", add, 1>;
2524 defm UADDLvvv : NeonI_3VDL_u<0b1, 0b0000, "uaddl", add, 1>;
2526 defm SADDL2vvv : NeonI_3VDL2_s<0b0, 0b0000, "saddl2", add, 1>;
2527 defm UADDL2vvv : NeonI_3VDL2_u<0b1, 0b0000, "uaddl2", add, 1>;
2529 defm SSUBLvvv : NeonI_3VDL_s<0b0, 0b0010, "ssubl", sub, 0>;
2530 defm USUBLvvv : NeonI_3VDL_u<0b1, 0b0010, "usubl", sub, 0>;
2532 defm SSUBL2vvv : NeonI_3VDL2_s<0b0, 0b0010, "ssubl2", sub, 0>;
2533 defm USUBL2vvv : NeonI_3VDL2_u<0b1, 0b0010, "usubl2", sub, 0>;
2535 // normal wide/wide2 pattern
2536 class NeonI_3VDW<bit q, bit u, bits<2> size, bits<4> opcode,
2537 string asmop, string ResS, string OpS,
2538 SDPatternOperator opnode, SDPatternOperator ext,
2539 RegisterOperand OpVPR,
2540 ValueType ResTy, ValueType OpTy>
2541 : NeonI_3VDiff<q, u, size, opcode,
2542 (outs VPR128:$Rd), (ins VPR128:$Rn, OpVPR:$Rm),
2543 asmop # "\t$Rd." # ResS # ", $Rn." # ResS # ", $Rm." # OpS,
2544 [(set (ResTy VPR128:$Rd),
2545 (ResTy (opnode (ResTy VPR128:$Rn),
2546 (ResTy (ext (OpTy OpVPR:$Rm))))))],
2549 multiclass NeonI_3VDW_s<bit u, bits<4> opcode, string asmop,
2550 SDPatternOperator opnode> {
2551 def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2552 opnode, sext, VPR64, v8i16, v8i8>;
2553 def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2554 opnode, sext, VPR64, v4i32, v4i16>;
2555 def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2556 opnode, sext, VPR64, v2i64, v2i32>;
2559 defm SADDWvvv : NeonI_3VDW_s<0b0, 0b0001, "saddw", add>;
2560 defm SSUBWvvv : NeonI_3VDW_s<0b0, 0b0011, "ssubw", sub>;
2562 multiclass NeonI_3VDW2_s<bit u, bits<4> opcode, string asmop,
2563 SDPatternOperator opnode> {
2564 def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2565 opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2566 def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2567 opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2568 def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2569 opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2572 defm SADDW2vvv : NeonI_3VDW2_s<0b0, 0b0001, "saddw2", add>;
2573 defm SSUBW2vvv : NeonI_3VDW2_s<0b0, 0b0011, "ssubw2", sub>;
2575 multiclass NeonI_3VDW_u<bit u, bits<4> opcode, string asmop,
2576 SDPatternOperator opnode> {
2577 def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2578 opnode, zext, VPR64, v8i16, v8i8>;
2579 def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2580 opnode, zext, VPR64, v4i32, v4i16>;
2581 def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2582 opnode, zext, VPR64, v2i64, v2i32>;
2585 defm UADDWvvv : NeonI_3VDW_u<0b1, 0b0001, "uaddw", add>;
2586 defm USUBWvvv : NeonI_3VDW_u<0b1, 0b0011, "usubw", sub>;
2588 multiclass NeonI_3VDW2_u<bit u, bits<4> opcode, string asmop,
2589 SDPatternOperator opnode> {
2590 def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2591 opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2592 def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2593 opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2594 def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2595 opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2598 defm UADDW2vvv : NeonI_3VDW2_u<0b1, 0b0001, "uaddw2", add>;
2599 defm USUBW2vvv : NeonI_3VDW2_u<0b1, 0b0011, "usubw2", sub>;
2601 // Get the high half part of the vector element.
2602 multiclass NeonI_get_high {
2603 def _8h : PatFrag<(ops node:$Rn),
2604 (v8i8 (trunc (v8i16 (srl (v8i16 node:$Rn),
2605 (v8i16 (Neon_vdup (i32 8)))))))>;
2606 def _4s : PatFrag<(ops node:$Rn),
2607 (v4i16 (trunc (v4i32 (srl (v4i32 node:$Rn),
2608 (v4i32 (Neon_vdup (i32 16)))))))>;
2609 def _2d : PatFrag<(ops node:$Rn),
2610 (v2i32 (trunc (v2i64 (srl (v2i64 node:$Rn),
2611 (v2i64 (Neon_vdup (i32 32)))))))>;
2614 defm NI_get_hi : NeonI_get_high;
2616 // pattern for addhn/subhn with 2 operands
2617 class NeonI_3VDN_addhn_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2618 string asmop, string ResS, string OpS,
2619 SDPatternOperator opnode, SDPatternOperator get_hi,
2620 ValueType ResTy, ValueType OpTy>
2621 : NeonI_3VDiff<q, u, size, opcode,
2622 (outs VPR64:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2623 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2624 [(set (ResTy VPR64:$Rd),
2626 (OpTy (opnode (OpTy VPR128:$Rn),
2627 (OpTy VPR128:$Rm))))))],
2630 multiclass NeonI_3VDN_addhn_2Op<bit u, bits<4> opcode, string asmop,
2631 SDPatternOperator opnode, bit Commutable = 0> {
2632 let isCommutable = Commutable in {
2633 def _8b8h : NeonI_3VDN_addhn_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2634 opnode, NI_get_hi_8h, v8i8, v8i16>;
2635 def _4h4s : NeonI_3VDN_addhn_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2636 opnode, NI_get_hi_4s, v4i16, v4i32>;
2637 def _2s2d : NeonI_3VDN_addhn_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2638 opnode, NI_get_hi_2d, v2i32, v2i64>;
2642 defm ADDHNvvv : NeonI_3VDN_addhn_2Op<0b0, 0b0100, "addhn", add, 1>;
2643 defm SUBHNvvv : NeonI_3VDN_addhn_2Op<0b0, 0b0110, "subhn", sub, 0>;
2645 // pattern for operation with 2 operands
2646 class NeonI_3VD_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2647 string asmop, string ResS, string OpS,
2648 SDPatternOperator opnode,
2649 RegisterOperand ResVPR, RegisterOperand OpVPR,
2650 ValueType ResTy, ValueType OpTy>
2651 : NeonI_3VDiff<q, u, size, opcode,
2652 (outs ResVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2653 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2654 [(set (ResTy ResVPR:$Rd),
2655 (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))],
2658 // normal narrow pattern
2659 multiclass NeonI_3VDN_2Op<bit u, bits<4> opcode, string asmop,
2660 SDPatternOperator opnode, bit Commutable = 0> {
2661 let isCommutable = Commutable in {
2662 def _8b8h : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2663 opnode, VPR64, VPR128, v8i8, v8i16>;
2664 def _4h4s : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2665 opnode, VPR64, VPR128, v4i16, v4i32>;
2666 def _2s2d : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2667 opnode, VPR64, VPR128, v2i32, v2i64>;
2671 defm RADDHNvvv : NeonI_3VDN_2Op<0b1, 0b0100, "raddhn", int_arm_neon_vraddhn, 1>;
2672 defm RSUBHNvvv : NeonI_3VDN_2Op<0b1, 0b0110, "rsubhn", int_arm_neon_vrsubhn, 0>;
2674 // pattern for acle intrinsic with 3 operands
2675 class NeonI_3VDN_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2676 string asmop, string ResS, string OpS>
2677 : NeonI_3VDiff<q, u, size, opcode,
2678 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
2679 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2681 let Constraints = "$src = $Rd";
2682 let neverHasSideEffects = 1;
2685 multiclass NeonI_3VDN_3Op_v1<bit u, bits<4> opcode, string asmop> {
2686 def _16b8h : NeonI_3VDN_3Op<0b1, u, 0b00, opcode, asmop, "16b", "8h">;
2687 def _8h4s : NeonI_3VDN_3Op<0b1, u, 0b01, opcode, asmop, "8h", "4s">;
2688 def _4s2d : NeonI_3VDN_3Op<0b1, u, 0b10, opcode, asmop, "4s", "2d">;
2691 defm ADDHN2vvv : NeonI_3VDN_3Op_v1<0b0, 0b0100, "addhn2">;
2692 defm SUBHN2vvv : NeonI_3VDN_3Op_v1<0b0, 0b0110, "subhn2">;
2694 defm RADDHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0100, "raddhn2">;
2695 defm RSUBHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0110, "rsubhn2">;
2697 // Patterns have to be separate because there's a SUBREG_TO_REG in the output
2699 class NarrowHighHalfPat<Instruction INST, ValueType DstTy, ValueType SrcTy,
2700 SDPatternOperator coreop>
2701 : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2702 (v1i64 (bitconvert (DstTy (coreop (SrcTy VPR128:$Rn),
2703 (SrcTy VPR128:$Rm)))))),
2704 (INST (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2705 VPR128:$Rn, VPR128:$Rm)>;
2708 def : NarrowHighHalfPat<ADDHN2vvv_16b8h, v8i8, v8i16,
2709 BinOpFrag<(NI_get_hi_8h (add node:$LHS, node:$RHS))>>;
2710 def : NarrowHighHalfPat<ADDHN2vvv_8h4s, v4i16, v4i32,
2711 BinOpFrag<(NI_get_hi_4s (add node:$LHS, node:$RHS))>>;
2712 def : NarrowHighHalfPat<ADDHN2vvv_4s2d, v2i32, v2i64,
2713 BinOpFrag<(NI_get_hi_2d (add node:$LHS, node:$RHS))>>;
2716 def : NarrowHighHalfPat<SUBHN2vvv_16b8h, v8i8, v8i16,
2717 BinOpFrag<(NI_get_hi_8h (sub node:$LHS, node:$RHS))>>;
2718 def : NarrowHighHalfPat<SUBHN2vvv_8h4s, v4i16, v4i32,
2719 BinOpFrag<(NI_get_hi_4s (sub node:$LHS, node:$RHS))>>;
2720 def : NarrowHighHalfPat<SUBHN2vvv_4s2d, v2i32, v2i64,
2721 BinOpFrag<(NI_get_hi_2d (sub node:$LHS, node:$RHS))>>;
2724 def : NarrowHighHalfPat<RADDHN2vvv_16b8h, v8i8, v8i16, int_arm_neon_vraddhn>;
2725 def : NarrowHighHalfPat<RADDHN2vvv_8h4s, v4i16, v4i32, int_arm_neon_vraddhn>;
2726 def : NarrowHighHalfPat<RADDHN2vvv_4s2d, v2i32, v2i64, int_arm_neon_vraddhn>;
2729 def : NarrowHighHalfPat<RSUBHN2vvv_16b8h, v8i8, v8i16, int_arm_neon_vrsubhn>;
2730 def : NarrowHighHalfPat<RSUBHN2vvv_8h4s, v4i16, v4i32, int_arm_neon_vrsubhn>;
2731 def : NarrowHighHalfPat<RSUBHN2vvv_4s2d, v2i32, v2i64, int_arm_neon_vrsubhn>;
2733 // pattern that need to extend result
2734 class NeonI_3VDL_Ext<bit q, bit u, bits<2> size, bits<4> opcode,
2735 string asmop, string ResS, string OpS,
2736 SDPatternOperator opnode,
2737 RegisterOperand OpVPR,
2738 ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2739 : NeonI_3VDiff<q, u, size, opcode,
2740 (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2741 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2742 [(set (ResTy VPR128:$Rd),
2743 (ResTy (zext (OpSTy (opnode (OpTy OpVPR:$Rn),
2744 (OpTy OpVPR:$Rm))))))],
2747 multiclass NeonI_3VDL_zext<bit u, bits<4> opcode, string asmop,
2748 SDPatternOperator opnode, bit Commutable = 0> {
2749 let isCommutable = Commutable in {
2750 def _8h8b : NeonI_3VDL_Ext<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2751 opnode, VPR64, v8i16, v8i8, v8i8>;
2752 def _4s4h : NeonI_3VDL_Ext<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2753 opnode, VPR64, v4i32, v4i16, v4i16>;
2754 def _2d2s : NeonI_3VDL_Ext<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2755 opnode, VPR64, v2i64, v2i32, v2i32>;
2759 defm SABDLvvv : NeonI_3VDL_zext<0b0, 0b0111, "sabdl", int_arm_neon_vabds, 1>;
2760 defm UABDLvvv : NeonI_3VDL_zext<0b1, 0b0111, "uabdl", int_arm_neon_vabdu, 1>;
2762 multiclass NeonI_Op_High<SDPatternOperator op> {
2763 def _16B : PatFrag<(ops node:$Rn, node:$Rm),
2764 (op (v8i8 (Neon_High16B node:$Rn)),
2765 (v8i8 (Neon_High16B node:$Rm)))>;
2766 def _8H : PatFrag<(ops node:$Rn, node:$Rm),
2767 (op (v4i16 (Neon_High8H node:$Rn)),
2768 (v4i16 (Neon_High8H node:$Rm)))>;
2769 def _4S : PatFrag<(ops node:$Rn, node:$Rm),
2770 (op (v2i32 (Neon_High4S node:$Rn)),
2771 (v2i32 (Neon_High4S node:$Rm)))>;
2774 defm NI_sabdl_hi : NeonI_Op_High<int_arm_neon_vabds>;
2775 defm NI_uabdl_hi : NeonI_Op_High<int_arm_neon_vabdu>;
2776 defm NI_smull_hi : NeonI_Op_High<int_arm_neon_vmulls>;
2777 defm NI_umull_hi : NeonI_Op_High<int_arm_neon_vmullu>;
2778 defm NI_qdmull_hi : NeonI_Op_High<int_arm_neon_vqdmull>;
2779 defm NI_pmull_hi : NeonI_Op_High<int_arm_neon_vmullp>;
2781 multiclass NeonI_3VDL_Abd_u<bit u, bits<4> opcode, string asmop, string opnode,
2782 bit Commutable = 0> {
2783 let isCommutable = Commutable in {
2784 def _8h8b : NeonI_3VDL_Ext<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2785 !cast<PatFrag>(opnode # "_16B"),
2786 VPR128, v8i16, v16i8, v8i8>;
2787 def _4s4h : NeonI_3VDL_Ext<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2788 !cast<PatFrag>(opnode # "_8H"),
2789 VPR128, v4i32, v8i16, v4i16>;
2790 def _2d2s : NeonI_3VDL_Ext<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2791 !cast<PatFrag>(opnode # "_4S"),
2792 VPR128, v2i64, v4i32, v2i32>;
2796 defm SABDL2vvv : NeonI_3VDL_Abd_u<0b0, 0b0111, "sabdl2", "NI_sabdl_hi", 1>;
2797 defm UABDL2vvv : NeonI_3VDL_Abd_u<0b1, 0b0111, "uabdl2", "NI_uabdl_hi", 1>;
2799 // For pattern that need two operators being chained.
2800 class NeonI_3VDL_Aba<bit q, bit u, bits<2> size, bits<4> opcode,
2801 string asmop, string ResS, string OpS,
2802 SDPatternOperator opnode, SDPatternOperator subop,
2803 RegisterOperand OpVPR,
2804 ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2805 : NeonI_3VDiff<q, u, size, opcode,
2806 (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2807 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2808 [(set (ResTy VPR128:$Rd),
2810 (ResTy VPR128:$src),
2811 (ResTy (zext (OpSTy (subop (OpTy OpVPR:$Rn),
2812 (OpTy OpVPR:$Rm))))))))],
2814 let Constraints = "$src = $Rd";
2817 multiclass NeonI_3VDL_Aba_v1<bit u, bits<4> opcode, string asmop,
2818 SDPatternOperator opnode, SDPatternOperator subop>{
2819 def _8h8b : NeonI_3VDL_Aba<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2820 opnode, subop, VPR64, v8i16, v8i8, v8i8>;
2821 def _4s4h : NeonI_3VDL_Aba<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2822 opnode, subop, VPR64, v4i32, v4i16, v4i16>;
2823 def _2d2s : NeonI_3VDL_Aba<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2824 opnode, subop, VPR64, v2i64, v2i32, v2i32>;
2827 defm SABALvvv : NeonI_3VDL_Aba_v1<0b0, 0b0101, "sabal",
2828 add, int_arm_neon_vabds>;
2829 defm UABALvvv : NeonI_3VDL_Aba_v1<0b1, 0b0101, "uabal",
2830 add, int_arm_neon_vabdu>;
2832 multiclass NeonI_3VDL2_Aba_v1<bit u, bits<4> opcode, string asmop,
2833 SDPatternOperator opnode, string subop> {
2834 def _8h8b : NeonI_3VDL_Aba<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2835 opnode, !cast<PatFrag>(subop # "_16B"),
2836 VPR128, v8i16, v16i8, v8i8>;
2837 def _4s4h : NeonI_3VDL_Aba<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2838 opnode, !cast<PatFrag>(subop # "_8H"),
2839 VPR128, v4i32, v8i16, v4i16>;
2840 def _2d2s : NeonI_3VDL_Aba<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2841 opnode, !cast<PatFrag>(subop # "_4S"),
2842 VPR128, v2i64, v4i32, v2i32>;
2845 defm SABAL2vvv : NeonI_3VDL2_Aba_v1<0b0, 0b0101, "sabal2", add,
2847 defm UABAL2vvv : NeonI_3VDL2_Aba_v1<0b1, 0b0101, "uabal2", add,
2850 // Long pattern with 2 operands
2851 multiclass NeonI_3VDL_2Op<bit u, bits<4> opcode, string asmop,
2852 SDPatternOperator opnode, bit Commutable = 0> {
2853 let isCommutable = Commutable in {
2854 def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2855 opnode, VPR128, VPR64, v8i16, v8i8>;
2856 def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2857 opnode, VPR128, VPR64, v4i32, v4i16>;
2858 def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2859 opnode, VPR128, VPR64, v2i64, v2i32>;
2863 defm SMULLvvv : NeonI_3VDL_2Op<0b0, 0b1100, "smull", int_arm_neon_vmulls, 1>;
2864 defm UMULLvvv : NeonI_3VDL_2Op<0b1, 0b1100, "umull", int_arm_neon_vmullu, 1>;
2866 class NeonI_3VDL2_2Op_mull<bit q, bit u, bits<2> size, bits<4> opcode,
2867 string asmop, string ResS, string OpS,
2868 SDPatternOperator opnode,
2869 ValueType ResTy, ValueType OpTy>
2870 : NeonI_3VDiff<q, u, size, opcode,
2871 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2872 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2873 [(set (ResTy VPR128:$Rd),
2874 (ResTy (opnode (OpTy VPR128:$Rn), (OpTy VPR128:$Rm))))],
2877 multiclass NeonI_3VDL2_2Op_mull_v1<bit u, bits<4> opcode, string asmop,
2878 string opnode, bit Commutable = 0> {
2879 let isCommutable = Commutable in {
2880 def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2881 !cast<PatFrag>(opnode # "_16B"),
2883 def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2884 !cast<PatFrag>(opnode # "_8H"),
2886 def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2887 !cast<PatFrag>(opnode # "_4S"),
2892 defm SMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b0, 0b1100, "smull2",
2894 defm UMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b1, 0b1100, "umull2",
2897 // Long pattern with 3 operands
2898 class NeonI_3VDL_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2899 string asmop, string ResS, string OpS,
2900 SDPatternOperator opnode,
2901 ValueType ResTy, ValueType OpTy>
2902 : NeonI_3VDiff<q, u, size, opcode,
2903 (outs VPR128:$Rd), (ins VPR128:$src, VPR64:$Rn, VPR64:$Rm),
2904 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2905 [(set (ResTy VPR128:$Rd),
2907 (ResTy VPR128:$src),
2908 (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))))],
2910 let Constraints = "$src = $Rd";
2913 multiclass NeonI_3VDL_3Op_v1<bit u, bits<4> opcode, string asmop,
2914 SDPatternOperator opnode> {
2915 def _8h8b : NeonI_3VDL_3Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2916 opnode, v8i16, v8i8>;
2917 def _4s4h : NeonI_3VDL_3Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2918 opnode, v4i32, v4i16>;
2919 def _2d2s : NeonI_3VDL_3Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2920 opnode, v2i64, v2i32>;
2923 def Neon_smlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2925 (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
2927 def Neon_umlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2929 (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
2931 def Neon_smlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2933 (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
2935 def Neon_umlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2937 (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
2939 defm SMLALvvv : NeonI_3VDL_3Op_v1<0b0, 0b1000, "smlal", Neon_smlal>;
2940 defm UMLALvvv : NeonI_3VDL_3Op_v1<0b1, 0b1000, "umlal", Neon_umlal>;
2942 defm SMLSLvvv : NeonI_3VDL_3Op_v1<0b0, 0b1010, "smlsl", Neon_smlsl>;
2943 defm UMLSLvvv : NeonI_3VDL_3Op_v1<0b1, 0b1010, "umlsl", Neon_umlsl>;
2945 class NeonI_3VDL2_3Op_mlas<bit q, bit u, bits<2> size, bits<4> opcode,
2946 string asmop, string ResS, string OpS,
2947 SDPatternOperator subop, SDPatternOperator opnode,
2948 RegisterOperand OpVPR,
2949 ValueType ResTy, ValueType OpTy>
2950 : NeonI_3VDiff<q, u, size, opcode,
2951 (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2952 asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2953 [(set (ResTy VPR128:$Rd),
2955 (ResTy VPR128:$src),
2956 (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))))],
2958 let Constraints = "$src = $Rd";
2961 multiclass NeonI_3VDL2_3Op_mlas_v1<bit u, bits<4> opcode, string asmop,
2962 SDPatternOperator subop, string opnode> {
2963 def _8h16b : NeonI_3VDL2_3Op_mlas<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2964 subop, !cast<PatFrag>(opnode # "_16B"),
2965 VPR128, v8i16, v16i8>;
2966 def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2967 subop, !cast<PatFrag>(opnode # "_8H"),
2968 VPR128, v4i32, v8i16>;
2969 def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2970 subop, !cast<PatFrag>(opnode # "_4S"),
2971 VPR128, v2i64, v4i32>;
2974 defm SMLAL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1000, "smlal2",
2975 add, "NI_smull_hi">;
2976 defm UMLAL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1000, "umlal2",
2977 add, "NI_umull_hi">;
2979 defm SMLSL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1010, "smlsl2",
2980 sub, "NI_smull_hi">;
2981 defm UMLSL2vvv : NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1010, "umlsl2",
2982 sub, "NI_umull_hi">;
2984 multiclass NeonI_3VDL_qdmlal_3Op_v2<bit u, bits<4> opcode, string asmop,
2985 SDPatternOperator opnode> {
2986 def _4s4h : NeonI_3VDL2_3Op_mlas<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2987 opnode, int_arm_neon_vqdmull,
2988 VPR64, v4i32, v4i16>;
2989 def _2d2s : NeonI_3VDL2_3Op_mlas<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2990 opnode, int_arm_neon_vqdmull,
2991 VPR64, v2i64, v2i32>;
2994 defm SQDMLALvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1001, "sqdmlal",
2995 int_arm_neon_vqadds>;
2996 defm SQDMLSLvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1011, "sqdmlsl",
2997 int_arm_neon_vqsubs>;
2999 multiclass NeonI_3VDL_v2<bit u, bits<4> opcode, string asmop,
3000 SDPatternOperator opnode, bit Commutable = 0> {
3001 let isCommutable = Commutable in {
3002 def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3003 opnode, VPR128, VPR64, v4i32, v4i16>;
3004 def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3005 opnode, VPR128, VPR64, v2i64, v2i32>;
3009 defm SQDMULLvvv : NeonI_3VDL_v2<0b0, 0b1101, "sqdmull",
3010 int_arm_neon_vqdmull, 1>;
3012 multiclass NeonI_3VDL2_2Op_mull_v2<bit u, bits<4> opcode, string asmop,
3013 string opnode, bit Commutable = 0> {
3014 let isCommutable = Commutable in {
3015 def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3016 !cast<PatFrag>(opnode # "_8H"),
3018 def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3019 !cast<PatFrag>(opnode # "_4S"),
3024 defm SQDMULL2vvv : NeonI_3VDL2_2Op_mull_v2<0b0, 0b1101, "sqdmull2",
3027 multiclass NeonI_3VDL2_3Op_qdmlal_v2<bit u, bits<4> opcode, string asmop,
3028 SDPatternOperator opnode> {
3029 def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3030 opnode, NI_qdmull_hi_8H,
3031 VPR128, v4i32, v8i16>;
3032 def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3033 opnode, NI_qdmull_hi_4S,
3034 VPR128, v2i64, v4i32>;
3037 defm SQDMLAL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1001, "sqdmlal2",
3038 int_arm_neon_vqadds>;
3039 defm SQDMLSL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1011, "sqdmlsl2",
3040 int_arm_neon_vqsubs>;
3042 multiclass NeonI_3VDL_v3<bit u, bits<4> opcode, string asmop,
3043 SDPatternOperator opnode_8h8b,
3044 SDPatternOperator opnode_1q1d, bit Commutable = 0> {
3045 let isCommutable = Commutable in {
3046 def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3047 opnode_8h8b, VPR128, VPR64, v8i16, v8i8>;
3049 def _1q1d : NeonI_3VD_2Op<0b0, u, 0b11, opcode, asmop, "1q", "1d",
3050 opnode_1q1d, VPR128, VPR64, v16i8, v1i64>;
3054 defm PMULLvvv : NeonI_3VDL_v3<0b0, 0b1110, "pmull", int_arm_neon_vmullp,
3055 int_aarch64_neon_vmull_p64, 1>;
3057 multiclass NeonI_3VDL2_2Op_mull_v3<bit u, bits<4> opcode, string asmop,
3058 string opnode, bit Commutable = 0> {
3059 let isCommutable = Commutable in {
3060 def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3061 !cast<PatFrag>(opnode # "_16B"),
3065 NeonI_3VDiff<0b1, u, 0b11, opcode,
3066 (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3067 asmop # "\t$Rd.1q, $Rn.2d, $Rm.2d",
3068 [(set (v16i8 VPR128:$Rd),
3069 (v16i8 (int_aarch64_neon_vmull_p64
3070 (v1i64 (scalar_to_vector
3071 (i64 (vector_extract (v2i64 VPR128:$Rn), 1)))),
3072 (v1i64 (scalar_to_vector
3073 (i64 (vector_extract (v2i64 VPR128:$Rm), 1)))))))],
3078 defm PMULL2vvv : NeonI_3VDL2_2Op_mull_v3<0b0, 0b1110, "pmull2", "NI_pmull_hi",
3081 // End of implementation for instruction class (3V Diff)
3083 // The followings are vector load/store multiple N-element structure
3084 // (class SIMD lselem).
3086 // ld1: load multiple 1-element structure to 1/2/3/4 registers.
3087 // ld2/ld3/ld4: load multiple N-element structure to N registers (N = 2, 3, 4).
3088 // The structure consists of a sequence of sets of N values.
3089 // The first element of the structure is placed in the first lane
3090 // of the first first vector, the second element in the first lane
3091 // of the second vector, and so on.
3092 // E.g. LD1_3V_2S will load 32-bit elements {A, B, C, D, E, F} sequentially into
3093 // the three 64-bit vectors list {BA, DC, FE}.
3094 // E.g. LD3_2S will load 32-bit elements {A, B, C, D, E, F} into the three
3095 // 64-bit vectors list {DA, EB, FC}.
3096 // Store instructions store multiple structure to N registers like load.
3099 class NeonI_LDVList<bit q, bits<4> opcode, bits<2> size,
3100 RegisterOperand VecList, string asmop>
3101 : NeonI_LdStMult<q, 1, opcode, size,
3102 (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3103 asmop # "\t$Rt, [$Rn]",
3107 let neverHasSideEffects = 1;
3110 multiclass LDVList_BHSD<bits<4> opcode, string List, string asmop> {
3111 def _8B : NeonI_LDVList<0, opcode, 0b00,
3112 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3114 def _4H : NeonI_LDVList<0, opcode, 0b01,
3115 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3117 def _2S : NeonI_LDVList<0, opcode, 0b10,
3118 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3120 def _16B : NeonI_LDVList<1, opcode, 0b00,
3121 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3123 def _8H : NeonI_LDVList<1, opcode, 0b01,
3124 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3126 def _4S : NeonI_LDVList<1, opcode, 0b10,
3127 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3129 def _2D : NeonI_LDVList<1, opcode, 0b11,
3130 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3133 // Load multiple N-element structure to N consecutive registers (N = 1,2,3,4)
3134 defm LD1 : LDVList_BHSD<0b0111, "VOne", "ld1">;
3135 def LD1_1D : NeonI_LDVList<0, 0b0111, 0b11, VOne1D_operand, "ld1">;
3137 defm LD2 : LDVList_BHSD<0b1000, "VPair", "ld2">;
3139 defm LD3 : LDVList_BHSD<0b0100, "VTriple", "ld3">;
3141 defm LD4 : LDVList_BHSD<0b0000, "VQuad", "ld4">;
3143 // Load multiple 1-element structure to N consecutive registers (N = 2,3,4)
3144 defm LD1x2 : LDVList_BHSD<0b1010, "VPair", "ld1">;
3145 def LD1x2_1D : NeonI_LDVList<0, 0b1010, 0b11, VPair1D_operand, "ld1">;
3147 defm LD1x3 : LDVList_BHSD<0b0110, "VTriple", "ld1">;
3148 def LD1x3_1D : NeonI_LDVList<0, 0b0110, 0b11, VTriple1D_operand, "ld1">;
3150 defm LD1x4 : LDVList_BHSD<0b0010, "VQuad", "ld1">;
3151 def LD1x4_1D : NeonI_LDVList<0, 0b0010, 0b11, VQuad1D_operand, "ld1">;
3153 class NeonI_STVList<bit q, bits<4> opcode, bits<2> size,
3154 RegisterOperand VecList, string asmop>
3155 : NeonI_LdStMult<q, 0, opcode, size,
3156 (outs), (ins GPR64xsp:$Rn, VecList:$Rt),
3157 asmop # "\t$Rt, [$Rn]",
3161 let neverHasSideEffects = 1;
3164 multiclass STVList_BHSD<bits<4> opcode, string List, string asmop> {
3165 def _8B : NeonI_STVList<0, opcode, 0b00,
3166 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3168 def _4H : NeonI_STVList<0, opcode, 0b01,
3169 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3171 def _2S : NeonI_STVList<0, opcode, 0b10,
3172 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3174 def _16B : NeonI_STVList<1, opcode, 0b00,
3175 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3177 def _8H : NeonI_STVList<1, opcode, 0b01,
3178 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3180 def _4S : NeonI_STVList<1, opcode, 0b10,
3181 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3183 def _2D : NeonI_STVList<1, opcode, 0b11,
3184 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3187 // Store multiple N-element structures from N registers (N = 1,2,3,4)
3188 defm ST1 : STVList_BHSD<0b0111, "VOne", "st1">;
3189 def ST1_1D : NeonI_STVList<0, 0b0111, 0b11, VOne1D_operand, "st1">;
3191 defm ST2 : STVList_BHSD<0b1000, "VPair", "st2">;
3193 defm ST3 : STVList_BHSD<0b0100, "VTriple", "st3">;
3195 defm ST4 : STVList_BHSD<0b0000, "VQuad", "st4">;
3197 // Store multiple 1-element structures from N consecutive registers (N = 2,3,4)
3198 defm ST1x2 : STVList_BHSD<0b1010, "VPair", "st1">;
3199 def ST1x2_1D : NeonI_STVList<0, 0b1010, 0b11, VPair1D_operand, "st1">;
3201 defm ST1x3 : STVList_BHSD<0b0110, "VTriple", "st1">;
3202 def ST1x3_1D : NeonI_STVList<0, 0b0110, 0b11, VTriple1D_operand, "st1">;
3204 defm ST1x4 : STVList_BHSD<0b0010, "VQuad", "st1">;
3205 def ST1x4_1D : NeonI_STVList<0, 0b0010, 0b11, VQuad1D_operand, "st1">;
3207 def : Pat<(v2f64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3208 def : Pat<(v2i64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3210 def : Pat<(v4f32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3211 def : Pat<(v4i32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3213 def : Pat<(v8i16 (load GPR64xsp:$addr)), (LD1_8H GPR64xsp:$addr)>;
3214 def : Pat<(v16i8 (load GPR64xsp:$addr)), (LD1_16B GPR64xsp:$addr)>;
3216 def : Pat<(v1f64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3217 def : Pat<(v1i64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3219 def : Pat<(v2f32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3220 def : Pat<(v2i32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3222 def : Pat<(v4i16 (load GPR64xsp:$addr)), (LD1_4H GPR64xsp:$addr)>;
3223 def : Pat<(v8i8 (load GPR64xsp:$addr)), (LD1_8B GPR64xsp:$addr)>;
3225 def : Pat<(store (v2i64 VPR128:$value), GPR64xsp:$addr),
3226 (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3227 def : Pat<(store (v2f64 VPR128:$value), GPR64xsp:$addr),
3228 (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3230 def : Pat<(store (v4i32 VPR128:$value), GPR64xsp:$addr),
3231 (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3232 def : Pat<(store (v4f32 VPR128:$value), GPR64xsp:$addr),
3233 (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3235 def : Pat<(store (v8i16 VPR128:$value), GPR64xsp:$addr),
3236 (ST1_8H GPR64xsp:$addr, VPR128:$value)>;
3237 def : Pat<(store (v16i8 VPR128:$value), GPR64xsp:$addr),
3238 (ST1_16B GPR64xsp:$addr, VPR128:$value)>;
3240 def : Pat<(store (v1i64 VPR64:$value), GPR64xsp:$addr),
3241 (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3242 def : Pat<(store (v1f64 VPR64:$value), GPR64xsp:$addr),
3243 (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3245 def : Pat<(store (v2i32 VPR64:$value), GPR64xsp:$addr),
3246 (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3247 def : Pat<(store (v2f32 VPR64:$value), GPR64xsp:$addr),
3248 (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3250 def : Pat<(store (v4i16 VPR64:$value), GPR64xsp:$addr),
3251 (ST1_4H GPR64xsp:$addr, VPR64:$value)>;
3252 def : Pat<(store (v8i8 VPR64:$value), GPR64xsp:$addr),
3253 (ST1_8B GPR64xsp:$addr, VPR64:$value)>;
3255 // End of vector load/store multiple N-element structure(class SIMD lselem)
3257 // The followings are post-index vector load/store multiple N-element
3258 // structure(class SIMD lselem-post)
3259 def exact1_asmoperand : AsmOperandClass {
3260 let Name = "Exact1";
3261 let PredicateMethod = "isExactImm<1>";
3262 let RenderMethod = "addImmOperands";
3264 def uimm_exact1 : Operand<i32>, ImmLeaf<i32, [{return Imm == 1;}]> {
3265 let ParserMatchClass = exact1_asmoperand;
3268 def exact2_asmoperand : AsmOperandClass {
3269 let Name = "Exact2";
3270 let PredicateMethod = "isExactImm<2>";
3271 let RenderMethod = "addImmOperands";
3273 def uimm_exact2 : Operand<i32>, ImmLeaf<i32, [{return Imm == 2;}]> {
3274 let ParserMatchClass = exact2_asmoperand;
3277 def exact3_asmoperand : AsmOperandClass {
3278 let Name = "Exact3";
3279 let PredicateMethod = "isExactImm<3>";
3280 let RenderMethod = "addImmOperands";
3282 def uimm_exact3 : Operand<i32>, ImmLeaf<i32, [{return Imm == 3;}]> {
3283 let ParserMatchClass = exact3_asmoperand;
3286 def exact4_asmoperand : AsmOperandClass {
3287 let Name = "Exact4";
3288 let PredicateMethod = "isExactImm<4>";
3289 let RenderMethod = "addImmOperands";
3291 def uimm_exact4 : Operand<i32>, ImmLeaf<i32, [{return Imm == 4;}]> {
3292 let ParserMatchClass = exact4_asmoperand;
3295 def exact6_asmoperand : AsmOperandClass {
3296 let Name = "Exact6";
3297 let PredicateMethod = "isExactImm<6>";
3298 let RenderMethod = "addImmOperands";
3300 def uimm_exact6 : Operand<i32>, ImmLeaf<i32, [{return Imm == 6;}]> {
3301 let ParserMatchClass = exact6_asmoperand;
3304 def exact8_asmoperand : AsmOperandClass {
3305 let Name = "Exact8";
3306 let PredicateMethod = "isExactImm<8>";
3307 let RenderMethod = "addImmOperands";
3309 def uimm_exact8 : Operand<i32>, ImmLeaf<i32, [{return Imm == 8;}]> {
3310 let ParserMatchClass = exact8_asmoperand;
3313 def exact12_asmoperand : AsmOperandClass {
3314 let Name = "Exact12";
3315 let PredicateMethod = "isExactImm<12>";
3316 let RenderMethod = "addImmOperands";
3318 def uimm_exact12 : Operand<i32>, ImmLeaf<i32, [{return Imm == 12;}]> {
3319 let ParserMatchClass = exact12_asmoperand;
3322 def exact16_asmoperand : AsmOperandClass {
3323 let Name = "Exact16";
3324 let PredicateMethod = "isExactImm<16>";
3325 let RenderMethod = "addImmOperands";
3327 def uimm_exact16 : Operand<i32>, ImmLeaf<i32, [{return Imm == 16;}]> {
3328 let ParserMatchClass = exact16_asmoperand;
3331 def exact24_asmoperand : AsmOperandClass {
3332 let Name = "Exact24";
3333 let PredicateMethod = "isExactImm<24>";
3334 let RenderMethod = "addImmOperands";
3336 def uimm_exact24 : Operand<i32>, ImmLeaf<i32, [{return Imm == 24;}]> {
3337 let ParserMatchClass = exact24_asmoperand;
3340 def exact32_asmoperand : AsmOperandClass {
3341 let Name = "Exact32";
3342 let PredicateMethod = "isExactImm<32>";
3343 let RenderMethod = "addImmOperands";
3345 def uimm_exact32 : Operand<i32>, ImmLeaf<i32, [{return Imm == 32;}]> {
3346 let ParserMatchClass = exact32_asmoperand;
3349 def exact48_asmoperand : AsmOperandClass {
3350 let Name = "Exact48";
3351 let PredicateMethod = "isExactImm<48>";
3352 let RenderMethod = "addImmOperands";
3354 def uimm_exact48 : Operand<i32>, ImmLeaf<i32, [{return Imm == 48;}]> {
3355 let ParserMatchClass = exact48_asmoperand;
3358 def exact64_asmoperand : AsmOperandClass {
3359 let Name = "Exact64";
3360 let PredicateMethod = "isExactImm<64>";
3361 let RenderMethod = "addImmOperands";
3363 def uimm_exact64 : Operand<i32>, ImmLeaf<i32, [{return Imm == 64;}]> {
3364 let ParserMatchClass = exact64_asmoperand;
3367 multiclass NeonI_LDWB_VList<bit q, bits<4> opcode, bits<2> size,
3368 RegisterOperand VecList, Operand ImmTy,
3370 let Constraints = "$Rn = $wb", mayLoad = 1, neverHasSideEffects = 1,
3371 DecoderMethod = "DecodeVLDSTPostInstruction" in {
3372 def _fixed : NeonI_LdStMult_Post<q, 1, opcode, size,
3373 (outs VecList:$Rt, GPR64xsp:$wb),
3374 (ins GPR64xsp:$Rn, ImmTy:$amt),
3375 asmop # "\t$Rt, [$Rn], $amt",
3381 def _register : NeonI_LdStMult_Post<q, 1, opcode, size,
3382 (outs VecList:$Rt, GPR64xsp:$wb),
3383 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3384 asmop # "\t$Rt, [$Rn], $Rm",
3390 multiclass LDWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3391 Operand ImmTy2, string asmop> {
3392 defm _8B : NeonI_LDWB_VList<0, opcode, 0b00,
3393 !cast<RegisterOperand>(List # "8B_operand"),
3396 defm _4H : NeonI_LDWB_VList<0, opcode, 0b01,
3397 !cast<RegisterOperand>(List # "4H_operand"),
3400 defm _2S : NeonI_LDWB_VList<0, opcode, 0b10,
3401 !cast<RegisterOperand>(List # "2S_operand"),
3404 defm _16B : NeonI_LDWB_VList<1, opcode, 0b00,
3405 !cast<RegisterOperand>(List # "16B_operand"),
3408 defm _8H : NeonI_LDWB_VList<1, opcode, 0b01,
3409 !cast<RegisterOperand>(List # "8H_operand"),
3412 defm _4S : NeonI_LDWB_VList<1, opcode, 0b10,
3413 !cast<RegisterOperand>(List # "4S_operand"),
3416 defm _2D : NeonI_LDWB_VList<1, opcode, 0b11,
3417 !cast<RegisterOperand>(List # "2D_operand"),
3421 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3422 defm LD1WB : LDWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "ld1">;
3423 defm LD1WB_1D : NeonI_LDWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3426 defm LD2WB : LDWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "ld2">;
3428 defm LD3WB : LDWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3431 defm LD4WB : LDWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "ld4">;
3433 // Post-index load multiple 1-element structures from N consecutive registers
3435 defm LD1x2WB : LDWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3437 defm LD1x2WB_1D : NeonI_LDWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3438 uimm_exact16, "ld1">;
3440 defm LD1x3WB : LDWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3442 defm LD1x3WB_1D : NeonI_LDWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3443 uimm_exact24, "ld1">;
3445 defm LD1x4WB : LDWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3447 defm LD1x4WB_1D : NeonI_LDWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3448 uimm_exact32, "ld1">;
3450 multiclass NeonI_STWB_VList<bit q, bits<4> opcode, bits<2> size,
3451 RegisterOperand VecList, Operand ImmTy,
3453 let Constraints = "$Rn = $wb", mayStore = 1, neverHasSideEffects = 1,
3454 DecoderMethod = "DecodeVLDSTPostInstruction" in {
3455 def _fixed : NeonI_LdStMult_Post<q, 0, opcode, size,
3456 (outs GPR64xsp:$wb),
3457 (ins GPR64xsp:$Rn, ImmTy:$amt, VecList:$Rt),
3458 asmop # "\t$Rt, [$Rn], $amt",
3464 def _register : NeonI_LdStMult_Post<q, 0, opcode, size,
3465 (outs GPR64xsp:$wb),
3466 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VecList:$Rt),
3467 asmop # "\t$Rt, [$Rn], $Rm",
3473 multiclass STWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3474 Operand ImmTy2, string asmop> {
3475 defm _8B : NeonI_STWB_VList<0, opcode, 0b00,
3476 !cast<RegisterOperand>(List # "8B_operand"), ImmTy, asmop>;
3478 defm _4H : NeonI_STWB_VList<0, opcode, 0b01,
3479 !cast<RegisterOperand>(List # "4H_operand"),
3482 defm _2S : NeonI_STWB_VList<0, opcode, 0b10,
3483 !cast<RegisterOperand>(List # "2S_operand"),
3486 defm _16B : NeonI_STWB_VList<1, opcode, 0b00,
3487 !cast<RegisterOperand>(List # "16B_operand"),
3490 defm _8H : NeonI_STWB_VList<1, opcode, 0b01,
3491 !cast<RegisterOperand>(List # "8H_operand"),
3494 defm _4S : NeonI_STWB_VList<1, opcode, 0b10,
3495 !cast<RegisterOperand>(List # "4S_operand"),
3498 defm _2D : NeonI_STWB_VList<1, opcode, 0b11,
3499 !cast<RegisterOperand>(List # "2D_operand"),
3503 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3504 defm ST1WB : STWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "st1">;
3505 defm ST1WB_1D : NeonI_STWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3508 defm ST2WB : STWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "st2">;
3510 defm ST3WB : STWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3513 defm ST4WB : STWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "st4">;
3515 // Post-index load multiple 1-element structures from N consecutive registers
3517 defm ST1x2WB : STWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3519 defm ST1x2WB_1D : NeonI_STWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3520 uimm_exact16, "st1">;
3522 defm ST1x3WB : STWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3524 defm ST1x3WB_1D : NeonI_STWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3525 uimm_exact24, "st1">;
3527 defm ST1x4WB : STWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3529 defm ST1x4WB_1D : NeonI_STWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3530 uimm_exact32, "st1">;
3532 // End of post-index vector load/store multiple N-element structure
3533 // (class SIMD lselem-post)
3535 // The followings are vector load/store single N-element structure
3536 // (class SIMD lsone).
3537 def neon_uimm0_bare : Operand<i64>,
3538 ImmLeaf<i64, [{return Imm == 0;}]> {
3539 let ParserMatchClass = neon_uimm0_asmoperand;
3540 let PrintMethod = "printUImmBareOperand";
3543 def neon_uimm1_bare : Operand<i64>,
3544 ImmLeaf<i64, [{return Imm < 2;}]> {
3545 let ParserMatchClass = neon_uimm1_asmoperand;
3546 let PrintMethod = "printUImmBareOperand";
3549 def neon_uimm2_bare : Operand<i64>,
3550 ImmLeaf<i64, [{return Imm < 4;}]> {
3551 let ParserMatchClass = neon_uimm2_asmoperand;
3552 let PrintMethod = "printUImmBareOperand";
3555 def neon_uimm3_bare : Operand<i64>,
3556 ImmLeaf<i64, [{return Imm < 8;}]> {
3557 let ParserMatchClass = uimm3_asmoperand;
3558 let PrintMethod = "printUImmBareOperand";
3561 def neon_uimm4_bare : Operand<i64>,
3562 ImmLeaf<i64, [{return Imm < 16;}]> {
3563 let ParserMatchClass = uimm4_asmoperand;
3564 let PrintMethod = "printUImmBareOperand";
3567 class NeonI_LDN_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3568 RegisterOperand VecList, string asmop>
3569 : NeonI_LdOne_Dup<q, r, opcode, size,
3570 (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3571 asmop # "\t$Rt, [$Rn]",
3575 let neverHasSideEffects = 1;
3578 multiclass LDN_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop> {
3579 def _8B : NeonI_LDN_Dup<0, r, opcode, 0b00,
3580 !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3582 def _4H : NeonI_LDN_Dup<0, r, opcode, 0b01,
3583 !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3585 def _2S : NeonI_LDN_Dup<0, r, opcode, 0b10,
3586 !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3588 def _1D : NeonI_LDN_Dup<0, r, opcode, 0b11,
3589 !cast<RegisterOperand>(List # "1D_operand"), asmop>;
3591 def _16B : NeonI_LDN_Dup<1, r, opcode, 0b00,
3592 !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3594 def _8H : NeonI_LDN_Dup<1, r, opcode, 0b01,
3595 !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3597 def _4S : NeonI_LDN_Dup<1, r, opcode, 0b10,
3598 !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3600 def _2D : NeonI_LDN_Dup<1, r, opcode, 0b11,
3601 !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3604 // Load single 1-element structure to all lanes of 1 register
3605 defm LD1R : LDN_Dup_BHSD<0b0, 0b110, "VOne", "ld1r">;
3607 // Load single N-element structure to all lanes of N consecutive
3608 // registers (N = 2,3,4)
3609 defm LD2R : LDN_Dup_BHSD<0b1, 0b110, "VPair", "ld2r">;
3610 defm LD3R : LDN_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r">;
3611 defm LD4R : LDN_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r">;
3614 class LD1R_pattern <ValueType VTy, ValueType DTy, PatFrag LoadOp,
3616 : Pat<(VTy (Neon_vdup (DTy (LoadOp GPR64xsp:$Rn)))),
3617 (VTy (INST GPR64xsp:$Rn))>;
3619 // Match all LD1R instructions
3620 def : LD1R_pattern<v8i8, i32, extloadi8, LD1R_8B>;
3622 def : LD1R_pattern<v16i8, i32, extloadi8, LD1R_16B>;
3624 def : LD1R_pattern<v4i16, i32, extloadi16, LD1R_4H>;
3626 def : LD1R_pattern<v8i16, i32, extloadi16, LD1R_8H>;
3628 def : LD1R_pattern<v2i32, i32, load, LD1R_2S>;
3629 def : LD1R_pattern<v2f32, f32, load, LD1R_2S>;
3631 def : LD1R_pattern<v4i32, i32, load, LD1R_4S>;
3632 def : LD1R_pattern<v4f32, f32, load, LD1R_4S>;
3634 def : LD1R_pattern<v1i64, i64, load, LD1R_1D>;
3635 def : LD1R_pattern<v1f64, f64, load, LD1R_1D>;
3637 def : LD1R_pattern<v2i64, i64, load, LD1R_2D>;
3638 def : LD1R_pattern<v2f64, f64, load, LD1R_2D>;
3641 multiclass VectorList_Bare_BHSD<string PREFIX, int Count,
3642 RegisterClass RegList> {
3643 defm B : VectorList_operands<PREFIX, "B", Count, RegList>;
3644 defm H : VectorList_operands<PREFIX, "H", Count, RegList>;
3645 defm S : VectorList_operands<PREFIX, "S", Count, RegList>;
3646 defm D : VectorList_operands<PREFIX, "D", Count, RegList>;
3649 // Special vector list operand of 128-bit vectors with bare layout.
3650 // i.e. only show ".b", ".h", ".s", ".d"
3651 defm VOne : VectorList_Bare_BHSD<"VOne", 1, FPR128>;
3652 defm VPair : VectorList_Bare_BHSD<"VPair", 2, QPair>;
3653 defm VTriple : VectorList_Bare_BHSD<"VTriple", 3, QTriple>;
3654 defm VQuad : VectorList_Bare_BHSD<"VQuad", 4, QQuad>;
3656 class NeonI_LDN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3657 Operand ImmOp, string asmop>
3658 : NeonI_LdStOne_Lane<1, r, op2_1, op0,
3660 (ins GPR64xsp:$Rn, VList:$src, ImmOp:$lane),
3661 asmop # "\t$Rt[$lane], [$Rn]",
3665 let neverHasSideEffects = 1;
3666 let hasExtraDefRegAllocReq = 1;
3667 let Constraints = "$src = $Rt";
3670 multiclass LDN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3671 def _B : NeonI_LDN_Lane<r, 0b00, op0,
3672 !cast<RegisterOperand>(List # "B_operand"),
3673 neon_uimm4_bare, asmop> {
3674 let Inst{12-10} = lane{2-0};
3675 let Inst{30} = lane{3};
3678 def _H : NeonI_LDN_Lane<r, 0b01, op0,
3679 !cast<RegisterOperand>(List # "H_operand"),
3680 neon_uimm3_bare, asmop> {
3681 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3682 let Inst{30} = lane{2};
3685 def _S : NeonI_LDN_Lane<r, 0b10, op0,
3686 !cast<RegisterOperand>(List # "S_operand"),
3687 neon_uimm2_bare, asmop> {
3688 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3689 let Inst{30} = lane{1};
3692 def _D : NeonI_LDN_Lane<r, 0b10, op0,
3693 !cast<RegisterOperand>(List # "D_operand"),
3694 neon_uimm1_bare, asmop> {
3695 let Inst{12-10} = 0b001;
3696 let Inst{30} = lane{0};
3700 // Load single 1-element structure to one lane of 1 register.
3701 defm LD1LN : LDN_Lane_BHSD<0b0, 0b0, "VOne", "ld1">;
3703 // Load single N-element structure to one lane of N consecutive registers
3705 defm LD2LN : LDN_Lane_BHSD<0b1, 0b0, "VPair", "ld2">;
3706 defm LD3LN : LDN_Lane_BHSD<0b0, 0b1, "VTriple", "ld3">;
3707 defm LD4LN : LDN_Lane_BHSD<0b1, 0b1, "VQuad", "ld4">;
3709 multiclass LD1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3710 Operand ImmOp, Operand ImmOp2, PatFrag LoadOp,
3712 def : Pat<(VTy (vector_insert (VTy VPR64:$src),
3713 (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp:$lane))),
3714 (VTy (EXTRACT_SUBREG
3716 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
3720 def : Pat<(VTy2 (vector_insert (VTy2 VPR128:$src),
3721 (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp2:$lane))),
3722 (VTy2 (INST GPR64xsp:$Rn, VPR128:$src, ImmOp2:$lane))>;
3725 // Match all LD1LN instructions
3726 defm : LD1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3727 extloadi8, LD1LN_B>;
3729 defm : LD1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3730 extloadi16, LD1LN_H>;
3732 defm : LD1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3734 defm : LD1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3737 defm : LD1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3739 defm : LD1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3742 class NeonI_STN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3743 Operand ImmOp, string asmop>
3744 : NeonI_LdStOne_Lane<0, r, op2_1, op0,
3745 (outs), (ins GPR64xsp:$Rn, VList:$Rt, ImmOp:$lane),
3746 asmop # "\t$Rt[$lane], [$Rn]",
3750 let neverHasSideEffects = 1;
3751 let hasExtraDefRegAllocReq = 1;
3754 multiclass STN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3755 def _B : NeonI_STN_Lane<r, 0b00, op0,
3756 !cast<RegisterOperand>(List # "B_operand"),
3757 neon_uimm4_bare, asmop> {
3758 let Inst{12-10} = lane{2-0};
3759 let Inst{30} = lane{3};
3762 def _H : NeonI_STN_Lane<r, 0b01, op0,
3763 !cast<RegisterOperand>(List # "H_operand"),
3764 neon_uimm3_bare, asmop> {
3765 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3766 let Inst{30} = lane{2};
3769 def _S : NeonI_STN_Lane<r, 0b10, op0,
3770 !cast<RegisterOperand>(List # "S_operand"),
3771 neon_uimm2_bare, asmop> {
3772 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3773 let Inst{30} = lane{1};
3776 def _D : NeonI_STN_Lane<r, 0b10, op0,
3777 !cast<RegisterOperand>(List # "D_operand"),
3778 neon_uimm1_bare, asmop>{
3779 let Inst{12-10} = 0b001;
3780 let Inst{30} = lane{0};
3784 // Store single 1-element structure from one lane of 1 register.
3785 defm ST1LN : STN_Lane_BHSD<0b0, 0b0, "VOne", "st1">;
3787 // Store single N-element structure from one lane of N consecutive registers
3789 defm ST2LN : STN_Lane_BHSD<0b1, 0b0, "VPair", "st2">;
3790 defm ST3LN : STN_Lane_BHSD<0b0, 0b1, "VTriple", "st3">;
3791 defm ST4LN : STN_Lane_BHSD<0b1, 0b1, "VQuad", "st4">;
3793 multiclass ST1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3794 Operand ImmOp, Operand ImmOp2, PatFrag StoreOp,
3796 def : Pat<(StoreOp (DTy (vector_extract (VTy VPR64:$Rt), ImmOp:$lane)),
3799 (SUBREG_TO_REG (i64 0), VPR64:$Rt, sub_64),
3802 def : Pat<(StoreOp (DTy (vector_extract (VTy2 VPR128:$Rt), ImmOp2:$lane)),
3804 (INST GPR64xsp:$Rn, VPR128:$Rt, ImmOp2:$lane)>;
3807 // Match all ST1LN instructions
3808 defm : ST1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3809 truncstorei8, ST1LN_B>;
3811 defm : ST1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3812 truncstorei16, ST1LN_H>;
3814 defm : ST1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3816 defm : ST1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3819 defm : ST1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3821 defm : ST1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3824 // End of vector load/store single N-element structure (class SIMD lsone).
3827 // The following are post-index load/store single N-element instructions
3828 // (class SIMD lsone-post)
3830 multiclass NeonI_LDN_WB_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3831 RegisterOperand VecList, Operand ImmTy,
3833 let mayLoad = 1, neverHasSideEffects = 1, Constraints = "$wb = $Rn",
3834 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
3835 def _fixed : NeonI_LdOne_Dup_Post<q, r, opcode, size,
3836 (outs VecList:$Rt, GPR64xsp:$wb),
3837 (ins GPR64xsp:$Rn, ImmTy:$amt),
3838 asmop # "\t$Rt, [$Rn], $amt",
3844 def _register : NeonI_LdOne_Dup_Post<q, r, opcode, size,
3845 (outs VecList:$Rt, GPR64xsp:$wb),
3846 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3847 asmop # "\t$Rt, [$Rn], $Rm",
3853 multiclass LDWB_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop,
3854 Operand uimm_b, Operand uimm_h,
3855 Operand uimm_s, Operand uimm_d> {
3856 defm _8B : NeonI_LDN_WB_Dup<0, r, opcode, 0b00,
3857 !cast<RegisterOperand>(List # "8B_operand"),
3860 defm _4H : NeonI_LDN_WB_Dup<0, r, opcode, 0b01,
3861 !cast<RegisterOperand>(List # "4H_operand"),
3864 defm _2S : NeonI_LDN_WB_Dup<0, r, opcode, 0b10,
3865 !cast<RegisterOperand>(List # "2S_operand"),
3868 defm _1D : NeonI_LDN_WB_Dup<0, r, opcode, 0b11,
3869 !cast<RegisterOperand>(List # "1D_operand"),
3872 defm _16B : NeonI_LDN_WB_Dup<1, r, opcode, 0b00,
3873 !cast<RegisterOperand>(List # "16B_operand"),
3876 defm _8H : NeonI_LDN_WB_Dup<1, r, opcode, 0b01,
3877 !cast<RegisterOperand>(List # "8H_operand"),
3880 defm _4S : NeonI_LDN_WB_Dup<1, r, opcode, 0b10,
3881 !cast<RegisterOperand>(List # "4S_operand"),
3884 defm _2D : NeonI_LDN_WB_Dup<1, r, opcode, 0b11,
3885 !cast<RegisterOperand>(List # "2D_operand"),
3889 // Post-index load single 1-element structure to all lanes of 1 register
3890 defm LD1R_WB : LDWB_Dup_BHSD<0b0, 0b110, "VOne", "ld1r", uimm_exact1,
3891 uimm_exact2, uimm_exact4, uimm_exact8>;
3893 // Post-index load single N-element structure to all lanes of N consecutive
3894 // registers (N = 2,3,4)
3895 defm LD2R_WB : LDWB_Dup_BHSD<0b1, 0b110, "VPair", "ld2r", uimm_exact2,
3896 uimm_exact4, uimm_exact8, uimm_exact16>;
3897 defm LD3R_WB : LDWB_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r", uimm_exact3,
3898 uimm_exact6, uimm_exact12, uimm_exact24>;
3899 defm LD4R_WB : LDWB_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r", uimm_exact4,
3900 uimm_exact8, uimm_exact16, uimm_exact32>;
3902 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
3903 Constraints = "$Rn = $wb, $Rt = $src",
3904 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
3905 class LDN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3906 Operand ImmTy, Operand ImmOp, string asmop>
3907 : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
3908 (outs VList:$Rt, GPR64xsp:$wb),
3909 (ins GPR64xsp:$Rn, ImmTy:$amt,
3910 VList:$src, ImmOp:$lane),
3911 asmop # "\t$Rt[$lane], [$Rn], $amt",
3917 class LDN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3918 Operand ImmTy, Operand ImmOp, string asmop>
3919 : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
3920 (outs VList:$Rt, GPR64xsp:$wb),
3921 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm,
3922 VList:$src, ImmOp:$lane),
3923 asmop # "\t$Rt[$lane], [$Rn], $Rm",
3928 multiclass LD_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
3929 Operand uimm_b, Operand uimm_h,
3930 Operand uimm_s, Operand uimm_d> {
3931 def _B_fixed : LDN_WBFx_Lane<r, 0b00, op0,
3932 !cast<RegisterOperand>(List # "B_operand"),
3933 uimm_b, neon_uimm4_bare, asmop> {
3934 let Inst{12-10} = lane{2-0};
3935 let Inst{30} = lane{3};
3938 def _B_register : LDN_WBReg_Lane<r, 0b00, op0,
3939 !cast<RegisterOperand>(List # "B_operand"),
3940 uimm_b, neon_uimm4_bare, asmop> {
3941 let Inst{12-10} = lane{2-0};
3942 let Inst{30} = lane{3};
3945 def _H_fixed : LDN_WBFx_Lane<r, 0b01, op0,
3946 !cast<RegisterOperand>(List # "H_operand"),
3947 uimm_h, neon_uimm3_bare, asmop> {
3948 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3949 let Inst{30} = lane{2};
3952 def _H_register : LDN_WBReg_Lane<r, 0b01, op0,
3953 !cast<RegisterOperand>(List # "H_operand"),
3954 uimm_h, neon_uimm3_bare, asmop> {
3955 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3956 let Inst{30} = lane{2};
3959 def _S_fixed : LDN_WBFx_Lane<r, 0b10, op0,
3960 !cast<RegisterOperand>(List # "S_operand"),
3961 uimm_s, neon_uimm2_bare, asmop> {
3962 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3963 let Inst{30} = lane{1};
3966 def _S_register : LDN_WBReg_Lane<r, 0b10, op0,
3967 !cast<RegisterOperand>(List # "S_operand"),
3968 uimm_s, neon_uimm2_bare, asmop> {
3969 let Inst{12-10} = {lane{0}, 0b0, 0b0};
3970 let Inst{30} = lane{1};
3973 def _D_fixed : LDN_WBFx_Lane<r, 0b10, op0,
3974 !cast<RegisterOperand>(List # "D_operand"),
3975 uimm_d, neon_uimm1_bare, asmop> {
3976 let Inst{12-10} = 0b001;
3977 let Inst{30} = lane{0};
3980 def _D_register : LDN_WBReg_Lane<r, 0b10, op0,
3981 !cast<RegisterOperand>(List # "D_operand"),
3982 uimm_d, neon_uimm1_bare, asmop> {
3983 let Inst{12-10} = 0b001;
3984 let Inst{30} = lane{0};
3988 // Post-index load single 1-element structure to one lane of 1 register.
3989 defm LD1LN_WB : LD_Lane_WB_BHSD<0b0, 0b0, "VOne", "ld1", uimm_exact1,
3990 uimm_exact2, uimm_exact4, uimm_exact8>;
3992 // Post-index load single N-element structure to one lane of N consecutive
3995 defm LD2LN_WB : LD_Lane_WB_BHSD<0b1, 0b0, "VPair", "ld2", uimm_exact2,
3996 uimm_exact4, uimm_exact8, uimm_exact16>;
3997 defm LD3LN_WB : LD_Lane_WB_BHSD<0b0, 0b1, "VTriple", "ld3", uimm_exact3,
3998 uimm_exact6, uimm_exact12, uimm_exact24>;
3999 defm LD4LN_WB : LD_Lane_WB_BHSD<0b1, 0b1, "VQuad", "ld4", uimm_exact4,
4000 uimm_exact8, uimm_exact16, uimm_exact32>;
4002 let mayStore = 1, neverHasSideEffects = 1,
4003 hasExtraDefRegAllocReq = 1, Constraints = "$Rn = $wb",
4004 DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4005 class STN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4006 Operand ImmTy, Operand ImmOp, string asmop>
4007 : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4008 (outs GPR64xsp:$wb),
4009 (ins GPR64xsp:$Rn, ImmTy:$amt,
4010 VList:$Rt, ImmOp:$lane),
4011 asmop # "\t$Rt[$lane], [$Rn], $amt",
4017 class STN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4018 Operand ImmTy, Operand ImmOp, string asmop>
4019 : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4020 (outs GPR64xsp:$wb),
4021 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VList:$Rt,
4023 asmop # "\t$Rt[$lane], [$Rn], $Rm",
4028 multiclass ST_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4029 Operand uimm_b, Operand uimm_h,
4030 Operand uimm_s, Operand uimm_d> {
4031 def _B_fixed : STN_WBFx_Lane<r, 0b00, op0,
4032 !cast<RegisterOperand>(List # "B_operand"),
4033 uimm_b, neon_uimm4_bare, asmop> {
4034 let Inst{12-10} = lane{2-0};
4035 let Inst{30} = lane{3};
4038 def _B_register : STN_WBReg_Lane<r, 0b00, op0,
4039 !cast<RegisterOperand>(List # "B_operand"),
4040 uimm_b, neon_uimm4_bare, asmop> {
4041 let Inst{12-10} = lane{2-0};
4042 let Inst{30} = lane{3};
4045 def _H_fixed : STN_WBFx_Lane<r, 0b01, op0,
4046 !cast<RegisterOperand>(List # "H_operand"),
4047 uimm_h, neon_uimm3_bare, asmop> {
4048 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4049 let Inst{30} = lane{2};
4052 def _H_register : STN_WBReg_Lane<r, 0b01, op0,
4053 !cast<RegisterOperand>(List # "H_operand"),
4054 uimm_h, neon_uimm3_bare, asmop> {
4055 let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4056 let Inst{30} = lane{2};
4059 def _S_fixed : STN_WBFx_Lane<r, 0b10, op0,
4060 !cast<RegisterOperand>(List # "S_operand"),
4061 uimm_s, neon_uimm2_bare, asmop> {
4062 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4063 let Inst{30} = lane{1};
4066 def _S_register : STN_WBReg_Lane<r, 0b10, op0,
4067 !cast<RegisterOperand>(List # "S_operand"),
4068 uimm_s, neon_uimm2_bare, asmop> {
4069 let Inst{12-10} = {lane{0}, 0b0, 0b0};
4070 let Inst{30} = lane{1};
4073 def _D_fixed : STN_WBFx_Lane<r, 0b10, op0,
4074 !cast<RegisterOperand>(List # "D_operand"),
4075 uimm_d, neon_uimm1_bare, asmop> {
4076 let Inst{12-10} = 0b001;
4077 let Inst{30} = lane{0};
4080 def _D_register : STN_WBReg_Lane<r, 0b10, op0,
4081 !cast<RegisterOperand>(List # "D_operand"),
4082 uimm_d, neon_uimm1_bare, asmop> {
4083 let Inst{12-10} = 0b001;
4084 let Inst{30} = lane{0};
4088 // Post-index store single 1-element structure from one lane of 1 register.
4089 defm ST1LN_WB : ST_Lane_WB_BHSD<0b0, 0b0, "VOne", "st1", uimm_exact1,
4090 uimm_exact2, uimm_exact4, uimm_exact8>;
4092 // Post-index store single N-element structure from one lane of N consecutive
4093 // registers (N = 2,3,4)
4094 defm ST2LN_WB : ST_Lane_WB_BHSD<0b1, 0b0, "VPair", "st2", uimm_exact2,
4095 uimm_exact4, uimm_exact8, uimm_exact16>;
4096 defm ST3LN_WB : ST_Lane_WB_BHSD<0b0, 0b1, "VTriple", "st3", uimm_exact3,
4097 uimm_exact6, uimm_exact12, uimm_exact24>;
4098 defm ST4LN_WB : ST_Lane_WB_BHSD<0b1, 0b1, "VQuad", "st4", uimm_exact4,
4099 uimm_exact8, uimm_exact16, uimm_exact32>;
4101 // End of post-index load/store single N-element instructions
4102 // (class SIMD lsone-post)
4104 // Neon Scalar instructions implementation
4105 // Scalar Three Same
4107 class NeonI_Scalar3Same_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4109 : NeonI_Scalar3Same<u, size, opcode,
4110 (outs FPRC:$Rd), (ins FPRC:$Rn, FPRC:$Rm),
4111 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4115 class NeonI_Scalar3Same_D_size<bit u, bits<5> opcode, string asmop>
4116 : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4118 multiclass NeonI_Scalar3Same_HS_sizes<bit u, bits<5> opcode, string asmop,
4119 bit Commutable = 0> {
4120 let isCommutable = Commutable in {
4121 def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4122 def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4126 multiclass NeonI_Scalar3Same_SD_sizes<bit u, bit size_high, bits<5> opcode,
4127 string asmop, bit Commutable = 0> {
4128 let isCommutable = Commutable in {
4129 def sss : NeonI_Scalar3Same_size<u, {size_high, 0b0}, opcode, asmop, FPR32>;
4130 def ddd : NeonI_Scalar3Same_size<u, {size_high, 0b1}, opcode, asmop, FPR64>;
4134 multiclass NeonI_Scalar3Same_BHSD_sizes<bit u, bits<5> opcode,
4135 string asmop, bit Commutable = 0> {
4136 let isCommutable = Commutable in {
4137 def bbb : NeonI_Scalar3Same_size<u, 0b00, opcode, asmop, FPR8>;
4138 def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4139 def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4140 def ddd : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4144 multiclass Neon_Scalar3Same_D_size_patterns<SDPatternOperator opnode,
4145 Instruction INSTD> {
4146 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4147 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4150 multiclass Neon_Scalar3Same_BHSD_size_patterns<SDPatternOperator opnode,
4155 : Neon_Scalar3Same_D_size_patterns<opnode, INSTD> {
4156 def: Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (v1i8 FPR8:$Rm))),
4157 (INSTB FPR8:$Rn, FPR8:$Rm)>;
4159 def: Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4160 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4162 def: Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4163 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4166 class Neon_Scalar3Same_cmp_D_size_patterns<SDPatternOperator opnode,
4168 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4169 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4171 multiclass Neon_Scalar3Same_HS_size_patterns<SDPatternOperator opnode,
4173 Instruction INSTS> {
4174 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4175 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4176 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4177 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4180 multiclass Neon_Scalar3Same_fabd_SD_size_patterns<SDPatternOperator opnode,
4182 Instruction INSTD> {
4183 def : Pat<(f32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
4184 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4185 def : Pat<(f64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
4186 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4189 multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
4190 SDPatternOperator opnodeV,
4192 Instruction INSTD> {
4193 def : Pat<(f32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
4194 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4195 def : Pat<(f64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
4196 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4197 def : Pat<(v1f64 (opnodeV (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
4198 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4201 multiclass Neon_Scalar3Same_cmp_SD_size_patterns<SDPatternOperator opnode,
4203 Instruction INSTD> {
4204 def : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
4205 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4206 def : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
4207 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4210 class Neon_Scalar3Same_cmp_V1_D_size_patterns<CondCode CC,
4212 : Pat<(v1i64 (Neon_cmp (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm), CC)),
4213 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4215 // Scalar Three Different
4217 class NeonI_Scalar3Diff_size<bit u, bits<2> size, bits<4> opcode, string asmop,
4218 RegisterClass FPRCD, RegisterClass FPRCS>
4219 : NeonI_Scalar3Diff<u, size, opcode,
4220 (outs FPRCD:$Rd), (ins FPRCS:$Rn, FPRCS:$Rm),
4221 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4225 multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> {
4226 def shh : NeonI_Scalar3Diff_size<u, 0b01, opcode, asmop, FPR32, FPR16>;
4227 def dss : NeonI_Scalar3Diff_size<u, 0b10, opcode, asmop, FPR64, FPR32>;
4230 multiclass NeonI_Scalar3Diff_ml_HS_size<bit u, bits<4> opcode, string asmop> {
4231 let Constraints = "$Src = $Rd" in {
4232 def shh : NeonI_Scalar3Diff<u, 0b01, opcode,
4233 (outs FPR32:$Rd), (ins FPR32:$Src, FPR16:$Rn, FPR16:$Rm),
4234 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4237 def dss : NeonI_Scalar3Diff<u, 0b10, opcode,
4238 (outs FPR64:$Rd), (ins FPR64:$Src, FPR32:$Rn, FPR32:$Rm),
4239 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4245 multiclass Neon_Scalar3Diff_HS_size_patterns<SDPatternOperator opnode,
4247 Instruction INSTS> {
4248 def : Pat<(v1i32 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4249 (INSTH FPR16:$Rn, FPR16:$Rm)>;
4250 def : Pat<(v1i64 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4251 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4254 multiclass Neon_Scalar3Diff_ml_HS_size_patterns<SDPatternOperator opnode,
4256 Instruction INSTS> {
4257 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4258 (INSTH FPR32:$Src, FPR16:$Rn, FPR16:$Rm)>;
4259 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4260 (INSTS FPR64:$Src, FPR32:$Rn, FPR32:$Rm)>;
4263 // Scalar Two Registers Miscellaneous
4265 class NeonI_Scalar2SameMisc_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4266 RegisterClass FPRCD, RegisterClass FPRCS>
4267 : NeonI_Scalar2SameMisc<u, size, opcode,
4268 (outs FPRCD:$Rd), (ins FPRCS:$Rn),
4269 !strconcat(asmop, "\t$Rd, $Rn"),
4273 multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
4275 def ss : NeonI_Scalar2SameMisc_size<u, {size_high, 0b0}, opcode, asmop, FPR32,
4277 def dd : NeonI_Scalar2SameMisc_size<u, {size_high, 0b1}, opcode, asmop, FPR64,
4281 multiclass NeonI_Scalar2SameMisc_D_size<bit u, bits<5> opcode, string asmop> {
4282 def dd : NeonI_Scalar2SameMisc_size<u, 0b11, opcode, asmop, FPR64, FPR64>;
4285 multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>
4286 : NeonI_Scalar2SameMisc_D_size<u, opcode, asmop> {
4287 def bb : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR8>;
4288 def hh : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR16>;
4289 def ss : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR32>;
4292 class NeonI_Scalar2SameMisc_fcvtxn_D_size<bit u, bits<5> opcode, string asmop>
4293 : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR32, FPR64>;
4295 multiclass NeonI_Scalar2SameMisc_narrow_HSD_size<bit u, bits<5> opcode,
4297 def bh : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR16>;
4298 def hs : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR32>;
4299 def sd : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR64>;
4302 class NeonI_Scalar2SameMisc_accum_size<bit u, bits<2> size, bits<5> opcode,
4303 string asmop, RegisterClass FPRC>
4304 : NeonI_Scalar2SameMisc<u, size, opcode,
4305 (outs FPRC:$Rd), (ins FPRC:$Src, FPRC:$Rn),
4306 !strconcat(asmop, "\t$Rd, $Rn"),
4310 multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
4313 let Constraints = "$Src = $Rd" in {
4314 def bb : NeonI_Scalar2SameMisc_accum_size<u, 0b00, opcode, asmop, FPR8>;
4315 def hh : NeonI_Scalar2SameMisc_accum_size<u, 0b01, opcode, asmop, FPR16>;
4316 def ss : NeonI_Scalar2SameMisc_accum_size<u, 0b10, opcode, asmop, FPR32>;
4317 def dd : NeonI_Scalar2SameMisc_accum_size<u, 0b11, opcode, asmop, FPR64>;
4321 class Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<SDPatternOperator opnode,
4323 : Pat<(f32 (opnode (f64 FPR64:$Rn))),
4326 multiclass Neon_Scalar2SameMisc_fcvt_SD_size_patterns<SDPatternOperator opnode,
4328 Instruction INSTD> {
4329 def : Pat<(v1i32 (opnode (f32 FPR32:$Rn))),
4331 def : Pat<(v1i64 (opnode (f64 FPR64:$Rn))),
4335 class Neon_Scalar2SameMisc_vcvt_D_size_patterns<SDPatternOperator opnode,
4337 : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))),
4340 multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator opnode,
4342 Instruction INSTD> {
4343 def : Pat<(f32 (opnode (v1i32 FPR32:$Rn))),
4345 def : Pat<(f64 (opnode (v1i64 FPR64:$Rn))),
4349 multiclass Neon_Scalar2SameMisc_SD_size_patterns<SDPatternOperator opnode,
4351 Instruction INSTD> {
4352 def : Pat<(f32 (opnode (f32 FPR32:$Rn))),
4354 def : Pat<(f64 (opnode (f64 FPR64:$Rn))),
4358 class Neon_Scalar2SameMisc_V1_D_size_patterns<SDPatternOperator opnode,
4360 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))),
4363 class NeonI_Scalar2SameMisc_cmpz_D_size<bit u, bits<5> opcode, string asmop>
4364 : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4365 (outs FPR64:$Rd), (ins FPR64:$Rn, neon_uimm0:$Imm),
4366 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4370 multiclass NeonI_Scalar2SameMisc_cmpz_SD_size<bit u, bits<5> opcode,
4372 def ssi : NeonI_Scalar2SameMisc<u, 0b10, opcode,
4373 (outs FPR32:$Rd), (ins FPR32:$Rn, fpz32:$FPImm),
4374 !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4377 def ddi : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4378 (outs FPR64:$Rd), (ins FPR64:$Rn, fpz32:$FPImm),
4379 !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4384 class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode,
4386 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4387 (v1i64 (bitconvert (v8i8 Neon_AllZero))))),
4388 (INSTD FPR64:$Rn, 0)>;
4390 class Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<CondCode CC,
4392 : Pat<(v1i64 (Neon_cmpz (v1i64 FPR64:$Rn),
4393 (i32 neon_uimm0:$Imm), CC)),
4394 (INSTD FPR64:$Rn, neon_uimm0:$Imm)>;
4396 multiclass Neon_Scalar2SameMisc_cmpz_SD_size_patterns<SDPatternOperator opnode,
4398 Instruction INSTD> {
4399 def : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (f32 fpz32:$FPImm))),
4400 (INSTS FPR32:$Rn, fpz32:$FPImm)>;
4401 def : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (f32 fpz32:$FPImm))),
4402 (INSTD FPR64:$Rn, fpz32:$FPImm)>;
4405 multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode,
4406 Instruction INSTD> {
4407 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))),
4411 multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
4416 : Neon_Scalar2SameMisc_D_size_patterns<opnode, INSTD> {
4417 def : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn))),
4419 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn))),
4421 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn))),
4425 multiclass Neon_Scalar2SameMisc_narrow_HSD_size_patterns<
4426 SDPatternOperator opnode,
4429 Instruction INSTD> {
4430 def : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn))),
4432 def : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn))),
4434 def : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn))),
4439 multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns<
4440 SDPatternOperator opnode,
4444 Instruction INSTD> {
4445 def : Pat<(v1i8 (opnode (v1i8 FPR8:$Src), (v1i8 FPR8:$Rn))),
4446 (INSTB FPR8:$Src, FPR8:$Rn)>;
4447 def : Pat<(v1i16 (opnode (v1i16 FPR16:$Src), (v1i16 FPR16:$Rn))),
4448 (INSTH FPR16:$Src, FPR16:$Rn)>;
4449 def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i32 FPR32:$Rn))),
4450 (INSTS FPR32:$Src, FPR32:$Rn)>;
4451 def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn))),
4452 (INSTD FPR64:$Src, FPR64:$Rn)>;
4455 // Scalar Shift By Immediate
4457 class NeonI_ScalarShiftImm_size<bit u, bits<5> opcode, string asmop,
4458 RegisterClass FPRC, Operand ImmTy>
4459 : NeonI_ScalarShiftImm<u, opcode,
4460 (outs FPRC:$Rd), (ins FPRC:$Rn, ImmTy:$Imm),
4461 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4464 multiclass NeonI_ScalarShiftRightImm_D_size<bit u, bits<5> opcode,
4466 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4468 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4469 let Inst{21-16} = Imm;
4473 multiclass NeonI_ScalarShiftRightImm_BHSD_size<bit u, bits<5> opcode,
4475 : NeonI_ScalarShiftRightImm_D_size<u, opcode, asmop> {
4476 def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shr_imm8> {
4478 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4479 let Inst{18-16} = Imm;
4481 def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shr_imm16> {
4483 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4484 let Inst{19-16} = Imm;
4486 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4488 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4489 let Inst{20-16} = Imm;
4493 multiclass NeonI_ScalarShiftLeftImm_D_size<bit u, bits<5> opcode,
4495 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shl_imm64> {
4497 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4498 let Inst{21-16} = Imm;
4502 multiclass NeonI_ScalarShiftLeftImm_BHSD_size<bit u, bits<5> opcode,
4504 : NeonI_ScalarShiftLeftImm_D_size<u, opcode, asmop> {
4505 def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shl_imm8> {
4507 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4508 let Inst{18-16} = Imm;
4510 def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shl_imm16> {
4512 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4513 let Inst{19-16} = Imm;
4515 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shl_imm32> {
4517 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4518 let Inst{20-16} = Imm;
4522 class NeonI_ScalarShiftRightImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4523 : NeonI_ScalarShiftImm<u, opcode,
4525 (ins FPR64:$Src, FPR64:$Rn, shr_imm64:$Imm),
4526 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4529 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4530 let Inst{21-16} = Imm;
4531 let Constraints = "$Src = $Rd";
4534 class NeonI_ScalarShiftLeftImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4535 : NeonI_ScalarShiftImm<u, opcode,
4537 (ins FPR64:$Src, FPR64:$Rn, shl_imm64:$Imm),
4538 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4541 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4542 let Inst{21-16} = Imm;
4543 let Constraints = "$Src = $Rd";
4546 class NeonI_ScalarShiftImm_narrow_size<bit u, bits<5> opcode, string asmop,
4547 RegisterClass FPRCD, RegisterClass FPRCS,
4549 : NeonI_ScalarShiftImm<u, opcode,
4550 (outs FPRCD:$Rd), (ins FPRCS:$Rn, ImmTy:$Imm),
4551 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4554 multiclass NeonI_ScalarShiftImm_narrow_HSD_size<bit u, bits<5> opcode,
4556 def bhi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR8, FPR16,
4559 let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4560 let Inst{18-16} = Imm;
4562 def hsi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR16, FPR32,
4565 let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4566 let Inst{19-16} = Imm;
4568 def sdi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR32, FPR64,
4571 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4572 let Inst{20-16} = Imm;
4576 multiclass NeonI_ScalarShiftImm_cvt_SD_size<bit u, bits<5> opcode, string asmop> {
4577 def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4579 let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4580 let Inst{20-16} = Imm;
4582 def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4584 let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4585 let Inst{21-16} = Imm;
4589 multiclass Neon_ScalarShiftRImm_D_size_patterns<SDPatternOperator opnode,
4590 Instruction INSTD> {
4591 def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4592 (INSTD FPR64:$Rn, imm:$Imm)>;
4595 multiclass Neon_ScalarShiftLImm_D_size_patterns<SDPatternOperator opnode,
4596 Instruction INSTD> {
4597 def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shl_imm64:$Imm))),
4598 (INSTD FPR64:$Rn, imm:$Imm)>;
4601 class Neon_ScalarShiftImm_V1_D_size_patterns<SDPatternOperator opnode,
4603 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4604 (v1i64 (Neon_vdup (i32 shr_imm64:$Imm))))),
4605 (INSTD FPR64:$Rn, imm:$Imm)>;
4607 multiclass Neon_ScalarShiftLImm_BHSD_size_patterns<SDPatternOperator opnode,
4612 : Neon_ScalarShiftLImm_D_size_patterns<opnode, INSTD> {
4613 def bbi : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (i32 shl_imm8:$Imm))),
4614 (INSTB FPR8:$Rn, imm:$Imm)>;
4615 def hhi : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (i32 shl_imm16:$Imm))),
4616 (INSTH FPR16:$Rn, imm:$Imm)>;
4617 def ssi : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (i32 shl_imm32:$Imm))),
4618 (INSTS FPR32:$Rn, imm:$Imm)>;
4621 class Neon_ScalarShiftLImm_accum_D_size_patterns<SDPatternOperator opnode,
4623 : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4624 (i32 shl_imm64:$Imm))),
4625 (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4627 class Neon_ScalarShiftRImm_accum_D_size_patterns<SDPatternOperator opnode,
4629 : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4630 (i32 shr_imm64:$Imm))),
4631 (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4633 multiclass Neon_ScalarShiftImm_narrow_HSD_size_patterns<
4634 SDPatternOperator opnode,
4637 Instruction INSTD> {
4638 def bhi : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn), (i32 shr_imm16:$Imm))),
4639 (INSTH FPR16:$Rn, imm:$Imm)>;
4640 def hsi : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4641 (INSTS FPR32:$Rn, imm:$Imm)>;
4642 def sdi : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4643 (INSTD FPR64:$Rn, imm:$Imm)>;
4646 multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns<SDPatternOperator opnode,
4648 Instruction INSTD> {
4649 def ssi : Pat<(f32 (opnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4650 (INSTS FPR32:$Rn, imm:$Imm)>;
4651 def ddi : Pat<(f64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4652 (INSTD FPR64:$Rn, imm:$Imm)>;
4655 multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns<SDPatternOperator opnode,
4657 Instruction INSTD> {
4658 def ssi : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4659 (INSTS FPR32:$Rn, imm:$Imm)>;
4660 def ddi : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4661 (INSTD FPR64:$Rn, imm:$Imm)>;
4664 // Scalar Signed Shift Right (Immediate)
4665 defm SSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00000, "sshr">;
4666 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrds_n, SSHRddi>;
4667 // Pattern to match llvm.arm.* intrinsic.
4668 def : Neon_ScalarShiftImm_V1_D_size_patterns<sra, SSHRddi>;
4670 // Scalar Unsigned Shift Right (Immediate)
4671 defm USHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00000, "ushr">;
4672 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrdu_n, USHRddi>;
4673 // Pattern to match llvm.arm.* intrinsic.
4674 def : Neon_ScalarShiftImm_V1_D_size_patterns<srl, USHRddi>;
4676 // Scalar Signed Rounding Shift Right (Immediate)
4677 defm SRSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00100, "srshr">;
4678 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vsrshr, SRSHRddi>;
4680 // Scalar Unigned Rounding Shift Right (Immediate)
4681 defm URSHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00100, "urshr">;
4682 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vurshr, URSHRddi>;
4684 // Scalar Signed Shift Right and Accumulate (Immediate)
4685 def SSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00010, "ssra">;
4686 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4687 <int_aarch64_neon_vsrads_n, SSRA>;
4689 // Scalar Unsigned Shift Right and Accumulate (Immediate)
4690 def USRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00010, "usra">;
4691 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4692 <int_aarch64_neon_vsradu_n, USRA>;
4694 // Scalar Signed Rounding Shift Right and Accumulate (Immediate)
4695 def SRSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00110, "srsra">;
4696 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4697 <int_aarch64_neon_vrsrads_n, SRSRA>;
4699 // Scalar Unsigned Rounding Shift Right and Accumulate (Immediate)
4700 def URSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00110, "ursra">;
4701 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4702 <int_aarch64_neon_vrsradu_n, URSRA>;
4704 // Scalar Shift Left (Immediate)
4705 defm SHL : NeonI_ScalarShiftLeftImm_D_size<0b0, 0b01010, "shl">;
4706 defm : Neon_ScalarShiftLImm_D_size_patterns<int_aarch64_neon_vshld_n, SHLddi>;
4707 // Pattern to match llvm.arm.* intrinsic.
4708 def : Neon_ScalarShiftImm_V1_D_size_patterns<shl, SHLddi>;
4710 // Signed Saturating Shift Left (Immediate)
4711 defm SQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b0, 0b01110, "sqshl">;
4712 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshls_n,
4714 SQSHLssi, SQSHLddi>;
4715 // Pattern to match llvm.arm.* intrinsic.
4716 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_sqrshlImm, SQSHLddi>;
4718 // Unsigned Saturating Shift Left (Immediate)
4719 defm UQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01110, "uqshl">;
4720 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshlu_n,
4722 UQSHLssi, UQSHLddi>;
4723 // Pattern to match llvm.arm.* intrinsic.
4724 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_uqrshlImm, UQSHLddi>;
4726 // Signed Saturating Shift Left Unsigned (Immediate)
4727 defm SQSHLU : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01100, "sqshlu">;
4728 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vsqshlu,
4729 SQSHLUbbi, SQSHLUhhi,
4730 SQSHLUssi, SQSHLUddi>;
4732 // Shift Right And Insert (Immediate)
4733 def SRI : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b01000, "sri">;
4734 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4735 <int_aarch64_neon_vsri, SRI>;
4737 // Shift Left And Insert (Immediate)
4738 def SLI : NeonI_ScalarShiftLeftImm_accum_D_size<0b1, 0b01010, "sli">;
4739 def : Neon_ScalarShiftLImm_accum_D_size_patterns
4740 <int_aarch64_neon_vsli, SLI>;
4742 // Signed Saturating Shift Right Narrow (Immediate)
4743 defm SQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10010, "sqshrn">;
4744 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrn,
4745 SQSHRNbhi, SQSHRNhsi,
4748 // Unsigned Saturating Shift Right Narrow (Immediate)
4749 defm UQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10010, "uqshrn">;
4750 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqshrn,
4751 UQSHRNbhi, UQSHRNhsi,
4754 // Signed Saturating Rounded Shift Right Narrow (Immediate)
4755 defm SQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10011, "sqrshrn">;
4756 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrn,
4757 SQRSHRNbhi, SQRSHRNhsi,
4760 // Unsigned Saturating Rounded Shift Right Narrow (Immediate)
4761 defm UQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10011, "uqrshrn">;
4762 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqrshrn,
4763 UQRSHRNbhi, UQRSHRNhsi,
4766 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
4767 defm SQSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10000, "sqshrun">;
4768 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrun,
4769 SQSHRUNbhi, SQSHRUNhsi,
4772 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
4773 defm SQRSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10001, "sqrshrun">;
4774 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrun,
4775 SQRSHRUNbhi, SQRSHRUNhsi,
4778 // Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
4779 defm SCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11100, "scvtf">;
4780 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtfxs2fp_n,
4781 SCVTF_Nssi, SCVTF_Nddi>;
4783 // Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
4784 defm UCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11100, "ucvtf">;
4785 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtfxu2fp_n,
4786 UCVTF_Nssi, UCVTF_Nddi>;
4788 // Scalar Floating-point Convert To Signed Fixed-point (Immediate)
4789 defm FCVTZS_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11111, "fcvtzs">;
4790 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvtfp2fxs_n,
4791 FCVTZS_Nssi, FCVTZS_Nddi>;
4793 // Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
4794 defm FCVTZU_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11111, "fcvtzu">;
4795 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvtfp2fxu_n,
4796 FCVTZU_Nssi, FCVTZU_Nddi>;
4798 // Patterns For Convert Instructions Between v1f64 and v1i64
4799 class Neon_ScalarShiftImm_cvtf_v1f64_pattern<SDPatternOperator opnode,
4801 : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4802 (INST FPR64:$Rn, imm:$Imm)>;
4804 class Neon_ScalarShiftImm_fcvt_v1f64_pattern<SDPatternOperator opnode,
4806 : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4807 (INST FPR64:$Rn, imm:$Imm)>;
4809 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxs2fp,
4812 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxu2fp,
4815 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxs,
4818 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxu,
4821 // Scalar Integer Add
4822 let isCommutable = 1 in {
4823 def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
4826 // Scalar Integer Sub
4827 def SUBddd : NeonI_Scalar3Same_D_size<0b1, 0b10000, "sub">;
4829 // Pattern for Scalar Integer Add and Sub with D register only
4830 defm : Neon_Scalar3Same_D_size_patterns<add, ADDddd>;
4831 defm : Neon_Scalar3Same_D_size_patterns<sub, SUBddd>;
4833 // Patterns to match llvm.aarch64.* intrinsic for Scalar Add, Sub
4834 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vaddds, ADDddd>;
4835 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vadddu, ADDddd>;
4836 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubds, SUBddd>;
4837 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubdu, SUBddd>;
4839 // Scalar Integer Saturating Add (Signed, Unsigned)
4840 defm SQADD : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00001, "sqadd", 1>;
4841 defm UQADD : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00001, "uqadd", 1>;
4843 // Scalar Integer Saturating Sub (Signed, Unsigned)
4844 defm SQSUB : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00101, "sqsub", 0>;
4845 defm UQSUB : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00101, "uqsub", 0>;
4848 // Patterns to match llvm.aarch64.* intrinsic for
4849 // Scalar Integer Saturating Add, Sub (Signed, Unsigned)
4850 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqadds, SQADDbbb,
4851 SQADDhhh, SQADDsss, SQADDddd>;
4852 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqaddu, UQADDbbb,
4853 UQADDhhh, UQADDsss, UQADDddd>;
4854 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubs, SQSUBbbb,
4855 SQSUBhhh, SQSUBsss, SQSUBddd>;
4856 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubu, UQSUBbbb,
4857 UQSUBhhh, UQSUBsss, UQSUBddd>;
4859 // Scalar Integer Saturating Doubling Multiply Half High
4860 defm SQDMULH : NeonI_Scalar3Same_HS_sizes<0b0, 0b10110, "sqdmulh", 1>;
4862 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4863 defm SQRDMULH : NeonI_Scalar3Same_HS_sizes<0b1, 0b10110, "sqrdmulh", 1>;
4865 // Patterns to match llvm.arm.* intrinsic for
4866 // Scalar Integer Saturating Doubling Multiply Half High and
4867 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4868 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqdmulh, SQDMULHhhh,
4870 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqrdmulh, SQRDMULHhhh,
4873 // Scalar Floating-point Multiply Extended
4874 defm FMULX : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11011, "fmulx", 1>;
4876 // Scalar Floating-point Reciprocal Step
4877 defm FRECPS : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11111, "frecps", 0>;
4878 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vrecps,
4879 int_arm_neon_vrecps, FRECPSsss,
4882 // Scalar Floating-point Reciprocal Square Root Step
4883 defm FRSQRTS : NeonI_Scalar3Same_SD_sizes<0b0, 0b1, 0b11111, "frsqrts", 0>;
4884 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vrsqrts,
4885 int_arm_neon_vrsqrts, FRSQRTSsss,
4887 def : Pat<(v1f64 (fsqrt (v1f64 FPR64:$Rn))), (FSQRTdd FPR64:$Rn)>;
4889 // Patterns to match llvm.aarch64.* intrinsic for
4890 // Scalar Floating-point Multiply Extended,
4891 multiclass Neon_Scalar3Same_MULX_SD_size_patterns<SDPatternOperator opnode,
4893 Instruction INSTD> {
4894 def : Pat<(f32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
4895 (INSTS FPR32:$Rn, FPR32:$Rm)>;
4896 def : Pat<(f64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
4897 (INSTD FPR64:$Rn, FPR64:$Rm)>;
4900 defm : Neon_Scalar3Same_MULX_SD_size_patterns<int_aarch64_neon_vmulx,
4903 // Scalar Integer Shift Left (Signed, Unsigned)
4904 def SSHLddd : NeonI_Scalar3Same_D_size<0b0, 0b01000, "sshl">;
4905 def USHLddd : NeonI_Scalar3Same_D_size<0b1, 0b01000, "ushl">;
4907 // Patterns to match llvm.arm.* intrinsic for
4908 // Scalar Integer Shift Left (Signed, Unsigned)
4909 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshifts, SSHLddd>;
4910 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshiftu, USHLddd>;
4912 // Patterns to match llvm.aarch64.* intrinsic for
4913 // Scalar Integer Shift Left (Signed, Unsigned)
4914 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshlds, SSHLddd>;
4915 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshldu, USHLddd>;
4917 // Scalar Integer Saturating Shift Left (Signed, Unsigned)
4918 defm SQSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01001, "sqshl", 0>;
4919 defm UQSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01001, "uqshl", 0>;
4921 // Patterns to match llvm.aarch64.* intrinsic for
4922 // Scalar Integer Saturating Shift Letf (Signed, Unsigned)
4923 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshls, SQSHLbbb,
4924 SQSHLhhh, SQSHLsss, SQSHLddd>;
4925 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshlu, UQSHLbbb,
4926 UQSHLhhh, UQSHLsss, UQSHLddd>;
4928 // Patterns to match llvm.arm.* intrinsic for
4929 // Scalar Integer Saturating Shift Letf (Signed, Unsigned)
4930 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshifts, SQSHLddd>;
4931 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshiftu, UQSHLddd>;
4933 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4934 def SRSHLddd: NeonI_Scalar3Same_D_size<0b0, 0b01010, "srshl">;
4935 def URSHLddd: NeonI_Scalar3Same_D_size<0b1, 0b01010, "urshl">;
4937 // Patterns to match llvm.aarch64.* intrinsic for
4938 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4939 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshlds, SRSHLddd>;
4940 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshldu, URSHLddd>;
4942 // Patterns to match llvm.arm.* intrinsic for
4943 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4944 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshifts, SRSHLddd>;
4945 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshiftu, URSHLddd>;
4947 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4948 defm SQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01011, "sqrshl", 0>;
4949 defm UQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01011, "uqrshl", 0>;
4951 // Patterns to match llvm.aarch64.* intrinsic for
4952 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4953 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshls, SQRSHLbbb,
4954 SQRSHLhhh, SQRSHLsss, SQRSHLddd>;
4955 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb,
4956 UQRSHLhhh, UQRSHLsss, UQRSHLddd>;
4958 // Patterns to match llvm.arm.* intrinsic for
4959 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4960 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
4961 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
4963 // Signed Saturating Doubling Multiply-Add Long
4964 defm SQDMLAL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1001, "sqdmlal">;
4965 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlal,
4966 SQDMLALshh, SQDMLALdss>;
4968 // Signed Saturating Doubling Multiply-Subtract Long
4969 defm SQDMLSL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1011, "sqdmlsl">;
4970 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlsl,
4971 SQDMLSLshh, SQDMLSLdss>;
4973 // Signed Saturating Doubling Multiply Long
4974 defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">;
4975 defm : Neon_Scalar3Diff_HS_size_patterns<int_arm_neon_vqdmull,
4976 SQDMULLshh, SQDMULLdss>;
4978 // Scalar Signed Integer Convert To Floating-point
4979 defm SCVTF : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">;
4980 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtint2fps,
4983 // Scalar Unsigned Integer Convert To Floating-point
4984 defm UCVTF : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11101, "ucvtf">;
4985 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtint2fpu,
4988 // Scalar Floating-point Converts
4989 def FCVTXN : NeonI_Scalar2SameMisc_fcvtxn_D_size<0b1, 0b10110, "fcvtxn">;
4990 def : Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<int_aarch64_neon_fcvtxn,
4993 defm FCVTNS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11010, "fcvtns">;
4994 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtns,
4995 FCVTNSss, FCVTNSdd>;
4996 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtns, FCVTNSdd>;
4998 defm FCVTNU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11010, "fcvtnu">;
4999 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtnu,
5000 FCVTNUss, FCVTNUdd>;
5001 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtnu, FCVTNUdd>;
5003 defm FCVTMS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11011, "fcvtms">;
5004 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtms,
5005 FCVTMSss, FCVTMSdd>;
5006 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtms, FCVTMSdd>;
5008 defm FCVTMU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11011, "fcvtmu">;
5009 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtmu,
5010 FCVTMUss, FCVTMUdd>;
5011 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtmu, FCVTMUdd>;
5013 defm FCVTAS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11100, "fcvtas">;
5014 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtas,
5015 FCVTASss, FCVTASdd>;
5016 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtas, FCVTASdd>;
5018 defm FCVTAU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11100, "fcvtau">;
5019 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtau,
5020 FCVTAUss, FCVTAUdd>;
5021 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtau, FCVTAUdd>;
5023 defm FCVTPS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11010, "fcvtps">;
5024 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtps,
5025 FCVTPSss, FCVTPSdd>;
5026 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtps, FCVTPSdd>;
5028 defm FCVTPU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11010, "fcvtpu">;
5029 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtpu,
5030 FCVTPUss, FCVTPUdd>;
5031 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtpu, FCVTPUdd>;
5033 defm FCVTZS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11011, "fcvtzs">;
5034 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzs,
5035 FCVTZSss, FCVTZSdd>;
5036 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_aarch64_neon_vcvtzs,
5039 defm FCVTZU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11011, "fcvtzu">;
5040 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzu,
5041 FCVTZUss, FCVTZUdd>;
5042 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_aarch64_neon_vcvtzu,
5045 // Patterns For Convert Instructions Between v1f64 and v1i64
5046 class Neon_Scalar2SameMisc_cvtf_v1f64_pattern<SDPatternOperator opnode,
5048 : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5050 class Neon_Scalar2SameMisc_fcvt_v1f64_pattern<SDPatternOperator opnode,
5052 : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5054 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<sint_to_fp, SCVTFdd>;
5055 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<uint_to_fp, UCVTFdd>;
5057 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_sint, FCVTZSdd>;
5058 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_uint, FCVTZUdd>;
5060 // Scalar Floating-point Reciprocal Estimate
5061 defm FRECPE : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11101, "frecpe">;
5062 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpe,
5063 FRECPEss, FRECPEdd>;
5064 def : Neon_Scalar2SameMisc_V1_D_size_patterns<int_arm_neon_vrecpe,
5067 // Scalar Floating-point Reciprocal Exponent
5068 defm FRECPX : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11111, "frecpx">;
5069 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpx,
5070 FRECPXss, FRECPXdd>;
5072 // Scalar Floating-point Reciprocal Square Root Estimate
5073 defm FRSQRTE: NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11101, "frsqrte">;
5074 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrsqrte,
5075 FRSQRTEss, FRSQRTEdd>;
5076 def : Neon_Scalar2SameMisc_V1_D_size_patterns<int_arm_neon_vrsqrte,
5079 // Scalar Floating-point Round
5080 class Neon_ScalarFloatRound_pattern<SDPatternOperator opnode, Instruction INST>
5081 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5083 def : Neon_ScalarFloatRound_pattern<fceil, FRINTPdd>;
5084 def : Neon_ScalarFloatRound_pattern<ffloor, FRINTMdd>;
5085 def : Neon_ScalarFloatRound_pattern<ftrunc, FRINTZdd>;
5086 def : Neon_ScalarFloatRound_pattern<frint, FRINTXdd>;
5087 def : Neon_ScalarFloatRound_pattern<fnearbyint, FRINTIdd>;
5088 def : Neon_ScalarFloatRound_pattern<frnd, FRINTAdd>;
5089 def : Neon_ScalarFloatRound_pattern<int_aarch64_neon_frintn, FRINTNdd>;
5091 // Scalar Integer Compare
5093 // Scalar Compare Bitwise Equal
5094 def CMEQddd: NeonI_Scalar3Same_D_size<0b1, 0b10001, "cmeq">;
5095 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vceq, CMEQddd>;
5097 class Neon_Scalar3Same_cmp_D_size_v1_patterns<SDPatternOperator opnode,
5100 : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm), CC)),
5101 (INSTD FPR64:$Rn, FPR64:$Rm)>;
5103 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMEQddd, SETEQ>;
5105 // Scalar Compare Signed Greather Than Or Equal
5106 def CMGEddd: NeonI_Scalar3Same_D_size<0b0, 0b00111, "cmge">;
5107 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcge, CMGEddd>;
5108 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGEddd, SETGE>;
5110 // Scalar Compare Unsigned Higher Or Same
5111 def CMHSddd: NeonI_Scalar3Same_D_size<0b1, 0b00111, "cmhs">;
5112 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchs, CMHSddd>;
5113 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHSddd, SETUGE>;
5115 // Scalar Compare Unsigned Higher
5116 def CMHIddd: NeonI_Scalar3Same_D_size<0b1, 0b00110, "cmhi">;
5117 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchi, CMHIddd>;
5118 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHIddd, SETUGT>;
5120 // Scalar Compare Signed Greater Than
5121 def CMGTddd: NeonI_Scalar3Same_D_size<0b0, 0b00110, "cmgt">;
5122 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcgt, CMGTddd>;
5123 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGTddd, SETGT>;
5125 // Scalar Compare Bitwise Test Bits
5126 def CMTSTddd: NeonI_Scalar3Same_D_size<0b0, 0b10001, "cmtst">;
5127 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vtstd, CMTSTddd>;
5128 def : Neon_Scalar3Same_cmp_D_size_patterns<Neon_tst, CMTSTddd>;
5130 // Scalar Compare Bitwise Equal To Zero
5131 def CMEQddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01001, "cmeq">;
5132 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vceq,
5134 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETEQ, CMEQddi>;
5136 // Scalar Compare Signed Greather Than Or Equal To Zero
5137 def CMGEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01000, "cmge">;
5138 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcge,
5140 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGE, CMGEddi>;
5142 // Scalar Compare Signed Greater Than Zero
5143 def CMGTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01000, "cmgt">;
5144 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcgt,
5146 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGT, CMGTddi>;
5148 // Scalar Compare Signed Less Than Or Equal To Zero
5149 def CMLEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01001, "cmle">;
5150 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vclez,
5152 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLE, CMLEddi>;
5154 // Scalar Compare Less Than Zero
5155 def CMLTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01010, "cmlt">;
5156 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcltz,
5158 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLT, CMLTddi>;
5160 // Scalar Floating-point Compare
5162 // Scalar Floating-point Compare Mask Equal
5163 defm FCMEQ: NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11100, "fcmeq">;
5164 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_fceq,
5165 FCMEQsss, FCMEQddd>;
5166 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETEQ, FCMEQddd>;
5168 // Scalar Floating-point Compare Mask Equal To Zero
5169 defm FCMEQZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01101, "fcmeq">;
5170 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fceq,
5171 FCMEQZssi, FCMEQZddi>;
5172 def : Pat<(v1i64 (Neon_cmpz (v1f64 FPR64:$Rn), (f32 fpz32:$FPImm), SETEQ)),
5173 (FCMEQZddi FPR64:$Rn, fpz32:$FPImm)>;
5175 // Scalar Floating-point Compare Mask Greater Than Or Equal
5176 defm FCMGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11100, "fcmge">;
5177 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_fcge,
5178 FCMGEsss, FCMGEddd>;
5179 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGE, FCMGEddd>;
5181 // Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
5182 defm FCMGEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01100, "fcmge">;
5183 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcge,
5184 FCMGEZssi, FCMGEZddi>;
5186 // Scalar Floating-point Compare Mask Greather Than
5187 defm FCMGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11100, "fcmgt">;
5188 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_fcgt,
5189 FCMGTsss, FCMGTddd>;
5190 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGT, FCMGTddd>;
5192 // Scalar Floating-point Compare Mask Greather Than Zero
5193 defm FCMGTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01100, "fcmgt">;
5194 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcgt,
5195 FCMGTZssi, FCMGTZddi>;
5197 // Scalar Floating-point Compare Mask Less Than Or Equal To Zero
5198 defm FCMLEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01101, "fcmle">;
5199 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fclez,
5200 FCMLEZssi, FCMLEZddi>;
5202 // Scalar Floating-point Compare Mask Less Than Zero
5203 defm FCMLTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01110, "fcmlt">;
5204 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcltz,
5205 FCMLTZssi, FCMLTZddi>;
5207 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
5208 defm FACGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11101, "facge">;
5209 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_fcage,
5210 FACGEsss, FACGEddd>;
5211 def : Pat<(v1i64 (int_aarch64_neon_vcage (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5212 (FACGEddd FPR64:$Rn, FPR64:$Rm)>;
5214 // Scalar Floating-point Absolute Compare Mask Greater Than
5215 defm FACGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11101, "facgt">;
5216 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_fcagt,
5217 FACGTsss, FACGTddd>;
5218 def : Pat<(v1i64 (int_aarch64_neon_vcagt (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5219 (FACGTddd FPR64:$Rn, FPR64:$Rm)>;
5221 // Scakar Floating-point Absolute Difference
5222 defm FABD: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11010, "fabd">;
5223 defm : Neon_Scalar3Same_fabd_SD_size_patterns<int_aarch64_neon_vabd,
5226 // Scalar Absolute Value
5227 defm ABS : NeonI_Scalar2SameMisc_D_size<0b0, 0b01011, "abs">;
5228 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vabs, ABSdd>;
5230 // Scalar Signed Saturating Absolute Value
5231 defm SQABS : NeonI_Scalar2SameMisc_BHSD_size<0b0, 0b00111, "sqabs">;
5232 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqabs,
5233 SQABSbb, SQABShh, SQABSss, SQABSdd>;
5236 defm NEG : NeonI_Scalar2SameMisc_D_size<0b1, 0b01011, "neg">;
5237 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vneg, NEGdd>;
5239 // Scalar Signed Saturating Negate
5240 defm SQNEG : NeonI_Scalar2SameMisc_BHSD_size<0b1, 0b00111, "sqneg">;
5241 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqneg,
5242 SQNEGbb, SQNEGhh, SQNEGss, SQNEGdd>;
5244 // Scalar Signed Saturating Accumulated of Unsigned Value
5245 defm SUQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b0, 0b00011, "suqadd">;
5246 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vuqadd,
5248 SUQADDss, SUQADDdd>;
5250 // Scalar Unsigned Saturating Accumulated of Signed Value
5251 defm USQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b1, 0b00011, "usqadd">;
5252 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vsqadd,
5254 USQADDss, USQADDdd>;
5256 def : Pat<(v1i64 (int_aarch64_neon_suqadd (v1i64 FPR64:$Src),
5257 (v1i64 FPR64:$Rn))),
5258 (SUQADDdd FPR64:$Src, FPR64:$Rn)>;
5260 def : Pat<(v1i64 (int_aarch64_neon_usqadd (v1i64 FPR64:$Src),
5261 (v1i64 FPR64:$Rn))),
5262 (USQADDdd FPR64:$Src, FPR64:$Rn)>;
5264 def : Pat<(v1i64 (int_arm_neon_vabs (v1i64 FPR64:$Rn))),
5267 def : Pat<(v1i64 (int_arm_neon_vqabs (v1i64 FPR64:$Rn))),
5268 (SQABSdd FPR64:$Rn)>;
5270 def : Pat<(v1i64 (int_arm_neon_vqneg (v1i64 FPR64:$Rn))),
5271 (SQNEGdd FPR64:$Rn)>;
5273 def : Pat<(v1i64 (sub (v1i64 (bitconvert (v8i8 Neon_AllZero))),
5274 (v1i64 FPR64:$Rn))),
5277 // Scalar Signed Saturating Extract Unsigned Narrow
5278 defm SQXTUN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10010, "sqxtun">;
5279 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnsu,
5283 // Scalar Signed Saturating Extract Narrow
5284 defm SQXTN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b0, 0b10100, "sqxtn">;
5285 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovns,
5289 // Scalar Unsigned Saturating Extract Narrow
5290 defm UQXTN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10100, "uqxtn">;
5291 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnu,
5295 // Scalar Reduce Pairwise
5297 multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode,
5298 string asmop, bit Commutable = 0> {
5299 let isCommutable = Commutable in {
5300 def _D_2D : NeonI_ScalarPair<u, {size, 0b1}, opcode,
5301 (outs FPR64:$Rd), (ins VPR128:$Rn),
5302 !strconcat(asmop, "\t$Rd, $Rn.2d"),
5308 multiclass NeonI_ScalarPair_SD_sizes<bit u, bit size, bits<5> opcode,
5309 string asmop, bit Commutable = 0>
5310 : NeonI_ScalarPair_D_sizes<u, size, opcode, asmop, Commutable> {
5311 let isCommutable = Commutable in {
5312 def _S_2S : NeonI_ScalarPair<u, {size, 0b0}, opcode,
5313 (outs FPR32:$Rd), (ins VPR64:$Rn),
5314 !strconcat(asmop, "\t$Rd, $Rn.2s"),
5320 // Scalar Reduce Addition Pairwise (Integer) with
5321 // Pattern to match llvm.arm.* intrinsic
5322 defm ADDPvv : NeonI_ScalarPair_D_sizes<0b0, 0b1, 0b11011, "addp", 0>;
5324 // Pattern to match llvm.aarch64.* intrinsic for
5325 // Scalar Reduce Addition Pairwise (Integer)
5326 def : Pat<(v1i64 (int_aarch64_neon_vpadd (v2i64 VPR128:$Rn))),
5327 (ADDPvv_D_2D VPR128:$Rn)>;
5328 def : Pat<(v1i64 (int_aarch64_neon_vaddv (v2i64 VPR128:$Rn))),
5329 (ADDPvv_D_2D VPR128:$Rn)>;
5331 // Scalar Reduce Addition Pairwise (Floating Point)
5332 defm FADDPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01101, "faddp", 0>;
5334 // Scalar Reduce Maximum Pairwise (Floating Point)
5335 defm FMAXPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01111, "fmaxp", 0>;
5337 // Scalar Reduce Minimum Pairwise (Floating Point)
5338 defm FMINPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01111, "fminp", 0>;
5340 // Scalar Reduce maxNum Pairwise (Floating Point)
5341 defm FMAXNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01100, "fmaxnmp", 0>;
5343 // Scalar Reduce minNum Pairwise (Floating Point)
5344 defm FMINNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01100, "fminnmp", 0>;
5346 multiclass Neon_ScalarPair_SD_size_patterns<SDPatternOperator opnode,
5348 Instruction INSTD> {
5349 def : Pat<(f32 (opnode (v2f32 VPR64:$Rn))),
5351 def : Pat<(f64 (opnode (v2f64 VPR128:$Rn))),
5352 (INSTD VPR128:$Rn)>;
5355 // Patterns to match llvm.aarch64.* intrinsic for
5356 // Scalar Reduce Add, Max, Min, MaxiNum, MinNum Pairwise (Floating Point)
5357 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfadd,
5358 FADDPvv_S_2S, FADDPvv_D_2D>;
5360 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmax,
5361 FMAXPvv_S_2S, FMAXPvv_D_2D>;
5363 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmin,
5364 FMINPvv_S_2S, FMINPvv_D_2D>;
5366 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfmaxnm,
5367 FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
5369 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfminnm,
5370 FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
5372 def : Pat<(f32 (int_aarch64_neon_vpfadd (v4f32 VPR128:$Rn))),
5373 (FADDPvv_S_2S (v2f32
5375 (v4f32 (FADDP_4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rn))),
5378 // Scalar by element Arithmetic
5380 class NeonI_ScalarXIndexedElemArith<string asmop, bits<4> opcode,
5381 string rmlane, bit u, bit szhi, bit szlo,
5382 RegisterClass ResFPR, RegisterClass OpFPR,
5383 RegisterOperand OpVPR, Operand OpImm>
5384 : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5386 (ins OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5387 asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5394 class NeonI_ScalarXIndexedElemArith_Constraint_Impl<string asmop, bits<4> opcode,
5396 bit u, bit szhi, bit szlo,
5397 RegisterClass ResFPR,
5398 RegisterClass OpFPR,
5399 RegisterOperand OpVPR,
5401 : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5403 (ins ResFPR:$src, OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5404 asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5407 let Constraints = "$src = $Rd";
5412 // Scalar Floating Point multiply (scalar, by element)
5413 def FMULssv_4S : NeonI_ScalarXIndexedElemArith<"fmul",
5414 0b1001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5415 let Inst{11} = Imm{1}; // h
5416 let Inst{21} = Imm{0}; // l
5417 let Inst{20-16} = MRm;
5419 def FMULddv_2D : NeonI_ScalarXIndexedElemArith<"fmul",
5420 0b1001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5421 let Inst{11} = Imm{0}; // h
5422 let Inst{21} = 0b0; // l
5423 let Inst{20-16} = MRm;
5426 // Scalar Floating Point multiply extended (scalar, by element)
5427 def FMULXssv_4S : NeonI_ScalarXIndexedElemArith<"fmulx",
5428 0b1001, ".s", 0b1, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5429 let Inst{11} = Imm{1}; // h
5430 let Inst{21} = Imm{0}; // l
5431 let Inst{20-16} = MRm;
5433 def FMULXddv_2D : NeonI_ScalarXIndexedElemArith<"fmulx",
5434 0b1001, ".d", 0b1, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5435 let Inst{11} = Imm{0}; // h
5436 let Inst{21} = 0b0; // l
5437 let Inst{20-16} = MRm;
5440 multiclass Neon_ScalarXIndexedElem_MUL_MULX_Patterns<
5441 SDPatternOperator opnode,
5443 ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5444 ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5446 def : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5447 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)))),
5448 (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5450 def : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5451 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)))),
5452 (ResTy (INST (ResTy FPRC:$Rn),
5453 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5457 def : Pat<(ResTy (opnode
5458 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5460 (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5462 def : Pat<(ResTy (opnode
5463 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5465 (ResTy (INST (ResTy FPRC:$Rn),
5466 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5470 // Patterns for Scalar Floating Point multiply (scalar, by element)
5471 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULssv_4S,
5472 f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5473 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULddv_2D,
5474 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5476 // Patterns for Scalar Floating Point multiply extended (scalar, by element)
5477 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5478 FMULXssv_4S, f32, FPR32, v4f32, neon_uimm2_bare,
5479 v2f32, v4f32, neon_uimm1_bare>;
5480 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5481 FMULXddv_2D, f64, FPR64, v2f64, neon_uimm1_bare,
5482 v1f64, v2f64, neon_uimm0_bare>;
5485 // Scalar Floating Point fused multiply-add (scalar, by element)
5486 def FMLAssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5487 0b0001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5488 let Inst{11} = Imm{1}; // h
5489 let Inst{21} = Imm{0}; // l
5490 let Inst{20-16} = MRm;
5492 def FMLAddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5493 0b0001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5494 let Inst{11} = Imm{0}; // h
5495 let Inst{21} = 0b0; // l
5496 let Inst{20-16} = MRm;
5499 // Scalar Floating Point fused multiply-subtract (scalar, by element)
5500 def FMLSssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5501 0b0101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5502 let Inst{11} = Imm{1}; // h
5503 let Inst{21} = Imm{0}; // l
5504 let Inst{20-16} = MRm;
5506 def FMLSddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5507 0b0101, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5508 let Inst{11} = Imm{0}; // h
5509 let Inst{21} = 0b0; // l
5510 let Inst{20-16} = MRm;
5512 // We are allowed to match the fma instruction regardless of compile options.
5513 multiclass Neon_ScalarXIndexedElem_FMA_Patterns<
5514 Instruction FMLAI, Instruction FMLSI,
5515 ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5516 ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5518 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5519 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5521 (ResTy (FMLAI (ResTy FPRC:$Ra),
5522 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5524 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5525 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5527 (ResTy (FMLAI (ResTy FPRC:$Ra),
5529 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5532 // swapped fmla operands
5533 def : Pat<(ResTy (fma
5534 (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5537 (ResTy (FMLAI (ResTy FPRC:$Ra),
5538 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5540 def : Pat<(ResTy (fma
5541 (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5544 (ResTy (FMLAI (ResTy FPRC:$Ra),
5546 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5550 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5551 (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5553 (ResTy (FMLSI (ResTy FPRC:$Ra),
5554 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5556 def : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5557 (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5559 (ResTy (FMLSI (ResTy FPRC:$Ra),
5561 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5564 // swapped fmls operands
5565 def : Pat<(ResTy (fma
5566 (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5569 (ResTy (FMLSI (ResTy FPRC:$Ra),
5570 (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5572 def : Pat<(ResTy (fma
5573 (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5576 (ResTy (FMLSI (ResTy FPRC:$Ra),
5578 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5582 // Scalar Floating Point fused multiply-add and
5583 // multiply-subtract (scalar, by element)
5584 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAssv_4S, FMLSssv_4S,
5585 f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5586 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5587 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5588 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5589 f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5591 // Scalar Signed saturating doubling multiply long (scalar, by element)
5592 def SQDMULLshv_4H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5593 0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5594 let Inst{11} = 0b0; // h
5595 let Inst{21} = Imm{1}; // l
5596 let Inst{20} = Imm{0}; // m
5597 let Inst{19-16} = MRm{3-0};
5599 def SQDMULLshv_8H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5600 0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5601 let Inst{11} = Imm{2}; // h
5602 let Inst{21} = Imm{1}; // l
5603 let Inst{20} = Imm{0}; // m
5604 let Inst{19-16} = MRm{3-0};
5606 def SQDMULLdsv_2S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5607 0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5608 let Inst{11} = 0b0; // h
5609 let Inst{21} = Imm{0}; // l
5610 let Inst{20-16} = MRm;
5612 def SQDMULLdsv_4S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5613 0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5614 let Inst{11} = Imm{1}; // h
5615 let Inst{21} = Imm{0}; // l
5616 let Inst{20-16} = MRm;
5619 multiclass Neon_ScalarXIndexedElem_MUL_Patterns<
5620 SDPatternOperator opnode,
5622 ValueType ResTy, RegisterClass FPRC,
5623 ValueType OpVTy, ValueType OpTy,
5624 ValueType VecOpTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5626 def : Pat<(ResTy (opnode (OpVTy FPRC:$Rn),
5627 (OpVTy (scalar_to_vector
5628 (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))))),
5629 (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5632 def : Pat<(ResTy (opnode
5633 (OpVTy (scalar_to_vector
5634 (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))),
5636 (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5640 // Patterns for Scalar Signed saturating doubling
5641 // multiply long (scalar, by element)
5642 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5643 SQDMULLshv_4H, v1i32, FPR16, v1i16, i16, v4i16,
5644 i32, VPR64Lo, neon_uimm2_bare>;
5645 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5646 SQDMULLshv_8H, v1i32, FPR16, v1i16, i16, v8i16,
5647 i32, VPR128Lo, neon_uimm3_bare>;
5648 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5649 SQDMULLdsv_2S, v1i64, FPR32, v1i32, i32, v2i32,
5650 i32, VPR64Lo, neon_uimm1_bare>;
5651 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5652 SQDMULLdsv_4S, v1i64, FPR32, v1i32, i32, v4i32,
5653 i32, VPR128Lo, neon_uimm2_bare>;
5655 // Scalar Signed saturating doubling multiply-add long (scalar, by element)
5656 def SQDMLALshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5657 0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5658 let Inst{11} = 0b0; // h
5659 let Inst{21} = Imm{1}; // l
5660 let Inst{20} = Imm{0}; // m
5661 let Inst{19-16} = MRm{3-0};
5663 def SQDMLALshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5664 0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5665 let Inst{11} = Imm{2}; // h
5666 let Inst{21} = Imm{1}; // l
5667 let Inst{20} = Imm{0}; // m
5668 let Inst{19-16} = MRm{3-0};
5670 def SQDMLALdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5671 0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5672 let Inst{11} = 0b0; // h
5673 let Inst{21} = Imm{0}; // l
5674 let Inst{20-16} = MRm;
5676 def SQDMLALdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5677 0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5678 let Inst{11} = Imm{1}; // h
5679 let Inst{21} = Imm{0}; // l
5680 let Inst{20-16} = MRm;
5683 // Scalar Signed saturating doubling
5684 // multiply-subtract long (scalar, by element)
5685 def SQDMLSLshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5686 0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5687 let Inst{11} = 0b0; // h
5688 let Inst{21} = Imm{1}; // l
5689 let Inst{20} = Imm{0}; // m
5690 let Inst{19-16} = MRm{3-0};
5692 def SQDMLSLshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5693 0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5694 let Inst{11} = Imm{2}; // h
5695 let Inst{21} = Imm{1}; // l
5696 let Inst{20} = Imm{0}; // m
5697 let Inst{19-16} = MRm{3-0};
5699 def SQDMLSLdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5700 0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5701 let Inst{11} = 0b0; // h
5702 let Inst{21} = Imm{0}; // l
5703 let Inst{20-16} = MRm;
5705 def SQDMLSLdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5706 0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5707 let Inst{11} = Imm{1}; // h
5708 let Inst{21} = Imm{0}; // l
5709 let Inst{20-16} = MRm;
5712 multiclass Neon_ScalarXIndexedElem_MLAL_Patterns<
5713 SDPatternOperator opnode,
5714 SDPatternOperator coreopnode,
5716 ValueType ResTy, RegisterClass ResFPRC, RegisterClass FPRC,
5718 ValueType OpVTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5720 def : Pat<(ResTy (opnode
5721 (ResTy ResFPRC:$Ra),
5722 (ResTy (coreopnode (OpTy FPRC:$Rn),
5723 (OpTy (scalar_to_vector
5724 (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))))))),
5725 (ResTy (INST (ResTy ResFPRC:$Ra),
5726 (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5729 def : Pat<(ResTy (opnode
5730 (ResTy ResFPRC:$Ra),
5732 (OpTy (scalar_to_vector
5733 (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))),
5734 (OpTy FPRC:$Rn))))),
5735 (ResTy (INST (ResTy ResFPRC:$Ra),
5736 (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5739 // Patterns for Scalar Signed saturating
5740 // doubling multiply-add long (scalar, by element)
5741 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5742 int_arm_neon_vqdmull, SQDMLALshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5743 i32, VPR64Lo, neon_uimm2_bare>;
5744 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5745 int_arm_neon_vqdmull, SQDMLALshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5746 i32, VPR128Lo, neon_uimm3_bare>;
5747 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5748 int_arm_neon_vqdmull, SQDMLALdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5749 i32, VPR64Lo, neon_uimm1_bare>;
5750 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5751 int_arm_neon_vqdmull, SQDMLALdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5752 i32, VPR128Lo, neon_uimm2_bare>;
5754 // Patterns for Scalar Signed saturating
5755 // doubling multiply-sub long (scalar, by element)
5756 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5757 int_arm_neon_vqdmull, SQDMLSLshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5758 i32, VPR64Lo, neon_uimm2_bare>;
5759 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5760 int_arm_neon_vqdmull, SQDMLSLshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5761 i32, VPR128Lo, neon_uimm3_bare>;
5762 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5763 int_arm_neon_vqdmull, SQDMLSLdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5764 i32, VPR64Lo, neon_uimm1_bare>;
5765 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5766 int_arm_neon_vqdmull, SQDMLSLdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5767 i32, VPR128Lo, neon_uimm2_bare>;
5769 // Scalar general arithmetic operation
5770 class Neon_Scalar_GeneralMath2D_pattern<SDPatternOperator opnode,
5772 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5774 class Neon_Scalar_GeneralMath3D_pattern<SDPatternOperator opnode,
5776 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5777 (INST FPR64:$Rn, FPR64:$Rm)>;
5779 class Neon_Scalar_GeneralMath4D_pattern<SDPatternOperator opnode,
5781 : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm),
5782 (v1f64 FPR64:$Ra))),
5783 (INST FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
5785 def : Neon_Scalar_GeneralMath3D_pattern<fadd, FADDddd>;
5786 def : Neon_Scalar_GeneralMath3D_pattern<fmul, FMULddd>;
5787 def : Neon_Scalar_GeneralMath3D_pattern<fsub, FSUBddd>;
5788 def : Neon_Scalar_GeneralMath3D_pattern<fdiv, FDIVddd>;
5789 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vabds, FABDddd>;
5790 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmaxs, FMAXddd>;
5791 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmins, FMINddd>;
5792 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vmaxnm, FMAXNMddd>;
5793 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vminnm, FMINNMddd>;
5795 def : Neon_Scalar_GeneralMath2D_pattern<fabs, FABSdd>;
5796 def : Neon_Scalar_GeneralMath2D_pattern<fneg, FNEGdd>;
5798 def : Neon_Scalar_GeneralMath4D_pattern<fma, FMADDdddd>;
5799 def : Neon_Scalar_GeneralMath4D_pattern<fmsub, FMSUBdddd>;
5801 // Scalar Signed saturating doubling multiply returning
5802 // high half (scalar, by element)
5803 def SQDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5804 0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5805 let Inst{11} = 0b0; // h
5806 let Inst{21} = Imm{1}; // l
5807 let Inst{20} = Imm{0}; // m
5808 let Inst{19-16} = MRm{3-0};
5810 def SQDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5811 0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5812 let Inst{11} = Imm{2}; // h
5813 let Inst{21} = Imm{1}; // l
5814 let Inst{20} = Imm{0}; // m
5815 let Inst{19-16} = MRm{3-0};
5817 def SQDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5818 0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5819 let Inst{11} = 0b0; // h
5820 let Inst{21} = Imm{0}; // l
5821 let Inst{20-16} = MRm;
5823 def SQDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5824 0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5825 let Inst{11} = Imm{1}; // h
5826 let Inst{21} = Imm{0}; // l
5827 let Inst{20-16} = MRm;
5830 // Patterns for Scalar Signed saturating doubling multiply returning
5831 // high half (scalar, by element)
5832 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5833 SQDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16,
5834 i32, VPR64Lo, neon_uimm2_bare>;
5835 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5836 SQDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16,
5837 i32, VPR128Lo, neon_uimm3_bare>;
5838 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5839 SQDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32,
5840 i32, VPR64Lo, neon_uimm1_bare>;
5841 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5842 SQDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32,
5843 i32, VPR128Lo, neon_uimm2_bare>;
5845 // Scalar Signed saturating rounding doubling multiply
5846 // returning high half (scalar, by element)
5847 def SQRDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5848 0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5849 let Inst{11} = 0b0; // h
5850 let Inst{21} = Imm{1}; // l
5851 let Inst{20} = Imm{0}; // m
5852 let Inst{19-16} = MRm{3-0};
5854 def SQRDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5855 0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5856 let Inst{11} = Imm{2}; // h
5857 let Inst{21} = Imm{1}; // l
5858 let Inst{20} = Imm{0}; // m
5859 let Inst{19-16} = MRm{3-0};
5861 def SQRDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5862 0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5863 let Inst{11} = 0b0; // h
5864 let Inst{21} = Imm{0}; // l
5865 let Inst{20-16} = MRm;
5867 def SQRDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5868 0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5869 let Inst{11} = Imm{1}; // h
5870 let Inst{21} = Imm{0}; // l
5871 let Inst{20-16} = MRm;
5874 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5875 SQRDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16, i32,
5876 VPR64Lo, neon_uimm2_bare>;
5877 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5878 SQRDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16, i32,
5879 VPR128Lo, neon_uimm3_bare>;
5880 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5881 SQRDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32, i32,
5882 VPR64Lo, neon_uimm1_bare>;
5883 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5884 SQRDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32, i32,
5885 VPR128Lo, neon_uimm2_bare>;
5887 // Scalar Copy - DUP element to scalar
5888 class NeonI_Scalar_DUP<string asmop, string asmlane,
5889 RegisterClass ResRC, RegisterOperand VPRC,
5891 : NeonI_ScalarCopy<(outs ResRC:$Rd), (ins VPRC:$Rn, OpImm:$Imm),
5892 asmop # "\t$Rd, $Rn." # asmlane # "[$Imm]",
5898 def DUPbv_B : NeonI_Scalar_DUP<"dup", "b", FPR8, VPR128, neon_uimm4_bare> {
5899 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
5901 def DUPhv_H : NeonI_Scalar_DUP<"dup", "h", FPR16, VPR128, neon_uimm3_bare> {
5902 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
5904 def DUPsv_S : NeonI_Scalar_DUP<"dup", "s", FPR32, VPR128, neon_uimm2_bare> {
5905 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
5907 def DUPdv_D : NeonI_Scalar_DUP<"dup", "d", FPR64, VPR128, neon_uimm1_bare> {
5908 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
5911 multiclass NeonI_Scalar_DUP_Elt_pattern<Instruction DUPI, ValueType ResTy,
5912 ValueType OpTy, Operand OpImm,
5913 ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5914 def : Pat<(ResTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
5915 (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5917 def : Pat<(ResTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
5919 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5923 // Patterns for vector extract of FP data using scalar DUP instructions
5924 defm : NeonI_Scalar_DUP_Elt_pattern<DUPsv_S, f32,
5925 v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5926 defm : NeonI_Scalar_DUP_Elt_pattern<DUPdv_D, f64,
5927 v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5929 multiclass NeonI_Scalar_DUP_Ext_Vec_pattern<Instruction DUPI,
5930 ValueType ResTy, ValueType OpTy,Operand OpLImm,
5931 ValueType NOpTy, ValueType ExTy, Operand OpNImm> {
5933 def : Pat<(ResTy (extract_subvector (OpTy VPR128:$Rn), OpLImm:$Imm)),
5934 (ResTy (DUPI VPR128:$Rn, OpLImm:$Imm))>;
5936 def : Pat<(ResTy (extract_subvector (NOpTy VPR64:$Rn), OpNImm:$Imm)),
5938 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5942 // Patterns for extract subvectors of v1ix data using scalar DUP instructions.
5943 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPbv_B, v1i8, v16i8, neon_uimm4_bare,
5944 v8i8, v16i8, neon_uimm3_bare>;
5945 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPhv_H, v1i16, v8i16, neon_uimm3_bare,
5946 v4i16, v8i16, neon_uimm2_bare>;
5947 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPsv_S, v1i32, v4i32, neon_uimm2_bare,
5948 v2i32, v4i32, neon_uimm1_bare>;
5950 multiclass NeonI_Scalar_DUP_Copy_pattern1<Instruction DUPI, ValueType ResTy,
5951 ValueType OpTy, ValueType ElemTy,
5952 Operand OpImm, ValueType OpNTy,
5953 ValueType ExTy, Operand OpNImm> {
5955 def : Pat<(ResTy (vector_insert (ResTy undef),
5956 (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
5957 (neon_uimm0_bare:$Imm))),
5958 (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5960 def : Pat<(ResTy (vector_insert (ResTy undef),
5961 (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
5964 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5968 multiclass NeonI_Scalar_DUP_Copy_pattern2<Instruction DUPI, ValueType ResTy,
5969 ValueType OpTy, ValueType ElemTy,
5970 Operand OpImm, ValueType OpNTy,
5971 ValueType ExTy, Operand OpNImm> {
5973 def : Pat<(ResTy (scalar_to_vector
5974 (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)))),
5975 (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5977 def : Pat<(ResTy (scalar_to_vector
5978 (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)))),
5980 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5984 // Patterns for vector copy to v1ix and v1fx vectors using scalar DUP
5986 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPdv_D,
5987 v1i64, v2i64, i64, neon_uimm1_bare,
5988 v1i64, v2i64, neon_uimm0_bare>;
5989 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPsv_S,
5990 v1i32, v4i32, i32, neon_uimm2_bare,
5991 v2i32, v4i32, neon_uimm1_bare>;
5992 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPhv_H,
5993 v1i16, v8i16, i32, neon_uimm3_bare,
5994 v4i16, v8i16, neon_uimm2_bare>;
5995 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPbv_B,
5996 v1i8, v16i8, i32, neon_uimm4_bare,
5997 v8i8, v16i8, neon_uimm3_bare>;
5998 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPdv_D,
5999 v1f64, v2f64, f64, neon_uimm1_bare,
6000 v1f64, v2f64, neon_uimm0_bare>;
6001 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPsv_S,
6002 v1f32, v4f32, f32, neon_uimm2_bare,
6003 v2f32, v4f32, neon_uimm1_bare>;
6004 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPdv_D,
6005 v1i64, v2i64, i64, neon_uimm1_bare,
6006 v1i64, v2i64, neon_uimm0_bare>;
6007 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPsv_S,
6008 v1i32, v4i32, i32, neon_uimm2_bare,
6009 v2i32, v4i32, neon_uimm1_bare>;
6010 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPhv_H,
6011 v1i16, v8i16, i32, neon_uimm3_bare,
6012 v4i16, v8i16, neon_uimm2_bare>;
6013 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPbv_B,
6014 v1i8, v16i8, i32, neon_uimm4_bare,
6015 v8i8, v16i8, neon_uimm3_bare>;
6016 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPdv_D,
6017 v1f64, v2f64, f64, neon_uimm1_bare,
6018 v1f64, v2f64, neon_uimm0_bare>;
6019 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPsv_S,
6020 v1f32, v4f32, f32, neon_uimm2_bare,
6021 v2f32, v4f32, neon_uimm1_bare>;
6023 multiclass NeonI_Scalar_DUP_alias<string asmop, string asmlane,
6024 Instruction DUPI, Operand OpImm,
6025 RegisterClass ResRC> {
6026 def : NeonInstAlias<!strconcat(asmop, "$Rd, $Rn" # asmlane # "[$Imm]"),
6027 (DUPI ResRC:$Rd, VPR128:$Rn, OpImm:$Imm), 0b0>;
6030 // Aliases for Scalar copy - DUP element (scalar)
6031 // FIXME: This is actually the preferred syntax but TableGen can't deal with
6032 // custom printing of aliases.
6033 defm : NeonI_Scalar_DUP_alias<"mov", ".b", DUPbv_B, neon_uimm4_bare, FPR8>;
6034 defm : NeonI_Scalar_DUP_alias<"mov", ".h", DUPhv_H, neon_uimm3_bare, FPR16>;
6035 defm : NeonI_Scalar_DUP_alias<"mov", ".s", DUPsv_S, neon_uimm2_bare, FPR32>;
6036 defm : NeonI_Scalar_DUP_alias<"mov", ".d", DUPdv_D, neon_uimm1_bare, FPR64>;
6038 multiclass NeonI_SDUP<PatFrag GetLow, PatFrag GetHigh, ValueType ResTy,
6040 def : Pat<(ResTy (GetLow VPR128:$Rn)),
6041 (ResTy (EXTRACT_SUBREG (OpTy VPR128:$Rn), sub_64))>;
6042 def : Pat<(ResTy (GetHigh VPR128:$Rn)),
6043 (ResTy (DUPdv_D (OpTy VPR128:$Rn), 1))>;
6046 defm : NeonI_SDUP<Neon_Low16B, Neon_High16B, v8i8, v16i8>;
6047 defm : NeonI_SDUP<Neon_Low8H, Neon_High8H, v4i16, v8i16>;
6048 defm : NeonI_SDUP<Neon_Low4S, Neon_High4S, v2i32, v4i32>;
6049 defm : NeonI_SDUP<Neon_Low2D, Neon_High2D, v1i64, v2i64>;
6050 defm : NeonI_SDUP<Neon_Low4float, Neon_High4float, v2f32, v4f32>;
6051 defm : NeonI_SDUP<Neon_Low2double, Neon_High2double, v1f64, v2f64>;
6053 //===----------------------------------------------------------------------===//
6054 // Non-Instruction Patterns
6055 //===----------------------------------------------------------------------===//
6057 // 64-bit vector bitcasts...
6059 def : Pat<(v1i64 (bitconvert (v8i8 VPR64:$src))), (v1i64 VPR64:$src)>;
6060 def : Pat<(v2f32 (bitconvert (v8i8 VPR64:$src))), (v2f32 VPR64:$src)>;
6061 def : Pat<(v2i32 (bitconvert (v8i8 VPR64:$src))), (v2i32 VPR64:$src)>;
6062 def : Pat<(v4i16 (bitconvert (v8i8 VPR64:$src))), (v4i16 VPR64:$src)>;
6064 def : Pat<(v1i64 (bitconvert (v4i16 VPR64:$src))), (v1i64 VPR64:$src)>;
6065 def : Pat<(v2i32 (bitconvert (v4i16 VPR64:$src))), (v2i32 VPR64:$src)>;
6066 def : Pat<(v2f32 (bitconvert (v4i16 VPR64:$src))), (v2f32 VPR64:$src)>;
6067 def : Pat<(v8i8 (bitconvert (v4i16 VPR64:$src))), (v8i8 VPR64:$src)>;
6069 def : Pat<(v1i64 (bitconvert (v2i32 VPR64:$src))), (v1i64 VPR64:$src)>;
6070 def : Pat<(v2f32 (bitconvert (v2i32 VPR64:$src))), (v2f32 VPR64:$src)>;
6071 def : Pat<(v4i16 (bitconvert (v2i32 VPR64:$src))), (v4i16 VPR64:$src)>;
6072 def : Pat<(v8i8 (bitconvert (v2i32 VPR64:$src))), (v8i8 VPR64:$src)>;
6074 def : Pat<(v1i64 (bitconvert (v2f32 VPR64:$src))), (v1i64 VPR64:$src)>;
6075 def : Pat<(v2i32 (bitconvert (v2f32 VPR64:$src))), (v2i32 VPR64:$src)>;
6076 def : Pat<(v4i16 (bitconvert (v2f32 VPR64:$src))), (v4i16 VPR64:$src)>;
6077 def : Pat<(v8i8 (bitconvert (v2f32 VPR64:$src))), (v8i8 VPR64:$src)>;
6079 def : Pat<(v2f32 (bitconvert (v1i64 VPR64:$src))), (v2f32 VPR64:$src)>;
6080 def : Pat<(v2i32 (bitconvert (v1i64 VPR64:$src))), (v2i32 VPR64:$src)>;
6081 def : Pat<(v4i16 (bitconvert (v1i64 VPR64:$src))), (v4i16 VPR64:$src)>;
6082 def : Pat<(v8i8 (bitconvert (v1i64 VPR64:$src))), (v8i8 VPR64:$src)>;
6084 // ..and 128-bit vector bitcasts...
6086 def : Pat<(v2f64 (bitconvert (v16i8 VPR128:$src))), (v2f64 VPR128:$src)>;
6087 def : Pat<(v2i64 (bitconvert (v16i8 VPR128:$src))), (v2i64 VPR128:$src)>;
6088 def : Pat<(v4f32 (bitconvert (v16i8 VPR128:$src))), (v4f32 VPR128:$src)>;
6089 def : Pat<(v4i32 (bitconvert (v16i8 VPR128:$src))), (v4i32 VPR128:$src)>;
6090 def : Pat<(v8i16 (bitconvert (v16i8 VPR128:$src))), (v8i16 VPR128:$src)>;
6092 def : Pat<(v2f64 (bitconvert (v8i16 VPR128:$src))), (v2f64 VPR128:$src)>;
6093 def : Pat<(v2i64 (bitconvert (v8i16 VPR128:$src))), (v2i64 VPR128:$src)>;
6094 def : Pat<(v4i32 (bitconvert (v8i16 VPR128:$src))), (v4i32 VPR128:$src)>;
6095 def : Pat<(v4f32 (bitconvert (v8i16 VPR128:$src))), (v4f32 VPR128:$src)>;
6096 def : Pat<(v16i8 (bitconvert (v8i16 VPR128:$src))), (v16i8 VPR128:$src)>;
6098 def : Pat<(v2f64 (bitconvert (v4i32 VPR128:$src))), (v2f64 VPR128:$src)>;
6099 def : Pat<(v2i64 (bitconvert (v4i32 VPR128:$src))), (v2i64 VPR128:$src)>;
6100 def : Pat<(v4f32 (bitconvert (v4i32 VPR128:$src))), (v4f32 VPR128:$src)>;
6101 def : Pat<(v8i16 (bitconvert (v4i32 VPR128:$src))), (v8i16 VPR128:$src)>;
6102 def : Pat<(v16i8 (bitconvert (v4i32 VPR128:$src))), (v16i8 VPR128:$src)>;
6104 def : Pat<(v2f64 (bitconvert (v4f32 VPR128:$src))), (v2f64 VPR128:$src)>;
6105 def : Pat<(v2i64 (bitconvert (v4f32 VPR128:$src))), (v2i64 VPR128:$src)>;
6106 def : Pat<(v4i32 (bitconvert (v4f32 VPR128:$src))), (v4i32 VPR128:$src)>;
6107 def : Pat<(v8i16 (bitconvert (v4f32 VPR128:$src))), (v8i16 VPR128:$src)>;
6108 def : Pat<(v16i8 (bitconvert (v4f32 VPR128:$src))), (v16i8 VPR128:$src)>;
6110 def : Pat<(v2f64 (bitconvert (v2i64 VPR128:$src))), (v2f64 VPR128:$src)>;
6111 def : Pat<(v4f32 (bitconvert (v2i64 VPR128:$src))), (v4f32 VPR128:$src)>;
6112 def : Pat<(v4i32 (bitconvert (v2i64 VPR128:$src))), (v4i32 VPR128:$src)>;
6113 def : Pat<(v8i16 (bitconvert (v2i64 VPR128:$src))), (v8i16 VPR128:$src)>;
6114 def : Pat<(v16i8 (bitconvert (v2i64 VPR128:$src))), (v16i8 VPR128:$src)>;
6116 def : Pat<(v2i64 (bitconvert (v2f64 VPR128:$src))), (v2i64 VPR128:$src)>;
6117 def : Pat<(v4f32 (bitconvert (v2f64 VPR128:$src))), (v4f32 VPR128:$src)>;
6118 def : Pat<(v4i32 (bitconvert (v2f64 VPR128:$src))), (v4i32 VPR128:$src)>;
6119 def : Pat<(v8i16 (bitconvert (v2f64 VPR128:$src))), (v8i16 VPR128:$src)>;
6120 def : Pat<(v16i8 (bitconvert (v2f64 VPR128:$src))), (v16i8 VPR128:$src)>;
6122 // ...and scalar bitcasts...
6123 def : Pat<(f16 (bitconvert (v1i16 FPR16:$src))), (f16 FPR16:$src)>;
6124 def : Pat<(f32 (bitconvert (v1i32 FPR32:$src))), (f32 FPR32:$src)>;
6125 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
6126 def : Pat<(f32 (bitconvert (v1f32 FPR32:$src))), (f32 FPR32:$src)>;
6127 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
6129 def : Pat<(i64 (bitconvert (v1i64 FPR64:$src))), (FMOVxd $src)>;
6130 def : Pat<(i64 (bitconvert (v1f64 FPR64:$src))), (FMOVxd $src)>;
6131 def : Pat<(i64 (bitconvert (v2i32 FPR64:$src))), (FMOVxd $src)>;
6132 def : Pat<(i64 (bitconvert (v2f32 FPR64:$src))), (FMOVxd $src)>;
6133 def : Pat<(i64 (bitconvert (v4i16 FPR64:$src))), (FMOVxd $src)>;
6134 def : Pat<(i64 (bitconvert (v8i8 FPR64:$src))), (FMOVxd $src)>;
6136 def : Pat<(i32 (bitconvert (v1i32 FPR32:$src))), (FMOVws $src)>;
6138 def : Pat<(v8i8 (bitconvert (v1i64 VPR64:$src))), (v8i8 VPR64:$src)>;
6139 def : Pat<(v4i16 (bitconvert (v1i64 VPR64:$src))), (v4i16 VPR64:$src)>;
6140 def : Pat<(v2i32 (bitconvert (v1i64 VPR64:$src))), (v2i32 VPR64:$src)>;
6142 def : Pat<(f64 (bitconvert (v8i8 VPR64:$src))), (f64 VPR64:$src)>;
6143 def : Pat<(f64 (bitconvert (v4i16 VPR64:$src))), (f64 VPR64:$src)>;
6144 def : Pat<(f64 (bitconvert (v2i32 VPR64:$src))), (f64 VPR64:$src)>;
6145 def : Pat<(f64 (bitconvert (v2f32 VPR64:$src))), (f64 VPR64:$src)>;
6146 def : Pat<(f64 (bitconvert (v1i64 VPR64:$src))), (f64 VPR64:$src)>;
6148 def : Pat<(f128 (bitconvert (v16i8 VPR128:$src))), (f128 VPR128:$src)>;
6149 def : Pat<(f128 (bitconvert (v8i16 VPR128:$src))), (f128 VPR128:$src)>;
6150 def : Pat<(f128 (bitconvert (v4i32 VPR128:$src))), (f128 VPR128:$src)>;
6151 def : Pat<(f128 (bitconvert (v2i64 VPR128:$src))), (f128 VPR128:$src)>;
6152 def : Pat<(f128 (bitconvert (v4f32 VPR128:$src))), (f128 VPR128:$src)>;
6153 def : Pat<(f128 (bitconvert (v2f64 VPR128:$src))), (f128 VPR128:$src)>;
6155 def : Pat<(v1i16 (bitconvert (f16 FPR16:$src))), (v1i16 FPR16:$src)>;
6156 def : Pat<(v1i32 (bitconvert (f32 FPR32:$src))), (v1i32 FPR32:$src)>;
6157 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
6158 def : Pat<(v1f32 (bitconvert (f32 FPR32:$src))), (v1f32 FPR32:$src)>;
6159 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
6161 def : Pat<(v1i64 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6162 def : Pat<(v1f64 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6163 def : Pat<(v2i32 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6164 def : Pat<(v2f32 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6165 def : Pat<(v4i16 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6166 def : Pat<(v8i8 (bitconvert (i64 GPR64:$src))), (FMOVdx $src)>;
6168 def : Pat<(v1i32 (bitconvert (i32 GPR32:$src))), (FMOVsw $src)>;
6170 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
6171 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
6172 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
6173 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
6174 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
6176 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
6177 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
6178 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
6179 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
6180 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
6181 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
6183 // Scalar Three Same
6185 def neon_uimm3 : Operand<i64>,
6186 ImmLeaf<i64, [{return Imm < 8;}]> {
6187 let ParserMatchClass = uimm3_asmoperand;
6188 let PrintMethod = "printUImmHexOperand";
6191 def neon_uimm4 : Operand<i64>,
6192 ImmLeaf<i64, [{return Imm < 16;}]> {
6193 let ParserMatchClass = uimm4_asmoperand;
6194 let PrintMethod = "printUImmHexOperand";
6198 class NeonI_Extract<bit q, bits<2> op2, string asmop,
6199 string OpS, RegisterOperand OpVPR, Operand OpImm>
6200 : NeonI_BitExtract<q, op2, (outs OpVPR:$Rd),
6201 (ins OpVPR:$Rn, OpVPR:$Rm, OpImm:$Index),
6202 asmop # "\t$Rd." # OpS # ", $Rn." # OpS #
6203 ", $Rm." # OpS # ", $Index",
6209 def EXTvvvi_8b : NeonI_Extract<0b0, 0b00, "ext", "8b",
6210 VPR64, neon_uimm3> {
6211 let Inst{14-11} = {0b0, Index{2}, Index{1}, Index{0}};
6214 def EXTvvvi_16b: NeonI_Extract<0b1, 0b00, "ext", "16b",
6215 VPR128, neon_uimm4> {
6216 let Inst{14-11} = Index;
6219 class NI_Extract<ValueType OpTy, RegisterOperand OpVPR, Instruction INST,
6221 : Pat<(OpTy (Neon_vextract (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm),
6223 (INST OpVPR:$Rn, OpVPR:$Rm, OpImm:$Imm)>;
6225 def : NI_Extract<v8i8, VPR64, EXTvvvi_8b, neon_uimm3>;
6226 def : NI_Extract<v4i16, VPR64, EXTvvvi_8b, neon_uimm3>;
6227 def : NI_Extract<v2i32, VPR64, EXTvvvi_8b, neon_uimm3>;
6228 def : NI_Extract<v1i64, VPR64, EXTvvvi_8b, neon_uimm3>;
6229 def : NI_Extract<v2f32, VPR64, EXTvvvi_8b, neon_uimm3>;
6230 def : NI_Extract<v1f64, VPR64, EXTvvvi_8b, neon_uimm3>;
6231 def : NI_Extract<v16i8, VPR128, EXTvvvi_16b, neon_uimm4>;
6232 def : NI_Extract<v8i16, VPR128, EXTvvvi_16b, neon_uimm4>;
6233 def : NI_Extract<v4i32, VPR128, EXTvvvi_16b, neon_uimm4>;
6234 def : NI_Extract<v2i64, VPR128, EXTvvvi_16b, neon_uimm4>;
6235 def : NI_Extract<v4f32, VPR128, EXTvvvi_16b, neon_uimm4>;
6236 def : NI_Extract<v2f64, VPR128, EXTvvvi_16b, neon_uimm4>;
6239 class NI_TBL<bit q, bits<2> op2, bits<2> len, bit op,
6240 string asmop, string OpS, RegisterOperand OpVPR,
6241 RegisterOperand VecList>
6242 : NeonI_TBL<q, op2, len, op,
6243 (outs OpVPR:$Rd), (ins VecList:$Rn, OpVPR:$Rm),
6244 asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6248 // The vectors in look up table are always 16b
6249 multiclass NI_TBL_pat<bits<2> len, bit op, string asmop, string List> {
6250 def _8b : NI_TBL<0, 0b00, len, op, asmop, "8b", VPR64,
6251 !cast<RegisterOperand>(List # "16B_operand")>;
6253 def _16b : NI_TBL<1, 0b00, len, op, asmop, "16b", VPR128,
6254 !cast<RegisterOperand>(List # "16B_operand")>;
6257 defm TBL1 : NI_TBL_pat<0b00, 0b0, "tbl", "VOne">;
6258 defm TBL2 : NI_TBL_pat<0b01, 0b0, "tbl", "VPair">;
6259 defm TBL3 : NI_TBL_pat<0b10, 0b0, "tbl", "VTriple">;
6260 defm TBL4 : NI_TBL_pat<0b11, 0b0, "tbl", "VQuad">;
6262 // Table lookup extention
6263 class NI_TBX<bit q, bits<2> op2, bits<2> len, bit op,
6264 string asmop, string OpS, RegisterOperand OpVPR,
6265 RegisterOperand VecList>
6266 : NeonI_TBL<q, op2, len, op,
6267 (outs OpVPR:$Rd), (ins OpVPR:$src, VecList:$Rn, OpVPR:$Rm),
6268 asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6271 let Constraints = "$src = $Rd";
6274 // The vectors in look up table are always 16b
6275 multiclass NI_TBX_pat<bits<2> len, bit op, string asmop, string List> {
6276 def _8b : NI_TBX<0, 0b00, len, op, asmop, "8b", VPR64,
6277 !cast<RegisterOperand>(List # "16B_operand")>;
6279 def _16b : NI_TBX<1, 0b00, len, op, asmop, "16b", VPR128,
6280 !cast<RegisterOperand>(List # "16B_operand")>;
6283 defm TBX1 : NI_TBX_pat<0b00, 0b1, "tbx", "VOne">;
6284 defm TBX2 : NI_TBX_pat<0b01, 0b1, "tbx", "VPair">;
6285 defm TBX3 : NI_TBX_pat<0b10, 0b1, "tbx", "VTriple">;
6286 defm TBX4 : NI_TBX_pat<0b11, 0b1, "tbx", "VQuad">;
6288 class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
6289 RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
6290 : NeonI_copy<0b1, 0b0, 0b0011,
6291 (outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
6292 asmop # "\t$Rd." # Res # "[$Imm], $Rn",
6293 [(set (ResTy VPR128:$Rd),
6294 (ResTy (vector_insert
6295 (ResTy VPR128:$src),
6300 let Constraints = "$src = $Rd";
6303 //Insert element (vector, from main)
6304 def INSbw : NeonI_INS_main<"ins", "b", v16i8, GPR32, i32,
6306 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6308 def INShw : NeonI_INS_main<"ins", "h", v8i16, GPR32, i32,
6310 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6312 def INSsw : NeonI_INS_main<"ins", "s", v4i32, GPR32, i32,
6314 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6316 def INSdx : NeonI_INS_main<"ins", "d", v2i64, GPR64, i64,
6318 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6321 def : NeonInstAlias<"mov $Rd.b[$Imm], $Rn",
6322 (INSbw VPR128:$Rd, GPR32:$Rn, neon_uimm4_bare:$Imm), 0>;
6323 def : NeonInstAlias<"mov $Rd.h[$Imm], $Rn",
6324 (INShw VPR128:$Rd, GPR32:$Rn, neon_uimm3_bare:$Imm), 0>;
6325 def : NeonInstAlias<"mov $Rd.s[$Imm], $Rn",
6326 (INSsw VPR128:$Rd, GPR32:$Rn, neon_uimm2_bare:$Imm), 0>;
6327 def : NeonInstAlias<"mov $Rd.d[$Imm], $Rn",
6328 (INSdx VPR128:$Rd, GPR64:$Rn, neon_uimm1_bare:$Imm), 0>;
6330 class Neon_INS_main_pattern <ValueType ResTy,ValueType ExtResTy,
6331 RegisterClass OpGPR, ValueType OpTy,
6332 Operand OpImm, Instruction INS>
6333 : Pat<(ResTy (vector_insert
6337 (ResTy (EXTRACT_SUBREG
6338 (ExtResTy (INS (ExtResTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
6339 OpGPR:$Rn, OpImm:$Imm)), sub_64))>;
6341 def INSbw_pattern : Neon_INS_main_pattern<v8i8, v16i8, GPR32, i32,
6342 neon_uimm3_bare, INSbw>;
6343 def INShw_pattern : Neon_INS_main_pattern<v4i16, v8i16, GPR32, i32,
6344 neon_uimm2_bare, INShw>;
6345 def INSsw_pattern : Neon_INS_main_pattern<v2i32, v4i32, GPR32, i32,
6346 neon_uimm1_bare, INSsw>;
6347 def INSdx_pattern : Neon_INS_main_pattern<v1i64, v2i64, GPR64, i64,
6348 neon_uimm0_bare, INSdx>;
6350 class NeonI_INS_element<string asmop, string Res, Operand ResImm>
6351 : NeonI_insert<0b1, 0b1,
6352 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn,
6353 ResImm:$Immd, ResImm:$Immn),
6354 asmop # "\t$Rd." # Res # "[$Immd], $Rn." # Res # "[$Immn]",
6357 let Constraints = "$src = $Rd";
6362 //Insert element (vector, from element)
6363 def INSELb : NeonI_INS_element<"ins", "b", neon_uimm4_bare> {
6364 let Inst{20-16} = {Immd{3}, Immd{2}, Immd{1}, Immd{0}, 0b1};
6365 let Inst{14-11} = {Immn{3}, Immn{2}, Immn{1}, Immn{0}};
6367 def INSELh : NeonI_INS_element<"ins", "h", neon_uimm3_bare> {
6368 let Inst{20-16} = {Immd{2}, Immd{1}, Immd{0}, 0b1, 0b0};
6369 let Inst{14-11} = {Immn{2}, Immn{1}, Immn{0}, 0b0};
6370 // bit 11 is unspecified, but should be set to zero.
6372 def INSELs : NeonI_INS_element<"ins", "s", neon_uimm2_bare> {
6373 let Inst{20-16} = {Immd{1}, Immd{0}, 0b1, 0b0, 0b0};
6374 let Inst{14-11} = {Immn{1}, Immn{0}, 0b0, 0b0};
6375 // bits 11-12 are unspecified, but should be set to zero.
6377 def INSELd : NeonI_INS_element<"ins", "d", neon_uimm1_bare> {
6378 let Inst{20-16} = {Immd, 0b1, 0b0, 0b0, 0b0};
6379 let Inst{14-11} = {Immn{0}, 0b0, 0b0, 0b0};
6380 // bits 11-13 are unspecified, but should be set to zero.
6383 def : NeonInstAlias<"mov $Rd.b[$Immd], $Rn.b[$Immn]",
6384 (INSELb VPR128:$Rd, VPR128:$Rn,
6385 neon_uimm4_bare:$Immd, neon_uimm4_bare:$Immn), 0>;
6386 def : NeonInstAlias<"mov $Rd.h[$Immd], $Rn.h[$Immn]",
6387 (INSELh VPR128:$Rd, VPR128:$Rn,
6388 neon_uimm3_bare:$Immd, neon_uimm3_bare:$Immn), 0>;
6389 def : NeonInstAlias<"mov $Rd.s[$Immd], $Rn.s[$Immn]",
6390 (INSELs VPR128:$Rd, VPR128:$Rn,
6391 neon_uimm2_bare:$Immd, neon_uimm2_bare:$Immn), 0>;
6392 def : NeonInstAlias<"mov $Rd.d[$Immd], $Rn.d[$Immn]",
6393 (INSELd VPR128:$Rd, VPR128:$Rn,
6394 neon_uimm1_bare:$Immd, neon_uimm1_bare:$Immn), 0>;
6396 multiclass Neon_INS_elt_pattern<ValueType ResTy, ValueType NaTy,
6397 ValueType MidTy, Operand StImm, Operand NaImm,
6399 def : Pat<(ResTy (vector_insert
6400 (ResTy VPR128:$src),
6401 (MidTy (vector_extract
6405 (INS (ResTy VPR128:$src), (ResTy VPR128:$Rn),
6406 StImm:$Immd, StImm:$Immn)>;
6408 def : Pat <(ResTy (vector_insert
6409 (ResTy VPR128:$src),
6410 (MidTy (vector_extract
6414 (INS (ResTy VPR128:$src),
6415 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6416 StImm:$Immd, NaImm:$Immn)>;
6418 def : Pat <(NaTy (vector_insert
6420 (MidTy (vector_extract
6424 (NaTy (EXTRACT_SUBREG
6426 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6428 NaImm:$Immd, StImm:$Immn)),
6431 def : Pat <(NaTy (vector_insert
6433 (MidTy (vector_extract
6437 (NaTy (EXTRACT_SUBREG
6439 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6440 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6441 NaImm:$Immd, NaImm:$Immn)),
6445 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, neon_uimm2_bare,
6446 neon_uimm1_bare, INSELs>;
6447 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, neon_uimm1_bare,
6448 neon_uimm0_bare, INSELd>;
6449 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6450 neon_uimm3_bare, INSELb>;
6451 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6452 neon_uimm2_bare, INSELh>;
6453 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6454 neon_uimm1_bare, INSELs>;
6455 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, neon_uimm1_bare,
6456 neon_uimm0_bare, INSELd>;
6458 multiclass Neon_INS_elt_float_pattern<ValueType ResTy, ValueType NaTy,
6460 RegisterClass OpFPR, Operand ResImm,
6461 SubRegIndex SubIndex, Instruction INS> {
6462 def : Pat <(ResTy (vector_insert
6463 (ResTy VPR128:$src),
6466 (INS (ResTy VPR128:$src),
6467 (ResTy (SUBREG_TO_REG (i64 0), OpFPR:$Rn, SubIndex)),
6471 def : Pat <(NaTy (vector_insert
6475 (NaTy (EXTRACT_SUBREG
6477 (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6478 (ResTy (SUBREG_TO_REG (i64 0), (MidTy OpFPR:$Rn), SubIndex)),
6484 defm : Neon_INS_elt_float_pattern<v4f32, v2f32, f32, FPR32, neon_uimm2_bare,
6486 defm : Neon_INS_elt_float_pattern<v2f64, v1f64, f64, FPR64, neon_uimm1_bare,
6489 class NeonI_SMOV<string asmop, string Res, bit Q,
6490 ValueType OpTy, ValueType eleTy,
6491 Operand OpImm, RegisterClass ResGPR, ValueType ResTy>
6492 : NeonI_copy<Q, 0b0, 0b0101,
6493 (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6494 asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6495 [(set (ResTy ResGPR:$Rd),
6497 (ResTy (vector_extract
6498 (OpTy VPR128:$Rn), (OpImm:$Imm))),
6504 //Signed integer move (main, from element)
6505 def SMOVwb : NeonI_SMOV<"smov", "b", 0b0, v16i8, i8, neon_uimm4_bare,
6507 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6509 def SMOVwh : NeonI_SMOV<"smov", "h", 0b0, v8i16, i16, neon_uimm3_bare,
6511 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6513 def SMOVxb : NeonI_SMOV<"smov", "b", 0b1, v16i8, i8, neon_uimm4_bare,
6515 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6517 def SMOVxh : NeonI_SMOV<"smov", "h", 0b1, v8i16, i16, neon_uimm3_bare,
6519 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6521 def SMOVxs : NeonI_SMOV<"smov", "s", 0b1, v4i32, i32, neon_uimm2_bare,
6523 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6526 multiclass Neon_SMOVx_pattern <ValueType StTy, ValueType NaTy,
6527 ValueType eleTy, Operand StImm, Operand NaImm,
6528 Instruction SMOVI> {
6529 def : Pat<(i64 (sext_inreg
6531 (i32 (vector_extract
6532 (StTy VPR128:$Rn), (StImm:$Imm))))),
6534 (SMOVI VPR128:$Rn, StImm:$Imm)>;
6536 def : Pat<(i64 (sext
6537 (i32 (vector_extract
6538 (StTy VPR128:$Rn), (StImm:$Imm))))),
6539 (SMOVI VPR128:$Rn, StImm:$Imm)>;
6541 def : Pat<(i64 (sext_inreg
6542 (i64 (vector_extract
6543 (NaTy VPR64:$Rn), (NaImm:$Imm))),
6545 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6548 def : Pat<(i64 (sext_inreg
6550 (i32 (vector_extract
6551 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6553 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6556 def : Pat<(i64 (sext
6557 (i32 (vector_extract
6558 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6559 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6563 defm : Neon_SMOVx_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6564 neon_uimm3_bare, SMOVxb>;
6565 defm : Neon_SMOVx_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6566 neon_uimm2_bare, SMOVxh>;
6567 defm : Neon_SMOVx_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6568 neon_uimm1_bare, SMOVxs>;
6570 class Neon_SMOVw_pattern <ValueType StTy, ValueType NaTy,
6571 ValueType eleTy, Operand StImm, Operand NaImm,
6573 : Pat<(i32 (sext_inreg
6574 (i32 (vector_extract
6575 (NaTy VPR64:$Rn), (NaImm:$Imm))),
6577 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6580 def : Neon_SMOVw_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6581 neon_uimm3_bare, SMOVwb>;
6582 def : Neon_SMOVw_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6583 neon_uimm2_bare, SMOVwh>;
6585 class NeonI_UMOV<string asmop, string Res, bit Q,
6586 ValueType OpTy, Operand OpImm,
6587 RegisterClass ResGPR, ValueType ResTy>
6588 : NeonI_copy<Q, 0b0, 0b0111,
6589 (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6590 asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6591 [(set (ResTy ResGPR:$Rd),
6592 (ResTy (vector_extract
6593 (OpTy VPR128:$Rn), (OpImm:$Imm))))],
6598 //Unsigned integer move (main, from element)
6599 def UMOVwb : NeonI_UMOV<"umov", "b", 0b0, v16i8, neon_uimm4_bare,
6601 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6603 def UMOVwh : NeonI_UMOV<"umov", "h", 0b0, v8i16, neon_uimm3_bare,
6605 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6607 def UMOVws : NeonI_UMOV<"umov", "s", 0b0, v4i32, neon_uimm2_bare,
6609 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6611 def UMOVxd : NeonI_UMOV<"umov", "d", 0b1, v2i64, neon_uimm1_bare,
6613 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6616 def : NeonInstAlias<"mov $Rd, $Rn.s[$Imm]",
6617 (UMOVws GPR32:$Rd, VPR128:$Rn, neon_uimm2_bare:$Imm), 0>;
6618 def : NeonInstAlias<"mov $Rd, $Rn.d[$Imm]",
6619 (UMOVxd GPR64:$Rd, VPR128:$Rn, neon_uimm1_bare:$Imm), 0>;
6621 class Neon_UMOV_pattern <ValueType StTy, ValueType NaTy, ValueType ResTy,
6622 Operand StImm, Operand NaImm,
6624 : Pat<(ResTy (vector_extract
6625 (NaTy VPR64:$Rn), NaImm:$Imm)),
6626 (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6629 def : Neon_UMOV_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6630 neon_uimm3_bare, UMOVwb>;
6631 def : Neon_UMOV_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6632 neon_uimm2_bare, UMOVwh>;
6633 def : Neon_UMOV_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6634 neon_uimm1_bare, UMOVws>;
6637 (i32 (vector_extract
6638 (v16i8 VPR128:$Rn), (neon_uimm4_bare:$Imm))),
6640 (UMOVwb VPR128:$Rn, neon_uimm4_bare:$Imm)>;
6643 (i32 (vector_extract
6644 (v8i16 VPR128:$Rn), (neon_uimm3_bare:$Imm))),
6646 (UMOVwh VPR128:$Rn, neon_uimm3_bare:$Imm)>;
6648 def : Pat<(i64 (zext
6649 (i32 (vector_extract
6650 (v2i64 VPR128:$Rn), (neon_uimm1_bare:$Imm))))),
6651 (UMOVxd VPR128:$Rn, neon_uimm1_bare:$Imm)>;
6654 (i32 (vector_extract
6655 (v8i8 VPR64:$Rn), (neon_uimm3_bare:$Imm))),
6657 (UMOVwb (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6658 neon_uimm3_bare:$Imm)>;
6661 (i32 (vector_extract
6662 (v4i16 VPR64:$Rn), (neon_uimm2_bare:$Imm))),
6664 (UMOVwh (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6665 neon_uimm2_bare:$Imm)>;
6667 def : Pat<(i64 (zext
6668 (i32 (vector_extract
6669 (v1i64 VPR64:$Rn), (neon_uimm0_bare:$Imm))))),
6670 (UMOVxd (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6671 neon_uimm0_bare:$Imm)>;
6673 // Additional copy patterns for scalar types
6674 def : Pat<(i32 (vector_extract (v1i8 FPR8:$Rn), (i64 0))),
6676 (SUBREG_TO_REG (i64 0), FPR8:$Rn, sub_8)), (i64 0))>;
6678 def : Pat<(i32 (vector_extract (v1i16 FPR16:$Rn), (i64 0))),
6680 (SUBREG_TO_REG (i64 0), FPR16:$Rn, sub_16)), (i64 0))>;
6682 def : Pat<(i32 (vector_extract (v1i32 FPR32:$Rn), (i64 0))),
6683 (FMOVws FPR32:$Rn)>;
6685 def : Pat<(i64 (vector_extract (v1i64 FPR64:$Rn), (i64 0))),
6686 (FMOVxd FPR64:$Rn)>;
6688 def : Pat<(f64 (vector_extract (v1f64 FPR64:$Rn), (i64 0))),
6691 def : Pat<(f32 (vector_extract (v1f32 FPR32:$Rn), (i64 0))),
6694 def : Pat<(v1i8 (scalar_to_vector GPR32:$Rn)),
6695 (v1i8 (EXTRACT_SUBREG (v16i8
6696 (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
6699 def : Pat<(v1i16 (scalar_to_vector GPR32:$Rn)),
6700 (v1i16 (EXTRACT_SUBREG (v8i16
6701 (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
6704 def : Pat<(v1i32 (scalar_to_vector GPR32:$src)),
6707 def : Pat<(v1i64 (scalar_to_vector GPR64:$src)),
6710 def : Pat<(v1f32 (scalar_to_vector (f32 FPR32:$Rn))),
6712 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
6715 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
6718 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$src))),
6719 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
6720 (f64 FPR64:$src), sub_64)>;
6722 class NeonI_DUP_Elt<bit Q, string asmop, string rdlane, string rnlane,
6723 RegisterOperand ResVPR, Operand OpImm>
6724 : NeonI_copy<Q, 0b0, 0b0000, (outs ResVPR:$Rd),
6725 (ins VPR128:$Rn, OpImm:$Imm),
6726 asmop # "\t$Rd" # rdlane # ", $Rn" # rnlane # "[$Imm]",
6732 def DUPELT16b : NeonI_DUP_Elt<0b1, "dup", ".16b", ".b", VPR128,
6734 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6737 def DUPELT8h : NeonI_DUP_Elt<0b1, "dup", ".8h", ".h", VPR128,
6739 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6742 def DUPELT4s : NeonI_DUP_Elt<0b1, "dup", ".4s", ".s", VPR128,
6744 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6747 def DUPELT2d : NeonI_DUP_Elt<0b1, "dup", ".2d", ".d", VPR128,
6749 let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6752 def DUPELT8b : NeonI_DUP_Elt<0b0, "dup", ".8b", ".b", VPR64,
6754 let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6757 def DUPELT4h : NeonI_DUP_Elt<0b0, "dup", ".4h", ".h", VPR64,
6759 let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6762 def DUPELT2s : NeonI_DUP_Elt<0b0, "dup", ".2s", ".s", VPR64,
6764 let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6767 multiclass NeonI_DUP_Elt_pattern<Instruction DUPELT, ValueType ResTy,
6768 ValueType OpTy,ValueType NaTy,
6769 ValueType ExTy, Operand OpLImm,
6771 def : Pat<(ResTy (Neon_vduplane (OpTy VPR128:$Rn), OpLImm:$Imm)),
6772 (ResTy (DUPELT (OpTy VPR128:$Rn), OpLImm:$Imm))>;
6774 def : Pat<(ResTy (Neon_vduplane
6775 (NaTy VPR64:$Rn), OpNImm:$Imm)),
6777 (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)), OpNImm:$Imm))>;
6779 defm : NeonI_DUP_Elt_pattern<DUPELT16b, v16i8, v16i8, v8i8, v16i8,
6780 neon_uimm4_bare, neon_uimm3_bare>;
6781 defm : NeonI_DUP_Elt_pattern<DUPELT8b, v8i8, v16i8, v8i8, v16i8,
6782 neon_uimm4_bare, neon_uimm3_bare>;
6783 defm : NeonI_DUP_Elt_pattern<DUPELT8h, v8i16, v8i16, v4i16, v8i16,
6784 neon_uimm3_bare, neon_uimm2_bare>;
6785 defm : NeonI_DUP_Elt_pattern<DUPELT4h, v4i16, v8i16, v4i16, v8i16,
6786 neon_uimm3_bare, neon_uimm2_bare>;
6787 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4i32, v4i32, v2i32, v4i32,
6788 neon_uimm2_bare, neon_uimm1_bare>;
6789 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2i32, v4i32, v2i32, v4i32,
6790 neon_uimm2_bare, neon_uimm1_bare>;
6791 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2i64, v2i64, v1i64, v2i64,
6792 neon_uimm1_bare, neon_uimm0_bare>;
6793 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4f32, v4f32, v2f32, v4f32,
6794 neon_uimm2_bare, neon_uimm1_bare>;
6795 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2f32, v4f32, v2f32, v4f32,
6796 neon_uimm2_bare, neon_uimm1_bare>;
6797 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2f64, v2f64, v1f64, v2f64,
6798 neon_uimm1_bare, neon_uimm0_bare>;
6800 def : Pat<(v2f32 (Neon_vdup (f32 FPR32:$Rn))),
6802 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
6804 def : Pat<(v4f32 (Neon_vdup (f32 FPR32:$Rn))),
6806 (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
6808 def : Pat<(v2f64 (Neon_vdup (f64 FPR64:$Rn))),
6810 (SUBREG_TO_REG (i64 0), FPR64:$Rn, sub_64),
6813 class NeonI_DUP<bit Q, string asmop, string rdlane,
6814 RegisterOperand ResVPR, ValueType ResTy,
6815 RegisterClass OpGPR, ValueType OpTy>
6816 : NeonI_copy<Q, 0b0, 0b0001, (outs ResVPR:$Rd), (ins OpGPR:$Rn),
6817 asmop # "\t$Rd" # rdlane # ", $Rn",
6818 [(set (ResTy ResVPR:$Rd),
6819 (ResTy (Neon_vdup (OpTy OpGPR:$Rn))))],
6822 def DUP16b : NeonI_DUP<0b1, "dup", ".16b", VPR128, v16i8, GPR32, i32> {
6823 let Inst{20-16} = 0b00001;
6824 // bits 17-20 are unspecified, but should be set to zero.
6827 def DUP8h : NeonI_DUP<0b1, "dup", ".8h", VPR128, v8i16, GPR32, i32> {
6828 let Inst{20-16} = 0b00010;
6829 // bits 18-20 are unspecified, but should be set to zero.
6832 def DUP4s : NeonI_DUP<0b1, "dup", ".4s", VPR128, v4i32, GPR32, i32> {
6833 let Inst{20-16} = 0b00100;
6834 // bits 19-20 are unspecified, but should be set to zero.
6837 def DUP2d : NeonI_DUP<0b1, "dup", ".2d", VPR128, v2i64, GPR64, i64> {
6838 let Inst{20-16} = 0b01000;
6839 // bit 20 is unspecified, but should be set to zero.
6842 def DUP8b : NeonI_DUP<0b0, "dup", ".8b", VPR64, v8i8, GPR32, i32> {
6843 let Inst{20-16} = 0b00001;
6844 // bits 17-20 are unspecified, but should be set to zero.
6847 def DUP4h : NeonI_DUP<0b0, "dup", ".4h", VPR64, v4i16, GPR32, i32> {
6848 let Inst{20-16} = 0b00010;
6849 // bits 18-20 are unspecified, but should be set to zero.
6852 def DUP2s : NeonI_DUP<0b0, "dup", ".2s", VPR64, v2i32, GPR32, i32> {
6853 let Inst{20-16} = 0b00100;
6854 // bits 19-20 are unspecified, but should be set to zero.
6857 // patterns for CONCAT_VECTORS
6858 multiclass Concat_Vector_Pattern<ValueType ResTy, ValueType OpTy> {
6859 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), undef)),
6860 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)>;
6861 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))),
6863 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6864 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rm, sub_64)),
6867 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rn))),
6869 (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6873 defm : Concat_Vector_Pattern<v16i8, v8i8>;
6874 defm : Concat_Vector_Pattern<v8i16, v4i16>;
6875 defm : Concat_Vector_Pattern<v4i32, v2i32>;
6876 defm : Concat_Vector_Pattern<v2i64, v1i64>;
6877 defm : Concat_Vector_Pattern<v4f32, v2f32>;
6878 defm : Concat_Vector_Pattern<v2f64, v1f64>;
6880 //patterns for EXTRACT_SUBVECTOR
6881 def : Pat<(v8i8 (extract_subvector (v16i8 VPR128:$Rn), (i64 0))),
6882 (v8i8 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6883 def : Pat<(v4i16 (extract_subvector (v8i16 VPR128:$Rn), (i64 0))),
6884 (v4i16 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6885 def : Pat<(v2i32 (extract_subvector (v4i32 VPR128:$Rn), (i64 0))),
6886 (v2i32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6887 def : Pat<(v1i64 (extract_subvector (v2i64 VPR128:$Rn), (i64 0))),
6888 (v1i64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6889 def : Pat<(v2f32 (extract_subvector (v4f32 VPR128:$Rn), (i64 0))),
6890 (v2f32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6891 def : Pat<(v1f64 (extract_subvector (v2f64 VPR128:$Rn), (i64 0))),
6892 (v1f64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6894 // The followings are for instruction class (3V Elem)
6898 class NI_2VE<bit q, bit u, bits<2> size, bits<4> opcode,
6899 string asmop, string ResS, string OpS, string EleOpS,
6900 Operand OpImm, RegisterOperand ResVPR,
6901 RegisterOperand OpVPR, RegisterOperand EleOpVPR>
6902 : NeonI_2VElem<q, u, size, opcode,
6903 (outs ResVPR:$Rd), (ins ResVPR:$src, OpVPR:$Rn,
6904 EleOpVPR:$Re, OpImm:$Index),
6905 asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
6906 ", $Re." # EleOpS # "[$Index]",
6912 let Constraints = "$src = $Rd";
6915 multiclass NI_2VE_v1<bit u, bits<4> opcode, string asmop> {
6916 // vector register class for element is always 128-bit to cover the max index
6917 def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6918 neon_uimm2_bare, VPR64, VPR64, VPR128> {
6919 let Inst{11} = {Index{1}};
6920 let Inst{21} = {Index{0}};
6921 let Inst{20-16} = Re;
6924 def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6925 neon_uimm2_bare, VPR128, VPR128, VPR128> {
6926 let Inst{11} = {Index{1}};
6927 let Inst{21} = {Index{0}};
6928 let Inst{20-16} = Re;
6931 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6932 def _4h8h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
6933 neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
6934 let Inst{11} = {Index{2}};
6935 let Inst{21} = {Index{1}};
6936 let Inst{20} = {Index{0}};
6937 let Inst{19-16} = Re{3-0};
6940 def _8h8h : NI_2VE<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
6941 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
6942 let Inst{11} = {Index{2}};
6943 let Inst{21} = {Index{1}};
6944 let Inst{20} = {Index{0}};
6945 let Inst{19-16} = Re{3-0};
6949 defm MLAvve : NI_2VE_v1<0b1, 0b0000, "mla">;
6950 defm MLSvve : NI_2VE_v1<0b1, 0b0100, "mls">;
6952 // Pattern for lane in 128-bit vector
6953 class NI_2VE_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6954 RegisterOperand ResVPR, RegisterOperand OpVPR,
6955 RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
6957 : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
6958 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6959 (INST ResVPR:$src, OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
6961 // Pattern for lane in 64-bit vector
6962 class NI_2VE_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6963 RegisterOperand ResVPR, RegisterOperand OpVPR,
6964 RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
6966 : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
6967 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6968 (INST ResVPR:$src, OpVPR:$Rn,
6969 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
6971 multiclass NI_2VE_v1_pat<string subop, SDPatternOperator op>
6973 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
6974 op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32>;
6976 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
6977 op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32>;
6979 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
6980 op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
6982 def : NI_2VE_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
6983 op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
6985 // Index can only be half of the max value for lane in 64-bit vector
6987 def : NI_2VE_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
6988 op, VPR64, VPR64, VPR64, v2i32, v2i32, v2i32>;
6990 def : NI_2VE_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
6991 op, VPR64, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
6994 defm MLA_lane_v1 : NI_2VE_v1_pat<"MLAvve", Neon_mla>;
6995 defm MLS_lane_v1 : NI_2VE_v1_pat<"MLSvve", Neon_mls>;
6997 class NI_2VE_2op<bit q, bit u, bits<2> size, bits<4> opcode,
6998 string asmop, string ResS, string OpS, string EleOpS,
6999 Operand OpImm, RegisterOperand ResVPR,
7000 RegisterOperand OpVPR, RegisterOperand EleOpVPR>
7001 : NeonI_2VElem<q, u, size, opcode,
7002 (outs ResVPR:$Rd), (ins OpVPR:$Rn,
7003 EleOpVPR:$Re, OpImm:$Index),
7004 asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
7005 ", $Re." # EleOpS # "[$Index]",
7012 multiclass NI_2VE_v1_2op<bit u, bits<4> opcode, string asmop> {
7013 // vector register class for element is always 128-bit to cover the max index
7014 def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7015 neon_uimm2_bare, VPR64, VPR64, VPR128> {
7016 let Inst{11} = {Index{1}};
7017 let Inst{21} = {Index{0}};
7018 let Inst{20-16} = Re;
7021 def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7022 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7023 let Inst{11} = {Index{1}};
7024 let Inst{21} = {Index{0}};
7025 let Inst{20-16} = Re;
7028 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7029 def _4h8h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
7030 neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
7031 let Inst{11} = {Index{2}};
7032 let Inst{21} = {Index{1}};
7033 let Inst{20} = {Index{0}};
7034 let Inst{19-16} = Re{3-0};
7037 def _8h8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
7038 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7039 let Inst{11} = {Index{2}};
7040 let Inst{21} = {Index{1}};
7041 let Inst{20} = {Index{0}};
7042 let Inst{19-16} = Re{3-0};
7046 defm MULve : NI_2VE_v1_2op<0b0, 0b1000, "mul">;
7047 defm SQDMULHve : NI_2VE_v1_2op<0b0, 0b1100, "sqdmulh">;
7048 defm SQRDMULHve : NI_2VE_v1_2op<0b0, 0b1101, "sqrdmulh">;
7050 // Pattern for lane in 128-bit vector
7051 class NI_2VE_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7052 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7053 ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7054 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7055 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7056 (INST OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7058 // Pattern for lane in 64-bit vector
7059 class NI_2VE_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7060 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7061 ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7062 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7063 (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7065 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7067 multiclass NI_2VE_mul_v1_pat<string subop, SDPatternOperator op> {
7068 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7069 op, VPR64, VPR128, v2i32, v2i32, v4i32>;
7071 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7072 op, VPR128, VPR128, v4i32, v4i32, v4i32>;
7074 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
7075 op, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
7077 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
7078 op, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
7080 // Index can only be half of the max value for lane in 64-bit vector
7082 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7083 op, VPR64, VPR64, v2i32, v2i32, v2i32>;
7085 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
7086 op, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
7089 defm MUL_lane_v1 : NI_2VE_mul_v1_pat<"MULve", mul>;
7090 defm SQDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQDMULHve", int_arm_neon_vqdmulh>;
7091 defm SQRDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQRDMULHve", int_arm_neon_vqrdmulh>;
7095 multiclass NI_2VE_v2_2op<bit u, bits<4> opcode, string asmop> {
7096 // vector register class for element is always 128-bit to cover the max index
7097 def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7098 neon_uimm2_bare, VPR64, VPR64, VPR128> {
7099 let Inst{11} = {Index{1}};
7100 let Inst{21} = {Index{0}};
7101 let Inst{20-16} = Re;
7104 def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7105 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7106 let Inst{11} = {Index{1}};
7107 let Inst{21} = {Index{0}};
7108 let Inst{20-16} = Re;
7111 // _1d2d doesn't exist!
7113 def _2d2d : NI_2VE_2op<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7114 neon_uimm1_bare, VPR128, VPR128, VPR128> {
7115 let Inst{11} = {Index{0}};
7117 let Inst{20-16} = Re;
7121 defm FMULve : NI_2VE_v2_2op<0b0, 0b1001, "fmul">;
7122 defm FMULXve : NI_2VE_v2_2op<0b1, 0b1001, "fmulx">;
7124 class NI_2VE_mul_lane_2d<Instruction INST, Operand OpImm, SDPatternOperator op,
7125 RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7126 ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
7127 SDPatternOperator coreop>
7128 : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7129 (OpTy (coreop (EleOpTy EleOpVPR:$Re), (EleOpTy EleOpVPR:$Re))))),
7131 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), 0)>;
7133 multiclass NI_2VE_mul_v2_pat<string subop, SDPatternOperator op> {
7134 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7135 op, VPR64, VPR128, v2f32, v2f32, v4f32>;
7137 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7138 op, VPR128, VPR128, v4f32, v4f32, v4f32>;
7140 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7141 op, VPR128, VPR128, v2f64, v2f64, v2f64>;
7143 // Index can only be half of the max value for lane in 64-bit vector
7145 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7146 op, VPR64, VPR64, v2f32, v2f32, v2f32>;
7148 def : NI_2VE_mul_lane_2d<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7149 op, VPR128, VPR64, v2f64, v2f64, v1f64,
7150 BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7153 defm FMUL_lane_v2 : NI_2VE_mul_v2_pat<"FMULve", fmul>;
7154 defm FMULX_lane_v2 : NI_2VE_mul_v2_pat<"FMULXve", int_aarch64_neon_vmulx>;
7156 def : Pat<(v2f32 (fmul (v2f32 (Neon_vdup (f32 FPR32:$Re))),
7157 (v2f32 VPR64:$Rn))),
7158 (FMULve_2s4s VPR64:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7160 def : Pat<(v4f32 (fmul (v4f32 (Neon_vdup (f32 FPR32:$Re))),
7161 (v4f32 VPR128:$Rn))),
7162 (FMULve_4s4s VPR128:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7164 def : Pat<(v2f64 (fmul (v2f64 (Neon_vdup (f64 FPR64:$Re))),
7165 (v2f64 VPR128:$Rn))),
7166 (FMULve_2d2d VPR128:$Rn, (SUBREG_TO_REG (i64 0), $Re, sub_64), 0)>;
7168 // The followings are patterns using fma
7169 // -ffp-contract=fast generates fma
7171 multiclass NI_2VE_v2<bit u, bits<4> opcode, string asmop> {
7172 // vector register class for element is always 128-bit to cover the max index
7173 def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7174 neon_uimm2_bare, VPR64, VPR64, VPR128> {
7175 let Inst{11} = {Index{1}};
7176 let Inst{21} = {Index{0}};
7177 let Inst{20-16} = Re;
7180 def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7181 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7182 let Inst{11} = {Index{1}};
7183 let Inst{21} = {Index{0}};
7184 let Inst{20-16} = Re;
7187 // _1d2d doesn't exist!
7189 def _2d2d : NI_2VE<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7190 neon_uimm1_bare, VPR128, VPR128, VPR128> {
7191 let Inst{11} = {Index{0}};
7193 let Inst{20-16} = Re;
7197 defm FMLAvve : NI_2VE_v2<0b0, 0b0001, "fmla">;
7198 defm FMLSvve : NI_2VE_v2<0b0, 0b0101, "fmls">;
7200 // Pattern for lane in 128-bit vector
7201 class NI_2VEswap_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7202 RegisterOperand ResVPR, RegisterOperand OpVPR,
7203 ValueType ResTy, ValueType OpTy,
7204 SDPatternOperator coreop>
7205 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7206 (ResTy ResVPR:$src), (ResTy ResVPR:$Rn))),
7207 (INST ResVPR:$src, ResVPR:$Rn, OpVPR:$Re, OpImm:$Index)>;
7209 // Pattern for lane 0
7210 class NI_2VEfma_lane0<Instruction INST, SDPatternOperator op,
7211 RegisterOperand ResVPR, ValueType ResTy>
7212 : Pat<(ResTy (op (ResTy ResVPR:$Rn),
7213 (ResTy (Neon_vdup (f32 FPR32:$Re))),
7214 (ResTy ResVPR:$src))),
7215 (INST ResVPR:$src, ResVPR:$Rn,
7216 (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7218 // Pattern for lane in 64-bit vector
7219 class NI_2VEswap_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7220 RegisterOperand ResVPR, RegisterOperand OpVPR,
7221 ValueType ResTy, ValueType OpTy,
7222 SDPatternOperator coreop>
7223 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7224 (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7225 (INST ResVPR:$src, ResVPR:$Rn,
7226 (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), OpImm:$Index)>;
7228 // Pattern for lane in 64-bit vector
7229 class NI_2VEswap_lane_2d2d<Instruction INST, Operand OpImm,
7230 SDPatternOperator op,
7231 RegisterOperand ResVPR, RegisterOperand OpVPR,
7232 ValueType ResTy, ValueType OpTy,
7233 SDPatternOperator coreop>
7234 : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (OpTy OpVPR:$Re))),
7235 (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7236 (INST ResVPR:$src, ResVPR:$Rn,
7237 (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), 0)>;
7240 multiclass NI_2VE_fma_v2_pat<string subop, SDPatternOperator op> {
7241 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7242 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7243 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7245 def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_2s4s"),
7248 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7249 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7250 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7252 def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_4s4s"),
7255 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7256 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7257 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7259 // Index can only be half of the max value for lane in 64-bit vector
7261 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7262 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7263 BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7265 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7266 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7267 BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7270 defm FMLA_lane_v2_s : NI_2VE_fma_v2_pat<"FMLAvve", fma>;
7272 // Pattern for lane 0
7273 class NI_2VEfms_lane0<Instruction INST, SDPatternOperator op,
7274 RegisterOperand ResVPR, ValueType ResTy>
7275 : Pat<(ResTy (op (ResTy (fneg ResVPR:$Rn)),
7276 (ResTy (Neon_vdup (f32 FPR32:$Re))),
7277 (ResTy ResVPR:$src))),
7278 (INST ResVPR:$src, ResVPR:$Rn,
7279 (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7281 multiclass NI_2VE_fms_v2_pat<string subop, SDPatternOperator op>
7283 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7284 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7285 BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7287 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7288 neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7289 BinOpFrag<(Neon_vduplane
7290 (fneg node:$LHS), node:$RHS)>>;
7292 def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_2s4s"),
7295 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7296 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7297 BinOpFrag<(fneg (Neon_vduplane
7298 node:$LHS, node:$RHS))>>;
7300 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7301 neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7302 BinOpFrag<(Neon_vduplane
7303 (fneg node:$LHS), node:$RHS)>>;
7305 def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_4s4s"),
7308 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7309 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7310 BinOpFrag<(fneg (Neon_vduplane
7311 node:$LHS, node:$RHS))>>;
7313 def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7314 neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7315 BinOpFrag<(Neon_vduplane
7316 (fneg node:$LHS), node:$RHS)>>;
7318 // Index can only be half of the max value for lane in 64-bit vector
7320 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7321 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7322 BinOpFrag<(fneg (Neon_vduplane
7323 node:$LHS, node:$RHS))>>;
7325 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7326 neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7327 BinOpFrag<(Neon_vduplane
7328 (fneg node:$LHS), node:$RHS)>>;
7330 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7331 neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7332 BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7334 def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7335 neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7336 BinOpFrag<(Neon_vduplane (fneg node:$LHS), node:$RHS)>>;
7338 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7339 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7340 BinOpFrag<(fneg (Neon_combine_2d
7341 node:$LHS, node:$RHS))>>;
7343 def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7344 neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7345 BinOpFrag<(Neon_combine_2d
7346 (fneg node:$LHS), (fneg node:$RHS))>>;
7349 defm FMLS_lane_v2_s : NI_2VE_fms_v2_pat<"FMLSvve", fma>;
7351 // Variant 3: Long type
7352 // E.g. SMLAL : 4S/4H/H (v0-v15), 2D/2S/S
7353 // SMLAL2: 4S/8H/H (v0-v15), 2D/4S/S
7355 multiclass NI_2VE_v3<bit u, bits<4> opcode, string asmop> {
7356 // vector register class for element is always 128-bit to cover the max index
7357 def _2d2s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7358 neon_uimm2_bare, VPR128, VPR64, VPR128> {
7359 let Inst{11} = {Index{1}};
7360 let Inst{21} = {Index{0}};
7361 let Inst{20-16} = Re;
7364 def _2d4s : NI_2VE<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7365 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7366 let Inst{11} = {Index{1}};
7367 let Inst{21} = {Index{0}};
7368 let Inst{20-16} = Re;
7371 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7372 def _4s8h : NI_2VE<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7373 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7374 let Inst{11} = {Index{2}};
7375 let Inst{21} = {Index{1}};
7376 let Inst{20} = {Index{0}};
7377 let Inst{19-16} = Re{3-0};
7380 def _4s4h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7381 neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7382 let Inst{11} = {Index{2}};
7383 let Inst{21} = {Index{1}};
7384 let Inst{20} = {Index{0}};
7385 let Inst{19-16} = Re{3-0};
7389 defm SMLALvve : NI_2VE_v3<0b0, 0b0010, "smlal">;
7390 defm UMLALvve : NI_2VE_v3<0b1, 0b0010, "umlal">;
7391 defm SMLSLvve : NI_2VE_v3<0b0, 0b0110, "smlsl">;
7392 defm UMLSLvve : NI_2VE_v3<0b1, 0b0110, "umlsl">;
7393 defm SQDMLALvve : NI_2VE_v3<0b0, 0b0011, "sqdmlal">;
7394 defm SQDMLSLvve : NI_2VE_v3<0b0, 0b0111, "sqdmlsl">;
7396 multiclass NI_2VE_v3_2op<bit u, bits<4> opcode, string asmop> {
7397 // vector register class for element is always 128-bit to cover the max index
7398 def _2d2s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7399 neon_uimm2_bare, VPR128, VPR64, VPR128> {
7400 let Inst{11} = {Index{1}};
7401 let Inst{21} = {Index{0}};
7402 let Inst{20-16} = Re;
7405 def _2d4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7406 neon_uimm2_bare, VPR128, VPR128, VPR128> {
7407 let Inst{11} = {Index{1}};
7408 let Inst{21} = {Index{0}};
7409 let Inst{20-16} = Re;
7412 // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7413 def _4s8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7414 neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7415 let Inst{11} = {Index{2}};
7416 let Inst{21} = {Index{1}};
7417 let Inst{20} = {Index{0}};
7418 let Inst{19-16} = Re{3-0};
7421 def _4s4h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7422 neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7423 let Inst{11} = {Index{2}};
7424 let Inst{21} = {Index{1}};
7425 let Inst{20} = {Index{0}};
7426 let Inst{19-16} = Re{3-0};
7430 defm SMULLve : NI_2VE_v3_2op<0b0, 0b1010, "smull">;
7431 defm UMULLve : NI_2VE_v3_2op<0b1, 0b1010, "umull">;
7432 defm SQDMULLve : NI_2VE_v3_2op<0b0, 0b1011, "sqdmull">;
7434 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
7436 def : Pat<(v1f32 (scalar_to_vector (f32 FPR32:$src))),
7439 // Pattern for lane in 128-bit vector
7440 class NI_2VEL2_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7441 RegisterOperand EleOpVPR, ValueType ResTy,
7442 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7443 SDPatternOperator hiop>
7444 : Pat<(ResTy (op (ResTy VPR128:$src),
7445 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7446 (HalfOpTy (Neon_vduplane
7447 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7448 (INST VPR128:$src, VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7450 // Pattern for lane in 64-bit vector
7451 class NI_2VEL2_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7452 RegisterOperand EleOpVPR, ValueType ResTy,
7453 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7454 SDPatternOperator hiop>
7455 : Pat<(ResTy (op (ResTy VPR128:$src),
7456 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7457 (HalfOpTy (Neon_vduplane
7458 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7459 (INST VPR128:$src, VPR128:$Rn,
7460 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7462 class NI_2VEL2_lane0<Instruction INST, SDPatternOperator op,
7463 ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7464 SDPatternOperator hiop, Instruction DupInst>
7465 : Pat<(ResTy (op (ResTy VPR128:$src),
7466 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7467 (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7468 (INST VPR128:$src, VPR128:$Rn, (DupInst $Re), 0)>;
7470 multiclass NI_2VEL_v3_pat<string subop, SDPatternOperator op> {
7471 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7472 op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7474 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7475 op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32>;
7477 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7478 op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7480 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7481 op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7483 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7484 op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7486 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7487 op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7489 // Index can only be half of the max value for lane in 64-bit vector
7491 def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7492 op, VPR128, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7494 def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7495 op, VPR128, VPR64, VPR64, v2i64, v2i32, v2i32>;
7497 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7498 op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7500 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7501 op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7504 defm SMLAL_lane_v3 : NI_2VEL_v3_pat<"SMLALvve", Neon_smlal>;
7505 defm UMLAL_lane_v3 : NI_2VEL_v3_pat<"UMLALvve", Neon_umlal>;
7506 defm SMLSL_lane_v3 : NI_2VEL_v3_pat<"SMLSLvve", Neon_smlsl>;
7507 defm UMLSL_lane_v3 : NI_2VEL_v3_pat<"UMLSLvve", Neon_umlsl>;
7509 // Pattern for lane in 128-bit vector
7510 class NI_2VEL2_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7511 RegisterOperand EleOpVPR, ValueType ResTy,
7512 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7513 SDPatternOperator hiop>
7515 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7516 (HalfOpTy (Neon_vduplane
7517 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7518 (INST VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7520 // Pattern for lane in 64-bit vector
7521 class NI_2VEL2_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7522 RegisterOperand EleOpVPR, ValueType ResTy,
7523 ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7524 SDPatternOperator hiop>
7526 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7527 (HalfOpTy (Neon_vduplane
7528 (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7530 (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7532 // Pattern for fixed lane 0
7533 class NI_2VEL2_mul_lane0<Instruction INST, SDPatternOperator op,
7534 ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7535 SDPatternOperator hiop, Instruction DupInst>
7537 (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7538 (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7539 (INST VPR128:$Rn, (DupInst $Re), 0)>;
7541 multiclass NI_2VEL_mul_v3_pat<string subop, SDPatternOperator op> {
7542 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7543 op, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7545 def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7546 op, VPR64, VPR128, v2i64, v2i32, v4i32>;
7548 def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7549 op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7551 def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7552 op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7554 def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_4s8h"),
7555 op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7557 def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_2d4s"),
7558 op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7560 // Index can only be half of the max value for lane in 64-bit vector
7562 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7563 op, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7565 def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7566 op, VPR64, VPR64, v2i64, v2i32, v2i32>;
7568 def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7569 op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7571 def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7572 op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7575 defm SMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SMULLve", int_arm_neon_vmulls>;
7576 defm UMULL_lane_v3 : NI_2VEL_mul_v3_pat<"UMULLve", int_arm_neon_vmullu>;
7577 defm SQDMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SQDMULLve", int_arm_neon_vqdmull>;
7579 multiclass NI_qdma<SDPatternOperator op> {
7580 def _4s : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7582 (v4i32 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7584 def _2d : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7586 (v2i64 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7589 defm Neon_qdmlal : NI_qdma<int_arm_neon_vqadds>;
7590 defm Neon_qdmlsl : NI_qdma<int_arm_neon_vqsubs>;
7592 multiclass NI_2VEL_v3_qdma_pat<string subop, string op> {
7593 def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7594 !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR128Lo,
7595 v4i32, v4i16, v8i16>;
7597 def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7598 !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR128,
7599 v2i64, v2i32, v4i32>;
7601 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7602 !cast<PatFrag>(op # "_4s"), VPR128Lo,
7603 v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7605 def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7606 !cast<PatFrag>(op # "_2d"), VPR128,
7607 v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7609 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7610 !cast<PatFrag>(op # "_4s"),
7611 v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7613 def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7614 !cast<PatFrag>(op # "_2d"),
7615 v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7617 // Index can only be half of the max value for lane in 64-bit vector
7619 def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7620 !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR64Lo,
7621 v4i32, v4i16, v4i16>;
7623 def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7624 !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR64,
7625 v2i64, v2i32, v2i32>;
7627 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7628 !cast<PatFrag>(op # "_4s"), VPR64Lo,
7629 v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7631 def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7632 !cast<PatFrag>(op # "_2d"), VPR64,
7633 v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7636 defm SQDMLAL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLALvve", "Neon_qdmlal">;
7637 defm SQDMLSL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLSLvve", "Neon_qdmlsl">;
7639 // End of implementation for instruction class (3V Elem)
7641 class NeonI_REV<string asmop, string Res, bits<2> size, bit Q, bit U,
7642 bits<5> opcode, RegisterOperand ResVPR, ValueType ResTy,
7643 SDPatternOperator Neon_Rev>
7644 : NeonI_2VMisc<Q, U, size, opcode,
7645 (outs ResVPR:$Rd), (ins ResVPR:$Rn),
7646 asmop # "\t$Rd." # Res # ", $Rn." # Res,
7647 [(set (ResTy ResVPR:$Rd),
7648 (ResTy (Neon_Rev (ResTy ResVPR:$Rn))))],
7651 def REV64_16b : NeonI_REV<"rev64", "16b", 0b00, 0b1, 0b0, 0b00000, VPR128,
7653 def REV64_8h : NeonI_REV<"rev64", "8h", 0b01, 0b1, 0b0, 0b00000, VPR128,
7655 def REV64_4s : NeonI_REV<"rev64", "4s", 0b10, 0b1, 0b0, 0b00000, VPR128,
7657 def REV64_8b : NeonI_REV<"rev64", "8b", 0b00, 0b0, 0b0, 0b00000, VPR64,
7659 def REV64_4h : NeonI_REV<"rev64", "4h", 0b01, 0b0, 0b0, 0b00000, VPR64,
7661 def REV64_2s : NeonI_REV<"rev64", "2s", 0b10, 0b0, 0b0, 0b00000, VPR64,
7664 def : Pat<(v4f32 (Neon_rev64 (v4f32 VPR128:$Rn))), (REV64_4s VPR128:$Rn)>;
7665 def : Pat<(v2f32 (Neon_rev64 (v2f32 VPR64:$Rn))), (REV64_2s VPR64:$Rn)>;
7667 def REV32_16b : NeonI_REV<"rev32", "16b", 0b00, 0b1, 0b1, 0b00000, VPR128,
7669 def REV32_8h : NeonI_REV<"rev32", "8h", 0b01, 0b1, 0b1, 0b00000, VPR128,
7671 def REV32_8b : NeonI_REV<"rev32", "8b", 0b00, 0b0, 0b1, 0b00000, VPR64,
7673 def REV32_4h : NeonI_REV<"rev32", "4h", 0b01, 0b0, 0b1, 0b00000, VPR64,
7676 def REV16_16b : NeonI_REV<"rev16", "16b", 0b00, 0b1, 0b0, 0b00001, VPR128,
7678 def REV16_8b : NeonI_REV<"rev16", "8b", 0b00, 0b0, 0b0, 0b00001, VPR64,
7681 multiclass NeonI_PairwiseAdd<string asmop, bit U, bits<5> opcode,
7682 SDPatternOperator Neon_Padd> {
7683 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7684 (outs VPR128:$Rd), (ins VPR128:$Rn),
7685 asmop # "\t$Rd.8h, $Rn.16b",
7686 [(set (v8i16 VPR128:$Rd),
7687 (v8i16 (Neon_Padd (v16i8 VPR128:$Rn))))],
7690 def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7691 (outs VPR64:$Rd), (ins VPR64:$Rn),
7692 asmop # "\t$Rd.4h, $Rn.8b",
7693 [(set (v4i16 VPR64:$Rd),
7694 (v4i16 (Neon_Padd (v8i8 VPR64:$Rn))))],
7697 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7698 (outs VPR128:$Rd), (ins VPR128:$Rn),
7699 asmop # "\t$Rd.4s, $Rn.8h",
7700 [(set (v4i32 VPR128:$Rd),
7701 (v4i32 (Neon_Padd (v8i16 VPR128:$Rn))))],
7704 def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7705 (outs VPR64:$Rd), (ins VPR64:$Rn),
7706 asmop # "\t$Rd.2s, $Rn.4h",
7707 [(set (v2i32 VPR64:$Rd),
7708 (v2i32 (Neon_Padd (v4i16 VPR64:$Rn))))],
7711 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7712 (outs VPR128:$Rd), (ins VPR128:$Rn),
7713 asmop # "\t$Rd.2d, $Rn.4s",
7714 [(set (v2i64 VPR128:$Rd),
7715 (v2i64 (Neon_Padd (v4i32 VPR128:$Rn))))],
7718 def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7719 (outs VPR64:$Rd), (ins VPR64:$Rn),
7720 asmop # "\t$Rd.1d, $Rn.2s",
7721 [(set (v1i64 VPR64:$Rd),
7722 (v1i64 (Neon_Padd (v2i32 VPR64:$Rn))))],
7726 defm SADDLP : NeonI_PairwiseAdd<"saddlp", 0b0, 0b00010,
7727 int_arm_neon_vpaddls>;
7728 defm UADDLP : NeonI_PairwiseAdd<"uaddlp", 0b1, 0b00010,
7729 int_arm_neon_vpaddlu>;
7731 def : Pat<(v1i64 (int_aarch64_neon_saddlv (v2i32 VPR64:$Rn))),
7733 def : Pat<(v1i64 (int_aarch64_neon_uaddlv (v2i32 VPR64:$Rn))),
7736 multiclass NeonI_PairwiseAddAcc<string asmop, bit U, bits<5> opcode,
7737 SDPatternOperator Neon_Padd> {
7738 let Constraints = "$src = $Rd" in {
7739 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7740 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7741 asmop # "\t$Rd.8h, $Rn.16b",
7742 [(set (v8i16 VPR128:$Rd),
7744 (v8i16 VPR128:$src), (v16i8 VPR128:$Rn))))],
7747 def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7748 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7749 asmop # "\t$Rd.4h, $Rn.8b",
7750 [(set (v4i16 VPR64:$Rd),
7752 (v4i16 VPR64:$src), (v8i8 VPR64:$Rn))))],
7755 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7756 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7757 asmop # "\t$Rd.4s, $Rn.8h",
7758 [(set (v4i32 VPR128:$Rd),
7760 (v4i32 VPR128:$src), (v8i16 VPR128:$Rn))))],
7763 def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7764 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7765 asmop # "\t$Rd.2s, $Rn.4h",
7766 [(set (v2i32 VPR64:$Rd),
7768 (v2i32 VPR64:$src), (v4i16 VPR64:$Rn))))],
7771 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7772 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7773 asmop # "\t$Rd.2d, $Rn.4s",
7774 [(set (v2i64 VPR128:$Rd),
7776 (v2i64 VPR128:$src), (v4i32 VPR128:$Rn))))],
7779 def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7780 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7781 asmop # "\t$Rd.1d, $Rn.2s",
7782 [(set (v1i64 VPR64:$Rd),
7784 (v1i64 VPR64:$src), (v2i32 VPR64:$Rn))))],
7789 defm SADALP : NeonI_PairwiseAddAcc<"sadalp", 0b0, 0b00110,
7790 int_arm_neon_vpadals>;
7791 defm UADALP : NeonI_PairwiseAddAcc<"uadalp", 0b1, 0b00110,
7792 int_arm_neon_vpadalu>;
7794 multiclass NeonI_2VMisc_BHSDsize_1Arg<string asmop, bit U, bits<5> opcode> {
7795 def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7796 (outs VPR128:$Rd), (ins VPR128:$Rn),
7797 asmop # "\t$Rd.16b, $Rn.16b",
7800 def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7801 (outs VPR128:$Rd), (ins VPR128:$Rn),
7802 asmop # "\t$Rd.8h, $Rn.8h",
7805 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7806 (outs VPR128:$Rd), (ins VPR128:$Rn),
7807 asmop # "\t$Rd.4s, $Rn.4s",
7810 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7811 (outs VPR128:$Rd), (ins VPR128:$Rn),
7812 asmop # "\t$Rd.2d, $Rn.2d",
7815 def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7816 (outs VPR64:$Rd), (ins VPR64:$Rn),
7817 asmop # "\t$Rd.8b, $Rn.8b",
7820 def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7821 (outs VPR64:$Rd), (ins VPR64:$Rn),
7822 asmop # "\t$Rd.4h, $Rn.4h",
7825 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7826 (outs VPR64:$Rd), (ins VPR64:$Rn),
7827 asmop # "\t$Rd.2s, $Rn.2s",
7831 defm SQABS : NeonI_2VMisc_BHSDsize_1Arg<"sqabs", 0b0, 0b00111>;
7832 defm SQNEG : NeonI_2VMisc_BHSDsize_1Arg<"sqneg", 0b1, 0b00111>;
7833 defm ABS : NeonI_2VMisc_BHSDsize_1Arg<"abs", 0b0, 0b01011>;
7834 defm NEG : NeonI_2VMisc_BHSDsize_1Arg<"neg", 0b1, 0b01011>;
7836 multiclass NeonI_2VMisc_BHSD_1Arg_Pattern<string Prefix,
7837 SDPatternOperator Neon_Op> {
7838 def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$Rn))),
7839 (v16i8 (!cast<Instruction>(Prefix # 16b) (v16i8 VPR128:$Rn)))>;
7841 def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$Rn))),
7842 (v8i16 (!cast<Instruction>(Prefix # 8h) (v8i16 VPR128:$Rn)))>;
7844 def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$Rn))),
7845 (v4i32 (!cast<Instruction>(Prefix # 4s) (v4i32 VPR128:$Rn)))>;
7847 def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$Rn))),
7848 (v2i64 (!cast<Instruction>(Prefix # 2d) (v2i64 VPR128:$Rn)))>;
7850 def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$Rn))),
7851 (v8i8 (!cast<Instruction>(Prefix # 8b) (v8i8 VPR64:$Rn)))>;
7853 def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$Rn))),
7854 (v4i16 (!cast<Instruction>(Prefix # 4h) (v4i16 VPR64:$Rn)))>;
7856 def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$Rn))),
7857 (v2i32 (!cast<Instruction>(Prefix # 2s) (v2i32 VPR64:$Rn)))>;
7860 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQABS", int_arm_neon_vqabs>;
7861 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQNEG", int_arm_neon_vqneg>;
7862 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"ABS", int_arm_neon_vabs>;
7864 def : Pat<(v16i8 (sub
7865 (v16i8 Neon_AllZero),
7866 (v16i8 VPR128:$Rn))),
7867 (v16i8 (NEG16b (v16i8 VPR128:$Rn)))>;
7868 def : Pat<(v8i8 (sub
7869 (v8i8 Neon_AllZero),
7871 (v8i8 (NEG8b (v8i8 VPR64:$Rn)))>;
7872 def : Pat<(v8i16 (sub
7873 (v8i16 (bitconvert (v16i8 Neon_AllZero))),
7874 (v8i16 VPR128:$Rn))),
7875 (v8i16 (NEG8h (v8i16 VPR128:$Rn)))>;
7876 def : Pat<(v4i16 (sub
7877 (v4i16 (bitconvert (v8i8 Neon_AllZero))),
7878 (v4i16 VPR64:$Rn))),
7879 (v4i16 (NEG4h (v4i16 VPR64:$Rn)))>;
7880 def : Pat<(v4i32 (sub
7881 (v4i32 (bitconvert (v16i8 Neon_AllZero))),
7882 (v4i32 VPR128:$Rn))),
7883 (v4i32 (NEG4s (v4i32 VPR128:$Rn)))>;
7884 def : Pat<(v2i32 (sub
7885 (v2i32 (bitconvert (v8i8 Neon_AllZero))),
7886 (v2i32 VPR64:$Rn))),
7887 (v2i32 (NEG2s (v2i32 VPR64:$Rn)))>;
7888 def : Pat<(v2i64 (sub
7889 (v2i64 (bitconvert (v16i8 Neon_AllZero))),
7890 (v2i64 VPR128:$Rn))),
7891 (v2i64 (NEG2d (v2i64 VPR128:$Rn)))>;
7893 multiclass NeonI_2VMisc_BHSDsize_2Args<string asmop, bit U, bits<5> opcode> {
7894 let Constraints = "$src = $Rd" in {
7895 def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7896 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7897 asmop # "\t$Rd.16b, $Rn.16b",
7900 def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7901 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7902 asmop # "\t$Rd.8h, $Rn.8h",
7905 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7906 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7907 asmop # "\t$Rd.4s, $Rn.4s",
7910 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7911 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7912 asmop # "\t$Rd.2d, $Rn.2d",
7915 def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7916 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7917 asmop # "\t$Rd.8b, $Rn.8b",
7920 def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7921 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7922 asmop # "\t$Rd.4h, $Rn.4h",
7925 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7926 (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7927 asmop # "\t$Rd.2s, $Rn.2s",
7932 defm SUQADD : NeonI_2VMisc_BHSDsize_2Args<"suqadd", 0b0, 0b00011>;
7933 defm USQADD : NeonI_2VMisc_BHSDsize_2Args<"usqadd", 0b1, 0b00011>;
7935 multiclass NeonI_2VMisc_BHSD_2Args_Pattern<string Prefix,
7936 SDPatternOperator Neon_Op> {
7937 def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$src), (v16i8 VPR128:$Rn))),
7938 (v16i8 (!cast<Instruction>(Prefix # 16b)
7939 (v16i8 VPR128:$src), (v16i8 VPR128:$Rn)))>;
7941 def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$src), (v8i16 VPR128:$Rn))),
7942 (v8i16 (!cast<Instruction>(Prefix # 8h)
7943 (v8i16 VPR128:$src), (v8i16 VPR128:$Rn)))>;
7945 def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$src), (v4i32 VPR128:$Rn))),
7946 (v4i32 (!cast<Instruction>(Prefix # 4s)
7947 (v4i32 VPR128:$src), (v4i32 VPR128:$Rn)))>;
7949 def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$src), (v2i64 VPR128:$Rn))),
7950 (v2i64 (!cast<Instruction>(Prefix # 2d)
7951 (v2i64 VPR128:$src), (v2i64 VPR128:$Rn)))>;
7953 def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$src), (v8i8 VPR64:$Rn))),
7954 (v8i8 (!cast<Instruction>(Prefix # 8b)
7955 (v8i8 VPR64:$src), (v8i8 VPR64:$Rn)))>;
7957 def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$src), (v4i16 VPR64:$Rn))),
7958 (v4i16 (!cast<Instruction>(Prefix # 4h)
7959 (v4i16 VPR64:$src), (v4i16 VPR64:$Rn)))>;
7961 def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$src), (v2i32 VPR64:$Rn))),
7962 (v2i32 (!cast<Instruction>(Prefix # 2s)
7963 (v2i32 VPR64:$src), (v2i32 VPR64:$Rn)))>;
7966 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"SUQADD", int_aarch64_neon_suqadd>;
7967 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"USQADD", int_aarch64_neon_usqadd>;
7969 multiclass NeonI_2VMisc_BHSsizes<string asmop, bit U,
7970 SDPatternOperator Neon_Op> {
7971 def 16b : NeonI_2VMisc<0b1, U, 0b00, 0b00100,
7972 (outs VPR128:$Rd), (ins VPR128:$Rn),
7973 asmop # "\t$Rd.16b, $Rn.16b",
7974 [(set (v16i8 VPR128:$Rd),
7975 (v16i8 (Neon_Op (v16i8 VPR128:$Rn))))],
7978 def 8h : NeonI_2VMisc<0b1, U, 0b01, 0b00100,
7979 (outs VPR128:$Rd), (ins VPR128:$Rn),
7980 asmop # "\t$Rd.8h, $Rn.8h",
7981 [(set (v8i16 VPR128:$Rd),
7982 (v8i16 (Neon_Op (v8i16 VPR128:$Rn))))],
7985 def 4s : NeonI_2VMisc<0b1, U, 0b10, 0b00100,
7986 (outs VPR128:$Rd), (ins VPR128:$Rn),
7987 asmop # "\t$Rd.4s, $Rn.4s",
7988 [(set (v4i32 VPR128:$Rd),
7989 (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
7992 def 8b : NeonI_2VMisc<0b0, U, 0b00, 0b00100,
7993 (outs VPR64:$Rd), (ins VPR64:$Rn),
7994 asmop # "\t$Rd.8b, $Rn.8b",
7995 [(set (v8i8 VPR64:$Rd),
7996 (v8i8 (Neon_Op (v8i8 VPR64:$Rn))))],
7999 def 4h : NeonI_2VMisc<0b0, U, 0b01, 0b00100,
8000 (outs VPR64:$Rd), (ins VPR64:$Rn),
8001 asmop # "\t$Rd.4h, $Rn.4h",
8002 [(set (v4i16 VPR64:$Rd),
8003 (v4i16 (Neon_Op (v4i16 VPR64:$Rn))))],
8006 def 2s : NeonI_2VMisc<0b0, U, 0b10, 0b00100,
8007 (outs VPR64:$Rd), (ins VPR64:$Rn),
8008 asmop # "\t$Rd.2s, $Rn.2s",
8009 [(set (v2i32 VPR64:$Rd),
8010 (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8014 defm CLS : NeonI_2VMisc_BHSsizes<"cls", 0b0, int_arm_neon_vcls>;
8015 defm CLZ : NeonI_2VMisc_BHSsizes<"clz", 0b1, ctlz>;
8017 multiclass NeonI_2VMisc_Bsize<string asmop, bit U, bits<2> size,
8019 def 16b : NeonI_2VMisc<0b1, U, size, Opcode,
8020 (outs VPR128:$Rd), (ins VPR128:$Rn),
8021 asmop # "\t$Rd.16b, $Rn.16b",
8024 def 8b : NeonI_2VMisc<0b0, U, size, Opcode,
8025 (outs VPR64:$Rd), (ins VPR64:$Rn),
8026 asmop # "\t$Rd.8b, $Rn.8b",
8030 defm CNT : NeonI_2VMisc_Bsize<"cnt", 0b0, 0b00, 0b00101>;
8031 defm NOT : NeonI_2VMisc_Bsize<"not", 0b1, 0b00, 0b00101>;
8032 defm RBIT : NeonI_2VMisc_Bsize<"rbit", 0b1, 0b01, 0b00101>;
8034 def : NeonInstAlias<"mvn $Rd.16b, $Rn.16b",
8035 (NOT16b VPR128:$Rd, VPR128:$Rn), 0>;
8036 def : NeonInstAlias<"mvn $Rd.8b, $Rn.8b",
8037 (NOT8b VPR64:$Rd, VPR64:$Rn), 0>;
8039 def : Pat<(v16i8 (ctpop (v16i8 VPR128:$Rn))),
8040 (v16i8 (CNT16b (v16i8 VPR128:$Rn)))>;
8041 def : Pat<(v8i8 (ctpop (v8i8 VPR64:$Rn))),
8042 (v8i8 (CNT8b (v8i8 VPR64:$Rn)))>;
8044 def : Pat<(v16i8 (xor
8046 (v16i8 Neon_AllOne))),
8047 (v16i8 (NOT16b (v16i8 VPR128:$Rn)))>;
8048 def : Pat<(v8i8 (xor
8050 (v8i8 Neon_AllOne))),
8051 (v8i8 (NOT8b (v8i8 VPR64:$Rn)))>;
8052 def : Pat<(v8i16 (xor
8054 (v8i16 (bitconvert (v16i8 Neon_AllOne))))),
8055 (NOT16b VPR128:$Rn)>;
8056 def : Pat<(v4i16 (xor
8058 (v4i16 (bitconvert (v8i8 Neon_AllOne))))),
8060 def : Pat<(v4i32 (xor
8062 (v4i32 (bitconvert (v16i8 Neon_AllOne))))),
8063 (NOT16b VPR128:$Rn)>;
8064 def : Pat<(v2i32 (xor
8066 (v2i32 (bitconvert (v8i8 Neon_AllOne))))),
8068 def : Pat<(v2i64 (xor
8070 (v2i64 (bitconvert (v16i8 Neon_AllOne))))),
8071 (NOT16b VPR128:$Rn)>;
8073 def : Pat<(v16i8 (int_aarch64_neon_rbit (v16i8 VPR128:$Rn))),
8074 (v16i8 (RBIT16b (v16i8 VPR128:$Rn)))>;
8075 def : Pat<(v8i8 (int_aarch64_neon_rbit (v8i8 VPR64:$Rn))),
8076 (v8i8 (RBIT8b (v8i8 VPR64:$Rn)))>;
8078 multiclass NeonI_2VMisc_SDsizes<string asmop, bit U, bits<5> opcode,
8079 SDPatternOperator Neon_Op> {
8080 def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8081 (outs VPR128:$Rd), (ins VPR128:$Rn),
8082 asmop # "\t$Rd.4s, $Rn.4s",
8083 [(set (v4f32 VPR128:$Rd),
8084 (v4f32 (Neon_Op (v4f32 VPR128:$Rn))))],
8087 def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
8088 (outs VPR128:$Rd), (ins VPR128:$Rn),
8089 asmop # "\t$Rd.2d, $Rn.2d",
8090 [(set (v2f64 VPR128:$Rd),
8091 (v2f64 (Neon_Op (v2f64 VPR128:$Rn))))],
8094 def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8095 (outs VPR64:$Rd), (ins VPR64:$Rn),
8096 asmop # "\t$Rd.2s, $Rn.2s",
8097 [(set (v2f32 VPR64:$Rd),
8098 (v2f32 (Neon_Op (v2f32 VPR64:$Rn))))],
8102 defm FABS : NeonI_2VMisc_SDsizes<"fabs", 0b0, 0b01111, fabs>;
8103 defm FNEG : NeonI_2VMisc_SDsizes<"fneg", 0b1, 0b01111, fneg>;
8105 multiclass NeonI_2VMisc_HSD_Narrow<string asmop, bit U, bits<5> opcode> {
8106 def 8h8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
8107 (outs VPR64:$Rd), (ins VPR128:$Rn),
8108 asmop # "\t$Rd.8b, $Rn.8h",
8111 def 4s4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
8112 (outs VPR64:$Rd), (ins VPR128:$Rn),
8113 asmop # "\t$Rd.4h, $Rn.4s",
8116 def 2d2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8117 (outs VPR64:$Rd), (ins VPR128:$Rn),
8118 asmop # "\t$Rd.2s, $Rn.2d",
8121 let Constraints = "$Rd = $src" in {
8122 def 8h16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
8123 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8124 asmop # "2\t$Rd.16b, $Rn.8h",
8127 def 4s8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
8128 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8129 asmop # "2\t$Rd.8h, $Rn.4s",
8132 def 2d4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8133 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8134 asmop # "2\t$Rd.4s, $Rn.2d",
8139 defm XTN : NeonI_2VMisc_HSD_Narrow<"xtn", 0b0, 0b10010>;
8140 defm SQXTUN : NeonI_2VMisc_HSD_Narrow<"sqxtun", 0b1, 0b10010>;
8141 defm SQXTN : NeonI_2VMisc_HSD_Narrow<"sqxtn", 0b0, 0b10100>;
8142 defm UQXTN : NeonI_2VMisc_HSD_Narrow<"uqxtn", 0b1, 0b10100>;
8144 multiclass NeonI_2VMisc_Narrow_Patterns<string Prefix,
8145 SDPatternOperator Neon_Op> {
8146 def : Pat<(v8i8 (Neon_Op (v8i16 VPR128:$Rn))),
8147 (v8i8 (!cast<Instruction>(Prefix # 8h8b) (v8i16 VPR128:$Rn)))>;
8149 def : Pat<(v4i16 (Neon_Op (v4i32 VPR128:$Rn))),
8150 (v4i16 (!cast<Instruction>(Prefix # 4s4h) (v4i32 VPR128:$Rn)))>;
8152 def : Pat<(v2i32 (Neon_Op (v2i64 VPR128:$Rn))),
8153 (v2i32 (!cast<Instruction>(Prefix # 2d2s) (v2i64 VPR128:$Rn)))>;
8155 def : Pat<(v16i8 (concat_vectors
8157 (v8i8 (Neon_Op (v8i16 VPR128:$Rn))))),
8158 (!cast<Instruction>(Prefix # 8h16b)
8159 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8162 def : Pat<(v8i16 (concat_vectors
8164 (v4i16 (Neon_Op (v4i32 VPR128:$Rn))))),
8165 (!cast<Instruction>(Prefix # 4s8h)
8166 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8169 def : Pat<(v4i32 (concat_vectors
8171 (v2i32 (Neon_Op (v2i64 VPR128:$Rn))))),
8172 (!cast<Instruction>(Prefix # 2d4s)
8173 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8177 defm : NeonI_2VMisc_Narrow_Patterns<"XTN", trunc>;
8178 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTUN", int_arm_neon_vqmovnsu>;
8179 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTN", int_arm_neon_vqmovns>;
8180 defm : NeonI_2VMisc_Narrow_Patterns<"UQXTN", int_arm_neon_vqmovnu>;
8182 multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> {
8183 let DecoderMethod = "DecodeSHLLInstruction" in {
8184 def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8186 (ins VPR64:$Rn, uimm_exact8:$Imm),
8187 asmop # "\t$Rd.8h, $Rn.8b, $Imm",
8190 def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8192 (ins VPR64:$Rn, uimm_exact16:$Imm),
8193 asmop # "\t$Rd.4s, $Rn.4h, $Imm",
8196 def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
8198 (ins VPR64:$Rn, uimm_exact32:$Imm),
8199 asmop # "\t$Rd.2d, $Rn.2s, $Imm",
8202 def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8204 (ins VPR128:$Rn, uimm_exact8:$Imm),
8205 asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
8208 def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8210 (ins VPR128:$Rn, uimm_exact16:$Imm),
8211 asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
8214 def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
8216 (ins VPR128:$Rn, uimm_exact32:$Imm),
8217 asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
8222 defm SHLL : NeonI_2VMisc_SHIFT<"shll", 0b1, 0b10011>;
8224 class NeonI_SHLL_Patterns<ValueType OpTy, ValueType DesTy,
8225 SDPatternOperator ExtOp, Operand Neon_Imm,
8228 (DesTy (ExtOp (OpTy VPR64:$Rn))),
8230 (i32 Neon_Imm:$Imm))))),
8231 (!cast<Instruction>("SHLL" # suffix) VPR64:$Rn, Neon_Imm:$Imm)>;
8233 class NeonI_SHLL_High_Patterns<ValueType OpTy, ValueType DesTy,
8234 SDPatternOperator ExtOp, Operand Neon_Imm,
8235 string suffix, PatFrag GetHigh>
8238 (OpTy (GetHigh VPR128:$Rn)))),
8240 (i32 Neon_Imm:$Imm))))),
8241 (!cast<Instruction>("SHLL" # suffix) VPR128:$Rn, Neon_Imm:$Imm)>;
8243 def : NeonI_SHLL_Patterns<v8i8, v8i16, zext, uimm_exact8, "8b8h">;
8244 def : NeonI_SHLL_Patterns<v8i8, v8i16, sext, uimm_exact8, "8b8h">;
8245 def : NeonI_SHLL_Patterns<v4i16, v4i32, zext, uimm_exact16, "4h4s">;
8246 def : NeonI_SHLL_Patterns<v4i16, v4i32, sext, uimm_exact16, "4h4s">;
8247 def : NeonI_SHLL_Patterns<v2i32, v2i64, zext, uimm_exact32, "2s2d">;
8248 def : NeonI_SHLL_Patterns<v2i32, v2i64, sext, uimm_exact32, "2s2d">;
8249 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, zext, uimm_exact8, "16b8h",
8251 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, sext, uimm_exact8, "16b8h",
8253 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, zext, uimm_exact16, "8h4s",
8255 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, sext, uimm_exact16, "8h4s",
8257 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, zext, uimm_exact32, "4s2d",
8259 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, sext, uimm_exact32, "4s2d",
8262 multiclass NeonI_2VMisc_SD_Narrow<string asmop, bit U, bits<5> opcode> {
8263 def 4s4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8264 (outs VPR64:$Rd), (ins VPR128:$Rn),
8265 asmop # "\t$Rd.4h, $Rn.4s",
8268 def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8269 (outs VPR64:$Rd), (ins VPR128:$Rn),
8270 asmop # "\t$Rd.2s, $Rn.2d",
8273 let Constraints = "$src = $Rd" in {
8274 def 4s8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8275 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8276 asmop # "2\t$Rd.8h, $Rn.4s",
8279 def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8280 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8281 asmop # "2\t$Rd.4s, $Rn.2d",
8286 defm FCVTN : NeonI_2VMisc_SD_Narrow<"fcvtn", 0b0, 0b10110>;
8288 multiclass NeonI_2VMisc_Narrow_Pattern<string prefix,
8289 SDPatternOperator f32_to_f16_Op,
8290 SDPatternOperator f64_to_f32_Op> {
8292 def : Pat<(v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))),
8293 (!cast<Instruction>(prefix # "4s4h") (v4f32 VPR128:$Rn))>;
8295 def : Pat<(v8i16 (concat_vectors
8297 (v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))))),
8298 (!cast<Instruction>(prefix # "4s8h")
8299 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8300 (v4f32 VPR128:$Rn))>;
8302 def : Pat<(v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))),
8303 (!cast<Instruction>(prefix # "2d2s") (v2f64 VPR128:$Rn))>;
8305 def : Pat<(v4f32 (concat_vectors
8307 (v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))))),
8308 (!cast<Instruction>(prefix # "2d4s")
8309 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8310 (v2f64 VPR128:$Rn))>;
8313 defm : NeonI_2VMisc_Narrow_Pattern<"FCVTN", int_arm_neon_vcvtfp2hf, fround>;
8315 multiclass NeonI_2VMisc_D_Narrow<string asmop, string prefix, bit U,
8317 def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8318 (outs VPR64:$Rd), (ins VPR128:$Rn),
8319 asmop # "\t$Rd.2s, $Rn.2d",
8322 def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8323 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8324 asmop # "2\t$Rd.4s, $Rn.2d",
8326 let Constraints = "$src = $Rd";
8329 def : Pat<(v2f32 (int_aarch64_neon_vcvtxn (v2f64 VPR128:$Rn))),
8330 (!cast<Instruction>(prefix # "2d2s") VPR128:$Rn)>;
8332 def : Pat<(v4f32 (concat_vectors
8334 (v2f32 (int_aarch64_neon_vcvtxn (v2f64 VPR128:$Rn))))),
8335 (!cast<Instruction>(prefix # "2d4s")
8336 (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8340 defm FCVTXN : NeonI_2VMisc_D_Narrow<"fcvtxn","FCVTXN", 0b1, 0b10110>;
8342 def Neon_High4Float : PatFrag<(ops node:$in),
8343 (extract_subvector (v4f32 node:$in), (iPTR 2))>;
8345 multiclass NeonI_2VMisc_HS_Extend<string asmop, bit U, bits<5> opcode> {
8346 def 4h4s : NeonI_2VMisc<0b0, U, 0b00, opcode,
8347 (outs VPR128:$Rd), (ins VPR64:$Rn),
8348 asmop # "\t$Rd.4s, $Rn.4h",
8351 def 2s2d : NeonI_2VMisc<0b0, U, 0b01, opcode,
8352 (outs VPR128:$Rd), (ins VPR64:$Rn),
8353 asmop # "\t$Rd.2d, $Rn.2s",
8356 def 8h4s : NeonI_2VMisc<0b1, U, 0b00, opcode,
8357 (outs VPR128:$Rd), (ins VPR128:$Rn),
8358 asmop # "2\t$Rd.4s, $Rn.8h",
8361 def 4s2d : NeonI_2VMisc<0b1, U, 0b01, opcode,
8362 (outs VPR128:$Rd), (ins VPR128:$Rn),
8363 asmop # "2\t$Rd.2d, $Rn.4s",
8367 defm FCVTL : NeonI_2VMisc_HS_Extend<"fcvtl", 0b0, 0b10111>;
8369 multiclass NeonI_2VMisc_Extend_Pattern<string prefix> {
8370 def : Pat<(v4f32 (int_arm_neon_vcvthf2fp (v4i16 VPR64:$Rn))),
8371 (!cast<Instruction>(prefix # "4h4s") VPR64:$Rn)>;
8373 def : Pat<(v4f32 (int_arm_neon_vcvthf2fp
8375 (v8i16 VPR128:$Rn))))),
8376 (!cast<Instruction>(prefix # "8h4s") VPR128:$Rn)>;
8378 def : Pat<(v2f64 (fextend (v2f32 VPR64:$Rn))),
8379 (!cast<Instruction>(prefix # "2s2d") VPR64:$Rn)>;
8381 def : Pat<(v2f64 (fextend
8382 (v2f32 (Neon_High4Float
8383 (v4f32 VPR128:$Rn))))),
8384 (!cast<Instruction>(prefix # "4s2d") VPR128:$Rn)>;
8387 defm : NeonI_2VMisc_Extend_Pattern<"FCVTL">;
8389 multiclass NeonI_2VMisc_SD_Conv<string asmop, bit Size, bit U, bits<5> opcode,
8390 ValueType ResTy4s, ValueType OpTy4s,
8391 ValueType ResTy2d, ValueType OpTy2d,
8392 ValueType ResTy2s, ValueType OpTy2s,
8393 SDPatternOperator Neon_Op> {
8395 def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8396 (outs VPR128:$Rd), (ins VPR128:$Rn),
8397 asmop # "\t$Rd.4s, $Rn.4s",
8398 [(set (ResTy4s VPR128:$Rd),
8399 (ResTy4s (Neon_Op (OpTy4s VPR128:$Rn))))],
8402 def 2d : NeonI_2VMisc<0b1, U, {Size, 0b1}, opcode,
8403 (outs VPR128:$Rd), (ins VPR128:$Rn),
8404 asmop # "\t$Rd.2d, $Rn.2d",
8405 [(set (ResTy2d VPR128:$Rd),
8406 (ResTy2d (Neon_Op (OpTy2d VPR128:$Rn))))],
8409 def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8410 (outs VPR64:$Rd), (ins VPR64:$Rn),
8411 asmop # "\t$Rd.2s, $Rn.2s",
8412 [(set (ResTy2s VPR64:$Rd),
8413 (ResTy2s (Neon_Op (OpTy2s VPR64:$Rn))))],
8417 multiclass NeonI_2VMisc_fp_to_int<string asmop, bit Size, bit U,
8418 bits<5> opcode, SDPatternOperator Neon_Op> {
8419 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4i32, v4f32, v2i64,
8420 v2f64, v2i32, v2f32, Neon_Op>;
8423 defm FCVTNS : NeonI_2VMisc_fp_to_int<"fcvtns", 0b0, 0b0, 0b11010,
8424 int_arm_neon_vcvtns>;
8425 defm FCVTNU : NeonI_2VMisc_fp_to_int<"fcvtnu", 0b0, 0b1, 0b11010,
8426 int_arm_neon_vcvtnu>;
8427 defm FCVTPS : NeonI_2VMisc_fp_to_int<"fcvtps", 0b1, 0b0, 0b11010,
8428 int_arm_neon_vcvtps>;
8429 defm FCVTPU : NeonI_2VMisc_fp_to_int<"fcvtpu", 0b1, 0b1, 0b11010,
8430 int_arm_neon_vcvtpu>;
8431 defm FCVTMS : NeonI_2VMisc_fp_to_int<"fcvtms", 0b0, 0b0, 0b11011,
8432 int_arm_neon_vcvtms>;
8433 defm FCVTMU : NeonI_2VMisc_fp_to_int<"fcvtmu", 0b0, 0b1, 0b11011,
8434 int_arm_neon_vcvtmu>;
8435 defm FCVTZS : NeonI_2VMisc_fp_to_int<"fcvtzs", 0b1, 0b0, 0b11011, fp_to_sint>;
8436 defm FCVTZU : NeonI_2VMisc_fp_to_int<"fcvtzu", 0b1, 0b1, 0b11011, fp_to_uint>;
8437 defm FCVTAS : NeonI_2VMisc_fp_to_int<"fcvtas", 0b0, 0b0, 0b11100,
8438 int_arm_neon_vcvtas>;
8439 defm FCVTAU : NeonI_2VMisc_fp_to_int<"fcvtau", 0b0, 0b1, 0b11100,
8440 int_arm_neon_vcvtau>;
8442 multiclass NeonI_2VMisc_int_to_fp<string asmop, bit Size, bit U,
8443 bits<5> opcode, SDPatternOperator Neon_Op> {
8444 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4i32, v2f64,
8445 v2i64, v2f32, v2i32, Neon_Op>;
8448 defm SCVTF : NeonI_2VMisc_int_to_fp<"scvtf", 0b0, 0b0, 0b11101, sint_to_fp>;
8449 defm UCVTF : NeonI_2VMisc_int_to_fp<"ucvtf", 0b0, 0b1, 0b11101, uint_to_fp>;
8451 multiclass NeonI_2VMisc_fp_to_fp<string asmop, bit Size, bit U,
8452 bits<5> opcode, SDPatternOperator Neon_Op> {
8453 defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4f32, v2f64,
8454 v2f64, v2f32, v2f32, Neon_Op>;
8457 defm FRINTN : NeonI_2VMisc_fp_to_fp<"frintn", 0b0, 0b0, 0b11000,
8458 int_aarch64_neon_frintn>;
8459 defm FRINTA : NeonI_2VMisc_fp_to_fp<"frinta", 0b0, 0b1, 0b11000, frnd>;
8460 defm FRINTP : NeonI_2VMisc_fp_to_fp<"frintp", 0b1, 0b0, 0b11000, fceil>;
8461 defm FRINTM : NeonI_2VMisc_fp_to_fp<"frintm", 0b0, 0b0, 0b11001, ffloor>;
8462 defm FRINTX : NeonI_2VMisc_fp_to_fp<"frintx", 0b0, 0b1, 0b11001, frint>;
8463 defm FRINTZ : NeonI_2VMisc_fp_to_fp<"frintz", 0b1, 0b0, 0b11001, ftrunc>;
8464 defm FRINTI : NeonI_2VMisc_fp_to_fp<"frinti", 0b1, 0b1, 0b11001, fnearbyint>;
8465 defm FRECPE : NeonI_2VMisc_fp_to_fp<"frecpe", 0b1, 0b0, 0b11101,
8466 int_arm_neon_vrecpe>;
8467 defm FRSQRTE : NeonI_2VMisc_fp_to_fp<"frsqrte", 0b1, 0b1, 0b11101,
8468 int_arm_neon_vrsqrte>;
8469 defm FSQRT : NeonI_2VMisc_fp_to_fp<"fsqrt", 0b1, 0b1, 0b11111, fsqrt>;
8471 multiclass NeonI_2VMisc_S_Conv<string asmop, bit Size, bit U,
8472 bits<5> opcode, SDPatternOperator Neon_Op> {
8473 def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8474 (outs VPR128:$Rd), (ins VPR128:$Rn),
8475 asmop # "\t$Rd.4s, $Rn.4s",
8476 [(set (v4i32 VPR128:$Rd),
8477 (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
8480 def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8481 (outs VPR64:$Rd), (ins VPR64:$Rn),
8482 asmop # "\t$Rd.2s, $Rn.2s",
8483 [(set (v2i32 VPR64:$Rd),
8484 (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8488 defm URECPE : NeonI_2VMisc_S_Conv<"urecpe", 0b1, 0b0, 0b11100,
8489 int_arm_neon_vrecpe>;
8490 defm URSQRTE : NeonI_2VMisc_S_Conv<"ursqrte", 0b1, 0b1, 0b11100,
8491 int_arm_neon_vrsqrte>;
8494 class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
8495 string asmop, SDPatternOperator opnode>
8496 : NeonI_Crypto_AES<size, opcode,
8497 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8498 asmop # "\t$Rd.16b, $Rn.16b",
8499 [(set (v16i8 VPR128:$Rd),
8500 (v16i8 (opnode (v16i8 VPR128:$src),
8501 (v16i8 VPR128:$Rn))))],
8503 let Constraints = "$src = $Rd";
8504 let Predicates = [HasNEON, HasCrypto];
8507 def AESE : NeonI_Cryptoaes_2v<0b00, 0b00100, "aese", int_arm_neon_aese>;
8508 def AESD : NeonI_Cryptoaes_2v<0b00, 0b00101, "aesd", int_arm_neon_aesd>;
8510 class NeonI_Cryptoaes<bits<2> size, bits<5> opcode,
8511 string asmop, SDPatternOperator opnode>
8512 : NeonI_Crypto_AES<size, opcode,
8513 (outs VPR128:$Rd), (ins VPR128:$Rn),
8514 asmop # "\t$Rd.16b, $Rn.16b",
8515 [(set (v16i8 VPR128:$Rd),
8516 (v16i8 (opnode (v16i8 VPR128:$Rn))))],
8519 def AESMC : NeonI_Cryptoaes<0b00, 0b00110, "aesmc", int_arm_neon_aesmc>;
8520 def AESIMC : NeonI_Cryptoaes<0b00, 0b00111, "aesimc", int_arm_neon_aesimc>;
8522 class NeonI_Cryptosha_vv<bits<2> size, bits<5> opcode,
8523 string asmop, SDPatternOperator opnode>
8524 : NeonI_Crypto_SHA<size, opcode,
8525 (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8526 asmop # "\t$Rd.4s, $Rn.4s",
8527 [(set (v4i32 VPR128:$Rd),
8528 (v4i32 (opnode (v4i32 VPR128:$src),
8529 (v4i32 VPR128:$Rn))))],
8531 let Constraints = "$src = $Rd";
8532 let Predicates = [HasNEON, HasCrypto];
8535 def SHA1SU1 : NeonI_Cryptosha_vv<0b00, 0b00001, "sha1su1",
8536 int_arm_neon_sha1su1>;
8537 def SHA256SU0 : NeonI_Cryptosha_vv<0b00, 0b00010, "sha256su0",
8538 int_arm_neon_sha256su0>;
8540 class NeonI_Cryptosha_ss<bits<2> size, bits<5> opcode,
8541 string asmop, SDPatternOperator opnode>
8542 : NeonI_Crypto_SHA<size, opcode,
8543 (outs FPR32:$Rd), (ins FPR32:$Rn),
8544 asmop # "\t$Rd, $Rn",
8545 [(set (v1i32 FPR32:$Rd),
8546 (v1i32 (opnode (v1i32 FPR32:$Rn))))],
8548 let Predicates = [HasNEON, HasCrypto];
8551 def SHA1H : NeonI_Cryptosha_ss<0b00, 0b00000, "sha1h", int_arm_neon_sha1h>;
8553 class NeonI_Cryptosha3_vvv<bits<2> size, bits<3> opcode, string asmop,
8554 SDPatternOperator opnode>
8555 : NeonI_Crypto_3VSHA<size, opcode,
8557 (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
8558 asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
8559 [(set (v4i32 VPR128:$Rd),
8560 (v4i32 (opnode (v4i32 VPR128:$src),
8562 (v4i32 VPR128:$Rm))))],
8564 let Constraints = "$src = $Rd";
8565 let Predicates = [HasNEON, HasCrypto];
8568 def SHA1SU0 : NeonI_Cryptosha3_vvv<0b00, 0b011, "sha1su0",
8569 int_arm_neon_sha1su0>;
8570 def SHA256SU1 : NeonI_Cryptosha3_vvv<0b00, 0b110, "sha256su1",
8571 int_arm_neon_sha256su1>;
8573 class NeonI_Cryptosha3_qqv<bits<2> size, bits<3> opcode, string asmop,
8574 SDPatternOperator opnode>
8575 : NeonI_Crypto_3VSHA<size, opcode,
8577 (ins FPR128:$src, FPR128:$Rn, VPR128:$Rm),
8578 asmop # "\t$Rd, $Rn, $Rm.4s",
8579 [(set (v4i32 FPR128:$Rd),
8580 (v4i32 (opnode (v4i32 FPR128:$src),
8582 (v4i32 VPR128:$Rm))))],
8584 let Constraints = "$src = $Rd";
8585 let Predicates = [HasNEON, HasCrypto];
8588 def SHA256H : NeonI_Cryptosha3_qqv<0b00, 0b100, "sha256h",
8589 int_arm_neon_sha256h>;
8590 def SHA256H2 : NeonI_Cryptosha3_qqv<0b00, 0b101, "sha256h2",
8591 int_arm_neon_sha256h2>;
8593 class NeonI_Cryptosha3_qsv<bits<2> size, bits<3> opcode, string asmop,
8594 SDPatternOperator opnode>
8595 : NeonI_Crypto_3VSHA<size, opcode,
8597 (ins FPR128:$src, FPR32:$Rn, VPR128:$Rm),
8598 asmop # "\t$Rd, $Rn, $Rm.4s",
8599 [(set (v4i32 FPR128:$Rd),
8600 (v4i32 (opnode (v4i32 FPR128:$src),
8602 (v4i32 VPR128:$Rm))))],
8604 let Constraints = "$src = $Rd";
8605 let Predicates = [HasNEON, HasCrypto];
8608 def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
8609 def SHA1P : NeonI_Cryptosha3_qsv<0b00, 0b001, "sha1p", int_aarch64_neon_sha1p>;
8610 def SHA1M : NeonI_Cryptosha3_qsv<0b00, 0b010, "sha1m", int_aarch64_neon_sha1m>;
8613 // Patterns for handling half-precision values
8616 // Convert f16 value coming in as i16 value to f32
8617 def : Pat<(f32 (f16_to_f32 (i32 (and (i32 GPR32:$Rn), 65535)))),
8618 (FCVTsh (EXTRACT_SUBREG (FMOVsw GPR32:$Rn), sub_16))>;
8619 def : Pat<(f32 (f16_to_f32 (i32 (assertzext GPR32:$Rn)))),
8620 (FCVTsh (EXTRACT_SUBREG (FMOVsw GPR32:$Rn), sub_16))>;
8622 def : Pat<(f32 (f16_to_f32 (i32 (assertzext (i32 (
8623 f32_to_f16 (f32 FPR32:$Rn))))))),
8626 // Patterns for vector extract of half-precision FP value in i16 storage type
8627 def : Pat<(f32 (f16_to_f32 ( i32 (and (i32 (vector_extract
8628 (v4i16 VPR64:$Rn), neon_uimm2_bare:$Imm)), 65535)))),
8629 (FCVTsh (f16 (DUPhv_H
8630 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8631 neon_uimm2_bare:$Imm)))>;
8633 def : Pat<(f32 (f16_to_f32 ( i32 (and (i32 (vector_extract
8634 (v8i16 VPR128:$Rn), neon_uimm3_bare:$Imm)), 65535)))),
8635 (FCVTsh (f16 (DUPhv_H (v8i16 VPR128:$Rn), neon_uimm3_bare:$Imm)))>;
8637 // Patterns for vector insert of half-precision FP value 0 in i16 storage type
8638 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8639 (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 0))))))),
8640 (neon_uimm3_bare:$Imm))),
8641 (v8i16 (INSELh (v8i16 VPR128:$Rn),
8642 (v8i16 (SUBREG_TO_REG (i64 0),
8643 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 WZR))), sub_16)),
8645 neon_uimm3_bare:$Imm, 0))>;
8647 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8648 (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 0))))))),
8649 (neon_uimm2_bare:$Imm))),
8650 (v4i16 (EXTRACT_SUBREG
8652 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8653 (v8i16 (SUBREG_TO_REG (i64 0),
8654 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 WZR))), sub_16)),
8656 neon_uimm2_bare:$Imm, 0)),
8659 // Patterns for vector insert of half-precision FP value in i16 storage type
8660 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8661 (i32 (assertsext (i32 (fp_to_sint
8662 (f32 (f16_to_f32 (i32 (and (i32 GPR32:$src), 65535)))))))),
8663 (neon_uimm3_bare:$Imm))),
8664 (v8i16 (INSELh (v8i16 VPR128:$Rn),
8665 (v8i16 (SUBREG_TO_REG (i64 0),
8666 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 GPR32:$src))), sub_16)),
8668 neon_uimm3_bare:$Imm, 0))>;
8670 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8671 (i32 (assertsext (i32 (fp_to_sint
8672 (f32 (f16_to_f32 (i32 (and (i32 GPR32:$src), 65535)))))))),
8673 (neon_uimm2_bare:$Imm))),
8674 (v4i16 (EXTRACT_SUBREG
8676 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8677 (v8i16 (SUBREG_TO_REG (i64 0),
8678 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 GPR32:$src))), sub_16)),
8680 neon_uimm2_bare:$Imm, 0)),
8683 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8684 (i32 (vector_extract (v8i16 VPR128:$src), neon_uimm3_bare:$Imm2)),
8685 (neon_uimm3_bare:$Imm1))),
8686 (v8i16 (INSELh (v8i16 VPR128:$Rn), (v8i16 VPR128:$src),
8687 neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2))>;
8689 // Patterns for vector copy of half-precision FP value in i16 storage type
8690 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8691 (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 (and (i32
8692 (vector_extract (v8i16 VPR128:$src), neon_uimm3_bare:$Imm2)),
8694 (neon_uimm3_bare:$Imm1))),
8695 (v8i16 (INSELh (v8i16 VPR128:$Rn), (v8i16 VPR128:$src),
8696 neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2))>;
8698 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8699 (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 (and (i32
8700 (vector_extract (v4i16 VPR64:$src), neon_uimm3_bare:$Imm2)),
8702 (neon_uimm3_bare:$Imm1))),
8703 (v4i16 (EXTRACT_SUBREG
8705 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8706 (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
8707 neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2)),