1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // AArch64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">,
18 AssemblerPredicate<"HasV8_1aOps", "armv8.1a">;
19 def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">,
20 AssemblerPredicate<"HasV8_2aOps", "armv8.2a">;
21 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
22 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
23 def HasNEON : Predicate<"Subtarget->hasNEON()">,
24 AssemblerPredicate<"FeatureNEON", "neon">;
25 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
26 AssemblerPredicate<"FeatureCrypto", "crypto">;
27 def HasCRC : Predicate<"Subtarget->hasCRC()">,
28 AssemblerPredicate<"FeatureCRC", "crc">;
29 def HasPerfMon : Predicate<"Subtarget->hasPerfMon()">;
30 def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">,
31 AssemblerPredicate<"FeatureFullFP16", "fullfp16">;
32 def HasSPE : Predicate<"Subtarget->hasSPE()">,
33 AssemblerPredicate<"FeatureSPE", "spe">;
35 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
36 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
37 def IsCyclone : Predicate<"Subtarget->isCyclone()">;
39 //===----------------------------------------------------------------------===//
40 // AArch64-specific DAG Nodes.
43 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
44 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
47 SDTCisInt<0>, SDTCisVT<1, i32>]>;
49 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
50 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
56 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
57 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
64 def SDT_AArch64Brcond : SDTypeProfile<0, 3,
65 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
67 def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
68 def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
69 SDTCisVT<2, OtherVT>]>;
72 def SDT_AArch64CSel : SDTypeProfile<1, 4,
77 def SDT_AArch64CCMP : SDTypeProfile<1, 5,
84 def SDT_AArch64FCCMP : SDTypeProfile<1, 5,
91 def SDT_AArch64FCmp : SDTypeProfile<0, 2,
94 def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
95 def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
96 def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
99 def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
100 def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
101 def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
102 SDTCisInt<2>, SDTCisInt<3>]>;
103 def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
104 def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
105 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
106 def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
108 def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
109 def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>;
110 def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
111 def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
113 def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
116 def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
117 def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
119 def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
121 def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
124 // Generates the general dynamic sequences, i.e.
125 // adrp x0, :tlsdesc:var
126 // ldr x1, [x0, #:tlsdesc_lo12:var]
127 // add x0, x0, #:tlsdesc_lo12:var
131 // (the TPIDR_EL0 offset is put directly in X0, hence no "result" here)
132 // number of operands (the variable)
133 def SDT_AArch64TLSDescCallSeq : SDTypeProfile<0,1,
136 def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
137 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
138 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
139 SDTCisSameAs<1, 4>]>;
143 def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
144 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
145 def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
146 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
147 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
148 [SDNPHasChain, SDNPOutGlue]>;
149 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",
150 SDCallSeqEnd<[ SDTCisVT<0, i32>,
152 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
153 def AArch64call : SDNode<"AArch64ISD::CALL",
154 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
155 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
157 def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond,
159 def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,
161 def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz,
163 def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz,
165 def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz,
169 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
170 def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>;
171 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;
172 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
173 def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone,
174 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
175 def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >;
176 def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>;
177 def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut,
179 def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
180 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
182 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
183 def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
185 def AArch64ccmp : SDNode<"AArch64ISD::CCMP", SDT_AArch64CCMP>;
186 def AArch64ccmn : SDNode<"AArch64ISD::CCMN", SDT_AArch64CCMP>;
187 def AArch64fccmp : SDNode<"AArch64ISD::FCCMP", SDT_AArch64FCCMP>;
189 def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
191 def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
193 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;
194 def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;
195 def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;
196 def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>;
197 def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>;
199 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
200 def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>;
201 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
202 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;
203 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;
204 def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>;
206 def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>;
207 def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>;
208 def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>;
209 def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>;
210 def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;
211 def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;
212 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;
214 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
215 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
216 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
217 def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;
219 def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;
220 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;
221 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;
222 def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>;
223 def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>;
224 def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>;
225 def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>;
226 def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>;
228 def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>;
229 def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>;
230 def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>;
232 def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
233 def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>;
234 def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>;
235 def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>;
236 def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>;
238 def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;
239 def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>;
240 def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>;
242 def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>;
243 def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>;
244 def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>;
245 def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>;
246 def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>;
247 def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
248 (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
250 def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>;
251 def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>;
252 def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>;
253 def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>;
254 def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>;
256 def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>;
257 def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>;
259 def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>;
261 def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET,
262 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
264 def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH,
265 [SDNPHasChain, SDNPSideEffect]>;
267 def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>;
268 def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;
270 def AArch64tlsdesc_callseq : SDNode<"AArch64ISD::TLSDESC_CALLSEQ",
271 SDT_AArch64TLSDescCallSeq,
272 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
276 def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
277 SDT_AArch64WrapperLarge>;
279 def AArch64NvCast : SDNode<"AArch64ISD::NVCAST", SDTUnaryOp>;
281 def SDT_AArch64mull : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
282 SDTCisSameAs<1, 2>]>;
283 def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull>;
284 def AArch64umull : SDNode<"AArch64ISD::UMULL", SDT_AArch64mull>;
286 def AArch64saddv : SDNode<"AArch64ISD::SADDV", SDT_AArch64UnaryVec>;
287 def AArch64uaddv : SDNode<"AArch64ISD::UADDV", SDT_AArch64UnaryVec>;
288 def AArch64sminv : SDNode<"AArch64ISD::SMINV", SDT_AArch64UnaryVec>;
289 def AArch64uminv : SDNode<"AArch64ISD::UMINV", SDT_AArch64UnaryVec>;
290 def AArch64smaxv : SDNode<"AArch64ISD::SMAXV", SDT_AArch64UnaryVec>;
291 def AArch64umaxv : SDNode<"AArch64ISD::UMAXV", SDT_AArch64UnaryVec>;
293 //===----------------------------------------------------------------------===//
295 //===----------------------------------------------------------------------===//
297 // AArch64 Instruction Predicate Definitions.
299 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
300 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
301 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
302 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
303 def ForCodeSize : Predicate<"ForCodeSize">;
304 def NotForCodeSize : Predicate<"!ForCodeSize">;
306 include "AArch64InstrFormats.td"
308 //===----------------------------------------------------------------------===//
310 //===----------------------------------------------------------------------===//
311 // Miscellaneous instructions.
312 //===----------------------------------------------------------------------===//
314 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
315 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
316 [(AArch64callseq_start timm:$amt)]>;
317 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
318 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
319 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
321 let isReMaterializable = 1, isCodeGenOnly = 1 in {
322 // FIXME: The following pseudo instructions are only needed because remat
323 // cannot handle multiple instructions. When that changes, they can be
324 // removed, along with the AArch64Wrapper node.
326 let AddedComplexity = 10 in
327 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
328 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
331 // The MOVaddr instruction should match only when the add is not folded
332 // into a load or store address.
334 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
335 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
336 tglobaladdr:$low))]>,
337 Sched<[WriteAdrAdr]>;
339 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
340 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
342 Sched<[WriteAdrAdr]>;
344 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
345 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
347 Sched<[WriteAdrAdr]>;
349 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
350 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
351 tblockaddress:$low))]>,
352 Sched<[WriteAdrAdr]>;
354 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
355 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),
356 tglobaltlsaddr:$low))]>,
357 Sched<[WriteAdrAdr]>;
359 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
360 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),
361 texternalsym:$low))]>,
362 Sched<[WriteAdrAdr]>;
364 } // isReMaterializable, isCodeGenOnly
366 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
367 (LOADgot tglobaltlsaddr:$addr)>;
369 def : Pat<(AArch64LOADgot texternalsym:$addr),
370 (LOADgot texternalsym:$addr)>;
372 def : Pat<(AArch64LOADgot tconstpool:$addr),
373 (LOADgot tconstpool:$addr)>;
375 //===----------------------------------------------------------------------===//
376 // System instructions.
377 //===----------------------------------------------------------------------===//
379 def HINT : HintI<"hint">;
380 def : InstAlias<"nop", (HINT 0b000)>;
381 def : InstAlias<"yield",(HINT 0b001)>;
382 def : InstAlias<"wfe", (HINT 0b010)>;
383 def : InstAlias<"wfi", (HINT 0b011)>;
384 def : InstAlias<"sev", (HINT 0b100)>;
385 def : InstAlias<"sevl", (HINT 0b101)>;
387 // v8.2a Statistical Profiling extension
388 def : InstAlias<"psb $op", (HINT psbhint_op:$op)>, Requires<[HasSPE]>;
390 // As far as LLVM is concerned this writes to the system's exclusive monitors.
391 let mayLoad = 1, mayStore = 1 in
392 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
394 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
395 // model patterns with sufficiently fine granularity.
396 let mayLoad = ?, mayStore = ? in {
397 def DMB : CRmSystemI<barrier_op, 0b101, "dmb",
398 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;
400 def DSB : CRmSystemI<barrier_op, 0b100, "dsb",
401 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
403 def ISB : CRmSystemI<barrier_op, 0b110, "isb",
404 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
407 def : InstAlias<"clrex", (CLREX 0xf)>;
408 def : InstAlias<"isb", (ISB 0xf)>;
412 def MSRpstateImm1 : MSRpstateImm0_1;
413 def MSRpstateImm4 : MSRpstateImm0_15;
415 // The thread pointer (on Linux, at least, where this has been implemented) is
417 def : Pat<(AArch64threadpointer), (MRS 0xde82)>;
419 // The cycle counter PMC register is PMCCNTR_EL0.
420 let Predicates = [HasPerfMon] in
421 def : Pat<(readcyclecounter), (MRS 0xdce8)>;
423 // Generic system instructions
424 def SYSxt : SystemXtI<0, "sys">;
425 def SYSLxt : SystemLXtI<1, "sysl">;
427 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
428 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
429 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
431 //===----------------------------------------------------------------------===//
432 // Move immediate instructions.
433 //===----------------------------------------------------------------------===//
435 defm MOVK : InsertImmediate<0b11, "movk">;
436 defm MOVN : MoveImmediate<0b00, "movn">;
438 let PostEncoderMethod = "fixMOVZ" in
439 defm MOVZ : MoveImmediate<0b10, "movz">;
441 // First group of aliases covers an implicit "lsl #0".
442 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
443 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
444 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
445 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
446 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
447 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
449 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
450 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
451 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
452 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
453 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
455 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
456 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
457 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
458 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
460 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
461 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
462 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
463 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
465 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
466 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
468 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
469 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
471 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
472 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
474 // Final group of aliases covers true "mov $Rd, $imm" cases.
475 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
476 int width, int shift> {
477 def _asmoperand : AsmOperandClass {
478 let Name = basename # width # "_lsl" # shift # "MovAlias";
479 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
481 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
484 def _movimm : Operand<i32> {
485 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
488 def : InstAlias<"mov $Rd, $imm",
489 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
492 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
493 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
495 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
496 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
497 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
498 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
500 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
501 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
503 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
504 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
505 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
506 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
508 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
509 isAsCheapAsAMove = 1 in {
510 // FIXME: The following pseudo instructions are only needed because remat
511 // cannot handle multiple instructions. When that changes, we can select
512 // directly to the real instructions and get rid of these pseudos.
515 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
516 [(set GPR32:$dst, imm:$src)]>,
519 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
520 [(set GPR64:$dst, imm:$src)]>,
522 } // isReMaterializable, isCodeGenOnly
524 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
525 // eventual expansion code fewer bits to worry about getting right. Marshalling
526 // the types is a little tricky though:
527 def i64imm_32bit : ImmLeaf<i64, [{
528 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
531 def trunc_imm : SDNodeXForm<imm, [{
532 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i32);
535 def : Pat<(i64 i64imm_32bit:$src),
536 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
538 // Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model).
539 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
540 return CurDAG->getTargetConstant(
541 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
544 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
545 return CurDAG->getTargetConstant(
546 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
550 def : Pat<(f32 fpimm:$in),
551 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>;
552 def : Pat<(f64 fpimm:$in),
553 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>;
556 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
558 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
559 tglobaladdr:$g1, tglobaladdr:$g0),
560 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
561 tglobaladdr:$g2, 32),
562 tglobaladdr:$g1, 16),
563 tglobaladdr:$g0, 0)>;
565 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
566 tblockaddress:$g1, tblockaddress:$g0),
567 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
568 tblockaddress:$g2, 32),
569 tblockaddress:$g1, 16),
570 tblockaddress:$g0, 0)>;
572 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
573 tconstpool:$g1, tconstpool:$g0),
574 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
579 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
580 tjumptable:$g1, tjumptable:$g0),
581 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
587 //===----------------------------------------------------------------------===//
588 // Arithmetic instructions.
589 //===----------------------------------------------------------------------===//
591 // Add/subtract with carry.
592 defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>;
593 defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>;
595 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
596 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
597 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
598 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
601 defm ADD : AddSub<0, "add", "sub", add>;
602 defm SUB : AddSub<1, "sub", "add">;
604 def : InstAlias<"mov $dst, $src",
605 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
606 def : InstAlias<"mov $dst, $src",
607 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
608 def : InstAlias<"mov $dst, $src",
609 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
610 def : InstAlias<"mov $dst, $src",
611 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
613 defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn", "subs", "cmp">;
614 defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp", "adds", "cmn">;
616 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
617 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
618 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
619 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
620 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
621 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
622 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
623 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
624 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
625 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
626 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
627 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
628 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
629 let AddedComplexity = 1 in {
630 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
631 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
632 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
633 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
636 // Because of the immediate format for add/sub-imm instructions, the
637 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
638 // These patterns capture that transformation.
639 let AddedComplexity = 1 in {
640 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
641 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
642 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
643 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
644 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
645 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
646 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
647 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
650 // Because of the immediate format for add/sub-imm instructions, the
651 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
652 // These patterns capture that transformation.
653 let AddedComplexity = 1 in {
654 def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
655 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
656 def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
657 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
658 def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
659 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
660 def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
661 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
664 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
665 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
666 def : InstAlias<"neg $dst, $src$shift",
667 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
668 def : InstAlias<"neg $dst, $src$shift",
669 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
671 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
672 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
673 def : InstAlias<"negs $dst, $src$shift",
674 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
675 def : InstAlias<"negs $dst, $src$shift",
676 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
679 // Unsigned/Signed divide
680 defm UDIV : Div<0, "udiv", udiv>;
681 defm SDIV : Div<1, "sdiv", sdiv>;
682 let isCodeGenOnly = 1 in {
683 defm UDIV_Int : Div<0, "udiv", int_aarch64_udiv>;
684 defm SDIV_Int : Div<1, "sdiv", int_aarch64_sdiv>;
688 defm ASRV : Shift<0b10, "asr", sra>;
689 defm LSLV : Shift<0b00, "lsl", shl>;
690 defm LSRV : Shift<0b01, "lsr", srl>;
691 defm RORV : Shift<0b11, "ror", rotr>;
693 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
694 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
695 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
696 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
697 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
698 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
699 def : ShiftAlias<"rorv", RORVWr, GPR32>;
700 def : ShiftAlias<"rorv", RORVXr, GPR64>;
703 let AddedComplexity = 7 in {
704 defm MADD : MulAccum<0, "madd", add>;
705 defm MSUB : MulAccum<1, "msub", sub>;
707 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
708 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
709 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
710 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
712 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
713 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
714 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
715 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
716 def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)),
717 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
718 def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)),
719 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
720 } // AddedComplexity = 7
722 let AddedComplexity = 5 in {
723 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
724 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
725 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
726 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
728 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
729 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
730 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
731 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
733 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
734 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
735 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
736 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
737 } // AddedComplexity = 5
739 def : MulAccumWAlias<"mul", MADDWrrr>;
740 def : MulAccumXAlias<"mul", MADDXrrr>;
741 def : MulAccumWAlias<"mneg", MSUBWrrr>;
742 def : MulAccumXAlias<"mneg", MSUBXrrr>;
743 def : WideMulAccumAlias<"smull", SMADDLrrr>;
744 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
745 def : WideMulAccumAlias<"umull", UMADDLrrr>;
746 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
749 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
750 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
753 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
754 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
755 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">;
756 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
758 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
759 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
760 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">;
761 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
764 defm CAS : CompareAndSwap<0, 0, "">;
765 defm CASA : CompareAndSwap<1, 0, "a">;
766 defm CASL : CompareAndSwap<0, 1, "l">;
767 defm CASAL : CompareAndSwap<1, 1, "al">;
770 defm CASP : CompareAndSwapPair<0, 0, "">;
771 defm CASPA : CompareAndSwapPair<1, 0, "a">;
772 defm CASPL : CompareAndSwapPair<0, 1, "l">;
773 defm CASPAL : CompareAndSwapPair<1, 1, "al">;
776 defm SWP : Swap<0, 0, "">;
777 defm SWPA : Swap<1, 0, "a">;
778 defm SWPL : Swap<0, 1, "l">;
779 defm SWPAL : Swap<1, 1, "al">;
781 // v8.1 atomic LD<OP>(register). Performs load and then ST<OP>(register)
782 defm LDADD : LDOPregister<0b000, "add", 0, 0, "">;
783 defm LDADDA : LDOPregister<0b000, "add", 1, 0, "a">;
784 defm LDADDL : LDOPregister<0b000, "add", 0, 1, "l">;
785 defm LDADDAL : LDOPregister<0b000, "add", 1, 1, "al">;
787 defm LDCLR : LDOPregister<0b001, "clr", 0, 0, "">;
788 defm LDCLRA : LDOPregister<0b001, "clr", 1, 0, "a">;
789 defm LDCLRL : LDOPregister<0b001, "clr", 0, 1, "l">;
790 defm LDCLRAL : LDOPregister<0b001, "clr", 1, 1, "al">;
792 defm LDEOR : LDOPregister<0b010, "eor", 0, 0, "">;
793 defm LDEORA : LDOPregister<0b010, "eor", 1, 0, "a">;
794 defm LDEORL : LDOPregister<0b010, "eor", 0, 1, "l">;
795 defm LDEORAL : LDOPregister<0b010, "eor", 1, 1, "al">;
797 defm LDSET : LDOPregister<0b011, "set", 0, 0, "">;
798 defm LDSETA : LDOPregister<0b011, "set", 1, 0, "a">;
799 defm LDSETL : LDOPregister<0b011, "set", 0, 1, "l">;
800 defm LDSETAL : LDOPregister<0b011, "set", 1, 1, "al">;
802 defm LDSMAX : LDOPregister<0b100, "smax", 0, 0, "">;
803 defm LDSMAXA : LDOPregister<0b100, "smax", 1, 0, "a">;
804 defm LDSMAXL : LDOPregister<0b100, "smax", 0, 1, "l">;
805 defm LDSMAXAL : LDOPregister<0b100, "smax", 1, 1, "al">;
807 defm LDSMIN : LDOPregister<0b101, "smin", 0, 0, "">;
808 defm LDSMINA : LDOPregister<0b101, "smin", 1, 0, "a">;
809 defm LDSMINL : LDOPregister<0b101, "smin", 0, 1, "l">;
810 defm LDSMINAL : LDOPregister<0b101, "smin", 1, 1, "al">;
812 defm LDUMAX : LDOPregister<0b110, "umax", 0, 0, "">;
813 defm LDUMAXA : LDOPregister<0b110, "umax", 1, 0, "a">;
814 defm LDUMAXL : LDOPregister<0b110, "umax", 0, 1, "l">;
815 defm LDUMAXAL : LDOPregister<0b110, "umax", 1, 1, "al">;
817 defm LDUMIN : LDOPregister<0b111, "umin", 0, 0, "">;
818 defm LDUMINA : LDOPregister<0b111, "umin", 1, 0, "a">;
819 defm LDUMINL : LDOPregister<0b111, "umin", 0, 1, "l">;
820 defm LDUMINAL : LDOPregister<0b111, "umin", 1, 1, "al">;
822 // v8.1 atomic ST<OP>(register) as aliases to "LD<OP>(register) when Rt=xZR"
823 defm : STOPregister<"stadd","LDADD">; // STADDx
824 defm : STOPregister<"stclr","LDCLR">; // STCLRx
825 defm : STOPregister<"steor","LDEOR">; // STEORx
826 defm : STOPregister<"stset","LDSET">; // STSETx
827 defm : STOPregister<"stsmax","LDSMAX">;// STSMAXx
828 defm : STOPregister<"stsmin","LDSMIN">;// STSMINx
829 defm : STOPregister<"stumax","LDUMAX">;// STUMAXx
830 defm : STOPregister<"stumin","LDUMIN">;// STUMINx
832 //===----------------------------------------------------------------------===//
833 // Logical instructions.
834 //===----------------------------------------------------------------------===//
837 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
838 defm AND : LogicalImm<0b00, "and", and, "bic">;
839 defm EOR : LogicalImm<0b10, "eor", xor, "eon">;
840 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
842 // FIXME: these aliases *are* canonical sometimes (when movz can't be
843 // used). Actually, it seems to be working right now, but putting logical_immXX
844 // here is a bit dodgy on the AsmParser side too.
845 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
846 logical_imm32:$imm), 0>;
847 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
848 logical_imm64:$imm), 0>;
852 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
853 defm BICS : LogicalRegS<0b11, 1, "bics",
854 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;
855 defm AND : LogicalReg<0b00, 0, "and", and>;
856 defm BIC : LogicalReg<0b00, 1, "bic",
857 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
858 defm EON : LogicalReg<0b10, 1, "eon",
859 BinOpFrag<(not (xor node:$LHS, node:$RHS))>>;
860 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
861 defm ORN : LogicalReg<0b01, 1, "orn",
862 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
863 defm ORR : LogicalReg<0b01, 0, "orr", or>;
865 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
866 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
868 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
869 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
871 def : InstAlias<"mvn $Wd, $Wm$sh",
872 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
873 def : InstAlias<"mvn $Xd, $Xm$sh",
874 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
876 def : InstAlias<"tst $src1, $src2",
877 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
878 def : InstAlias<"tst $src1, $src2",
879 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
881 def : InstAlias<"tst $src1, $src2",
882 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
883 def : InstAlias<"tst $src1, $src2",
884 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
886 def : InstAlias<"tst $src1, $src2$sh",
887 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
888 def : InstAlias<"tst $src1, $src2$sh",
889 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
892 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
893 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
896 //===----------------------------------------------------------------------===//
897 // One operand data processing instructions.
898 //===----------------------------------------------------------------------===//
900 defm CLS : OneOperandData<0b101, "cls">;
901 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
902 defm RBIT : OneOperandData<0b000, "rbit">;
904 def : Pat<(int_aarch64_rbit GPR32:$Rn), (RBITWr $Rn)>;
905 def : Pat<(int_aarch64_rbit GPR64:$Rn), (RBITXr $Rn)>;
907 def REV16Wr : OneWRegData<0b001, "rev16",
908 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
909 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
911 def : Pat<(cttz GPR32:$Rn),
912 (CLZWr (RBITWr GPR32:$Rn))>;
913 def : Pat<(cttz GPR64:$Rn),
914 (CLZXr (RBITXr GPR64:$Rn))>;
915 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
918 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
922 // Unlike the other one operand instructions, the instructions with the "rev"
923 // mnemonic do *not* just different in the size bit, but actually use different
924 // opcode bits for the different sizes.
925 def REVWr : OneWRegData<0b010, "rev", bswap>;
926 def REVXr : OneXRegData<0b011, "rev", bswap>;
927 def REV32Xr : OneXRegData<0b010, "rev32",
928 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
930 def : InstAlias<"rev64 $Rd, $Rn", (REVXr GPR64:$Rd, GPR64:$Rn), 0>;
932 // The bswap commutes with the rotr so we want a pattern for both possible
934 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
935 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
937 //===----------------------------------------------------------------------===//
938 // Bitfield immediate extraction instruction.
939 //===----------------------------------------------------------------------===//
940 let hasSideEffects = 0 in
941 defm EXTR : ExtractImm<"extr">;
942 def : InstAlias<"ror $dst, $src, $shift",
943 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
944 def : InstAlias<"ror $dst, $src, $shift",
945 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
947 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
948 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
949 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
950 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
952 //===----------------------------------------------------------------------===//
953 // Other bitfield immediate instructions.
954 //===----------------------------------------------------------------------===//
955 let hasSideEffects = 0 in {
956 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
957 defm SBFM : BitfieldImm<0b00, "sbfm">;
958 defm UBFM : BitfieldImm<0b10, "ubfm">;
961 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
962 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
963 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
966 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
967 uint64_t enc = 31 - N->getZExtValue();
968 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
971 // min(7, 31 - shift_amt)
972 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
973 uint64_t enc = 31 - N->getZExtValue();
974 enc = enc > 7 ? 7 : enc;
975 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
978 // min(15, 31 - shift_amt)
979 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
980 uint64_t enc = 31 - N->getZExtValue();
981 enc = enc > 15 ? 15 : enc;
982 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
985 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
986 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
987 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
990 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
991 uint64_t enc = 63 - N->getZExtValue();
992 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
995 // min(7, 63 - shift_amt)
996 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
997 uint64_t enc = 63 - N->getZExtValue();
998 enc = enc > 7 ? 7 : enc;
999 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1002 // min(15, 63 - shift_amt)
1003 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
1004 uint64_t enc = 63 - N->getZExtValue();
1005 enc = enc > 15 ? 15 : enc;
1006 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1009 // min(31, 63 - shift_amt)
1010 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
1011 uint64_t enc = 63 - N->getZExtValue();
1012 enc = enc > 31 ? 31 : enc;
1013 return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
1016 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
1017 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
1018 (i64 (i32shift_b imm0_31:$imm)))>;
1019 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
1020 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
1021 (i64 (i64shift_b imm0_63:$imm)))>;
1023 let AddedComplexity = 10 in {
1024 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
1025 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
1026 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
1027 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
1030 def : InstAlias<"asr $dst, $src, $shift",
1031 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
1032 def : InstAlias<"asr $dst, $src, $shift",
1033 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
1034 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
1035 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
1036 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
1037 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
1038 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
1040 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
1041 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
1042 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
1043 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
1045 def : InstAlias<"lsr $dst, $src, $shift",
1046 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
1047 def : InstAlias<"lsr $dst, $src, $shift",
1048 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
1049 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
1050 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
1051 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
1052 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
1053 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
1055 //===----------------------------------------------------------------------===//
1056 // Conditional comparison instructions.
1057 //===----------------------------------------------------------------------===//
1058 defm CCMN : CondComparison<0, "ccmn", AArch64ccmn>;
1059 defm CCMP : CondComparison<1, "ccmp", AArch64ccmp>;
1061 //===----------------------------------------------------------------------===//
1062 // Conditional select instructions.
1063 //===----------------------------------------------------------------------===//
1064 defm CSEL : CondSelect<0, 0b00, "csel">;
1066 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
1067 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
1068 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
1069 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
1071 def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1072 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1073 def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1074 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1075 def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1076 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1077 def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1078 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1079 def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
1080 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
1081 def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
1082 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
1084 def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
1085 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
1086 def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
1087 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
1088 def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
1089 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
1090 def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
1091 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
1093 // The inverse of the condition code from the alias instruction is what is used
1094 // in the aliased instruction. The parser all ready inverts the condition code
1095 // for these aliases.
1096 def : InstAlias<"cset $dst, $cc",
1097 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
1098 def : InstAlias<"cset $dst, $cc",
1099 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
1101 def : InstAlias<"csetm $dst, $cc",
1102 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
1103 def : InstAlias<"csetm $dst, $cc",
1104 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
1106 def : InstAlias<"cinc $dst, $src, $cc",
1107 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1108 def : InstAlias<"cinc $dst, $src, $cc",
1109 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1111 def : InstAlias<"cinv $dst, $src, $cc",
1112 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1113 def : InstAlias<"cinv $dst, $src, $cc",
1114 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1116 def : InstAlias<"cneg $dst, $src, $cc",
1117 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
1118 def : InstAlias<"cneg $dst, $src, $cc",
1119 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
1121 //===----------------------------------------------------------------------===//
1122 // PC-relative instructions.
1123 //===----------------------------------------------------------------------===//
1124 let isReMaterializable = 1 in {
1125 let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in {
1126 def ADR : ADRI<0, "adr", adrlabel, []>;
1127 } // hasSideEffects = 0
1129 def ADRP : ADRI<1, "adrp", adrplabel,
1130 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;
1131 } // isReMaterializable = 1
1133 // page address of a constant pool entry, block address
1134 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
1135 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
1137 //===----------------------------------------------------------------------===//
1138 // Unconditional branch (register) instructions.
1139 //===----------------------------------------------------------------------===//
1141 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1142 def RET : BranchReg<0b0010, "ret", []>;
1143 def DRPS : SpecialReturn<0b0101, "drps">;
1144 def ERET : SpecialReturn<0b0100, "eret">;
1145 } // isReturn = 1, isTerminator = 1, isBarrier = 1
1147 // Default to the LR register.
1148 def : InstAlias<"ret", (RET LR)>;
1150 let isCall = 1, Defs = [LR], Uses = [SP] in {
1151 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
1154 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1155 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
1156 } // isBranch, isTerminator, isBarrier, isIndirectBranch
1158 // Create a separate pseudo-instruction for codegen to use so that we don't
1159 // flag lr as used in every function. It'll be restored before the RET by the
1160 // epilogue if it's legitimately used.
1161 def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]> {
1162 let isTerminator = 1;
1167 // This is a directive-like pseudo-instruction. The purpose is to insert an
1168 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
1169 // (which in the usual case is a BLR).
1170 let hasSideEffects = 1 in
1171 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
1172 let AsmString = ".tlsdesccall $sym";
1175 // FIXME: maybe the scratch register used shouldn't be fixed to X1?
1176 // FIXME: can "hasSideEffects be dropped?
1177 let isCall = 1, Defs = [LR, X0, X1], hasSideEffects = 1,
1178 isCodeGenOnly = 1 in
1180 : Pseudo<(outs), (ins i64imm:$sym),
1181 [(AArch64tlsdesc_callseq tglobaltlsaddr:$sym)]>;
1182 def : Pat<(AArch64tlsdesc_callseq texternalsym:$sym),
1183 (TLSDESC_CALLSEQ texternalsym:$sym)>;
1185 //===----------------------------------------------------------------------===//
1186 // Conditional branch (immediate) instruction.
1187 //===----------------------------------------------------------------------===//
1188 def Bcc : BranchCond;
1190 //===----------------------------------------------------------------------===//
1191 // Compare-and-branch instructions.
1192 //===----------------------------------------------------------------------===//
1193 defm CBZ : CmpBranch<0, "cbz", AArch64cbz>;
1194 defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>;
1196 //===----------------------------------------------------------------------===//
1197 // Test-bit-and-branch instructions.
1198 //===----------------------------------------------------------------------===//
1199 defm TBZ : TestBranch<0, "tbz", AArch64tbz>;
1200 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;
1202 //===----------------------------------------------------------------------===//
1203 // Unconditional branch (immediate) instructions.
1204 //===----------------------------------------------------------------------===//
1205 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1206 def B : BranchImm<0, "b", [(br bb:$addr)]>;
1207 } // isBranch, isTerminator, isBarrier
1209 let isCall = 1, Defs = [LR], Uses = [SP] in {
1210 def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>;
1212 def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>;
1214 //===----------------------------------------------------------------------===//
1215 // Exception generation instructions.
1216 //===----------------------------------------------------------------------===//
1217 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1218 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1219 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
1220 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1221 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1222 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1223 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1224 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1226 // DCPSn defaults to an immediate operand of zero if unspecified.
1227 def : InstAlias<"dcps1", (DCPS1 0)>;
1228 def : InstAlias<"dcps2", (DCPS2 0)>;
1229 def : InstAlias<"dcps3", (DCPS3 0)>;
1231 //===----------------------------------------------------------------------===//
1232 // Load instructions.
1233 //===----------------------------------------------------------------------===//
1235 // Pair (indexed, offset)
1236 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1237 defm LDPX : LoadPairOffset<0b10, 0, GPR64, simm7s8, "ldp">;
1238 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1239 defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">;
1240 defm LDPQ : LoadPairOffset<0b10, 1, FPR128, simm7s16, "ldp">;
1242 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
1244 // Pair (pre-indexed)
1245 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1246 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1247 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1248 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1249 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1251 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1253 // Pair (post-indexed)
1254 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1255 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1256 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1257 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1258 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1260 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1263 // Pair (no allocate)
1264 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1265 defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64, simm7s8, "ldnp">;
1266 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1267 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">;
1268 defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128, simm7s16, "ldnp">;
1271 // (register offset)
1275 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1276 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;
1277 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
1278 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1281 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1282 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16, "ldr", f16, load>;
1283 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32, "ldr", f32, load>;
1284 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>;
1285 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1287 // Load sign-extended half-word
1288 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1289 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;
1291 // Load sign-extended byte
1292 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1293 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1295 // Load sign-extended word
1296 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;
1299 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
1301 // For regular load, we do not have any alignment requirement.
1302 // Thus, it is safe to directly map the vector loads with interesting
1303 // addressing modes.
1304 // FIXME: We could do the same for bitconvert to floating point vectors.
1305 multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop,
1306 ValueType ScalTy, ValueType VecTy,
1307 Instruction LOADW, Instruction LOADX,
1309 def : Pat<(VecTy (scalar_to_vector (ScalTy
1310 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))),
1311 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1312 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset),
1315 def : Pat<(VecTy (scalar_to_vector (ScalTy
1316 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))),
1317 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1318 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset),
1322 let AddedComplexity = 10 in {
1323 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>;
1324 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>;
1326 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1327 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1329 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
1330 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1332 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
1333 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
1335 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
1336 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
1338 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
1340 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1343 def : Pat <(v1i64 (scalar_to_vector (i64
1344 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
1345 ro_Wextend64:$extend))))),
1346 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
1348 def : Pat <(v1i64 (scalar_to_vector (i64
1349 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
1350 ro_Xextend64:$extend))))),
1351 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
1354 // Match all load 64 bits width whose type is compatible with FPR64
1355 multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy,
1356 Instruction LOADW, Instruction LOADX> {
1358 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1359 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1361 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1362 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1365 let AddedComplexity = 10 in {
1366 let Predicates = [IsLE] in {
1367 // We must do vector loads with LD1 in big-endian.
1368 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;
1369 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
1370 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;
1371 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>;
1372 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>;
1375 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
1376 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1378 // Match all load 128 bits width whose type is compatible with FPR128
1379 let Predicates = [IsLE] in {
1380 // We must do vector loads with LD1 in big-endian.
1381 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>;
1382 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
1383 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;
1384 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
1385 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;
1386 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;
1387 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;
1389 } // AddedComplexity = 10
1392 multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop,
1393 Instruction INSTW, Instruction INSTX> {
1394 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1395 (SUBREG_TO_REG (i64 0),
1396 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
1399 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1400 (SUBREG_TO_REG (i64 0),
1401 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
1405 let AddedComplexity = 10 in {
1406 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>;
1407 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>;
1408 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>;
1410 // zextloadi1 -> zextloadi8
1411 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1413 // extload -> zextload
1414 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1415 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1416 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1418 // extloadi1 -> zextloadi8
1419 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>;
1424 multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop,
1425 Instruction INSTW, Instruction INSTX> {
1426 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1427 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1429 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1430 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1434 let AddedComplexity = 10 in {
1435 // extload -> zextload
1436 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1437 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1438 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1440 // zextloadi1 -> zextloadi8
1441 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1445 // (unsigned immediate)
1447 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr",
1449 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1450 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32, uimm12s4, "ldr",
1452 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1453 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1455 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>;
1456 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16, uimm12s2, "ldr",
1457 [(set (f16 FPR16:$Rt),
1458 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>;
1459 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32, uimm12s4, "ldr",
1460 [(set (f32 FPR32:$Rt),
1461 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1462 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr",
1463 [(set (f64 FPR64:$Rt),
1464 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1465 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1466 [(set (f128 FPR128:$Rt),
1467 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>;
1469 // For regular load, we do not have any alignment requirement.
1470 // Thus, it is safe to directly map the vector loads with interesting
1471 // addressing modes.
1472 // FIXME: We could do the same for bitconvert to floating point vectors.
1473 def : Pat <(v8i8 (scalar_to_vector (i32
1474 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1475 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1476 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1477 def : Pat <(v16i8 (scalar_to_vector (i32
1478 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1479 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1480 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1481 def : Pat <(v4i16 (scalar_to_vector (i32
1482 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1483 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1484 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1485 def : Pat <(v8i16 (scalar_to_vector (i32
1486 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1487 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1488 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1489 def : Pat <(v2i32 (scalar_to_vector (i32
1490 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1491 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1492 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1493 def : Pat <(v4i32 (scalar_to_vector (i32
1494 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1495 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1496 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1497 def : Pat <(v1i64 (scalar_to_vector (i64
1498 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1499 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1500 def : Pat <(v2i64 (scalar_to_vector (i64
1501 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1502 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1503 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
1505 // Match all load 64 bits width whose type is compatible with FPR64
1506 let Predicates = [IsLE] in {
1507 // We must use LD1 to perform vector loads in big-endian.
1508 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1509 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1510 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1511 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1512 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1513 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1514 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1515 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1516 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1517 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1519 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1520 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1521 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1522 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1524 // Match all load 128 bits width whose type is compatible with FPR128
1525 let Predicates = [IsLE] in {
1526 // We must use LD1 to perform vector loads in big-endian.
1527 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1528 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1529 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1530 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1531 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1532 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1533 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1534 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1535 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1536 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1537 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1538 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1539 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1540 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1542 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1543 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1545 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
1547 (zextloadi16 (am_indexed16 GPR64sp:$Rn,
1548 uimm12s2:$offset)))]>;
1549 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1551 (zextloadi8 (am_indexed8 GPR64sp:$Rn,
1552 uimm12s1:$offset)))]>;
1554 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1555 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1556 def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1557 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1559 // zextloadi1 -> zextloadi8
1560 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1561 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1562 def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1563 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1565 // extload -> zextload
1566 def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1567 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
1568 def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1569 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1570 def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1571 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1572 def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1573 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1574 def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1575 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1576 def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1577 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1578 def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1579 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1581 // load sign-extended half-word
1582 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
1584 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1585 uimm12s2:$offset)))]>;
1586 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",
1588 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1589 uimm12s2:$offset)))]>;
1591 // load sign-extended byte
1592 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1594 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1595 uimm12s1:$offset)))]>;
1596 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1598 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1599 uimm12s1:$offset)))]>;
1601 // load sign-extended word
1602 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
1604 (sextloadi32 (am_indexed32 GPR64sp:$Rn,
1605 uimm12s4:$offset)))]>;
1607 // load zero-extended word
1608 def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1609 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1612 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1613 [(AArch64Prefetch imm:$Rt,
1614 (am_indexed64 GPR64sp:$Rn,
1615 uimm12s8:$offset))]>;
1617 def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>;
1621 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1622 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1623 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1624 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1625 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1627 // load sign-extended word
1628 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1631 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1632 // [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1635 // (unscaled immediate)
1636 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur",
1638 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1639 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32, "ldur",
1641 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1642 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1644 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1645 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16, "ldur",
1647 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1648 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32, "ldur",
1649 [(set (f32 FPR32:$Rt),
1650 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1651 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur",
1652 [(set (f64 FPR64:$Rt),
1653 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1654 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1655 [(set (f128 FPR128:$Rt),
1656 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;
1659 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
1661 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1663 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1665 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1667 // Match all load 64 bits width whose type is compatible with FPR64
1668 let Predicates = [IsLE] in {
1669 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1670 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1671 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1672 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1673 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1674 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1675 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1676 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1677 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1678 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1680 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1681 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1682 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1683 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1685 // Match all load 128 bits width whose type is compatible with FPR128
1686 let Predicates = [IsLE] in {
1687 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1688 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1689 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1690 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1691 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1692 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1693 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1694 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1695 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1696 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1697 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1698 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1699 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1700 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1704 def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1705 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1706 def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1707 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1708 def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1709 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1710 def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1711 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1712 def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1713 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1714 def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1715 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1716 def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1717 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1719 def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1720 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1721 def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1722 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1723 def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1724 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1725 def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1726 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1727 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1728 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1729 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1730 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1731 def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1732 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1736 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1738 // Define new assembler match classes as we want to only match these when
1739 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1740 // associate a DiagnosticType either, as we want the diagnostic for the
1741 // canonical form (the scaled operand) to take precedence.
1742 class SImm9OffsetOperand<int Width> : AsmOperandClass {
1743 let Name = "SImm9OffsetFB" # Width;
1744 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">";
1745 let RenderMethod = "addImmOperands";
1748 def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>;
1749 def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>;
1750 def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>;
1751 def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>;
1752 def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>;
1754 def simm9_offset_fb8 : Operand<i64> {
1755 let ParserMatchClass = SImm9OffsetFB8Operand;
1757 def simm9_offset_fb16 : Operand<i64> {
1758 let ParserMatchClass = SImm9OffsetFB16Operand;
1760 def simm9_offset_fb32 : Operand<i64> {
1761 let ParserMatchClass = SImm9OffsetFB32Operand;
1763 def simm9_offset_fb64 : Operand<i64> {
1764 let ParserMatchClass = SImm9OffsetFB64Operand;
1766 def simm9_offset_fb128 : Operand<i64> {
1767 let ParserMatchClass = SImm9OffsetFB128Operand;
1770 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1771 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1772 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1773 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1774 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1775 (LDURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1776 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1777 (LDURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1778 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1779 (LDURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1780 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1781 (LDURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1782 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1783 (LDURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
1786 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1787 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1788 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1789 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1791 // load sign-extended half-word
1793 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
1795 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1797 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",
1799 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1801 // load sign-extended byte
1803 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1805 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1807 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1809 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1811 // load sign-extended word
1813 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",
1815 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1817 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1818 def : InstAlias<"ldrb $Rt, [$Rn, $offset]",
1819 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1820 def : InstAlias<"ldrh $Rt, [$Rn, $offset]",
1821 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1822 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1823 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1824 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1825 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1826 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1827 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1828 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1829 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1830 def : InstAlias<"ldrsw $Rt, [$Rn, $offset]",
1831 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1834 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1835 [(AArch64Prefetch imm:$Rt,
1836 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1839 // (unscaled immediate, unprivileged)
1840 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1841 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1843 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1844 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1846 // load sign-extended half-word
1847 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1848 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1850 // load sign-extended byte
1851 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1852 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1854 // load sign-extended word
1855 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1858 // (immediate pre-indexed)
1859 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1860 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1861 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1862 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1863 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1864 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1865 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1867 // load sign-extended half-word
1868 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1869 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1871 // load sign-extended byte
1872 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1873 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1875 // load zero-extended byte
1876 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1877 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1879 // load sign-extended word
1880 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1883 // (immediate post-indexed)
1884 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1885 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1886 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1887 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1888 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1889 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1890 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1892 // load sign-extended half-word
1893 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1894 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1896 // load sign-extended byte
1897 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1898 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1900 // load zero-extended byte
1901 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1902 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1904 // load sign-extended word
1905 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1907 //===----------------------------------------------------------------------===//
1908 // Store instructions.
1909 //===----------------------------------------------------------------------===//
1911 // Pair (indexed, offset)
1912 // FIXME: Use dedicated range-checked addressing mode operand here.
1913 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1914 defm STPX : StorePairOffset<0b10, 0, GPR64, simm7s8, "stp">;
1915 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1916 defm STPD : StorePairOffset<0b01, 1, FPR64, simm7s8, "stp">;
1917 defm STPQ : StorePairOffset<0b10, 1, FPR128, simm7s16, "stp">;
1919 // Pair (pre-indexed)
1920 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1921 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, simm7s8, "stp">;
1922 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1923 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, simm7s8, "stp">;
1924 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, simm7s16, "stp">;
1926 // Pair (pre-indexed)
1927 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1928 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1929 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1930 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1931 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1933 // Pair (no allocate)
1934 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
1935 defm STNPX : StorePairNoAlloc<0b10, 0, GPR64, simm7s8, "stnp">;
1936 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
1937 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64, simm7s8, "stnp">;
1938 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128, simm7s16, "stnp">;
1941 // (Register offset)
1944 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
1945 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
1946 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
1947 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
1951 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
1952 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
1953 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
1954 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
1955 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
1957 multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
1958 Instruction STRW, Instruction STRX> {
1960 def : Pat<(storeop GPR64:$Rt,
1961 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1962 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1963 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1965 def : Pat<(storeop GPR64:$Rt,
1966 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1967 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1968 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1971 let AddedComplexity = 10 in {
1973 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>;
1974 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>;
1975 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>;
1978 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
1979 Instruction STRW, Instruction STRX> {
1980 def : Pat<(store (VecTy FPR:$Rt),
1981 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1982 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1984 def : Pat<(store (VecTy FPR:$Rt),
1985 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1986 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1989 let AddedComplexity = 10 in {
1990 // Match all store 64 bits width whose type is compatible with FPR64
1991 let Predicates = [IsLE] in {
1992 // We must use ST1 to store vectors in big-endian.
1993 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
1994 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
1995 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
1996 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;
1997 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>;
2000 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
2001 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
2003 // Match all store 128 bits width whose type is compatible with FPR128
2004 let Predicates = [IsLE] in {
2005 // We must use ST1 to store vectors in big-endian.
2006 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;
2007 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
2008 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;
2009 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
2010 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>;
2011 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>;
2012 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;
2014 } // AddedComplexity = 10
2016 // Match stores from lane 0 to the appropriate subreg's store.
2017 multiclass VecROStoreLane0Pat<ROAddrMode ro, SDPatternOperator storeop,
2018 ValueType VecTy, ValueType STy,
2019 SubRegIndex SubRegIdx,
2020 Instruction STRW, Instruction STRX> {
2022 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
2023 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
2024 (STRW (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
2025 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
2027 def : Pat<(storeop (STy (vector_extract (VecTy VecListOne128:$Vt), 0)),
2028 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
2029 (STRX (EXTRACT_SUBREG VecListOne128:$Vt, SubRegIdx),
2030 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
2033 let AddedComplexity = 19 in {
2034 defm : VecROStoreLane0Pat<ro16, truncstorei16, v8i16, i32, hsub, STRHroW, STRHroX>;
2035 defm : VecROStoreLane0Pat<ro16, store , v8i16, i16, hsub, STRHroW, STRHroX>;
2036 defm : VecROStoreLane0Pat<ro32, truncstorei32, v4i32, i32, ssub, STRSroW, STRSroX>;
2037 defm : VecROStoreLane0Pat<ro32, store , v4i32, i32, ssub, STRSroW, STRSroX>;
2038 defm : VecROStoreLane0Pat<ro32, store , v4f32, f32, ssub, STRSroW, STRSroX>;
2039 defm : VecROStoreLane0Pat<ro64, store , v2i64, i64, dsub, STRDroW, STRDroX>;
2040 defm : VecROStoreLane0Pat<ro64, store , v2f64, f64, dsub, STRDroW, STRDroX>;
2044 // (unsigned immediate)
2045 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
2047 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
2048 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
2050 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
2051 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
2053 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>;
2054 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
2055 [(store (f16 FPR16:$Rt),
2056 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>;
2057 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
2058 [(store (f32 FPR32:$Rt),
2059 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
2060 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
2061 [(store (f64 FPR64:$Rt),
2062 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
2063 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
2065 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
2066 [(truncstorei16 GPR32:$Rt,
2067 (am_indexed16 GPR64sp:$Rn,
2068 uimm12s2:$offset))]>;
2069 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
2070 [(truncstorei8 GPR32:$Rt,
2071 (am_indexed8 GPR64sp:$Rn,
2072 uimm12s1:$offset))]>;
2074 // Match all store 64 bits width whose type is compatible with FPR64
2075 let AddedComplexity = 10 in {
2076 let Predicates = [IsLE] in {
2077 // We must use ST1 to store vectors in big-endian.
2078 def : Pat<(store (v2f32 FPR64:$Rt),
2079 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2080 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2081 def : Pat<(store (v8i8 FPR64:$Rt),
2082 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2083 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2084 def : Pat<(store (v4i16 FPR64:$Rt),
2085 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2086 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2087 def : Pat<(store (v2i32 FPR64:$Rt),
2088 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2089 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2090 def : Pat<(store (v4f16 FPR64:$Rt),
2091 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2092 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2094 def : Pat<(store (v1f64 FPR64:$Rt),
2095 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2096 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2097 def : Pat<(store (v1i64 FPR64:$Rt),
2098 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
2099 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
2101 // Match all store 128 bits width whose type is compatible with FPR128
2102 let Predicates = [IsLE] in {
2103 // We must use ST1 to store vectors in big-endian.
2104 def : Pat<(store (v4f32 FPR128:$Rt),
2105 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2106 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2107 def : Pat<(store (v2f64 FPR128:$Rt),
2108 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2109 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2110 def : Pat<(store (v16i8 FPR128:$Rt),
2111 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2112 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2113 def : Pat<(store (v8i16 FPR128:$Rt),
2114 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2115 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2116 def : Pat<(store (v4i32 FPR128:$Rt),
2117 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2118 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2119 def : Pat<(store (v2i64 FPR128:$Rt),
2120 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2121 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2122 def : Pat<(store (v8f16 FPR128:$Rt),
2123 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2124 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2126 def : Pat<(store (f128 FPR128:$Rt),
2127 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
2128 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
2131 def : Pat<(truncstorei32 GPR64:$Rt,
2132 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
2133 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;
2134 def : Pat<(truncstorei16 GPR64:$Rt,
2135 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
2136 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;
2137 def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
2138 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>;
2140 } // AddedComplexity = 10
2143 // (unscaled immediate)
2144 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
2146 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2147 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
2149 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2150 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
2152 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2153 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
2154 [(store (f16 FPR16:$Rt),
2155 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2156 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
2157 [(store (f32 FPR32:$Rt),
2158 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2159 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
2160 [(store (f64 FPR64:$Rt),
2161 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2162 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
2163 [(store (f128 FPR128:$Rt),
2164 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;
2165 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
2166 [(truncstorei16 GPR32:$Rt,
2167 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2168 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
2169 [(truncstorei8 GPR32:$Rt,
2170 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2172 // Match all store 64 bits width whose type is compatible with FPR64
2173 let Predicates = [IsLE] in {
2174 // We must use ST1 to store vectors in big-endian.
2175 def : Pat<(store (v2f32 FPR64:$Rt),
2176 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2177 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2178 def : Pat<(store (v8i8 FPR64:$Rt),
2179 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2180 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2181 def : Pat<(store (v4i16 FPR64:$Rt),
2182 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2183 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2184 def : Pat<(store (v2i32 FPR64:$Rt),
2185 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2186 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2187 def : Pat<(store (v4f16 FPR64:$Rt),
2188 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2189 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2191 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2192 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2193 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2194 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2196 // Match all store 128 bits width whose type is compatible with FPR128
2197 let Predicates = [IsLE] in {
2198 // We must use ST1 to store vectors in big-endian.
2199 def : Pat<(store (v4f32 FPR128:$Rt),
2200 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2201 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2202 def : Pat<(store (v2f64 FPR128:$Rt),
2203 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2204 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2205 def : Pat<(store (v16i8 FPR128:$Rt),
2206 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2207 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2208 def : Pat<(store (v8i16 FPR128:$Rt),
2209 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2210 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2211 def : Pat<(store (v4i32 FPR128:$Rt),
2212 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2213 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2214 def : Pat<(store (v2i64 FPR128:$Rt),
2215 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2216 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2217 def : Pat<(store (v2f64 FPR128:$Rt),
2218 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2219 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2220 def : Pat<(store (v8f16 FPR128:$Rt),
2221 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2222 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2225 // unscaled i64 truncating stores
2226 def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
2227 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2228 def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2229 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2230 def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
2231 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2234 // STR mnemonics fall back to STUR for negative or unaligned offsets.
2235 def : InstAlias<"str $Rt, [$Rn, $offset]",
2236 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2237 def : InstAlias<"str $Rt, [$Rn, $offset]",
2238 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2239 def : InstAlias<"str $Rt, [$Rn, $offset]",
2240 (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2241 def : InstAlias<"str $Rt, [$Rn, $offset]",
2242 (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2243 def : InstAlias<"str $Rt, [$Rn, $offset]",
2244 (STURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2245 def : InstAlias<"str $Rt, [$Rn, $offset]",
2246 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2247 def : InstAlias<"str $Rt, [$Rn, $offset]",
2248 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
2250 def : InstAlias<"strb $Rt, [$Rn, $offset]",
2251 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2252 def : InstAlias<"strh $Rt, [$Rn, $offset]",
2253 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2256 // (unscaled immediate, unprivileged)
2257 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2258 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2260 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2261 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2264 // (immediate pre-indexed)
2265 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2266 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2267 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2268 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2269 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2270 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2271 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2273 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2274 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2277 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2278 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2280 def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2281 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2283 def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2284 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2287 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2288 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2289 def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2290 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2291 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2292 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2293 def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2294 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2295 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2296 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2297 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2298 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2299 def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2300 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2302 def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2303 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2304 def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2305 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2306 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2307 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2308 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2309 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2310 def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2311 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2312 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2313 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2314 def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2315 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2318 // (immediate post-indexed)
2319 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2320 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2321 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2322 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2323 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2324 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2325 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2327 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2328 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2331 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2332 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2334 def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2335 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2337 def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2338 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2341 def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2342 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2343 def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2344 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2345 def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2346 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2347 def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2348 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2349 def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2350 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2351 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2352 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2353 def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2354 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2356 def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2357 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2358 def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2359 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2360 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2361 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2362 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2363 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2364 def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2365 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2366 def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2367 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2368 def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2369 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2371 //===----------------------------------------------------------------------===//
2372 // Load/store exclusive instructions.
2373 //===----------------------------------------------------------------------===//
2375 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
2376 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2377 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2378 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2380 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2381 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2382 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2383 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2385 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
2386 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2387 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2388 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2390 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
2391 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2392 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2393 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2395 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
2396 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2397 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2398 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2400 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
2401 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2402 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2403 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2405 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
2406 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2408 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
2409 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2411 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
2412 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2414 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
2415 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2417 let Predicates = [HasV8_1a] in {
2418 // v8.1a "Limited Order Region" extension load-acquire instructions
2419 def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">;
2420 def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">;
2421 def LDLARB : LoadAcquire <0b00, 1, 1, 0, 0, GPR32, "ldlarb">;
2422 def LDLARH : LoadAcquire <0b01, 1, 1, 0, 0, GPR32, "ldlarh">;
2424 // v8.1a "Limited Order Region" extension store-release instructions
2425 def STLLRW : StoreRelease <0b10, 1, 0, 0, 0, GPR32, "stllr">;
2426 def STLLRX : StoreRelease <0b11, 1, 0, 0, 0, GPR64, "stllr">;
2427 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;
2428 def STLLRH : StoreRelease <0b01, 1, 0, 0, 0, GPR32, "stllrh">;
2431 //===----------------------------------------------------------------------===//
2432 // Scaled floating point to integer conversion instructions.
2433 //===----------------------------------------------------------------------===//
2435 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2436 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2437 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
2438 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;
2439 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2440 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2441 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
2442 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
2443 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2444 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2445 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2446 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2447 let isCodeGenOnly = 1 in {
2448 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2449 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2450 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2451 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2454 multiclass FPToIntegerPats<SDNode to_int, SDNode round, string INST> {
2455 def : Pat<(i32 (to_int (round f32:$Rn))),
2456 (!cast<Instruction>(INST # UWSr) f32:$Rn)>;
2457 def : Pat<(i64 (to_int (round f32:$Rn))),
2458 (!cast<Instruction>(INST # UXSr) f32:$Rn)>;
2459 def : Pat<(i32 (to_int (round f64:$Rn))),
2460 (!cast<Instruction>(INST # UWDr) f64:$Rn)>;
2461 def : Pat<(i64 (to_int (round f64:$Rn))),
2462 (!cast<Instruction>(INST # UXDr) f64:$Rn)>;
2465 defm : FPToIntegerPats<fp_to_sint, fceil, "FCVTPS">;
2466 defm : FPToIntegerPats<fp_to_uint, fceil, "FCVTPU">;
2467 defm : FPToIntegerPats<fp_to_sint, ffloor, "FCVTMS">;
2468 defm : FPToIntegerPats<fp_to_uint, ffloor, "FCVTMU">;
2469 defm : FPToIntegerPats<fp_to_sint, ftrunc, "FCVTZS">;
2470 defm : FPToIntegerPats<fp_to_uint, ftrunc, "FCVTZU">;
2471 defm : FPToIntegerPats<fp_to_sint, frnd, "FCVTAS">;
2472 defm : FPToIntegerPats<fp_to_uint, frnd, "FCVTAU">;
2474 //===----------------------------------------------------------------------===//
2475 // Scaled integer to floating point conversion instructions.
2476 //===----------------------------------------------------------------------===//
2478 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2479 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2481 //===----------------------------------------------------------------------===//
2482 // Unscaled integer to floating point conversion instruction.
2483 //===----------------------------------------------------------------------===//
2485 defm FMOV : UnscaledConversion<"fmov">;
2487 // Add pseudo ops for FMOV 0 so we can mark them as isReMaterializable
2488 let isReMaterializable = 1, isCodeGenOnly = 1 in {
2489 def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>,
2490 PseudoInstExpansion<(FMOVWSr FPR32:$Rd, WZR)>,
2492 def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>,
2493 PseudoInstExpansion<(FMOVXDr FPR64:$Rd, XZR)>,
2497 //===----------------------------------------------------------------------===//
2498 // Floating point conversion instruction.
2499 //===----------------------------------------------------------------------===//
2501 defm FCVT : FPConversion<"fcvt">;
2503 //===----------------------------------------------------------------------===//
2504 // Floating point single operand instructions.
2505 //===----------------------------------------------------------------------===//
2507 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2508 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2509 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2510 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2511 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2512 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2513 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>;
2514 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2516 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
2517 (FRINTNDr FPR64:$Rn)>;
2519 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2520 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2522 let SchedRW = [WriteFDiv] in {
2523 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2526 //===----------------------------------------------------------------------===//
2527 // Floating point two operand instructions.
2528 //===----------------------------------------------------------------------===//
2530 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2531 let SchedRW = [WriteFDiv] in {
2532 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2534 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", fmaxnum>;
2535 defm FMAX : TwoOperandFPData<0b0100, "fmax", fmaxnan>;
2536 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", fminnum>;
2537 defm FMIN : TwoOperandFPData<0b0101, "fmin", fminnan>;
2538 let SchedRW = [WriteFMul] in {
2539 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2540 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2542 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2544 def : Pat<(v1f64 (fmaxnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2545 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2546 def : Pat<(v1f64 (fminnan (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2547 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2548 def : Pat<(v1f64 (fmaxnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2549 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2550 def : Pat<(v1f64 (fminnum (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2551 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2553 //===----------------------------------------------------------------------===//
2554 // Floating point three operand instructions.
2555 //===----------------------------------------------------------------------===//
2557 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2558 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2559 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2560 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2561 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2562 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2563 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2565 // The following def pats catch the case where the LHS of an FMA is negated.
2566 // The TriOpFrag above catches the case where the middle operand is negated.
2568 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2569 // the NEON variant.
2570 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2571 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2573 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2574 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2576 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2578 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2579 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2581 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2582 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2584 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2585 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2587 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2588 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2590 //===----------------------------------------------------------------------===//
2591 // Floating point comparison instructions.
2592 //===----------------------------------------------------------------------===//
2594 defm FCMPE : FPComparison<1, "fcmpe">;
2595 defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>;
2597 //===----------------------------------------------------------------------===//
2598 // Floating point conditional comparison instructions.
2599 //===----------------------------------------------------------------------===//
2601 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2602 defm FCCMP : FPCondComparison<0, "fccmp", AArch64fccmp>;
2604 //===----------------------------------------------------------------------===//
2605 // Floating point conditional select instruction.
2606 //===----------------------------------------------------------------------===//
2608 defm FCSEL : FPCondSelect<"fcsel">;
2610 // CSEL instructions providing f128 types need to be handled by a
2611 // pseudo-instruction since the eventual code will need to introduce basic
2612 // blocks and control flow.
2613 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2614 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2615 [(set (f128 FPR128:$Rd),
2616 (AArch64csel FPR128:$Rn, FPR128:$Rm,
2617 (i32 imm:$cond), NZCV))]> {
2619 let usesCustomInserter = 1;
2623 //===----------------------------------------------------------------------===//
2624 // Floating point immediate move.
2625 //===----------------------------------------------------------------------===//
2627 let isReMaterializable = 1 in {
2628 defm FMOV : FPMoveImmediate<"fmov">;
2631 //===----------------------------------------------------------------------===//
2632 // Advanced SIMD two vector instructions.
2633 //===----------------------------------------------------------------------===//
2635 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
2637 // Match UABDL in log2-shuffle patterns.
2638 def : Pat<(xor (v8i16 (AArch64vashr v8i16:$src, (i32 15))),
2639 (v8i16 (add (sub (zext (v8i8 V64:$opA)),
2640 (zext (v8i8 V64:$opB))),
2641 (AArch64vashr v8i16:$src, (i32 15))))),
2642 (UABDLv8i8_v8i16 V64:$opA, V64:$opB)>;
2643 def : Pat<(xor (v8i16 (AArch64vashr v8i16:$src, (i32 15))),
2644 (v8i16 (add (sub (zext (extract_high_v16i8 V128:$opA)),
2645 (zext (extract_high_v16i8 V128:$opB))),
2646 (AArch64vashr v8i16:$src, (i32 15))))),
2647 (UABDLv16i8_v8i16 V128:$opA, V128:$opB)>;
2648 def : Pat<(xor (v4i32 (AArch64vashr v4i32:$src, (i32 31))),
2649 (v4i32 (add (sub (zext (v4i16 V64:$opA)),
2650 (zext (v4i16 V64:$opB))),
2651 (AArch64vashr v4i32:$src, (i32 31))))),
2652 (UABDLv4i16_v4i32 V64:$opA, V64:$opB)>;
2653 def : Pat<(xor (v4i32 (AArch64vashr v4i32:$src, (i32 31))),
2654 (v4i32 (add (sub (zext (extract_high_v8i16 V128:$opA)),
2655 (zext (extract_high_v8i16 V128:$opB))),
2656 (AArch64vashr v4i32:$src, (i32 31))))),
2657 (UABDLv8i16_v4i32 V128:$opA, V128:$opB)>;
2658 def : Pat<(xor (v2i64 (AArch64vashr v2i64:$src, (i32 63))),
2659 (v2i64 (add (sub (zext (v2i32 V64:$opA)),
2660 (zext (v2i32 V64:$opB))),
2661 (AArch64vashr v2i64:$src, (i32 63))))),
2662 (UABDLv2i32_v2i64 V64:$opA, V64:$opB)>;
2663 def : Pat<(xor (v2i64 (AArch64vashr v2i64:$src, (i32 63))),
2664 (v2i64 (add (sub (zext (extract_high_v4i32 V128:$opA)),
2665 (zext (extract_high_v4i32 V128:$opB))),
2666 (AArch64vashr v2i64:$src, (i32 63))))),
2667 (UABDLv4i32_v2i64 V128:$opA, V128:$opB)>;
2669 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_aarch64_neon_abs>;
2670 def : Pat<(xor (v8i8 (AArch64vashr V64:$src, (i32 7))),
2671 (v8i8 (add V64:$src, (AArch64vashr V64:$src, (i32 7))))),
2672 (ABSv8i8 V64:$src)>;
2673 def : Pat<(xor (v4i16 (AArch64vashr V64:$src, (i32 15))),
2674 (v4i16 (add V64:$src, (AArch64vashr V64:$src, (i32 15))))),
2675 (ABSv4i16 V64:$src)>;
2676 def : Pat<(xor (v2i32 (AArch64vashr V64:$src, (i32 31))),
2677 (v2i32 (add V64:$src, (AArch64vashr V64:$src, (i32 31))))),
2678 (ABSv2i32 V64:$src)>;
2679 def : Pat<(xor (v16i8 (AArch64vashr V128:$src, (i32 7))),
2680 (v16i8 (add V128:$src, (AArch64vashr V128:$src, (i32 7))))),
2681 (ABSv16i8 V128:$src)>;
2682 def : Pat<(xor (v8i16 (AArch64vashr V128:$src, (i32 15))),
2683 (v8i16 (add V128:$src, (AArch64vashr V128:$src, (i32 15))))),
2684 (ABSv8i16 V128:$src)>;
2685 def : Pat<(xor (v4i32 (AArch64vashr V128:$src, (i32 31))),
2686 (v4i32 (add V128:$src, (AArch64vashr V128:$src, (i32 31))))),
2687 (ABSv4i32 V128:$src)>;
2688 def : Pat<(xor (v2i64 (AArch64vashr V128:$src, (i32 63))),
2689 (v2i64 (add V128:$src, (AArch64vashr V128:$src, (i32 63))))),
2690 (ABSv2i64 V128:$src)>;
2692 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
2693 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2694 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;
2695 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;
2696 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
2697 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;
2698 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;
2699 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2700 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2702 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2703 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2704 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2705 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2706 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2707 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>;
2708 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;
2709 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2710 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2711 (FCVTLv4i16 V64:$Rn)>;
2712 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2714 (FCVTLv8i16 V128:$Rn)>;
2715 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2716 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2718 (FCVTLv4i32 V128:$Rn)>;
2720 def : Pat<(v4f32 (fextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>;
2721 def : Pat<(v4f32 (fextend (v4f16 (extract_subvector (v8f16 V128:$Rn),
2723 (FCVTLv8i16 V128:$Rn)>;
2725 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;
2726 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;
2727 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>;
2728 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>;
2729 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2730 def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2731 (FCVTNv4i16 V128:$Rn)>;
2732 def : Pat<(concat_vectors V64:$Rd,
2733 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2734 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2735 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2736 def : Pat<(v4f16 (fround (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>;
2737 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2738 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2739 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
2740 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
2741 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2742 int_aarch64_neon_fcvtxn>;
2743 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2744 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2745 let isCodeGenOnly = 1 in {
2746 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2747 int_aarch64_neon_fcvtzs>;
2748 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2749 int_aarch64_neon_fcvtzu>;
2751 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2752 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;
2753 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2754 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2755 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2756 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>;
2757 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2758 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2759 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2760 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>;
2761 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2762 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2763 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2764 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2765 // Aliases for MVN -> NOT.
2766 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2767 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2768 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2769 (NOTv16i8 V128:$Vd, V128:$Vn)>;
2771 def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2772 def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2773 def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2774 def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2775 def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2776 def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2777 def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2779 def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2780 def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2781 def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2782 def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2783 def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2784 def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2785 def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2786 def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2788 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2789 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2790 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2791 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2792 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2794 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>;
2795 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
2796 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>;
2797 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
2798 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2799 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >;
2800 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>;
2801 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2802 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2803 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2804 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2805 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>;
2806 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>;
2807 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>;
2808 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2809 BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >;
2810 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2811 int_aarch64_neon_uaddlp>;
2812 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2813 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>;
2814 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>;
2815 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;
2816 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>;
2817 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2819 def : Pat<(v4f16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>;
2820 def : Pat<(v4f16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>;
2821 def : Pat<(v8f16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>;
2822 def : Pat<(v8f16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>;
2823 def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2824 def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2826 // Patterns for vector long shift (by element width). These need to match all
2827 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2829 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2830 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2831 (SHLLv8i8 V64:$Rn)>;
2832 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2833 (SHLLv16i8 V128:$Rn)>;
2834 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2835 (SHLLv4i16 V64:$Rn)>;
2836 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2837 (SHLLv8i16 V128:$Rn)>;
2838 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2839 (SHLLv2i32 V64:$Rn)>;
2840 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2841 (SHLLv4i32 V128:$Rn)>;
2844 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2845 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2846 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2848 //===----------------------------------------------------------------------===//
2849 // Advanced SIMD three vector instructions.
2850 //===----------------------------------------------------------------------===//
2852 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2853 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
2854 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
2855 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
2856 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
2857 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
2858 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
2859 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
2860 defm FABD : SIMDThreeSameVectorFP<1,1,0b010,"fabd", int_aarch64_neon_fabd>;
2861 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b101,"facge",int_aarch64_neon_facge>;
2862 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b101,"facgt",int_aarch64_neon_facgt>;
2863 defm FADDP : SIMDThreeSameVectorFP<1,0,0b010,"faddp",int_aarch64_neon_addp>;
2864 defm FADD : SIMDThreeSameVectorFP<0,0,0b010,"fadd", fadd>;
2865 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b100, "fcmeq", AArch64fcmeq>;
2866 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b100, "fcmge", AArch64fcmge>;
2867 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b100, "fcmgt", AArch64fcmgt>;
2868 defm FDIV : SIMDThreeSameVectorFP<1,0,0b111,"fdiv", fdiv>;
2869 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
2870 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b000,"fmaxnm", fmaxnum>;
2871 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b110,"fmaxp", int_aarch64_neon_fmaxp>;
2872 defm FMAX : SIMDThreeSameVectorFP<0,0,0b110,"fmax", fmaxnan>;
2873 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b000,"fminnmp", int_aarch64_neon_fminnmp>;
2874 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b000,"fminnm", fminnum>;
2875 defm FMINP : SIMDThreeSameVectorFP<1,1,0b110,"fminp", int_aarch64_neon_fminp>;
2876 defm FMIN : SIMDThreeSameVectorFP<0,1,0b110,"fmin", fminnan>;
2878 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2879 // instruction expects the addend first, while the fma intrinsic puts it last.
2880 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b001, "fmla",
2881 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2882 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b001, "fmls",
2883 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2885 // The following def pats catch the case where the LHS of an FMA is negated.
2886 // The TriOpFrag above catches the case where the middle operand is negated.
2887 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2888 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2890 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2891 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2893 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2894 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2896 defm FMULX : SIMDThreeSameVectorFP<0,0,0b011,"fmulx", int_aarch64_neon_fmulx>;
2897 defm FMUL : SIMDThreeSameVectorFP<1,0,0b011,"fmul", fmul>;
2898 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b111,"frecps", int_aarch64_neon_frecps>;
2899 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b111,"frsqrts", int_aarch64_neon_frsqrts>;
2900 defm FSUB : SIMDThreeSameVectorFP<0,1,0b010,"fsub", fsub>;
2901 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2902 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2903 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2904 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2905 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2906 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
2907 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2908 TriOpFrag<(add node:$LHS, (sabsdiff node:$MHS, node:$RHS))> >;
2909 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", sabsdiff>;
2910 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>;
2911 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
2912 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
2913 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", smax>;
2914 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>;
2915 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", smin>;
2916 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>;
2917 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>;
2918 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>;
2919 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>;
2920 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>;
2921 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>;
2922 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>;
2923 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
2924 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
2925 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2926 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2927 TriOpFrag<(add node:$LHS, (uabsdiff node:$MHS, node:$RHS))> >;
2928 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", uabsdiff>;
2929 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>;
2930 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
2931 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
2932 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", umax>;
2933 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>;
2934 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", umin>;
2935 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>;
2936 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>;
2937 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>;
2938 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>;
2939 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>;
2940 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;
2941 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
2942 defm SQRDMLAH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10000,"sqrdmlah",
2943 int_aarch64_neon_sqadd>;
2944 defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh",
2945 int_aarch64_neon_sqsub>;
2947 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2948 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2949 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2950 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2951 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>;
2952 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2953 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2954 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2955 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2956 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2957 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2960 def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2961 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2962 def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2963 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2964 def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2965 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2966 def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2967 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2969 def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2970 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2971 def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2972 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2973 def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2974 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2975 def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2976 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2978 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2979 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
2980 def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",
2981 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2982 def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}",
2983 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2984 def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}",
2985 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2987 def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}",
2988 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>;
2989 def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}",
2990 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2991 def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}",
2992 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2993 def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}",
2994 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2996 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2997 "|cmls.8b\t$dst, $src1, $src2}",
2998 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2999 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
3000 "|cmls.16b\t$dst, $src1, $src2}",
3001 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3002 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
3003 "|cmls.4h\t$dst, $src1, $src2}",
3004 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3005 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
3006 "|cmls.8h\t$dst, $src1, $src2}",
3007 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3008 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
3009 "|cmls.2s\t$dst, $src1, $src2}",
3010 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3011 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
3012 "|cmls.4s\t$dst, $src1, $src2}",
3013 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3014 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
3015 "|cmls.2d\t$dst, $src1, $src2}",
3016 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3018 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
3019 "|cmlo.8b\t$dst, $src1, $src2}",
3020 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3021 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
3022 "|cmlo.16b\t$dst, $src1, $src2}",
3023 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3024 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
3025 "|cmlo.4h\t$dst, $src1, $src2}",
3026 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3027 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
3028 "|cmlo.8h\t$dst, $src1, $src2}",
3029 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3030 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
3031 "|cmlo.2s\t$dst, $src1, $src2}",
3032 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3033 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
3034 "|cmlo.4s\t$dst, $src1, $src2}",
3035 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3036 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
3037 "|cmlo.2d\t$dst, $src1, $src2}",
3038 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3040 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
3041 "|cmle.8b\t$dst, $src1, $src2}",
3042 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3043 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
3044 "|cmle.16b\t$dst, $src1, $src2}",
3045 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3046 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
3047 "|cmle.4h\t$dst, $src1, $src2}",
3048 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3049 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
3050 "|cmle.8h\t$dst, $src1, $src2}",
3051 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3052 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
3053 "|cmle.2s\t$dst, $src1, $src2}",
3054 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3055 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
3056 "|cmle.4s\t$dst, $src1, $src2}",
3057 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3058 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
3059 "|cmle.2d\t$dst, $src1, $src2}",
3060 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3062 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
3063 "|cmlt.8b\t$dst, $src1, $src2}",
3064 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
3065 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
3066 "|cmlt.16b\t$dst, $src1, $src2}",
3067 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
3068 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
3069 "|cmlt.4h\t$dst, $src1, $src2}",
3070 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
3071 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
3072 "|cmlt.8h\t$dst, $src1, $src2}",
3073 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
3074 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
3075 "|cmlt.2s\t$dst, $src1, $src2}",
3076 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
3077 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
3078 "|cmlt.4s\t$dst, $src1, $src2}",
3079 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
3080 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
3081 "|cmlt.2d\t$dst, $src1, $src2}",
3082 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
3084 let Predicates = [HasNEON, HasFullFP16] in {
3085 def : InstAlias<"{fcmle\t$dst.4h, $src1.4h, $src2.4h" #
3086 "|fcmle.4h\t$dst, $src1, $src2}",
3087 (FCMGEv4f16 V64:$dst, V64:$src2, V64:$src1), 0>;
3088 def : InstAlias<"{fcmle\t$dst.8h, $src1.8h, $src2.8h" #
3089 "|fcmle.8h\t$dst, $src1, $src2}",
3090 (FCMGEv8f16 V128:$dst, V128:$src2, V128:$src1), 0>;
3092 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
3093 "|fcmle.2s\t$dst, $src1, $src2}",
3094 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3095 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
3096 "|fcmle.4s\t$dst, $src1, $src2}",
3097 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3098 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
3099 "|fcmle.2d\t$dst, $src1, $src2}",
3100 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3102 let Predicates = [HasNEON, HasFullFP16] in {
3103 def : InstAlias<"{fcmlt\t$dst.4h, $src1.4h, $src2.4h" #
3104 "|fcmlt.4h\t$dst, $src1, $src2}",
3105 (FCMGTv4f16 V64:$dst, V64:$src2, V64:$src1), 0>;
3106 def : InstAlias<"{fcmlt\t$dst.8h, $src1.8h, $src2.8h" #
3107 "|fcmlt.8h\t$dst, $src1, $src2}",
3108 (FCMGTv8f16 V128:$dst, V128:$src2, V128:$src1), 0>;
3110 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
3111 "|fcmlt.2s\t$dst, $src1, $src2}",
3112 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3113 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
3114 "|fcmlt.4s\t$dst, $src1, $src2}",
3115 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3116 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
3117 "|fcmlt.2d\t$dst, $src1, $src2}",
3118 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3120 let Predicates = [HasNEON, HasFullFP16] in {
3121 def : InstAlias<"{facle\t$dst.4h, $src1.4h, $src2.4h" #
3122 "|facle.4h\t$dst, $src1, $src2}",
3123 (FACGEv4f16 V64:$dst, V64:$src2, V64:$src1), 0>;
3124 def : InstAlias<"{facle\t$dst.8h, $src1.8h, $src2.8h" #
3125 "|facle.8h\t$dst, $src1, $src2}",
3126 (FACGEv8f16 V128:$dst, V128:$src2, V128:$src1), 0>;
3128 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
3129 "|facle.2s\t$dst, $src1, $src2}",
3130 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3131 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
3132 "|facle.4s\t$dst, $src1, $src2}",
3133 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3134 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
3135 "|facle.2d\t$dst, $src1, $src2}",
3136 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3138 let Predicates = [HasNEON, HasFullFP16] in {
3139 def : InstAlias<"{faclt\t$dst.4h, $src1.4h, $src2.4h" #
3140 "|faclt.4h\t$dst, $src1, $src2}",
3141 (FACGTv4f16 V64:$dst, V64:$src2, V64:$src1), 0>;
3142 def : InstAlias<"{faclt\t$dst.8h, $src1.8h, $src2.8h" #
3143 "|faclt.8h\t$dst, $src1, $src2}",
3144 (FACGTv8f16 V128:$dst, V128:$src2, V128:$src1), 0>;
3146 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
3147 "|faclt.2s\t$dst, $src1, $src2}",
3148 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
3149 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
3150 "|faclt.4s\t$dst, $src1, $src2}",
3151 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
3152 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
3153 "|faclt.2d\t$dst, $src1, $src2}",
3154 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
3156 //===----------------------------------------------------------------------===//
3157 // Advanced SIMD three scalar instructions.
3158 //===----------------------------------------------------------------------===//
3160 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
3161 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>;
3162 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
3163 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
3164 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
3165 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
3166 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
3167 defm FABD : SIMDFPThreeScalar<1, 1, 0b010, "fabd", int_aarch64_sisd_fabd>;
3168 def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3169 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
3170 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b101, "facge",
3171 int_aarch64_neon_facge>;
3172 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b101, "facgt",
3173 int_aarch64_neon_facgt>;
3174 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b100, "fcmeq", AArch64fcmeq>;
3175 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b100, "fcmge", AArch64fcmge>;
3176 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b100, "fcmgt", AArch64fcmgt>;
3177 defm FMULX : SIMDFPThreeScalar<0, 0, 0b011, "fmulx", int_aarch64_neon_fmulx>;
3178 defm FRECPS : SIMDFPThreeScalar<0, 0, 0b111, "frecps", int_aarch64_neon_frecps>;
3179 defm FRSQRTS : SIMDFPThreeScalar<0, 1, 0b111, "frsqrts", int_aarch64_neon_frsqrts>;
3180 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>;
3181 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;
3182 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
3183 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>;
3184 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>;
3185 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>;
3186 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>;
3187 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;
3188 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
3189 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>;
3190 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>;
3191 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>;
3192 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>;
3193 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>;
3194 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;
3195 let Predicates = [HasV8_1a] in {
3196 defm SQRDMLAH : SIMDThreeScalarHSTied<1, 0, 0b10000, "sqrdmlah">;
3197 defm SQRDMLSH : SIMDThreeScalarHSTied<1, 0, 0b10001, "sqrdmlsh">;
3198 def : Pat<(i32 (int_aarch64_neon_sqadd
3200 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn),
3201 (i32 FPR32:$Rm))))),
3202 (SQRDMLAHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3203 def : Pat<(i32 (int_aarch64_neon_sqsub
3205 (i32 (int_aarch64_neon_sqrdmulh (i32 FPR32:$Rn),
3206 (i32 FPR32:$Rm))))),
3207 (SQRDMLSHv1i32 FPR32:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3210 def : InstAlias<"cmls $dst, $src1, $src2",
3211 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3212 def : InstAlias<"cmle $dst, $src1, $src2",
3213 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3214 def : InstAlias<"cmlo $dst, $src1, $src2",
3215 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3216 def : InstAlias<"cmlt $dst, $src1, $src2",
3217 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3218 def : InstAlias<"fcmle $dst, $src1, $src2",
3219 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3220 def : InstAlias<"fcmle $dst, $src1, $src2",
3221 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3222 def : InstAlias<"fcmlt $dst, $src1, $src2",
3223 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3224 def : InstAlias<"fcmlt $dst, $src1, $src2",
3225 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3226 def : InstAlias<"facle $dst, $src1, $src2",
3227 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3228 def : InstAlias<"facle $dst, $src1, $src2",
3229 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3230 def : InstAlias<"faclt $dst, $src1, $src2",
3231 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
3232 def : InstAlias<"faclt $dst, $src1, $src2",
3233 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
3235 //===----------------------------------------------------------------------===//
3236 // Advanced SIMD three scalar instructions (mixed operands).
3237 //===----------------------------------------------------------------------===//
3238 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
3239 int_aarch64_neon_sqdmulls_scalar>;
3240 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
3241 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
3243 def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),
3244 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3245 (i32 FPR32:$Rm))))),
3246 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3247 def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),
3248 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3249 (i32 FPR32:$Rm))))),
3250 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3252 //===----------------------------------------------------------------------===//
3253 // Advanced SIMD two scalar instructions.
3254 //===----------------------------------------------------------------------===//
3256 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_aarch64_neon_abs>;
3257 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;
3258 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;
3259 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;
3260 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>;
3261 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>;
3262 defm FCMEQ : SIMDFPCmpTwoScalar<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
3263 defm FCMGE : SIMDFPCmpTwoScalar<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
3264 defm FCMGT : SIMDFPCmpTwoScalar<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
3265 defm FCMLE : SIMDFPCmpTwoScalar<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
3266 defm FCMLT : SIMDFPCmpTwoScalar<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
3267 defm FCVTAS : SIMDFPTwoScalar< 0, 0, 0b11100, "fcvtas">;
3268 defm FCVTAU : SIMDFPTwoScalar< 1, 0, 0b11100, "fcvtau">;
3269 defm FCVTMS : SIMDFPTwoScalar< 0, 0, 0b11011, "fcvtms">;
3270 defm FCVTMU : SIMDFPTwoScalar< 1, 0, 0b11011, "fcvtmu">;
3271 defm FCVTNS : SIMDFPTwoScalar< 0, 0, 0b11010, "fcvtns">;
3272 defm FCVTNU : SIMDFPTwoScalar< 1, 0, 0b11010, "fcvtnu">;
3273 defm FCVTPS : SIMDFPTwoScalar< 0, 1, 0b11010, "fcvtps">;
3274 defm FCVTPU : SIMDFPTwoScalar< 1, 1, 0b11010, "fcvtpu">;
3275 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
3276 defm FCVTZS : SIMDFPTwoScalar< 0, 1, 0b11011, "fcvtzs">;
3277 defm FCVTZU : SIMDFPTwoScalar< 1, 1, 0b11011, "fcvtzu">;
3278 defm FRECPE : SIMDFPTwoScalar< 0, 1, 0b11101, "frecpe">;
3279 defm FRECPX : SIMDFPTwoScalar< 0, 1, 0b11111, "frecpx">;
3280 defm FRSQRTE : SIMDFPTwoScalar< 1, 1, 0b11101, "frsqrte">;
3281 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
3282 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
3283 defm SCVTF : SIMDFPTwoScalarCVT< 0, 0, 0b11101, "scvtf", AArch64sitof>;
3284 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
3285 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
3286 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>;
3287 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>;
3288 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
3289 int_aarch64_neon_suqadd>;
3290 defm UCVTF : SIMDFPTwoScalarCVT< 1, 0, 0b11101, "ucvtf", AArch64uitof>;
3291 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>;
3292 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
3293 int_aarch64_neon_usqadd>;
3295 def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
3297 def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))),
3298 (FCVTASv1i64 FPR64:$Rn)>;
3299 def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))),
3300 (FCVTAUv1i64 FPR64:$Rn)>;
3301 def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))),
3302 (FCVTMSv1i64 FPR64:$Rn)>;
3303 def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))),
3304 (FCVTMUv1i64 FPR64:$Rn)>;
3305 def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))),
3306 (FCVTNSv1i64 FPR64:$Rn)>;
3307 def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))),
3308 (FCVTNUv1i64 FPR64:$Rn)>;
3309 def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),
3310 (FCVTPSv1i64 FPR64:$Rn)>;
3311 def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),
3312 (FCVTPUv1i64 FPR64:$Rn)>;
3314 def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),
3315 (FRECPEv1i32 FPR32:$Rn)>;
3316 def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),
3317 (FRECPEv1i64 FPR64:$Rn)>;
3318 def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))),
3319 (FRECPEv1i64 FPR64:$Rn)>;
3321 def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),
3322 (FRECPXv1i32 FPR32:$Rn)>;
3323 def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),
3324 (FRECPXv1i64 FPR64:$Rn)>;
3326 def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),
3327 (FRSQRTEv1i32 FPR32:$Rn)>;
3328 def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),
3329 (FRSQRTEv1i64 FPR64:$Rn)>;
3330 def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))),
3331 (FRSQRTEv1i64 FPR64:$Rn)>;
3333 // If an integer is about to be converted to a floating point value,
3334 // just load it on the floating point unit.
3335 // Here are the patterns for 8 and 16-bits to float.
3337 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
3338 SDPatternOperator loadop, Instruction UCVTF,
3339 ROAddrMode ro, Instruction LDRW, Instruction LDRX,
3341 def : Pat<(DstTy (uint_to_fp (SrcTy
3342 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm,
3343 ro.Wext:$extend))))),
3344 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3345 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
3348 def : Pat<(DstTy (uint_to_fp (SrcTy
3349 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm,
3350 ro.Wext:$extend))))),
3351 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3352 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
3356 defm : UIntToFPROLoadPat<f32, i32, zextloadi8,
3357 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>;
3358 def : Pat <(f32 (uint_to_fp (i32
3359 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3360 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3361 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3362 def : Pat <(f32 (uint_to_fp (i32
3363 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3364 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3365 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3366 // 16-bits -> float.
3367 defm : UIntToFPROLoadPat<f32, i32, zextloadi16,
3368 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
3369 def : Pat <(f32 (uint_to_fp (i32
3370 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3371 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3372 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3373 def : Pat <(f32 (uint_to_fp (i32
3374 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3375 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3376 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3377 // 32-bits are handled in target specific dag combine:
3378 // performIntToFpCombine.
3379 // 64-bits integer to 32-bits floating point, not possible with
3380 // UCVTF on floating point registers (both source and destination
3381 // must have the same size).
3383 // Here are the patterns for 8, 16, 32, and 64-bits to double.
3384 // 8-bits -> double.
3385 defm : UIntToFPROLoadPat<f64, i32, zextloadi8,
3386 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>;
3387 def : Pat <(f64 (uint_to_fp (i32
3388 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3389 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3390 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3391 def : Pat <(f64 (uint_to_fp (i32
3392 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3393 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3394 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3395 // 16-bits -> double.
3396 defm : UIntToFPROLoadPat<f64, i32, zextloadi16,
3397 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;
3398 def : Pat <(f64 (uint_to_fp (i32
3399 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3400 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3401 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3402 def : Pat <(f64 (uint_to_fp (i32
3403 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3404 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3405 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3406 // 32-bits -> double.
3407 defm : UIntToFPROLoadPat<f64, i32, load,
3408 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>;
3409 def : Pat <(f64 (uint_to_fp (i32
3410 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
3411 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3412 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;
3413 def : Pat <(f64 (uint_to_fp (i32
3414 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
3415 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3416 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
3417 // 64-bits -> double are handled in target specific dag combine:
3418 // performIntToFpCombine.
3420 //===----------------------------------------------------------------------===//
3421 // Advanced SIMD three different-sized vector instructions.
3422 //===----------------------------------------------------------------------===//
3424 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
3425 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
3426 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
3427 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
3428 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;
3429 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
3431 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
3433 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
3434 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
3435 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
3436 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
3437 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
3438 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3439 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
3440 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3441 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>;
3442 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
3443 int_aarch64_neon_sqadd>;
3444 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
3445 int_aarch64_neon_sqsub>;
3446 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
3447 int_aarch64_neon_sqdmull>;
3448 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
3449 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
3450 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
3451 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
3452 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
3454 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
3455 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
3456 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
3457 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
3458 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
3459 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3460 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
3461 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3462 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>;
3463 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
3464 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
3465 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
3466 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
3468 // Additional patterns for SMULL and UMULL
3469 multiclass Neon_mul_widen_patterns<SDPatternOperator opnode,
3470 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3471 def : Pat<(v8i16 (opnode (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3472 (INST8B V64:$Rn, V64:$Rm)>;
3473 def : Pat<(v4i32 (opnode (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3474 (INST4H V64:$Rn, V64:$Rm)>;
3475 def : Pat<(v2i64 (opnode (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3476 (INST2S V64:$Rn, V64:$Rm)>;
3479 defm : Neon_mul_widen_patterns<AArch64smull, SMULLv8i8_v8i16,
3480 SMULLv4i16_v4i32, SMULLv2i32_v2i64>;
3481 defm : Neon_mul_widen_patterns<AArch64umull, UMULLv8i8_v8i16,
3482 UMULLv4i16_v4i32, UMULLv2i32_v2i64>;
3484 // Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL
3485 multiclass Neon_mulacc_widen_patterns<SDPatternOperator opnode,
3486 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3487 def : Pat<(v8i16 (opnode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3488 (INST8B V128:$Rd, V64:$Rn, V64:$Rm)>;
3489 def : Pat<(v4i32 (opnode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3490 (INST4H V128:$Rd, V64:$Rn, V64:$Rm)>;
3491 def : Pat<(v2i64 (opnode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3492 (INST2S V128:$Rd, V64:$Rn, V64:$Rm)>;
3495 defm : Neon_mulacc_widen_patterns<
3496 TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3497 SMLALv8i8_v8i16, SMLALv4i16_v4i32, SMLALv2i32_v2i64>;
3498 defm : Neon_mulacc_widen_patterns<
3499 TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3500 UMLALv8i8_v8i16, UMLALv4i16_v4i32, UMLALv2i32_v2i64>;
3501 defm : Neon_mulacc_widen_patterns<
3502 TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3503 SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>;
3504 defm : Neon_mulacc_widen_patterns<
3505 TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3506 UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>;
3508 // Patterns for 64-bit pmull
3509 def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm),
3510 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
3511 def : Pat<(int_aarch64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
3512 (vector_extract (v2i64 V128:$Rm), (i64 1))),
3513 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
3515 // CodeGen patterns for addhn and subhn instructions, which can actually be
3516 // written in LLVM IR without too much difficulty.
3519 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
3520 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3521 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3523 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3524 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3526 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3527 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3528 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3530 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3531 V128:$Rn, V128:$Rm)>;
3532 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3533 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3535 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3536 V128:$Rn, V128:$Rm)>;
3537 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3538 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3540 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3541 V128:$Rn, V128:$Rm)>;
3544 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
3545 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3546 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3548 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3549 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3551 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3552 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3553 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3555 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3556 V128:$Rn, V128:$Rm)>;
3557 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3558 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3560 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3561 V128:$Rn, V128:$Rm)>;
3562 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3563 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3565 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3566 V128:$Rn, V128:$Rm)>;
3568 //----------------------------------------------------------------------------
3569 // AdvSIMD bitwise extract from vector instruction.
3570 //----------------------------------------------------------------------------
3572 defm EXT : SIMDBitwiseExtract<"ext">;
3574 def : Pat<(v4i16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3575 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3576 def : Pat<(v8i16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3577 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3578 def : Pat<(v2i32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3579 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3580 def : Pat<(v2f32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3581 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3582 def : Pat<(v4i32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3583 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3584 def : Pat<(v4f32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3585 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3586 def : Pat<(v2i64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3587 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3588 def : Pat<(v2f64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3589 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3590 def : Pat<(v4f16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3591 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3592 def : Pat<(v8f16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3593 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3595 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
3597 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
3598 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3599 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
3600 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3601 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
3602 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3603 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
3604 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3605 def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 4))),
3606 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3607 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
3608 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3609 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
3610 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3613 //----------------------------------------------------------------------------
3614 // AdvSIMD zip vector
3615 //----------------------------------------------------------------------------
3617 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;
3618 defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>;
3619 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
3620 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;
3621 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
3622 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;
3624 //----------------------------------------------------------------------------
3625 // AdvSIMD TBL/TBX instructions
3626 //----------------------------------------------------------------------------
3628 defm TBL : SIMDTableLookup< 0, "tbl">;
3629 defm TBX : SIMDTableLookupTied<1, "tbx">;
3631 def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3632 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
3633 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3634 (TBLv16i8One V128:$Ri, V128:$Rn)>;
3636 def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),
3637 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3638 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
3639 def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),
3640 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3641 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
3644 //----------------------------------------------------------------------------
3645 // AdvSIMD scalar CPY instruction
3646 //----------------------------------------------------------------------------
3648 defm CPY : SIMDScalarCPY<"cpy">;
3650 //----------------------------------------------------------------------------
3651 // AdvSIMD scalar pairwise instructions
3652 //----------------------------------------------------------------------------
3654 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
3655 defm FADDP : SIMDFPPairwiseScalar<0, 0b01101, "faddp">;
3656 defm FMAXNMP : SIMDFPPairwiseScalar<0, 0b01100, "fmaxnmp">;
3657 defm FMAXP : SIMDFPPairwiseScalar<0, 0b01111, "fmaxp">;
3658 defm FMINNMP : SIMDFPPairwiseScalar<1, 0b01100, "fminnmp">;
3659 defm FMINP : SIMDFPPairwiseScalar<1, 0b01111, "fminp">;
3660 def : Pat<(v2i64 (AArch64saddv V128:$Rn)),
3661 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
3662 def : Pat<(v2i64 (AArch64uaddv V128:$Rn)),
3663 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), (ADDPv2i64p V128:$Rn), dsub)>;
3664 def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))),
3665 (FADDPv2i32p V64:$Rn)>;
3666 def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))),
3667 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
3668 def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))),
3669 (FADDPv2i64p V128:$Rn)>;
3670 def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))),
3671 (FMAXNMPv2i32p V64:$Rn)>;
3672 def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))),
3673 (FMAXNMPv2i64p V128:$Rn)>;
3674 def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))),
3675 (FMAXPv2i32p V64:$Rn)>;
3676 def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))),
3677 (FMAXPv2i64p V128:$Rn)>;
3678 def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))),
3679 (FMINNMPv2i32p V64:$Rn)>;
3680 def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))),
3681 (FMINNMPv2i64p V128:$Rn)>;
3682 def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))),
3683 (FMINPv2i32p V64:$Rn)>;
3684 def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))),
3685 (FMINPv2i64p V128:$Rn)>;
3687 //----------------------------------------------------------------------------
3688 // AdvSIMD INS/DUP instructions
3689 //----------------------------------------------------------------------------
3691 def DUPv8i8gpr : SIMDDupFromMain<0, {?,?,?,?,1}, ".8b", v8i8, V64, GPR32>;
3692 def DUPv16i8gpr : SIMDDupFromMain<1, {?,?,?,?,1}, ".16b", v16i8, V128, GPR32>;
3693 def DUPv4i16gpr : SIMDDupFromMain<0, {?,?,?,1,0}, ".4h", v4i16, V64, GPR32>;
3694 def DUPv8i16gpr : SIMDDupFromMain<1, {?,?,?,1,0}, ".8h", v8i16, V128, GPR32>;
3695 def DUPv2i32gpr : SIMDDupFromMain<0, {?,?,1,0,0}, ".2s", v2i32, V64, GPR32>;
3696 def DUPv4i32gpr : SIMDDupFromMain<1, {?,?,1,0,0}, ".4s", v4i32, V128, GPR32>;
3697 def DUPv2i64gpr : SIMDDupFromMain<1, {?,1,0,0,0}, ".2d", v2i64, V128, GPR64>;
3699 def DUPv2i64lane : SIMDDup64FromElement;
3700 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3701 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3702 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3703 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3704 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3705 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3707 def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))),
3708 (v2f32 (DUPv2i32lane
3709 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3711 def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))),
3712 (v4f32 (DUPv4i32lane
3713 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3715 def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))),
3716 (v2f64 (DUPv2i64lane
3717 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3719 def : Pat<(v4f16 (AArch64dup (f16 FPR16:$Rn))),
3720 (v4f16 (DUPv4i16lane
3721 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3723 def : Pat<(v8f16 (AArch64dup (f16 FPR16:$Rn))),
3724 (v8f16 (DUPv8i16lane
3725 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3728 def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3729 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>;
3730 def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3731 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>;
3733 def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3734 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3735 def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3736 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3737 def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3738 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3740 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane
3741 // instruction even if the types don't match: we just have to remap the lane
3742 // carefully. N.b. this trick only applies to truncations.
3743 def VecIndex_x2 : SDNodeXForm<imm, [{
3744 return CurDAG->getTargetConstant(2 * N->getZExtValue(), SDLoc(N), MVT::i64);
3746 def VecIndex_x4 : SDNodeXForm<imm, [{
3747 return CurDAG->getTargetConstant(4 * N->getZExtValue(), SDLoc(N), MVT::i64);
3749 def VecIndex_x8 : SDNodeXForm<imm, [{
3750 return CurDAG->getTargetConstant(8 * N->getZExtValue(), SDLoc(N), MVT::i64);
3753 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3754 ValueType Src128VT, ValueType ScalVT,
3755 Instruction DUP, SDNodeXForm IdxXFORM> {
3756 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3758 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3760 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3762 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3765 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3766 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3767 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3769 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3770 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3771 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3773 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3774 SDNodeXForm IdxXFORM> {
3775 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3777 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3779 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3781 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3784 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3785 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3786 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3788 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3789 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3790 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3792 // SMOV and UMOV definitions, with some extra patterns for convenience
3796 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3797 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3798 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3799 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3800 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3801 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3802 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3803 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3804 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3805 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3806 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3807 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3809 // Extracting i8 or i16 elements will have the zero-extend transformed to
3810 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3811 // for AArch64. Match these patterns here since UMOV already zeroes out the high
3812 // bits of the destination register.
3813 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3815 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3816 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3818 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3822 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3823 (SUBREG_TO_REG (i32 0),
3824 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3825 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3826 (SUBREG_TO_REG (i32 0),
3827 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3829 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3830 (SUBREG_TO_REG (i32 0),
3831 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3832 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3833 (SUBREG_TO_REG (i32 0),
3834 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3836 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3837 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3838 (i32 FPR32:$Rn), ssub))>;
3839 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3840 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3841 (i32 FPR32:$Rn), ssub))>;
3842 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3843 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3844 (i64 FPR64:$Rn), dsub))>;
3846 def : Pat<(v4f16 (scalar_to_vector (f16 FPR16:$Rn))),
3847 (INSERT_SUBREG (v4f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;
3848 def : Pat<(v8f16 (scalar_to_vector (f16 FPR16:$Rn))),
3849 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rn, hsub)>;
3851 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3852 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3853 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3854 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3855 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3856 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3858 def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn),
3859 (f16 FPR16:$Rm), (i64 VectorIndexS:$imm))),
3862 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3864 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3868 def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn),
3869 (f16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
3871 V128:$Rn, VectorIndexH:$imm,
3872 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3875 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3876 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3879 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3881 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3884 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3885 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3887 V128:$Rn, VectorIndexS:$imm,
3888 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3890 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3891 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3893 V128:$Rn, VectorIndexD:$imm,
3894 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3897 // Copy an element at a constant index in one vector into a constant indexed
3898 // element of another.
3899 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3900 // index type and INS extension
3901 def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane
3902 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3903 VectorIndexB:$idx2)),
3905 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3907 def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane
3908 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3909 VectorIndexH:$idx2)),
3911 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3913 def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane
3914 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3915 VectorIndexS:$idx2)),
3917 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3919 def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
3920 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3921 VectorIndexD:$idx2)),
3923 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3926 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3927 ValueType VTScal, Instruction INS> {
3928 def : Pat<(VT128 (vector_insert V128:$src,
3929 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3931 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3933 def : Pat<(VT128 (vector_insert V128:$src,
3934 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3936 (INS V128:$src, imm:$Immd,
3937 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3939 def : Pat<(VT64 (vector_insert V64:$src,
3940 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3942 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3943 imm:$Immd, V128:$Rn, imm:$Immn),
3946 def : Pat<(VT64 (vector_insert V64:$src,
3947 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3950 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3951 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3955 defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>;
3956 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3957 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3960 // Floating point vector extractions are codegen'd as either a sequence of
3961 // subregister extractions, or a MOV (aka CPY here, alias for DUP) if
3962 // the lane number is anything other than zero.
3963 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3964 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3965 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3966 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3967 def : Pat<(vector_extract (v8f16 V128:$Rn), 0),
3968 (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>;
3970 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3971 (f64 (CPYi64 V128:$Rn, VectorIndexD:$idx))>;
3972 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3973 (f32 (CPYi32 V128:$Rn, VectorIndexS:$idx))>;
3974 def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx),
3975 (f16 (CPYi16 V128:$Rn, VectorIndexH:$idx))>;
3977 // All concat_vectors operations are canonicalised to act on i64 vectors for
3978 // AArch64. In the general case we need an instruction, which had just as well be
3980 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3981 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3982 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3983 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3985 def : ConcatPat<v2i64, v1i64>;
3986 def : ConcatPat<v2f64, v1f64>;
3987 def : ConcatPat<v4i32, v2i32>;
3988 def : ConcatPat<v4f32, v2f32>;
3989 def : ConcatPat<v8i16, v4i16>;
3990 def : ConcatPat<v8f16, v4f16>;
3991 def : ConcatPat<v16i8, v8i8>;
3993 // If the high lanes are undef, though, we can just ignore them:
3994 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3995 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3996 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3998 def : ConcatUndefPat<v2i64, v1i64>;
3999 def : ConcatUndefPat<v2f64, v1f64>;
4000 def : ConcatUndefPat<v4i32, v2i32>;
4001 def : ConcatUndefPat<v4f32, v2f32>;
4002 def : ConcatUndefPat<v8i16, v4i16>;
4003 def : ConcatUndefPat<v16i8, v8i8>;
4005 //----------------------------------------------------------------------------
4006 // AdvSIMD across lanes instructions
4007 //----------------------------------------------------------------------------
4009 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
4010 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
4011 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
4012 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
4013 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
4014 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
4015 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
4016 defm FMAXNMV : SIMDFPAcrossLanes<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>;
4017 defm FMAXV : SIMDFPAcrossLanes<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>;
4018 defm FMINNMV : SIMDFPAcrossLanes<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>;
4019 defm FMINV : SIMDFPAcrossLanes<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
4021 // Patterns for across-vector intrinsics, that have a node equivalent, that
4022 // returns a vector (with only the low lane defined) instead of a scalar.
4023 // In effect, opNode is the same as (scalar_to_vector (IntNode)).
4024 multiclass SIMDAcrossLanesIntrinsic<string baseOpc,
4025 SDPatternOperator opNode> {
4026 // If a lane instruction caught the vector_extract around opNode, we can
4027 // directly match the latter to the instruction.
4028 def : Pat<(v8i8 (opNode V64:$Rn)),
4029 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
4030 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub)>;
4031 def : Pat<(v16i8 (opNode V128:$Rn)),
4032 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4033 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub)>;
4034 def : Pat<(v4i16 (opNode V64:$Rn)),
4035 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
4036 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub)>;
4037 def : Pat<(v8i16 (opNode V128:$Rn)),
4038 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4039 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub)>;
4040 def : Pat<(v4i32 (opNode V128:$Rn)),
4041 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4042 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub)>;
4045 // If none did, fallback to the explicit patterns, consuming the vector_extract.
4046 def : Pat<(i32 (vector_extract (insert_subvector undef, (v8i8 (opNode V64:$Rn)),
4047 (i32 0)), (i64 0))),
4048 (EXTRACT_SUBREG (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
4049 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn),
4051 def : Pat<(i32 (vector_extract (v16i8 (opNode V128:$Rn)), (i64 0))),
4052 (EXTRACT_SUBREG (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4053 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn),
4055 def : Pat<(i32 (vector_extract (insert_subvector undef,
4056 (v4i16 (opNode V64:$Rn)), (i32 0)), (i64 0))),
4057 (EXTRACT_SUBREG (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
4058 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn),
4060 def : Pat<(i32 (vector_extract (v8i16 (opNode V128:$Rn)), (i64 0))),
4061 (EXTRACT_SUBREG (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4062 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn),
4064 def : Pat<(i32 (vector_extract (v4i32 (opNode V128:$Rn)), (i64 0))),
4065 (EXTRACT_SUBREG (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4066 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn),
4071 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc,
4072 SDPatternOperator opNode>
4073 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
4074 // If there is a sign extension after this intrinsic, consume it as smov already
4076 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
4077 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), i8)),
4079 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4080 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
4082 def : Pat<(i32 (sext_inreg (i32 (vector_extract
4083 (opNode (v16i8 V128:$Rn)), (i64 0))), i8)),
4085 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4086 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
4088 def : Pat<(i32 (sext_inreg (i32 (vector_extract (insert_subvector undef,
4089 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), i16)),
4091 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4092 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
4094 def : Pat<(i32 (sext_inreg (i32 (vector_extract
4095 (opNode (v8i16 V128:$Rn)), (i64 0))), i16)),
4097 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4098 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
4102 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc,
4103 SDPatternOperator opNode>
4104 : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
4105 // If there is a masking operation keeping only what has been actually
4106 // generated, consume it.
4107 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
4108 (opNode (v8i8 V64:$Rn)), (i32 0)), (i64 0))), maski8_or_more)),
4109 (i32 (EXTRACT_SUBREG
4110 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4111 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
4113 def : Pat<(i32 (and (i32 (vector_extract (opNode (v16i8 V128:$Rn)), (i64 0))),
4115 (i32 (EXTRACT_SUBREG
4116 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4117 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
4119 def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
4120 (opNode (v4i16 V64:$Rn)), (i32 0)), (i64 0))), maski16_or_more)),
4121 (i32 (EXTRACT_SUBREG
4122 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4123 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
4125 def : Pat<(i32 (and (i32 (vector_extract (opNode (v8i16 V128:$Rn)), (i64 0))),
4127 (i32 (EXTRACT_SUBREG
4128 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4129 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
4133 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", AArch64saddv>;
4134 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
4135 def : Pat<(v2i32 (AArch64saddv (v2i32 V64:$Rn))),
4136 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
4138 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", AArch64uaddv>;
4139 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
4140 def : Pat<(v2i32 (AArch64uaddv (v2i32 V64:$Rn))),
4141 (ADDPv2i32 V64:$Rn, V64:$Rn)>;
4143 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", AArch64smaxv>;
4144 def : Pat<(v2i32 (AArch64smaxv (v2i32 V64:$Rn))),
4145 (SMAXPv2i32 V64:$Rn, V64:$Rn)>;
4147 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", AArch64sminv>;
4148 def : Pat<(v2i32 (AArch64sminv (v2i32 V64:$Rn))),
4149 (SMINPv2i32 V64:$Rn, V64:$Rn)>;
4151 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", AArch64umaxv>;
4152 def : Pat<(v2i32 (AArch64umaxv (v2i32 V64:$Rn))),
4153 (UMAXPv2i32 V64:$Rn, V64:$Rn)>;
4155 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", AArch64uminv>;
4156 def : Pat<(v2i32 (AArch64uminv (v2i32 V64:$Rn))),
4157 (UMINPv2i32 V64:$Rn, V64:$Rn)>;
4159 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
4160 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
4162 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4163 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
4165 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
4167 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4168 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
4171 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
4172 (i32 (EXTRACT_SUBREG
4173 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4174 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
4176 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
4177 (i32 (EXTRACT_SUBREG
4178 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4179 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
4182 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
4183 (i64 (EXTRACT_SUBREG
4184 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4185 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
4189 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
4191 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
4192 (i32 (EXTRACT_SUBREG
4193 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4194 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
4196 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
4197 (i32 (EXTRACT_SUBREG
4198 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4199 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
4202 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
4203 (i32 (EXTRACT_SUBREG
4204 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4205 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
4207 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
4208 (i32 (EXTRACT_SUBREG
4209 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4210 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
4213 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
4214 (i64 (EXTRACT_SUBREG
4215 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4216 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
4220 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>;
4221 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>;
4223 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
4224 def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))),
4225 (i64 (EXTRACT_SUBREG
4226 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4227 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
4229 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
4230 def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))),
4231 (i64 (EXTRACT_SUBREG
4232 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4233 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
4236 //------------------------------------------------------------------------------
4237 // AdvSIMD modified immediate instructions
4238 //------------------------------------------------------------------------------
4241 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
4243 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
4245 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4246 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4247 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4248 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4250 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4251 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4252 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4253 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4255 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4256 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4257 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4258 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4260 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4261 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4262 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4263 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4266 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1111, V128, fpimm8,
4268 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4269 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0, 0b1111, V64, fpimm8,
4271 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4272 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0, 0b1111, V128, fpimm8,
4274 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4275 let Predicates = [HasNEON, HasFullFP16] in {
4276 def FMOVv4f16_ns : SIMDModifiedImmVectorNoShift<0, 0, 1, 0b1111, V64, fpimm8,
4278 [(set (v4f16 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4279 def FMOVv8f16_ns : SIMDModifiedImmVectorNoShift<1, 0, 1, 0b1111, V128, fpimm8,
4281 [(set (v8f16 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4282 } // Predicates = [HasNEON, HasFullFP16]
4286 // EDIT byte mask: scalar
4287 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4288 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
4289 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
4290 // The movi_edit node has the immediate value already encoded, so we use
4291 // a plain imm0_255 here.
4292 def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)),
4293 (MOVID imm0_255:$shift)>;
4295 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
4296 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
4297 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
4298 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
4300 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
4301 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
4302 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
4303 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
4305 // EDIT byte mask: 2d
4307 // The movi_edit node has the immediate value already encoded, so we use
4308 // a plain imm0_255 in the pattern
4309 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4310 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1110, V128,
4313 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;
4316 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
4317 // Complexity is added to break a tie with a plain MOVI.
4318 let AddedComplexity = 1 in {
4319 def : Pat<(f32 fpimm0),
4320 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
4322 def : Pat<(f64 fpimm0),
4323 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
4327 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4328 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4329 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4330 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4332 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4333 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4334 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4335 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4337 def : Pat<(v2f64 (AArch64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
4338 def : Pat<(v4f32 (AArch64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
4340 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4341 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
4343 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4344 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4345 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4346 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4348 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4349 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4350 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4351 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4353 def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4354 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
4355 def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4356 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
4357 def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4358 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
4359 def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4360 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
4362 // EDIT per word: 2s & 4s with MSL shifter
4363 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
4364 [(set (v2i32 V64:$Rd),
4365 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4366 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
4367 [(set (v4i32 V128:$Rd),
4368 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4370 // Per byte: 8b & 16b
4371 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0, 0b1110, V64, imm0_255,
4373 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>;
4374 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0, 0b1110, V128, imm0_255,
4376 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>;
4380 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4381 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
4383 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4384 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4385 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4386 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4388 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4389 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4390 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4391 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4393 def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4394 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
4395 def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4396 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
4397 def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4398 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
4399 def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4400 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
4402 // EDIT per word: 2s & 4s with MSL shifter
4403 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
4404 [(set (v2i32 V64:$Rd),
4405 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4406 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
4407 [(set (v4i32 V128:$Rd),
4408 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4410 //----------------------------------------------------------------------------
4411 // AdvSIMD indexed element
4412 //----------------------------------------------------------------------------
4414 let hasSideEffects = 0 in {
4415 defm FMLA : SIMDFPIndexedTied<0, 0b0001, "fmla">;
4416 defm FMLS : SIMDFPIndexedTied<0, 0b0101, "fmls">;
4419 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
4420 // instruction expects the addend first, while the intrinsic expects it last.
4422 // On the other hand, there are quite a few valid combinatorial options due to
4423 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
4424 defm : SIMDFPIndexedTiedPatterns<"FMLA",
4425 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
4426 defm : SIMDFPIndexedTiedPatterns<"FMLA",
4427 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
4429 defm : SIMDFPIndexedTiedPatterns<"FMLS",
4430 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
4431 defm : SIMDFPIndexedTiedPatterns<"FMLS",
4432 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
4433 defm : SIMDFPIndexedTiedPatterns<"FMLS",
4434 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
4435 defm : SIMDFPIndexedTiedPatterns<"FMLS",
4436 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
4438 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
4439 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4441 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4442 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4443 VectorIndexS:$idx))),
4444 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4445 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4446 (v2f32 (AArch64duplane32
4447 (v4f32 (insert_subvector undef,
4448 (v2f32 (fneg V64:$Rm)),
4450 VectorIndexS:$idx)))),
4451 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4452 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4453 VectorIndexS:$idx)>;
4454 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4455 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4456 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4457 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4459 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4461 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4462 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4463 VectorIndexS:$idx))),
4464 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
4465 VectorIndexS:$idx)>;
4466 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4467 (v4f32 (AArch64duplane32
4468 (v4f32 (insert_subvector undef,
4469 (v2f32 (fneg V64:$Rm)),
4471 VectorIndexS:$idx)))),
4472 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4473 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4474 VectorIndexS:$idx)>;
4475 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4476 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4477 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4478 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4480 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
4481 // (DUPLANE from 64-bit would be trivial).
4482 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4483 (AArch64duplane64 (v2f64 (fneg V128:$Rm)),
4484 VectorIndexD:$idx))),
4486 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4487 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4488 (AArch64dup (f64 (fneg FPR64Op:$Rm))))),
4489 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
4490 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
4492 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
4493 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4494 (vector_extract (v4f32 (fneg V128:$Rm)),
4495 VectorIndexS:$idx))),
4496 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4497 V128:$Rm, VectorIndexS:$idx)>;
4498 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4499 (vector_extract (v4f32 (insert_subvector undef,
4500 (v2f32 (fneg V64:$Rm)),
4502 VectorIndexS:$idx))),
4503 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4504 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
4506 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
4507 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
4508 (vector_extract (v2f64 (fneg V128:$Rm)),
4509 VectorIndexS:$idx))),
4510 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
4511 V128:$Rm, VectorIndexS:$idx)>;
4514 defm : FMLSIndexedAfterNegPatterns<
4515 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
4516 defm : FMLSIndexedAfterNegPatterns<
4517 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
4519 defm FMULX : SIMDFPIndexed<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;
4520 defm FMUL : SIMDFPIndexed<0, 0b1001, "fmul", fmul>;
4522 def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4523 (FMULv2i32_indexed V64:$Rn,
4524 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4526 def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4527 (FMULv4i32_indexed V128:$Rn,
4528 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4530 def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))),
4531 (FMULv2i64_indexed V128:$Rn,
4532 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
4535 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>;
4536 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
4537 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
4538 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
4539 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
4540 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
4541 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
4542 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
4543 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4544 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
4545 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4546 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
4547 int_aarch64_neon_smull>;
4548 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
4549 int_aarch64_neon_sqadd>;
4550 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
4551 int_aarch64_neon_sqsub>;
4552 defm SQRDMLAH : SIMDIndexedSQRDMLxHSDTied<1, 0b1101, "sqrdmlah",
4553 int_aarch64_neon_sqadd>;
4554 defm SQRDMLSH : SIMDIndexedSQRDMLxHSDTied<1, 0b1111, "sqrdmlsh",
4555 int_aarch64_neon_sqsub>;
4556 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;
4557 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
4558 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4559 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
4560 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4561 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
4562 int_aarch64_neon_umull>;
4564 // A scalar sqdmull with the second operand being a vector lane can be
4565 // handled directly with the indexed instruction encoding.
4566 def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
4567 (vector_extract (v4i32 V128:$Vm),
4568 VectorIndexS:$idx)),
4569 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
4571 //----------------------------------------------------------------------------
4572 // AdvSIMD scalar shift instructions
4573 //----------------------------------------------------------------------------
4574 defm FCVTZS : SIMDFPScalarRShift<0, 0b11111, "fcvtzs">;
4575 defm FCVTZU : SIMDFPScalarRShift<1, 0b11111, "fcvtzu">;
4576 defm SCVTF : SIMDFPScalarRShift<0, 0b11100, "scvtf">;
4577 defm UCVTF : SIMDFPScalarRShift<1, 0b11100, "ucvtf">;
4578 // Codegen patterns for the above. We don't put these directly on the
4579 // instructions because TableGen's type inference can't handle the truth.
4580 // Having the same base pattern for fp <--> int totally freaks it out.
4581 def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
4582 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
4583 def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
4584 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
4585 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
4586 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4587 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
4588 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4589 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
4591 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4592 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
4594 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4595 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
4596 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4597 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
4598 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4599 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4600 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4601 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4602 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4603 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
4605 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4606 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
4608 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4610 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;
4611 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
4612 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
4613 int_aarch64_neon_sqrshrn>;
4614 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
4615 int_aarch64_neon_sqrshrun>;
4616 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4617 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4618 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
4619 int_aarch64_neon_sqshrn>;
4620 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
4621 int_aarch64_neon_sqshrun>;
4622 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4623 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>;
4624 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4625 TriOpFrag<(add node:$LHS,
4626 (AArch64srshri node:$MHS, node:$RHS))>>;
4627 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>;
4628 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
4629 TriOpFrag<(add node:$LHS,
4630 (AArch64vashr node:$MHS, node:$RHS))>>;
4631 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
4632 int_aarch64_neon_uqrshrn>;
4633 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4634 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4635 int_aarch64_neon_uqshrn>;
4636 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>;
4637 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
4638 TriOpFrag<(add node:$LHS,
4639 (AArch64urshri node:$MHS, node:$RHS))>>;
4640 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>;
4641 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
4642 TriOpFrag<(add node:$LHS,
4643 (AArch64vlshr node:$MHS, node:$RHS))>>;
4645 //----------------------------------------------------------------------------
4646 // AdvSIMD vector shift instructions
4647 //----------------------------------------------------------------------------
4648 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
4649 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
4650 defm SCVTF: SIMDVectorRShiftToFP<0, 0b11100, "scvtf",
4651 int_aarch64_neon_vcvtfxs2fp>;
4652 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
4653 int_aarch64_neon_rshrn>;
4654 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>;
4655 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
4656 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>;
4657 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>;
4658 def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4659 (i32 vecshiftL64:$imm))),
4660 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
4661 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
4662 int_aarch64_neon_sqrshrn>;
4663 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
4664 int_aarch64_neon_sqrshrun>;
4665 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4666 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4667 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
4668 int_aarch64_neon_sqshrn>;
4669 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
4670 int_aarch64_neon_sqshrun>;
4671 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>;
4672 def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4673 (i32 vecshiftR64:$imm))),
4674 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
4675 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>;
4676 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
4677 TriOpFrag<(add node:$LHS,
4678 (AArch64srshri node:$MHS, node:$RHS))> >;
4679 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
4680 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>;
4682 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>;
4683 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
4684 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>;
4685 defm UCVTF : SIMDVectorRShiftToFP<1, 0b11100, "ucvtf",
4686 int_aarch64_neon_vcvtfxu2fp>;
4687 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
4688 int_aarch64_neon_uqrshrn>;
4689 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4690 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
4691 int_aarch64_neon_uqshrn>;
4692 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>;
4693 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
4694 TriOpFrag<(add node:$LHS,
4695 (AArch64urshri node:$MHS, node:$RHS))> >;
4696 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
4697 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>;
4698 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>;
4699 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
4700 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >;
4702 // SHRN patterns for when a logical right shift was used instead of arithmetic
4703 // (the immediate guarantees no sign bits actually end up in the result so it
4705 def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
4706 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
4707 def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
4708 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
4709 def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
4710 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
4712 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
4713 (trunc (AArch64vlshr (v8i16 V128:$Rn),
4714 vecshiftR16Narrow:$imm)))),
4715 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4716 V128:$Rn, vecshiftR16Narrow:$imm)>;
4717 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
4718 (trunc (AArch64vlshr (v4i32 V128:$Rn),
4719 vecshiftR32Narrow:$imm)))),
4720 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4721 V128:$Rn, vecshiftR32Narrow:$imm)>;
4722 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
4723 (trunc (AArch64vlshr (v2i64 V128:$Rn),
4724 vecshiftR64Narrow:$imm)))),
4725 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4726 V128:$Rn, vecshiftR32Narrow:$imm)>;
4728 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
4729 // Anyexts are implemented as zexts.
4730 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
4731 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4732 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4733 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
4734 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4735 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4736 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
4737 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4738 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4739 // Also match an extend from the upper half of a 128 bit source register.
4740 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4741 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4742 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4743 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4744 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4745 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
4746 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4747 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4748 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4749 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4750 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4751 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
4752 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4753 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4754 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4755 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4756 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4757 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
4759 // Vector shift sxtl aliases
4760 def : InstAlias<"sxtl.8h $dst, $src1",
4761 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4762 def : InstAlias<"sxtl $dst.8h, $src1.8b",
4763 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4764 def : InstAlias<"sxtl.4s $dst, $src1",
4765 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4766 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4767 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4768 def : InstAlias<"sxtl.2d $dst, $src1",
4769 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4770 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4771 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4773 // Vector shift sxtl2 aliases
4774 def : InstAlias<"sxtl2.8h $dst, $src1",
4775 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4776 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4777 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4778 def : InstAlias<"sxtl2.4s $dst, $src1",
4779 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4780 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4781 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4782 def : InstAlias<"sxtl2.2d $dst, $src1",
4783 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4784 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4785 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4787 // Vector shift uxtl aliases
4788 def : InstAlias<"uxtl.8h $dst, $src1",
4789 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4790 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4791 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4792 def : InstAlias<"uxtl.4s $dst, $src1",
4793 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4794 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4795 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4796 def : InstAlias<"uxtl.2d $dst, $src1",
4797 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4798 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4799 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4801 // Vector shift uxtl2 aliases
4802 def : InstAlias<"uxtl2.8h $dst, $src1",
4803 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4804 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4805 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4806 def : InstAlias<"uxtl2.4s $dst, $src1",
4807 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4808 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4809 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4810 def : InstAlias<"uxtl2.2d $dst, $src1",
4811 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4812 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4813 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4815 // If an integer is about to be converted to a floating point value,
4816 // just load it on the floating point unit.
4817 // These patterns are more complex because floating point loads do not
4818 // support sign extension.
4819 // The sign extension has to be explicitly added and is only supported for
4820 // one step: byte-to-half, half-to-word, word-to-doubleword.
4821 // SCVTF GPR -> FPR is 9 cycles.
4822 // SCVTF FPR -> FPR is 4 cyclces.
4823 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4824 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4825 // and still being faster.
4826 // However, this is not good for code size.
4827 // 8-bits -> float. 2 sizes step-up.
4828 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>
4829 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),
4830 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4835 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4841 ssub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4843 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
4844 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
4845 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),
4846 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;
4847 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),
4848 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;
4849 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),
4850 (LDURBi GPR64sp:$Rn, simm9:$offset)>;
4852 // 16-bits -> float. 1 size step-up.
4853 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
4854 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4855 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4857 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4861 ssub)))>, Requires<[NotForCodeSize]>;
4863 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4864 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4865 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4866 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4867 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4868 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4869 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4870 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4872 // 32-bits to 32-bits are handled in target specific dag combine:
4873 // performIntToFpCombine.
4874 // 64-bits integer to 32-bits floating point, not possible with
4875 // SCVTF on floating point registers (both source and destination
4876 // must have the same size).
4878 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4879 // 8-bits -> double. 3 size step-up: give up.
4880 // 16-bits -> double. 2 size step.
4881 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>
4882 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4883 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4888 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4894 dsub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4896 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4897 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4898 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4899 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4900 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4901 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4902 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4903 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4904 // 32-bits -> double. 1 size step-up.
4905 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
4906 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),
4907 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4909 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4913 dsub)))>, Requires<[NotForCodeSize]>;
4915 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
4916 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
4917 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),
4918 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;
4919 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),
4920 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;
4921 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),
4922 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
4924 // 64-bits -> double are handled in target specific dag combine:
4925 // performIntToFpCombine.
4928 //----------------------------------------------------------------------------
4929 // AdvSIMD Load-Store Structure
4930 //----------------------------------------------------------------------------
4931 defm LD1 : SIMDLd1Multiple<"ld1">;
4932 defm LD2 : SIMDLd2Multiple<"ld2">;
4933 defm LD3 : SIMDLd3Multiple<"ld3">;
4934 defm LD4 : SIMDLd4Multiple<"ld4">;
4936 defm ST1 : SIMDSt1Multiple<"st1">;
4937 defm ST2 : SIMDSt2Multiple<"st2">;
4938 defm ST3 : SIMDSt3Multiple<"st3">;
4939 defm ST4 : SIMDSt4Multiple<"st4">;
4941 class Ld1Pat<ValueType ty, Instruction INST>
4942 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>;
4944 def : Ld1Pat<v16i8, LD1Onev16b>;
4945 def : Ld1Pat<v8i16, LD1Onev8h>;
4946 def : Ld1Pat<v4i32, LD1Onev4s>;
4947 def : Ld1Pat<v2i64, LD1Onev2d>;
4948 def : Ld1Pat<v8i8, LD1Onev8b>;
4949 def : Ld1Pat<v4i16, LD1Onev4h>;
4950 def : Ld1Pat<v2i32, LD1Onev2s>;
4951 def : Ld1Pat<v1i64, LD1Onev1d>;
4953 class St1Pat<ValueType ty, Instruction INST>
4954 : Pat<(store ty:$Vt, GPR64sp:$Rn),
4955 (INST ty:$Vt, GPR64sp:$Rn)>;
4957 def : St1Pat<v16i8, ST1Onev16b>;
4958 def : St1Pat<v8i16, ST1Onev8h>;
4959 def : St1Pat<v4i32, ST1Onev4s>;
4960 def : St1Pat<v2i64, ST1Onev2d>;
4961 def : St1Pat<v8i8, ST1Onev8b>;
4962 def : St1Pat<v4i16, ST1Onev4h>;
4963 def : St1Pat<v2i32, ST1Onev2s>;
4964 def : St1Pat<v1i64, ST1Onev1d>;
4970 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4971 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4972 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4973 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4974 let mayLoad = 1, hasSideEffects = 0 in {
4975 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4976 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4977 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4978 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4979 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4980 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4981 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4982 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4983 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4984 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4985 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4986 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4987 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4988 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4989 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4990 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4993 def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4994 (LD1Rv8b GPR64sp:$Rn)>;
4995 def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4996 (LD1Rv16b GPR64sp:$Rn)>;
4997 def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4998 (LD1Rv4h GPR64sp:$Rn)>;
4999 def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
5000 (LD1Rv8h GPR64sp:$Rn)>;
5001 def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
5002 (LD1Rv2s GPR64sp:$Rn)>;
5003 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
5004 (LD1Rv4s GPR64sp:$Rn)>;
5005 def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
5006 (LD1Rv2d GPR64sp:$Rn)>;
5007 def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
5008 (LD1Rv1d GPR64sp:$Rn)>;
5009 // Grab the floating point version too
5010 def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
5011 (LD1Rv2s GPR64sp:$Rn)>;
5012 def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
5013 (LD1Rv4s GPR64sp:$Rn)>;
5014 def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
5015 (LD1Rv2d GPR64sp:$Rn)>;
5016 def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
5017 (LD1Rv1d GPR64sp:$Rn)>;
5018 def : Pat<(v4f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
5019 (LD1Rv4h GPR64sp:$Rn)>;
5020 def : Pat<(v8f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
5021 (LD1Rv8h GPR64sp:$Rn)>;
5023 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
5024 ValueType VTy, ValueType STy, Instruction LD1>
5025 : Pat<(vector_insert (VTy VecListOne128:$Rd),
5026 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
5027 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
5029 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
5030 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
5031 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
5032 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
5033 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
5034 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
5035 def : Ld1Lane128Pat<load, VectorIndexH, v8f16, f16, LD1i16>;
5037 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
5038 ValueType VTy, ValueType STy, Instruction LD1>
5039 : Pat<(vector_insert (VTy VecListOne64:$Rd),
5040 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
5042 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
5043 VecIndex:$idx, GPR64sp:$Rn),
5046 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
5047 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
5048 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
5049 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
5050 def : Ld1Lane64Pat<load, VectorIndexH, v4f16, f16, LD1i16>;
5053 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
5054 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
5055 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
5056 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
5059 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
5060 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
5061 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
5062 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
5064 let AddedComplexity = 19 in
5065 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
5066 ValueType VTy, ValueType STy, Instruction ST1>
5068 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5070 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
5072 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
5073 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
5074 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
5075 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
5076 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
5077 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
5078 def : St1Lane128Pat<store, VectorIndexH, v8f16, f16, ST1i16>;
5080 let AddedComplexity = 19 in
5081 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
5082 ValueType VTy, ValueType STy, Instruction ST1>
5084 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5086 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5087 VecIndex:$idx, GPR64sp:$Rn)>;
5089 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
5090 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
5091 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
5092 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
5093 def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>;
5095 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
5096 ValueType VTy, ValueType STy, Instruction ST1,
5098 def : Pat<(scalar_store
5099 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5100 GPR64sp:$Rn, offset),
5101 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5102 VecIndex:$idx, GPR64sp:$Rn, XZR)>;
5104 def : Pat<(scalar_store
5105 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
5106 GPR64sp:$Rn, GPR64:$Rm),
5107 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
5108 VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
5111 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
5112 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
5114 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
5115 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
5116 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
5117 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
5118 defm : St1LanePost64Pat<post_store, VectorIndexH, v4f16, f16, ST1i16_POST, 2>;
5120 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
5121 ValueType VTy, ValueType STy, Instruction ST1,
5123 def : Pat<(scalar_store
5124 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5125 GPR64sp:$Rn, offset),
5126 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
5128 def : Pat<(scalar_store
5129 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
5130 GPR64sp:$Rn, GPR64:$Rm),
5131 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
5134 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
5136 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
5138 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
5139 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
5140 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
5141 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
5142 defm : St1LanePost128Pat<post_store, VectorIndexH, v8f16, f16, ST1i16_POST, 2>;
5144 let mayStore = 1, hasSideEffects = 0 in {
5145 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
5146 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
5147 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
5148 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
5149 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
5150 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
5151 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
5152 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
5153 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
5154 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
5155 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
5156 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
5159 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
5160 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
5161 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
5162 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
5164 //----------------------------------------------------------------------------
5165 // Crypto extensions
5166 //----------------------------------------------------------------------------
5168 def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>;
5169 def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;
5170 def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>;
5171 def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
5173 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>;
5174 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>;
5175 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>;
5176 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>;
5177 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>;
5178 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>;
5179 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>;
5181 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>;
5182 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>;
5183 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>;
5185 //----------------------------------------------------------------------------
5187 //----------------------------------------------------------------------------
5188 // FIXME: Like for X86, these should go in their own separate .td file.
5190 // Any instruction that defines a 32-bit result leaves the high half of the
5191 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
5192 // be copying from a truncate. But any other 32-bit operation will zero-extend
5194 // FIXME: X86 also checks for CMOV here. Do we need something similar?
5195 def def32 : PatLeaf<(i32 GPR32:$src), [{
5196 return N->getOpcode() != ISD::TRUNCATE &&
5197 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
5198 N->getOpcode() != ISD::CopyFromReg;
5201 // In the case of a 32-bit def that is known to implicitly zero-extend,
5202 // we can use a SUBREG_TO_REG.
5203 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
5205 // For an anyext, we don't care what the high bits are, so we can perform an
5206 // INSERT_SUBREF into an IMPLICIT_DEF.
5207 def : Pat<(i64 (anyext GPR32:$src)),
5208 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
5210 // When we need to explicitly zero-extend, we use a 32-bit MOV instruction and
5211 // then assert the extension has happened.
5212 def : Pat<(i64 (zext GPR32:$src)),
5213 (SUBREG_TO_REG (i32 0), (ORRWrs WZR, GPR32:$src, 0), sub_32)>;
5215 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
5216 // containing super-reg.
5217 def : Pat<(i64 (sext GPR32:$src)),
5218 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
5219 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
5220 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
5221 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
5222 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
5223 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
5224 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
5225 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
5227 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
5228 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
5229 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
5230 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
5231 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5232 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
5234 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
5235 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
5236 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
5237 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
5238 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
5239 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
5241 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
5242 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
5243 (i64 (i64shift_a imm0_63:$imm)),
5244 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
5246 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
5247 // AddedComplexity for the following patterns since we want to match sext + sra
5248 // patterns before we attempt to match a single sra node.
5249 let AddedComplexity = 20 in {
5250 // We support all sext + sra combinations which preserve at least one bit of the
5251 // original value which is to be sign extended. E.g. we support shifts up to
5253 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
5254 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
5255 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
5256 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
5258 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
5259 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
5260 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
5261 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
5263 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
5264 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
5265 (i64 imm0_31:$imm), 31)>;
5266 } // AddedComplexity = 20
5268 // To truncate, we can simply extract from a subregister.
5269 def : Pat<(i32 (trunc GPR64sp:$src)),
5270 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
5272 // __builtin_trap() uses the BRK instruction on AArch64.
5273 def : Pat<(trap), (BRK 1)>;
5275 // Conversions within AdvSIMD types in the same register size are free.
5276 // But because we need a consistent lane ordering, in big endian many
5277 // conversions require one or more REV instructions.
5279 // Consider a simple memory load followed by a bitconvert then a store.
5281 // v1 = BITCAST v2i32 v0 to v4i16
5284 // In big endian mode every memory access has an implicit byte swap. LDR and
5285 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
5286 // is, they treat the vector as a sequence of elements to be byte-swapped.
5287 // The two pairs of instructions are fundamentally incompatible. We've decided
5288 // to use LD1/ST1 only to simplify compiler implementation.
5290 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
5291 // the original code sequence:
5293 // v1 = REV v2i32 (implicit)
5294 // v2 = BITCAST v2i32 v1 to v4i16
5295 // v3 = REV v4i16 v2 (implicit)
5298 // But this is now broken - the value stored is different to the value loaded
5299 // due to lane reordering. To fix this, on every BITCAST we must perform two
5302 // v1 = REV v2i32 (implicit)
5304 // v3 = BITCAST v2i32 v2 to v4i16
5306 // v5 = REV v4i16 v4 (implicit)
5309 // This means an extra two instructions, but actually in most cases the two REV
5310 // instructions can be combined into one. For example:
5311 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
5313 // There is also no 128-bit REV instruction. This must be synthesized with an
5316 // Most bitconverts require some sort of conversion. The only exceptions are:
5317 // a) Identity conversions - vNfX <-> vNiX
5318 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
5321 // Natural vector casts (64 bit)
5322 def : Pat<(v8i8 (AArch64NvCast (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5323 def : Pat<(v4i16 (AArch64NvCast (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5324 def : Pat<(v4f16 (AArch64NvCast (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5325 def : Pat<(v2i32 (AArch64NvCast (v2i32 FPR64:$src))), (v2i32 FPR64:$src)>;
5326 def : Pat<(v2f32 (AArch64NvCast (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5327 def : Pat<(v1i64 (AArch64NvCast (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5329 def : Pat<(v8i8 (AArch64NvCast (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5330 def : Pat<(v4i16 (AArch64NvCast (v4i16 FPR64:$src))), (v4i16 FPR64:$src)>;
5331 def : Pat<(v4f16 (AArch64NvCast (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5332 def : Pat<(v2i32 (AArch64NvCast (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5333 def : Pat<(v1i64 (AArch64NvCast (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5335 def : Pat<(v8i8 (AArch64NvCast (v8i8 FPR64:$src))), (v8i8 FPR64:$src)>;
5336 def : Pat<(v4i16 (AArch64NvCast (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5337 def : Pat<(v4f16 (AArch64NvCast (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5338 def : Pat<(v2i32 (AArch64NvCast (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5339 def : Pat<(v1i64 (AArch64NvCast (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5341 def : Pat<(v8i8 (AArch64NvCast (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5342 def : Pat<(v4i16 (AArch64NvCast (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5343 def : Pat<(v4f16 (AArch64NvCast (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5344 def : Pat<(v2i32 (AArch64NvCast (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5345 def : Pat<(v2f32 (AArch64NvCast (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5346 def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5347 def : Pat<(v1f64 (AArch64NvCast (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5349 def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5350 def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5351 def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5352 def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>;
5353 def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5355 // Natural vector casts (128 bit)
5356 def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5357 def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5358 def : Pat<(v8f16 (AArch64NvCast (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5359 def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>;
5360 def : Pat<(v4f32 (AArch64NvCast (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5361 def : Pat<(v2i64 (AArch64NvCast (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5362 def : Pat<(v2f64 (AArch64NvCast (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5364 def : Pat<(v16i8 (AArch64NvCast (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5365 def : Pat<(v8i16 (AArch64NvCast (v8i16 FPR128:$src))), (v8i16 FPR128:$src)>;
5366 def : Pat<(v8f16 (AArch64NvCast (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5367 def : Pat<(v4i32 (AArch64NvCast (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5368 def : Pat<(v2i64 (AArch64NvCast (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5369 def : Pat<(v4f32 (AArch64NvCast (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5370 def : Pat<(v2f64 (AArch64NvCast (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5372 def : Pat<(v16i8 (AArch64NvCast (v16i8 FPR128:$src))), (v16i8 FPR128:$src)>;
5373 def : Pat<(v8i16 (AArch64NvCast (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5374 def : Pat<(v8f16 (AArch64NvCast (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5375 def : Pat<(v4i32 (AArch64NvCast (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5376 def : Pat<(v2i64 (AArch64NvCast (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5377 def : Pat<(v4f32 (AArch64NvCast (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5378 def : Pat<(v2f64 (AArch64NvCast (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5380 def : Pat<(v16i8 (AArch64NvCast (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5381 def : Pat<(v8i16 (AArch64NvCast (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5382 def : Pat<(v8f16 (AArch64NvCast (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5383 def : Pat<(v4i32 (AArch64NvCast (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5384 def : Pat<(v2i64 (AArch64NvCast (v2i64 FPR128:$src))), (v2i64 FPR128:$src)>;
5385 def : Pat<(v4f32 (AArch64NvCast (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5386 def : Pat<(v2f64 (AArch64NvCast (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5388 def : Pat<(v16i8 (AArch64NvCast (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5389 def : Pat<(v8i16 (AArch64NvCast (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5390 def : Pat<(v4i32 (AArch64NvCast (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5391 def : Pat<(v4f32 (AArch64NvCast (v4f32 FPR128:$src))), (v4f32 FPR128:$src)>;
5392 def : Pat<(v2i64 (AArch64NvCast (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5393 def : Pat<(v8f16 (AArch64NvCast (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
5394 def : Pat<(v2f64 (AArch64NvCast (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5396 def : Pat<(v16i8 (AArch64NvCast (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5397 def : Pat<(v8i16 (AArch64NvCast (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5398 def : Pat<(v4i32 (AArch64NvCast (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5399 def : Pat<(v2i64 (AArch64NvCast (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5400 def : Pat<(v2f64 (AArch64NvCast (v2f64 FPR128:$src))), (v2f64 FPR128:$src)>;
5401 def : Pat<(v8f16 (AArch64NvCast (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
5402 def : Pat<(v4f32 (AArch64NvCast (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5404 let Predicates = [IsLE] in {
5405 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5406 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5407 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5408 def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5409 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5411 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5412 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5413 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5414 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5415 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5416 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5417 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5418 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5419 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5420 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5421 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5422 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5424 let Predicates = [IsBE] in {
5425 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
5426 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5427 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
5428 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5429 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
5430 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5431 def : Pat<(v4f16 (bitconvert GPR64:$Xn)),
5432 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5433 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
5434 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5436 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5437 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5438 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5439 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5440 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5441 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5442 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5443 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5444 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5445 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5447 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5448 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5449 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
5450 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5451 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
5452 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5453 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
5454 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5455 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
5457 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
5458 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
5459 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
5460 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
5461 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
5462 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5463 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
5464 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
5465 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5466 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5468 let Predicates = [IsLE] in {
5469 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5470 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5471 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5472 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>;
5473 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5475 let Predicates = [IsBE] in {
5476 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
5477 (v1i64 (REV64v2i32 FPR64:$src))>;
5478 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
5479 (v1i64 (REV64v4i16 FPR64:$src))>;
5480 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
5481 (v1i64 (REV64v8i8 FPR64:$src))>;
5482 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))),
5483 (v1i64 (REV64v4i16 FPR64:$src))>;
5484 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
5485 (v1i64 (REV64v2i32 FPR64:$src))>;
5487 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5488 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5490 let Predicates = [IsLE] in {
5491 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
5492 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5493 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5494 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5495 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5496 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 FPR64:$src)>;
5498 let Predicates = [IsBE] in {
5499 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
5500 (v2i32 (REV64v2i32 FPR64:$src))>;
5501 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
5502 (v2i32 (REV32v4i16 FPR64:$src))>;
5503 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
5504 (v2i32 (REV32v8i8 FPR64:$src))>;
5505 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
5506 (v2i32 (REV64v2i32 FPR64:$src))>;
5507 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
5508 (v2i32 (REV64v2i32 FPR64:$src))>;
5509 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))),
5510 (v2i32 (REV64v4i16 FPR64:$src))>;
5512 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5514 let Predicates = [IsLE] in {
5515 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
5516 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5517 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5518 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5519 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))), (v4i16 FPR64:$src)>;
5520 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5521 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5523 let Predicates = [IsBE] in {
5524 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
5525 (v4i16 (REV64v4i16 FPR64:$src))>;
5526 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
5527 (v4i16 (REV32v4i16 FPR64:$src))>;
5528 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
5529 (v4i16 (REV16v8i8 FPR64:$src))>;
5530 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
5531 (v4i16 (REV64v4i16 FPR64:$src))>;
5532 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))),
5533 (v4i16 (REV32v4i16 FPR64:$src))>;
5534 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
5535 (v4i16 (REV32v4i16 FPR64:$src))>;
5536 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
5537 (v4i16 (REV64v4i16 FPR64:$src))>;
5540 let Predicates = [IsLE] in {
5541 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 FPR64:$src)>;
5542 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5543 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5544 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5545 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5546 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 FPR64:$src)>;
5547 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5549 let Predicates = [IsBE] in {
5550 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))),
5551 (v4f16 (REV64v4i16 FPR64:$src))>;
5552 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))),
5553 (v4f16 (REV64v4i16 FPR64:$src))>;
5554 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))),
5555 (v4f16 (REV64v4i16 FPR64:$src))>;
5556 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))),
5557 (v4f16 (REV16v8i8 FPR64:$src))>;
5558 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))),
5559 (v4f16 (REV64v4i16 FPR64:$src))>;
5560 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))),
5561 (v4f16 (REV64v4i16 FPR64:$src))>;
5562 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))),
5563 (v4f16 (REV64v4i16 FPR64:$src))>;
5568 let Predicates = [IsLE] in {
5569 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
5570 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5571 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5572 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5573 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5574 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5575 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 FPR64:$src)>;
5577 let Predicates = [IsBE] in {
5578 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
5579 (v8i8 (REV64v8i8 FPR64:$src))>;
5580 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
5581 (v8i8 (REV32v8i8 FPR64:$src))>;
5582 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
5583 (v8i8 (REV16v8i8 FPR64:$src))>;
5584 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
5585 (v8i8 (REV64v8i8 FPR64:$src))>;
5586 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
5587 (v8i8 (REV32v8i8 FPR64:$src))>;
5588 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
5589 (v8i8 (REV64v8i8 FPR64:$src))>;
5590 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))),
5591 (v8i8 (REV16v8i8 FPR64:$src))>;
5594 let Predicates = [IsLE] in {
5595 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
5596 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
5597 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
5598 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
5599 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 FPR64:$src)>;
5601 let Predicates = [IsBE] in {
5602 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
5603 (f64 (REV64v2i32 FPR64:$src))>;
5604 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
5605 (f64 (REV64v4i16 FPR64:$src))>;
5606 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
5607 (f64 (REV64v2i32 FPR64:$src))>;
5608 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
5609 (f64 (REV64v8i8 FPR64:$src))>;
5610 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))),
5611 (f64 (REV64v4i16 FPR64:$src))>;
5613 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
5614 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
5616 let Predicates = [IsLE] in {
5617 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
5618 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
5619 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
5620 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
5621 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 FPR64:$src)>;
5623 let Predicates = [IsBE] in {
5624 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
5625 (v1f64 (REV64v2i32 FPR64:$src))>;
5626 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
5627 (v1f64 (REV64v4i16 FPR64:$src))>;
5628 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
5629 (v1f64 (REV64v8i8 FPR64:$src))>;
5630 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
5631 (v1f64 (REV64v2i32 FPR64:$src))>;
5632 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))),
5633 (v1f64 (REV64v4i16 FPR64:$src))>;
5635 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
5636 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5638 let Predicates = [IsLE] in {
5639 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
5640 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
5641 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
5642 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5643 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5644 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 FPR64:$src)>;
5646 let Predicates = [IsBE] in {
5647 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
5648 (v2f32 (REV64v2i32 FPR64:$src))>;
5649 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
5650 (v2f32 (REV32v4i16 FPR64:$src))>;
5651 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
5652 (v2f32 (REV32v8i8 FPR64:$src))>;
5653 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
5654 (v2f32 (REV64v2i32 FPR64:$src))>;
5655 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
5656 (v2f32 (REV64v2i32 FPR64:$src))>;
5657 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))),
5658 (v2f32 (REV64v4i16 FPR64:$src))>;
5660 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5662 let Predicates = [IsLE] in {
5663 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
5664 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
5665 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
5666 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
5667 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
5668 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 FPR128:$src)>;
5669 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
5671 let Predicates = [IsBE] in {
5672 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
5673 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5674 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
5675 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5676 (REV64v4i32 FPR128:$src), (i32 8)))>;
5677 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
5678 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5679 (REV64v8i16 FPR128:$src), (i32 8)))>;
5680 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))),
5681 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5682 (REV64v8i16 FPR128:$src), (i32 8)))>;
5683 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
5684 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5685 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
5686 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5687 (REV64v4i32 FPR128:$src), (i32 8)))>;
5688 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
5689 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
5690 (REV64v16i8 FPR128:$src), (i32 8)))>;
5693 let Predicates = [IsLE] in {
5694 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
5695 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5696 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5697 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 FPR128:$src)>;
5698 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5699 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5701 let Predicates = [IsBE] in {
5702 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
5703 (v2f64 (EXTv16i8 FPR128:$src,
5704 FPR128:$src, (i32 8)))>;
5705 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
5706 (v2f64 (REV64v4i32 FPR128:$src))>;
5707 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
5708 (v2f64 (REV64v8i16 FPR128:$src))>;
5709 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))),
5710 (v2f64 (REV64v8i16 FPR128:$src))>;
5711 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
5712 (v2f64 (REV64v16i8 FPR128:$src))>;
5713 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
5714 (v2f64 (REV64v4i32 FPR128:$src))>;
5716 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5718 let Predicates = [IsLE] in {
5719 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
5720 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5721 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 FPR128:$src)>;
5722 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5723 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5724 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5726 let Predicates = [IsBE] in {
5727 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
5728 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5729 (REV64v4i32 FPR128:$src), (i32 8)))>;
5730 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
5731 (v4f32 (REV32v8i16 FPR128:$src))>;
5732 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))),
5733 (v4f32 (REV32v8i16 FPR128:$src))>;
5734 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
5735 (v4f32 (REV32v16i8 FPR128:$src))>;
5736 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
5737 (v4f32 (REV64v4i32 FPR128:$src))>;
5738 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
5739 (v4f32 (REV64v4i32 FPR128:$src))>;
5741 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5743 let Predicates = [IsLE] in {
5744 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5745 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5746 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5747 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5748 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5749 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 FPR128:$src)>;
5751 let Predicates = [IsBE] in {
5752 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
5753 (v2i64 (EXTv16i8 FPR128:$src,
5754 FPR128:$src, (i32 8)))>;
5755 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
5756 (v2i64 (REV64v4i32 FPR128:$src))>;
5757 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
5758 (v2i64 (REV64v8i16 FPR128:$src))>;
5759 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
5760 (v2i64 (REV64v16i8 FPR128:$src))>;
5761 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
5762 (v2i64 (REV64v4i32 FPR128:$src))>;
5763 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))),
5764 (v2i64 (REV64v8i16 FPR128:$src))>;
5766 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5768 let Predicates = [IsLE] in {
5769 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5770 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5771 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5772 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5773 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5774 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>;
5776 let Predicates = [IsBE] in {
5777 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
5778 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5779 (REV64v4i32 FPR128:$src),
5781 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
5782 (v4i32 (REV64v4i32 FPR128:$src))>;
5783 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
5784 (v4i32 (REV32v8i16 FPR128:$src))>;
5785 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
5786 (v4i32 (REV32v16i8 FPR128:$src))>;
5787 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
5788 (v4i32 (REV64v4i32 FPR128:$src))>;
5789 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))),
5790 (v4i32 (REV32v8i16 FPR128:$src))>;
5792 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5794 let Predicates = [IsLE] in {
5795 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5796 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5797 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5798 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5799 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5800 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5801 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))), (v8i16 FPR128:$src)>;
5803 let Predicates = [IsBE] in {
5804 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
5805 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5806 (REV64v8i16 FPR128:$src),
5808 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
5809 (v8i16 (REV64v8i16 FPR128:$src))>;
5810 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
5811 (v8i16 (REV32v8i16 FPR128:$src))>;
5812 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
5813 (v8i16 (REV16v16i8 FPR128:$src))>;
5814 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
5815 (v8i16 (REV64v8i16 FPR128:$src))>;
5816 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
5817 (v8i16 (REV32v8i16 FPR128:$src))>;
5818 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))),
5819 (v8i16 (REV32v8i16 FPR128:$src))>;
5822 let Predicates = [IsLE] in {
5823 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 FPR128:$src)>;
5824 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5825 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5826 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5827 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5828 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
5829 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
5831 let Predicates = [IsBE] in {
5832 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))),
5833 (v8f16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5834 (REV64v8i16 FPR128:$src),
5836 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))),
5837 (v8f16 (REV64v8i16 FPR128:$src))>;
5838 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))),
5839 (v8f16 (REV32v8i16 FPR128:$src))>;
5840 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))),
5841 (v8f16 (REV64v8i16 FPR128:$src))>;
5842 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))),
5843 (v8f16 (REV16v16i8 FPR128:$src))>;
5844 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))),
5845 (v8f16 (REV64v8i16 FPR128:$src))>;
5846 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))),
5847 (v8f16 (REV32v8i16 FPR128:$src))>;
5850 let Predicates = [IsLE] in {
5851 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5852 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5853 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5854 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5855 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5856 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5857 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 FPR128:$src)>;
5859 let Predicates = [IsBE] in {
5860 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
5861 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
5862 (REV64v16i8 FPR128:$src),
5864 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
5865 (v16i8 (REV64v16i8 FPR128:$src))>;
5866 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
5867 (v16i8 (REV32v16i8 FPR128:$src))>;
5868 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
5869 (v16i8 (REV16v16i8 FPR128:$src))>;
5870 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
5871 (v16i8 (REV64v16i8 FPR128:$src))>;
5872 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
5873 (v16i8 (REV32v16i8 FPR128:$src))>;
5874 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))),
5875 (v16i8 (REV16v16i8 FPR128:$src))>;
5878 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 0))),
5879 (EXTRACT_SUBREG V128:$Rn, dsub)>;
5880 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 0))),
5881 (EXTRACT_SUBREG V128:$Rn, dsub)>;
5882 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 0))),
5883 (EXTRACT_SUBREG V128:$Rn, dsub)>;
5884 def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 0))),
5885 (EXTRACT_SUBREG V128:$Rn, dsub)>;
5886 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 0))),
5887 (EXTRACT_SUBREG V128:$Rn, dsub)>;
5888 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 0))),
5889 (EXTRACT_SUBREG V128:$Rn, dsub)>;
5890 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 0))),
5891 (EXTRACT_SUBREG V128:$Rn, dsub)>;
5893 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
5894 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5895 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
5896 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5897 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
5898 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5899 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
5900 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5902 // A 64-bit subvector insert to the first 128-bit vector position
5903 // is a subregister copy that needs no instruction.
5904 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
5905 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5906 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
5907 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5908 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
5909 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5910 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
5911 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5912 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
5913 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5914 def : Pat<(insert_subvector undef, (v4f16 FPR64:$src), (i32 0)),
5915 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5916 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
5917 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5919 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
5921 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
5922 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
5923 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
5924 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
5925 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
5926 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
5927 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
5928 // so we match on v4f32 here, not v2f32. This will also catch adding
5929 // the low two lanes of a true v4f32 vector.
5930 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
5931 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
5932 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
5934 // Scalar 64-bit shifts in FPR64 registers.
5935 def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5936 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5937 def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5938 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5939 def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5940 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5941 def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5942 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5944 // Patterns for nontemporal/no-allocate stores.
5945 // We have to resort to tricks to turn a single-input store into a store pair,
5946 // because there is no single-input nontemporal store, only STNP.
5947 let Predicates = [IsLE] in {
5948 let AddedComplexity = 15 in {
5949 class NTStore128Pat<ValueType VT> :
5950 Pat<(nontemporalstore (VT FPR128:$Rt),
5951 (am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)),
5952 (STNPDi (EXTRACT_SUBREG FPR128:$Rt, dsub),
5953 (CPYi64 FPR128:$Rt, (i64 1)),
5954 GPR64sp:$Rn, simm7s8:$offset)>;
5956 def : NTStore128Pat<v2i64>;
5957 def : NTStore128Pat<v4i32>;
5958 def : NTStore128Pat<v8i16>;
5959 def : NTStore128Pat<v16i8>;
5961 class NTStore64Pat<ValueType VT> :
5962 Pat<(nontemporalstore (VT FPR64:$Rt),
5963 (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)),
5964 (STNPSi (EXTRACT_SUBREG FPR64:$Rt, ssub),
5965 (CPYi32 (SUBREG_TO_REG (i64 0), FPR64:$Rt, dsub), (i64 1)),
5966 GPR64sp:$Rn, simm7s4:$offset)>;
5968 // FIXME: Shouldn't v1f64 loads/stores be promoted to v1i64?
5969 def : NTStore64Pat<v1f64>;
5970 def : NTStore64Pat<v1i64>;
5971 def : NTStore64Pat<v2i32>;
5972 def : NTStore64Pat<v4i16>;
5973 def : NTStore64Pat<v8i8>;
5975 def : Pat<(nontemporalstore GPR64:$Rt,
5976 (am_indexed7s32 GPR64sp:$Rn, simm7s4:$offset)),
5977 (STNPWi (EXTRACT_SUBREG GPR64:$Rt, sub_32),
5978 (EXTRACT_SUBREG (UBFMXri GPR64:$Rt, 0, 31), sub_32),
5979 GPR64sp:$Rn, simm7s4:$offset)>;
5980 } // AddedComplexity=10
5981 } // Predicates = [IsLE]
5983 // Tail call return handling. These are all compiler pseudo-instructions,
5984 // so no encoding information or anything like that.
5985 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
5986 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff),[]>;
5987 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>;
5990 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
5991 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
5992 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
5993 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5994 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
5995 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5997 include "AArch64InstrAtomics.td"