1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // AArch64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
18 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
19 def HasNEON : Predicate<"Subtarget->hasNEON()">,
20 AssemblerPredicate<"FeatureNEON", "neon">;
21 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
22 AssemblerPredicate<"FeatureCrypto", "crypto">;
23 def HasCRC : Predicate<"Subtarget->hasCRC()">,
24 AssemblerPredicate<"FeatureCRC", "crc">;
25 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
26 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
28 //===----------------------------------------------------------------------===//
29 // AArch64-specific DAG Nodes.
32 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
33 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
36 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
39 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
45 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
46 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
53 def SDT_AArch64Brcond : SDTypeProfile<0, 3,
54 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
56 def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
57 def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
58 SDTCisVT<2, OtherVT>]>;
61 def SDT_AArch64CSel : SDTypeProfile<1, 4,
66 def SDT_AArch64FCmp : SDTypeProfile<0, 2,
69 def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
70 def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
71 def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
74 def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
75 def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
76 def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
77 SDTCisInt<2>, SDTCisInt<3>]>;
78 def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
79 def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
80 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
81 def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
83 def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
84 def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>;
85 def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
86 def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
88 def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
91 def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
92 def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
94 def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
96 def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
98 def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
99 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
100 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
101 SDTCisSameAs<1, 4>]>;
105 def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
106 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
107 def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
108 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
109 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
110 [SDNPHasChain, SDNPOutGlue]>;
111 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",
112 SDCallSeqEnd<[ SDTCisVT<0, i32>,
114 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
115 def AArch64call : SDNode<"AArch64ISD::CALL",
116 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
117 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond,
121 def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,
123 def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz,
125 def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz,
127 def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz,
131 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
132 def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>;
133 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;
134 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
135 def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone,
136 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
137 def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >;
138 def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>;
139 def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut,
141 def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
142 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
144 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
145 def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
147 def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
149 def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
151 def AArch64fmax : SDNode<"AArch64ISD::FMAX", SDTFPBinOp>;
152 def AArch64fmin : SDNode<"AArch64ISD::FMIN", SDTFPBinOp>;
154 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;
155 def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;
156 def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;
157 def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>;
158 def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>;
160 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
161 def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>;
162 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
163 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;
164 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;
165 def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>;
167 def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>;
168 def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>;
169 def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>;
170 def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>;
171 def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;
172 def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;
173 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;
175 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
176 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
177 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
178 def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;
180 def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;
181 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;
182 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;
183 def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>;
184 def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>;
185 def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>;
186 def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>;
187 def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>;
189 def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>;
190 def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>;
191 def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>;
193 def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
194 def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>;
195 def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>;
196 def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>;
197 def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>;
199 def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;
200 def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>;
201 def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>;
203 def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>;
204 def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>;
205 def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>;
206 def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>;
207 def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>;
208 def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
209 (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
211 def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>;
212 def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>;
213 def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>;
214 def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>;
215 def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>;
217 def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>;
218 def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>;
220 def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>;
222 def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET,
223 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
225 def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH,
226 [SDNPHasChain, SDNPSideEffect]>;
228 def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>;
229 def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;
231 def AArch64tlsdesc_call : SDNode<"AArch64ISD::TLSDESC_CALL",
232 SDT_AArch64TLSDescCall,
233 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
236 def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
237 SDT_AArch64WrapperLarge>;
240 //===----------------------------------------------------------------------===//
242 //===----------------------------------------------------------------------===//
244 // AArch64 Instruction Predicate Definitions.
246 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
247 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
248 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
249 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
250 def ForCodeSize : Predicate<"ForCodeSize">;
251 def NotForCodeSize : Predicate<"!ForCodeSize">;
253 include "AArch64InstrFormats.td"
255 //===----------------------------------------------------------------------===//
257 //===----------------------------------------------------------------------===//
258 // Miscellaneous instructions.
259 //===----------------------------------------------------------------------===//
261 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
262 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
263 [(AArch64callseq_start timm:$amt)]>;
264 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
265 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
266 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
268 let isReMaterializable = 1, isCodeGenOnly = 1 in {
269 // FIXME: The following pseudo instructions are only needed because remat
270 // cannot handle multiple instructions. When that changes, they can be
271 // removed, along with the AArch64Wrapper node.
273 let AddedComplexity = 10 in
274 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
275 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
278 // The MOVaddr instruction should match only when the add is not folded
279 // into a load or store address.
281 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
282 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
283 tglobaladdr:$low))]>,
284 Sched<[WriteAdrAdr]>;
286 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
287 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
289 Sched<[WriteAdrAdr]>;
291 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
292 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
294 Sched<[WriteAdrAdr]>;
296 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
297 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
298 tblockaddress:$low))]>,
299 Sched<[WriteAdrAdr]>;
301 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
302 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),
303 tglobaltlsaddr:$low))]>,
304 Sched<[WriteAdrAdr]>;
306 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
307 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),
308 texternalsym:$low))]>,
309 Sched<[WriteAdrAdr]>;
311 } // isReMaterializable, isCodeGenOnly
313 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
314 (LOADgot tglobaltlsaddr:$addr)>;
316 def : Pat<(AArch64LOADgot texternalsym:$addr),
317 (LOADgot texternalsym:$addr)>;
319 def : Pat<(AArch64LOADgot tconstpool:$addr),
320 (LOADgot tconstpool:$addr)>;
322 //===----------------------------------------------------------------------===//
323 // System instructions.
324 //===----------------------------------------------------------------------===//
326 def HINT : HintI<"hint">;
327 def : InstAlias<"nop", (HINT 0b000)>;
328 def : InstAlias<"yield",(HINT 0b001)>;
329 def : InstAlias<"wfe", (HINT 0b010)>;
330 def : InstAlias<"wfi", (HINT 0b011)>;
331 def : InstAlias<"sev", (HINT 0b100)>;
332 def : InstAlias<"sevl", (HINT 0b101)>;
334 // As far as LLVM is concerned this writes to the system's exclusive monitors.
335 let mayLoad = 1, mayStore = 1 in
336 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
338 def DMB : CRmSystemI<barrier_op, 0b101, "dmb">;
339 def DSB : CRmSystemI<barrier_op, 0b100, "dsb">;
340 def ISB : CRmSystemI<barrier_op, 0b110, "isb">;
341 def : InstAlias<"clrex", (CLREX 0xf)>;
342 def : InstAlias<"isb", (ISB 0xf)>;
346 def MSRpstate: MSRpstateI;
348 // The thread pointer (on Linux, at least, where this has been implemented) is
350 def : Pat<(AArch64threadpointer), (MRS 0xde82)>;
352 // Generic system instructions
353 def SYSxt : SystemXtI<0, "sys">;
354 def SYSLxt : SystemLXtI<1, "sysl">;
356 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
357 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
358 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
360 //===----------------------------------------------------------------------===//
361 // Move immediate instructions.
362 //===----------------------------------------------------------------------===//
364 defm MOVK : InsertImmediate<0b11, "movk">;
365 defm MOVN : MoveImmediate<0b00, "movn">;
367 let PostEncoderMethod = "fixMOVZ" in
368 defm MOVZ : MoveImmediate<0b10, "movz">;
370 // First group of aliases covers an implicit "lsl #0".
371 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
372 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
373 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
374 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
375 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
376 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
378 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
379 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
380 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
381 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
382 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
384 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
385 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
386 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
387 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
389 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
390 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
391 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
392 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
394 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
395 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
397 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
398 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
400 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
401 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
403 // Final group of aliases covers true "mov $Rd, $imm" cases.
404 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
405 int width, int shift> {
406 def _asmoperand : AsmOperandClass {
407 let Name = basename # width # "_lsl" # shift # "MovAlias";
408 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
410 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
413 def _movimm : Operand<i32> {
414 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
417 def : InstAlias<"mov $Rd, $imm",
418 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
421 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
422 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
424 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
425 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
426 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
427 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
429 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
430 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
432 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
433 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
434 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
435 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
437 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
438 isAsCheapAsAMove = 1 in {
439 // FIXME: The following pseudo instructions are only needed because remat
440 // cannot handle multiple instructions. When that changes, we can select
441 // directly to the real instructions and get rid of these pseudos.
444 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
445 [(set GPR32:$dst, imm:$src)]>,
448 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
449 [(set GPR64:$dst, imm:$src)]>,
451 } // isReMaterializable, isCodeGenOnly
453 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
454 // eventual expansion code fewer bits to worry about getting right. Marshalling
455 // the types is a little tricky though:
456 def i64imm_32bit : ImmLeaf<i64, [{
457 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
460 def trunc_imm : SDNodeXForm<imm, [{
461 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i32);
464 def : Pat<(i64 i64imm_32bit:$src),
465 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
467 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
469 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
470 tglobaladdr:$g1, tglobaladdr:$g0),
471 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
472 tglobaladdr:$g2, 32),
473 tglobaladdr:$g1, 16),
474 tglobaladdr:$g0, 0)>;
476 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
477 tblockaddress:$g1, tblockaddress:$g0),
478 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
479 tblockaddress:$g2, 32),
480 tblockaddress:$g1, 16),
481 tblockaddress:$g0, 0)>;
483 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
484 tconstpool:$g1, tconstpool:$g0),
485 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
490 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
491 tjumptable:$g1, tjumptable:$g0),
492 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
498 //===----------------------------------------------------------------------===//
499 // Arithmetic instructions.
500 //===----------------------------------------------------------------------===//
502 // Add/subtract with carry.
503 defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>;
504 defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>;
506 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
507 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
508 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
509 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
512 defm ADD : AddSub<0, "add", add>;
513 defm SUB : AddSub<1, "sub">;
515 def : InstAlias<"mov $dst, $src",
516 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
517 def : InstAlias<"mov $dst, $src",
518 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
519 def : InstAlias<"mov $dst, $src",
520 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
521 def : InstAlias<"mov $dst, $src",
522 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
524 defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn">;
525 defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp">;
527 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
528 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
529 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
530 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
531 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
532 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
533 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
534 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
535 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
536 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
537 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
538 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
539 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
540 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
541 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
542 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
543 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
545 // Because of the immediate format for add/sub-imm instructions, the
546 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
547 // These patterns capture that transformation.
548 let AddedComplexity = 1 in {
549 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
550 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
551 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
552 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
553 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
554 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
555 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
556 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
559 // Because of the immediate format for add/sub-imm instructions, the
560 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
561 // These patterns capture that transformation.
562 let AddedComplexity = 1 in {
563 def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
564 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
565 def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
566 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
567 def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
568 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
569 def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
570 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
573 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
574 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
575 def : InstAlias<"neg $dst, $src$shift",
576 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
577 def : InstAlias<"neg $dst, $src$shift",
578 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
580 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
581 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
582 def : InstAlias<"negs $dst, $src$shift",
583 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
584 def : InstAlias<"negs $dst, $src$shift",
585 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
588 // Unsigned/Signed divide
589 defm UDIV : Div<0, "udiv", udiv>;
590 defm SDIV : Div<1, "sdiv", sdiv>;
591 let isCodeGenOnly = 1 in {
592 defm UDIV_Int : Div<0, "udiv", int_aarch64_udiv>;
593 defm SDIV_Int : Div<1, "sdiv", int_aarch64_sdiv>;
597 defm ASRV : Shift<0b10, "asr", sra>;
598 defm LSLV : Shift<0b00, "lsl", shl>;
599 defm LSRV : Shift<0b01, "lsr", srl>;
600 defm RORV : Shift<0b11, "ror", rotr>;
602 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
603 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
604 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
605 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
606 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
607 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
608 def : ShiftAlias<"rorv", RORVWr, GPR32>;
609 def : ShiftAlias<"rorv", RORVXr, GPR64>;
612 let AddedComplexity = 7 in {
613 defm MADD : MulAccum<0, "madd", add>;
614 defm MSUB : MulAccum<1, "msub", sub>;
616 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
617 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
618 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
619 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
621 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
622 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
623 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
624 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
625 } // AddedComplexity = 7
627 let AddedComplexity = 5 in {
628 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
629 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
630 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
631 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
633 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
634 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
635 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
636 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
638 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
639 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
640 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
641 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
642 } // AddedComplexity = 5
644 def : MulAccumWAlias<"mul", MADDWrrr>;
645 def : MulAccumXAlias<"mul", MADDXrrr>;
646 def : MulAccumWAlias<"mneg", MSUBWrrr>;
647 def : MulAccumXAlias<"mneg", MSUBXrrr>;
648 def : WideMulAccumAlias<"smull", SMADDLrrr>;
649 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
650 def : WideMulAccumAlias<"umull", UMADDLrrr>;
651 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
654 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
655 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
658 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
659 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
660 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">;
661 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
663 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
664 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
665 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">;
666 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
669 //===----------------------------------------------------------------------===//
670 // Logical instructions.
671 //===----------------------------------------------------------------------===//
674 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag>;
675 defm AND : LogicalImm<0b00, "and", and>;
676 defm EOR : LogicalImm<0b10, "eor", xor>;
677 defm ORR : LogicalImm<0b01, "orr", or>;
679 // FIXME: these aliases *are* canonical sometimes (when movz can't be
680 // used). Actually, it seems to be working right now, but putting logical_immXX
681 // here is a bit dodgy on the AsmParser side too.
682 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
683 logical_imm32:$imm), 0>;
684 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
685 logical_imm64:$imm), 0>;
689 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
690 defm BICS : LogicalRegS<0b11, 1, "bics",
691 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;
692 defm AND : LogicalReg<0b00, 0, "and", and>;
693 defm BIC : LogicalReg<0b00, 1, "bic",
694 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
695 defm EON : LogicalReg<0b10, 1, "eon",
696 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
697 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
698 defm ORN : LogicalReg<0b01, 1, "orn",
699 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
700 defm ORR : LogicalReg<0b01, 0, "orr", or>;
702 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
703 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
705 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
706 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
708 def : InstAlias<"mvn $Wd, $Wm$sh",
709 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
710 def : InstAlias<"mvn $Xd, $Xm$sh",
711 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
713 def : InstAlias<"tst $src1, $src2",
714 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
715 def : InstAlias<"tst $src1, $src2",
716 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
718 def : InstAlias<"tst $src1, $src2",
719 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
720 def : InstAlias<"tst $src1, $src2",
721 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
723 def : InstAlias<"tst $src1, $src2$sh",
724 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
725 def : InstAlias<"tst $src1, $src2$sh",
726 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
729 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
730 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
733 //===----------------------------------------------------------------------===//
734 // One operand data processing instructions.
735 //===----------------------------------------------------------------------===//
737 defm CLS : OneOperandData<0b101, "cls">;
738 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
739 defm RBIT : OneOperandData<0b000, "rbit">;
741 def : Pat<(int_aarch64_rbit GPR32:$Rn), (RBITWr $Rn)>;
742 def : Pat<(int_aarch64_rbit GPR64:$Rn), (RBITXr $Rn)>;
744 def REV16Wr : OneWRegData<0b001, "rev16",
745 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
746 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
748 def : Pat<(cttz GPR32:$Rn),
749 (CLZWr (RBITWr GPR32:$Rn))>;
750 def : Pat<(cttz GPR64:$Rn),
751 (CLZXr (RBITXr GPR64:$Rn))>;
752 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
755 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
759 // Unlike the other one operand instructions, the instructions with the "rev"
760 // mnemonic do *not* just different in the size bit, but actually use different
761 // opcode bits for the different sizes.
762 def REVWr : OneWRegData<0b010, "rev", bswap>;
763 def REVXr : OneXRegData<0b011, "rev", bswap>;
764 def REV32Xr : OneXRegData<0b010, "rev32",
765 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
767 // The bswap commutes with the rotr so we want a pattern for both possible
769 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
770 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
772 //===----------------------------------------------------------------------===//
773 // Bitfield immediate extraction instruction.
774 //===----------------------------------------------------------------------===//
775 let neverHasSideEffects = 1 in
776 defm EXTR : ExtractImm<"extr">;
777 def : InstAlias<"ror $dst, $src, $shift",
778 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
779 def : InstAlias<"ror $dst, $src, $shift",
780 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
782 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
783 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
784 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
785 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
787 //===----------------------------------------------------------------------===//
788 // Other bitfield immediate instructions.
789 //===----------------------------------------------------------------------===//
790 let neverHasSideEffects = 1 in {
791 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
792 defm SBFM : BitfieldImm<0b00, "sbfm">;
793 defm UBFM : BitfieldImm<0b10, "ubfm">;
796 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
797 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
798 return CurDAG->getTargetConstant(enc, MVT::i64);
801 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
802 uint64_t enc = 31 - N->getZExtValue();
803 return CurDAG->getTargetConstant(enc, MVT::i64);
806 // min(7, 31 - shift_amt)
807 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
808 uint64_t enc = 31 - N->getZExtValue();
809 enc = enc > 7 ? 7 : enc;
810 return CurDAG->getTargetConstant(enc, MVT::i64);
813 // min(15, 31 - shift_amt)
814 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
815 uint64_t enc = 31 - N->getZExtValue();
816 enc = enc > 15 ? 15 : enc;
817 return CurDAG->getTargetConstant(enc, MVT::i64);
820 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
821 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
822 return CurDAG->getTargetConstant(enc, MVT::i64);
825 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
826 uint64_t enc = 63 - N->getZExtValue();
827 return CurDAG->getTargetConstant(enc, MVT::i64);
830 // min(7, 63 - shift_amt)
831 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
832 uint64_t enc = 63 - N->getZExtValue();
833 enc = enc > 7 ? 7 : enc;
834 return CurDAG->getTargetConstant(enc, MVT::i64);
837 // min(15, 63 - shift_amt)
838 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
839 uint64_t enc = 63 - N->getZExtValue();
840 enc = enc > 15 ? 15 : enc;
841 return CurDAG->getTargetConstant(enc, MVT::i64);
844 // min(31, 63 - shift_amt)
845 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
846 uint64_t enc = 63 - N->getZExtValue();
847 enc = enc > 31 ? 31 : enc;
848 return CurDAG->getTargetConstant(enc, MVT::i64);
851 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
852 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
853 (i64 (i32shift_b imm0_31:$imm)))>;
854 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
855 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
856 (i64 (i64shift_b imm0_63:$imm)))>;
858 let AddedComplexity = 10 in {
859 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
860 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
861 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
862 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
865 def : InstAlias<"asr $dst, $src, $shift",
866 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
867 def : InstAlias<"asr $dst, $src, $shift",
868 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
869 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
870 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
871 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
872 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
873 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
875 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
876 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
877 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
878 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
880 def : InstAlias<"lsr $dst, $src, $shift",
881 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
882 def : InstAlias<"lsr $dst, $src, $shift",
883 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
884 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
885 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
886 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
887 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
888 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
890 //===----------------------------------------------------------------------===//
891 // Conditionally set flags instructions.
892 //===----------------------------------------------------------------------===//
893 defm CCMN : CondSetFlagsImm<0, "ccmn">;
894 defm CCMP : CondSetFlagsImm<1, "ccmp">;
896 defm CCMN : CondSetFlagsReg<0, "ccmn">;
897 defm CCMP : CondSetFlagsReg<1, "ccmp">;
899 //===----------------------------------------------------------------------===//
900 // Conditional select instructions.
901 //===----------------------------------------------------------------------===//
902 defm CSEL : CondSelect<0, 0b00, "csel">;
904 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
905 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
906 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
907 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
909 def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
910 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
911 def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
912 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
913 def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
914 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
915 def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
916 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
917 def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
918 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
919 def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
920 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
922 def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
923 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
924 def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
925 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
926 def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
927 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
928 def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
929 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
931 // The inverse of the condition code from the alias instruction is what is used
932 // in the aliased instruction. The parser all ready inverts the condition code
933 // for these aliases.
934 def : InstAlias<"cset $dst, $cc",
935 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
936 def : InstAlias<"cset $dst, $cc",
937 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
939 def : InstAlias<"csetm $dst, $cc",
940 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
941 def : InstAlias<"csetm $dst, $cc",
942 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
944 def : InstAlias<"cinc $dst, $src, $cc",
945 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
946 def : InstAlias<"cinc $dst, $src, $cc",
947 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
949 def : InstAlias<"cinv $dst, $src, $cc",
950 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
951 def : InstAlias<"cinv $dst, $src, $cc",
952 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
954 def : InstAlias<"cneg $dst, $src, $cc",
955 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
956 def : InstAlias<"cneg $dst, $src, $cc",
957 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
959 //===----------------------------------------------------------------------===//
960 // PC-relative instructions.
961 //===----------------------------------------------------------------------===//
962 let isReMaterializable = 1 in {
963 let neverHasSideEffects = 1, mayStore = 0, mayLoad = 0 in {
964 def ADR : ADRI<0, "adr", adrlabel, []>;
965 } // neverHasSideEffects = 1
967 def ADRP : ADRI<1, "adrp", adrplabel,
968 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;
969 } // isReMaterializable = 1
971 // page address of a constant pool entry, block address
972 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
973 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
975 //===----------------------------------------------------------------------===//
976 // Unconditional branch (register) instructions.
977 //===----------------------------------------------------------------------===//
979 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
980 def RET : BranchReg<0b0010, "ret", []>;
981 def DRPS : SpecialReturn<0b0101, "drps">;
982 def ERET : SpecialReturn<0b0100, "eret">;
983 } // isReturn = 1, isTerminator = 1, isBarrier = 1
985 // Default to the LR register.
986 def : InstAlias<"ret", (RET LR)>;
988 let isCall = 1, Defs = [LR], Uses = [SP] in {
989 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
992 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
993 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
994 } // isBranch, isTerminator, isBarrier, isIndirectBranch
996 // Create a separate pseudo-instruction for codegen to use so that we don't
997 // flag lr as used in every function. It'll be restored before the RET by the
998 // epilogue if it's legitimately used.
999 def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]> {
1000 let isTerminator = 1;
1005 // This is a directive-like pseudo-instruction. The purpose is to insert an
1006 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
1007 // (which in the usual case is a BLR).
1008 let hasSideEffects = 1 in
1009 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
1010 let AsmString = ".tlsdesccall $sym";
1013 // Pseudo-instruction representing a BLR with attached TLSDESC relocation. It
1014 // gets expanded to two MCInsts during lowering.
1015 let isCall = 1, Defs = [LR] in
1017 : Pseudo<(outs), (ins GPR64:$dest, i64imm:$sym),
1018 [(AArch64tlsdesc_call GPR64:$dest, tglobaltlsaddr:$sym)]>;
1020 def : Pat<(AArch64tlsdesc_call GPR64:$dest, texternalsym:$sym),
1021 (TLSDESC_BLR GPR64:$dest, texternalsym:$sym)>;
1022 //===----------------------------------------------------------------------===//
1023 // Conditional branch (immediate) instruction.
1024 //===----------------------------------------------------------------------===//
1025 def Bcc : BranchCond;
1027 //===----------------------------------------------------------------------===//
1028 // Compare-and-branch instructions.
1029 //===----------------------------------------------------------------------===//
1030 defm CBZ : CmpBranch<0, "cbz", AArch64cbz>;
1031 defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>;
1033 //===----------------------------------------------------------------------===//
1034 // Test-bit-and-branch instructions.
1035 //===----------------------------------------------------------------------===//
1036 defm TBZ : TestBranch<0, "tbz", AArch64tbz>;
1037 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;
1039 //===----------------------------------------------------------------------===//
1040 // Unconditional branch (immediate) instructions.
1041 //===----------------------------------------------------------------------===//
1042 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1043 def B : BranchImm<0, "b", [(br bb:$addr)]>;
1044 } // isBranch, isTerminator, isBarrier
1046 let isCall = 1, Defs = [LR], Uses = [SP] in {
1047 def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>;
1049 def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>;
1051 //===----------------------------------------------------------------------===//
1052 // Exception generation instructions.
1053 //===----------------------------------------------------------------------===//
1054 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1055 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1056 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
1057 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1058 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1059 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1060 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1061 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1063 // DCPSn defaults to an immediate operand of zero if unspecified.
1064 def : InstAlias<"dcps1", (DCPS1 0)>;
1065 def : InstAlias<"dcps2", (DCPS2 0)>;
1066 def : InstAlias<"dcps3", (DCPS3 0)>;
1068 //===----------------------------------------------------------------------===//
1069 // Load instructions.
1070 //===----------------------------------------------------------------------===//
1072 // Pair (indexed, offset)
1073 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1074 defm LDPX : LoadPairOffset<0b10, 0, GPR64, simm7s8, "ldp">;
1075 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1076 defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">;
1077 defm LDPQ : LoadPairOffset<0b10, 1, FPR128, simm7s16, "ldp">;
1079 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
1081 // Pair (pre-indexed)
1082 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1083 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1084 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1085 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1086 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1088 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1090 // Pair (post-indexed)
1091 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1092 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1093 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1094 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1095 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1097 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1100 // Pair (no allocate)
1101 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1102 defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64, simm7s8, "ldnp">;
1103 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1104 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">;
1105 defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128, simm7s16, "ldnp">;
1108 // (register offset)
1112 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1113 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;
1114 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
1115 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1118 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1119 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16, "ldr", f16, load>;
1120 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32, "ldr", f32, load>;
1121 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>;
1122 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1124 // Load sign-extended half-word
1125 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1126 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;
1128 // Load sign-extended byte
1129 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1130 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1132 // Load sign-extended word
1133 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;
1136 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
1138 // For regular load, we do not have any alignment requirement.
1139 // Thus, it is safe to directly map the vector loads with interesting
1140 // addressing modes.
1141 // FIXME: We could do the same for bitconvert to floating point vectors.
1142 multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop,
1143 ValueType ScalTy, ValueType VecTy,
1144 Instruction LOADW, Instruction LOADX,
1146 def : Pat<(VecTy (scalar_to_vector (ScalTy
1147 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))),
1148 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1149 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset),
1152 def : Pat<(VecTy (scalar_to_vector (ScalTy
1153 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))),
1154 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1155 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset),
1159 let AddedComplexity = 10 in {
1160 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>;
1161 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>;
1163 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1164 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1166 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
1167 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
1169 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
1170 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
1172 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
1174 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1177 def : Pat <(v1i64 (scalar_to_vector (i64
1178 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
1179 ro_Wextend64:$extend))))),
1180 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
1182 def : Pat <(v1i64 (scalar_to_vector (i64
1183 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
1184 ro_Xextend64:$extend))))),
1185 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
1188 // Match all load 64 bits width whose type is compatible with FPR64
1189 multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy,
1190 Instruction LOADW, Instruction LOADX> {
1192 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1193 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1195 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1196 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1199 let AddedComplexity = 10 in {
1200 let Predicates = [IsLE] in {
1201 // We must do vector loads with LD1 in big-endian.
1202 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;
1203 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
1204 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;
1205 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>;
1208 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
1209 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1211 // Match all load 128 bits width whose type is compatible with FPR128
1212 let Predicates = [IsLE] in {
1213 // We must do vector loads with LD1 in big-endian.
1214 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>;
1215 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
1216 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;
1217 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
1218 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;
1219 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;
1221 } // AddedComplexity = 10
1224 multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop,
1225 Instruction INSTW, Instruction INSTX> {
1226 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1227 (SUBREG_TO_REG (i64 0),
1228 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
1231 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1232 (SUBREG_TO_REG (i64 0),
1233 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
1237 let AddedComplexity = 10 in {
1238 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>;
1239 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>;
1240 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>;
1242 // zextloadi1 -> zextloadi8
1243 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1245 // extload -> zextload
1246 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1247 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1248 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1250 // extloadi1 -> zextloadi8
1251 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>;
1256 multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop,
1257 Instruction INSTW, Instruction INSTX> {
1258 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1259 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1261 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1262 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1266 let AddedComplexity = 10 in {
1267 // extload -> zextload
1268 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1269 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1270 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1272 // zextloadi1 -> zextloadi8
1273 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1277 // (unsigned immediate)
1279 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr",
1281 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1282 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32, uimm12s4, "ldr",
1284 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1285 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1287 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>;
1288 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16, uimm12s2, "ldr",
1289 [(set (f16 FPR16:$Rt),
1290 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>;
1291 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32, uimm12s4, "ldr",
1292 [(set (f32 FPR32:$Rt),
1293 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1294 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr",
1295 [(set (f64 FPR64:$Rt),
1296 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1297 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1298 [(set (f128 FPR128:$Rt),
1299 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>;
1301 // For regular load, we do not have any alignment requirement.
1302 // Thus, it is safe to directly map the vector loads with interesting
1303 // addressing modes.
1304 // FIXME: We could do the same for bitconvert to floating point vectors.
1305 def : Pat <(v8i8 (scalar_to_vector (i32
1306 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1307 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1308 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1309 def : Pat <(v16i8 (scalar_to_vector (i32
1310 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1311 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1312 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1313 def : Pat <(v4i16 (scalar_to_vector (i32
1314 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1315 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1316 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1317 def : Pat <(v8i16 (scalar_to_vector (i32
1318 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1319 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1320 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1321 def : Pat <(v2i32 (scalar_to_vector (i32
1322 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1323 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1324 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1325 def : Pat <(v4i32 (scalar_to_vector (i32
1326 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1327 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1328 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1329 def : Pat <(v1i64 (scalar_to_vector (i64
1330 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1331 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1332 def : Pat <(v2i64 (scalar_to_vector (i64
1333 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1334 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1335 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
1337 // Match all load 64 bits width whose type is compatible with FPR64
1338 let Predicates = [IsLE] in {
1339 // We must use LD1 to perform vector loads in big-endian.
1340 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1341 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1342 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1343 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1344 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1345 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1346 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1347 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1349 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1350 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1351 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1352 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1354 // Match all load 128 bits width whose type is compatible with FPR128
1355 let Predicates = [IsLE] in {
1356 // We must use LD1 to perform vector loads in big-endian.
1357 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1358 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1359 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1360 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1361 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1362 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1363 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1364 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1365 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1366 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1367 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1368 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1370 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1371 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1373 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
1375 (zextloadi16 (am_indexed16 GPR64sp:$Rn,
1376 uimm12s2:$offset)))]>;
1377 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1379 (zextloadi8 (am_indexed8 GPR64sp:$Rn,
1380 uimm12s1:$offset)))]>;
1382 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1383 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1384 def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1385 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1387 // zextloadi1 -> zextloadi8
1388 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1389 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1390 def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1391 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1393 // extload -> zextload
1394 def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1395 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
1396 def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1397 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1398 def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1399 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1400 def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1401 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1402 def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1403 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1404 def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1405 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1406 def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1407 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1409 // load sign-extended half-word
1410 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
1412 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1413 uimm12s2:$offset)))]>;
1414 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",
1416 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1417 uimm12s2:$offset)))]>;
1419 // load sign-extended byte
1420 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1422 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1423 uimm12s1:$offset)))]>;
1424 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1426 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1427 uimm12s1:$offset)))]>;
1429 // load sign-extended word
1430 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
1432 (sextloadi32 (am_indexed32 GPR64sp:$Rn,
1433 uimm12s4:$offset)))]>;
1435 // load zero-extended word
1436 def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1437 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1440 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1441 [(AArch64Prefetch imm:$Rt,
1442 (am_indexed64 GPR64sp:$Rn,
1443 uimm12s8:$offset))]>;
1445 def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>;
1449 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1450 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1451 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1452 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1453 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1455 // load sign-extended word
1456 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1459 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1460 // [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1463 // (unscaled immediate)
1464 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur",
1466 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1467 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32, "ldur",
1469 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1470 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1472 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1473 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16, "ldur",
1475 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1476 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32, "ldur",
1477 [(set (f32 FPR32:$Rt),
1478 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1479 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur",
1480 [(set (f64 FPR64:$Rt),
1481 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1482 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1483 [(set (f128 FPR128:$Rt),
1484 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;
1487 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
1489 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1491 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1493 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1495 // Match all load 64 bits width whose type is compatible with FPR64
1496 let Predicates = [IsLE] in {
1497 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1498 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1499 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1500 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1501 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1502 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1503 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1504 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1506 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1507 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1508 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1509 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1511 // Match all load 128 bits width whose type is compatible with FPR128
1512 let Predicates = [IsLE] in {
1513 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1514 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1515 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1516 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1517 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1518 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1519 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1520 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1521 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1522 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1523 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1524 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1528 def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1529 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1530 def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1531 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1532 def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1533 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1534 def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1535 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1536 def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1537 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1538 def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1539 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1540 def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1541 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1543 def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1544 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1545 def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1546 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1547 def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1548 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1549 def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1550 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1551 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1552 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1553 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1554 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1555 def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1556 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1560 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1562 // Define new assembler match classes as we want to only match these when
1563 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1564 // associate a DiagnosticType either, as we want the diagnostic for the
1565 // canonical form (the scaled operand) to take precedence.
1566 class SImm9OffsetOperand<int Width> : AsmOperandClass {
1567 let Name = "SImm9OffsetFB" # Width;
1568 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">";
1569 let RenderMethod = "addImmOperands";
1572 def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>;
1573 def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>;
1574 def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>;
1575 def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>;
1576 def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>;
1578 def simm9_offset_fb8 : Operand<i64> {
1579 let ParserMatchClass = SImm9OffsetFB8Operand;
1581 def simm9_offset_fb16 : Operand<i64> {
1582 let ParserMatchClass = SImm9OffsetFB16Operand;
1584 def simm9_offset_fb32 : Operand<i64> {
1585 let ParserMatchClass = SImm9OffsetFB32Operand;
1587 def simm9_offset_fb64 : Operand<i64> {
1588 let ParserMatchClass = SImm9OffsetFB64Operand;
1590 def simm9_offset_fb128 : Operand<i64> {
1591 let ParserMatchClass = SImm9OffsetFB128Operand;
1594 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1595 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1596 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1597 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1598 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1599 (LDURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1600 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1601 (LDURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1602 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1603 (LDURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1604 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1605 (LDURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1606 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1607 (LDURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
1610 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1611 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1612 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1613 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1615 // load sign-extended half-word
1617 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
1619 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1621 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",
1623 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1625 // load sign-extended byte
1627 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1629 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1631 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1633 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1635 // load sign-extended word
1637 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",
1639 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1641 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1642 def : InstAlias<"ldrb $Rt, [$Rn, $offset]",
1643 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1644 def : InstAlias<"ldrh $Rt, [$Rn, $offset]",
1645 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1646 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1647 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1648 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1649 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1650 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1651 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1652 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1653 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1654 def : InstAlias<"ldrsw $Rt, [$Rn, $offset]",
1655 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1658 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1659 [(AArch64Prefetch imm:$Rt,
1660 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1663 // (unscaled immediate, unprivileged)
1664 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1665 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1667 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1668 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1670 // load sign-extended half-word
1671 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1672 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1674 // load sign-extended byte
1675 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1676 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1678 // load sign-extended word
1679 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1682 // (immediate pre-indexed)
1683 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1684 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1685 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1686 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1687 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1688 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1689 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1691 // load sign-extended half-word
1692 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1693 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1695 // load sign-extended byte
1696 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1697 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1699 // load zero-extended byte
1700 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1701 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1703 // load sign-extended word
1704 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1707 // (immediate post-indexed)
1708 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1709 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1710 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1711 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1712 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1713 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1714 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1716 // load sign-extended half-word
1717 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1718 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1720 // load sign-extended byte
1721 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1722 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1724 // load zero-extended byte
1725 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1726 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1728 // load sign-extended word
1729 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1731 //===----------------------------------------------------------------------===//
1732 // Store instructions.
1733 //===----------------------------------------------------------------------===//
1735 // Pair (indexed, offset)
1736 // FIXME: Use dedicated range-checked addressing mode operand here.
1737 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1738 defm STPX : StorePairOffset<0b10, 0, GPR64, simm7s8, "stp">;
1739 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1740 defm STPD : StorePairOffset<0b01, 1, FPR64, simm7s8, "stp">;
1741 defm STPQ : StorePairOffset<0b10, 1, FPR128, simm7s16, "stp">;
1743 // Pair (pre-indexed)
1744 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1745 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, simm7s8, "stp">;
1746 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1747 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, simm7s8, "stp">;
1748 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, simm7s16, "stp">;
1750 // Pair (pre-indexed)
1751 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1752 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1753 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1754 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1755 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1757 // Pair (no allocate)
1758 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
1759 defm STNPX : StorePairNoAlloc<0b10, 0, GPR64, simm7s8, "stnp">;
1760 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
1761 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64, simm7s8, "stnp">;
1762 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128, simm7s16, "stnp">;
1765 // (Register offset)
1768 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
1769 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
1770 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
1771 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
1775 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
1776 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
1777 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
1778 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
1779 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
1781 multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
1782 Instruction STRW, Instruction STRX> {
1784 def : Pat<(storeop GPR64:$Rt,
1785 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1786 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1787 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1789 def : Pat<(storeop GPR64:$Rt,
1790 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1791 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1792 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1795 let AddedComplexity = 10 in {
1797 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>;
1798 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>;
1799 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>;
1802 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
1803 Instruction STRW, Instruction STRX> {
1804 def : Pat<(store (VecTy FPR:$Rt),
1805 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1806 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1808 def : Pat<(store (VecTy FPR:$Rt),
1809 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1810 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1813 let AddedComplexity = 10 in {
1814 // Match all store 64 bits width whose type is compatible with FPR64
1815 let Predicates = [IsLE] in {
1816 // We must use ST1 to store vectors in big-endian.
1817 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
1818 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
1819 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
1820 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;
1823 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
1824 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
1826 // Match all store 128 bits width whose type is compatible with FPR128
1827 let Predicates = [IsLE] in {
1828 // We must use ST1 to store vectors in big-endian.
1829 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;
1830 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
1831 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;
1832 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
1833 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>;
1834 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>;
1836 } // AddedComplexity = 10
1839 // (unsigned immediate)
1840 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
1842 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1843 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
1845 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1846 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
1848 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>;
1849 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
1850 [(store (f16 FPR16:$Rt),
1851 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>;
1852 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
1853 [(store (f32 FPR32:$Rt),
1854 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1855 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
1856 [(store (f64 FPR64:$Rt),
1857 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1858 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
1860 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
1861 [(truncstorei16 GPR32:$Rt,
1862 (am_indexed16 GPR64sp:$Rn,
1863 uimm12s2:$offset))]>;
1864 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
1865 [(truncstorei8 GPR32:$Rt,
1866 (am_indexed8 GPR64sp:$Rn,
1867 uimm12s1:$offset))]>;
1869 // Match all store 64 bits width whose type is compatible with FPR64
1870 let AddedComplexity = 10 in {
1871 let Predicates = [IsLE] in {
1872 // We must use ST1 to store vectors in big-endian.
1873 def : Pat<(store (v2f32 FPR64:$Rt),
1874 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1875 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1876 def : Pat<(store (v8i8 FPR64:$Rt),
1877 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1878 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1879 def : Pat<(store (v4i16 FPR64:$Rt),
1880 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1881 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1882 def : Pat<(store (v2i32 FPR64:$Rt),
1883 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1884 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1886 def : Pat<(store (v1f64 FPR64:$Rt),
1887 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1888 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1889 def : Pat<(store (v1i64 FPR64:$Rt),
1890 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1891 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1893 // Match all store 128 bits width whose type is compatible with FPR128
1894 let Predicates = [IsLE] in {
1895 // We must use ST1 to store vectors in big-endian.
1896 def : Pat<(store (v4f32 FPR128:$Rt),
1897 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1898 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1899 def : Pat<(store (v2f64 FPR128:$Rt),
1900 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1901 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1902 def : Pat<(store (v16i8 FPR128:$Rt),
1903 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1904 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1905 def : Pat<(store (v8i16 FPR128:$Rt),
1906 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1907 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1908 def : Pat<(store (v4i32 FPR128:$Rt),
1909 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1910 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1911 def : Pat<(store (v2i64 FPR128:$Rt),
1912 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1913 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1915 def : Pat<(store (f128 FPR128:$Rt),
1916 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1917 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1920 def : Pat<(truncstorei32 GPR64:$Rt,
1921 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
1922 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;
1923 def : Pat<(truncstorei16 GPR64:$Rt,
1924 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
1925 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;
1926 def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
1927 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>;
1929 } // AddedComplexity = 10
1932 // (unscaled immediate)
1933 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
1935 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1936 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
1938 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
1939 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
1941 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
1942 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
1943 [(store (f16 FPR16:$Rt),
1944 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
1945 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
1946 [(store (f32 FPR32:$Rt),
1947 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
1948 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
1949 [(store (f64 FPR64:$Rt),
1950 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1951 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
1952 [(store (f128 FPR128:$Rt),
1953 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;
1954 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
1955 [(truncstorei16 GPR32:$Rt,
1956 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
1957 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
1958 [(truncstorei8 GPR32:$Rt,
1959 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
1961 // Match all store 64 bits width whose type is compatible with FPR64
1962 let Predicates = [IsLE] in {
1963 // We must use ST1 to store vectors in big-endian.
1964 def : Pat<(store (v2f32 FPR64:$Rt),
1965 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1966 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1967 def : Pat<(store (v8i8 FPR64:$Rt),
1968 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1969 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1970 def : Pat<(store (v4i16 FPR64:$Rt),
1971 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1972 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1973 def : Pat<(store (v2i32 FPR64:$Rt),
1974 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1975 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1977 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1978 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1979 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
1980 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1982 // Match all store 128 bits width whose type is compatible with FPR128
1983 let Predicates = [IsLE] in {
1984 // We must use ST1 to store vectors in big-endian.
1985 def : Pat<(store (v4f32 FPR128:$Rt),
1986 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
1987 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1988 def : Pat<(store (v2f64 FPR128:$Rt),
1989 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
1990 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1991 def : Pat<(store (v16i8 FPR128:$Rt),
1992 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
1993 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1994 def : Pat<(store (v8i16 FPR128:$Rt),
1995 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
1996 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
1997 def : Pat<(store (v4i32 FPR128:$Rt),
1998 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
1999 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2000 def : Pat<(store (v2i64 FPR128:$Rt),
2001 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2002 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2003 def : Pat<(store (v2f64 FPR128:$Rt),
2004 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2005 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2008 // unscaled i64 truncating stores
2009 def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
2010 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2011 def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2012 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2013 def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
2014 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2017 // STR mnemonics fall back to STUR for negative or unaligned offsets.
2018 def : InstAlias<"str $Rt, [$Rn, $offset]",
2019 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2020 def : InstAlias<"str $Rt, [$Rn, $offset]",
2021 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2022 def : InstAlias<"str $Rt, [$Rn, $offset]",
2023 (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2024 def : InstAlias<"str $Rt, [$Rn, $offset]",
2025 (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2026 def : InstAlias<"str $Rt, [$Rn, $offset]",
2027 (STURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2028 def : InstAlias<"str $Rt, [$Rn, $offset]",
2029 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2030 def : InstAlias<"str $Rt, [$Rn, $offset]",
2031 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
2033 def : InstAlias<"strb $Rt, [$Rn, $offset]",
2034 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2035 def : InstAlias<"strh $Rt, [$Rn, $offset]",
2036 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2039 // (unscaled immediate, unprivileged)
2040 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2041 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2043 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2044 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2047 // (immediate pre-indexed)
2048 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2049 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2050 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2051 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2052 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2053 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2054 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2056 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2057 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2060 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2061 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2063 def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2064 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2066 def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2067 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2070 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2071 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2072 def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2073 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2074 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2075 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2076 def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2077 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2078 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2079 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2080 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2081 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2083 def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2084 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2085 def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2086 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2087 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2088 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2089 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2090 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2091 def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2092 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2093 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2094 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2097 // (immediate post-indexed)
2098 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2099 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2100 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2101 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2102 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2103 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2104 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2106 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2107 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2110 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2111 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2113 def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2114 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2116 def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2117 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2120 def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2121 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2122 def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2123 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2124 def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2125 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2126 def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2127 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2128 def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2129 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2130 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2131 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2133 def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2134 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2135 def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2136 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2137 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2138 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2139 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2140 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2141 def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2142 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2143 def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2144 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2146 //===----------------------------------------------------------------------===//
2147 // Load/store exclusive instructions.
2148 //===----------------------------------------------------------------------===//
2150 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
2151 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2152 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2153 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2155 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2156 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2157 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2158 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2160 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
2161 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2162 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2163 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2165 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
2166 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2167 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2168 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2170 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
2171 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2172 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2173 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2175 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
2176 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2177 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2178 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2180 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
2181 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2183 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
2184 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2186 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
2187 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2189 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
2190 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2192 //===----------------------------------------------------------------------===//
2193 // Scaled floating point to integer conversion instructions.
2194 //===----------------------------------------------------------------------===//
2196 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2197 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2198 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
2199 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;
2200 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2201 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2202 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
2203 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
2204 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2205 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2206 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2207 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2208 let isCodeGenOnly = 1 in {
2209 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2210 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2211 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2212 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2215 //===----------------------------------------------------------------------===//
2216 // Scaled integer to floating point conversion instructions.
2217 //===----------------------------------------------------------------------===//
2219 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2220 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2222 //===----------------------------------------------------------------------===//
2223 // Unscaled integer to floating point conversion instruction.
2224 //===----------------------------------------------------------------------===//
2226 defm FMOV : UnscaledConversion<"fmov">;
2228 def : Pat<(f32 (fpimm0)), (FMOVWSr WZR)>, Requires<[NoZCZ]>;
2229 def : Pat<(f64 (fpimm0)), (FMOVXDr XZR)>, Requires<[NoZCZ]>;
2231 //===----------------------------------------------------------------------===//
2232 // Floating point conversion instruction.
2233 //===----------------------------------------------------------------------===//
2235 defm FCVT : FPConversion<"fcvt">;
2237 def : Pat<(f32_to_f16 FPR32:$Rn),
2238 (i32 (COPY_TO_REGCLASS
2239 (f32 (SUBREG_TO_REG (i32 0), (FCVTHSr FPR32:$Rn), hsub)),
2242 def FCVTSHpseudo : Pseudo<(outs FPR32:$Rd), (ins FPR32:$Rn),
2243 [(set (f32 FPR32:$Rd), (f16_to_f32 i32:$Rn))]>;
2245 //===----------------------------------------------------------------------===//
2246 // Floating point single operand instructions.
2247 //===----------------------------------------------------------------------===//
2249 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2250 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2251 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2252 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2253 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2254 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2255 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>;
2256 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2258 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
2259 (FRINTNDr FPR64:$Rn)>;
2261 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
2262 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
2263 // <rdar://problem/13715968>
2264 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2265 let hasSideEffects = 1 in {
2266 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2269 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2271 let SchedRW = [WriteFDiv] in {
2272 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2275 //===----------------------------------------------------------------------===//
2276 // Floating point two operand instructions.
2277 //===----------------------------------------------------------------------===//
2279 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2280 let SchedRW = [WriteFDiv] in {
2281 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2283 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_aarch64_neon_fmaxnm>;
2284 defm FMAX : TwoOperandFPData<0b0100, "fmax", AArch64fmax>;
2285 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_aarch64_neon_fminnm>;
2286 defm FMIN : TwoOperandFPData<0b0101, "fmin", AArch64fmin>;
2287 let SchedRW = [WriteFMul] in {
2288 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2289 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2291 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2293 def : Pat<(v1f64 (AArch64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2294 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2295 def : Pat<(v1f64 (AArch64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2296 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2297 def : Pat<(v1f64 (int_aarch64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2298 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2299 def : Pat<(v1f64 (int_aarch64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2300 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2302 //===----------------------------------------------------------------------===//
2303 // Floating point three operand instructions.
2304 //===----------------------------------------------------------------------===//
2306 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2307 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2308 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2309 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2310 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2311 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2312 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2314 // The following def pats catch the case where the LHS of an FMA is negated.
2315 // The TriOpFrag above catches the case where the middle operand is negated.
2317 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2318 // the NEON variant.
2319 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2320 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2322 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2323 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2325 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2327 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2328 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2330 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2331 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2333 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2334 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2336 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2337 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2339 //===----------------------------------------------------------------------===//
2340 // Floating point comparison instructions.
2341 //===----------------------------------------------------------------------===//
2343 defm FCMPE : FPComparison<1, "fcmpe">;
2344 defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>;
2346 //===----------------------------------------------------------------------===//
2347 // Floating point conditional comparison instructions.
2348 //===----------------------------------------------------------------------===//
2350 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2351 defm FCCMP : FPCondComparison<0, "fccmp">;
2353 //===----------------------------------------------------------------------===//
2354 // Floating point conditional select instruction.
2355 //===----------------------------------------------------------------------===//
2357 defm FCSEL : FPCondSelect<"fcsel">;
2359 // CSEL instructions providing f128 types need to be handled by a
2360 // pseudo-instruction since the eventual code will need to introduce basic
2361 // blocks and control flow.
2362 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2363 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2364 [(set (f128 FPR128:$Rd),
2365 (AArch64csel FPR128:$Rn, FPR128:$Rm,
2366 (i32 imm:$cond), NZCV))]> {
2368 let usesCustomInserter = 1;
2372 //===----------------------------------------------------------------------===//
2373 // Floating point immediate move.
2374 //===----------------------------------------------------------------------===//
2376 let isReMaterializable = 1 in {
2377 defm FMOV : FPMoveImmediate<"fmov">;
2380 //===----------------------------------------------------------------------===//
2381 // Advanced SIMD two vector instructions.
2382 //===----------------------------------------------------------------------===//
2384 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_aarch64_neon_abs>;
2385 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
2386 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2387 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;
2388 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;
2389 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
2390 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;
2391 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;
2392 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2393 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2395 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2396 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2397 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2398 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2399 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2400 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>;
2401 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;
2402 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2403 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2404 (FCVTLv4i16 V64:$Rn)>;
2405 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2407 (FCVTLv8i16 V128:$Rn)>;
2408 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2409 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2411 (FCVTLv4i32 V128:$Rn)>;
2413 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;
2414 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;
2415 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>;
2416 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>;
2417 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2418 def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2419 (FCVTNv4i16 V128:$Rn)>;
2420 def : Pat<(concat_vectors V64:$Rd,
2421 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2422 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2423 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2424 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2425 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2426 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
2427 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
2428 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2429 int_aarch64_neon_fcvtxn>;
2430 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2431 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2432 let isCodeGenOnly = 1 in {
2433 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2434 int_aarch64_neon_fcvtzs>;
2435 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2436 int_aarch64_neon_fcvtzu>;
2438 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2439 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;
2440 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2441 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2442 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2443 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>;
2444 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2445 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2446 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2447 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>;
2448 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2449 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2450 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2451 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2452 // Aliases for MVN -> NOT.
2453 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2454 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2455 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2456 (NOTv16i8 V128:$Vd, V128:$Vn)>;
2458 def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2459 def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2460 def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2461 def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2462 def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2463 def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2464 def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2466 def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2467 def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2468 def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2469 def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2470 def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2471 def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2472 def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2473 def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2475 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2476 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2477 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2478 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2479 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2481 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>;
2482 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
2483 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>;
2484 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
2485 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2486 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >;
2487 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>;
2488 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2489 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2490 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2491 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2492 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>;
2493 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>;
2494 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>;
2495 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2496 BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >;
2497 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2498 int_aarch64_neon_uaddlp>;
2499 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2500 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>;
2501 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>;
2502 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;
2503 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>;
2504 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2506 def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2507 def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2509 // Patterns for vector long shift (by element width). These need to match all
2510 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2512 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2513 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2514 (SHLLv8i8 V64:$Rn)>;
2515 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2516 (SHLLv16i8 V128:$Rn)>;
2517 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2518 (SHLLv4i16 V64:$Rn)>;
2519 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2520 (SHLLv8i16 V128:$Rn)>;
2521 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2522 (SHLLv2i32 V64:$Rn)>;
2523 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2524 (SHLLv4i32 V128:$Rn)>;
2527 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2528 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2529 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2531 //===----------------------------------------------------------------------===//
2532 // Advanced SIMD three vector instructions.
2533 //===----------------------------------------------------------------------===//
2535 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2536 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
2537 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
2538 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
2539 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
2540 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
2541 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
2542 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
2543 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_aarch64_neon_fabd>;
2544 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_aarch64_neon_facge>;
2545 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_aarch64_neon_facgt>;
2546 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_aarch64_neon_addp>;
2547 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2548 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2549 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2550 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2551 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2552 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
2553 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_aarch64_neon_fmaxnm>;
2554 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_aarch64_neon_fmaxp>;
2555 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", AArch64fmax>;
2556 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_aarch64_neon_fminnmp>;
2557 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_aarch64_neon_fminnm>;
2558 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_aarch64_neon_fminp>;
2559 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", AArch64fmin>;
2561 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2562 // instruction expects the addend first, while the fma intrinsic puts it last.
2563 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2564 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2565 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2566 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2568 // The following def pats catch the case where the LHS of an FMA is negated.
2569 // The TriOpFrag above catches the case where the middle operand is negated.
2570 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2571 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2573 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2574 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2576 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2577 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2579 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_aarch64_neon_fmulx>;
2580 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2581 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_aarch64_neon_frecps>;
2582 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_aarch64_neon_frsqrts>;
2583 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2584 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2585 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2586 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2587 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2588 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2589 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
2590 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2591 TriOpFrag<(add node:$LHS, (int_aarch64_neon_sabd node:$MHS, node:$RHS))> >;
2592 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_aarch64_neon_sabd>;
2593 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>;
2594 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
2595 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
2596 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_aarch64_neon_smax>;
2597 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>;
2598 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_aarch64_neon_smin>;
2599 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>;
2600 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>;
2601 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>;
2602 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>;
2603 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>;
2604 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>;
2605 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>;
2606 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
2607 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
2608 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2609 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2610 TriOpFrag<(add node:$LHS, (int_aarch64_neon_uabd node:$MHS, node:$RHS))> >;
2611 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_aarch64_neon_uabd>;
2612 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>;
2613 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
2614 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
2615 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_aarch64_neon_umax>;
2616 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>;
2617 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_aarch64_neon_umin>;
2618 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>;
2619 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>;
2620 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>;
2621 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>;
2622 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>;
2623 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;
2624 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
2626 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2627 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2628 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2629 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2630 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>;
2631 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2632 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2633 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2634 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2635 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2636 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2638 def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2639 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2640 def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2641 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2642 def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2643 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2644 def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2645 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2647 def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2648 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2649 def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2650 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2651 def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2652 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2653 def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2654 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2656 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2657 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
2658 def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",
2659 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2660 def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}",
2661 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2662 def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}",
2663 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2665 def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}",
2666 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>;
2667 def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}",
2668 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2669 def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}",
2670 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2671 def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}",
2672 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2674 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2675 "|cmls.8b\t$dst, $src1, $src2}",
2676 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2677 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2678 "|cmls.16b\t$dst, $src1, $src2}",
2679 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2680 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2681 "|cmls.4h\t$dst, $src1, $src2}",
2682 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2683 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2684 "|cmls.8h\t$dst, $src1, $src2}",
2685 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2686 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2687 "|cmls.2s\t$dst, $src1, $src2}",
2688 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2689 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2690 "|cmls.4s\t$dst, $src1, $src2}",
2691 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2692 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2693 "|cmls.2d\t$dst, $src1, $src2}",
2694 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2696 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2697 "|cmlo.8b\t$dst, $src1, $src2}",
2698 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2699 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2700 "|cmlo.16b\t$dst, $src1, $src2}",
2701 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2702 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2703 "|cmlo.4h\t$dst, $src1, $src2}",
2704 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2705 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2706 "|cmlo.8h\t$dst, $src1, $src2}",
2707 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2708 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
2709 "|cmlo.2s\t$dst, $src1, $src2}",
2710 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2711 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
2712 "|cmlo.4s\t$dst, $src1, $src2}",
2713 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2714 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
2715 "|cmlo.2d\t$dst, $src1, $src2}",
2716 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2718 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
2719 "|cmle.8b\t$dst, $src1, $src2}",
2720 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2721 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
2722 "|cmle.16b\t$dst, $src1, $src2}",
2723 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2724 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
2725 "|cmle.4h\t$dst, $src1, $src2}",
2726 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2727 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
2728 "|cmle.8h\t$dst, $src1, $src2}",
2729 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2730 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
2731 "|cmle.2s\t$dst, $src1, $src2}",
2732 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2733 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
2734 "|cmle.4s\t$dst, $src1, $src2}",
2735 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2736 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
2737 "|cmle.2d\t$dst, $src1, $src2}",
2738 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2740 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
2741 "|cmlt.8b\t$dst, $src1, $src2}",
2742 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2743 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
2744 "|cmlt.16b\t$dst, $src1, $src2}",
2745 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2746 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
2747 "|cmlt.4h\t$dst, $src1, $src2}",
2748 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2749 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
2750 "|cmlt.8h\t$dst, $src1, $src2}",
2751 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2752 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
2753 "|cmlt.2s\t$dst, $src1, $src2}",
2754 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2755 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
2756 "|cmlt.4s\t$dst, $src1, $src2}",
2757 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2758 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
2759 "|cmlt.2d\t$dst, $src1, $src2}",
2760 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2762 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
2763 "|fcmle.2s\t$dst, $src1, $src2}",
2764 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2765 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
2766 "|fcmle.4s\t$dst, $src1, $src2}",
2767 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2768 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
2769 "|fcmle.2d\t$dst, $src1, $src2}",
2770 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2772 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
2773 "|fcmlt.2s\t$dst, $src1, $src2}",
2774 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2775 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
2776 "|fcmlt.4s\t$dst, $src1, $src2}",
2777 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2778 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
2779 "|fcmlt.2d\t$dst, $src1, $src2}",
2780 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2782 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
2783 "|facle.2s\t$dst, $src1, $src2}",
2784 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2785 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
2786 "|facle.4s\t$dst, $src1, $src2}",
2787 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2788 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
2789 "|facle.2d\t$dst, $src1, $src2}",
2790 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2792 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
2793 "|faclt.2s\t$dst, $src1, $src2}",
2794 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2795 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
2796 "|faclt.4s\t$dst, $src1, $src2}",
2797 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2798 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
2799 "|faclt.2d\t$dst, $src1, $src2}",
2800 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2802 //===----------------------------------------------------------------------===//
2803 // Advanced SIMD three scalar instructions.
2804 //===----------------------------------------------------------------------===//
2806 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
2807 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>;
2808 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
2809 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
2810 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
2811 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
2812 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
2813 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_aarch64_sisd_fabd>;
2814 def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2815 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
2816 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
2817 int_aarch64_neon_facge>;
2818 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
2819 int_aarch64_neon_facgt>;
2820 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2821 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2822 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2823 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_aarch64_neon_fmulx>;
2824 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_aarch64_neon_frecps>;
2825 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_aarch64_neon_frsqrts>;
2826 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>;
2827 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;
2828 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
2829 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>;
2830 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>;
2831 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>;
2832 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>;
2833 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;
2834 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
2835 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>;
2836 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>;
2837 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>;
2838 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>;
2839 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>;
2840 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;
2842 def : InstAlias<"cmls $dst, $src1, $src2",
2843 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2844 def : InstAlias<"cmle $dst, $src1, $src2",
2845 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2846 def : InstAlias<"cmlo $dst, $src1, $src2",
2847 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2848 def : InstAlias<"cmlt $dst, $src1, $src2",
2849 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2850 def : InstAlias<"fcmle $dst, $src1, $src2",
2851 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2852 def : InstAlias<"fcmle $dst, $src1, $src2",
2853 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2854 def : InstAlias<"fcmlt $dst, $src1, $src2",
2855 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2856 def : InstAlias<"fcmlt $dst, $src1, $src2",
2857 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2858 def : InstAlias<"facle $dst, $src1, $src2",
2859 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2860 def : InstAlias<"facle $dst, $src1, $src2",
2861 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2862 def : InstAlias<"faclt $dst, $src1, $src2",
2863 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2864 def : InstAlias<"faclt $dst, $src1, $src2",
2865 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2867 //===----------------------------------------------------------------------===//
2868 // Advanced SIMD three scalar instructions (mixed operands).
2869 //===----------------------------------------------------------------------===//
2870 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
2871 int_aarch64_neon_sqdmulls_scalar>;
2872 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
2873 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
2875 def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),
2876 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2877 (i32 FPR32:$Rm))))),
2878 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2879 def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),
2880 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2881 (i32 FPR32:$Rm))))),
2882 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2884 //===----------------------------------------------------------------------===//
2885 // Advanced SIMD two scalar instructions.
2886 //===----------------------------------------------------------------------===//
2888 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_aarch64_neon_abs>;
2889 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;
2890 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;
2891 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;
2892 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>;
2893 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>;
2894 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2895 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2896 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2897 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2898 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2899 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
2900 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
2901 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
2902 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
2903 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
2904 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
2905 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
2906 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
2907 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
2908 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
2909 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
2910 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
2911 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
2912 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
2913 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
2914 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2915 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", AArch64sitof>;
2916 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2917 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2918 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>;
2919 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>;
2920 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
2921 int_aarch64_neon_suqadd>;
2922 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", AArch64uitof>;
2923 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>;
2924 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
2925 int_aarch64_neon_usqadd>;
2927 def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
2929 def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))),
2930 (FCVTASv1i64 FPR64:$Rn)>;
2931 def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))),
2932 (FCVTAUv1i64 FPR64:$Rn)>;
2933 def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))),
2934 (FCVTMSv1i64 FPR64:$Rn)>;
2935 def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))),
2936 (FCVTMUv1i64 FPR64:$Rn)>;
2937 def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))),
2938 (FCVTNSv1i64 FPR64:$Rn)>;
2939 def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))),
2940 (FCVTNUv1i64 FPR64:$Rn)>;
2941 def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),
2942 (FCVTPSv1i64 FPR64:$Rn)>;
2943 def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),
2944 (FCVTPUv1i64 FPR64:$Rn)>;
2946 def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),
2947 (FRECPEv1i32 FPR32:$Rn)>;
2948 def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),
2949 (FRECPEv1i64 FPR64:$Rn)>;
2950 def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))),
2951 (FRECPEv1i64 FPR64:$Rn)>;
2953 def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),
2954 (FRECPXv1i32 FPR32:$Rn)>;
2955 def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),
2956 (FRECPXv1i64 FPR64:$Rn)>;
2958 def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),
2959 (FRSQRTEv1i32 FPR32:$Rn)>;
2960 def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),
2961 (FRSQRTEv1i64 FPR64:$Rn)>;
2962 def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))),
2963 (FRSQRTEv1i64 FPR64:$Rn)>;
2965 // If an integer is about to be converted to a floating point value,
2966 // just load it on the floating point unit.
2967 // Here are the patterns for 8 and 16-bits to float.
2969 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
2970 SDPatternOperator loadop, Instruction UCVTF,
2971 ROAddrMode ro, Instruction LDRW, Instruction LDRX,
2973 def : Pat<(DstTy (uint_to_fp (SrcTy
2974 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm,
2975 ro.Wext:$extend))))),
2976 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
2977 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
2980 def : Pat<(DstTy (uint_to_fp (SrcTy
2981 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm,
2982 ro.Wext:$extend))))),
2983 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
2984 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
2988 defm : UIntToFPROLoadPat<f32, i32, zextloadi8,
2989 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>;
2990 def : Pat <(f32 (uint_to_fp (i32
2991 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
2992 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2993 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
2994 def : Pat <(f32 (uint_to_fp (i32
2995 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
2996 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2997 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
2998 // 16-bits -> float.
2999 defm : UIntToFPROLoadPat<f32, i32, zextloadi16,
3000 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
3001 def : Pat <(f32 (uint_to_fp (i32
3002 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3003 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3004 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3005 def : Pat <(f32 (uint_to_fp (i32
3006 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3007 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3008 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3009 // 32-bits are handled in target specific dag combine:
3010 // performIntToFpCombine.
3011 // 64-bits integer to 32-bits floating point, not possible with
3012 // UCVTF on floating point registers (both source and destination
3013 // must have the same size).
3015 // Here are the patterns for 8, 16, 32, and 64-bits to double.
3016 // 8-bits -> double.
3017 defm : UIntToFPROLoadPat<f64, i32, zextloadi8,
3018 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>;
3019 def : Pat <(f64 (uint_to_fp (i32
3020 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3021 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3022 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3023 def : Pat <(f64 (uint_to_fp (i32
3024 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3025 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3026 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3027 // 16-bits -> double.
3028 defm : UIntToFPROLoadPat<f64, i32, zextloadi16,
3029 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;
3030 def : Pat <(f64 (uint_to_fp (i32
3031 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3032 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3033 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3034 def : Pat <(f64 (uint_to_fp (i32
3035 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3036 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3037 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3038 // 32-bits -> double.
3039 defm : UIntToFPROLoadPat<f64, i32, load,
3040 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>;
3041 def : Pat <(f64 (uint_to_fp (i32
3042 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
3043 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3044 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;
3045 def : Pat <(f64 (uint_to_fp (i32
3046 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
3047 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3048 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
3049 // 64-bits -> double are handled in target specific dag combine:
3050 // performIntToFpCombine.
3052 //===----------------------------------------------------------------------===//
3053 // Advanced SIMD three different-sized vector instructions.
3054 //===----------------------------------------------------------------------===//
3056 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
3057 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
3058 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
3059 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
3060 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;
3061 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
3062 int_aarch64_neon_sabd>;
3063 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
3064 int_aarch64_neon_sabd>;
3065 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
3066 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
3067 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
3068 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
3069 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
3070 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3071 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
3072 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3073 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>;
3074 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
3075 int_aarch64_neon_sqadd>;
3076 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
3077 int_aarch64_neon_sqsub>;
3078 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
3079 int_aarch64_neon_sqdmull>;
3080 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
3081 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
3082 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
3083 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
3084 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
3085 int_aarch64_neon_uabd>;
3086 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
3087 int_aarch64_neon_uabd>;
3088 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
3089 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
3090 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
3091 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
3092 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
3093 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3094 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
3095 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3096 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>;
3097 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
3098 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
3099 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
3100 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
3102 // Patterns for 64-bit pmull
3103 def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm),
3104 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
3105 def : Pat<(int_aarch64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
3106 (vector_extract (v2i64 V128:$Rm), (i64 1))),
3107 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
3109 // CodeGen patterns for addhn and subhn instructions, which can actually be
3110 // written in LLVM IR without too much difficulty.
3113 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
3114 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3115 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3117 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3118 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3120 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3121 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3122 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3124 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3125 V128:$Rn, V128:$Rm)>;
3126 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3127 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3129 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3130 V128:$Rn, V128:$Rm)>;
3131 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3132 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3134 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3135 V128:$Rn, V128:$Rm)>;
3138 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
3139 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3140 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3142 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3143 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3145 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3146 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3147 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3149 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3150 V128:$Rn, V128:$Rm)>;
3151 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3152 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3154 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3155 V128:$Rn, V128:$Rm)>;
3156 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3157 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3159 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3160 V128:$Rn, V128:$Rm)>;
3162 //----------------------------------------------------------------------------
3163 // AdvSIMD bitwise extract from vector instruction.
3164 //----------------------------------------------------------------------------
3166 defm EXT : SIMDBitwiseExtract<"ext">;
3168 def : Pat<(v4i16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3169 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3170 def : Pat<(v8i16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3171 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3172 def : Pat<(v2i32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3173 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3174 def : Pat<(v2f32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3175 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3176 def : Pat<(v4i32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3177 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3178 def : Pat<(v4f32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3179 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3180 def : Pat<(v2i64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3181 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3182 def : Pat<(v2f64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3183 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3185 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
3187 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
3188 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3189 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
3190 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3191 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
3192 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3193 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
3194 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3195 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
3196 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3197 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
3198 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3201 //----------------------------------------------------------------------------
3202 // AdvSIMD zip vector
3203 //----------------------------------------------------------------------------
3205 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;
3206 defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>;
3207 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
3208 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;
3209 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
3210 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;
3212 //----------------------------------------------------------------------------
3213 // AdvSIMD TBL/TBX instructions
3214 //----------------------------------------------------------------------------
3216 defm TBL : SIMDTableLookup< 0, "tbl">;
3217 defm TBX : SIMDTableLookupTied<1, "tbx">;
3219 def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3220 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
3221 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3222 (TBLv16i8One V128:$Ri, V128:$Rn)>;
3224 def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),
3225 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3226 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
3227 def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),
3228 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3229 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
3232 //----------------------------------------------------------------------------
3233 // AdvSIMD scalar CPY instruction
3234 //----------------------------------------------------------------------------
3236 defm CPY : SIMDScalarCPY<"cpy">;
3238 //----------------------------------------------------------------------------
3239 // AdvSIMD scalar pairwise instructions
3240 //----------------------------------------------------------------------------
3242 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
3243 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
3244 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
3245 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
3246 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
3247 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
3248 def : Pat<(i64 (int_aarch64_neon_saddv (v2i64 V128:$Rn))),
3249 (ADDPv2i64p V128:$Rn)>;
3250 def : Pat<(i64 (int_aarch64_neon_uaddv (v2i64 V128:$Rn))),
3251 (ADDPv2i64p V128:$Rn)>;
3252 def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))),
3253 (FADDPv2i32p V64:$Rn)>;
3254 def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))),
3255 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
3256 def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))),
3257 (FADDPv2i64p V128:$Rn)>;
3258 def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))),
3259 (FMAXNMPv2i32p V64:$Rn)>;
3260 def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))),
3261 (FMAXNMPv2i64p V128:$Rn)>;
3262 def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))),
3263 (FMAXPv2i32p V64:$Rn)>;
3264 def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))),
3265 (FMAXPv2i64p V128:$Rn)>;
3266 def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))),
3267 (FMINNMPv2i32p V64:$Rn)>;
3268 def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))),
3269 (FMINNMPv2i64p V128:$Rn)>;
3270 def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))),
3271 (FMINPv2i32p V64:$Rn)>;
3272 def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))),
3273 (FMINPv2i64p V128:$Rn)>;
3275 //----------------------------------------------------------------------------
3276 // AdvSIMD INS/DUP instructions
3277 //----------------------------------------------------------------------------
3279 def DUPv8i8gpr : SIMDDupFromMain<0, 0b00001, ".8b", v8i8, V64, GPR32>;
3280 def DUPv16i8gpr : SIMDDupFromMain<1, 0b00001, ".16b", v16i8, V128, GPR32>;
3281 def DUPv4i16gpr : SIMDDupFromMain<0, 0b00010, ".4h", v4i16, V64, GPR32>;
3282 def DUPv8i16gpr : SIMDDupFromMain<1, 0b00010, ".8h", v8i16, V128, GPR32>;
3283 def DUPv2i32gpr : SIMDDupFromMain<0, 0b00100, ".2s", v2i32, V64, GPR32>;
3284 def DUPv4i32gpr : SIMDDupFromMain<1, 0b00100, ".4s", v4i32, V128, GPR32>;
3285 def DUPv2i64gpr : SIMDDupFromMain<1, 0b01000, ".2d", v2i64, V128, GPR64>;
3287 def DUPv2i64lane : SIMDDup64FromElement;
3288 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3289 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3290 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3291 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3292 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3293 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3295 def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))),
3296 (v2f32 (DUPv2i32lane
3297 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3299 def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))),
3300 (v4f32 (DUPv4i32lane
3301 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3303 def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))),
3304 (v2f64 (DUPv2i64lane
3305 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3308 def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3309 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3310 def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3311 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3312 def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3313 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3315 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane
3316 // instruction even if the types don't match: we just have to remap the lane
3317 // carefully. N.b. this trick only applies to truncations.
3318 def VecIndex_x2 : SDNodeXForm<imm, [{
3319 return CurDAG->getTargetConstant(2 * N->getZExtValue(), MVT::i64);
3321 def VecIndex_x4 : SDNodeXForm<imm, [{
3322 return CurDAG->getTargetConstant(4 * N->getZExtValue(), MVT::i64);
3324 def VecIndex_x8 : SDNodeXForm<imm, [{
3325 return CurDAG->getTargetConstant(8 * N->getZExtValue(), MVT::i64);
3328 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3329 ValueType Src128VT, ValueType ScalVT,
3330 Instruction DUP, SDNodeXForm IdxXFORM> {
3331 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3333 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3335 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3337 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3340 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3341 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3342 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3344 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3345 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3346 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3348 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3349 SDNodeXForm IdxXFORM> {
3350 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3352 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3354 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3356 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3359 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3360 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3361 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3363 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3364 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3365 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3367 // SMOV and UMOV definitions, with some extra patterns for convenience
3371 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3372 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3373 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3374 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3375 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3376 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3377 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3378 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3379 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3380 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3381 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3382 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3384 // Extracting i8 or i16 elements will have the zero-extend transformed to
3385 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3386 // for AArch64. Match these patterns here since UMOV already zeroes out the high
3387 // bits of the destination register.
3388 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3390 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3391 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3393 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3397 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3398 (SUBREG_TO_REG (i32 0),
3399 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3400 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3401 (SUBREG_TO_REG (i32 0),
3402 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3404 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3405 (SUBREG_TO_REG (i32 0),
3406 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3407 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3408 (SUBREG_TO_REG (i32 0),
3409 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3411 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3412 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3413 (i32 FPR32:$Rn), ssub))>;
3414 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3415 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3416 (i32 FPR32:$Rn), ssub))>;
3417 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3418 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3419 (i64 FPR64:$Rn), dsub))>;
3421 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3422 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3423 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3424 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3425 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3426 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3428 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3429 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3432 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3434 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3437 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3438 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3440 V128:$Rn, VectorIndexS:$imm,
3441 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3443 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3444 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3446 V128:$Rn, VectorIndexD:$imm,
3447 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3450 // Copy an element at a constant index in one vector into a constant indexed
3451 // element of another.
3452 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3453 // index type and INS extension
3454 def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane
3455 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3456 VectorIndexB:$idx2)),
3458 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3460 def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane
3461 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3462 VectorIndexH:$idx2)),
3464 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3466 def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane
3467 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3468 VectorIndexS:$idx2)),
3470 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3472 def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
3473 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3474 VectorIndexD:$idx2)),
3476 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3479 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3480 ValueType VTScal, Instruction INS> {
3481 def : Pat<(VT128 (vector_insert V128:$src,
3482 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3484 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3486 def : Pat<(VT128 (vector_insert V128:$src,
3487 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3489 (INS V128:$src, imm:$Immd,
3490 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3492 def : Pat<(VT64 (vector_insert V64:$src,
3493 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3495 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3496 imm:$Immd, V128:$Rn, imm:$Immn),
3499 def : Pat<(VT64 (vector_insert V64:$src,
3500 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3503 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3504 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3508 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3509 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3510 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, INSvi8lane>;
3511 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, INSvi16lane>;
3512 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, INSvi32lane>;
3513 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, INSvi32lane>;
3516 // Floating point vector extractions are codegen'd as either a sequence of
3517 // subregister extractions, possibly fed by an INS if the lane number is
3518 // anything other than zero.
3519 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3520 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3521 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3522 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3523 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3524 (f64 (EXTRACT_SUBREG
3525 (INSvi64lane (v2f64 (IMPLICIT_DEF)), 0,
3526 V128:$Rn, VectorIndexD:$idx),
3528 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3529 (f32 (EXTRACT_SUBREG
3530 (INSvi32lane (v4f32 (IMPLICIT_DEF)), 0,
3531 V128:$Rn, VectorIndexS:$idx),
3534 // All concat_vectors operations are canonicalised to act on i64 vectors for
3535 // AArch64. In the general case we need an instruction, which had just as well be
3537 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3538 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3539 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3540 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3542 def : ConcatPat<v2i64, v1i64>;
3543 def : ConcatPat<v2f64, v1f64>;
3544 def : ConcatPat<v4i32, v2i32>;
3545 def : ConcatPat<v4f32, v2f32>;
3546 def : ConcatPat<v8i16, v4i16>;
3547 def : ConcatPat<v16i8, v8i8>;
3549 // If the high lanes are undef, though, we can just ignore them:
3550 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3551 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3552 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3554 def : ConcatUndefPat<v2i64, v1i64>;
3555 def : ConcatUndefPat<v2f64, v1f64>;
3556 def : ConcatUndefPat<v4i32, v2i32>;
3557 def : ConcatUndefPat<v4f32, v2f32>;
3558 def : ConcatUndefPat<v8i16, v4i16>;
3559 def : ConcatUndefPat<v16i8, v8i8>;
3561 //----------------------------------------------------------------------------
3562 // AdvSIMD across lanes instructions
3563 //----------------------------------------------------------------------------
3565 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3566 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3567 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3568 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3569 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3570 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3571 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3572 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>;
3573 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>;
3574 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>;
3575 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
3577 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, Intrinsic intOp> {
3578 // If there is a sign extension after this intrinsic, consume it as smov already
3580 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i8 V64:$Rn))), i8)),
3582 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3583 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3585 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3587 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3588 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3590 // If there is a sign extension after this intrinsic, consume it as smov already
3592 def : Pat<(i32 (sext_inreg (i32 (intOp (v16i8 V128:$Rn))), i8)),
3594 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3595 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3597 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3599 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3600 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3602 // If there is a sign extension after this intrinsic, consume it as smov already
3604 def : Pat<(i32 (sext_inreg (i32 (intOp (v4i16 V64:$Rn))), i16)),
3606 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3607 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3609 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3611 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3612 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3614 // If there is a sign extension after this intrinsic, consume it as smov already
3616 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i16 V128:$Rn))), i16)),
3618 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3619 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3621 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3623 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3624 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3627 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3628 (i32 (EXTRACT_SUBREG
3629 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3630 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3634 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc, Intrinsic intOp> {
3635 // If there is a masking operation keeping only what has been actually
3636 // generated, consume it.
3637 def : Pat<(i32 (and (i32 (intOp (v8i8 V64:$Rn))), maski8_or_more)),
3638 (i32 (EXTRACT_SUBREG
3639 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3640 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3642 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3643 (i32 (EXTRACT_SUBREG
3644 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3645 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3647 // If there is a masking operation keeping only what has been actually
3648 // generated, consume it.
3649 def : Pat<(i32 (and (i32 (intOp (v16i8 V128:$Rn))), maski8_or_more)),
3650 (i32 (EXTRACT_SUBREG
3651 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3652 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3654 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3655 (i32 (EXTRACT_SUBREG
3656 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3657 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3660 // If there is a masking operation keeping only what has been actually
3661 // generated, consume it.
3662 def : Pat<(i32 (and (i32 (intOp (v4i16 V64:$Rn))), maski16_or_more)),
3663 (i32 (EXTRACT_SUBREG
3664 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3665 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3667 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3668 (i32 (EXTRACT_SUBREG
3669 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3670 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3672 // If there is a masking operation keeping only what has been actually
3673 // generated, consume it.
3674 def : Pat<(i32 (and (i32 (intOp (v8i16 V128:$Rn))), maski16_or_more)),
3675 (i32 (EXTRACT_SUBREG
3676 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3677 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3679 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3680 (i32 (EXTRACT_SUBREG
3681 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3682 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3685 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3686 (i32 (EXTRACT_SUBREG
3687 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3688 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3693 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
3694 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3696 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3697 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3699 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3701 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3702 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3705 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3706 (i32 (EXTRACT_SUBREG
3707 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3708 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3710 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3711 (i32 (EXTRACT_SUBREG
3712 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3713 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3716 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3717 (i64 (EXTRACT_SUBREG
3718 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3719 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3723 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
3725 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3726 (i32 (EXTRACT_SUBREG
3727 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3728 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3730 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3731 (i32 (EXTRACT_SUBREG
3732 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3733 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3736 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3737 (i32 (EXTRACT_SUBREG
3738 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3739 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3741 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3742 (i32 (EXTRACT_SUBREG
3743 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3744 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3747 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3748 (i64 (EXTRACT_SUBREG
3749 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3750 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3754 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", int_aarch64_neon_saddv>;
3755 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3756 def : Pat<(i32 (int_aarch64_neon_saddv (v2i32 V64:$Rn))),
3757 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3759 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", int_aarch64_neon_uaddv>;
3760 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3761 def : Pat<(i32 (int_aarch64_neon_uaddv (v2i32 V64:$Rn))),
3762 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3764 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", int_aarch64_neon_smaxv>;
3765 def : Pat<(i32 (int_aarch64_neon_smaxv (v2i32 V64:$Rn))),
3766 (EXTRACT_SUBREG (SMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3768 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", int_aarch64_neon_sminv>;
3769 def : Pat<(i32 (int_aarch64_neon_sminv (v2i32 V64:$Rn))),
3770 (EXTRACT_SUBREG (SMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3772 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", int_aarch64_neon_umaxv>;
3773 def : Pat<(i32 (int_aarch64_neon_umaxv (v2i32 V64:$Rn))),
3774 (EXTRACT_SUBREG (UMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3776 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", int_aarch64_neon_uminv>;
3777 def : Pat<(i32 (int_aarch64_neon_uminv (v2i32 V64:$Rn))),
3778 (EXTRACT_SUBREG (UMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3780 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>;
3781 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>;
3783 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
3784 def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))),
3785 (i64 (EXTRACT_SUBREG
3786 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3787 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
3789 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
3790 def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))),
3791 (i64 (EXTRACT_SUBREG
3792 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3793 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
3796 //------------------------------------------------------------------------------
3797 // AdvSIMD modified immediate instructions
3798 //------------------------------------------------------------------------------
3801 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
3803 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
3805 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
3806 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
3807 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
3808 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
3810 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3811 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3812 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3813 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3815 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
3816 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
3817 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
3818 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
3820 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3821 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3822 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3823 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3826 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
3828 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
3829 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
3831 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
3832 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
3834 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
3838 // EDIT byte mask: scalar
3839 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3840 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
3841 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
3842 // The movi_edit node has the immediate value already encoded, so we use
3843 // a plain imm0_255 here.
3844 def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)),
3845 (MOVID imm0_255:$shift)>;
3847 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
3848 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
3849 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
3850 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
3852 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
3853 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
3854 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
3855 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
3857 // EDIT byte mask: 2d
3859 // The movi_edit node has the immediate value already encoded, so we use
3860 // a plain imm0_255 in the pattern
3861 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3862 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
3865 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;
3868 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
3869 // Complexity is added to break a tie with a plain MOVI.
3870 let AddedComplexity = 1 in {
3871 def : Pat<(f32 fpimm0),
3872 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
3874 def : Pat<(f64 fpimm0),
3875 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
3879 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3880 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3881 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3882 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3884 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3885 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3886 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3887 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3889 def : Pat<(v2f64 (AArch64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
3890 def : Pat<(v4f32 (AArch64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
3892 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3893 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
3895 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3896 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3897 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3898 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3900 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3901 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3902 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3903 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3905 def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3906 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
3907 def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3908 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
3909 def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3910 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
3911 def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3912 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
3914 // EDIT per word: 2s & 4s with MSL shifter
3915 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
3916 [(set (v2i32 V64:$Rd),
3917 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3918 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
3919 [(set (v4i32 V128:$Rd),
3920 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3922 // Per byte: 8b & 16b
3923 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
3925 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>;
3926 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
3928 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>;
3932 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3933 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
3935 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3936 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3937 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3938 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3940 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3941 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3942 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3943 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3945 def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3946 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
3947 def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3948 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
3949 def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3950 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
3951 def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3952 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
3954 // EDIT per word: 2s & 4s with MSL shifter
3955 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
3956 [(set (v2i32 V64:$Rd),
3957 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3958 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
3959 [(set (v4i32 V128:$Rd),
3960 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3962 //----------------------------------------------------------------------------
3963 // AdvSIMD indexed element
3964 //----------------------------------------------------------------------------
3966 let neverHasSideEffects = 1 in {
3967 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
3968 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
3971 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
3972 // instruction expects the addend first, while the intrinsic expects it last.
3974 // On the other hand, there are quite a few valid combinatorial options due to
3975 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
3976 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3977 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
3978 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3979 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
3981 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3982 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
3983 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3984 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
3985 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3986 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
3987 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3988 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
3990 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
3991 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
3993 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3994 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
3995 VectorIndexS:$idx))),
3996 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
3997 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3998 (v2f32 (AArch64duplane32
3999 (v4f32 (insert_subvector undef,
4000 (v2f32 (fneg V64:$Rm)),
4002 VectorIndexS:$idx)))),
4003 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4004 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4005 VectorIndexS:$idx)>;
4006 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4007 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4008 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4009 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4011 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4013 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4014 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4015 VectorIndexS:$idx))),
4016 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
4017 VectorIndexS:$idx)>;
4018 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4019 (v4f32 (AArch64duplane32
4020 (v4f32 (insert_subvector undef,
4021 (v2f32 (fneg V64:$Rm)),
4023 VectorIndexS:$idx)))),
4024 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4025 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4026 VectorIndexS:$idx)>;
4027 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4028 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4029 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4030 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4032 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
4033 // (DUPLANE from 64-bit would be trivial).
4034 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4035 (AArch64duplane64 (v2f64 (fneg V128:$Rm)),
4036 VectorIndexD:$idx))),
4038 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4039 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4040 (AArch64dup (f64 (fneg FPR64Op:$Rm))))),
4041 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
4042 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
4044 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
4045 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4046 (vector_extract (v4f32 (fneg V128:$Rm)),
4047 VectorIndexS:$idx))),
4048 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4049 V128:$Rm, VectorIndexS:$idx)>;
4050 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4051 (vector_extract (v2f32 (fneg V64:$Rm)),
4052 VectorIndexS:$idx))),
4053 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4054 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
4056 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
4057 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
4058 (vector_extract (v2f64 (fneg V128:$Rm)),
4059 VectorIndexS:$idx))),
4060 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
4061 V128:$Rm, VectorIndexS:$idx)>;
4064 defm : FMLSIndexedAfterNegPatterns<
4065 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
4066 defm : FMLSIndexedAfterNegPatterns<
4067 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
4069 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;
4070 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
4072 def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4073 (FMULv2i32_indexed V64:$Rn,
4074 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4076 def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4077 (FMULv4i32_indexed V128:$Rn,
4078 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4080 def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))),
4081 (FMULv2i64_indexed V128:$Rn,
4082 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
4085 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>;
4086 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
4087 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
4088 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
4089 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
4090 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
4091 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
4092 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
4093 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4094 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
4095 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4096 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
4097 int_aarch64_neon_smull>;
4098 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
4099 int_aarch64_neon_sqadd>;
4100 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
4101 int_aarch64_neon_sqsub>;
4102 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;
4103 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
4104 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4105 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
4106 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4107 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
4108 int_aarch64_neon_umull>;
4110 // A scalar sqdmull with the second operand being a vector lane can be
4111 // handled directly with the indexed instruction encoding.
4112 def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
4113 (vector_extract (v4i32 V128:$Vm),
4114 VectorIndexS:$idx)),
4115 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
4117 //----------------------------------------------------------------------------
4118 // AdvSIMD scalar shift instructions
4119 //----------------------------------------------------------------------------
4120 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
4121 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
4122 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
4123 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
4124 // Codegen patterns for the above. We don't put these directly on the
4125 // instructions because TableGen's type inference can't handle the truth.
4126 // Having the same base pattern for fp <--> int totally freaks it out.
4127 def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
4128 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
4129 def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
4130 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
4131 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
4132 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4133 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
4134 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4135 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
4137 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4138 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
4140 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4141 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
4142 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4143 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
4144 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4145 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4146 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4147 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4148 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4149 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
4151 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4152 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
4154 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4156 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;
4157 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
4158 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
4159 int_aarch64_neon_sqrshrn>;
4160 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
4161 int_aarch64_neon_sqrshrun>;
4162 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4163 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4164 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
4165 int_aarch64_neon_sqshrn>;
4166 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
4167 int_aarch64_neon_sqshrun>;
4168 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4169 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>;
4170 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4171 TriOpFrag<(add node:$LHS,
4172 (AArch64srshri node:$MHS, node:$RHS))>>;
4173 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>;
4174 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
4175 TriOpFrag<(add node:$LHS,
4176 (AArch64vashr node:$MHS, node:$RHS))>>;
4177 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
4178 int_aarch64_neon_uqrshrn>;
4179 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4180 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4181 int_aarch64_neon_uqshrn>;
4182 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>;
4183 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
4184 TriOpFrag<(add node:$LHS,
4185 (AArch64urshri node:$MHS, node:$RHS))>>;
4186 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>;
4187 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
4188 TriOpFrag<(add node:$LHS,
4189 (AArch64vlshr node:$MHS, node:$RHS))>>;
4191 //----------------------------------------------------------------------------
4192 // AdvSIMD vector shift instructions
4193 //----------------------------------------------------------------------------
4194 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
4195 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
4196 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
4197 int_aarch64_neon_vcvtfxs2fp>;
4198 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
4199 int_aarch64_neon_rshrn>;
4200 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>;
4201 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
4202 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>;
4203 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>;
4204 def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4205 (i32 vecshiftL64:$imm))),
4206 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
4207 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
4208 int_aarch64_neon_sqrshrn>;
4209 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
4210 int_aarch64_neon_sqrshrun>;
4211 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4212 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4213 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
4214 int_aarch64_neon_sqshrn>;
4215 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
4216 int_aarch64_neon_sqshrun>;
4217 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>;
4218 def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4219 (i32 vecshiftR64:$imm))),
4220 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
4221 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>;
4222 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
4223 TriOpFrag<(add node:$LHS,
4224 (AArch64srshri node:$MHS, node:$RHS))> >;
4225 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
4226 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>;
4228 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>;
4229 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
4230 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>;
4231 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
4232 int_aarch64_neon_vcvtfxu2fp>;
4233 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
4234 int_aarch64_neon_uqrshrn>;
4235 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4236 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
4237 int_aarch64_neon_uqshrn>;
4238 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>;
4239 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
4240 TriOpFrag<(add node:$LHS,
4241 (AArch64urshri node:$MHS, node:$RHS))> >;
4242 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
4243 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>;
4244 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>;
4245 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
4246 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >;
4248 // SHRN patterns for when a logical right shift was used instead of arithmetic
4249 // (the immediate guarantees no sign bits actually end up in the result so it
4251 def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
4252 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
4253 def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
4254 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
4255 def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
4256 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
4258 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
4259 (trunc (AArch64vlshr (v8i16 V128:$Rn),
4260 vecshiftR16Narrow:$imm)))),
4261 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4262 V128:$Rn, vecshiftR16Narrow:$imm)>;
4263 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
4264 (trunc (AArch64vlshr (v4i32 V128:$Rn),
4265 vecshiftR32Narrow:$imm)))),
4266 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4267 V128:$Rn, vecshiftR32Narrow:$imm)>;
4268 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
4269 (trunc (AArch64vlshr (v2i64 V128:$Rn),
4270 vecshiftR64Narrow:$imm)))),
4271 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4272 V128:$Rn, vecshiftR32Narrow:$imm)>;
4274 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
4275 // Anyexts are implemented as zexts.
4276 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
4277 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4278 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4279 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
4280 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4281 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4282 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
4283 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4284 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4285 // Also match an extend from the upper half of a 128 bit source register.
4286 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4287 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4288 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4289 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4290 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4291 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
4292 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4293 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4294 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4295 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4296 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4297 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
4298 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4299 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4300 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4301 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4302 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4303 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
4305 // Vector shift sxtl aliases
4306 def : InstAlias<"sxtl.8h $dst, $src1",
4307 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4308 def : InstAlias<"sxtl $dst.8h, $src1.8b",
4309 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4310 def : InstAlias<"sxtl.4s $dst, $src1",
4311 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4312 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4313 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4314 def : InstAlias<"sxtl.2d $dst, $src1",
4315 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4316 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4317 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4319 // Vector shift sxtl2 aliases
4320 def : InstAlias<"sxtl2.8h $dst, $src1",
4321 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4322 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4323 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4324 def : InstAlias<"sxtl2.4s $dst, $src1",
4325 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4326 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4327 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4328 def : InstAlias<"sxtl2.2d $dst, $src1",
4329 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4330 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4331 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4333 // Vector shift uxtl aliases
4334 def : InstAlias<"uxtl.8h $dst, $src1",
4335 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4336 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4337 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4338 def : InstAlias<"uxtl.4s $dst, $src1",
4339 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4340 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4341 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4342 def : InstAlias<"uxtl.2d $dst, $src1",
4343 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4344 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4345 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4347 // Vector shift uxtl2 aliases
4348 def : InstAlias<"uxtl2.8h $dst, $src1",
4349 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4350 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4351 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4352 def : InstAlias<"uxtl2.4s $dst, $src1",
4353 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4354 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4355 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4356 def : InstAlias<"uxtl2.2d $dst, $src1",
4357 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4358 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4359 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4361 // If an integer is about to be converted to a floating point value,
4362 // just load it on the floating point unit.
4363 // These patterns are more complex because floating point loads do not
4364 // support sign extension.
4365 // The sign extension has to be explicitly added and is only supported for
4366 // one step: byte-to-half, half-to-word, word-to-doubleword.
4367 // SCVTF GPR -> FPR is 9 cycles.
4368 // SCVTF FPR -> FPR is 4 cyclces.
4369 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4370 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4371 // and still being faster.
4372 // However, this is not good for code size.
4373 // 8-bits -> float. 2 sizes step-up.
4374 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>
4375 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),
4376 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4381 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4387 ssub)))>, Requires<[NotForCodeSize]>;
4389 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
4390 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
4391 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),
4392 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;
4393 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),
4394 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;
4395 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),
4396 (LDURBi GPR64sp:$Rn, simm9:$offset)>;
4398 // 16-bits -> float. 1 size step-up.
4399 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
4400 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4401 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4403 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4407 ssub)))>, Requires<[NotForCodeSize]>;
4409 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4410 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4411 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4412 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4413 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4414 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4415 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4416 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4418 // 32-bits to 32-bits are handled in target specific dag combine:
4419 // performIntToFpCombine.
4420 // 64-bits integer to 32-bits floating point, not possible with
4421 // SCVTF on floating point registers (both source and destination
4422 // must have the same size).
4424 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4425 // 8-bits -> double. 3 size step-up: give up.
4426 // 16-bits -> double. 2 size step.
4427 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>
4428 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4429 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4434 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4440 dsub)))>, Requires<[NotForCodeSize]>;
4442 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4443 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4444 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4445 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4446 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4447 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4448 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4449 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4450 // 32-bits -> double. 1 size step-up.
4451 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
4452 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),
4453 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4455 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4459 dsub)))>, Requires<[NotForCodeSize]>;
4461 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
4462 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
4463 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),
4464 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;
4465 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),
4466 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;
4467 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),
4468 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
4470 // 64-bits -> double are handled in target specific dag combine:
4471 // performIntToFpCombine.
4474 //----------------------------------------------------------------------------
4475 // AdvSIMD Load-Store Structure
4476 //----------------------------------------------------------------------------
4477 defm LD1 : SIMDLd1Multiple<"ld1">;
4478 defm LD2 : SIMDLd2Multiple<"ld2">;
4479 defm LD3 : SIMDLd3Multiple<"ld3">;
4480 defm LD4 : SIMDLd4Multiple<"ld4">;
4482 defm ST1 : SIMDSt1Multiple<"st1">;
4483 defm ST2 : SIMDSt2Multiple<"st2">;
4484 defm ST3 : SIMDSt3Multiple<"st3">;
4485 defm ST4 : SIMDSt4Multiple<"st4">;
4487 class Ld1Pat<ValueType ty, Instruction INST>
4488 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>;
4490 def : Ld1Pat<v16i8, LD1Onev16b>;
4491 def : Ld1Pat<v8i16, LD1Onev8h>;
4492 def : Ld1Pat<v4i32, LD1Onev4s>;
4493 def : Ld1Pat<v2i64, LD1Onev2d>;
4494 def : Ld1Pat<v8i8, LD1Onev8b>;
4495 def : Ld1Pat<v4i16, LD1Onev4h>;
4496 def : Ld1Pat<v2i32, LD1Onev2s>;
4497 def : Ld1Pat<v1i64, LD1Onev1d>;
4499 class St1Pat<ValueType ty, Instruction INST>
4500 : Pat<(store ty:$Vt, GPR64sp:$Rn),
4501 (INST ty:$Vt, GPR64sp:$Rn)>;
4503 def : St1Pat<v16i8, ST1Onev16b>;
4504 def : St1Pat<v8i16, ST1Onev8h>;
4505 def : St1Pat<v4i32, ST1Onev4s>;
4506 def : St1Pat<v2i64, ST1Onev2d>;
4507 def : St1Pat<v8i8, ST1Onev8b>;
4508 def : St1Pat<v4i16, ST1Onev4h>;
4509 def : St1Pat<v2i32, ST1Onev2s>;
4510 def : St1Pat<v1i64, ST1Onev1d>;
4516 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4517 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4518 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4519 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4520 let mayLoad = 1, neverHasSideEffects = 1 in {
4521 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4522 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4523 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4524 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4525 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4526 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4527 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4528 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4529 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4530 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4531 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4532 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4533 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4534 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4535 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4536 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4539 def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4540 (LD1Rv8b GPR64sp:$Rn)>;
4541 def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4542 (LD1Rv16b GPR64sp:$Rn)>;
4543 def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4544 (LD1Rv4h GPR64sp:$Rn)>;
4545 def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4546 (LD1Rv8h GPR64sp:$Rn)>;
4547 def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4548 (LD1Rv2s GPR64sp:$Rn)>;
4549 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4550 (LD1Rv4s GPR64sp:$Rn)>;
4551 def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4552 (LD1Rv2d GPR64sp:$Rn)>;
4553 def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4554 (LD1Rv1d GPR64sp:$Rn)>;
4555 // Grab the floating point version too
4556 def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4557 (LD1Rv2s GPR64sp:$Rn)>;
4558 def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4559 (LD1Rv4s GPR64sp:$Rn)>;
4560 def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4561 (LD1Rv2d GPR64sp:$Rn)>;
4562 def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4563 (LD1Rv1d GPR64sp:$Rn)>;
4565 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4566 ValueType VTy, ValueType STy, Instruction LD1>
4567 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4568 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4569 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
4571 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4572 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4573 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4574 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4575 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4576 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4578 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4579 ValueType VTy, ValueType STy, Instruction LD1>
4580 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4581 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4583 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4584 VecIndex:$idx, GPR64sp:$Rn),
4587 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4588 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4589 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4590 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4593 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4594 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4595 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4596 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4599 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4600 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4601 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4602 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4604 let AddedComplexity = 15 in
4605 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4606 ValueType VTy, ValueType STy, Instruction ST1>
4608 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4610 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
4612 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4613 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
4614 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
4615 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
4616 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
4617 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
4619 let AddedComplexity = 15 in
4620 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4621 ValueType VTy, ValueType STy, Instruction ST1>
4623 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4625 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4626 VecIndex:$idx, GPR64sp:$Rn)>;
4628 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
4629 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
4630 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
4631 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
4633 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4634 ValueType VTy, ValueType STy, Instruction ST1,
4636 def : Pat<(scalar_store
4637 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4638 GPR64sp:$Rn, offset),
4639 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4640 VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4642 def : Pat<(scalar_store
4643 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4644 GPR64sp:$Rn, GPR64:$Rm),
4645 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4646 VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4649 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
4650 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
4652 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
4653 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
4654 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
4655 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
4657 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4658 ValueType VTy, ValueType STy, Instruction ST1,
4660 def : Pat<(scalar_store
4661 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4662 GPR64sp:$Rn, offset),
4663 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4665 def : Pat<(scalar_store
4666 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4667 GPR64sp:$Rn, GPR64:$Rm),
4668 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4671 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
4673 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
4675 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
4676 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
4677 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
4678 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
4680 let mayStore = 1, neverHasSideEffects = 1 in {
4681 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
4682 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
4683 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
4684 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
4685 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
4686 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
4687 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
4688 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
4689 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
4690 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
4691 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
4692 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
4695 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
4696 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
4697 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
4698 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
4700 //----------------------------------------------------------------------------
4701 // Crypto extensions
4702 //----------------------------------------------------------------------------
4704 def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>;
4705 def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;
4706 def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>;
4707 def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
4709 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>;
4710 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>;
4711 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>;
4712 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>;
4713 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>;
4714 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>;
4715 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>;
4717 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>;
4718 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>;
4719 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>;
4721 //----------------------------------------------------------------------------
4723 //----------------------------------------------------------------------------
4724 // FIXME: Like for X86, these should go in their own separate .td file.
4726 // Any instruction that defines a 32-bit result leaves the high half of the
4727 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
4728 // be copying from a truncate. But any other 32-bit operation will zero-extend
4730 // FIXME: X86 also checks for CMOV here. Do we need something similar?
4731 def def32 : PatLeaf<(i32 GPR32:$src), [{
4732 return N->getOpcode() != ISD::TRUNCATE &&
4733 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
4734 N->getOpcode() != ISD::CopyFromReg;
4737 // In the case of a 32-bit def that is known to implicitly zero-extend,
4738 // we can use a SUBREG_TO_REG.
4739 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
4741 // For an anyext, we don't care what the high bits are, so we can perform an
4742 // INSERT_SUBREF into an IMPLICIT_DEF.
4743 def : Pat<(i64 (anyext GPR32:$src)),
4744 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
4746 // When we need to explicitly zero-extend, we use an unsigned bitfield move
4747 // instruction (UBFM) on the enclosing super-reg.
4748 def : Pat<(i64 (zext GPR32:$src)),
4749 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4751 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
4752 // containing super-reg.
4753 def : Pat<(i64 (sext GPR32:$src)),
4754 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4755 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
4756 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
4757 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
4758 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
4759 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
4760 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
4761 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
4763 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
4764 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4765 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
4766 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
4767 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4768 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
4770 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
4771 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4772 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
4773 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
4774 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4775 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
4777 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
4778 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4779 (i64 (i64shift_a imm0_63:$imm)),
4780 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
4782 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
4783 // AddedComplexity for the following patterns since we want to match sext + sra
4784 // patterns before we attempt to match a single sra node.
4785 let AddedComplexity = 20 in {
4786 // We support all sext + sra combinations which preserve at least one bit of the
4787 // original value which is to be sign extended. E.g. we support shifts up to
4789 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
4790 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
4791 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
4792 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
4794 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
4795 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
4796 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
4797 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
4799 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
4800 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4801 (i64 imm0_31:$imm), 31)>;
4802 } // AddedComplexity = 20
4804 // To truncate, we can simply extract from a subregister.
4805 def : Pat<(i32 (trunc GPR64sp:$src)),
4806 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
4808 // __builtin_trap() uses the BRK instruction on AArch64.
4809 def : Pat<(trap), (BRK 1)>;
4811 // Conversions within AdvSIMD types in the same register size are free.
4812 // But because we need a consistent lane ordering, in big endian many
4813 // conversions require one or more REV instructions.
4815 // Consider a simple memory load followed by a bitconvert then a store.
4817 // v1 = BITCAST v2i32 v0 to v4i16
4820 // In big endian mode every memory access has an implicit byte swap. LDR and
4821 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
4822 // is, they treat the vector as a sequence of elements to be byte-swapped.
4823 // The two pairs of instructions are fundamentally incompatible. We've decided
4824 // to use LD1/ST1 only to simplify compiler implementation.
4826 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
4827 // the original code sequence:
4829 // v1 = REV v2i32 (implicit)
4830 // v2 = BITCAST v2i32 v1 to v4i16
4831 // v3 = REV v4i16 v2 (implicit)
4834 // But this is now broken - the value stored is different to the value loaded
4835 // due to lane reordering. To fix this, on every BITCAST we must perform two
4838 // v1 = REV v2i32 (implicit)
4840 // v3 = BITCAST v2i32 v2 to v4i16
4842 // v5 = REV v4i16 v4 (implicit)
4845 // This means an extra two instructions, but actually in most cases the two REV
4846 // instructions can be combined into one. For example:
4847 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
4849 // There is also no 128-bit REV instruction. This must be synthesized with an
4852 // Most bitconverts require some sort of conversion. The only exceptions are:
4853 // a) Identity conversions - vNfX <-> vNiX
4854 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
4857 let Predicates = [IsLE] in {
4858 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4859 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4860 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4861 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4863 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
4864 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4865 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
4866 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4867 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
4868 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4869 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
4870 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4871 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
4872 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4874 let Predicates = [IsBE] in {
4875 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
4876 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4877 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
4878 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4879 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
4880 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4881 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
4882 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4884 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
4885 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4886 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
4887 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4888 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
4889 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4890 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
4891 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4893 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4894 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4895 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
4896 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4897 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
4898 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4899 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
4900 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4901 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
4903 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
4904 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
4905 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
4906 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
4907 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
4908 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4909 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
4910 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
4911 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
4912 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4914 let Predicates = [IsLE] in {
4915 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
4916 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
4917 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
4918 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
4920 let Predicates = [IsBE] in {
4921 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
4922 (v1i64 (REV64v2i32 FPR64:$src))>;
4923 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
4924 (v1i64 (REV64v4i16 FPR64:$src))>;
4925 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
4926 (v1i64 (REV64v8i8 FPR64:$src))>;
4927 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
4928 (v1i64 (REV64v2i32 FPR64:$src))>;
4930 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4931 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4933 let Predicates = [IsLE] in {
4934 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
4935 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
4936 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
4937 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4938 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4940 let Predicates = [IsBE] in {
4941 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
4942 (v2i32 (REV64v2i32 FPR64:$src))>;
4943 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
4944 (v2i32 (REV32v4i16 FPR64:$src))>;
4945 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
4946 (v2i32 (REV32v8i8 FPR64:$src))>;
4947 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
4948 (v2i32 (REV64v2i32 FPR64:$src))>;
4949 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
4950 (v2i32 (REV64v2i32 FPR64:$src))>;
4952 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
4954 let Predicates = [IsLE] in {
4955 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
4956 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
4957 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
4958 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4959 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
4960 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4962 let Predicates = [IsBE] in {
4963 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
4964 (v4i16 (REV64v4i16 FPR64:$src))>;
4965 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
4966 (v4i16 (REV32v4i16 FPR64:$src))>;
4967 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
4968 (v4i16 (REV16v8i8 FPR64:$src))>;
4969 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
4970 (v4i16 (REV64v4i16 FPR64:$src))>;
4971 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
4972 (v4i16 (REV32v4i16 FPR64:$src))>;
4973 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
4974 (v4i16 (REV64v4i16 FPR64:$src))>;
4977 let Predicates = [IsLE] in {
4978 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
4979 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
4980 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
4981 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4982 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
4983 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4985 let Predicates = [IsBE] in {
4986 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
4987 (v8i8 (REV64v8i8 FPR64:$src))>;
4988 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
4989 (v8i8 (REV32v8i8 FPR64:$src))>;
4990 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
4991 (v8i8 (REV16v8i8 FPR64:$src))>;
4992 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
4993 (v8i8 (REV64v8i8 FPR64:$src))>;
4994 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
4995 (v8i8 (REV32v8i8 FPR64:$src))>;
4996 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
4997 (v8i8 (REV64v8i8 FPR64:$src))>;
5000 let Predicates = [IsLE] in {
5001 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
5002 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
5003 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
5004 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
5006 let Predicates = [IsBE] in {
5007 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
5008 (f64 (REV64v2i32 FPR64:$src))>;
5009 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
5010 (f64 (REV64v4i16 FPR64:$src))>;
5011 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
5012 (f64 (REV64v2i32 FPR64:$src))>;
5013 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
5014 (f64 (REV64v8i8 FPR64:$src))>;
5016 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
5017 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
5019 let Predicates = [IsLE] in {
5020 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
5021 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
5022 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
5023 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
5025 let Predicates = [IsBE] in {
5026 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
5027 (v1f64 (REV64v2i32 FPR64:$src))>;
5028 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
5029 (v1f64 (REV64v4i16 FPR64:$src))>;
5030 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
5031 (v1f64 (REV64v8i8 FPR64:$src))>;
5032 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
5033 (v1f64 (REV64v2i32 FPR64:$src))>;
5035 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
5036 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5038 let Predicates = [IsLE] in {
5039 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
5040 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
5041 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
5042 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5043 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5045 let Predicates = [IsBE] in {
5046 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
5047 (v2f32 (REV64v2i32 FPR64:$src))>;
5048 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
5049 (v2f32 (REV32v4i16 FPR64:$src))>;
5050 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
5051 (v2f32 (REV32v8i8 FPR64:$src))>;
5052 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
5053 (v2f32 (REV64v2i32 FPR64:$src))>;
5054 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
5055 (v2f32 (REV64v2i32 FPR64:$src))>;
5057 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5059 let Predicates = [IsLE] in {
5060 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
5061 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
5062 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
5063 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
5064 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
5065 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
5067 let Predicates = [IsBE] in {
5068 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
5069 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5070 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
5071 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5072 (REV64v4i32 FPR128:$src), (i32 8)))>;
5073 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
5074 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5075 (REV64v8i16 FPR128:$src), (i32 8)))>;
5076 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
5077 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5078 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
5079 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5080 (REV64v4i32 FPR128:$src), (i32 8)))>;
5081 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
5082 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
5083 (REV64v16i8 FPR128:$src), (i32 8)))>;
5086 let Predicates = [IsLE] in {
5087 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
5088 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5089 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5090 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5091 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5093 let Predicates = [IsBE] in {
5094 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
5095 (v2f64 (EXTv16i8 FPR128:$src,
5096 FPR128:$src, (i32 8)))>;
5097 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
5098 (v2f64 (REV64v4i32 FPR128:$src))>;
5099 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
5100 (v2f64 (REV64v8i16 FPR128:$src))>;
5101 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
5102 (v2f64 (REV64v16i8 FPR128:$src))>;
5103 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
5104 (v2f64 (REV64v4i32 FPR128:$src))>;
5106 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5108 let Predicates = [IsLE] in {
5109 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
5110 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5111 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5112 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5113 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5115 let Predicates = [IsBE] in {
5116 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
5117 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5118 (REV64v4i32 FPR128:$src), (i32 8)))>;
5119 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
5120 (v4f32 (REV32v8i16 FPR128:$src))>;
5121 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
5122 (v4f32 (REV32v16i8 FPR128:$src))>;
5123 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
5124 (v4f32 (REV64v4i32 FPR128:$src))>;
5125 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
5126 (v4f32 (REV64v4i32 FPR128:$src))>;
5128 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5130 let Predicates = [IsLE] in {
5131 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5132 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5133 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5134 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5135 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5137 let Predicates = [IsBE] in {
5138 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
5139 (v2i64 (EXTv16i8 FPR128:$src,
5140 FPR128:$src, (i32 8)))>;
5141 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
5142 (v2i64 (REV64v4i32 FPR128:$src))>;
5143 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
5144 (v2i64 (REV64v8i16 FPR128:$src))>;
5145 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
5146 (v2i64 (REV64v16i8 FPR128:$src))>;
5147 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
5148 (v2i64 (REV64v4i32 FPR128:$src))>;
5150 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5152 let Predicates = [IsLE] in {
5153 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5154 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5155 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5156 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5157 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5159 let Predicates = [IsBE] in {
5160 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
5161 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5162 (REV64v4i32 FPR128:$src),
5164 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
5165 (v4i32 (REV64v4i32 FPR128:$src))>;
5166 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
5167 (v4i32 (REV32v8i16 FPR128:$src))>;
5168 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
5169 (v4i32 (REV32v16i8 FPR128:$src))>;
5170 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
5171 (v4i32 (REV64v4i32 FPR128:$src))>;
5173 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5175 let Predicates = [IsLE] in {
5176 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5177 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5178 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5179 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5180 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5181 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5183 let Predicates = [IsBE] in {
5184 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
5185 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5186 (REV64v8i16 FPR128:$src),
5188 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
5189 (v8i16 (REV64v8i16 FPR128:$src))>;
5190 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
5191 (v8i16 (REV32v8i16 FPR128:$src))>;
5192 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
5193 (v8i16 (REV16v16i8 FPR128:$src))>;
5194 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
5195 (v8i16 (REV64v8i16 FPR128:$src))>;
5196 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
5197 (v8i16 (REV32v8i16 FPR128:$src))>;
5200 let Predicates = [IsLE] in {
5201 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5202 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5203 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5204 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5205 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5206 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5208 let Predicates = [IsBE] in {
5209 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
5210 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
5211 (REV64v16i8 FPR128:$src),
5213 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
5214 (v16i8 (REV64v16i8 FPR128:$src))>;
5215 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
5216 (v16i8 (REV32v16i8 FPR128:$src))>;
5217 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
5218 (v16i8 (REV16v16i8 FPR128:$src))>;
5219 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
5220 (v16i8 (REV64v16i8 FPR128:$src))>;
5221 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
5222 (v16i8 (REV32v16i8 FPR128:$src))>;
5225 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
5226 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5227 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
5228 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5229 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
5230 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5231 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
5232 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5234 // A 64-bit subvector insert to the first 128-bit vector position
5235 // is a subregister copy that needs no instruction.
5236 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
5237 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5238 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
5239 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5240 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
5241 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5242 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
5243 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5244 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
5245 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5246 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
5247 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5249 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
5251 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
5252 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
5253 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
5254 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
5255 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
5256 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
5257 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
5258 // so we match on v4f32 here, not v2f32. This will also catch adding
5259 // the low two lanes of a true v4f32 vector.
5260 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
5261 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
5262 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
5264 // Scalar 64-bit shifts in FPR64 registers.
5265 def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5266 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5267 def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5268 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5269 def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5270 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5271 def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5272 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5274 // Tail call return handling. These are all compiler pseudo-instructions,
5275 // so no encoding information or anything like that.
5276 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
5277 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff),[]>;
5278 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>;
5281 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
5282 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
5283 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
5284 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5285 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
5286 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5288 include "AArch64InstrAtomics.td"