1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // AArch64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
18 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
19 def HasNEON : Predicate<"Subtarget->hasNEON()">,
20 AssemblerPredicate<"FeatureNEON", "neon">;
21 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
22 AssemblerPredicate<"FeatureCrypto", "crypto">;
23 def HasCRC : Predicate<"Subtarget->hasCRC()">,
24 AssemblerPredicate<"FeatureCRC", "crc">;
25 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
26 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
27 def IsCyclone : Predicate<"Subtarget->isCyclone()">;
29 //===----------------------------------------------------------------------===//
30 // AArch64-specific DAG Nodes.
33 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
34 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
39 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
40 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
46 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
47 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
54 def SDT_AArch64Brcond : SDTypeProfile<0, 3,
55 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
57 def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
58 def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
59 SDTCisVT<2, OtherVT>]>;
62 def SDT_AArch64CSel : SDTypeProfile<1, 4,
67 def SDT_AArch64FCmp : SDTypeProfile<0, 2,
70 def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
71 def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
72 def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
75 def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
76 def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
77 def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
78 SDTCisInt<2>, SDTCisInt<3>]>;
79 def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
80 def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
81 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
82 def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
84 def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
85 def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>;
86 def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
87 def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
89 def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
92 def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
93 def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
95 def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
97 def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
99 def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
100 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
101 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
102 SDTCisSameAs<1, 4>]>;
106 def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
107 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
108 def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
109 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
110 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
111 [SDNPHasChain, SDNPOutGlue]>;
112 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",
113 SDCallSeqEnd<[ SDTCisVT<0, i32>,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
116 def AArch64call : SDNode<"AArch64ISD::CALL",
117 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
120 def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond,
122 def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,
124 def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz,
126 def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz,
128 def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz,
132 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
133 def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>;
134 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;
135 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
136 def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone,
137 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
138 def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >;
139 def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>;
140 def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut,
142 def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
143 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
145 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
146 def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
148 def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
150 def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
152 def AArch64fmax : SDNode<"AArch64ISD::FMAX", SDTFPBinOp>;
153 def AArch64fmin : SDNode<"AArch64ISD::FMIN", SDTFPBinOp>;
155 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;
156 def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;
157 def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;
158 def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>;
159 def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>;
161 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
162 def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>;
163 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
164 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;
165 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;
166 def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>;
168 def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>;
169 def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>;
170 def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>;
171 def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>;
172 def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;
173 def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;
174 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;
176 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
177 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
178 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
179 def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;
181 def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;
182 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;
183 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;
184 def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>;
185 def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>;
186 def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>;
187 def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>;
188 def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>;
190 def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>;
191 def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>;
192 def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>;
194 def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
195 def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>;
196 def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>;
197 def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>;
198 def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>;
200 def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;
201 def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>;
202 def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>;
204 def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>;
205 def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>;
206 def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>;
207 def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>;
208 def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>;
209 def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
210 (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
212 def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>;
213 def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>;
214 def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>;
215 def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>;
216 def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>;
218 def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>;
219 def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>;
221 def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>;
223 def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET,
224 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
226 def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH,
227 [SDNPHasChain, SDNPSideEffect]>;
229 def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>;
230 def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;
232 def AArch64tlsdesc_call : SDNode<"AArch64ISD::TLSDESC_CALL",
233 SDT_AArch64TLSDescCall,
234 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
237 def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
238 SDT_AArch64WrapperLarge>;
240 def AArch64NvCast : SDNode<"AArch64ISD::NVCAST", SDTUnaryOp>;
242 def SDT_AArch64mull : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
243 SDTCisSameAs<1, 2>]>;
244 def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull>;
245 def AArch64umull : SDNode<"AArch64ISD::UMULL", SDT_AArch64mull>;
247 //===----------------------------------------------------------------------===//
249 //===----------------------------------------------------------------------===//
251 // AArch64 Instruction Predicate Definitions.
253 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
254 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
255 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
256 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
257 def ForCodeSize : Predicate<"ForCodeSize">;
258 def NotForCodeSize : Predicate<"!ForCodeSize">;
260 include "AArch64InstrFormats.td"
262 //===----------------------------------------------------------------------===//
264 //===----------------------------------------------------------------------===//
265 // Miscellaneous instructions.
266 //===----------------------------------------------------------------------===//
268 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
269 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
270 [(AArch64callseq_start timm:$amt)]>;
271 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
272 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
273 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
275 let isReMaterializable = 1, isCodeGenOnly = 1 in {
276 // FIXME: The following pseudo instructions are only needed because remat
277 // cannot handle multiple instructions. When that changes, they can be
278 // removed, along with the AArch64Wrapper node.
280 let AddedComplexity = 10 in
281 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
282 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
285 // The MOVaddr instruction should match only when the add is not folded
286 // into a load or store address.
288 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
289 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
290 tglobaladdr:$low))]>,
291 Sched<[WriteAdrAdr]>;
293 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
294 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
296 Sched<[WriteAdrAdr]>;
298 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
299 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
301 Sched<[WriteAdrAdr]>;
303 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
304 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
305 tblockaddress:$low))]>,
306 Sched<[WriteAdrAdr]>;
308 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
309 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),
310 tglobaltlsaddr:$low))]>,
311 Sched<[WriteAdrAdr]>;
313 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
314 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),
315 texternalsym:$low))]>,
316 Sched<[WriteAdrAdr]>;
318 } // isReMaterializable, isCodeGenOnly
320 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
321 (LOADgot tglobaltlsaddr:$addr)>;
323 def : Pat<(AArch64LOADgot texternalsym:$addr),
324 (LOADgot texternalsym:$addr)>;
326 def : Pat<(AArch64LOADgot tconstpool:$addr),
327 (LOADgot tconstpool:$addr)>;
329 //===----------------------------------------------------------------------===//
330 // System instructions.
331 //===----------------------------------------------------------------------===//
333 def HINT : HintI<"hint">;
334 def : InstAlias<"nop", (HINT 0b000)>;
335 def : InstAlias<"yield",(HINT 0b001)>;
336 def : InstAlias<"wfe", (HINT 0b010)>;
337 def : InstAlias<"wfi", (HINT 0b011)>;
338 def : InstAlias<"sev", (HINT 0b100)>;
339 def : InstAlias<"sevl", (HINT 0b101)>;
341 // As far as LLVM is concerned this writes to the system's exclusive monitors.
342 let mayLoad = 1, mayStore = 1 in
343 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
345 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
346 // model patterns with sufficiently fine granularity.
347 let mayLoad = ?, mayStore = ? in {
348 def DMB : CRmSystemI<barrier_op, 0b101, "dmb",
349 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;
351 def DSB : CRmSystemI<barrier_op, 0b100, "dsb",
352 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
354 def ISB : CRmSystemI<barrier_op, 0b110, "isb",
355 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
358 def : InstAlias<"clrex", (CLREX 0xf)>;
359 def : InstAlias<"isb", (ISB 0xf)>;
363 def MSRpstate: MSRpstateI;
365 // The thread pointer (on Linux, at least, where this has been implemented) is
367 def : Pat<(AArch64threadpointer), (MRS 0xde82)>;
369 // Generic system instructions
370 def SYSxt : SystemXtI<0, "sys">;
371 def SYSLxt : SystemLXtI<1, "sysl">;
373 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
374 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
375 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
377 //===----------------------------------------------------------------------===//
378 // Move immediate instructions.
379 //===----------------------------------------------------------------------===//
381 defm MOVK : InsertImmediate<0b11, "movk">;
382 defm MOVN : MoveImmediate<0b00, "movn">;
384 let PostEncoderMethod = "fixMOVZ" in
385 defm MOVZ : MoveImmediate<0b10, "movz">;
387 // First group of aliases covers an implicit "lsl #0".
388 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
389 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
390 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
391 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
392 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
393 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
395 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
396 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
397 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
398 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
399 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
401 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
402 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
403 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
404 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
406 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
407 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
408 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
409 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
411 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
412 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
414 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
415 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
417 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
418 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
420 // Final group of aliases covers true "mov $Rd, $imm" cases.
421 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
422 int width, int shift> {
423 def _asmoperand : AsmOperandClass {
424 let Name = basename # width # "_lsl" # shift # "MovAlias";
425 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
427 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
430 def _movimm : Operand<i32> {
431 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
434 def : InstAlias<"mov $Rd, $imm",
435 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
438 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
439 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
441 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
442 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
443 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
444 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
446 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
447 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
449 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
450 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
451 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
452 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
454 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
455 isAsCheapAsAMove = 1 in {
456 // FIXME: The following pseudo instructions are only needed because remat
457 // cannot handle multiple instructions. When that changes, we can select
458 // directly to the real instructions and get rid of these pseudos.
461 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
462 [(set GPR32:$dst, imm:$src)]>,
465 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
466 [(set GPR64:$dst, imm:$src)]>,
468 } // isReMaterializable, isCodeGenOnly
470 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
471 // eventual expansion code fewer bits to worry about getting right. Marshalling
472 // the types is a little tricky though:
473 def i64imm_32bit : ImmLeaf<i64, [{
474 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
477 def trunc_imm : SDNodeXForm<imm, [{
478 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i32);
481 def : Pat<(i64 i64imm_32bit:$src),
482 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
484 // Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model).
485 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
486 return CurDAG->getTargetConstant(
487 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
490 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
491 return CurDAG->getTargetConstant(
492 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
496 def : Pat<(f32 fpimm:$in),
497 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>;
498 def : Pat<(f64 fpimm:$in),
499 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>;
502 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
504 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
505 tglobaladdr:$g1, tglobaladdr:$g0),
506 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
507 tglobaladdr:$g2, 32),
508 tglobaladdr:$g1, 16),
509 tglobaladdr:$g0, 0)>;
511 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
512 tblockaddress:$g1, tblockaddress:$g0),
513 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
514 tblockaddress:$g2, 32),
515 tblockaddress:$g1, 16),
516 tblockaddress:$g0, 0)>;
518 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
519 tconstpool:$g1, tconstpool:$g0),
520 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
525 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
526 tjumptable:$g1, tjumptable:$g0),
527 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
533 //===----------------------------------------------------------------------===//
534 // Arithmetic instructions.
535 //===----------------------------------------------------------------------===//
537 // Add/subtract with carry.
538 defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>;
539 defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>;
541 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
542 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
543 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
544 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
547 defm ADD : AddSub<0, "add", add>;
548 defm SUB : AddSub<1, "sub">;
550 def : InstAlias<"mov $dst, $src",
551 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
552 def : InstAlias<"mov $dst, $src",
553 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
554 def : InstAlias<"mov $dst, $src",
555 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
556 def : InstAlias<"mov $dst, $src",
557 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
559 defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn">;
560 defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp">;
562 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
563 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
564 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
565 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
566 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
567 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
568 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
569 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
570 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
571 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
572 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
573 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
574 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
575 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
576 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
577 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
578 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
580 // Because of the immediate format for add/sub-imm instructions, the
581 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
582 // These patterns capture that transformation.
583 let AddedComplexity = 1 in {
584 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
585 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
586 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
587 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
588 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
589 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
590 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
591 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
594 // Because of the immediate format for add/sub-imm instructions, the
595 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
596 // These patterns capture that transformation.
597 let AddedComplexity = 1 in {
598 def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
599 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
600 def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
601 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
602 def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
603 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
604 def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
605 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
608 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
609 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
610 def : InstAlias<"neg $dst, $src$shift",
611 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
612 def : InstAlias<"neg $dst, $src$shift",
613 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
615 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
616 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
617 def : InstAlias<"negs $dst, $src$shift",
618 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
619 def : InstAlias<"negs $dst, $src$shift",
620 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
623 // Unsigned/Signed divide
624 defm UDIV : Div<0, "udiv", udiv>;
625 defm SDIV : Div<1, "sdiv", sdiv>;
626 let isCodeGenOnly = 1 in {
627 defm UDIV_Int : Div<0, "udiv", int_aarch64_udiv>;
628 defm SDIV_Int : Div<1, "sdiv", int_aarch64_sdiv>;
632 defm ASRV : Shift<0b10, "asr", sra>;
633 defm LSLV : Shift<0b00, "lsl", shl>;
634 defm LSRV : Shift<0b01, "lsr", srl>;
635 defm RORV : Shift<0b11, "ror", rotr>;
637 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
638 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
639 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
640 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
641 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
642 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
643 def : ShiftAlias<"rorv", RORVWr, GPR32>;
644 def : ShiftAlias<"rorv", RORVXr, GPR64>;
647 let AddedComplexity = 7 in {
648 defm MADD : MulAccum<0, "madd", add>;
649 defm MSUB : MulAccum<1, "msub", sub>;
651 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
652 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
653 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
654 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
656 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
657 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
658 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
659 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
660 def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)),
661 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
662 def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)),
663 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
664 } // AddedComplexity = 7
666 let AddedComplexity = 5 in {
667 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
668 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
669 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
670 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
672 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
673 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
674 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
675 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
677 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
678 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
679 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
680 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
681 } // AddedComplexity = 5
683 def : MulAccumWAlias<"mul", MADDWrrr>;
684 def : MulAccumXAlias<"mul", MADDXrrr>;
685 def : MulAccumWAlias<"mneg", MSUBWrrr>;
686 def : MulAccumXAlias<"mneg", MSUBXrrr>;
687 def : WideMulAccumAlias<"smull", SMADDLrrr>;
688 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
689 def : WideMulAccumAlias<"umull", UMADDLrrr>;
690 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
693 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
694 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
697 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
698 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
699 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">;
700 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
702 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
703 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
704 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">;
705 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
708 //===----------------------------------------------------------------------===//
709 // Logical instructions.
710 //===----------------------------------------------------------------------===//
713 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
714 defm AND : LogicalImm<0b00, "and", and, "bic">;
715 defm EOR : LogicalImm<0b10, "eor", xor, "eon">;
716 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
718 // FIXME: these aliases *are* canonical sometimes (when movz can't be
719 // used). Actually, it seems to be working right now, but putting logical_immXX
720 // here is a bit dodgy on the AsmParser side too.
721 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
722 logical_imm32:$imm), 0>;
723 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
724 logical_imm64:$imm), 0>;
728 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
729 defm BICS : LogicalRegS<0b11, 1, "bics",
730 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;
731 defm AND : LogicalReg<0b00, 0, "and", and>;
732 defm BIC : LogicalReg<0b00, 1, "bic",
733 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
734 defm EON : LogicalReg<0b10, 1, "eon",
735 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
736 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
737 defm ORN : LogicalReg<0b01, 1, "orn",
738 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
739 defm ORR : LogicalReg<0b01, 0, "orr", or>;
741 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
742 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
744 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
745 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
747 def : InstAlias<"mvn $Wd, $Wm$sh",
748 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
749 def : InstAlias<"mvn $Xd, $Xm$sh",
750 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
752 def : InstAlias<"tst $src1, $src2",
753 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
754 def : InstAlias<"tst $src1, $src2",
755 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
757 def : InstAlias<"tst $src1, $src2",
758 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
759 def : InstAlias<"tst $src1, $src2",
760 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
762 def : InstAlias<"tst $src1, $src2$sh",
763 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
764 def : InstAlias<"tst $src1, $src2$sh",
765 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
768 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
769 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
772 //===----------------------------------------------------------------------===//
773 // One operand data processing instructions.
774 //===----------------------------------------------------------------------===//
776 defm CLS : OneOperandData<0b101, "cls">;
777 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
778 defm RBIT : OneOperandData<0b000, "rbit">;
780 def : Pat<(int_aarch64_rbit GPR32:$Rn), (RBITWr $Rn)>;
781 def : Pat<(int_aarch64_rbit GPR64:$Rn), (RBITXr $Rn)>;
783 def REV16Wr : OneWRegData<0b001, "rev16",
784 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
785 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
787 def : Pat<(cttz GPR32:$Rn),
788 (CLZWr (RBITWr GPR32:$Rn))>;
789 def : Pat<(cttz GPR64:$Rn),
790 (CLZXr (RBITXr GPR64:$Rn))>;
791 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
794 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
798 // Unlike the other one operand instructions, the instructions with the "rev"
799 // mnemonic do *not* just different in the size bit, but actually use different
800 // opcode bits for the different sizes.
801 def REVWr : OneWRegData<0b010, "rev", bswap>;
802 def REVXr : OneXRegData<0b011, "rev", bswap>;
803 def REV32Xr : OneXRegData<0b010, "rev32",
804 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
806 // The bswap commutes with the rotr so we want a pattern for both possible
808 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
809 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
811 //===----------------------------------------------------------------------===//
812 // Bitfield immediate extraction instruction.
813 //===----------------------------------------------------------------------===//
814 let hasSideEffects = 0 in
815 defm EXTR : ExtractImm<"extr">;
816 def : InstAlias<"ror $dst, $src, $shift",
817 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
818 def : InstAlias<"ror $dst, $src, $shift",
819 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
821 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
822 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
823 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
824 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
826 //===----------------------------------------------------------------------===//
827 // Other bitfield immediate instructions.
828 //===----------------------------------------------------------------------===//
829 let hasSideEffects = 0 in {
830 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
831 defm SBFM : BitfieldImm<0b00, "sbfm">;
832 defm UBFM : BitfieldImm<0b10, "ubfm">;
835 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
836 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
837 return CurDAG->getTargetConstant(enc, MVT::i64);
840 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
841 uint64_t enc = 31 - N->getZExtValue();
842 return CurDAG->getTargetConstant(enc, MVT::i64);
845 // min(7, 31 - shift_amt)
846 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
847 uint64_t enc = 31 - N->getZExtValue();
848 enc = enc > 7 ? 7 : enc;
849 return CurDAG->getTargetConstant(enc, MVT::i64);
852 // min(15, 31 - shift_amt)
853 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
854 uint64_t enc = 31 - N->getZExtValue();
855 enc = enc > 15 ? 15 : enc;
856 return CurDAG->getTargetConstant(enc, MVT::i64);
859 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
860 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
861 return CurDAG->getTargetConstant(enc, MVT::i64);
864 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
865 uint64_t enc = 63 - N->getZExtValue();
866 return CurDAG->getTargetConstant(enc, MVT::i64);
869 // min(7, 63 - shift_amt)
870 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
871 uint64_t enc = 63 - N->getZExtValue();
872 enc = enc > 7 ? 7 : enc;
873 return CurDAG->getTargetConstant(enc, MVT::i64);
876 // min(15, 63 - shift_amt)
877 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
878 uint64_t enc = 63 - N->getZExtValue();
879 enc = enc > 15 ? 15 : enc;
880 return CurDAG->getTargetConstant(enc, MVT::i64);
883 // min(31, 63 - shift_amt)
884 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
885 uint64_t enc = 63 - N->getZExtValue();
886 enc = enc > 31 ? 31 : enc;
887 return CurDAG->getTargetConstant(enc, MVT::i64);
890 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
891 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
892 (i64 (i32shift_b imm0_31:$imm)))>;
893 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
894 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
895 (i64 (i64shift_b imm0_63:$imm)))>;
897 let AddedComplexity = 10 in {
898 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
899 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
900 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
901 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
904 def : InstAlias<"asr $dst, $src, $shift",
905 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
906 def : InstAlias<"asr $dst, $src, $shift",
907 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
908 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
909 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
910 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
911 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
912 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
914 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
915 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
916 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
917 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
919 def : InstAlias<"lsr $dst, $src, $shift",
920 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
921 def : InstAlias<"lsr $dst, $src, $shift",
922 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
923 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
924 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
925 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
926 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
927 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
929 //===----------------------------------------------------------------------===//
930 // Conditionally set flags instructions.
931 //===----------------------------------------------------------------------===//
932 defm CCMN : CondSetFlagsImm<0, "ccmn">;
933 defm CCMP : CondSetFlagsImm<1, "ccmp">;
935 defm CCMN : CondSetFlagsReg<0, "ccmn">;
936 defm CCMP : CondSetFlagsReg<1, "ccmp">;
938 //===----------------------------------------------------------------------===//
939 // Conditional select instructions.
940 //===----------------------------------------------------------------------===//
941 defm CSEL : CondSelect<0, 0b00, "csel">;
943 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
944 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
945 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
946 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
948 def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
949 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
950 def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
951 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
952 def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
953 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
954 def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
955 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
956 def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
957 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
958 def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
959 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
961 def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
962 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
963 def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
964 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
965 def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
966 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
967 def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
968 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
970 // The inverse of the condition code from the alias instruction is what is used
971 // in the aliased instruction. The parser all ready inverts the condition code
972 // for these aliases.
973 def : InstAlias<"cset $dst, $cc",
974 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
975 def : InstAlias<"cset $dst, $cc",
976 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
978 def : InstAlias<"csetm $dst, $cc",
979 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
980 def : InstAlias<"csetm $dst, $cc",
981 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
983 def : InstAlias<"cinc $dst, $src, $cc",
984 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
985 def : InstAlias<"cinc $dst, $src, $cc",
986 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
988 def : InstAlias<"cinv $dst, $src, $cc",
989 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
990 def : InstAlias<"cinv $dst, $src, $cc",
991 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
993 def : InstAlias<"cneg $dst, $src, $cc",
994 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
995 def : InstAlias<"cneg $dst, $src, $cc",
996 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
998 //===----------------------------------------------------------------------===//
999 // PC-relative instructions.
1000 //===----------------------------------------------------------------------===//
1001 let isReMaterializable = 1 in {
1002 let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in {
1003 def ADR : ADRI<0, "adr", adrlabel, []>;
1004 } // hasSideEffects = 0
1006 def ADRP : ADRI<1, "adrp", adrplabel,
1007 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;
1008 } // isReMaterializable = 1
1010 // page address of a constant pool entry, block address
1011 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
1012 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
1014 //===----------------------------------------------------------------------===//
1015 // Unconditional branch (register) instructions.
1016 //===----------------------------------------------------------------------===//
1018 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1019 def RET : BranchReg<0b0010, "ret", []>;
1020 def DRPS : SpecialReturn<0b0101, "drps">;
1021 def ERET : SpecialReturn<0b0100, "eret">;
1022 } // isReturn = 1, isTerminator = 1, isBarrier = 1
1024 // Default to the LR register.
1025 def : InstAlias<"ret", (RET LR)>;
1027 let isCall = 1, Defs = [LR], Uses = [SP] in {
1028 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
1031 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1032 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
1033 } // isBranch, isTerminator, isBarrier, isIndirectBranch
1035 // Create a separate pseudo-instruction for codegen to use so that we don't
1036 // flag lr as used in every function. It'll be restored before the RET by the
1037 // epilogue if it's legitimately used.
1038 def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]> {
1039 let isTerminator = 1;
1044 // This is a directive-like pseudo-instruction. The purpose is to insert an
1045 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
1046 // (which in the usual case is a BLR).
1047 let hasSideEffects = 1 in
1048 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
1049 let AsmString = ".tlsdesccall $sym";
1052 // Pseudo-instruction representing a BLR with attached TLSDESC relocation. It
1053 // gets expanded to two MCInsts during lowering.
1054 let isCall = 1, Defs = [LR] in
1056 : Pseudo<(outs), (ins GPR64:$dest, i64imm:$sym),
1057 [(AArch64tlsdesc_call GPR64:$dest, tglobaltlsaddr:$sym)]>;
1059 def : Pat<(AArch64tlsdesc_call GPR64:$dest, texternalsym:$sym),
1060 (TLSDESC_BLR GPR64:$dest, texternalsym:$sym)>;
1061 //===----------------------------------------------------------------------===//
1062 // Conditional branch (immediate) instruction.
1063 //===----------------------------------------------------------------------===//
1064 def Bcc : BranchCond;
1066 //===----------------------------------------------------------------------===//
1067 // Compare-and-branch instructions.
1068 //===----------------------------------------------------------------------===//
1069 defm CBZ : CmpBranch<0, "cbz", AArch64cbz>;
1070 defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>;
1072 //===----------------------------------------------------------------------===//
1073 // Test-bit-and-branch instructions.
1074 //===----------------------------------------------------------------------===//
1075 defm TBZ : TestBranch<0, "tbz", AArch64tbz>;
1076 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;
1078 //===----------------------------------------------------------------------===//
1079 // Unconditional branch (immediate) instructions.
1080 //===----------------------------------------------------------------------===//
1081 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1082 def B : BranchImm<0, "b", [(br bb:$addr)]>;
1083 } // isBranch, isTerminator, isBarrier
1085 let isCall = 1, Defs = [LR], Uses = [SP] in {
1086 def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>;
1088 def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>;
1090 //===----------------------------------------------------------------------===//
1091 // Exception generation instructions.
1092 //===----------------------------------------------------------------------===//
1093 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1094 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1095 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
1096 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1097 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1098 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1099 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1100 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1102 // DCPSn defaults to an immediate operand of zero if unspecified.
1103 def : InstAlias<"dcps1", (DCPS1 0)>;
1104 def : InstAlias<"dcps2", (DCPS2 0)>;
1105 def : InstAlias<"dcps3", (DCPS3 0)>;
1107 //===----------------------------------------------------------------------===//
1108 // Load instructions.
1109 //===----------------------------------------------------------------------===//
1111 // Pair (indexed, offset)
1112 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1113 defm LDPX : LoadPairOffset<0b10, 0, GPR64, simm7s8, "ldp">;
1114 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1115 defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">;
1116 defm LDPQ : LoadPairOffset<0b10, 1, FPR128, simm7s16, "ldp">;
1118 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
1120 // Pair (pre-indexed)
1121 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1122 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1123 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1124 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1125 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1127 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1129 // Pair (post-indexed)
1130 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1131 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1132 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1133 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1134 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1136 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1139 // Pair (no allocate)
1140 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1141 defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64, simm7s8, "ldnp">;
1142 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1143 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">;
1144 defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128, simm7s16, "ldnp">;
1147 // (register offset)
1151 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1152 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;
1153 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
1154 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1157 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1158 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16, "ldr", f16, load>;
1159 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32, "ldr", f32, load>;
1160 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>;
1161 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1163 // Load sign-extended half-word
1164 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1165 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;
1167 // Load sign-extended byte
1168 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1169 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1171 // Load sign-extended word
1172 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;
1175 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
1177 // For regular load, we do not have any alignment requirement.
1178 // Thus, it is safe to directly map the vector loads with interesting
1179 // addressing modes.
1180 // FIXME: We could do the same for bitconvert to floating point vectors.
1181 multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop,
1182 ValueType ScalTy, ValueType VecTy,
1183 Instruction LOADW, Instruction LOADX,
1185 def : Pat<(VecTy (scalar_to_vector (ScalTy
1186 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))),
1187 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1188 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset),
1191 def : Pat<(VecTy (scalar_to_vector (ScalTy
1192 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))),
1193 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1194 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset),
1198 let AddedComplexity = 10 in {
1199 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>;
1200 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>;
1202 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1203 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1205 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
1206 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1208 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
1209 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
1211 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
1212 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
1214 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
1216 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1219 def : Pat <(v1i64 (scalar_to_vector (i64
1220 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
1221 ro_Wextend64:$extend))))),
1222 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
1224 def : Pat <(v1i64 (scalar_to_vector (i64
1225 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
1226 ro_Xextend64:$extend))))),
1227 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
1230 // Match all load 64 bits width whose type is compatible with FPR64
1231 multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy,
1232 Instruction LOADW, Instruction LOADX> {
1234 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1235 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1237 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1238 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1241 let AddedComplexity = 10 in {
1242 let Predicates = [IsLE] in {
1243 // We must do vector loads with LD1 in big-endian.
1244 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;
1245 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
1246 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;
1247 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>;
1248 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>;
1251 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
1252 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1254 // Match all load 128 bits width whose type is compatible with FPR128
1255 let Predicates = [IsLE] in {
1256 // We must do vector loads with LD1 in big-endian.
1257 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>;
1258 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
1259 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;
1260 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
1261 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;
1262 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;
1263 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;
1265 } // AddedComplexity = 10
1268 multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop,
1269 Instruction INSTW, Instruction INSTX> {
1270 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1271 (SUBREG_TO_REG (i64 0),
1272 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
1275 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1276 (SUBREG_TO_REG (i64 0),
1277 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
1281 let AddedComplexity = 10 in {
1282 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>;
1283 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>;
1284 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>;
1286 // zextloadi1 -> zextloadi8
1287 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1289 // extload -> zextload
1290 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1291 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1292 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1294 // extloadi1 -> zextloadi8
1295 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>;
1300 multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop,
1301 Instruction INSTW, Instruction INSTX> {
1302 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1303 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1305 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1306 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1310 let AddedComplexity = 10 in {
1311 // extload -> zextload
1312 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1313 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1314 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1316 // zextloadi1 -> zextloadi8
1317 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1321 // (unsigned immediate)
1323 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr",
1325 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1326 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32, uimm12s4, "ldr",
1328 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1329 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1331 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>;
1332 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16, uimm12s2, "ldr",
1333 [(set (f16 FPR16:$Rt),
1334 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>;
1335 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32, uimm12s4, "ldr",
1336 [(set (f32 FPR32:$Rt),
1337 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1338 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr",
1339 [(set (f64 FPR64:$Rt),
1340 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1341 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1342 [(set (f128 FPR128:$Rt),
1343 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>;
1345 // For regular load, we do not have any alignment requirement.
1346 // Thus, it is safe to directly map the vector loads with interesting
1347 // addressing modes.
1348 // FIXME: We could do the same for bitconvert to floating point vectors.
1349 def : Pat <(v8i8 (scalar_to_vector (i32
1350 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1351 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1352 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1353 def : Pat <(v16i8 (scalar_to_vector (i32
1354 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1355 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1356 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1357 def : Pat <(v4i16 (scalar_to_vector (i32
1358 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1359 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1360 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1361 def : Pat <(v8i16 (scalar_to_vector (i32
1362 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1363 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1364 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1365 def : Pat <(v2i32 (scalar_to_vector (i32
1366 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1367 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1368 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1369 def : Pat <(v4i32 (scalar_to_vector (i32
1370 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1371 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1372 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1373 def : Pat <(v1i64 (scalar_to_vector (i64
1374 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1375 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1376 def : Pat <(v2i64 (scalar_to_vector (i64
1377 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1378 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1379 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
1381 // Match all load 64 bits width whose type is compatible with FPR64
1382 let Predicates = [IsLE] in {
1383 // We must use LD1 to perform vector loads in big-endian.
1384 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1385 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1386 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1387 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1388 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1389 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1390 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1391 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1392 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1393 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1395 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1396 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1397 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1398 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1400 // Match all load 128 bits width whose type is compatible with FPR128
1401 let Predicates = [IsLE] in {
1402 // We must use LD1 to perform vector loads in big-endian.
1403 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1404 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1405 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1406 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1407 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1408 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1409 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1410 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1411 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1412 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1413 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1414 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1415 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1416 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1418 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1419 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1421 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
1423 (zextloadi16 (am_indexed16 GPR64sp:$Rn,
1424 uimm12s2:$offset)))]>;
1425 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1427 (zextloadi8 (am_indexed8 GPR64sp:$Rn,
1428 uimm12s1:$offset)))]>;
1430 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1431 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1432 def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1433 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1435 // zextloadi1 -> zextloadi8
1436 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1437 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1438 def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1439 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1441 // extload -> zextload
1442 def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1443 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
1444 def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1445 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1446 def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1447 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1448 def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1449 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1450 def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1451 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1452 def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1453 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1454 def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1455 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1457 // load sign-extended half-word
1458 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
1460 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1461 uimm12s2:$offset)))]>;
1462 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",
1464 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1465 uimm12s2:$offset)))]>;
1467 // load sign-extended byte
1468 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1470 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1471 uimm12s1:$offset)))]>;
1472 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1474 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1475 uimm12s1:$offset)))]>;
1477 // load sign-extended word
1478 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
1480 (sextloadi32 (am_indexed32 GPR64sp:$Rn,
1481 uimm12s4:$offset)))]>;
1483 // load zero-extended word
1484 def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1485 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1488 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1489 [(AArch64Prefetch imm:$Rt,
1490 (am_indexed64 GPR64sp:$Rn,
1491 uimm12s8:$offset))]>;
1493 def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>;
1497 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1498 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1499 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1500 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1501 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1503 // load sign-extended word
1504 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1507 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1508 // [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1511 // (unscaled immediate)
1512 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur",
1514 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1515 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32, "ldur",
1517 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1518 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1520 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1521 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16, "ldur",
1523 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1524 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32, "ldur",
1525 [(set (f32 FPR32:$Rt),
1526 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1527 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur",
1528 [(set (f64 FPR64:$Rt),
1529 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1530 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1531 [(set (f128 FPR128:$Rt),
1532 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;
1535 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
1537 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1539 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1541 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1543 // Match all load 64 bits width whose type is compatible with FPR64
1544 let Predicates = [IsLE] in {
1545 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1546 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1547 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1548 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1549 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1550 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1551 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1552 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1553 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1554 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1556 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1557 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1558 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1559 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1561 // Match all load 128 bits width whose type is compatible with FPR128
1562 let Predicates = [IsLE] in {
1563 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1564 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1565 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1566 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1567 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1568 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1569 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1570 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1571 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1572 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1573 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1574 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1575 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1576 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1580 def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1581 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1582 def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1583 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1584 def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1585 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1586 def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1587 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1588 def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1589 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1590 def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1591 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1592 def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1593 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1595 def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1596 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1597 def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1598 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1599 def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1600 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1601 def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1602 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1603 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1604 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1605 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1606 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1607 def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1608 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1612 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1614 // Define new assembler match classes as we want to only match these when
1615 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1616 // associate a DiagnosticType either, as we want the diagnostic for the
1617 // canonical form (the scaled operand) to take precedence.
1618 class SImm9OffsetOperand<int Width> : AsmOperandClass {
1619 let Name = "SImm9OffsetFB" # Width;
1620 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">";
1621 let RenderMethod = "addImmOperands";
1624 def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>;
1625 def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>;
1626 def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>;
1627 def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>;
1628 def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>;
1630 def simm9_offset_fb8 : Operand<i64> {
1631 let ParserMatchClass = SImm9OffsetFB8Operand;
1633 def simm9_offset_fb16 : Operand<i64> {
1634 let ParserMatchClass = SImm9OffsetFB16Operand;
1636 def simm9_offset_fb32 : Operand<i64> {
1637 let ParserMatchClass = SImm9OffsetFB32Operand;
1639 def simm9_offset_fb64 : Operand<i64> {
1640 let ParserMatchClass = SImm9OffsetFB64Operand;
1642 def simm9_offset_fb128 : Operand<i64> {
1643 let ParserMatchClass = SImm9OffsetFB128Operand;
1646 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1647 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1648 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1649 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1650 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1651 (LDURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1652 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1653 (LDURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1654 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1655 (LDURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1656 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1657 (LDURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1658 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1659 (LDURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
1662 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1663 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1664 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1665 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1667 // load sign-extended half-word
1669 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
1671 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1673 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",
1675 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1677 // load sign-extended byte
1679 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1681 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1683 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1685 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1687 // load sign-extended word
1689 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",
1691 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1693 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1694 def : InstAlias<"ldrb $Rt, [$Rn, $offset]",
1695 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1696 def : InstAlias<"ldrh $Rt, [$Rn, $offset]",
1697 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1698 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1699 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1700 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1701 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1702 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1703 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1704 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1705 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1706 def : InstAlias<"ldrsw $Rt, [$Rn, $offset]",
1707 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1710 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1711 [(AArch64Prefetch imm:$Rt,
1712 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1715 // (unscaled immediate, unprivileged)
1716 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1717 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1719 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1720 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1722 // load sign-extended half-word
1723 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1724 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1726 // load sign-extended byte
1727 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1728 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1730 // load sign-extended word
1731 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1734 // (immediate pre-indexed)
1735 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1736 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1737 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1738 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1739 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1740 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1741 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1743 // load sign-extended half-word
1744 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1745 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1747 // load sign-extended byte
1748 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1749 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1751 // load zero-extended byte
1752 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1753 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1755 // load sign-extended word
1756 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1759 // (immediate post-indexed)
1760 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1761 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1762 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1763 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1764 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1765 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1766 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1768 // load sign-extended half-word
1769 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1770 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1772 // load sign-extended byte
1773 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1774 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1776 // load zero-extended byte
1777 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1778 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1780 // load sign-extended word
1781 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1783 //===----------------------------------------------------------------------===//
1784 // Store instructions.
1785 //===----------------------------------------------------------------------===//
1787 // Pair (indexed, offset)
1788 // FIXME: Use dedicated range-checked addressing mode operand here.
1789 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1790 defm STPX : StorePairOffset<0b10, 0, GPR64, simm7s8, "stp">;
1791 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1792 defm STPD : StorePairOffset<0b01, 1, FPR64, simm7s8, "stp">;
1793 defm STPQ : StorePairOffset<0b10, 1, FPR128, simm7s16, "stp">;
1795 // Pair (pre-indexed)
1796 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1797 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, simm7s8, "stp">;
1798 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1799 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, simm7s8, "stp">;
1800 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, simm7s16, "stp">;
1802 // Pair (pre-indexed)
1803 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1804 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1805 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1806 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1807 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1809 // Pair (no allocate)
1810 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
1811 defm STNPX : StorePairNoAlloc<0b10, 0, GPR64, simm7s8, "stnp">;
1812 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
1813 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64, simm7s8, "stnp">;
1814 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128, simm7s16, "stnp">;
1817 // (Register offset)
1820 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
1821 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
1822 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
1823 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
1827 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
1828 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
1829 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
1830 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
1831 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
1833 multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
1834 Instruction STRW, Instruction STRX> {
1836 def : Pat<(storeop GPR64:$Rt,
1837 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1838 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1839 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1841 def : Pat<(storeop GPR64:$Rt,
1842 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1843 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1844 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1847 let AddedComplexity = 10 in {
1849 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>;
1850 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>;
1851 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>;
1854 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
1855 Instruction STRW, Instruction STRX> {
1856 def : Pat<(store (VecTy FPR:$Rt),
1857 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1858 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1860 def : Pat<(store (VecTy FPR:$Rt),
1861 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1862 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1865 let AddedComplexity = 10 in {
1866 // Match all store 64 bits width whose type is compatible with FPR64
1867 let Predicates = [IsLE] in {
1868 // We must use ST1 to store vectors in big-endian.
1869 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
1870 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
1871 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
1872 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;
1873 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>;
1876 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
1877 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
1879 // Match all store 128 bits width whose type is compatible with FPR128
1880 let Predicates = [IsLE] in {
1881 // We must use ST1 to store vectors in big-endian.
1882 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;
1883 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
1884 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;
1885 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
1886 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>;
1887 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>;
1888 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;
1890 } // AddedComplexity = 10
1893 // (unsigned immediate)
1894 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
1896 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1897 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
1899 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1900 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
1902 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>;
1903 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
1904 [(store (f16 FPR16:$Rt),
1905 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>;
1906 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
1907 [(store (f32 FPR32:$Rt),
1908 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1909 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
1910 [(store (f64 FPR64:$Rt),
1911 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1912 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
1914 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
1915 [(truncstorei16 GPR32:$Rt,
1916 (am_indexed16 GPR64sp:$Rn,
1917 uimm12s2:$offset))]>;
1918 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
1919 [(truncstorei8 GPR32:$Rt,
1920 (am_indexed8 GPR64sp:$Rn,
1921 uimm12s1:$offset))]>;
1923 // Match all store 64 bits width whose type is compatible with FPR64
1924 let AddedComplexity = 10 in {
1925 let Predicates = [IsLE] in {
1926 // We must use ST1 to store vectors in big-endian.
1927 def : Pat<(store (v2f32 FPR64:$Rt),
1928 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1929 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1930 def : Pat<(store (v8i8 FPR64:$Rt),
1931 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1932 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1933 def : Pat<(store (v4i16 FPR64:$Rt),
1934 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1935 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1936 def : Pat<(store (v2i32 FPR64:$Rt),
1937 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1938 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1939 def : Pat<(store (v4f16 FPR64:$Rt),
1940 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1941 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1943 def : Pat<(store (v1f64 FPR64:$Rt),
1944 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1945 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1946 def : Pat<(store (v1i64 FPR64:$Rt),
1947 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1948 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1950 // Match all store 128 bits width whose type is compatible with FPR128
1951 let Predicates = [IsLE] in {
1952 // We must use ST1 to store vectors in big-endian.
1953 def : Pat<(store (v4f32 FPR128:$Rt),
1954 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1955 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1956 def : Pat<(store (v2f64 FPR128:$Rt),
1957 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1958 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1959 def : Pat<(store (v16i8 FPR128:$Rt),
1960 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1961 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1962 def : Pat<(store (v8i16 FPR128:$Rt),
1963 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1964 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1965 def : Pat<(store (v4i32 FPR128:$Rt),
1966 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1967 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1968 def : Pat<(store (v2i64 FPR128:$Rt),
1969 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1970 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1971 def : Pat<(store (v8f16 FPR128:$Rt),
1972 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1973 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1975 def : Pat<(store (f128 FPR128:$Rt),
1976 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1977 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1980 def : Pat<(truncstorei32 GPR64:$Rt,
1981 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
1982 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;
1983 def : Pat<(truncstorei16 GPR64:$Rt,
1984 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
1985 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;
1986 def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
1987 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>;
1989 } // AddedComplexity = 10
1992 // (unscaled immediate)
1993 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
1995 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1996 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
1998 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
1999 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
2001 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2002 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
2003 [(store (f16 FPR16:$Rt),
2004 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2005 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
2006 [(store (f32 FPR32:$Rt),
2007 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2008 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
2009 [(store (f64 FPR64:$Rt),
2010 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2011 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
2012 [(store (f128 FPR128:$Rt),
2013 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;
2014 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
2015 [(truncstorei16 GPR32:$Rt,
2016 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2017 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
2018 [(truncstorei8 GPR32:$Rt,
2019 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2021 // Match all store 64 bits width whose type is compatible with FPR64
2022 let Predicates = [IsLE] in {
2023 // We must use ST1 to store vectors in big-endian.
2024 def : Pat<(store (v2f32 FPR64:$Rt),
2025 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2026 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2027 def : Pat<(store (v8i8 FPR64:$Rt),
2028 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2029 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2030 def : Pat<(store (v4i16 FPR64:$Rt),
2031 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2032 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2033 def : Pat<(store (v2i32 FPR64:$Rt),
2034 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2035 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2036 def : Pat<(store (v4f16 FPR64:$Rt),
2037 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2038 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2040 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2041 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2042 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2043 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2045 // Match all store 128 bits width whose type is compatible with FPR128
2046 let Predicates = [IsLE] in {
2047 // We must use ST1 to store vectors in big-endian.
2048 def : Pat<(store (v4f32 FPR128:$Rt),
2049 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2050 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2051 def : Pat<(store (v2f64 FPR128:$Rt),
2052 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2053 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2054 def : Pat<(store (v16i8 FPR128:$Rt),
2055 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2056 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2057 def : Pat<(store (v8i16 FPR128:$Rt),
2058 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2059 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2060 def : Pat<(store (v4i32 FPR128:$Rt),
2061 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2062 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2063 def : Pat<(store (v2i64 FPR128:$Rt),
2064 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2065 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2066 def : Pat<(store (v2f64 FPR128:$Rt),
2067 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2068 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2069 def : Pat<(store (v8f16 FPR128:$Rt),
2070 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2071 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2074 // unscaled i64 truncating stores
2075 def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
2076 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2077 def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2078 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2079 def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
2080 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2083 // STR mnemonics fall back to STUR for negative or unaligned offsets.
2084 def : InstAlias<"str $Rt, [$Rn, $offset]",
2085 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2086 def : InstAlias<"str $Rt, [$Rn, $offset]",
2087 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2088 def : InstAlias<"str $Rt, [$Rn, $offset]",
2089 (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2090 def : InstAlias<"str $Rt, [$Rn, $offset]",
2091 (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2092 def : InstAlias<"str $Rt, [$Rn, $offset]",
2093 (STURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2094 def : InstAlias<"str $Rt, [$Rn, $offset]",
2095 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2096 def : InstAlias<"str $Rt, [$Rn, $offset]",
2097 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
2099 def : InstAlias<"strb $Rt, [$Rn, $offset]",
2100 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2101 def : InstAlias<"strh $Rt, [$Rn, $offset]",
2102 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2105 // (unscaled immediate, unprivileged)
2106 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2107 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2109 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2110 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2113 // (immediate pre-indexed)
2114 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2115 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2116 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2117 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2118 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2119 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2120 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2122 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2123 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2126 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2127 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2129 def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2130 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2132 def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2133 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2136 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2137 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2138 def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2139 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2140 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2141 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2142 def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2143 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2144 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2145 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2146 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2147 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2148 def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2149 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2151 def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2152 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2153 def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2154 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2155 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2156 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2157 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2158 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2159 def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2160 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2161 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2162 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2163 def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2164 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2167 // (immediate post-indexed)
2168 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2169 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2170 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2171 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2172 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2173 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2174 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2176 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2177 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2180 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2181 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2183 def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2184 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2186 def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2187 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2190 def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2191 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2192 def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2193 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2194 def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2195 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2196 def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2197 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2198 def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2199 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2200 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2201 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2202 def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2203 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2205 def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2206 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2207 def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2208 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2209 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2210 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2211 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2212 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2213 def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2214 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2215 def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2216 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2217 def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2218 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2220 //===----------------------------------------------------------------------===//
2221 // Load/store exclusive instructions.
2222 //===----------------------------------------------------------------------===//
2224 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
2225 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2226 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2227 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2229 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2230 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2231 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2232 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2234 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
2235 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2236 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2237 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2239 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
2240 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2241 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2242 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2244 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
2245 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2246 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2247 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2249 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
2250 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2251 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2252 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2254 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
2255 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2257 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
2258 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2260 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
2261 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2263 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
2264 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2266 //===----------------------------------------------------------------------===//
2267 // Scaled floating point to integer conversion instructions.
2268 //===----------------------------------------------------------------------===//
2270 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2271 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2272 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
2273 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;
2274 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2275 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2276 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
2277 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
2278 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2279 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2280 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2281 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2282 let isCodeGenOnly = 1 in {
2283 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2284 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2285 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2286 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2289 //===----------------------------------------------------------------------===//
2290 // Scaled integer to floating point conversion instructions.
2291 //===----------------------------------------------------------------------===//
2293 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2294 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2296 //===----------------------------------------------------------------------===//
2297 // Unscaled integer to floating point conversion instruction.
2298 //===----------------------------------------------------------------------===//
2300 defm FMOV : UnscaledConversion<"fmov">;
2302 def : Pat<(f32 (fpimm0)), (FMOVWSr WZR)>, Requires<[NoZCZ]>;
2303 def : Pat<(f64 (fpimm0)), (FMOVXDr XZR)>, Requires<[NoZCZ]>;
2305 //===----------------------------------------------------------------------===//
2306 // Floating point conversion instruction.
2307 //===----------------------------------------------------------------------===//
2309 defm FCVT : FPConversion<"fcvt">;
2311 //===----------------------------------------------------------------------===//
2312 // Floating point single operand instructions.
2313 //===----------------------------------------------------------------------===//
2315 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2316 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2317 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2318 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2319 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2320 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2321 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>;
2322 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2324 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
2325 (FRINTNDr FPR64:$Rn)>;
2327 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
2328 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
2329 // <rdar://problem/13715968>
2330 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2331 let hasSideEffects = 1 in {
2332 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2335 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2337 let SchedRW = [WriteFDiv] in {
2338 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2341 //===----------------------------------------------------------------------===//
2342 // Floating point two operand instructions.
2343 //===----------------------------------------------------------------------===//
2345 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2346 let SchedRW = [WriteFDiv] in {
2347 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2349 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_aarch64_neon_fmaxnm>;
2350 defm FMAX : TwoOperandFPData<0b0100, "fmax", AArch64fmax>;
2351 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_aarch64_neon_fminnm>;
2352 defm FMIN : TwoOperandFPData<0b0101, "fmin", AArch64fmin>;
2353 let SchedRW = [WriteFMul] in {
2354 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2355 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2357 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2359 def : Pat<(v1f64 (AArch64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2360 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2361 def : Pat<(v1f64 (AArch64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2362 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2363 def : Pat<(v1f64 (int_aarch64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2364 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2365 def : Pat<(v1f64 (int_aarch64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2366 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2368 //===----------------------------------------------------------------------===//
2369 // Floating point three operand instructions.
2370 //===----------------------------------------------------------------------===//
2372 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2373 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2374 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2375 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2376 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2377 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2378 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2380 // The following def pats catch the case where the LHS of an FMA is negated.
2381 // The TriOpFrag above catches the case where the middle operand is negated.
2383 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2384 // the NEON variant.
2385 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2386 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2388 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2389 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2391 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2393 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2394 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2396 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2397 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2399 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2400 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2402 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2403 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2405 //===----------------------------------------------------------------------===//
2406 // Floating point comparison instructions.
2407 //===----------------------------------------------------------------------===//
2409 defm FCMPE : FPComparison<1, "fcmpe">;
2410 defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>;
2412 //===----------------------------------------------------------------------===//
2413 // Floating point conditional comparison instructions.
2414 //===----------------------------------------------------------------------===//
2416 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2417 defm FCCMP : FPCondComparison<0, "fccmp">;
2419 //===----------------------------------------------------------------------===//
2420 // Floating point conditional select instruction.
2421 //===----------------------------------------------------------------------===//
2423 defm FCSEL : FPCondSelect<"fcsel">;
2425 // CSEL instructions providing f128 types need to be handled by a
2426 // pseudo-instruction since the eventual code will need to introduce basic
2427 // blocks and control flow.
2428 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2429 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2430 [(set (f128 FPR128:$Rd),
2431 (AArch64csel FPR128:$Rn, FPR128:$Rm,
2432 (i32 imm:$cond), NZCV))]> {
2434 let usesCustomInserter = 1;
2438 //===----------------------------------------------------------------------===//
2439 // Floating point immediate move.
2440 //===----------------------------------------------------------------------===//
2442 let isReMaterializable = 1 in {
2443 defm FMOV : FPMoveImmediate<"fmov">;
2446 //===----------------------------------------------------------------------===//
2447 // Advanced SIMD two vector instructions.
2448 //===----------------------------------------------------------------------===//
2450 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_aarch64_neon_abs>;
2451 def : Pat<(xor (v8i8 (AArch64vashr V64:$src, (i32 7))),
2452 (v8i8 (add V64:$src, (AArch64vashr V64:$src, (i32 7))))),
2453 (ABSv8i8 V64:$src)>;
2454 def : Pat<(xor (v4i16 (AArch64vashr V64:$src, (i32 15))),
2455 (v4i16 (add V64:$src, (AArch64vashr V64:$src, (i32 15))))),
2456 (ABSv4i16 V64:$src)>;
2457 def : Pat<(xor (v2i32 (AArch64vashr V64:$src, (i32 31))),
2458 (v2i32 (add V64:$src, (AArch64vashr V64:$src, (i32 31))))),
2459 (ABSv2i32 V64:$src)>;
2460 def : Pat<(xor (v16i8 (AArch64vashr V128:$src, (i32 7))),
2461 (v16i8 (add V128:$src, (AArch64vashr V128:$src, (i32 7))))),
2462 (ABSv16i8 V128:$src)>;
2463 def : Pat<(xor (v8i16 (AArch64vashr V128:$src, (i32 15))),
2464 (v8i16 (add V128:$src, (AArch64vashr V128:$src, (i32 15))))),
2465 (ABSv8i16 V128:$src)>;
2466 def : Pat<(xor (v4i32 (AArch64vashr V128:$src, (i32 31))),
2467 (v4i32 (add V128:$src, (AArch64vashr V128:$src, (i32 31))))),
2468 (ABSv4i32 V128:$src)>;
2469 def : Pat<(xor (v2i64 (AArch64vashr V128:$src, (i32 63))),
2470 (v2i64 (add V128:$src, (AArch64vashr V128:$src, (i32 63))))),
2471 (ABSv2i64 V128:$src)>;
2473 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
2474 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2475 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;
2476 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;
2477 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
2478 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;
2479 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;
2480 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2481 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2483 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2484 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2485 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2486 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2487 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2488 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>;
2489 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;
2490 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2491 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2492 (FCVTLv4i16 V64:$Rn)>;
2493 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2495 (FCVTLv8i16 V128:$Rn)>;
2496 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2497 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2499 (FCVTLv4i32 V128:$Rn)>;
2501 def : Pat<(v4f32 (fextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>;
2502 def : Pat<(v4f32 (fextend (v4f16 (extract_subvector (v8f16 V128:$Rn),
2504 (FCVTLv8i16 V128:$Rn)>;
2506 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;
2507 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;
2508 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>;
2509 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>;
2510 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2511 def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2512 (FCVTNv4i16 V128:$Rn)>;
2513 def : Pat<(concat_vectors V64:$Rd,
2514 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2515 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2516 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2517 def : Pat<(v4f16 (fround (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>;
2518 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2519 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2520 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
2521 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
2522 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2523 int_aarch64_neon_fcvtxn>;
2524 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2525 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2526 let isCodeGenOnly = 1 in {
2527 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2528 int_aarch64_neon_fcvtzs>;
2529 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2530 int_aarch64_neon_fcvtzu>;
2532 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2533 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;
2534 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2535 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2536 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2537 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>;
2538 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2539 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2540 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2541 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>;
2542 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2543 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2544 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2545 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2546 // Aliases for MVN -> NOT.
2547 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2548 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2549 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2550 (NOTv16i8 V128:$Vd, V128:$Vn)>;
2552 def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2553 def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2554 def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2555 def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2556 def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2557 def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2558 def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2560 def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2561 def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2562 def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2563 def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2564 def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2565 def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2566 def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2567 def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2569 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2570 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2571 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2572 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2573 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2575 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>;
2576 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
2577 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>;
2578 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
2579 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2580 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >;
2581 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>;
2582 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2583 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2584 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2585 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2586 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>;
2587 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>;
2588 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>;
2589 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2590 BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >;
2591 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2592 int_aarch64_neon_uaddlp>;
2593 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2594 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>;
2595 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>;
2596 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;
2597 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>;
2598 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2600 def : Pat<(v4f16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>;
2601 def : Pat<(v4f16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>;
2602 def : Pat<(v8f16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>;
2603 def : Pat<(v8f16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>;
2604 def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2605 def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2607 // Patterns for vector long shift (by element width). These need to match all
2608 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2610 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2611 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2612 (SHLLv8i8 V64:$Rn)>;
2613 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2614 (SHLLv16i8 V128:$Rn)>;
2615 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2616 (SHLLv4i16 V64:$Rn)>;
2617 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2618 (SHLLv8i16 V128:$Rn)>;
2619 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2620 (SHLLv2i32 V64:$Rn)>;
2621 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2622 (SHLLv4i32 V128:$Rn)>;
2625 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2626 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2627 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2629 //===----------------------------------------------------------------------===//
2630 // Advanced SIMD three vector instructions.
2631 //===----------------------------------------------------------------------===//
2633 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2634 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
2635 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
2636 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
2637 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
2638 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
2639 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
2640 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
2641 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_aarch64_neon_fabd>;
2642 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_aarch64_neon_facge>;
2643 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_aarch64_neon_facgt>;
2644 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_aarch64_neon_addp>;
2645 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2646 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2647 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2648 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2649 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2650 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
2651 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_aarch64_neon_fmaxnm>;
2652 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_aarch64_neon_fmaxp>;
2653 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", AArch64fmax>;
2654 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_aarch64_neon_fminnmp>;
2655 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_aarch64_neon_fminnm>;
2656 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_aarch64_neon_fminp>;
2657 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", AArch64fmin>;
2659 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2660 // instruction expects the addend first, while the fma intrinsic puts it last.
2661 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2662 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2663 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2664 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2666 // The following def pats catch the case where the LHS of an FMA is negated.
2667 // The TriOpFrag above catches the case where the middle operand is negated.
2668 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2669 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2671 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2672 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2674 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2675 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2677 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_aarch64_neon_fmulx>;
2678 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2679 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_aarch64_neon_frecps>;
2680 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_aarch64_neon_frsqrts>;
2681 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2682 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2683 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2684 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2685 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2686 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2687 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
2688 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2689 TriOpFrag<(add node:$LHS, (int_aarch64_neon_sabd node:$MHS, node:$RHS))> >;
2690 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_aarch64_neon_sabd>;
2691 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>;
2692 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
2693 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
2694 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_aarch64_neon_smax>;
2695 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>;
2696 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_aarch64_neon_smin>;
2697 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>;
2698 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>;
2699 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>;
2700 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>;
2701 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>;
2702 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>;
2703 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>;
2704 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
2705 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
2706 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2707 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2708 TriOpFrag<(add node:$LHS, (int_aarch64_neon_uabd node:$MHS, node:$RHS))> >;
2709 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_aarch64_neon_uabd>;
2710 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>;
2711 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
2712 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
2713 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_aarch64_neon_umax>;
2714 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>;
2715 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_aarch64_neon_umin>;
2716 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>;
2717 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>;
2718 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>;
2719 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>;
2720 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>;
2721 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;
2722 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
2724 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2725 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2726 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2727 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2728 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>;
2729 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2730 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2731 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2732 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2733 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2734 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2736 // SABD Vd.<T>, Vn.<T>, Vm.<T> Subtracts the elements of Vm from the corresponding
2737 // elements of Vn, and places the absolute values of the results in the elements of Vd.
2738 def : Pat<(xor (v8i8 (AArch64vashr (v8i8(sub V64:$Rn, V64:$Rm)), (i32 7))),
2739 (v8i8 (add (v8i8(sub V64:$Rn, V64:$Rm)),
2740 (AArch64vashr (v8i8(sub V64:$Rn, V64:$Rm)), (i32 7))))),
2741 (SABDv8i8 V64:$Rn, V64:$Rm)>;
2742 def : Pat<(xor (v4i16 (AArch64vashr (v4i16(sub V64:$Rn, V64:$Rm)), (i32 15))),
2743 (v4i16 (add (v4i16(sub V64:$Rn, V64:$Rm)),
2744 (AArch64vashr (v4i16(sub V64:$Rn, V64:$Rm)), (i32 15))))),
2745 (SABDv4i16 V64:$Rn, V64:$Rm)>;
2746 def : Pat<(xor (v2i32 (AArch64vashr (v2i32(sub V64:$Rn, V64:$Rm)), (i32 31))),
2747 (v2i32 (add (v2i32(sub V64:$Rn, V64:$Rm)),
2748 (AArch64vashr (v2i32(sub V64:$Rn, V64:$Rm)), (i32 31))))),
2749 (SABDv2i32 V64:$Rn, V64:$Rm)>;
2750 def : Pat<(xor (v16i8 (AArch64vashr (v16i8(sub V128:$Rn, V128:$Rm)), (i32 7))),
2751 (v16i8 (add (v16i8(sub V128:$Rn, V128:$Rm)),
2752 (AArch64vashr (v16i8(sub V128:$Rn, V128:$Rm)), (i32 7))))),
2753 (SABDv16i8 V128:$Rn, V128:$Rm)>;
2754 def : Pat<(xor (v8i16 (AArch64vashr (v8i16(sub V128:$Rn, V128:$Rm)), (i32 15))),
2755 (v8i16 (add (v8i16(sub V128:$Rn, V128:$Rm)),
2756 (AArch64vashr (v8i16(sub V128:$Rn, V128:$Rm)), (i32 15))))),
2757 (SABDv8i16 V128:$Rn, V128:$Rm)>;
2758 def : Pat<(xor (v4i32 (AArch64vashr (v4i32(sub V128:$Rn, V128:$Rm)), (i32 31))),
2759 (v4i32 (add (v4i32(sub V128:$Rn, V128:$Rm)),
2760 (AArch64vashr (v4i32(sub V128:$Rn, V128:$Rm)), (i32 31))))),
2761 (SABDv4i32 V128:$Rn, V128:$Rm)>;
2763 def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2764 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2765 def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2766 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2767 def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2768 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2769 def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2770 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2772 def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2773 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2774 def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2775 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2776 def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2777 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2778 def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2779 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2781 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2782 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
2783 def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",
2784 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2785 def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}",
2786 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2787 def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}",
2788 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2790 def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}",
2791 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>;
2792 def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}",
2793 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2794 def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}",
2795 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2796 def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}",
2797 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2799 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2800 "|cmls.8b\t$dst, $src1, $src2}",
2801 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2802 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2803 "|cmls.16b\t$dst, $src1, $src2}",
2804 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2805 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2806 "|cmls.4h\t$dst, $src1, $src2}",
2807 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2808 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2809 "|cmls.8h\t$dst, $src1, $src2}",
2810 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2811 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2812 "|cmls.2s\t$dst, $src1, $src2}",
2813 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2814 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2815 "|cmls.4s\t$dst, $src1, $src2}",
2816 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2817 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2818 "|cmls.2d\t$dst, $src1, $src2}",
2819 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2821 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2822 "|cmlo.8b\t$dst, $src1, $src2}",
2823 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2824 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2825 "|cmlo.16b\t$dst, $src1, $src2}",
2826 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2827 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2828 "|cmlo.4h\t$dst, $src1, $src2}",
2829 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2830 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2831 "|cmlo.8h\t$dst, $src1, $src2}",
2832 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2833 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
2834 "|cmlo.2s\t$dst, $src1, $src2}",
2835 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2836 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
2837 "|cmlo.4s\t$dst, $src1, $src2}",
2838 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2839 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
2840 "|cmlo.2d\t$dst, $src1, $src2}",
2841 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2843 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
2844 "|cmle.8b\t$dst, $src1, $src2}",
2845 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2846 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
2847 "|cmle.16b\t$dst, $src1, $src2}",
2848 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2849 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
2850 "|cmle.4h\t$dst, $src1, $src2}",
2851 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2852 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
2853 "|cmle.8h\t$dst, $src1, $src2}",
2854 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2855 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
2856 "|cmle.2s\t$dst, $src1, $src2}",
2857 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2858 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
2859 "|cmle.4s\t$dst, $src1, $src2}",
2860 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2861 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
2862 "|cmle.2d\t$dst, $src1, $src2}",
2863 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2865 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
2866 "|cmlt.8b\t$dst, $src1, $src2}",
2867 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2868 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
2869 "|cmlt.16b\t$dst, $src1, $src2}",
2870 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2871 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
2872 "|cmlt.4h\t$dst, $src1, $src2}",
2873 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2874 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
2875 "|cmlt.8h\t$dst, $src1, $src2}",
2876 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2877 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
2878 "|cmlt.2s\t$dst, $src1, $src2}",
2879 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2880 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
2881 "|cmlt.4s\t$dst, $src1, $src2}",
2882 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2883 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
2884 "|cmlt.2d\t$dst, $src1, $src2}",
2885 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2887 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
2888 "|fcmle.2s\t$dst, $src1, $src2}",
2889 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2890 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
2891 "|fcmle.4s\t$dst, $src1, $src2}",
2892 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2893 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
2894 "|fcmle.2d\t$dst, $src1, $src2}",
2895 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2897 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
2898 "|fcmlt.2s\t$dst, $src1, $src2}",
2899 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2900 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
2901 "|fcmlt.4s\t$dst, $src1, $src2}",
2902 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2903 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
2904 "|fcmlt.2d\t$dst, $src1, $src2}",
2905 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2907 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
2908 "|facle.2s\t$dst, $src1, $src2}",
2909 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2910 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
2911 "|facle.4s\t$dst, $src1, $src2}",
2912 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2913 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
2914 "|facle.2d\t$dst, $src1, $src2}",
2915 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2917 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
2918 "|faclt.2s\t$dst, $src1, $src2}",
2919 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2920 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
2921 "|faclt.4s\t$dst, $src1, $src2}",
2922 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2923 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
2924 "|faclt.2d\t$dst, $src1, $src2}",
2925 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2927 //===----------------------------------------------------------------------===//
2928 // Advanced SIMD three scalar instructions.
2929 //===----------------------------------------------------------------------===//
2931 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
2932 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>;
2933 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
2934 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
2935 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
2936 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
2937 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
2938 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_aarch64_sisd_fabd>;
2939 def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2940 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
2941 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
2942 int_aarch64_neon_facge>;
2943 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
2944 int_aarch64_neon_facgt>;
2945 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2946 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2947 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2948 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_aarch64_neon_fmulx>;
2949 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_aarch64_neon_frecps>;
2950 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_aarch64_neon_frsqrts>;
2951 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>;
2952 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;
2953 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
2954 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>;
2955 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>;
2956 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>;
2957 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>;
2958 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;
2959 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
2960 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>;
2961 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>;
2962 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>;
2963 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>;
2964 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>;
2965 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;
2967 def : InstAlias<"cmls $dst, $src1, $src2",
2968 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2969 def : InstAlias<"cmle $dst, $src1, $src2",
2970 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2971 def : InstAlias<"cmlo $dst, $src1, $src2",
2972 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2973 def : InstAlias<"cmlt $dst, $src1, $src2",
2974 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2975 def : InstAlias<"fcmle $dst, $src1, $src2",
2976 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2977 def : InstAlias<"fcmle $dst, $src1, $src2",
2978 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2979 def : InstAlias<"fcmlt $dst, $src1, $src2",
2980 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2981 def : InstAlias<"fcmlt $dst, $src1, $src2",
2982 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2983 def : InstAlias<"facle $dst, $src1, $src2",
2984 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2985 def : InstAlias<"facle $dst, $src1, $src2",
2986 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2987 def : InstAlias<"faclt $dst, $src1, $src2",
2988 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2989 def : InstAlias<"faclt $dst, $src1, $src2",
2990 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2992 //===----------------------------------------------------------------------===//
2993 // Advanced SIMD three scalar instructions (mixed operands).
2994 //===----------------------------------------------------------------------===//
2995 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
2996 int_aarch64_neon_sqdmulls_scalar>;
2997 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
2998 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
3000 def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),
3001 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3002 (i32 FPR32:$Rm))))),
3003 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3004 def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),
3005 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3006 (i32 FPR32:$Rm))))),
3007 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
3009 //===----------------------------------------------------------------------===//
3010 // Advanced SIMD two scalar instructions.
3011 //===----------------------------------------------------------------------===//
3013 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_aarch64_neon_abs>;
3014 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;
3015 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;
3016 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;
3017 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>;
3018 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>;
3019 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
3020 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
3021 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
3022 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
3023 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
3024 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
3025 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
3026 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
3027 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
3028 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
3029 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
3030 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
3031 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
3032 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
3033 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
3034 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
3035 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
3036 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
3037 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
3038 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
3039 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
3040 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", AArch64sitof>;
3041 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
3042 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
3043 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>;
3044 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>;
3045 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
3046 int_aarch64_neon_suqadd>;
3047 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", AArch64uitof>;
3048 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>;
3049 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
3050 int_aarch64_neon_usqadd>;
3052 def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
3054 def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))),
3055 (FCVTASv1i64 FPR64:$Rn)>;
3056 def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))),
3057 (FCVTAUv1i64 FPR64:$Rn)>;
3058 def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))),
3059 (FCVTMSv1i64 FPR64:$Rn)>;
3060 def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))),
3061 (FCVTMUv1i64 FPR64:$Rn)>;
3062 def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))),
3063 (FCVTNSv1i64 FPR64:$Rn)>;
3064 def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))),
3065 (FCVTNUv1i64 FPR64:$Rn)>;
3066 def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),
3067 (FCVTPSv1i64 FPR64:$Rn)>;
3068 def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),
3069 (FCVTPUv1i64 FPR64:$Rn)>;
3071 def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),
3072 (FRECPEv1i32 FPR32:$Rn)>;
3073 def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),
3074 (FRECPEv1i64 FPR64:$Rn)>;
3075 def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))),
3076 (FRECPEv1i64 FPR64:$Rn)>;
3078 def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),
3079 (FRECPXv1i32 FPR32:$Rn)>;
3080 def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),
3081 (FRECPXv1i64 FPR64:$Rn)>;
3083 def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),
3084 (FRSQRTEv1i32 FPR32:$Rn)>;
3085 def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),
3086 (FRSQRTEv1i64 FPR64:$Rn)>;
3087 def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))),
3088 (FRSQRTEv1i64 FPR64:$Rn)>;
3090 // If an integer is about to be converted to a floating point value,
3091 // just load it on the floating point unit.
3092 // Here are the patterns for 8 and 16-bits to float.
3094 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
3095 SDPatternOperator loadop, Instruction UCVTF,
3096 ROAddrMode ro, Instruction LDRW, Instruction LDRX,
3098 def : Pat<(DstTy (uint_to_fp (SrcTy
3099 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm,
3100 ro.Wext:$extend))))),
3101 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3102 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
3105 def : Pat<(DstTy (uint_to_fp (SrcTy
3106 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm,
3107 ro.Wext:$extend))))),
3108 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3109 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
3113 defm : UIntToFPROLoadPat<f32, i32, zextloadi8,
3114 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>;
3115 def : Pat <(f32 (uint_to_fp (i32
3116 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3117 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3118 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3119 def : Pat <(f32 (uint_to_fp (i32
3120 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3121 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3122 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3123 // 16-bits -> float.
3124 defm : UIntToFPROLoadPat<f32, i32, zextloadi16,
3125 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
3126 def : Pat <(f32 (uint_to_fp (i32
3127 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3128 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3129 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3130 def : Pat <(f32 (uint_to_fp (i32
3131 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3132 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3133 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3134 // 32-bits are handled in target specific dag combine:
3135 // performIntToFpCombine.
3136 // 64-bits integer to 32-bits floating point, not possible with
3137 // UCVTF on floating point registers (both source and destination
3138 // must have the same size).
3140 // Here are the patterns for 8, 16, 32, and 64-bits to double.
3141 // 8-bits -> double.
3142 defm : UIntToFPROLoadPat<f64, i32, zextloadi8,
3143 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>;
3144 def : Pat <(f64 (uint_to_fp (i32
3145 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3146 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3147 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3148 def : Pat <(f64 (uint_to_fp (i32
3149 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3150 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3151 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3152 // 16-bits -> double.
3153 defm : UIntToFPROLoadPat<f64, i32, zextloadi16,
3154 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;
3155 def : Pat <(f64 (uint_to_fp (i32
3156 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3157 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3158 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3159 def : Pat <(f64 (uint_to_fp (i32
3160 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3161 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3162 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3163 // 32-bits -> double.
3164 defm : UIntToFPROLoadPat<f64, i32, load,
3165 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>;
3166 def : Pat <(f64 (uint_to_fp (i32
3167 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
3168 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3169 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;
3170 def : Pat <(f64 (uint_to_fp (i32
3171 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
3172 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3173 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
3174 // 64-bits -> double are handled in target specific dag combine:
3175 // performIntToFpCombine.
3177 //===----------------------------------------------------------------------===//
3178 // Advanced SIMD three different-sized vector instructions.
3179 //===----------------------------------------------------------------------===//
3181 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
3182 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
3183 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
3184 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
3185 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;
3186 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
3187 int_aarch64_neon_sabd>;
3188 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
3189 int_aarch64_neon_sabd>;
3190 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
3191 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
3192 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
3193 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
3194 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
3195 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3196 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
3197 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3198 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>;
3199 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
3200 int_aarch64_neon_sqadd>;
3201 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
3202 int_aarch64_neon_sqsub>;
3203 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
3204 int_aarch64_neon_sqdmull>;
3205 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
3206 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
3207 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
3208 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
3209 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
3210 int_aarch64_neon_uabd>;
3211 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
3212 int_aarch64_neon_uabd>;
3213 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
3214 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
3215 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
3216 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
3217 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
3218 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3219 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
3220 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3221 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>;
3222 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
3223 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
3224 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
3225 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
3227 // Additional patterns for SMULL and UMULL
3228 multiclass Neon_mul_widen_patterns<SDPatternOperator opnode,
3229 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3230 def : Pat<(v8i16 (opnode (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3231 (INST8B V64:$Rn, V64:$Rm)>;
3232 def : Pat<(v4i32 (opnode (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3233 (INST4H V64:$Rn, V64:$Rm)>;
3234 def : Pat<(v2i64 (opnode (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3235 (INST2S V64:$Rn, V64:$Rm)>;
3238 defm : Neon_mul_widen_patterns<AArch64smull, SMULLv8i8_v8i16,
3239 SMULLv4i16_v4i32, SMULLv2i32_v2i64>;
3240 defm : Neon_mul_widen_patterns<AArch64umull, UMULLv8i8_v8i16,
3241 UMULLv4i16_v4i32, UMULLv2i32_v2i64>;
3243 // Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL
3244 multiclass Neon_mulacc_widen_patterns<SDPatternOperator opnode,
3245 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3246 def : Pat<(v8i16 (opnode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3247 (INST8B V128:$Rd, V64:$Rn, V64:$Rm)>;
3248 def : Pat<(v4i32 (opnode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3249 (INST4H V128:$Rd, V64:$Rn, V64:$Rm)>;
3250 def : Pat<(v2i64 (opnode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3251 (INST2S V128:$Rd, V64:$Rn, V64:$Rm)>;
3254 defm : Neon_mulacc_widen_patterns<
3255 TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3256 SMLALv8i8_v8i16, SMLALv4i16_v4i32, SMLALv2i32_v2i64>;
3257 defm : Neon_mulacc_widen_patterns<
3258 TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3259 UMLALv8i8_v8i16, UMLALv4i16_v4i32, UMLALv2i32_v2i64>;
3260 defm : Neon_mulacc_widen_patterns<
3261 TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3262 SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>;
3263 defm : Neon_mulacc_widen_patterns<
3264 TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3265 UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>;
3267 // Patterns for 64-bit pmull
3268 def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm),
3269 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
3270 def : Pat<(int_aarch64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
3271 (vector_extract (v2i64 V128:$Rm), (i64 1))),
3272 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
3274 // CodeGen patterns for addhn and subhn instructions, which can actually be
3275 // written in LLVM IR without too much difficulty.
3278 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
3279 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3280 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3282 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3283 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3285 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3286 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3287 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3289 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3290 V128:$Rn, V128:$Rm)>;
3291 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3292 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3294 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3295 V128:$Rn, V128:$Rm)>;
3296 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3297 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3299 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3300 V128:$Rn, V128:$Rm)>;
3303 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
3304 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3305 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3307 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3308 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3310 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3311 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3312 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3314 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3315 V128:$Rn, V128:$Rm)>;
3316 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3317 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3319 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3320 V128:$Rn, V128:$Rm)>;
3321 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3322 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3324 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3325 V128:$Rn, V128:$Rm)>;
3327 //----------------------------------------------------------------------------
3328 // AdvSIMD bitwise extract from vector instruction.
3329 //----------------------------------------------------------------------------
3331 defm EXT : SIMDBitwiseExtract<"ext">;
3333 def : Pat<(v4i16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3334 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3335 def : Pat<(v8i16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3336 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3337 def : Pat<(v2i32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3338 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3339 def : Pat<(v2f32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3340 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3341 def : Pat<(v4i32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3342 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3343 def : Pat<(v4f32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3344 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3345 def : Pat<(v2i64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3346 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3347 def : Pat<(v2f64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3348 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3349 def : Pat<(v4f16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3350 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3351 def : Pat<(v8f16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3352 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3354 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
3356 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
3357 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3358 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
3359 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3360 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
3361 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3362 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
3363 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3364 def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 4))),
3365 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3366 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
3367 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3368 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
3369 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3372 //----------------------------------------------------------------------------
3373 // AdvSIMD zip vector
3374 //----------------------------------------------------------------------------
3376 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;
3377 defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>;
3378 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
3379 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;
3380 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
3381 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;
3383 //----------------------------------------------------------------------------
3384 // AdvSIMD TBL/TBX instructions
3385 //----------------------------------------------------------------------------
3387 defm TBL : SIMDTableLookup< 0, "tbl">;
3388 defm TBX : SIMDTableLookupTied<1, "tbx">;
3390 def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3391 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
3392 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3393 (TBLv16i8One V128:$Ri, V128:$Rn)>;
3395 def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),
3396 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3397 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
3398 def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),
3399 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3400 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
3403 //----------------------------------------------------------------------------
3404 // AdvSIMD scalar CPY instruction
3405 //----------------------------------------------------------------------------
3407 defm CPY : SIMDScalarCPY<"cpy">;
3409 //----------------------------------------------------------------------------
3410 // AdvSIMD scalar pairwise instructions
3411 //----------------------------------------------------------------------------
3413 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
3414 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
3415 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
3416 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
3417 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
3418 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
3419 def : Pat<(i64 (int_aarch64_neon_saddv (v2i64 V128:$Rn))),
3420 (ADDPv2i64p V128:$Rn)>;
3421 def : Pat<(i64 (int_aarch64_neon_uaddv (v2i64 V128:$Rn))),
3422 (ADDPv2i64p V128:$Rn)>;
3423 def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))),
3424 (FADDPv2i32p V64:$Rn)>;
3425 def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))),
3426 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
3427 def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))),
3428 (FADDPv2i64p V128:$Rn)>;
3429 def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))),
3430 (FMAXNMPv2i32p V64:$Rn)>;
3431 def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))),
3432 (FMAXNMPv2i64p V128:$Rn)>;
3433 def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))),
3434 (FMAXPv2i32p V64:$Rn)>;
3435 def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))),
3436 (FMAXPv2i64p V128:$Rn)>;
3437 def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))),
3438 (FMINNMPv2i32p V64:$Rn)>;
3439 def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))),
3440 (FMINNMPv2i64p V128:$Rn)>;
3441 def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))),
3442 (FMINPv2i32p V64:$Rn)>;
3443 def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))),
3444 (FMINPv2i64p V128:$Rn)>;
3446 //----------------------------------------------------------------------------
3447 // AdvSIMD INS/DUP instructions
3448 //----------------------------------------------------------------------------
3450 def DUPv8i8gpr : SIMDDupFromMain<0, 0b00001, ".8b", v8i8, V64, GPR32>;
3451 def DUPv16i8gpr : SIMDDupFromMain<1, 0b00001, ".16b", v16i8, V128, GPR32>;
3452 def DUPv4i16gpr : SIMDDupFromMain<0, 0b00010, ".4h", v4i16, V64, GPR32>;
3453 def DUPv8i16gpr : SIMDDupFromMain<1, 0b00010, ".8h", v8i16, V128, GPR32>;
3454 def DUPv2i32gpr : SIMDDupFromMain<0, 0b00100, ".2s", v2i32, V64, GPR32>;
3455 def DUPv4i32gpr : SIMDDupFromMain<1, 0b00100, ".4s", v4i32, V128, GPR32>;
3456 def DUPv2i64gpr : SIMDDupFromMain<1, 0b01000, ".2d", v2i64, V128, GPR64>;
3458 def DUPv2i64lane : SIMDDup64FromElement;
3459 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3460 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3461 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3462 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3463 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3464 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3466 def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))),
3467 (v2f32 (DUPv2i32lane
3468 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3470 def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))),
3471 (v4f32 (DUPv4i32lane
3472 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3474 def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))),
3475 (v2f64 (DUPv2i64lane
3476 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3478 def : Pat<(v4f16 (AArch64dup (f16 FPR16:$Rn))),
3479 (v4f16 (DUPv4i16lane
3480 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3482 def : Pat<(v8f16 (AArch64dup (f16 FPR16:$Rn))),
3483 (v8f16 (DUPv8i16lane
3484 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3487 def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3488 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>;
3489 def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3490 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>;
3492 def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3493 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3494 def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3495 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3496 def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3497 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3499 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane
3500 // instruction even if the types don't match: we just have to remap the lane
3501 // carefully. N.b. this trick only applies to truncations.
3502 def VecIndex_x2 : SDNodeXForm<imm, [{
3503 return CurDAG->getTargetConstant(2 * N->getZExtValue(), MVT::i64);
3505 def VecIndex_x4 : SDNodeXForm<imm, [{
3506 return CurDAG->getTargetConstant(4 * N->getZExtValue(), MVT::i64);
3508 def VecIndex_x8 : SDNodeXForm<imm, [{
3509 return CurDAG->getTargetConstant(8 * N->getZExtValue(), MVT::i64);
3512 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3513 ValueType Src128VT, ValueType ScalVT,
3514 Instruction DUP, SDNodeXForm IdxXFORM> {
3515 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3517 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3519 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3521 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3524 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3525 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3526 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3528 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3529 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3530 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3532 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3533 SDNodeXForm IdxXFORM> {
3534 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3536 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3538 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3540 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3543 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3544 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3545 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3547 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3548 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3549 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3551 // SMOV and UMOV definitions, with some extra patterns for convenience
3555 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3556 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3557 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3558 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3559 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3560 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3561 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3562 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3563 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3564 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3565 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3566 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3568 // Extracting i8 or i16 elements will have the zero-extend transformed to
3569 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3570 // for AArch64. Match these patterns here since UMOV already zeroes out the high
3571 // bits of the destination register.
3572 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3574 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3575 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3577 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3581 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3582 (SUBREG_TO_REG (i32 0),
3583 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3584 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3585 (SUBREG_TO_REG (i32 0),
3586 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3588 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3589 (SUBREG_TO_REG (i32 0),
3590 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3591 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3592 (SUBREG_TO_REG (i32 0),
3593 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3595 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3596 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3597 (i32 FPR32:$Rn), ssub))>;
3598 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3599 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3600 (i32 FPR32:$Rn), ssub))>;
3601 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3602 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3603 (i64 FPR64:$Rn), dsub))>;
3605 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3606 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3607 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3608 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3609 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3610 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3612 def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn),
3613 (f16 FPR16:$Rm), (i64 VectorIndexS:$imm))),
3616 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3618 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3622 def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn),
3623 (f16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
3625 V128:$Rn, VectorIndexH:$imm,
3626 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3629 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3630 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3633 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3635 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3638 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3639 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3641 V128:$Rn, VectorIndexS:$imm,
3642 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3644 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3645 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3647 V128:$Rn, VectorIndexD:$imm,
3648 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3651 // Copy an element at a constant index in one vector into a constant indexed
3652 // element of another.
3653 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3654 // index type and INS extension
3655 def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane
3656 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3657 VectorIndexB:$idx2)),
3659 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3661 def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane
3662 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3663 VectorIndexH:$idx2)),
3665 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3667 def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane
3668 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3669 VectorIndexS:$idx2)),
3671 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3673 def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
3674 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3675 VectorIndexD:$idx2)),
3677 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3680 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3681 ValueType VTScal, Instruction INS> {
3682 def : Pat<(VT128 (vector_insert V128:$src,
3683 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3685 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3687 def : Pat<(VT128 (vector_insert V128:$src,
3688 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3690 (INS V128:$src, imm:$Immd,
3691 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3693 def : Pat<(VT64 (vector_insert V64:$src,
3694 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3696 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3697 imm:$Immd, V128:$Rn, imm:$Immn),
3700 def : Pat<(VT64 (vector_insert V64:$src,
3701 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3704 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3705 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3709 defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>;
3710 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3711 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3712 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, INSvi8lane>;
3713 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, INSvi16lane>;
3714 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, INSvi32lane>;
3715 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, INSvi32lane>;
3718 // Floating point vector extractions are codegen'd as either a sequence of
3719 // subregister extractions, possibly fed by an INS if the lane number is
3720 // anything other than zero.
3721 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3722 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3723 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3724 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3725 def : Pat<(vector_extract (v8f16 V128:$Rn), 0),
3726 (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>;
3727 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3728 (f64 (EXTRACT_SUBREG
3729 (INSvi64lane (v2f64 (IMPLICIT_DEF)), 0,
3730 V128:$Rn, VectorIndexD:$idx),
3732 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3733 (f32 (EXTRACT_SUBREG
3734 (INSvi32lane (v4f32 (IMPLICIT_DEF)), 0,
3735 V128:$Rn, VectorIndexS:$idx),
3737 def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx),
3738 (f16 (EXTRACT_SUBREG
3739 (INSvi16lane (v8f16 (IMPLICIT_DEF)), 0,
3740 V128:$Rn, VectorIndexH:$idx),
3743 // All concat_vectors operations are canonicalised to act on i64 vectors for
3744 // AArch64. In the general case we need an instruction, which had just as well be
3746 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3747 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3748 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3749 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3751 def : ConcatPat<v2i64, v1i64>;
3752 def : ConcatPat<v2f64, v1f64>;
3753 def : ConcatPat<v4i32, v2i32>;
3754 def : ConcatPat<v4f32, v2f32>;
3755 def : ConcatPat<v8i16, v4i16>;
3756 def : ConcatPat<v8f16, v4f16>;
3757 def : ConcatPat<v16i8, v8i8>;
3759 // If the high lanes are undef, though, we can just ignore them:
3760 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3761 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3762 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3764 def : ConcatUndefPat<v2i64, v1i64>;
3765 def : ConcatUndefPat<v2f64, v1f64>;
3766 def : ConcatUndefPat<v4i32, v2i32>;
3767 def : ConcatUndefPat<v4f32, v2f32>;
3768 def : ConcatUndefPat<v8i16, v4i16>;
3769 def : ConcatUndefPat<v16i8, v8i8>;
3771 //----------------------------------------------------------------------------
3772 // AdvSIMD across lanes instructions
3773 //----------------------------------------------------------------------------
3775 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3776 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3777 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3778 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3779 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3780 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3781 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3782 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>;
3783 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>;
3784 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>;
3785 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
3787 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, Intrinsic intOp> {
3788 // If there is a sign extension after this intrinsic, consume it as smov already
3790 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i8 V64:$Rn))), i8)),
3792 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3793 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3795 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3797 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3798 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3800 // If there is a sign extension after this intrinsic, consume it as smov already
3802 def : Pat<(i32 (sext_inreg (i32 (intOp (v16i8 V128:$Rn))), i8)),
3804 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3805 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3807 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3809 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3810 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3812 // If there is a sign extension after this intrinsic, consume it as smov already
3814 def : Pat<(i32 (sext_inreg (i32 (intOp (v4i16 V64:$Rn))), i16)),
3816 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3817 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3819 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3821 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3822 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3824 // If there is a sign extension after this intrinsic, consume it as smov already
3826 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i16 V128:$Rn))), i16)),
3828 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3829 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3831 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3833 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3834 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3837 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3838 (i32 (EXTRACT_SUBREG
3839 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3840 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3844 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc, Intrinsic intOp> {
3845 // If there is a masking operation keeping only what has been actually
3846 // generated, consume it.
3847 def : Pat<(i32 (and (i32 (intOp (v8i8 V64:$Rn))), maski8_or_more)),
3848 (i32 (EXTRACT_SUBREG
3849 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3850 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3852 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3853 (i32 (EXTRACT_SUBREG
3854 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3855 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3857 // If there is a masking operation keeping only what has been actually
3858 // generated, consume it.
3859 def : Pat<(i32 (and (i32 (intOp (v16i8 V128:$Rn))), maski8_or_more)),
3860 (i32 (EXTRACT_SUBREG
3861 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3862 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3864 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3865 (i32 (EXTRACT_SUBREG
3866 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3867 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3870 // If there is a masking operation keeping only what has been actually
3871 // generated, consume it.
3872 def : Pat<(i32 (and (i32 (intOp (v4i16 V64:$Rn))), maski16_or_more)),
3873 (i32 (EXTRACT_SUBREG
3874 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3875 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3877 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3878 (i32 (EXTRACT_SUBREG
3879 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3880 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3882 // If there is a masking operation keeping only what has been actually
3883 // generated, consume it.
3884 def : Pat<(i32 (and (i32 (intOp (v8i16 V128:$Rn))), maski16_or_more)),
3885 (i32 (EXTRACT_SUBREG
3886 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3887 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3889 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3890 (i32 (EXTRACT_SUBREG
3891 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3892 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3895 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3896 (i32 (EXTRACT_SUBREG
3897 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3898 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3903 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
3904 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3906 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3907 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3909 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3911 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3912 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3915 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3916 (i32 (EXTRACT_SUBREG
3917 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3918 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3920 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3921 (i32 (EXTRACT_SUBREG
3922 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3923 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3926 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3927 (i64 (EXTRACT_SUBREG
3928 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3929 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3933 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
3935 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3936 (i32 (EXTRACT_SUBREG
3937 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3938 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3940 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3941 (i32 (EXTRACT_SUBREG
3942 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3943 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3946 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3947 (i32 (EXTRACT_SUBREG
3948 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3949 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3951 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3952 (i32 (EXTRACT_SUBREG
3953 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3954 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3957 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3958 (i64 (EXTRACT_SUBREG
3959 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3960 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3964 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", int_aarch64_neon_saddv>;
3965 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3966 def : Pat<(i32 (int_aarch64_neon_saddv (v2i32 V64:$Rn))),
3967 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3969 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", int_aarch64_neon_uaddv>;
3970 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3971 def : Pat<(i32 (int_aarch64_neon_uaddv (v2i32 V64:$Rn))),
3972 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3974 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", int_aarch64_neon_smaxv>;
3975 def : Pat<(i32 (int_aarch64_neon_smaxv (v2i32 V64:$Rn))),
3976 (EXTRACT_SUBREG (SMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3978 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", int_aarch64_neon_sminv>;
3979 def : Pat<(i32 (int_aarch64_neon_sminv (v2i32 V64:$Rn))),
3980 (EXTRACT_SUBREG (SMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3982 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", int_aarch64_neon_umaxv>;
3983 def : Pat<(i32 (int_aarch64_neon_umaxv (v2i32 V64:$Rn))),
3984 (EXTRACT_SUBREG (UMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3986 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", int_aarch64_neon_uminv>;
3987 def : Pat<(i32 (int_aarch64_neon_uminv (v2i32 V64:$Rn))),
3988 (EXTRACT_SUBREG (UMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3990 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>;
3991 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>;
3993 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
3994 def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))),
3995 (i64 (EXTRACT_SUBREG
3996 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3997 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
3999 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
4000 def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))),
4001 (i64 (EXTRACT_SUBREG
4002 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4003 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
4006 //------------------------------------------------------------------------------
4007 // AdvSIMD modified immediate instructions
4008 //------------------------------------------------------------------------------
4011 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
4013 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
4015 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4016 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4017 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4018 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4020 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4021 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4022 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4023 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4025 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4026 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4027 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4028 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4030 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4031 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4032 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4033 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4036 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
4038 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4039 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
4041 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4042 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
4044 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4048 // EDIT byte mask: scalar
4049 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4050 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
4051 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
4052 // The movi_edit node has the immediate value already encoded, so we use
4053 // a plain imm0_255 here.
4054 def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)),
4055 (MOVID imm0_255:$shift)>;
4057 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
4058 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
4059 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
4060 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
4062 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
4063 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
4064 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
4065 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
4067 // EDIT byte mask: 2d
4069 // The movi_edit node has the immediate value already encoded, so we use
4070 // a plain imm0_255 in the pattern
4071 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4072 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
4075 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;
4078 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
4079 // Complexity is added to break a tie with a plain MOVI.
4080 let AddedComplexity = 1 in {
4081 def : Pat<(f32 fpimm0),
4082 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
4084 def : Pat<(f64 fpimm0),
4085 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
4089 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4090 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4091 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4092 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4094 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4095 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4096 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4097 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4099 def : Pat<(v2f64 (AArch64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
4100 def : Pat<(v4f32 (AArch64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
4102 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4103 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
4105 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4106 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4107 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4108 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4110 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4111 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4112 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4113 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4115 def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4116 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
4117 def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4118 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
4119 def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4120 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
4121 def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4122 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
4124 // EDIT per word: 2s & 4s with MSL shifter
4125 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
4126 [(set (v2i32 V64:$Rd),
4127 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4128 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
4129 [(set (v4i32 V128:$Rd),
4130 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4132 // Per byte: 8b & 16b
4133 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
4135 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>;
4136 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
4138 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>;
4142 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4143 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
4145 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4146 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4147 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4148 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4150 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4151 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4152 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4153 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4155 def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4156 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
4157 def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4158 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
4159 def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4160 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
4161 def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4162 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
4164 // EDIT per word: 2s & 4s with MSL shifter
4165 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
4166 [(set (v2i32 V64:$Rd),
4167 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4168 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
4169 [(set (v4i32 V128:$Rd),
4170 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4172 //----------------------------------------------------------------------------
4173 // AdvSIMD indexed element
4174 //----------------------------------------------------------------------------
4176 let hasSideEffects = 0 in {
4177 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
4178 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
4181 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
4182 // instruction expects the addend first, while the intrinsic expects it last.
4184 // On the other hand, there are quite a few valid combinatorial options due to
4185 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
4186 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4187 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
4188 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4189 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
4191 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4192 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
4193 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4194 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
4195 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4196 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
4197 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4198 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
4200 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
4201 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4203 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4204 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4205 VectorIndexS:$idx))),
4206 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4207 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4208 (v2f32 (AArch64duplane32
4209 (v4f32 (insert_subvector undef,
4210 (v2f32 (fneg V64:$Rm)),
4212 VectorIndexS:$idx)))),
4213 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4214 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4215 VectorIndexS:$idx)>;
4216 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4217 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4218 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4219 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4221 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4223 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4224 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4225 VectorIndexS:$idx))),
4226 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
4227 VectorIndexS:$idx)>;
4228 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4229 (v4f32 (AArch64duplane32
4230 (v4f32 (insert_subvector undef,
4231 (v2f32 (fneg V64:$Rm)),
4233 VectorIndexS:$idx)))),
4234 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4235 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4236 VectorIndexS:$idx)>;
4237 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4238 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4239 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4240 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4242 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
4243 // (DUPLANE from 64-bit would be trivial).
4244 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4245 (AArch64duplane64 (v2f64 (fneg V128:$Rm)),
4246 VectorIndexD:$idx))),
4248 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4249 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4250 (AArch64dup (f64 (fneg FPR64Op:$Rm))))),
4251 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
4252 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
4254 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
4255 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4256 (vector_extract (v4f32 (fneg V128:$Rm)),
4257 VectorIndexS:$idx))),
4258 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4259 V128:$Rm, VectorIndexS:$idx)>;
4260 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4261 (vector_extract (v2f32 (fneg V64:$Rm)),
4262 VectorIndexS:$idx))),
4263 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4264 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
4266 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
4267 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
4268 (vector_extract (v2f64 (fneg V128:$Rm)),
4269 VectorIndexS:$idx))),
4270 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
4271 V128:$Rm, VectorIndexS:$idx)>;
4274 defm : FMLSIndexedAfterNegPatterns<
4275 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
4276 defm : FMLSIndexedAfterNegPatterns<
4277 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
4279 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;
4280 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
4282 def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4283 (FMULv2i32_indexed V64:$Rn,
4284 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4286 def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4287 (FMULv4i32_indexed V128:$Rn,
4288 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4290 def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))),
4291 (FMULv2i64_indexed V128:$Rn,
4292 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
4295 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>;
4296 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
4297 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
4298 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
4299 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
4300 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
4301 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
4302 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
4303 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4304 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
4305 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4306 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
4307 int_aarch64_neon_smull>;
4308 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
4309 int_aarch64_neon_sqadd>;
4310 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
4311 int_aarch64_neon_sqsub>;
4312 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;
4313 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
4314 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4315 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
4316 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4317 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
4318 int_aarch64_neon_umull>;
4320 // A scalar sqdmull with the second operand being a vector lane can be
4321 // handled directly with the indexed instruction encoding.
4322 def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
4323 (vector_extract (v4i32 V128:$Vm),
4324 VectorIndexS:$idx)),
4325 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
4327 //----------------------------------------------------------------------------
4328 // AdvSIMD scalar shift instructions
4329 //----------------------------------------------------------------------------
4330 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
4331 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
4332 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
4333 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
4334 // Codegen patterns for the above. We don't put these directly on the
4335 // instructions because TableGen's type inference can't handle the truth.
4336 // Having the same base pattern for fp <--> int totally freaks it out.
4337 def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
4338 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
4339 def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
4340 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
4341 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
4342 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4343 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
4344 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4345 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
4347 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4348 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
4350 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4351 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
4352 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4353 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
4354 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4355 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4356 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4357 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4358 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4359 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
4361 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4362 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
4364 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4366 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;
4367 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
4368 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
4369 int_aarch64_neon_sqrshrn>;
4370 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
4371 int_aarch64_neon_sqrshrun>;
4372 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4373 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4374 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
4375 int_aarch64_neon_sqshrn>;
4376 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
4377 int_aarch64_neon_sqshrun>;
4378 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4379 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>;
4380 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4381 TriOpFrag<(add node:$LHS,
4382 (AArch64srshri node:$MHS, node:$RHS))>>;
4383 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>;
4384 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
4385 TriOpFrag<(add node:$LHS,
4386 (AArch64vashr node:$MHS, node:$RHS))>>;
4387 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
4388 int_aarch64_neon_uqrshrn>;
4389 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4390 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4391 int_aarch64_neon_uqshrn>;
4392 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>;
4393 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
4394 TriOpFrag<(add node:$LHS,
4395 (AArch64urshri node:$MHS, node:$RHS))>>;
4396 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>;
4397 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
4398 TriOpFrag<(add node:$LHS,
4399 (AArch64vlshr node:$MHS, node:$RHS))>>;
4401 //----------------------------------------------------------------------------
4402 // AdvSIMD vector shift instructions
4403 //----------------------------------------------------------------------------
4404 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
4405 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
4406 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
4407 int_aarch64_neon_vcvtfxs2fp>;
4408 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
4409 int_aarch64_neon_rshrn>;
4410 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>;
4411 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
4412 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>;
4413 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>;
4414 def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4415 (i32 vecshiftL64:$imm))),
4416 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
4417 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
4418 int_aarch64_neon_sqrshrn>;
4419 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
4420 int_aarch64_neon_sqrshrun>;
4421 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4422 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4423 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
4424 int_aarch64_neon_sqshrn>;
4425 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
4426 int_aarch64_neon_sqshrun>;
4427 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>;
4428 def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4429 (i32 vecshiftR64:$imm))),
4430 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
4431 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>;
4432 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
4433 TriOpFrag<(add node:$LHS,
4434 (AArch64srshri node:$MHS, node:$RHS))> >;
4435 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
4436 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>;
4438 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>;
4439 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
4440 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>;
4441 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
4442 int_aarch64_neon_vcvtfxu2fp>;
4443 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
4444 int_aarch64_neon_uqrshrn>;
4445 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4446 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
4447 int_aarch64_neon_uqshrn>;
4448 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>;
4449 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
4450 TriOpFrag<(add node:$LHS,
4451 (AArch64urshri node:$MHS, node:$RHS))> >;
4452 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
4453 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>;
4454 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>;
4455 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
4456 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >;
4458 // SHRN patterns for when a logical right shift was used instead of arithmetic
4459 // (the immediate guarantees no sign bits actually end up in the result so it
4461 def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
4462 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
4463 def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
4464 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
4465 def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
4466 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
4468 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
4469 (trunc (AArch64vlshr (v8i16 V128:$Rn),
4470 vecshiftR16Narrow:$imm)))),
4471 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4472 V128:$Rn, vecshiftR16Narrow:$imm)>;
4473 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
4474 (trunc (AArch64vlshr (v4i32 V128:$Rn),
4475 vecshiftR32Narrow:$imm)))),
4476 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4477 V128:$Rn, vecshiftR32Narrow:$imm)>;
4478 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
4479 (trunc (AArch64vlshr (v2i64 V128:$Rn),
4480 vecshiftR64Narrow:$imm)))),
4481 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4482 V128:$Rn, vecshiftR32Narrow:$imm)>;
4484 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
4485 // Anyexts are implemented as zexts.
4486 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
4487 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4488 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4489 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
4490 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4491 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4492 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
4493 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4494 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4495 // Also match an extend from the upper half of a 128 bit source register.
4496 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4497 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4498 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4499 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4500 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4501 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
4502 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4503 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4504 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4505 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4506 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4507 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
4508 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4509 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4510 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4511 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4512 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4513 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
4515 // Vector shift sxtl aliases
4516 def : InstAlias<"sxtl.8h $dst, $src1",
4517 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4518 def : InstAlias<"sxtl $dst.8h, $src1.8b",
4519 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4520 def : InstAlias<"sxtl.4s $dst, $src1",
4521 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4522 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4523 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4524 def : InstAlias<"sxtl.2d $dst, $src1",
4525 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4526 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4527 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4529 // Vector shift sxtl2 aliases
4530 def : InstAlias<"sxtl2.8h $dst, $src1",
4531 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4532 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4533 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4534 def : InstAlias<"sxtl2.4s $dst, $src1",
4535 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4536 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4537 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4538 def : InstAlias<"sxtl2.2d $dst, $src1",
4539 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4540 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4541 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4543 // Vector shift uxtl aliases
4544 def : InstAlias<"uxtl.8h $dst, $src1",
4545 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4546 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4547 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4548 def : InstAlias<"uxtl.4s $dst, $src1",
4549 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4550 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4551 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4552 def : InstAlias<"uxtl.2d $dst, $src1",
4553 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4554 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4555 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4557 // Vector shift uxtl2 aliases
4558 def : InstAlias<"uxtl2.8h $dst, $src1",
4559 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4560 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4561 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4562 def : InstAlias<"uxtl2.4s $dst, $src1",
4563 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4564 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4565 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4566 def : InstAlias<"uxtl2.2d $dst, $src1",
4567 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4568 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4569 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4571 // If an integer is about to be converted to a floating point value,
4572 // just load it on the floating point unit.
4573 // These patterns are more complex because floating point loads do not
4574 // support sign extension.
4575 // The sign extension has to be explicitly added and is only supported for
4576 // one step: byte-to-half, half-to-word, word-to-doubleword.
4577 // SCVTF GPR -> FPR is 9 cycles.
4578 // SCVTF FPR -> FPR is 4 cyclces.
4579 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4580 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4581 // and still being faster.
4582 // However, this is not good for code size.
4583 // 8-bits -> float. 2 sizes step-up.
4584 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>
4585 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),
4586 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4591 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4597 ssub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4599 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
4600 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
4601 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),
4602 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;
4603 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),
4604 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;
4605 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),
4606 (LDURBi GPR64sp:$Rn, simm9:$offset)>;
4608 // 16-bits -> float. 1 size step-up.
4609 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
4610 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4611 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4613 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4617 ssub)))>, Requires<[NotForCodeSize]>;
4619 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4620 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4621 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4622 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4623 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4624 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4625 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4626 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4628 // 32-bits to 32-bits are handled in target specific dag combine:
4629 // performIntToFpCombine.
4630 // 64-bits integer to 32-bits floating point, not possible with
4631 // SCVTF on floating point registers (both source and destination
4632 // must have the same size).
4634 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4635 // 8-bits -> double. 3 size step-up: give up.
4636 // 16-bits -> double. 2 size step.
4637 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>
4638 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4639 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4644 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4650 dsub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4652 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4653 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4654 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4655 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4656 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4657 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4658 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4659 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4660 // 32-bits -> double. 1 size step-up.
4661 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
4662 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),
4663 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4665 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4669 dsub)))>, Requires<[NotForCodeSize]>;
4671 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
4672 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
4673 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),
4674 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;
4675 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),
4676 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;
4677 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),
4678 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
4680 // 64-bits -> double are handled in target specific dag combine:
4681 // performIntToFpCombine.
4684 //----------------------------------------------------------------------------
4685 // AdvSIMD Load-Store Structure
4686 //----------------------------------------------------------------------------
4687 defm LD1 : SIMDLd1Multiple<"ld1">;
4688 defm LD2 : SIMDLd2Multiple<"ld2">;
4689 defm LD3 : SIMDLd3Multiple<"ld3">;
4690 defm LD4 : SIMDLd4Multiple<"ld4">;
4692 defm ST1 : SIMDSt1Multiple<"st1">;
4693 defm ST2 : SIMDSt2Multiple<"st2">;
4694 defm ST3 : SIMDSt3Multiple<"st3">;
4695 defm ST4 : SIMDSt4Multiple<"st4">;
4697 class Ld1Pat<ValueType ty, Instruction INST>
4698 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>;
4700 def : Ld1Pat<v16i8, LD1Onev16b>;
4701 def : Ld1Pat<v8i16, LD1Onev8h>;
4702 def : Ld1Pat<v4i32, LD1Onev4s>;
4703 def : Ld1Pat<v2i64, LD1Onev2d>;
4704 def : Ld1Pat<v8i8, LD1Onev8b>;
4705 def : Ld1Pat<v4i16, LD1Onev4h>;
4706 def : Ld1Pat<v2i32, LD1Onev2s>;
4707 def : Ld1Pat<v1i64, LD1Onev1d>;
4709 class St1Pat<ValueType ty, Instruction INST>
4710 : Pat<(store ty:$Vt, GPR64sp:$Rn),
4711 (INST ty:$Vt, GPR64sp:$Rn)>;
4713 def : St1Pat<v16i8, ST1Onev16b>;
4714 def : St1Pat<v8i16, ST1Onev8h>;
4715 def : St1Pat<v4i32, ST1Onev4s>;
4716 def : St1Pat<v2i64, ST1Onev2d>;
4717 def : St1Pat<v8i8, ST1Onev8b>;
4718 def : St1Pat<v4i16, ST1Onev4h>;
4719 def : St1Pat<v2i32, ST1Onev2s>;
4720 def : St1Pat<v1i64, ST1Onev1d>;
4726 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4727 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4728 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4729 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4730 let mayLoad = 1, hasSideEffects = 0 in {
4731 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4732 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4733 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4734 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4735 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4736 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4737 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4738 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4739 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4740 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4741 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4742 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4743 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4744 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4745 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4746 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4749 def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4750 (LD1Rv8b GPR64sp:$Rn)>;
4751 def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4752 (LD1Rv16b GPR64sp:$Rn)>;
4753 def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4754 (LD1Rv4h GPR64sp:$Rn)>;
4755 def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4756 (LD1Rv8h GPR64sp:$Rn)>;
4757 def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4758 (LD1Rv2s GPR64sp:$Rn)>;
4759 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4760 (LD1Rv4s GPR64sp:$Rn)>;
4761 def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4762 (LD1Rv2d GPR64sp:$Rn)>;
4763 def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4764 (LD1Rv1d GPR64sp:$Rn)>;
4765 // Grab the floating point version too
4766 def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4767 (LD1Rv2s GPR64sp:$Rn)>;
4768 def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4769 (LD1Rv4s GPR64sp:$Rn)>;
4770 def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4771 (LD1Rv2d GPR64sp:$Rn)>;
4772 def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4773 (LD1Rv1d GPR64sp:$Rn)>;
4774 def : Pat<(v4f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4775 (LD1Rv4h GPR64sp:$Rn)>;
4776 def : Pat<(v8f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4777 (LD1Rv8h GPR64sp:$Rn)>;
4779 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4780 ValueType VTy, ValueType STy, Instruction LD1>
4781 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4782 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4783 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
4785 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4786 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4787 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4788 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4789 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4790 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4791 def : Ld1Lane128Pat<load, VectorIndexH, v8f16, f16, LD1i16>;
4793 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4794 ValueType VTy, ValueType STy, Instruction LD1>
4795 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4796 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4798 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4799 VecIndex:$idx, GPR64sp:$Rn),
4802 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4803 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4804 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4805 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4806 def : Ld1Lane64Pat<load, VectorIndexH, v4f16, f16, LD1i16>;
4809 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4810 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4811 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4812 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4815 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4816 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4817 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4818 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4820 let AddedComplexity = 15 in
4821 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4822 ValueType VTy, ValueType STy, Instruction ST1>
4824 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4826 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
4828 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4829 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
4830 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
4831 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
4832 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
4833 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
4834 def : St1Lane128Pat<store, VectorIndexH, v8f16, f16, ST1i16>;
4836 let AddedComplexity = 15 in
4837 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4838 ValueType VTy, ValueType STy, Instruction ST1>
4840 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4842 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4843 VecIndex:$idx, GPR64sp:$Rn)>;
4845 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
4846 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
4847 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
4848 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
4849 def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>;
4851 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4852 ValueType VTy, ValueType STy, Instruction ST1,
4854 def : Pat<(scalar_store
4855 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4856 GPR64sp:$Rn, offset),
4857 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4858 VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4860 def : Pat<(scalar_store
4861 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4862 GPR64sp:$Rn, GPR64:$Rm),
4863 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4864 VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4867 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
4868 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
4870 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
4871 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
4872 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
4873 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
4874 defm : St1LanePost64Pat<post_store, VectorIndexH, v4f16, f16, ST1i16_POST, 2>;
4876 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4877 ValueType VTy, ValueType STy, Instruction ST1,
4879 def : Pat<(scalar_store
4880 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4881 GPR64sp:$Rn, offset),
4882 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4884 def : Pat<(scalar_store
4885 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4886 GPR64sp:$Rn, GPR64:$Rm),
4887 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4890 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
4892 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
4894 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
4895 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
4896 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
4897 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
4898 defm : St1LanePost128Pat<post_store, VectorIndexH, v8f16, f16, ST1i16_POST, 2>;
4900 let mayStore = 1, hasSideEffects = 0 in {
4901 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
4902 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
4903 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
4904 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
4905 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
4906 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
4907 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
4908 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
4909 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
4910 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
4911 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
4912 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
4915 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
4916 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
4917 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
4918 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
4920 //----------------------------------------------------------------------------
4921 // Crypto extensions
4922 //----------------------------------------------------------------------------
4924 def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>;
4925 def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;
4926 def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>;
4927 def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
4929 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>;
4930 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>;
4931 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>;
4932 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>;
4933 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>;
4934 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>;
4935 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>;
4937 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>;
4938 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>;
4939 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>;
4941 //----------------------------------------------------------------------------
4943 //----------------------------------------------------------------------------
4944 // FIXME: Like for X86, these should go in their own separate .td file.
4946 // Any instruction that defines a 32-bit result leaves the high half of the
4947 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
4948 // be copying from a truncate. But any other 32-bit operation will zero-extend
4950 // FIXME: X86 also checks for CMOV here. Do we need something similar?
4951 def def32 : PatLeaf<(i32 GPR32:$src), [{
4952 return N->getOpcode() != ISD::TRUNCATE &&
4953 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
4954 N->getOpcode() != ISD::CopyFromReg;
4957 // In the case of a 32-bit def that is known to implicitly zero-extend,
4958 // we can use a SUBREG_TO_REG.
4959 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
4961 // For an anyext, we don't care what the high bits are, so we can perform an
4962 // INSERT_SUBREF into an IMPLICIT_DEF.
4963 def : Pat<(i64 (anyext GPR32:$src)),
4964 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
4966 // When we need to explicitly zero-extend, we use an unsigned bitfield move
4967 // instruction (UBFM) on the enclosing super-reg.
4968 def : Pat<(i64 (zext GPR32:$src)),
4969 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4971 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
4972 // containing super-reg.
4973 def : Pat<(i64 (sext GPR32:$src)),
4974 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4975 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
4976 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
4977 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
4978 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
4979 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
4980 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
4981 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
4983 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
4984 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4985 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
4986 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
4987 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4988 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
4990 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
4991 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4992 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
4993 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
4994 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4995 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
4997 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
4998 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4999 (i64 (i64shift_a imm0_63:$imm)),
5000 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
5002 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
5003 // AddedComplexity for the following patterns since we want to match sext + sra
5004 // patterns before we attempt to match a single sra node.
5005 let AddedComplexity = 20 in {
5006 // We support all sext + sra combinations which preserve at least one bit of the
5007 // original value which is to be sign extended. E.g. we support shifts up to
5009 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
5010 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
5011 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
5012 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
5014 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
5015 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
5016 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
5017 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
5019 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
5020 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
5021 (i64 imm0_31:$imm), 31)>;
5022 } // AddedComplexity = 20
5024 // To truncate, we can simply extract from a subregister.
5025 def : Pat<(i32 (trunc GPR64sp:$src)),
5026 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
5028 // __builtin_trap() uses the BRK instruction on AArch64.
5029 def : Pat<(trap), (BRK 1)>;
5031 // Conversions within AdvSIMD types in the same register size are free.
5032 // But because we need a consistent lane ordering, in big endian many
5033 // conversions require one or more REV instructions.
5035 // Consider a simple memory load followed by a bitconvert then a store.
5037 // v1 = BITCAST v2i32 v0 to v4i16
5040 // In big endian mode every memory access has an implicit byte swap. LDR and
5041 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
5042 // is, they treat the vector as a sequence of elements to be byte-swapped.
5043 // The two pairs of instructions are fundamentally incompatible. We've decided
5044 // to use LD1/ST1 only to simplify compiler implementation.
5046 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
5047 // the original code sequence:
5049 // v1 = REV v2i32 (implicit)
5050 // v2 = BITCAST v2i32 v1 to v4i16
5051 // v3 = REV v4i16 v2 (implicit)
5054 // But this is now broken - the value stored is different to the value loaded
5055 // due to lane reordering. To fix this, on every BITCAST we must perform two
5058 // v1 = REV v2i32 (implicit)
5060 // v3 = BITCAST v2i32 v2 to v4i16
5062 // v5 = REV v4i16 v4 (implicit)
5065 // This means an extra two instructions, but actually in most cases the two REV
5066 // instructions can be combined into one. For example:
5067 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
5069 // There is also no 128-bit REV instruction. This must be synthesized with an
5072 // Most bitconverts require some sort of conversion. The only exceptions are:
5073 // a) Identity conversions - vNfX <-> vNiX
5074 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
5077 // Natural vector casts (64 bit)
5078 def : Pat<(v8i8 (AArch64NvCast (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5079 def : Pat<(v4i16 (AArch64NvCast (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5080 def : Pat<(v2i32 (AArch64NvCast (v2i32 FPR64:$src))), (v2i32 FPR64:$src)>;
5081 def : Pat<(v2f32 (AArch64NvCast (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5082 def : Pat<(v1i64 (AArch64NvCast (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5084 def : Pat<(v8i8 (AArch64NvCast (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5085 def : Pat<(v4i16 (AArch64NvCast (v4i16 FPR64:$src))), (v4i16 FPR64:$src)>;
5086 def : Pat<(v2i32 (AArch64NvCast (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5087 def : Pat<(v1i64 (AArch64NvCast (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5089 def : Pat<(v8i8 (AArch64NvCast (v8i8 FPR64:$src))), (v8i8 FPR64:$src)>;
5090 def : Pat<(v4i16 (AArch64NvCast (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5091 def : Pat<(v2i32 (AArch64NvCast (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5092 def : Pat<(v1i64 (AArch64NvCast (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5094 def : Pat<(v8i8 (AArch64NvCast (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5095 def : Pat<(v4i16 (AArch64NvCast (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5096 def : Pat<(v2i32 (AArch64NvCast (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5097 def : Pat<(v2f32 (AArch64NvCast (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5098 def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5099 def : Pat<(v1f64 (AArch64NvCast (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5101 def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5102 def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5103 def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5104 def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>;
5105 def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5107 // Natural vector casts (128 bit)
5108 def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5109 def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5110 def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>;
5111 def : Pat<(v4f32 (AArch64NvCast (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5112 def : Pat<(v2i64 (AArch64NvCast (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5114 def : Pat<(v16i8 (AArch64NvCast (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5115 def : Pat<(v8i16 (AArch64NvCast (v8i16 FPR128:$src))), (v8i16 FPR128:$src)>;
5116 def : Pat<(v4i32 (AArch64NvCast (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5117 def : Pat<(v2i64 (AArch64NvCast (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5119 def : Pat<(v16i8 (AArch64NvCast (v16i8 FPR128:$src))), (v16i8 FPR128:$src)>;
5120 def : Pat<(v8i16 (AArch64NvCast (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5121 def : Pat<(v4i32 (AArch64NvCast (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5122 def : Pat<(v2i64 (AArch64NvCast (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5124 def : Pat<(v16i8 (AArch64NvCast (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5125 def : Pat<(v8i16 (AArch64NvCast (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5126 def : Pat<(v4i32 (AArch64NvCast (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5127 def : Pat<(v2i64 (AArch64NvCast (v2i64 FPR128:$src))), (v2i64 FPR128:$src)>;
5128 def : Pat<(v4f32 (AArch64NvCast (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5129 def : Pat<(v2f64 (AArch64NvCast (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5131 def : Pat<(v16i8 (AArch64NvCast (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5132 def : Pat<(v8i16 (AArch64NvCast (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5133 def : Pat<(v4i32 (AArch64NvCast (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5134 def : Pat<(v4f32 (AArch64NvCast (v4f32 FPR128:$src))), (v4f32 FPR128:$src)>;
5135 def : Pat<(v2i64 (AArch64NvCast (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5137 def : Pat<(v16i8 (AArch64NvCast (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5138 def : Pat<(v8i16 (AArch64NvCast (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5139 def : Pat<(v4i32 (AArch64NvCast (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5140 def : Pat<(v2i64 (AArch64NvCast (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5141 def : Pat<(v2f64 (AArch64NvCast (v2f64 FPR128:$src))), (v2f64 FPR128:$src)>;
5143 let Predicates = [IsLE] in {
5144 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5145 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5146 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5147 def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5148 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5150 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5151 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5152 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5153 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5154 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5155 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5156 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5157 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5158 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5159 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5160 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5161 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5163 let Predicates = [IsBE] in {
5164 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
5165 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5166 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
5167 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5168 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
5169 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5170 def : Pat<(v4f16 (bitconvert GPR64:$Xn)),
5171 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5172 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
5173 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5175 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5176 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5177 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5178 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5179 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5180 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5181 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5182 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5183 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5184 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5186 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5187 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5188 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
5189 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5190 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
5191 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5192 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
5193 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5194 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
5196 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
5197 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
5198 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
5199 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
5200 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
5201 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5202 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
5203 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
5204 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5205 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5207 let Predicates = [IsLE] in {
5208 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5209 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5210 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5211 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>;
5212 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5214 let Predicates = [IsBE] in {
5215 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
5216 (v1i64 (REV64v2i32 FPR64:$src))>;
5217 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
5218 (v1i64 (REV64v4i16 FPR64:$src))>;
5219 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
5220 (v1i64 (REV64v8i8 FPR64:$src))>;
5221 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))),
5222 (v1i64 (REV64v4i16 FPR64:$src))>;
5223 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
5224 (v1i64 (REV64v2i32 FPR64:$src))>;
5226 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5227 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5229 let Predicates = [IsLE] in {
5230 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
5231 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5232 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5233 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5234 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5235 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 FPR64:$src)>;
5237 let Predicates = [IsBE] in {
5238 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
5239 (v2i32 (REV64v2i32 FPR64:$src))>;
5240 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
5241 (v2i32 (REV32v4i16 FPR64:$src))>;
5242 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
5243 (v2i32 (REV32v8i8 FPR64:$src))>;
5244 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
5245 (v2i32 (REV64v2i32 FPR64:$src))>;
5246 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
5247 (v2i32 (REV64v2i32 FPR64:$src))>;
5248 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))),
5249 (v2i32 (REV64v4i16 FPR64:$src))>;
5251 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5253 let Predicates = [IsLE] in {
5254 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
5255 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5256 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5257 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5258 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))), (v4i16 FPR64:$src)>;
5259 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5260 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5262 let Predicates = [IsBE] in {
5263 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
5264 (v4i16 (REV64v4i16 FPR64:$src))>;
5265 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
5266 (v4i16 (REV32v4i16 FPR64:$src))>;
5267 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
5268 (v4i16 (REV16v8i8 FPR64:$src))>;
5269 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
5270 (v4i16 (REV64v4i16 FPR64:$src))>;
5271 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))),
5272 (v4i16 (REV32v4i16 FPR64:$src))>;
5273 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
5274 (v4i16 (REV32v4i16 FPR64:$src))>;
5275 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
5276 (v4i16 (REV64v4i16 FPR64:$src))>;
5279 let Predicates = [IsLE] in {
5280 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 FPR64:$src)>;
5281 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5282 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5283 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5284 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5285 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 FPR64:$src)>;
5286 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5288 let Predicates = [IsBE] in {
5289 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))),
5290 (v4f16 (REV64v4i16 FPR64:$src))>;
5291 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))),
5292 (v4f16 (REV64v4i16 FPR64:$src))>;
5293 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))),
5294 (v4f16 (REV64v4i16 FPR64:$src))>;
5295 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))),
5296 (v4f16 (REV16v8i8 FPR64:$src))>;
5297 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))),
5298 (v4f16 (REV64v4i16 FPR64:$src))>;
5299 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))),
5300 (v4f16 (REV64v4i16 FPR64:$src))>;
5301 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))),
5302 (v4f16 (REV64v4i16 FPR64:$src))>;
5307 let Predicates = [IsLE] in {
5308 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
5309 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5310 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5311 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5312 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5313 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5314 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 FPR64:$src)>;
5316 let Predicates = [IsBE] in {
5317 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
5318 (v8i8 (REV64v8i8 FPR64:$src))>;
5319 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
5320 (v8i8 (REV32v8i8 FPR64:$src))>;
5321 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
5322 (v8i8 (REV16v8i8 FPR64:$src))>;
5323 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
5324 (v8i8 (REV64v8i8 FPR64:$src))>;
5325 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
5326 (v8i8 (REV32v8i8 FPR64:$src))>;
5327 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
5328 (v8i8 (REV64v8i8 FPR64:$src))>;
5329 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))),
5330 (v8i8 (REV16v8i8 FPR64:$src))>;
5333 let Predicates = [IsLE] in {
5334 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
5335 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
5336 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
5337 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
5338 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 FPR64:$src)>;
5340 let Predicates = [IsBE] in {
5341 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
5342 (f64 (REV64v2i32 FPR64:$src))>;
5343 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
5344 (f64 (REV64v4i16 FPR64:$src))>;
5345 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
5346 (f64 (REV64v2i32 FPR64:$src))>;
5347 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
5348 (f64 (REV64v8i8 FPR64:$src))>;
5349 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))),
5350 (f64 (REV64v4i16 FPR64:$src))>;
5352 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
5353 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
5355 let Predicates = [IsLE] in {
5356 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
5357 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
5358 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
5359 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
5360 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 FPR64:$src)>;
5362 let Predicates = [IsBE] in {
5363 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
5364 (v1f64 (REV64v2i32 FPR64:$src))>;
5365 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
5366 (v1f64 (REV64v4i16 FPR64:$src))>;
5367 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
5368 (v1f64 (REV64v8i8 FPR64:$src))>;
5369 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
5370 (v1f64 (REV64v2i32 FPR64:$src))>;
5371 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))),
5372 (v1f64 (REV64v4i16 FPR64:$src))>;
5374 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
5375 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5377 let Predicates = [IsLE] in {
5378 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
5379 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
5380 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
5381 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5382 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5383 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 FPR64:$src)>;
5385 let Predicates = [IsBE] in {
5386 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
5387 (v2f32 (REV64v2i32 FPR64:$src))>;
5388 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
5389 (v2f32 (REV32v4i16 FPR64:$src))>;
5390 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
5391 (v2f32 (REV32v8i8 FPR64:$src))>;
5392 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
5393 (v2f32 (REV64v2i32 FPR64:$src))>;
5394 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
5395 (v2f32 (REV64v2i32 FPR64:$src))>;
5396 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))),
5397 (v2f32 (REV64v4i16 FPR64:$src))>;
5399 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5401 let Predicates = [IsLE] in {
5402 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
5403 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
5404 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
5405 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
5406 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
5407 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 FPR128:$src)>;
5408 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
5410 let Predicates = [IsBE] in {
5411 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
5412 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5413 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
5414 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5415 (REV64v4i32 FPR128:$src), (i32 8)))>;
5416 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
5417 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5418 (REV64v8i16 FPR128:$src), (i32 8)))>;
5419 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))),
5420 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5421 (REV64v8i16 FPR128:$src), (i32 8)))>;
5422 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
5423 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5424 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
5425 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5426 (REV64v4i32 FPR128:$src), (i32 8)))>;
5427 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
5428 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
5429 (REV64v16i8 FPR128:$src), (i32 8)))>;
5432 let Predicates = [IsLE] in {
5433 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
5434 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5435 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5436 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 FPR128:$src)>;
5437 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5438 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5440 let Predicates = [IsBE] in {
5441 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
5442 (v2f64 (EXTv16i8 FPR128:$src,
5443 FPR128:$src, (i32 8)))>;
5444 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
5445 (v2f64 (REV64v4i32 FPR128:$src))>;
5446 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
5447 (v2f64 (REV64v8i16 FPR128:$src))>;
5448 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))),
5449 (v2f64 (REV64v8i16 FPR128:$src))>;
5450 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
5451 (v2f64 (REV64v16i8 FPR128:$src))>;
5452 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
5453 (v2f64 (REV64v4i32 FPR128:$src))>;
5455 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5457 let Predicates = [IsLE] in {
5458 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
5459 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5460 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 FPR128:$src)>;
5461 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5462 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5463 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5465 let Predicates = [IsBE] in {
5466 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
5467 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5468 (REV64v4i32 FPR128:$src), (i32 8)))>;
5469 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
5470 (v4f32 (REV32v8i16 FPR128:$src))>;
5471 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))),
5472 (v4f32 (REV32v8i16 FPR128:$src))>;
5473 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
5474 (v4f32 (REV32v16i8 FPR128:$src))>;
5475 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
5476 (v4f32 (REV64v4i32 FPR128:$src))>;
5477 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
5478 (v4f32 (REV64v4i32 FPR128:$src))>;
5480 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5482 let Predicates = [IsLE] in {
5483 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5484 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5485 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5486 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5487 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5488 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 FPR128:$src)>;
5490 let Predicates = [IsBE] in {
5491 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
5492 (v2i64 (EXTv16i8 FPR128:$src,
5493 FPR128:$src, (i32 8)))>;
5494 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
5495 (v2i64 (REV64v4i32 FPR128:$src))>;
5496 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
5497 (v2i64 (REV64v8i16 FPR128:$src))>;
5498 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
5499 (v2i64 (REV64v16i8 FPR128:$src))>;
5500 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
5501 (v2i64 (REV64v4i32 FPR128:$src))>;
5502 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))),
5503 (v2i64 (REV64v8i16 FPR128:$src))>;
5505 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5507 let Predicates = [IsLE] in {
5508 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5509 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5510 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5511 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5512 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5513 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>;
5515 let Predicates = [IsBE] in {
5516 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
5517 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5518 (REV64v4i32 FPR128:$src),
5520 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
5521 (v4i32 (REV64v4i32 FPR128:$src))>;
5522 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
5523 (v4i32 (REV32v8i16 FPR128:$src))>;
5524 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
5525 (v4i32 (REV32v16i8 FPR128:$src))>;
5526 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
5527 (v4i32 (REV64v4i32 FPR128:$src))>;
5528 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))),
5529 (v4i32 (REV32v8i16 FPR128:$src))>;
5531 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5533 let Predicates = [IsLE] in {
5534 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5535 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5536 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5537 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5538 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5539 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5540 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))), (v8i16 FPR128:$src)>;
5542 let Predicates = [IsBE] in {
5543 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
5544 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5545 (REV64v8i16 FPR128:$src),
5547 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
5548 (v8i16 (REV64v8i16 FPR128:$src))>;
5549 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
5550 (v8i16 (REV32v8i16 FPR128:$src))>;
5551 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
5552 (v8i16 (REV16v16i8 FPR128:$src))>;
5553 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
5554 (v8i16 (REV64v8i16 FPR128:$src))>;
5555 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
5556 (v8i16 (REV32v8i16 FPR128:$src))>;
5557 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))),
5558 (v8i16 (REV32v8i16 FPR128:$src))>;
5561 let Predicates = [IsLE] in {
5562 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 FPR128:$src)>;
5563 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5564 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5565 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5566 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5567 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
5568 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
5570 let Predicates = [IsBE] in {
5571 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))),
5572 (v8f16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5573 (REV64v8i16 FPR128:$src),
5575 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))),
5576 (v8f16 (REV64v8i16 FPR128:$src))>;
5577 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))),
5578 (v8f16 (REV32v8i16 FPR128:$src))>;
5579 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))),
5580 (v8f16 (REV64v8i16 FPR128:$src))>;
5581 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))),
5582 (v8f16 (REV16v16i8 FPR128:$src))>;
5583 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))),
5584 (v8f16 (REV64v8i16 FPR128:$src))>;
5585 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))),
5586 (v8f16 (REV32v8i16 FPR128:$src))>;
5589 let Predicates = [IsLE] in {
5590 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5591 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5592 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5593 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5594 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5595 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5596 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 FPR128:$src)>;
5598 let Predicates = [IsBE] in {
5599 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
5600 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
5601 (REV64v16i8 FPR128:$src),
5603 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
5604 (v16i8 (REV64v16i8 FPR128:$src))>;
5605 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
5606 (v16i8 (REV32v16i8 FPR128:$src))>;
5607 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
5608 (v16i8 (REV16v16i8 FPR128:$src))>;
5609 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
5610 (v16i8 (REV64v16i8 FPR128:$src))>;
5611 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
5612 (v16i8 (REV32v16i8 FPR128:$src))>;
5613 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))),
5614 (v16i8 (REV16v16i8 FPR128:$src))>;
5617 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
5618 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5619 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
5620 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5621 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
5622 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5623 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
5624 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5626 // A 64-bit subvector insert to the first 128-bit vector position
5627 // is a subregister copy that needs no instruction.
5628 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
5629 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5630 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
5631 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5632 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
5633 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5634 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
5635 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5636 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
5637 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5638 def : Pat<(insert_subvector undef, (v4f16 FPR64:$src), (i32 0)),
5639 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5640 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
5641 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5643 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
5645 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
5646 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
5647 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
5648 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
5649 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
5650 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
5651 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
5652 // so we match on v4f32 here, not v2f32. This will also catch adding
5653 // the low two lanes of a true v4f32 vector.
5654 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
5655 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
5656 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
5658 // Scalar 64-bit shifts in FPR64 registers.
5659 def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5660 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5661 def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5662 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5663 def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5664 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5665 def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5666 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5668 // Tail call return handling. These are all compiler pseudo-instructions,
5669 // so no encoding information or anything like that.
5670 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
5671 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff),[]>;
5672 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>;
5675 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
5676 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
5677 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
5678 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5679 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
5680 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5682 include "AArch64InstrAtomics.td"