1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // AArch64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
18 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
19 def HasNEON : Predicate<"Subtarget->hasNEON()">,
20 AssemblerPredicate<"FeatureNEON", "neon">;
21 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
22 AssemblerPredicate<"FeatureCrypto", "crypto">;
23 def HasCRC : Predicate<"Subtarget->hasCRC()">,
24 AssemblerPredicate<"FeatureCRC", "crc">;
25 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
26 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
27 def IsCyclone : Predicate<"Subtarget->isCyclone()">;
29 //===----------------------------------------------------------------------===//
30 // AArch64-specific DAG Nodes.
33 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
34 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
37 SDTCisInt<0>, SDTCisVT<1, i32>]>;
39 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
40 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
46 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
47 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
54 def SDT_AArch64Brcond : SDTypeProfile<0, 3,
55 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
57 def SDT_AArch64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
58 def SDT_AArch64tbz : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>,
59 SDTCisVT<2, OtherVT>]>;
62 def SDT_AArch64CSel : SDTypeProfile<1, 4,
67 def SDT_AArch64FCmp : SDTypeProfile<0, 2,
70 def SDT_AArch64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
71 def SDT_AArch64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
72 def SDT_AArch64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
75 def SDT_AArch64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
76 def SDT_AArch64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
77 def SDT_AArch64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
78 SDTCisInt<2>, SDTCisInt<3>]>;
79 def SDT_AArch64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
80 def SDT_AArch64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
81 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
82 def SDT_AArch64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
84 def SDT_AArch64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
85 def SDT_AArch64fcmpz : SDTypeProfile<1, 1, []>;
86 def SDT_AArch64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
87 def SDT_AArch64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
89 def SDT_AArch64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
92 def SDT_AArch64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
93 def SDT_AArch64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
95 def SDT_AArch64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
97 def SDT_AArch64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
99 def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
100 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
101 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
102 SDTCisSameAs<1, 4>]>;
106 def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
107 def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
108 def AArch64LOADgot : SDNode<"AArch64ISD::LOADgot", SDTIntUnaryOp>;
109 def AArch64callseq_start : SDNode<"ISD::CALLSEQ_START",
110 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
111 [SDNPHasChain, SDNPOutGlue]>;
112 def AArch64callseq_end : SDNode<"ISD::CALLSEQ_END",
113 SDCallSeqEnd<[ SDTCisVT<0, i32>,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
116 def AArch64call : SDNode<"AArch64ISD::CALL",
117 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
118 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
120 def AArch64brcond : SDNode<"AArch64ISD::BRCOND", SDT_AArch64Brcond,
122 def AArch64cbz : SDNode<"AArch64ISD::CBZ", SDT_AArch64cbz,
124 def AArch64cbnz : SDNode<"AArch64ISD::CBNZ", SDT_AArch64cbz,
126 def AArch64tbz : SDNode<"AArch64ISD::TBZ", SDT_AArch64tbz,
128 def AArch64tbnz : SDNode<"AArch64ISD::TBNZ", SDT_AArch64tbz,
132 def AArch64csel : SDNode<"AArch64ISD::CSEL", SDT_AArch64CSel>;
133 def AArch64csinv : SDNode<"AArch64ISD::CSINV", SDT_AArch64CSel>;
134 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;
135 def AArch64csinc : SDNode<"AArch64ISD::CSINC", SDT_AArch64CSel>;
136 def AArch64retflag : SDNode<"AArch64ISD::RET_FLAG", SDTNone,
137 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
138 def AArch64adc : SDNode<"AArch64ISD::ADC", SDTBinaryArithWithFlagsIn >;
139 def AArch64sbc : SDNode<"AArch64ISD::SBC", SDTBinaryArithWithFlagsIn>;
140 def AArch64add_flag : SDNode<"AArch64ISD::ADDS", SDTBinaryArithWithFlagsOut,
142 def AArch64sub_flag : SDNode<"AArch64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
143 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
145 def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
146 def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
148 def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
150 def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
152 def AArch64fmax : SDNode<"AArch64ISD::FMAX", SDTFPBinOp>;
153 def AArch64fmin : SDNode<"AArch64ISD::FMIN", SDTFPBinOp>;
155 def AArch64dup : SDNode<"AArch64ISD::DUP", SDT_AArch64Dup>;
156 def AArch64duplane8 : SDNode<"AArch64ISD::DUPLANE8", SDT_AArch64DupLane>;
157 def AArch64duplane16 : SDNode<"AArch64ISD::DUPLANE16", SDT_AArch64DupLane>;
158 def AArch64duplane32 : SDNode<"AArch64ISD::DUPLANE32", SDT_AArch64DupLane>;
159 def AArch64duplane64 : SDNode<"AArch64ISD::DUPLANE64", SDT_AArch64DupLane>;
161 def AArch64zip1 : SDNode<"AArch64ISD::ZIP1", SDT_AArch64Zip>;
162 def AArch64zip2 : SDNode<"AArch64ISD::ZIP2", SDT_AArch64Zip>;
163 def AArch64uzp1 : SDNode<"AArch64ISD::UZP1", SDT_AArch64Zip>;
164 def AArch64uzp2 : SDNode<"AArch64ISD::UZP2", SDT_AArch64Zip>;
165 def AArch64trn1 : SDNode<"AArch64ISD::TRN1", SDT_AArch64Zip>;
166 def AArch64trn2 : SDNode<"AArch64ISD::TRN2", SDT_AArch64Zip>;
168 def AArch64movi_edit : SDNode<"AArch64ISD::MOVIedit", SDT_AArch64MOVIedit>;
169 def AArch64movi_shift : SDNode<"AArch64ISD::MOVIshift", SDT_AArch64MOVIshift>;
170 def AArch64movi_msl : SDNode<"AArch64ISD::MOVImsl", SDT_AArch64MOVIshift>;
171 def AArch64mvni_shift : SDNode<"AArch64ISD::MVNIshift", SDT_AArch64MOVIshift>;
172 def AArch64mvni_msl : SDNode<"AArch64ISD::MVNImsl", SDT_AArch64MOVIshift>;
173 def AArch64movi : SDNode<"AArch64ISD::MOVI", SDT_AArch64MOVIedit>;
174 def AArch64fmov : SDNode<"AArch64ISD::FMOV", SDT_AArch64MOVIedit>;
176 def AArch64rev16 : SDNode<"AArch64ISD::REV16", SDT_AArch64UnaryVec>;
177 def AArch64rev32 : SDNode<"AArch64ISD::REV32", SDT_AArch64UnaryVec>;
178 def AArch64rev64 : SDNode<"AArch64ISD::REV64", SDT_AArch64UnaryVec>;
179 def AArch64ext : SDNode<"AArch64ISD::EXT", SDT_AArch64ExtVec>;
181 def AArch64vashr : SDNode<"AArch64ISD::VASHR", SDT_AArch64vshift>;
182 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;
183 def AArch64vshl : SDNode<"AArch64ISD::VSHL", SDT_AArch64vshift>;
184 def AArch64sqshli : SDNode<"AArch64ISD::SQSHL_I", SDT_AArch64vshift>;
185 def AArch64uqshli : SDNode<"AArch64ISD::UQSHL_I", SDT_AArch64vshift>;
186 def AArch64sqshlui : SDNode<"AArch64ISD::SQSHLU_I", SDT_AArch64vshift>;
187 def AArch64srshri : SDNode<"AArch64ISD::SRSHR_I", SDT_AArch64vshift>;
188 def AArch64urshri : SDNode<"AArch64ISD::URSHR_I", SDT_AArch64vshift>;
190 def AArch64not: SDNode<"AArch64ISD::NOT", SDT_AArch64unvec>;
191 def AArch64bit: SDNode<"AArch64ISD::BIT", SDT_AArch64trivec>;
192 def AArch64bsl: SDNode<"AArch64ISD::BSL", SDT_AArch64trivec>;
194 def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
195 def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>;
196 def AArch64cmgt: SDNode<"AArch64ISD::CMGT", SDT_AArch64binvec>;
197 def AArch64cmhi: SDNode<"AArch64ISD::CMHI", SDT_AArch64binvec>;
198 def AArch64cmhs: SDNode<"AArch64ISD::CMHS", SDT_AArch64binvec>;
200 def AArch64fcmeq: SDNode<"AArch64ISD::FCMEQ", SDT_AArch64fcmp>;
201 def AArch64fcmge: SDNode<"AArch64ISD::FCMGE", SDT_AArch64fcmp>;
202 def AArch64fcmgt: SDNode<"AArch64ISD::FCMGT", SDT_AArch64fcmp>;
204 def AArch64cmeqz: SDNode<"AArch64ISD::CMEQz", SDT_AArch64unvec>;
205 def AArch64cmgez: SDNode<"AArch64ISD::CMGEz", SDT_AArch64unvec>;
206 def AArch64cmgtz: SDNode<"AArch64ISD::CMGTz", SDT_AArch64unvec>;
207 def AArch64cmlez: SDNode<"AArch64ISD::CMLEz", SDT_AArch64unvec>;
208 def AArch64cmltz: SDNode<"AArch64ISD::CMLTz", SDT_AArch64unvec>;
209 def AArch64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
210 (AArch64not (AArch64cmeqz (and node:$LHS, node:$RHS)))>;
212 def AArch64fcmeqz: SDNode<"AArch64ISD::FCMEQz", SDT_AArch64fcmpz>;
213 def AArch64fcmgez: SDNode<"AArch64ISD::FCMGEz", SDT_AArch64fcmpz>;
214 def AArch64fcmgtz: SDNode<"AArch64ISD::FCMGTz", SDT_AArch64fcmpz>;
215 def AArch64fcmlez: SDNode<"AArch64ISD::FCMLEz", SDT_AArch64fcmpz>;
216 def AArch64fcmltz: SDNode<"AArch64ISD::FCMLTz", SDT_AArch64fcmpz>;
218 def AArch64bici: SDNode<"AArch64ISD::BICi", SDT_AArch64vecimm>;
219 def AArch64orri: SDNode<"AArch64ISD::ORRi", SDT_AArch64vecimm>;
221 def AArch64neg : SDNode<"AArch64ISD::NEG", SDT_AArch64unvec>;
223 def AArch64tcret: SDNode<"AArch64ISD::TC_RETURN", SDT_AArch64TCRET,
224 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
226 def AArch64Prefetch : SDNode<"AArch64ISD::PREFETCH", SDT_AArch64PREFETCH,
227 [SDNPHasChain, SDNPSideEffect]>;
229 def AArch64sitof: SDNode<"AArch64ISD::SITOF", SDT_AArch64ITOF>;
230 def AArch64uitof: SDNode<"AArch64ISD::UITOF", SDT_AArch64ITOF>;
232 def AArch64tlsdesc_call : SDNode<"AArch64ISD::TLSDESC_CALL",
233 SDT_AArch64TLSDescCall,
234 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
237 def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
238 SDT_AArch64WrapperLarge>;
240 def AArch64NvCast : SDNode<"AArch64ISD::NVCAST", SDTUnaryOp>;
242 def SDT_AArch64mull : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
243 SDTCisSameAs<1, 2>]>;
244 def AArch64smull : SDNode<"AArch64ISD::SMULL", SDT_AArch64mull>;
245 def AArch64umull : SDNode<"AArch64ISD::UMULL", SDT_AArch64mull>;
247 //===----------------------------------------------------------------------===//
249 //===----------------------------------------------------------------------===//
251 // AArch64 Instruction Predicate Definitions.
253 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
254 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
255 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
256 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
257 def ForCodeSize : Predicate<"ForCodeSize">;
258 def NotForCodeSize : Predicate<"!ForCodeSize">;
260 include "AArch64InstrFormats.td"
262 //===----------------------------------------------------------------------===//
264 //===----------------------------------------------------------------------===//
265 // Miscellaneous instructions.
266 //===----------------------------------------------------------------------===//
268 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
269 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
270 [(AArch64callseq_start timm:$amt)]>;
271 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
272 [(AArch64callseq_end timm:$amt1, timm:$amt2)]>;
273 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
275 let isReMaterializable = 1, isCodeGenOnly = 1 in {
276 // FIXME: The following pseudo instructions are only needed because remat
277 // cannot handle multiple instructions. When that changes, they can be
278 // removed, along with the AArch64Wrapper node.
280 let AddedComplexity = 10 in
281 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
282 [(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
285 // The MOVaddr instruction should match only when the add is not folded
286 // into a load or store address.
288 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
289 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
290 tglobaladdr:$low))]>,
291 Sched<[WriteAdrAdr]>;
293 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
294 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
296 Sched<[WriteAdrAdr]>;
298 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
299 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
301 Sched<[WriteAdrAdr]>;
303 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
304 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
305 tblockaddress:$low))]>,
306 Sched<[WriteAdrAdr]>;
308 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
309 [(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),
310 tglobaltlsaddr:$low))]>,
311 Sched<[WriteAdrAdr]>;
313 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
314 [(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),
315 texternalsym:$low))]>,
316 Sched<[WriteAdrAdr]>;
318 } // isReMaterializable, isCodeGenOnly
320 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
321 (LOADgot tglobaltlsaddr:$addr)>;
323 def : Pat<(AArch64LOADgot texternalsym:$addr),
324 (LOADgot texternalsym:$addr)>;
326 def : Pat<(AArch64LOADgot tconstpool:$addr),
327 (LOADgot tconstpool:$addr)>;
329 //===----------------------------------------------------------------------===//
330 // System instructions.
331 //===----------------------------------------------------------------------===//
333 def HINT : HintI<"hint">;
334 def : InstAlias<"nop", (HINT 0b000)>;
335 def : InstAlias<"yield",(HINT 0b001)>;
336 def : InstAlias<"wfe", (HINT 0b010)>;
337 def : InstAlias<"wfi", (HINT 0b011)>;
338 def : InstAlias<"sev", (HINT 0b100)>;
339 def : InstAlias<"sevl", (HINT 0b101)>;
341 // As far as LLVM is concerned this writes to the system's exclusive monitors.
342 let mayLoad = 1, mayStore = 1 in
343 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
345 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
346 // model patterns with sufficiently fine granularity.
347 let mayLoad = ?, mayStore = ? in {
348 def DMB : CRmSystemI<barrier_op, 0b101, "dmb",
349 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;
351 def DSB : CRmSystemI<barrier_op, 0b100, "dsb",
352 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
354 def ISB : CRmSystemI<barrier_op, 0b110, "isb",
355 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
358 def : InstAlias<"clrex", (CLREX 0xf)>;
359 def : InstAlias<"isb", (ISB 0xf)>;
363 def MSRpstate: MSRpstateI;
365 // The thread pointer (on Linux, at least, where this has been implemented) is
367 def : Pat<(AArch64threadpointer), (MRS 0xde82)>;
369 // Generic system instructions
370 def SYSxt : SystemXtI<0, "sys">;
371 def SYSLxt : SystemLXtI<1, "sysl">;
373 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
374 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
375 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
377 //===----------------------------------------------------------------------===//
378 // Move immediate instructions.
379 //===----------------------------------------------------------------------===//
381 defm MOVK : InsertImmediate<0b11, "movk">;
382 defm MOVN : MoveImmediate<0b00, "movn">;
384 let PostEncoderMethod = "fixMOVZ" in
385 defm MOVZ : MoveImmediate<0b10, "movz">;
387 // First group of aliases covers an implicit "lsl #0".
388 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
389 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
390 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
391 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
392 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
393 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
395 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
396 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
397 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
398 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
399 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
401 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
402 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
403 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
404 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
406 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
407 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
408 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
409 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
411 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
412 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
414 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
415 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
417 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
418 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
420 // Final group of aliases covers true "mov $Rd, $imm" cases.
421 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
422 int width, int shift> {
423 def _asmoperand : AsmOperandClass {
424 let Name = basename # width # "_lsl" # shift # "MovAlias";
425 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
427 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
430 def _movimm : Operand<i32> {
431 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
434 def : InstAlias<"mov $Rd, $imm",
435 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
438 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
439 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
441 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
442 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
443 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
444 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
446 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
447 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
449 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
450 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
451 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
452 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
454 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
455 isAsCheapAsAMove = 1 in {
456 // FIXME: The following pseudo instructions are only needed because remat
457 // cannot handle multiple instructions. When that changes, we can select
458 // directly to the real instructions and get rid of these pseudos.
461 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
462 [(set GPR32:$dst, imm:$src)]>,
465 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
466 [(set GPR64:$dst, imm:$src)]>,
468 } // isReMaterializable, isCodeGenOnly
470 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
471 // eventual expansion code fewer bits to worry about getting right. Marshalling
472 // the types is a little tricky though:
473 def i64imm_32bit : ImmLeaf<i64, [{
474 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
477 def trunc_imm : SDNodeXForm<imm, [{
478 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i32);
481 def : Pat<(i64 i64imm_32bit:$src),
482 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
484 // Materialize FP constants via MOVi32imm/MOVi64imm (MachO large code model).
485 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
486 return CurDAG->getTargetConstant(
487 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i32);
490 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
491 return CurDAG->getTargetConstant(
492 N->getValueAPF().bitcastToAPInt().getZExtValue(), MVT::i64);
496 def : Pat<(f32 fpimm:$in),
497 (COPY_TO_REGCLASS (MOVi32imm (bitcast_fpimm_to_i32 f32:$in)), FPR32)>;
498 def : Pat<(f64 fpimm:$in),
499 (COPY_TO_REGCLASS (MOVi64imm (bitcast_fpimm_to_i64 f64:$in)), FPR64)>;
502 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
504 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
505 tglobaladdr:$g1, tglobaladdr:$g0),
506 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
507 tglobaladdr:$g2, 32),
508 tglobaladdr:$g1, 16),
509 tglobaladdr:$g0, 0)>;
511 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
512 tblockaddress:$g1, tblockaddress:$g0),
513 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
514 tblockaddress:$g2, 32),
515 tblockaddress:$g1, 16),
516 tblockaddress:$g0, 0)>;
518 def : Pat<(AArch64WrapperLarge tconstpool:$g3, tconstpool:$g2,
519 tconstpool:$g1, tconstpool:$g0),
520 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
525 def : Pat<(AArch64WrapperLarge tjumptable:$g3, tjumptable:$g2,
526 tjumptable:$g1, tjumptable:$g0),
527 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
533 //===----------------------------------------------------------------------===//
534 // Arithmetic instructions.
535 //===----------------------------------------------------------------------===//
537 // Add/subtract with carry.
538 defm ADC : AddSubCarry<0, "adc", "adcs", AArch64adc, AArch64adc_flag>;
539 defm SBC : AddSubCarry<1, "sbc", "sbcs", AArch64sbc, AArch64sbc_flag>;
541 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
542 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
543 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
544 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
547 defm ADD : AddSub<0, "add", add>;
548 defm SUB : AddSub<1, "sub">;
550 def : InstAlias<"mov $dst, $src",
551 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
552 def : InstAlias<"mov $dst, $src",
553 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
554 def : InstAlias<"mov $dst, $src",
555 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
556 def : InstAlias<"mov $dst, $src",
557 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
559 defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn">;
560 defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp">;
562 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
563 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
564 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
565 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
566 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
567 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
568 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
569 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
570 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
571 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
572 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
573 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
574 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
575 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
576 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
577 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
578 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
580 // Because of the immediate format for add/sub-imm instructions, the
581 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
582 // These patterns capture that transformation.
583 let AddedComplexity = 1 in {
584 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
585 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
586 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
587 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
588 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
589 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
590 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
591 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
594 // Because of the immediate format for add/sub-imm instructions, the
595 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
596 // These patterns capture that transformation.
597 let AddedComplexity = 1 in {
598 def : Pat<(AArch64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
599 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
600 def : Pat<(AArch64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
601 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
602 def : Pat<(AArch64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
603 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
604 def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
605 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
608 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
609 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
610 def : InstAlias<"neg $dst, $src$shift",
611 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
612 def : InstAlias<"neg $dst, $src$shift",
613 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
615 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
616 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
617 def : InstAlias<"negs $dst, $src$shift",
618 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
619 def : InstAlias<"negs $dst, $src$shift",
620 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
623 // Unsigned/Signed divide
624 defm UDIV : Div<0, "udiv", udiv>;
625 defm SDIV : Div<1, "sdiv", sdiv>;
626 let isCodeGenOnly = 1 in {
627 defm UDIV_Int : Div<0, "udiv", int_aarch64_udiv>;
628 defm SDIV_Int : Div<1, "sdiv", int_aarch64_sdiv>;
632 defm ASRV : Shift<0b10, "asr", sra>;
633 defm LSLV : Shift<0b00, "lsl", shl>;
634 defm LSRV : Shift<0b01, "lsr", srl>;
635 defm RORV : Shift<0b11, "ror", rotr>;
637 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
638 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
639 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
640 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
641 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
642 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
643 def : ShiftAlias<"rorv", RORVWr, GPR32>;
644 def : ShiftAlias<"rorv", RORVXr, GPR64>;
647 let AddedComplexity = 7 in {
648 defm MADD : MulAccum<0, "madd", add>;
649 defm MSUB : MulAccum<1, "msub", sub>;
651 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
652 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
653 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
654 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
656 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
657 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
658 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
659 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
660 def : Pat<(i32 (mul (ineg GPR32:$Rn), GPR32:$Rm)),
661 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
662 def : Pat<(i64 (mul (ineg GPR64:$Rn), GPR64:$Rm)),
663 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
664 } // AddedComplexity = 7
666 let AddedComplexity = 5 in {
667 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
668 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
669 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
670 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
672 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
673 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
674 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
675 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
677 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
678 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
679 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
680 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
681 } // AddedComplexity = 5
683 def : MulAccumWAlias<"mul", MADDWrrr>;
684 def : MulAccumXAlias<"mul", MADDXrrr>;
685 def : MulAccumWAlias<"mneg", MSUBWrrr>;
686 def : MulAccumXAlias<"mneg", MSUBXrrr>;
687 def : WideMulAccumAlias<"smull", SMADDLrrr>;
688 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
689 def : WideMulAccumAlias<"umull", UMADDLrrr>;
690 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
693 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
694 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
697 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
698 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_aarch64_crc32h, "crc32h">;
699 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_aarch64_crc32w, "crc32w">;
700 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_aarch64_crc32x, "crc32x">;
702 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
703 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_aarch64_crc32ch, "crc32ch">;
704 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_aarch64_crc32cw, "crc32cw">;
705 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_aarch64_crc32cx, "crc32cx">;
708 //===----------------------------------------------------------------------===//
709 // Logical instructions.
710 //===----------------------------------------------------------------------===//
713 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
714 defm AND : LogicalImm<0b00, "and", and, "bic">;
715 defm EOR : LogicalImm<0b10, "eor", xor, "eon">;
716 defm ORR : LogicalImm<0b01, "orr", or, "orn">;
718 // FIXME: these aliases *are* canonical sometimes (when movz can't be
719 // used). Actually, it seems to be working right now, but putting logical_immXX
720 // here is a bit dodgy on the AsmParser side too.
721 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
722 logical_imm32:$imm), 0>;
723 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
724 logical_imm64:$imm), 0>;
728 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
729 defm BICS : LogicalRegS<0b11, 1, "bics",
730 BinOpFrag<(AArch64and_flag node:$LHS, (not node:$RHS))>>;
731 defm AND : LogicalReg<0b00, 0, "and", and>;
732 defm BIC : LogicalReg<0b00, 1, "bic",
733 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
734 defm EON : LogicalReg<0b10, 1, "eon",
735 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
736 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
737 defm ORN : LogicalReg<0b01, 1, "orn",
738 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
739 defm ORR : LogicalReg<0b01, 0, "orr", or>;
741 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
742 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
744 def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
745 def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
747 def : InstAlias<"mvn $Wd, $Wm$sh",
748 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
749 def : InstAlias<"mvn $Xd, $Xm$sh",
750 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
752 def : InstAlias<"tst $src1, $src2",
753 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
754 def : InstAlias<"tst $src1, $src2",
755 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
757 def : InstAlias<"tst $src1, $src2",
758 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
759 def : InstAlias<"tst $src1, $src2",
760 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
762 def : InstAlias<"tst $src1, $src2$sh",
763 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
764 def : InstAlias<"tst $src1, $src2$sh",
765 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
768 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
769 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
772 //===----------------------------------------------------------------------===//
773 // One operand data processing instructions.
774 //===----------------------------------------------------------------------===//
776 defm CLS : OneOperandData<0b101, "cls">;
777 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
778 defm RBIT : OneOperandData<0b000, "rbit">;
780 def : Pat<(int_aarch64_rbit GPR32:$Rn), (RBITWr $Rn)>;
781 def : Pat<(int_aarch64_rbit GPR64:$Rn), (RBITXr $Rn)>;
783 def REV16Wr : OneWRegData<0b001, "rev16",
784 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
785 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
787 def : Pat<(cttz GPR32:$Rn),
788 (CLZWr (RBITWr GPR32:$Rn))>;
789 def : Pat<(cttz GPR64:$Rn),
790 (CLZXr (RBITXr GPR64:$Rn))>;
791 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
794 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
798 // Unlike the other one operand instructions, the instructions with the "rev"
799 // mnemonic do *not* just different in the size bit, but actually use different
800 // opcode bits for the different sizes.
801 def REVWr : OneWRegData<0b010, "rev", bswap>;
802 def REVXr : OneXRegData<0b011, "rev", bswap>;
803 def REV32Xr : OneXRegData<0b010, "rev32",
804 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
806 // The bswap commutes with the rotr so we want a pattern for both possible
808 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
809 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
811 //===----------------------------------------------------------------------===//
812 // Bitfield immediate extraction instruction.
813 //===----------------------------------------------------------------------===//
814 let hasSideEffects = 0 in
815 defm EXTR : ExtractImm<"extr">;
816 def : InstAlias<"ror $dst, $src, $shift",
817 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
818 def : InstAlias<"ror $dst, $src, $shift",
819 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
821 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
822 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
823 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
824 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
826 //===----------------------------------------------------------------------===//
827 // Other bitfield immediate instructions.
828 //===----------------------------------------------------------------------===//
829 let hasSideEffects = 0 in {
830 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
831 defm SBFM : BitfieldImm<0b00, "sbfm">;
832 defm UBFM : BitfieldImm<0b10, "ubfm">;
835 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
836 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
837 return CurDAG->getTargetConstant(enc, MVT::i64);
840 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
841 uint64_t enc = 31 - N->getZExtValue();
842 return CurDAG->getTargetConstant(enc, MVT::i64);
845 // min(7, 31 - shift_amt)
846 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
847 uint64_t enc = 31 - N->getZExtValue();
848 enc = enc > 7 ? 7 : enc;
849 return CurDAG->getTargetConstant(enc, MVT::i64);
852 // min(15, 31 - shift_amt)
853 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
854 uint64_t enc = 31 - N->getZExtValue();
855 enc = enc > 15 ? 15 : enc;
856 return CurDAG->getTargetConstant(enc, MVT::i64);
859 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
860 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
861 return CurDAG->getTargetConstant(enc, MVT::i64);
864 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
865 uint64_t enc = 63 - N->getZExtValue();
866 return CurDAG->getTargetConstant(enc, MVT::i64);
869 // min(7, 63 - shift_amt)
870 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
871 uint64_t enc = 63 - N->getZExtValue();
872 enc = enc > 7 ? 7 : enc;
873 return CurDAG->getTargetConstant(enc, MVT::i64);
876 // min(15, 63 - shift_amt)
877 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
878 uint64_t enc = 63 - N->getZExtValue();
879 enc = enc > 15 ? 15 : enc;
880 return CurDAG->getTargetConstant(enc, MVT::i64);
883 // min(31, 63 - shift_amt)
884 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
885 uint64_t enc = 63 - N->getZExtValue();
886 enc = enc > 31 ? 31 : enc;
887 return CurDAG->getTargetConstant(enc, MVT::i64);
890 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
891 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
892 (i64 (i32shift_b imm0_31:$imm)))>;
893 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
894 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
895 (i64 (i64shift_b imm0_63:$imm)))>;
897 let AddedComplexity = 10 in {
898 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
899 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
900 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
901 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
904 def : InstAlias<"asr $dst, $src, $shift",
905 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
906 def : InstAlias<"asr $dst, $src, $shift",
907 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
908 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
909 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
910 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
911 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
912 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
914 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
915 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
916 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
917 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
919 def : InstAlias<"lsr $dst, $src, $shift",
920 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
921 def : InstAlias<"lsr $dst, $src, $shift",
922 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
923 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
924 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
925 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
926 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
927 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
929 //===----------------------------------------------------------------------===//
930 // Conditionally set flags instructions.
931 //===----------------------------------------------------------------------===//
932 defm CCMN : CondSetFlagsImm<0, "ccmn">;
933 defm CCMP : CondSetFlagsImm<1, "ccmp">;
935 defm CCMN : CondSetFlagsReg<0, "ccmn">;
936 defm CCMP : CondSetFlagsReg<1, "ccmp">;
938 //===----------------------------------------------------------------------===//
939 // Conditional select instructions.
940 //===----------------------------------------------------------------------===//
941 defm CSEL : CondSelect<0, 0b00, "csel">;
943 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
944 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
945 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
946 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
948 def : Pat<(AArch64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
949 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
950 def : Pat<(AArch64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
951 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
952 def : Pat<(AArch64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
953 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
954 def : Pat<(AArch64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
955 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
956 def : Pat<(AArch64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
957 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
958 def : Pat<(AArch64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
959 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
961 def : Pat<(AArch64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
962 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
963 def : Pat<(AArch64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
964 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
965 def : Pat<(AArch64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
966 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
967 def : Pat<(AArch64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
968 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
970 // The inverse of the condition code from the alias instruction is what is used
971 // in the aliased instruction. The parser all ready inverts the condition code
972 // for these aliases.
973 def : InstAlias<"cset $dst, $cc",
974 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
975 def : InstAlias<"cset $dst, $cc",
976 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
978 def : InstAlias<"csetm $dst, $cc",
979 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
980 def : InstAlias<"csetm $dst, $cc",
981 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
983 def : InstAlias<"cinc $dst, $src, $cc",
984 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
985 def : InstAlias<"cinc $dst, $src, $cc",
986 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
988 def : InstAlias<"cinv $dst, $src, $cc",
989 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
990 def : InstAlias<"cinv $dst, $src, $cc",
991 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
993 def : InstAlias<"cneg $dst, $src, $cc",
994 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
995 def : InstAlias<"cneg $dst, $src, $cc",
996 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
998 //===----------------------------------------------------------------------===//
999 // PC-relative instructions.
1000 //===----------------------------------------------------------------------===//
1001 let isReMaterializable = 1 in {
1002 let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in {
1003 def ADR : ADRI<0, "adr", adrlabel, []>;
1004 } // hasSideEffects = 0
1006 def ADRP : ADRI<1, "adrp", adrplabel,
1007 [(set GPR64:$Xd, (AArch64adrp tglobaladdr:$label))]>;
1008 } // isReMaterializable = 1
1010 // page address of a constant pool entry, block address
1011 def : Pat<(AArch64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
1012 def : Pat<(AArch64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
1014 //===----------------------------------------------------------------------===//
1015 // Unconditional branch (register) instructions.
1016 //===----------------------------------------------------------------------===//
1018 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
1019 def RET : BranchReg<0b0010, "ret", []>;
1020 def DRPS : SpecialReturn<0b0101, "drps">;
1021 def ERET : SpecialReturn<0b0100, "eret">;
1022 } // isReturn = 1, isTerminator = 1, isBarrier = 1
1024 // Default to the LR register.
1025 def : InstAlias<"ret", (RET LR)>;
1027 let isCall = 1, Defs = [LR], Uses = [SP] in {
1028 def BLR : BranchReg<0b0001, "blr", [(AArch64call GPR64:$Rn)]>;
1031 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1032 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
1033 } // isBranch, isTerminator, isBarrier, isIndirectBranch
1035 // Create a separate pseudo-instruction for codegen to use so that we don't
1036 // flag lr as used in every function. It'll be restored before the RET by the
1037 // epilogue if it's legitimately used.
1038 def RET_ReallyLR : Pseudo<(outs), (ins), [(AArch64retflag)]> {
1039 let isTerminator = 1;
1044 // This is a directive-like pseudo-instruction. The purpose is to insert an
1045 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
1046 // (which in the usual case is a BLR).
1047 let hasSideEffects = 1 in
1048 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
1049 let AsmString = ".tlsdesccall $sym";
1052 // Pseudo-instruction representing a BLR with attached TLSDESC relocation. It
1053 // gets expanded to two MCInsts during lowering.
1054 let isCall = 1, Defs = [LR] in
1056 : Pseudo<(outs), (ins GPR64:$dest, i64imm:$sym),
1057 [(AArch64tlsdesc_call GPR64:$dest, tglobaltlsaddr:$sym)]>;
1059 def : Pat<(AArch64tlsdesc_call GPR64:$dest, texternalsym:$sym),
1060 (TLSDESC_BLR GPR64:$dest, texternalsym:$sym)>;
1061 //===----------------------------------------------------------------------===//
1062 // Conditional branch (immediate) instruction.
1063 //===----------------------------------------------------------------------===//
1064 def Bcc : BranchCond;
1066 //===----------------------------------------------------------------------===//
1067 // Compare-and-branch instructions.
1068 //===----------------------------------------------------------------------===//
1069 defm CBZ : CmpBranch<0, "cbz", AArch64cbz>;
1070 defm CBNZ : CmpBranch<1, "cbnz", AArch64cbnz>;
1072 //===----------------------------------------------------------------------===//
1073 // Test-bit-and-branch instructions.
1074 //===----------------------------------------------------------------------===//
1075 defm TBZ : TestBranch<0, "tbz", AArch64tbz>;
1076 defm TBNZ : TestBranch<1, "tbnz", AArch64tbnz>;
1078 //===----------------------------------------------------------------------===//
1079 // Unconditional branch (immediate) instructions.
1080 //===----------------------------------------------------------------------===//
1081 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1082 def B : BranchImm<0, "b", [(br bb:$addr)]>;
1083 } // isBranch, isTerminator, isBarrier
1085 let isCall = 1, Defs = [LR], Uses = [SP] in {
1086 def BL : CallImm<1, "bl", [(AArch64call tglobaladdr:$addr)]>;
1088 def : Pat<(AArch64call texternalsym:$func), (BL texternalsym:$func)>;
1090 //===----------------------------------------------------------------------===//
1091 // Exception generation instructions.
1092 //===----------------------------------------------------------------------===//
1093 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1094 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1095 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
1096 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1097 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1098 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1099 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1100 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1102 // DCPSn defaults to an immediate operand of zero if unspecified.
1103 def : InstAlias<"dcps1", (DCPS1 0)>;
1104 def : InstAlias<"dcps2", (DCPS2 0)>;
1105 def : InstAlias<"dcps3", (DCPS3 0)>;
1107 //===----------------------------------------------------------------------===//
1108 // Load instructions.
1109 //===----------------------------------------------------------------------===//
1111 // Pair (indexed, offset)
1112 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1113 defm LDPX : LoadPairOffset<0b10, 0, GPR64, simm7s8, "ldp">;
1114 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1115 defm LDPD : LoadPairOffset<0b01, 1, FPR64, simm7s8, "ldp">;
1116 defm LDPQ : LoadPairOffset<0b10, 1, FPR128, simm7s16, "ldp">;
1118 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
1120 // Pair (pre-indexed)
1121 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1122 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1123 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1124 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1125 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1127 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1129 // Pair (post-indexed)
1130 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1131 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1132 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1133 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1134 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1136 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1139 // Pair (no allocate)
1140 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1141 defm LDNPX : LoadPairNoAlloc<0b10, 0, GPR64, simm7s8, "ldnp">;
1142 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1143 defm LDNPD : LoadPairNoAlloc<0b01, 1, FPR64, simm7s8, "ldnp">;
1144 defm LDNPQ : LoadPairNoAlloc<0b10, 1, FPR128, simm7s16, "ldnp">;
1147 // (register offset)
1151 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1152 defm LDRHH : Load16RO<0b01, 0, 0b01, GPR32, "ldrh", i32, zextloadi16>;
1153 defm LDRW : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
1154 defm LDRX : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;
1157 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1158 defm LDRH : Load16RO<0b01, 1, 0b01, FPR16, "ldr", f16, load>;
1159 defm LDRS : Load32RO<0b10, 1, 0b01, FPR32, "ldr", f32, load>;
1160 defm LDRD : Load64RO<0b11, 1, 0b01, FPR64, "ldr", f64, load>;
1161 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1163 // Load sign-extended half-word
1164 defm LDRSHW : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh", i32, sextloadi16>;
1165 defm LDRSHX : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh", i64, sextloadi16>;
1167 // Load sign-extended byte
1168 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1169 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1171 // Load sign-extended word
1172 defm LDRSW : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw", i64, sextloadi32>;
1175 defm PRFM : PrefetchRO<0b11, 0, 0b10, "prfm">;
1177 // For regular load, we do not have any alignment requirement.
1178 // Thus, it is safe to directly map the vector loads with interesting
1179 // addressing modes.
1180 // FIXME: We could do the same for bitconvert to floating point vectors.
1181 multiclass ScalToVecROLoadPat<ROAddrMode ro, SDPatternOperator loadop,
1182 ValueType ScalTy, ValueType VecTy,
1183 Instruction LOADW, Instruction LOADX,
1185 def : Pat<(VecTy (scalar_to_vector (ScalTy
1186 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset))))),
1187 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1188 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$offset),
1191 def : Pat<(VecTy (scalar_to_vector (ScalTy
1192 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset))))),
1193 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1194 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$offset),
1198 let AddedComplexity = 10 in {
1199 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v8i8, LDRBroW, LDRBroX, bsub>;
1200 defm : ScalToVecROLoadPat<ro8, extloadi8, i32, v16i8, LDRBroW, LDRBroX, bsub>;
1202 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v4i16, LDRHroW, LDRHroX, hsub>;
1203 defm : ScalToVecROLoadPat<ro16, extloadi16, i32, v8i16, LDRHroW, LDRHroX, hsub>;
1205 defm : ScalToVecROLoadPat<ro16, load, i32, v4f16, LDRHroW, LDRHroX, hsub>;
1206 defm : ScalToVecROLoadPat<ro16, load, i32, v8f16, LDRHroW, LDRHroX, hsub>;
1208 defm : ScalToVecROLoadPat<ro32, load, i32, v2i32, LDRSroW, LDRSroX, ssub>;
1209 defm : ScalToVecROLoadPat<ro32, load, i32, v4i32, LDRSroW, LDRSroX, ssub>;
1211 defm : ScalToVecROLoadPat<ro32, load, f32, v2f32, LDRSroW, LDRSroX, ssub>;
1212 defm : ScalToVecROLoadPat<ro32, load, f32, v4f32, LDRSroW, LDRSroX, ssub>;
1214 defm : ScalToVecROLoadPat<ro64, load, i64, v2i64, LDRDroW, LDRDroX, dsub>;
1216 defm : ScalToVecROLoadPat<ro64, load, f64, v2f64, LDRDroW, LDRDroX, dsub>;
1219 def : Pat <(v1i64 (scalar_to_vector (i64
1220 (load (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
1221 ro_Wextend64:$extend))))),
1222 (LDRDroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend)>;
1224 def : Pat <(v1i64 (scalar_to_vector (i64
1225 (load (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
1226 ro_Xextend64:$extend))))),
1227 (LDRDroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
1230 // Match all load 64 bits width whose type is compatible with FPR64
1231 multiclass VecROLoadPat<ROAddrMode ro, ValueType VecTy,
1232 Instruction LOADW, Instruction LOADX> {
1234 def : Pat<(VecTy (load (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1235 (LOADW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1237 def : Pat<(VecTy (load (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1238 (LOADX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1241 let AddedComplexity = 10 in {
1242 let Predicates = [IsLE] in {
1243 // We must do vector loads with LD1 in big-endian.
1244 defm : VecROLoadPat<ro64, v2i32, LDRDroW, LDRDroX>;
1245 defm : VecROLoadPat<ro64, v2f32, LDRDroW, LDRDroX>;
1246 defm : VecROLoadPat<ro64, v8i8, LDRDroW, LDRDroX>;
1247 defm : VecROLoadPat<ro64, v4i16, LDRDroW, LDRDroX>;
1248 defm : VecROLoadPat<ro64, v4f16, LDRDroW, LDRDroX>;
1251 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
1252 defm : VecROLoadPat<ro64, v1f64, LDRDroW, LDRDroX>;
1254 // Match all load 128 bits width whose type is compatible with FPR128
1255 let Predicates = [IsLE] in {
1256 // We must do vector loads with LD1 in big-endian.
1257 defm : VecROLoadPat<ro128, v2i64, LDRQroW, LDRQroX>;
1258 defm : VecROLoadPat<ro128, v2f64, LDRQroW, LDRQroX>;
1259 defm : VecROLoadPat<ro128, v4i32, LDRQroW, LDRQroX>;
1260 defm : VecROLoadPat<ro128, v4f32, LDRQroW, LDRQroX>;
1261 defm : VecROLoadPat<ro128, v8i16, LDRQroW, LDRQroX>;
1262 defm : VecROLoadPat<ro128, v8f16, LDRQroW, LDRQroX>;
1263 defm : VecROLoadPat<ro128, v16i8, LDRQroW, LDRQroX>;
1265 } // AddedComplexity = 10
1268 multiclass ExtLoadTo64ROPat<ROAddrMode ro, SDPatternOperator loadop,
1269 Instruction INSTW, Instruction INSTX> {
1270 def : Pat<(i64 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1271 (SUBREG_TO_REG (i64 0),
1272 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
1275 def : Pat<(i64 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1276 (SUBREG_TO_REG (i64 0),
1277 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
1281 let AddedComplexity = 10 in {
1282 defm : ExtLoadTo64ROPat<ro8, zextloadi8, LDRBBroW, LDRBBroX>;
1283 defm : ExtLoadTo64ROPat<ro16, zextloadi16, LDRHHroW, LDRHHroX>;
1284 defm : ExtLoadTo64ROPat<ro32, zextloadi32, LDRWroW, LDRWroX>;
1286 // zextloadi1 -> zextloadi8
1287 defm : ExtLoadTo64ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1289 // extload -> zextload
1290 defm : ExtLoadTo64ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1291 defm : ExtLoadTo64ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1292 defm : ExtLoadTo64ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1294 // extloadi1 -> zextloadi8
1295 defm : ExtLoadTo64ROPat<ro8, extloadi1, LDRBBroW, LDRBBroX>;
1300 multiclass ExtLoadTo32ROPat<ROAddrMode ro, SDPatternOperator loadop,
1301 Instruction INSTW, Instruction INSTX> {
1302 def : Pat<(i32 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend))),
1303 (INSTW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1305 def : Pat<(i32 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend))),
1306 (INSTX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1310 let AddedComplexity = 10 in {
1311 // extload -> zextload
1312 defm : ExtLoadTo32ROPat<ro8, extloadi8, LDRBBroW, LDRBBroX>;
1313 defm : ExtLoadTo32ROPat<ro16, extloadi16, LDRHHroW, LDRHHroX>;
1314 defm : ExtLoadTo32ROPat<ro32, extloadi32, LDRWroW, LDRWroX>;
1316 // zextloadi1 -> zextloadi8
1317 defm : ExtLoadTo32ROPat<ro8, zextloadi1, LDRBBroW, LDRBBroX>;
1321 // (unsigned immediate)
1323 defm LDRX : LoadUI<0b11, 0, 0b01, GPR64, uimm12s8, "ldr",
1325 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1326 defm LDRW : LoadUI<0b10, 0, 0b01, GPR32, uimm12s4, "ldr",
1328 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1329 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1331 (load (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)))]>;
1332 defm LDRH : LoadUI<0b01, 1, 0b01, FPR16, uimm12s2, "ldr",
1333 [(set (f16 FPR16:$Rt),
1334 (load (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)))]>;
1335 defm LDRS : LoadUI<0b10, 1, 0b01, FPR32, uimm12s4, "ldr",
1336 [(set (f32 FPR32:$Rt),
1337 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
1338 defm LDRD : LoadUI<0b11, 1, 0b01, FPR64, uimm12s8, "ldr",
1339 [(set (f64 FPR64:$Rt),
1340 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;
1341 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1342 [(set (f128 FPR128:$Rt),
1343 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)))]>;
1345 // For regular load, we do not have any alignment requirement.
1346 // Thus, it is safe to directly map the vector loads with interesting
1347 // addressing modes.
1348 // FIXME: We could do the same for bitconvert to floating point vectors.
1349 def : Pat <(v8i8 (scalar_to_vector (i32
1350 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1351 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1352 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1353 def : Pat <(v16i8 (scalar_to_vector (i32
1354 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
1355 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1356 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub)>;
1357 def : Pat <(v4i16 (scalar_to_vector (i32
1358 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1359 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1360 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1361 def : Pat <(v8i16 (scalar_to_vector (i32
1362 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
1363 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1364 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub)>;
1365 def : Pat <(v2i32 (scalar_to_vector (i32
1366 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1367 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1368 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1369 def : Pat <(v4i32 (scalar_to_vector (i32
1370 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
1371 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1372 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub)>;
1373 def : Pat <(v1i64 (scalar_to_vector (i64
1374 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1375 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1376 def : Pat <(v2i64 (scalar_to_vector (i64
1377 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))))),
1378 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1379 (LDRDui GPR64sp:$Rn, uimm12s8:$offset), dsub)>;
1381 // Match all load 64 bits width whose type is compatible with FPR64
1382 let Predicates = [IsLE] in {
1383 // We must use LD1 to perform vector loads in big-endian.
1384 def : Pat<(v2f32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1385 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1386 def : Pat<(v8i8 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1387 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1388 def : Pat<(v4i16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1389 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1390 def : Pat<(v2i32 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1391 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1392 def : Pat<(v4f16 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1393 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1395 def : Pat<(v1f64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1396 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1397 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
1398 (LDRDui GPR64sp:$Rn, uimm12s8:$offset)>;
1400 // Match all load 128 bits width whose type is compatible with FPR128
1401 let Predicates = [IsLE] in {
1402 // We must use LD1 to perform vector loads in big-endian.
1403 def : Pat<(v4f32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1404 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1405 def : Pat<(v2f64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1406 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1407 def : Pat<(v16i8 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1408 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1409 def : Pat<(v8i16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1410 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1411 def : Pat<(v4i32 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1412 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1413 def : Pat<(v2i64 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1414 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1415 def : Pat<(v8f16 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1416 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1418 def : Pat<(f128 (load (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset))),
1419 (LDRQui GPR64sp:$Rn, uimm12s16:$offset)>;
1421 defm LDRHH : LoadUI<0b01, 0, 0b01, GPR32, uimm12s2, "ldrh",
1423 (zextloadi16 (am_indexed16 GPR64sp:$Rn,
1424 uimm12s2:$offset)))]>;
1425 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1427 (zextloadi8 (am_indexed8 GPR64sp:$Rn,
1428 uimm12s1:$offset)))]>;
1430 def : Pat<(i64 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1431 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1432 def : Pat<(i64 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1433 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1435 // zextloadi1 -> zextloadi8
1436 def : Pat<(i32 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1437 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1438 def : Pat<(i64 (zextloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1439 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1441 // extload -> zextload
1442 def : Pat<(i32 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1443 (LDRHHui GPR64sp:$Rn, uimm12s2:$offset)>;
1444 def : Pat<(i32 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1445 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1446 def : Pat<(i32 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1447 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
1448 def : Pat<(i64 (extloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1449 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1450 def : Pat<(i64 (extloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))),
1451 (SUBREG_TO_REG (i64 0), (LDRHHui GPR64sp:$Rn, uimm12s2:$offset), sub_32)>;
1452 def : Pat<(i64 (extloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1453 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1454 def : Pat<(i64 (extloadi1 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))),
1455 (SUBREG_TO_REG (i64 0), (LDRBBui GPR64sp:$Rn, uimm12s1:$offset), sub_32)>;
1457 // load sign-extended half-word
1458 defm LDRSHW : LoadUI<0b01, 0, 0b11, GPR32, uimm12s2, "ldrsh",
1460 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1461 uimm12s2:$offset)))]>;
1462 defm LDRSHX : LoadUI<0b01, 0, 0b10, GPR64, uimm12s2, "ldrsh",
1464 (sextloadi16 (am_indexed16 GPR64sp:$Rn,
1465 uimm12s2:$offset)))]>;
1467 // load sign-extended byte
1468 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1470 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1471 uimm12s1:$offset)))]>;
1472 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1474 (sextloadi8 (am_indexed8 GPR64sp:$Rn,
1475 uimm12s1:$offset)))]>;
1477 // load sign-extended word
1478 defm LDRSW : LoadUI<0b10, 0, 0b10, GPR64, uimm12s4, "ldrsw",
1480 (sextloadi32 (am_indexed32 GPR64sp:$Rn,
1481 uimm12s4:$offset)))]>;
1483 // load zero-extended word
1484 def : Pat<(i64 (zextloadi32 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))),
1485 (SUBREG_TO_REG (i64 0), (LDRWui GPR64sp:$Rn, uimm12s4:$offset), sub_32)>;
1488 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1489 [(AArch64Prefetch imm:$Rt,
1490 (am_indexed64 GPR64sp:$Rn,
1491 uimm12s8:$offset))]>;
1493 def : InstAlias<"prfm $Rt, [$Rn]", (PRFMui prfop:$Rt, GPR64sp:$Rn, 0)>;
1497 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1498 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1499 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1500 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1501 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1503 // load sign-extended word
1504 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1507 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1508 // [(AArch64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1511 // (unscaled immediate)
1512 defm LDURX : LoadUnscaled<0b11, 0, 0b01, GPR64, "ldur",
1514 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1515 defm LDURW : LoadUnscaled<0b10, 0, 0b01, GPR32, "ldur",
1517 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1518 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1520 (load (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1521 defm LDURH : LoadUnscaled<0b01, 1, 0b01, FPR16, "ldur",
1523 (load (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1524 defm LDURS : LoadUnscaled<0b10, 1, 0b01, FPR32, "ldur",
1525 [(set (f32 FPR32:$Rt),
1526 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1527 defm LDURD : LoadUnscaled<0b11, 1, 0b01, FPR64, "ldur",
1528 [(set (f64 FPR64:$Rt),
1529 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset)))]>;
1530 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1531 [(set (f128 FPR128:$Rt),
1532 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset)))]>;
1535 : LoadUnscaled<0b01, 0, 0b01, GPR32, "ldurh",
1537 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1539 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1541 (zextloadi8 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1543 // Match all load 64 bits width whose type is compatible with FPR64
1544 let Predicates = [IsLE] in {
1545 def : Pat<(v2f32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1546 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1547 def : Pat<(v2i32 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1548 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1549 def : Pat<(v4i16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1550 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1551 def : Pat<(v8i8 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1552 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1553 def : Pat<(v4f16 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1554 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1556 def : Pat<(v1f64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1557 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1558 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
1559 (LDURDi GPR64sp:$Rn, simm9:$offset)>;
1561 // Match all load 128 bits width whose type is compatible with FPR128
1562 let Predicates = [IsLE] in {
1563 def : Pat<(v2f64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1564 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1565 def : Pat<(v2i64 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1566 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1567 def : Pat<(v4f32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1568 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1569 def : Pat<(v4i32 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1570 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1571 def : Pat<(v8i16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1572 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1573 def : Pat<(v16i8 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1574 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1575 def : Pat<(v8f16 (load (am_unscaled128 GPR64sp:$Rn, simm9:$offset))),
1576 (LDURQi GPR64sp:$Rn, simm9:$offset)>;
1580 def : Pat<(i32 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1581 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1582 def : Pat<(i32 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1583 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1584 def : Pat<(i32 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1585 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1586 def : Pat<(i64 (extloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1587 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1588 def : Pat<(i64 (extloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1589 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1590 def : Pat<(i64 (extloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1591 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1592 def : Pat<(i64 (extloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1593 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1595 def : Pat<(i32 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1596 (LDURHHi GPR64sp:$Rn, simm9:$offset)>;
1597 def : Pat<(i32 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1598 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1599 def : Pat<(i32 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1600 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
1601 def : Pat<(i64 (zextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
1602 (SUBREG_TO_REG (i64 0), (LDURWi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1603 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1604 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1605 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1606 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1607 def : Pat<(i64 (zextloadi1 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1608 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1612 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1614 // Define new assembler match classes as we want to only match these when
1615 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1616 // associate a DiagnosticType either, as we want the diagnostic for the
1617 // canonical form (the scaled operand) to take precedence.
1618 class SImm9OffsetOperand<int Width> : AsmOperandClass {
1619 let Name = "SImm9OffsetFB" # Width;
1620 let PredicateMethod = "isSImm9OffsetFB<" # Width # ">";
1621 let RenderMethod = "addImmOperands";
1624 def SImm9OffsetFB8Operand : SImm9OffsetOperand<8>;
1625 def SImm9OffsetFB16Operand : SImm9OffsetOperand<16>;
1626 def SImm9OffsetFB32Operand : SImm9OffsetOperand<32>;
1627 def SImm9OffsetFB64Operand : SImm9OffsetOperand<64>;
1628 def SImm9OffsetFB128Operand : SImm9OffsetOperand<128>;
1630 def simm9_offset_fb8 : Operand<i64> {
1631 let ParserMatchClass = SImm9OffsetFB8Operand;
1633 def simm9_offset_fb16 : Operand<i64> {
1634 let ParserMatchClass = SImm9OffsetFB16Operand;
1636 def simm9_offset_fb32 : Operand<i64> {
1637 let ParserMatchClass = SImm9OffsetFB32Operand;
1639 def simm9_offset_fb64 : Operand<i64> {
1640 let ParserMatchClass = SImm9OffsetFB64Operand;
1642 def simm9_offset_fb128 : Operand<i64> {
1643 let ParserMatchClass = SImm9OffsetFB128Operand;
1646 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1647 (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1648 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1649 (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1650 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1651 (LDURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1652 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1653 (LDURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1654 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1655 (LDURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1656 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1657 (LDURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
1658 def : InstAlias<"ldr $Rt, [$Rn, $offset]",
1659 (LDURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
1662 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
1663 (SUBREG_TO_REG (i64 0), (LDURBBi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1664 def : Pat<(i64 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
1665 (SUBREG_TO_REG (i64 0), (LDURHHi GPR64sp:$Rn, simm9:$offset), sub_32)>;
1667 // load sign-extended half-word
1669 : LoadUnscaled<0b01, 0, 0b11, GPR32, "ldursh",
1671 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1673 : LoadUnscaled<0b01, 0, 0b10, GPR64, "ldursh",
1675 (sextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset)))]>;
1677 // load sign-extended byte
1679 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1681 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1683 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1685 (sextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)))]>;
1687 // load sign-extended word
1689 : LoadUnscaled<0b10, 0, 0b10, GPR64, "ldursw",
1691 (sextloadi32 (am_unscaled32 GPR64sp:$Rn, simm9:$offset)))]>;
1693 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1694 def : InstAlias<"ldrb $Rt, [$Rn, $offset]",
1695 (LDURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1696 def : InstAlias<"ldrh $Rt, [$Rn, $offset]",
1697 (LDURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1698 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1699 (LDURSBWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1700 def : InstAlias<"ldrsb $Rt, [$Rn, $offset]",
1701 (LDURSBXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
1702 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1703 (LDURSHWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1704 def : InstAlias<"ldrsh $Rt, [$Rn, $offset]",
1705 (LDURSHXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
1706 def : InstAlias<"ldrsw $Rt, [$Rn, $offset]",
1707 (LDURSWi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
1710 defm PRFUM : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1711 [(AArch64Prefetch imm:$Rt,
1712 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1715 // (unscaled immediate, unprivileged)
1716 defm LDTRX : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1717 defm LDTRW : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1719 defm LDTRH : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1720 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1722 // load sign-extended half-word
1723 defm LDTRSHW : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1724 defm LDTRSHX : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1726 // load sign-extended byte
1727 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1728 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1730 // load sign-extended word
1731 defm LDTRSW : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1734 // (immediate pre-indexed)
1735 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1736 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1737 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1738 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1739 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1740 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1741 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1743 // load sign-extended half-word
1744 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1745 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1747 // load sign-extended byte
1748 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1749 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1751 // load zero-extended byte
1752 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1753 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1755 // load sign-extended word
1756 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1759 // (immediate post-indexed)
1760 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1761 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1762 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1763 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1764 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1765 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1766 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1768 // load sign-extended half-word
1769 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1770 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1772 // load sign-extended byte
1773 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1774 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1776 // load zero-extended byte
1777 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1778 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1780 // load sign-extended word
1781 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1783 //===----------------------------------------------------------------------===//
1784 // Store instructions.
1785 //===----------------------------------------------------------------------===//
1787 // Pair (indexed, offset)
1788 // FIXME: Use dedicated range-checked addressing mode operand here.
1789 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1790 defm STPX : StorePairOffset<0b10, 0, GPR64, simm7s8, "stp">;
1791 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1792 defm STPD : StorePairOffset<0b01, 1, FPR64, simm7s8, "stp">;
1793 defm STPQ : StorePairOffset<0b10, 1, FPR128, simm7s16, "stp">;
1795 // Pair (pre-indexed)
1796 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1797 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, simm7s8, "stp">;
1798 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1799 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, simm7s8, "stp">;
1800 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, simm7s16, "stp">;
1802 // Pair (pre-indexed)
1803 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1804 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1805 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1806 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1807 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1809 // Pair (no allocate)
1810 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
1811 defm STNPX : StorePairNoAlloc<0b10, 0, GPR64, simm7s8, "stnp">;
1812 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
1813 defm STNPD : StorePairNoAlloc<0b01, 1, FPR64, simm7s8, "stnp">;
1814 defm STNPQ : StorePairNoAlloc<0b10, 1, FPR128, simm7s16, "stnp">;
1817 // (Register offset)
1820 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
1821 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
1822 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
1823 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
1827 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
1828 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
1829 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
1830 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
1831 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
1833 multiclass TruncStoreFrom64ROPat<ROAddrMode ro, SDPatternOperator storeop,
1834 Instruction STRW, Instruction STRX> {
1836 def : Pat<(storeop GPR64:$Rt,
1837 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1838 (STRW (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1839 GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1841 def : Pat<(storeop GPR64:$Rt,
1842 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1843 (STRX (EXTRACT_SUBREG GPR64:$Rt, sub_32),
1844 GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1847 let AddedComplexity = 10 in {
1849 defm : TruncStoreFrom64ROPat<ro8, truncstorei8, STRBBroW, STRBBroX>;
1850 defm : TruncStoreFrom64ROPat<ro16, truncstorei16, STRHHroW, STRHHroX>;
1851 defm : TruncStoreFrom64ROPat<ro32, truncstorei32, STRWroW, STRWroX>;
1854 multiclass VecROStorePat<ROAddrMode ro, ValueType VecTy, RegisterClass FPR,
1855 Instruction STRW, Instruction STRX> {
1856 def : Pat<(store (VecTy FPR:$Rt),
1857 (ro.Wpat GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)),
1858 (STRW FPR:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend)>;
1860 def : Pat<(store (VecTy FPR:$Rt),
1861 (ro.Xpat GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)),
1862 (STRX FPR:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend)>;
1865 let AddedComplexity = 10 in {
1866 // Match all store 64 bits width whose type is compatible with FPR64
1867 let Predicates = [IsLE] in {
1868 // We must use ST1 to store vectors in big-endian.
1869 defm : VecROStorePat<ro64, v2i32, FPR64, STRDroW, STRDroX>;
1870 defm : VecROStorePat<ro64, v2f32, FPR64, STRDroW, STRDroX>;
1871 defm : VecROStorePat<ro64, v4i16, FPR64, STRDroW, STRDroX>;
1872 defm : VecROStorePat<ro64, v8i8, FPR64, STRDroW, STRDroX>;
1873 defm : VecROStorePat<ro64, v4f16, FPR64, STRDroW, STRDroX>;
1876 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
1877 defm : VecROStorePat<ro64, v1f64, FPR64, STRDroW, STRDroX>;
1879 // Match all store 128 bits width whose type is compatible with FPR128
1880 let Predicates = [IsLE] in {
1881 // We must use ST1 to store vectors in big-endian.
1882 defm : VecROStorePat<ro128, v2i64, FPR128, STRQroW, STRQroX>;
1883 defm : VecROStorePat<ro128, v2f64, FPR128, STRQroW, STRQroX>;
1884 defm : VecROStorePat<ro128, v4i32, FPR128, STRQroW, STRQroX>;
1885 defm : VecROStorePat<ro128, v4f32, FPR128, STRQroW, STRQroX>;
1886 defm : VecROStorePat<ro128, v8i16, FPR128, STRQroW, STRQroX>;
1887 defm : VecROStorePat<ro128, v16i8, FPR128, STRQroW, STRQroX>;
1888 defm : VecROStorePat<ro128, v8f16, FPR128, STRQroW, STRQroX>;
1890 } // AddedComplexity = 10
1893 // (unsigned immediate)
1894 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
1896 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1897 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
1899 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1900 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
1902 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))]>;
1903 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
1904 [(store (f16 FPR16:$Rt),
1905 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))]>;
1906 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
1907 [(store (f32 FPR32:$Rt),
1908 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))]>;
1909 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
1910 [(store (f64 FPR64:$Rt),
1911 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))]>;
1912 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
1914 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
1915 [(truncstorei16 GPR32:$Rt,
1916 (am_indexed16 GPR64sp:$Rn,
1917 uimm12s2:$offset))]>;
1918 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
1919 [(truncstorei8 GPR32:$Rt,
1920 (am_indexed8 GPR64sp:$Rn,
1921 uimm12s1:$offset))]>;
1923 // Match all store 64 bits width whose type is compatible with FPR64
1924 let AddedComplexity = 10 in {
1925 let Predicates = [IsLE] in {
1926 // We must use ST1 to store vectors in big-endian.
1927 def : Pat<(store (v2f32 FPR64:$Rt),
1928 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1929 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1930 def : Pat<(store (v8i8 FPR64:$Rt),
1931 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1932 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1933 def : Pat<(store (v4i16 FPR64:$Rt),
1934 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1935 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1936 def : Pat<(store (v2i32 FPR64:$Rt),
1937 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1938 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1939 def : Pat<(store (v4f16 FPR64:$Rt),
1940 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1941 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1943 def : Pat<(store (v1f64 FPR64:$Rt),
1944 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1945 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1946 def : Pat<(store (v1i64 FPR64:$Rt),
1947 (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)),
1948 (STRDui FPR64:$Rt, GPR64sp:$Rn, uimm12s8:$offset)>;
1950 // Match all store 128 bits width whose type is compatible with FPR128
1951 let Predicates = [IsLE] in {
1952 // We must use ST1 to store vectors in big-endian.
1953 def : Pat<(store (v4f32 FPR128:$Rt),
1954 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1955 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1956 def : Pat<(store (v2f64 FPR128:$Rt),
1957 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1958 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1959 def : Pat<(store (v16i8 FPR128:$Rt),
1960 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1961 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1962 def : Pat<(store (v8i16 FPR128:$Rt),
1963 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1964 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1965 def : Pat<(store (v4i32 FPR128:$Rt),
1966 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1967 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1968 def : Pat<(store (v2i64 FPR128:$Rt),
1969 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1970 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1971 def : Pat<(store (v8f16 FPR128:$Rt),
1972 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1973 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1975 def : Pat<(store (f128 FPR128:$Rt),
1976 (am_indexed128 GPR64sp:$Rn, uimm12s16:$offset)),
1977 (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
1980 def : Pat<(truncstorei32 GPR64:$Rt,
1981 (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
1982 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s4:$offset)>;
1983 def : Pat<(truncstorei16 GPR64:$Rt,
1984 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
1985 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s2:$offset)>;
1986 def : Pat<(truncstorei8 GPR64:$Rt, (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset)),
1987 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, uimm12s1:$offset)>;
1989 } // AddedComplexity = 10
1992 // (unscaled immediate)
1993 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
1995 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
1996 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
1998 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
1999 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
2001 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2002 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
2003 [(store (f16 FPR16:$Rt),
2004 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2005 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
2006 [(store (f32 FPR32:$Rt),
2007 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))]>;
2008 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
2009 [(store (f64 FPR64:$Rt),
2010 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))]>;
2011 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
2012 [(store (f128 FPR128:$Rt),
2013 (am_unscaled128 GPR64sp:$Rn, simm9:$offset))]>;
2014 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
2015 [(truncstorei16 GPR32:$Rt,
2016 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))]>;
2017 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
2018 [(truncstorei8 GPR32:$Rt,
2019 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))]>;
2021 // Match all store 64 bits width whose type is compatible with FPR64
2022 let Predicates = [IsLE] in {
2023 // We must use ST1 to store vectors in big-endian.
2024 def : Pat<(store (v2f32 FPR64:$Rt),
2025 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2026 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2027 def : Pat<(store (v8i8 FPR64:$Rt),
2028 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2029 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2030 def : Pat<(store (v4i16 FPR64:$Rt),
2031 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2032 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2033 def : Pat<(store (v2i32 FPR64:$Rt),
2034 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2035 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2036 def : Pat<(store (v4f16 FPR64:$Rt),
2037 (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2038 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2040 def : Pat<(store (v1f64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2041 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2042 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
2043 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2045 // Match all store 128 bits width whose type is compatible with FPR128
2046 let Predicates = [IsLE] in {
2047 // We must use ST1 to store vectors in big-endian.
2048 def : Pat<(store (v4f32 FPR128:$Rt),
2049 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2050 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2051 def : Pat<(store (v2f64 FPR128:$Rt),
2052 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2053 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2054 def : Pat<(store (v16i8 FPR128:$Rt),
2055 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2056 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2057 def : Pat<(store (v8i16 FPR128:$Rt),
2058 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2059 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2060 def : Pat<(store (v4i32 FPR128:$Rt),
2061 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2062 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2063 def : Pat<(store (v2i64 FPR128:$Rt),
2064 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2065 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2066 def : Pat<(store (v2f64 FPR128:$Rt),
2067 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2068 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2069 def : Pat<(store (v8f16 FPR128:$Rt),
2070 (am_unscaled128 GPR64sp:$Rn, simm9:$offset)),
2071 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9:$offset)>;
2074 // unscaled i64 truncating stores
2075 def : Pat<(truncstorei32 GPR64:$Rt, (am_unscaled32 GPR64sp:$Rn, simm9:$offset)),
2076 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2077 def : Pat<(truncstorei16 GPR64:$Rt, (am_unscaled16 GPR64sp:$Rn, simm9:$offset)),
2078 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2079 def : Pat<(truncstorei8 GPR64:$Rt, (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
2080 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$Rn, simm9:$offset)>;
2083 // STR mnemonics fall back to STUR for negative or unaligned offsets.
2084 def : InstAlias<"str $Rt, [$Rn, $offset]",
2085 (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2086 def : InstAlias<"str $Rt, [$Rn, $offset]",
2087 (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2088 def : InstAlias<"str $Rt, [$Rn, $offset]",
2089 (STURBi FPR8:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2090 def : InstAlias<"str $Rt, [$Rn, $offset]",
2091 (STURHi FPR16:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2092 def : InstAlias<"str $Rt, [$Rn, $offset]",
2093 (STURSi FPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
2094 def : InstAlias<"str $Rt, [$Rn, $offset]",
2095 (STURDi FPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
2096 def : InstAlias<"str $Rt, [$Rn, $offset]",
2097 (STURQi FPR128:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
2099 def : InstAlias<"strb $Rt, [$Rn, $offset]",
2100 (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
2101 def : InstAlias<"strh $Rt, [$Rn, $offset]",
2102 (STURHHi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb16:$offset), 0>;
2105 // (unscaled immediate, unprivileged)
2106 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2107 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2109 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2110 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2113 // (immediate pre-indexed)
2114 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2115 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2116 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2117 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2118 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2119 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2120 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2122 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2123 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2126 def : Pat<(pre_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2127 (STRWpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2129 def : Pat<(pre_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2130 (STRHHpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2132 def : Pat<(pre_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2133 (STRBBpre (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2136 def : Pat<(pre_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2137 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2138 def : Pat<(pre_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2139 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2140 def : Pat<(pre_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2141 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2142 def : Pat<(pre_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2143 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2144 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2145 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2146 def : Pat<(pre_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2147 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2148 def : Pat<(pre_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2149 (STRDpre FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2151 def : Pat<(pre_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2152 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2153 def : Pat<(pre_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2154 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2155 def : Pat<(pre_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2156 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2157 def : Pat<(pre_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2158 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2159 def : Pat<(pre_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2160 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2161 def : Pat<(pre_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2162 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2163 def : Pat<(pre_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2164 (STRQpre FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2167 // (immediate post-indexed)
2168 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2169 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2170 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2171 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2172 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2173 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2174 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2176 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2177 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2180 def : Pat<(post_truncsti32 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2181 (STRWpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2183 def : Pat<(post_truncsti16 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2184 (STRHHpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2186 def : Pat<(post_truncsti8 GPR64:$Rt, GPR64sp:$addr, simm9:$off),
2187 (STRBBpost (EXTRACT_SUBREG GPR64:$Rt, sub_32), GPR64sp:$addr,
2190 def : Pat<(post_store (v8i8 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2191 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2192 def : Pat<(post_store (v4i16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2193 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2194 def : Pat<(post_store (v2i32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2195 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2196 def : Pat<(post_store (v2f32 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2197 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2198 def : Pat<(post_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2199 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2200 def : Pat<(post_store (v1f64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2201 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2202 def : Pat<(post_store (v4f16 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
2203 (STRDpost FPR64:$Rt, GPR64sp:$addr, simm9:$off)>;
2205 def : Pat<(post_store (v16i8 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2206 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2207 def : Pat<(post_store (v8i16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2208 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2209 def : Pat<(post_store (v4i32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2210 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2211 def : Pat<(post_store (v4f32 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2212 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2213 def : Pat<(post_store (v2i64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2214 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2215 def : Pat<(post_store (v2f64 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2216 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2217 def : Pat<(post_store (v8f16 FPR128:$Rt), GPR64sp:$addr, simm9:$off),
2218 (STRQpost FPR128:$Rt, GPR64sp:$addr, simm9:$off)>;
2220 //===----------------------------------------------------------------------===//
2221 // Load/store exclusive instructions.
2222 //===----------------------------------------------------------------------===//
2224 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
2225 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2226 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2227 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2229 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2230 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2231 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2232 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2234 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
2235 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2236 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2237 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2239 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
2240 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2241 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2242 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2244 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
2245 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2246 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2247 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2249 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
2250 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2251 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2252 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2254 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
2255 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2257 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
2258 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2260 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
2261 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2263 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
2264 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2266 //===----------------------------------------------------------------------===//
2267 // Scaled floating point to integer conversion instructions.
2268 //===----------------------------------------------------------------------===//
2270 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2271 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2272 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_aarch64_neon_fcvtms>;
2273 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_aarch64_neon_fcvtmu>;
2274 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2275 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2276 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
2277 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
2278 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2279 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2280 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2281 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2282 let isCodeGenOnly = 1 in {
2283 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2284 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2285 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_aarch64_neon_fcvtzs>;
2286 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_aarch64_neon_fcvtzu>;
2289 //===----------------------------------------------------------------------===//
2290 // Scaled integer to floating point conversion instructions.
2291 //===----------------------------------------------------------------------===//
2293 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2294 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2296 //===----------------------------------------------------------------------===//
2297 // Unscaled integer to floating point conversion instruction.
2298 //===----------------------------------------------------------------------===//
2300 defm FMOV : UnscaledConversion<"fmov">;
2302 def : Pat<(f32 (fpimm0)), (FMOVWSr WZR)>, Requires<[NoZCZ]>;
2303 def : Pat<(f64 (fpimm0)), (FMOVXDr XZR)>, Requires<[NoZCZ]>;
2305 //===----------------------------------------------------------------------===//
2306 // Floating point conversion instruction.
2307 //===----------------------------------------------------------------------===//
2309 defm FCVT : FPConversion<"fcvt">;
2311 //===----------------------------------------------------------------------===//
2312 // Floating point single operand instructions.
2313 //===----------------------------------------------------------------------===//
2315 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2316 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2317 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2318 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2319 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2320 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2321 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_aarch64_neon_frintn>;
2322 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2324 def : Pat<(v1f64 (int_aarch64_neon_frintn (v1f64 FPR64:$Rn))),
2325 (FRINTNDr FPR64:$Rn)>;
2327 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
2328 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
2329 // <rdar://problem/13715968>
2330 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2331 let hasSideEffects = 1 in {
2332 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2335 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2337 let SchedRW = [WriteFDiv] in {
2338 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2341 //===----------------------------------------------------------------------===//
2342 // Floating point two operand instructions.
2343 //===----------------------------------------------------------------------===//
2345 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2346 let SchedRW = [WriteFDiv] in {
2347 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2349 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_aarch64_neon_fmaxnm>;
2350 defm FMAX : TwoOperandFPData<0b0100, "fmax", AArch64fmax>;
2351 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_aarch64_neon_fminnm>;
2352 defm FMIN : TwoOperandFPData<0b0101, "fmin", AArch64fmin>;
2353 let SchedRW = [WriteFMul] in {
2354 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2355 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2357 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2359 def : Pat<(v1f64 (AArch64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2360 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2361 def : Pat<(v1f64 (AArch64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2362 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2363 def : Pat<(v1f64 (int_aarch64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2364 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2365 def : Pat<(v1f64 (int_aarch64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2366 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2368 //===----------------------------------------------------------------------===//
2369 // Floating point three operand instructions.
2370 //===----------------------------------------------------------------------===//
2372 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2373 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2374 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2375 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2376 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2377 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2378 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2380 // The following def pats catch the case where the LHS of an FMA is negated.
2381 // The TriOpFrag above catches the case where the middle operand is negated.
2383 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2384 // the NEON variant.
2385 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2386 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2388 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2389 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2391 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2393 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2394 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2396 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2397 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2399 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2400 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2402 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2403 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2405 //===----------------------------------------------------------------------===//
2406 // Floating point comparison instructions.
2407 //===----------------------------------------------------------------------===//
2409 defm FCMPE : FPComparison<1, "fcmpe">;
2410 defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>;
2412 //===----------------------------------------------------------------------===//
2413 // Floating point conditional comparison instructions.
2414 //===----------------------------------------------------------------------===//
2416 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2417 defm FCCMP : FPCondComparison<0, "fccmp">;
2419 //===----------------------------------------------------------------------===//
2420 // Floating point conditional select instruction.
2421 //===----------------------------------------------------------------------===//
2423 defm FCSEL : FPCondSelect<"fcsel">;
2425 // CSEL instructions providing f128 types need to be handled by a
2426 // pseudo-instruction since the eventual code will need to introduce basic
2427 // blocks and control flow.
2428 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2429 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2430 [(set (f128 FPR128:$Rd),
2431 (AArch64csel FPR128:$Rn, FPR128:$Rm,
2432 (i32 imm:$cond), NZCV))]> {
2434 let usesCustomInserter = 1;
2438 //===----------------------------------------------------------------------===//
2439 // Floating point immediate move.
2440 //===----------------------------------------------------------------------===//
2442 let isReMaterializable = 1 in {
2443 defm FMOV : FPMoveImmediate<"fmov">;
2446 //===----------------------------------------------------------------------===//
2447 // Advanced SIMD two vector instructions.
2448 //===----------------------------------------------------------------------===//
2450 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_aarch64_neon_abs>;
2451 def : Pat<(xor (v8i8 (AArch64vashr V64:$src, (i32 7))),
2452 (v8i8 (add V64:$src, (AArch64vashr V64:$src, (i32 7))))),
2453 (ABSv8i8 V64:$src)>;
2454 def : Pat<(xor (v4i16 (AArch64vashr V64:$src, (i32 15))),
2455 (v4i16 (add V64:$src, (AArch64vashr V64:$src, (i32 15))))),
2456 (ABSv4i16 V64:$src)>;
2457 def : Pat<(xor (v2i32 (AArch64vashr V64:$src, (i32 31))),
2458 (v2i32 (add V64:$src, (AArch64vashr V64:$src, (i32 31))))),
2459 (ABSv2i32 V64:$src)>;
2460 def : Pat<(xor (v16i8 (AArch64vashr V128:$src, (i32 7))),
2461 (v16i8 (add V128:$src, (AArch64vashr V128:$src, (i32 7))))),
2462 (ABSv16i8 V128:$src)>;
2463 def : Pat<(xor (v8i16 (AArch64vashr V128:$src, (i32 15))),
2464 (v8i16 (add V128:$src, (AArch64vashr V128:$src, (i32 15))))),
2465 (ABSv8i16 V128:$src)>;
2466 def : Pat<(xor (v4i32 (AArch64vashr V128:$src, (i32 31))),
2467 (v4i32 (add V128:$src, (AArch64vashr V128:$src, (i32 31))))),
2468 (ABSv4i32 V128:$src)>;
2469 def : Pat<(xor (v2i64 (AArch64vashr V128:$src, (i32 63))),
2470 (v2i64 (add V128:$src, (AArch64vashr V128:$src, (i32 63))))),
2471 (ABSv2i64 V128:$src)>;
2473 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_aarch64_neon_cls>;
2474 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2475 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", AArch64cmeqz>;
2476 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", AArch64cmgez>;
2477 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", AArch64cmgtz>;
2478 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", AArch64cmlez>;
2479 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", AArch64cmltz>;
2480 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2481 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2483 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2484 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2485 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2486 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2487 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2488 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_aarch64_neon_fcvtas>;
2489 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_aarch64_neon_fcvtau>;
2490 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2491 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2492 (FCVTLv4i16 V64:$Rn)>;
2493 def : Pat<(v4f32 (int_aarch64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2495 (FCVTLv8i16 V128:$Rn)>;
2496 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2497 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2499 (FCVTLv4i32 V128:$Rn)>;
2501 def : Pat<(v4f32 (fextend (v4f16 V64:$Rn))), (FCVTLv4i16 V64:$Rn)>;
2502 def : Pat<(v4f32 (fextend (v4f16 (extract_subvector (v8f16 V128:$Rn),
2504 (FCVTLv8i16 V128:$Rn)>;
2506 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_aarch64_neon_fcvtms>;
2507 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_aarch64_neon_fcvtmu>;
2508 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_aarch64_neon_fcvtns>;
2509 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_aarch64_neon_fcvtnu>;
2510 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2511 def : Pat<(v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2512 (FCVTNv4i16 V128:$Rn)>;
2513 def : Pat<(concat_vectors V64:$Rd,
2514 (v4i16 (int_aarch64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2515 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2516 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2517 def : Pat<(v4f16 (fround (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>;
2518 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2519 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2520 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_aarch64_neon_fcvtps>;
2521 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_aarch64_neon_fcvtpu>;
2522 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2523 int_aarch64_neon_fcvtxn>;
2524 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2525 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2526 let isCodeGenOnly = 1 in {
2527 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2528 int_aarch64_neon_fcvtzs>;
2529 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2530 int_aarch64_neon_fcvtzu>;
2532 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2533 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_aarch64_neon_frecpe>;
2534 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2535 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2536 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2537 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_aarch64_neon_frintn>;
2538 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2539 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2540 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2541 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_aarch64_neon_frsqrte>;
2542 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2543 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2544 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2545 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2546 // Aliases for MVN -> NOT.
2547 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2548 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2549 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2550 (NOTv16i8 V128:$Vd, V128:$Vn)>;
2552 def : Pat<(AArch64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2553 def : Pat<(AArch64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2554 def : Pat<(AArch64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2555 def : Pat<(AArch64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2556 def : Pat<(AArch64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2557 def : Pat<(AArch64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2558 def : Pat<(AArch64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2560 def : Pat<(AArch64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2561 def : Pat<(AArch64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2562 def : Pat<(AArch64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2563 def : Pat<(AArch64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2564 def : Pat<(AArch64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2565 def : Pat<(AArch64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2566 def : Pat<(AArch64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2567 def : Pat<(AArch64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2569 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2570 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2571 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2572 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2573 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2575 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>;
2576 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
2577 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", AArch64rev32>;
2578 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", AArch64rev64>;
2579 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2580 BinOpFrag<(add node:$LHS, (int_aarch64_neon_saddlp node:$RHS))> >;
2581 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_aarch64_neon_saddlp>;
2582 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2583 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2584 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
2585 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
2586 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_aarch64_neon_sqxtn>;
2587 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_aarch64_neon_sqxtun>;
2588 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_aarch64_neon_suqadd>;
2589 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2590 BinOpFrag<(add node:$LHS, (int_aarch64_neon_uaddlp node:$RHS))> >;
2591 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2592 int_aarch64_neon_uaddlp>;
2593 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2594 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_aarch64_neon_uqxtn>;
2595 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_aarch64_neon_urecpe>;
2596 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_aarch64_neon_ursqrte>;
2597 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_aarch64_neon_usqadd>;
2598 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2600 def : Pat<(v4f16 (AArch64rev32 V64:$Rn)), (REV32v4i16 V64:$Rn)>;
2601 def : Pat<(v4f16 (AArch64rev64 V64:$Rn)), (REV64v4i16 V64:$Rn)>;
2602 def : Pat<(v8f16 (AArch64rev32 V128:$Rn)), (REV32v8i16 V128:$Rn)>;
2603 def : Pat<(v8f16 (AArch64rev64 V128:$Rn)), (REV64v8i16 V128:$Rn)>;
2604 def : Pat<(v2f32 (AArch64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2605 def : Pat<(v4f32 (AArch64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2607 // Patterns for vector long shift (by element width). These need to match all
2608 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2610 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2611 def : Pat<(AArch64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2612 (SHLLv8i8 V64:$Rn)>;
2613 def : Pat<(AArch64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2614 (SHLLv16i8 V128:$Rn)>;
2615 def : Pat<(AArch64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2616 (SHLLv4i16 V64:$Rn)>;
2617 def : Pat<(AArch64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2618 (SHLLv8i16 V128:$Rn)>;
2619 def : Pat<(AArch64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2620 (SHLLv2i32 V64:$Rn)>;
2621 def : Pat<(AArch64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2622 (SHLLv4i32 V128:$Rn)>;
2625 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2626 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2627 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2629 //===----------------------------------------------------------------------===//
2630 // Advanced SIMD three vector instructions.
2631 //===----------------------------------------------------------------------===//
2633 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2634 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_aarch64_neon_addp>;
2635 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", AArch64cmeq>;
2636 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", AArch64cmge>;
2637 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", AArch64cmgt>;
2638 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", AArch64cmhi>;
2639 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", AArch64cmhs>;
2640 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", AArch64cmtst>;
2641 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_aarch64_neon_fabd>;
2642 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_aarch64_neon_facge>;
2643 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_aarch64_neon_facgt>;
2644 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_aarch64_neon_addp>;
2645 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2646 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2647 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2648 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2649 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2650 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_aarch64_neon_fmaxnmp>;
2651 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_aarch64_neon_fmaxnm>;
2652 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_aarch64_neon_fmaxp>;
2653 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", AArch64fmax>;
2654 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_aarch64_neon_fminnmp>;
2655 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_aarch64_neon_fminnm>;
2656 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_aarch64_neon_fminp>;
2657 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", AArch64fmin>;
2659 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2660 // instruction expects the addend first, while the fma intrinsic puts it last.
2661 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2662 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2663 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2664 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2666 // The following def pats catch the case where the LHS of an FMA is negated.
2667 // The TriOpFrag above catches the case where the middle operand is negated.
2668 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2669 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2671 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2672 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2674 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2675 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2677 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_aarch64_neon_fmulx>;
2678 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2679 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_aarch64_neon_frecps>;
2680 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_aarch64_neon_frsqrts>;
2681 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2682 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2683 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2684 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2685 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2686 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2687 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_aarch64_neon_pmul>;
2688 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2689 TriOpFrag<(add node:$LHS, (int_aarch64_neon_sabd node:$MHS, node:$RHS))> >;
2690 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_aarch64_neon_sabd>;
2691 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_aarch64_neon_shadd>;
2692 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_aarch64_neon_shsub>;
2693 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_aarch64_neon_smaxp>;
2694 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_aarch64_neon_smax>;
2695 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_aarch64_neon_sminp>;
2696 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_aarch64_neon_smin>;
2697 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_aarch64_neon_sqadd>;
2698 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_aarch64_neon_sqdmulh>;
2699 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_aarch64_neon_sqrdmulh>;
2700 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_aarch64_neon_sqrshl>;
2701 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_aarch64_neon_sqshl>;
2702 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_aarch64_neon_sqsub>;
2703 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_aarch64_neon_srhadd>;
2704 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_aarch64_neon_srshl>;
2705 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_aarch64_neon_sshl>;
2706 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2707 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2708 TriOpFrag<(add node:$LHS, (int_aarch64_neon_uabd node:$MHS, node:$RHS))> >;
2709 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_aarch64_neon_uabd>;
2710 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_aarch64_neon_uhadd>;
2711 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_aarch64_neon_uhsub>;
2712 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_aarch64_neon_umaxp>;
2713 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_aarch64_neon_umax>;
2714 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_aarch64_neon_uminp>;
2715 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_aarch64_neon_umin>;
2716 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_aarch64_neon_uqadd>;
2717 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_aarch64_neon_uqrshl>;
2718 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_aarch64_neon_uqshl>;
2719 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_aarch64_neon_uqsub>;
2720 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>;
2721 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;
2722 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
2724 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2725 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2726 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2727 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2728 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>;
2729 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2730 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2731 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2732 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2733 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2734 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2736 def : Pat<(AArch64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2737 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2738 def : Pat<(AArch64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2739 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2740 def : Pat<(AArch64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2741 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2742 def : Pat<(AArch64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2743 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2745 def : Pat<(AArch64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2746 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2747 def : Pat<(AArch64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2748 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2749 def : Pat<(AArch64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2750 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2751 def : Pat<(AArch64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2752 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2754 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2755 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
2756 def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",
2757 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2758 def : InstAlias<"mov{\t$dst.4s, $src.4s|.4s\t$dst, $src}",
2759 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2760 def : InstAlias<"mov{\t$dst.2d, $src.2d|.2d\t$dst, $src}",
2761 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2763 def : InstAlias<"mov{\t$dst.8b, $src.8b|.8b\t$dst, $src}",
2764 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 1>;
2765 def : InstAlias<"mov{\t$dst.4h, $src.4h|.4h\t$dst, $src}",
2766 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2767 def : InstAlias<"mov{\t$dst.2s, $src.2s|.2s\t$dst, $src}",
2768 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2769 def : InstAlias<"mov{\t$dst.1d, $src.1d|.1d\t$dst, $src}",
2770 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2772 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2773 "|cmls.8b\t$dst, $src1, $src2}",
2774 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2775 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2776 "|cmls.16b\t$dst, $src1, $src2}",
2777 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2778 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2779 "|cmls.4h\t$dst, $src1, $src2}",
2780 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2781 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2782 "|cmls.8h\t$dst, $src1, $src2}",
2783 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2784 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2785 "|cmls.2s\t$dst, $src1, $src2}",
2786 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2787 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2788 "|cmls.4s\t$dst, $src1, $src2}",
2789 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2790 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2791 "|cmls.2d\t$dst, $src1, $src2}",
2792 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2794 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2795 "|cmlo.8b\t$dst, $src1, $src2}",
2796 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2797 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2798 "|cmlo.16b\t$dst, $src1, $src2}",
2799 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2800 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2801 "|cmlo.4h\t$dst, $src1, $src2}",
2802 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2803 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2804 "|cmlo.8h\t$dst, $src1, $src2}",
2805 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2806 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
2807 "|cmlo.2s\t$dst, $src1, $src2}",
2808 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2809 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
2810 "|cmlo.4s\t$dst, $src1, $src2}",
2811 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2812 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
2813 "|cmlo.2d\t$dst, $src1, $src2}",
2814 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2816 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
2817 "|cmle.8b\t$dst, $src1, $src2}",
2818 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2819 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
2820 "|cmle.16b\t$dst, $src1, $src2}",
2821 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2822 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
2823 "|cmle.4h\t$dst, $src1, $src2}",
2824 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2825 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
2826 "|cmle.8h\t$dst, $src1, $src2}",
2827 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2828 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
2829 "|cmle.2s\t$dst, $src1, $src2}",
2830 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2831 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
2832 "|cmle.4s\t$dst, $src1, $src2}",
2833 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2834 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
2835 "|cmle.2d\t$dst, $src1, $src2}",
2836 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2838 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
2839 "|cmlt.8b\t$dst, $src1, $src2}",
2840 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2841 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
2842 "|cmlt.16b\t$dst, $src1, $src2}",
2843 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2844 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
2845 "|cmlt.4h\t$dst, $src1, $src2}",
2846 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2847 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
2848 "|cmlt.8h\t$dst, $src1, $src2}",
2849 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2850 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
2851 "|cmlt.2s\t$dst, $src1, $src2}",
2852 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2853 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
2854 "|cmlt.4s\t$dst, $src1, $src2}",
2855 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2856 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
2857 "|cmlt.2d\t$dst, $src1, $src2}",
2858 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2860 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
2861 "|fcmle.2s\t$dst, $src1, $src2}",
2862 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2863 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
2864 "|fcmle.4s\t$dst, $src1, $src2}",
2865 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2866 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
2867 "|fcmle.2d\t$dst, $src1, $src2}",
2868 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2870 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
2871 "|fcmlt.2s\t$dst, $src1, $src2}",
2872 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2873 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
2874 "|fcmlt.4s\t$dst, $src1, $src2}",
2875 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2876 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
2877 "|fcmlt.2d\t$dst, $src1, $src2}",
2878 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2880 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
2881 "|facle.2s\t$dst, $src1, $src2}",
2882 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2883 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
2884 "|facle.4s\t$dst, $src1, $src2}",
2885 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2886 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
2887 "|facle.2d\t$dst, $src1, $src2}",
2888 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2890 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
2891 "|faclt.2s\t$dst, $src1, $src2}",
2892 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2893 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
2894 "|faclt.4s\t$dst, $src1, $src2}",
2895 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2896 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
2897 "|faclt.2d\t$dst, $src1, $src2}",
2898 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2900 //===----------------------------------------------------------------------===//
2901 // Advanced SIMD three scalar instructions.
2902 //===----------------------------------------------------------------------===//
2904 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
2905 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", AArch64cmeq>;
2906 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", AArch64cmge>;
2907 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", AArch64cmgt>;
2908 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", AArch64cmhi>;
2909 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", AArch64cmhs>;
2910 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", AArch64cmtst>;
2911 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_aarch64_sisd_fabd>;
2912 def : Pat<(v1f64 (int_aarch64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2913 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
2914 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
2915 int_aarch64_neon_facge>;
2916 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
2917 int_aarch64_neon_facgt>;
2918 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", AArch64fcmeq>;
2919 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", AArch64fcmge>;
2920 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", AArch64fcmgt>;
2921 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_aarch64_neon_fmulx>;
2922 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_aarch64_neon_frecps>;
2923 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_aarch64_neon_frsqrts>;
2924 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_aarch64_neon_sqadd>;
2925 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_aarch64_neon_sqdmulh>;
2926 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
2927 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_aarch64_neon_sqrshl>;
2928 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_aarch64_neon_sqshl>;
2929 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_aarch64_neon_sqsub>;
2930 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_aarch64_neon_srshl>;
2931 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_aarch64_neon_sshl>;
2932 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
2933 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_aarch64_neon_uqadd>;
2934 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_aarch64_neon_uqrshl>;
2935 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_aarch64_neon_uqshl>;
2936 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_aarch64_neon_uqsub>;
2937 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_aarch64_neon_urshl>;
2938 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_aarch64_neon_ushl>;
2940 def : InstAlias<"cmls $dst, $src1, $src2",
2941 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2942 def : InstAlias<"cmle $dst, $src1, $src2",
2943 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2944 def : InstAlias<"cmlo $dst, $src1, $src2",
2945 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2946 def : InstAlias<"cmlt $dst, $src1, $src2",
2947 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2948 def : InstAlias<"fcmle $dst, $src1, $src2",
2949 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2950 def : InstAlias<"fcmle $dst, $src1, $src2",
2951 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2952 def : InstAlias<"fcmlt $dst, $src1, $src2",
2953 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2954 def : InstAlias<"fcmlt $dst, $src1, $src2",
2955 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2956 def : InstAlias<"facle $dst, $src1, $src2",
2957 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2958 def : InstAlias<"facle $dst, $src1, $src2",
2959 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2960 def : InstAlias<"faclt $dst, $src1, $src2",
2961 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
2962 def : InstAlias<"faclt $dst, $src1, $src2",
2963 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
2965 //===----------------------------------------------------------------------===//
2966 // Advanced SIMD three scalar instructions (mixed operands).
2967 //===----------------------------------------------------------------------===//
2968 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
2969 int_aarch64_neon_sqdmulls_scalar>;
2970 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
2971 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
2973 def : Pat<(i64 (int_aarch64_neon_sqadd (i64 FPR64:$Rd),
2974 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2975 (i32 FPR32:$Rm))))),
2976 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2977 def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),
2978 (i64 (int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2979 (i32 FPR32:$Rm))))),
2980 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2982 //===----------------------------------------------------------------------===//
2983 // Advanced SIMD two scalar instructions.
2984 //===----------------------------------------------------------------------===//
2986 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_aarch64_neon_abs>;
2987 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;
2988 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;
2989 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;
2990 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", AArch64cmlez>;
2991 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", AArch64cmltz>;
2992 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", AArch64fcmeqz>;
2993 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", AArch64fcmgez>;
2994 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", AArch64fcmgtz>;
2995 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", AArch64fcmlez>;
2996 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", AArch64fcmltz>;
2997 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
2998 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
2999 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
3000 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
3001 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
3002 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
3003 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
3004 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
3005 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
3006 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
3007 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
3008 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
3009 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
3010 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
3011 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
3012 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
3013 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", AArch64sitof>;
3014 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_aarch64_neon_sqabs>;
3015 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_aarch64_neon_sqneg>;
3016 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_aarch64_neon_scalar_sqxtn>;
3017 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_aarch64_neon_scalar_sqxtun>;
3018 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
3019 int_aarch64_neon_suqadd>;
3020 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", AArch64uitof>;
3021 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_aarch64_neon_scalar_uqxtn>;
3022 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
3023 int_aarch64_neon_usqadd>;
3025 def : Pat<(AArch64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
3027 def : Pat<(v1i64 (int_aarch64_neon_fcvtas (v1f64 FPR64:$Rn))),
3028 (FCVTASv1i64 FPR64:$Rn)>;
3029 def : Pat<(v1i64 (int_aarch64_neon_fcvtau (v1f64 FPR64:$Rn))),
3030 (FCVTAUv1i64 FPR64:$Rn)>;
3031 def : Pat<(v1i64 (int_aarch64_neon_fcvtms (v1f64 FPR64:$Rn))),
3032 (FCVTMSv1i64 FPR64:$Rn)>;
3033 def : Pat<(v1i64 (int_aarch64_neon_fcvtmu (v1f64 FPR64:$Rn))),
3034 (FCVTMUv1i64 FPR64:$Rn)>;
3035 def : Pat<(v1i64 (int_aarch64_neon_fcvtns (v1f64 FPR64:$Rn))),
3036 (FCVTNSv1i64 FPR64:$Rn)>;
3037 def : Pat<(v1i64 (int_aarch64_neon_fcvtnu (v1f64 FPR64:$Rn))),
3038 (FCVTNUv1i64 FPR64:$Rn)>;
3039 def : Pat<(v1i64 (int_aarch64_neon_fcvtps (v1f64 FPR64:$Rn))),
3040 (FCVTPSv1i64 FPR64:$Rn)>;
3041 def : Pat<(v1i64 (int_aarch64_neon_fcvtpu (v1f64 FPR64:$Rn))),
3042 (FCVTPUv1i64 FPR64:$Rn)>;
3044 def : Pat<(f32 (int_aarch64_neon_frecpe (f32 FPR32:$Rn))),
3045 (FRECPEv1i32 FPR32:$Rn)>;
3046 def : Pat<(f64 (int_aarch64_neon_frecpe (f64 FPR64:$Rn))),
3047 (FRECPEv1i64 FPR64:$Rn)>;
3048 def : Pat<(v1f64 (int_aarch64_neon_frecpe (v1f64 FPR64:$Rn))),
3049 (FRECPEv1i64 FPR64:$Rn)>;
3051 def : Pat<(f32 (int_aarch64_neon_frecpx (f32 FPR32:$Rn))),
3052 (FRECPXv1i32 FPR32:$Rn)>;
3053 def : Pat<(f64 (int_aarch64_neon_frecpx (f64 FPR64:$Rn))),
3054 (FRECPXv1i64 FPR64:$Rn)>;
3056 def : Pat<(f32 (int_aarch64_neon_frsqrte (f32 FPR32:$Rn))),
3057 (FRSQRTEv1i32 FPR32:$Rn)>;
3058 def : Pat<(f64 (int_aarch64_neon_frsqrte (f64 FPR64:$Rn))),
3059 (FRSQRTEv1i64 FPR64:$Rn)>;
3060 def : Pat<(v1f64 (int_aarch64_neon_frsqrte (v1f64 FPR64:$Rn))),
3061 (FRSQRTEv1i64 FPR64:$Rn)>;
3063 // If an integer is about to be converted to a floating point value,
3064 // just load it on the floating point unit.
3065 // Here are the patterns for 8 and 16-bits to float.
3067 multiclass UIntToFPROLoadPat<ValueType DstTy, ValueType SrcTy,
3068 SDPatternOperator loadop, Instruction UCVTF,
3069 ROAddrMode ro, Instruction LDRW, Instruction LDRX,
3071 def : Pat<(DstTy (uint_to_fp (SrcTy
3072 (loadop (ro.Wpat GPR64sp:$Rn, GPR32:$Rm,
3073 ro.Wext:$extend))))),
3074 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3075 (LDRW GPR64sp:$Rn, GPR32:$Rm, ro.Wext:$extend),
3078 def : Pat<(DstTy (uint_to_fp (SrcTy
3079 (loadop (ro.Xpat GPR64sp:$Rn, GPR64:$Rm,
3080 ro.Wext:$extend))))),
3081 (UCVTF (INSERT_SUBREG (DstTy (IMPLICIT_DEF)),
3082 (LDRX GPR64sp:$Rn, GPR64:$Rm, ro.Xext:$extend),
3086 defm : UIntToFPROLoadPat<f32, i32, zextloadi8,
3087 UCVTFv1i32, ro8, LDRBroW, LDRBroX, bsub>;
3088 def : Pat <(f32 (uint_to_fp (i32
3089 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3090 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3091 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3092 def : Pat <(f32 (uint_to_fp (i32
3093 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3094 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3095 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3096 // 16-bits -> float.
3097 defm : UIntToFPROLoadPat<f32, i32, zextloadi16,
3098 UCVTFv1i32, ro16, LDRHroW, LDRHroX, hsub>;
3099 def : Pat <(f32 (uint_to_fp (i32
3100 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3101 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3102 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3103 def : Pat <(f32 (uint_to_fp (i32
3104 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3105 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
3106 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3107 // 32-bits are handled in target specific dag combine:
3108 // performIntToFpCombine.
3109 // 64-bits integer to 32-bits floating point, not possible with
3110 // UCVTF on floating point registers (both source and destination
3111 // must have the same size).
3113 // Here are the patterns for 8, 16, 32, and 64-bits to double.
3114 // 8-bits -> double.
3115 defm : UIntToFPROLoadPat<f64, i32, zextloadi8,
3116 UCVTFv1i64, ro8, LDRBroW, LDRBroX, bsub>;
3117 def : Pat <(f64 (uint_to_fp (i32
3118 (zextloadi8 (am_indexed8 GPR64sp:$Rn, uimm12s1:$offset))))),
3119 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3120 (LDRBui GPR64sp:$Rn, uimm12s1:$offset), bsub))>;
3121 def : Pat <(f64 (uint_to_fp (i32
3122 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))))),
3123 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3124 (LDURBi GPR64sp:$Rn, simm9:$offset), bsub))>;
3125 // 16-bits -> double.
3126 defm : UIntToFPROLoadPat<f64, i32, zextloadi16,
3127 UCVTFv1i64, ro16, LDRHroW, LDRHroX, hsub>;
3128 def : Pat <(f64 (uint_to_fp (i32
3129 (zextloadi16 (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset))))),
3130 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3131 (LDRHui GPR64sp:$Rn, uimm12s2:$offset), hsub))>;
3132 def : Pat <(f64 (uint_to_fp (i32
3133 (zextloadi16 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))))),
3134 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3135 (LDURHi GPR64sp:$Rn, simm9:$offset), hsub))>;
3136 // 32-bits -> double.
3137 defm : UIntToFPROLoadPat<f64, i32, load,
3138 UCVTFv1i64, ro32, LDRSroW, LDRSroX, ssub>;
3139 def : Pat <(f64 (uint_to_fp (i32
3140 (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset))))),
3141 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3142 (LDRSui GPR64sp:$Rn, uimm12s4:$offset), ssub))>;
3143 def : Pat <(f64 (uint_to_fp (i32
3144 (load (am_unscaled32 GPR64sp:$Rn, simm9:$offset))))),
3145 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3146 (LDURSi GPR64sp:$Rn, simm9:$offset), ssub))>;
3147 // 64-bits -> double are handled in target specific dag combine:
3148 // performIntToFpCombine.
3150 //===----------------------------------------------------------------------===//
3151 // Advanced SIMD three different-sized vector instructions.
3152 //===----------------------------------------------------------------------===//
3154 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_aarch64_neon_addhn>;
3155 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_aarch64_neon_subhn>;
3156 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_aarch64_neon_raddhn>;
3157 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_aarch64_neon_rsubhn>;
3158 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_aarch64_neon_pmull>;
3159 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
3160 int_aarch64_neon_sabd>;
3161 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
3162 int_aarch64_neon_sabd>;
3163 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
3164 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
3165 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
3166 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
3167 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
3168 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3169 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
3170 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
3171 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_aarch64_neon_smull>;
3172 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
3173 int_aarch64_neon_sqadd>;
3174 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
3175 int_aarch64_neon_sqsub>;
3176 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
3177 int_aarch64_neon_sqdmull>;
3178 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
3179 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
3180 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
3181 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
3182 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
3183 int_aarch64_neon_uabd>;
3184 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
3185 int_aarch64_neon_uabd>;
3186 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
3187 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
3188 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
3189 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
3190 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
3191 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3192 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
3193 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
3194 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_aarch64_neon_umull>;
3195 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
3196 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
3197 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
3198 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
3200 // Additional patterns for SMULL and UMULL
3201 multiclass Neon_mul_widen_patterns<SDPatternOperator opnode,
3202 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3203 def : Pat<(v8i16 (opnode (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3204 (INST8B V64:$Rn, V64:$Rm)>;
3205 def : Pat<(v4i32 (opnode (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3206 (INST4H V64:$Rn, V64:$Rm)>;
3207 def : Pat<(v2i64 (opnode (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3208 (INST2S V64:$Rn, V64:$Rm)>;
3211 defm : Neon_mul_widen_patterns<AArch64smull, SMULLv8i8_v8i16,
3212 SMULLv4i16_v4i32, SMULLv2i32_v2i64>;
3213 defm : Neon_mul_widen_patterns<AArch64umull, UMULLv8i8_v8i16,
3214 UMULLv4i16_v4i32, UMULLv2i32_v2i64>;
3216 // Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL
3217 multiclass Neon_mulacc_widen_patterns<SDPatternOperator opnode,
3218 Instruction INST8B, Instruction INST4H, Instruction INST2S> {
3219 def : Pat<(v8i16 (opnode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm))),
3220 (INST8B V128:$Rd, V64:$Rn, V64:$Rm)>;
3221 def : Pat<(v4i32 (opnode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm))),
3222 (INST4H V128:$Rd, V64:$Rn, V64:$Rm)>;
3223 def : Pat<(v2i64 (opnode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm))),
3224 (INST2S V128:$Rd, V64:$Rn, V64:$Rm)>;
3227 defm : Neon_mulacc_widen_patterns<
3228 TriOpFrag<(add node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3229 SMLALv8i8_v8i16, SMLALv4i16_v4i32, SMLALv2i32_v2i64>;
3230 defm : Neon_mulacc_widen_patterns<
3231 TriOpFrag<(add node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3232 UMLALv8i8_v8i16, UMLALv4i16_v4i32, UMLALv2i32_v2i64>;
3233 defm : Neon_mulacc_widen_patterns<
3234 TriOpFrag<(sub node:$LHS, (AArch64smull node:$MHS, node:$RHS))>,
3235 SMLSLv8i8_v8i16, SMLSLv4i16_v4i32, SMLSLv2i32_v2i64>;
3236 defm : Neon_mulacc_widen_patterns<
3237 TriOpFrag<(sub node:$LHS, (AArch64umull node:$MHS, node:$RHS))>,
3238 UMLSLv8i8_v8i16, UMLSLv4i16_v4i32, UMLSLv2i32_v2i64>;
3240 // Patterns for 64-bit pmull
3241 def : Pat<(int_aarch64_neon_pmull64 V64:$Rn, V64:$Rm),
3242 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
3243 def : Pat<(int_aarch64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
3244 (vector_extract (v2i64 V128:$Rm), (i64 1))),
3245 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
3247 // CodeGen patterns for addhn and subhn instructions, which can actually be
3248 // written in LLVM IR without too much difficulty.
3251 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
3252 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3253 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3255 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3256 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3258 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3259 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3260 (trunc (v8i16 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3262 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3263 V128:$Rn, V128:$Rm)>;
3264 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3265 (trunc (v4i32 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3267 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3268 V128:$Rn, V128:$Rm)>;
3269 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3270 (trunc (v2i64 (AArch64vlshr (add V128:$Rn, V128:$Rm),
3272 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3273 V128:$Rn, V128:$Rm)>;
3276 def : Pat<(v8i8 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
3277 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
3278 def : Pat<(v4i16 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3280 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
3281 def : Pat<(v2i32 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3283 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
3284 def : Pat<(concat_vectors (v8i8 V64:$Rd),
3285 (trunc (v8i16 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3287 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3288 V128:$Rn, V128:$Rm)>;
3289 def : Pat<(concat_vectors (v4i16 V64:$Rd),
3290 (trunc (v4i32 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3292 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3293 V128:$Rn, V128:$Rm)>;
3294 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3295 (trunc (v2i64 (AArch64vlshr (sub V128:$Rn, V128:$Rm),
3297 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3298 V128:$Rn, V128:$Rm)>;
3300 //----------------------------------------------------------------------------
3301 // AdvSIMD bitwise extract from vector instruction.
3302 //----------------------------------------------------------------------------
3304 defm EXT : SIMDBitwiseExtract<"ext">;
3306 def : Pat<(v4i16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3307 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3308 def : Pat<(v8i16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3309 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3310 def : Pat<(v2i32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3311 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3312 def : Pat<(v2f32 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3313 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3314 def : Pat<(v4i32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3315 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3316 def : Pat<(v4f32 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3317 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3318 def : Pat<(v2i64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3319 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3320 def : Pat<(v2f64 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3321 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3322 def : Pat<(v4f16 (AArch64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3323 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3324 def : Pat<(v8f16 (AArch64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3325 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3327 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
3329 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
3330 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3331 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
3332 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3333 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
3334 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3335 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
3336 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3337 def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 4))),
3338 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3339 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
3340 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3341 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
3342 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3345 //----------------------------------------------------------------------------
3346 // AdvSIMD zip vector
3347 //----------------------------------------------------------------------------
3349 defm TRN1 : SIMDZipVector<0b010, "trn1", AArch64trn1>;
3350 defm TRN2 : SIMDZipVector<0b110, "trn2", AArch64trn2>;
3351 defm UZP1 : SIMDZipVector<0b001, "uzp1", AArch64uzp1>;
3352 defm UZP2 : SIMDZipVector<0b101, "uzp2", AArch64uzp2>;
3353 defm ZIP1 : SIMDZipVector<0b011, "zip1", AArch64zip1>;
3354 defm ZIP2 : SIMDZipVector<0b111, "zip2", AArch64zip2>;
3356 //----------------------------------------------------------------------------
3357 // AdvSIMD TBL/TBX instructions
3358 //----------------------------------------------------------------------------
3360 defm TBL : SIMDTableLookup< 0, "tbl">;
3361 defm TBX : SIMDTableLookupTied<1, "tbx">;
3363 def : Pat<(v8i8 (int_aarch64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3364 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
3365 def : Pat<(v16i8 (int_aarch64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3366 (TBLv16i8One V128:$Ri, V128:$Rn)>;
3368 def : Pat<(v8i8 (int_aarch64_neon_tbx1 (v8i8 V64:$Rd),
3369 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3370 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
3371 def : Pat<(v16i8 (int_aarch64_neon_tbx1 (v16i8 V128:$Rd),
3372 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3373 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
3376 //----------------------------------------------------------------------------
3377 // AdvSIMD scalar CPY instruction
3378 //----------------------------------------------------------------------------
3380 defm CPY : SIMDScalarCPY<"cpy">;
3382 //----------------------------------------------------------------------------
3383 // AdvSIMD scalar pairwise instructions
3384 //----------------------------------------------------------------------------
3386 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
3387 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
3388 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
3389 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
3390 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
3391 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
3392 def : Pat<(i64 (int_aarch64_neon_saddv (v2i64 V128:$Rn))),
3393 (ADDPv2i64p V128:$Rn)>;
3394 def : Pat<(i64 (int_aarch64_neon_uaddv (v2i64 V128:$Rn))),
3395 (ADDPv2i64p V128:$Rn)>;
3396 def : Pat<(f32 (int_aarch64_neon_faddv (v2f32 V64:$Rn))),
3397 (FADDPv2i32p V64:$Rn)>;
3398 def : Pat<(f32 (int_aarch64_neon_faddv (v4f32 V128:$Rn))),
3399 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
3400 def : Pat<(f64 (int_aarch64_neon_faddv (v2f64 V128:$Rn))),
3401 (FADDPv2i64p V128:$Rn)>;
3402 def : Pat<(f32 (int_aarch64_neon_fmaxnmv (v2f32 V64:$Rn))),
3403 (FMAXNMPv2i32p V64:$Rn)>;
3404 def : Pat<(f64 (int_aarch64_neon_fmaxnmv (v2f64 V128:$Rn))),
3405 (FMAXNMPv2i64p V128:$Rn)>;
3406 def : Pat<(f32 (int_aarch64_neon_fmaxv (v2f32 V64:$Rn))),
3407 (FMAXPv2i32p V64:$Rn)>;
3408 def : Pat<(f64 (int_aarch64_neon_fmaxv (v2f64 V128:$Rn))),
3409 (FMAXPv2i64p V128:$Rn)>;
3410 def : Pat<(f32 (int_aarch64_neon_fminnmv (v2f32 V64:$Rn))),
3411 (FMINNMPv2i32p V64:$Rn)>;
3412 def : Pat<(f64 (int_aarch64_neon_fminnmv (v2f64 V128:$Rn))),
3413 (FMINNMPv2i64p V128:$Rn)>;
3414 def : Pat<(f32 (int_aarch64_neon_fminv (v2f32 V64:$Rn))),
3415 (FMINPv2i32p V64:$Rn)>;
3416 def : Pat<(f64 (int_aarch64_neon_fminv (v2f64 V128:$Rn))),
3417 (FMINPv2i64p V128:$Rn)>;
3419 //----------------------------------------------------------------------------
3420 // AdvSIMD INS/DUP instructions
3421 //----------------------------------------------------------------------------
3423 def DUPv8i8gpr : SIMDDupFromMain<0, 0b00001, ".8b", v8i8, V64, GPR32>;
3424 def DUPv16i8gpr : SIMDDupFromMain<1, 0b00001, ".16b", v16i8, V128, GPR32>;
3425 def DUPv4i16gpr : SIMDDupFromMain<0, 0b00010, ".4h", v4i16, V64, GPR32>;
3426 def DUPv8i16gpr : SIMDDupFromMain<1, 0b00010, ".8h", v8i16, V128, GPR32>;
3427 def DUPv2i32gpr : SIMDDupFromMain<0, 0b00100, ".2s", v2i32, V64, GPR32>;
3428 def DUPv4i32gpr : SIMDDupFromMain<1, 0b00100, ".4s", v4i32, V128, GPR32>;
3429 def DUPv2i64gpr : SIMDDupFromMain<1, 0b01000, ".2d", v2i64, V128, GPR64>;
3431 def DUPv2i64lane : SIMDDup64FromElement;
3432 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3433 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3434 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3435 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3436 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3437 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3439 def : Pat<(v2f32 (AArch64dup (f32 FPR32:$Rn))),
3440 (v2f32 (DUPv2i32lane
3441 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3443 def : Pat<(v4f32 (AArch64dup (f32 FPR32:$Rn))),
3444 (v4f32 (DUPv4i32lane
3445 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3447 def : Pat<(v2f64 (AArch64dup (f64 FPR64:$Rn))),
3448 (v2f64 (DUPv2i64lane
3449 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3451 def : Pat<(v4f16 (AArch64dup (f16 FPR16:$Rn))),
3452 (v4f16 (DUPv4i16lane
3453 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3455 def : Pat<(v8f16 (AArch64dup (f16 FPR16:$Rn))),
3456 (v8f16 (DUPv8i16lane
3457 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR16:$Rn, hsub),
3460 def : Pat<(v4f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3461 (DUPv4i16lane V128:$Rn, VectorIndexH:$imm)>;
3462 def : Pat<(v8f16 (AArch64duplane16 (v8f16 V128:$Rn), VectorIndexH:$imm)),
3463 (DUPv8i16lane V128:$Rn, VectorIndexH:$imm)>;
3465 def : Pat<(v2f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3466 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3467 def : Pat<(v4f32 (AArch64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3468 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3469 def : Pat<(v2f64 (AArch64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3470 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3472 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane
3473 // instruction even if the types don't match: we just have to remap the lane
3474 // carefully. N.b. this trick only applies to truncations.
3475 def VecIndex_x2 : SDNodeXForm<imm, [{
3476 return CurDAG->getTargetConstant(2 * N->getZExtValue(), MVT::i64);
3478 def VecIndex_x4 : SDNodeXForm<imm, [{
3479 return CurDAG->getTargetConstant(4 * N->getZExtValue(), MVT::i64);
3481 def VecIndex_x8 : SDNodeXForm<imm, [{
3482 return CurDAG->getTargetConstant(8 * N->getZExtValue(), MVT::i64);
3485 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3486 ValueType Src128VT, ValueType ScalVT,
3487 Instruction DUP, SDNodeXForm IdxXFORM> {
3488 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3490 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3492 def : Pat<(ResVT (AArch64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3494 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3497 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3498 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3499 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3501 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3502 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3503 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3505 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3506 SDNodeXForm IdxXFORM> {
3507 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3509 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3511 def : Pat<(ResVT (AArch64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3513 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3516 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3517 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3518 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3520 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3521 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3522 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3524 // SMOV and UMOV definitions, with some extra patterns for convenience
3528 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3529 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3530 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3531 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3532 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3533 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3534 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3535 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3536 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3537 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3538 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3539 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3541 // Extracting i8 or i16 elements will have the zero-extend transformed to
3542 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3543 // for AArch64. Match these patterns here since UMOV already zeroes out the high
3544 // bits of the destination register.
3545 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3547 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3548 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3550 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3554 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3555 (SUBREG_TO_REG (i32 0),
3556 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3557 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3558 (SUBREG_TO_REG (i32 0),
3559 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3561 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3562 (SUBREG_TO_REG (i32 0),
3563 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3564 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3565 (SUBREG_TO_REG (i32 0),
3566 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3568 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3569 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3570 (i32 FPR32:$Rn), ssub))>;
3571 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3572 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3573 (i32 FPR32:$Rn), ssub))>;
3574 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3575 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3576 (i64 FPR64:$Rn), dsub))>;
3578 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3579 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3580 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3581 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3582 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3583 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3585 def : Pat<(v4f16 (vector_insert (v4f16 V64:$Rn),
3586 (f16 FPR16:$Rm), (i64 VectorIndexS:$imm))),
3589 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3591 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3595 def : Pat<(v8f16 (vector_insert (v8f16 V128:$Rn),
3596 (f16 FPR16:$Rm), (i64 VectorIndexH:$imm))),
3598 V128:$Rn, VectorIndexH:$imm,
3599 (v8f16 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR16:$Rm, hsub)),
3602 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3603 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3606 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3608 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3611 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3612 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3614 V128:$Rn, VectorIndexS:$imm,
3615 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3617 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3618 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3620 V128:$Rn, VectorIndexD:$imm,
3621 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3624 // Copy an element at a constant index in one vector into a constant indexed
3625 // element of another.
3626 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3627 // index type and INS extension
3628 def : Pat<(v16i8 (int_aarch64_neon_vcopy_lane
3629 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3630 VectorIndexB:$idx2)),
3632 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3634 def : Pat<(v8i16 (int_aarch64_neon_vcopy_lane
3635 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3636 VectorIndexH:$idx2)),
3638 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3640 def : Pat<(v4i32 (int_aarch64_neon_vcopy_lane
3641 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3642 VectorIndexS:$idx2)),
3644 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3646 def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
3647 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3648 VectorIndexD:$idx2)),
3650 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3653 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3654 ValueType VTScal, Instruction INS> {
3655 def : Pat<(VT128 (vector_insert V128:$src,
3656 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3658 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3660 def : Pat<(VT128 (vector_insert V128:$src,
3661 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3663 (INS V128:$src, imm:$Immd,
3664 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3666 def : Pat<(VT64 (vector_insert V64:$src,
3667 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3669 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3670 imm:$Immd, V128:$Rn, imm:$Immn),
3673 def : Pat<(VT64 (vector_insert V64:$src,
3674 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3677 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3678 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3682 defm : Neon_INS_elt_pattern<v8f16, v4f16, f16, INSvi16lane>;
3683 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3684 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3685 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, INSvi8lane>;
3686 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, INSvi16lane>;
3687 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, INSvi32lane>;
3688 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, INSvi32lane>;
3691 // Floating point vector extractions are codegen'd as either a sequence of
3692 // subregister extractions, possibly fed by an INS if the lane number is
3693 // anything other than zero.
3694 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3695 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3696 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3697 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3698 def : Pat<(vector_extract (v8f16 V128:$Rn), 0),
3699 (f16 (EXTRACT_SUBREG V128:$Rn, hsub))>;
3700 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3701 (f64 (EXTRACT_SUBREG
3702 (INSvi64lane (v2f64 (IMPLICIT_DEF)), 0,
3703 V128:$Rn, VectorIndexD:$idx),
3705 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3706 (f32 (EXTRACT_SUBREG
3707 (INSvi32lane (v4f32 (IMPLICIT_DEF)), 0,
3708 V128:$Rn, VectorIndexS:$idx),
3710 def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx),
3711 (f16 (EXTRACT_SUBREG
3712 (INSvi16lane (v8f16 (IMPLICIT_DEF)), 0,
3713 V128:$Rn, VectorIndexH:$idx),
3716 // All concat_vectors operations are canonicalised to act on i64 vectors for
3717 // AArch64. In the general case we need an instruction, which had just as well be
3719 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3720 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3721 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3722 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3724 def : ConcatPat<v2i64, v1i64>;
3725 def : ConcatPat<v2f64, v1f64>;
3726 def : ConcatPat<v4i32, v2i32>;
3727 def : ConcatPat<v4f32, v2f32>;
3728 def : ConcatPat<v8i16, v4i16>;
3729 def : ConcatPat<v8f16, v4f16>;
3730 def : ConcatPat<v16i8, v8i8>;
3732 // If the high lanes are undef, though, we can just ignore them:
3733 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3734 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3735 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3737 def : ConcatUndefPat<v2i64, v1i64>;
3738 def : ConcatUndefPat<v2f64, v1f64>;
3739 def : ConcatUndefPat<v4i32, v2i32>;
3740 def : ConcatUndefPat<v4f32, v2f32>;
3741 def : ConcatUndefPat<v8i16, v4i16>;
3742 def : ConcatUndefPat<v16i8, v8i8>;
3744 //----------------------------------------------------------------------------
3745 // AdvSIMD across lanes instructions
3746 //----------------------------------------------------------------------------
3748 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3749 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3750 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3751 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3752 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3753 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3754 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3755 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_aarch64_neon_fmaxnmv>;
3756 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_aarch64_neon_fmaxv>;
3757 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_aarch64_neon_fminnmv>;
3758 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_aarch64_neon_fminv>;
3760 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, Intrinsic intOp> {
3761 // If there is a sign extension after this intrinsic, consume it as smov already
3763 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i8 V64:$Rn))), i8)),
3765 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3766 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3768 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3770 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3771 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3773 // If there is a sign extension after this intrinsic, consume it as smov already
3775 def : Pat<(i32 (sext_inreg (i32 (intOp (v16i8 V128:$Rn))), i8)),
3777 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3778 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3780 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3782 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3783 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3785 // If there is a sign extension after this intrinsic, consume it as smov already
3787 def : Pat<(i32 (sext_inreg (i32 (intOp (v4i16 V64:$Rn))), i16)),
3789 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3790 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3792 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3794 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3795 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3797 // If there is a sign extension after this intrinsic, consume it as smov already
3799 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i16 V128:$Rn))), i16)),
3801 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3802 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3804 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3806 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3807 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3810 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3811 (i32 (EXTRACT_SUBREG
3812 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3813 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3817 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc, Intrinsic intOp> {
3818 // If there is a masking operation keeping only what has been actually
3819 // generated, consume it.
3820 def : Pat<(i32 (and (i32 (intOp (v8i8 V64:$Rn))), maski8_or_more)),
3821 (i32 (EXTRACT_SUBREG
3822 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3823 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3825 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3826 (i32 (EXTRACT_SUBREG
3827 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3828 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3830 // If there is a masking operation keeping only what has been actually
3831 // generated, consume it.
3832 def : Pat<(i32 (and (i32 (intOp (v16i8 V128:$Rn))), maski8_or_more)),
3833 (i32 (EXTRACT_SUBREG
3834 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3835 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3837 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3838 (i32 (EXTRACT_SUBREG
3839 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3840 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3843 // If there is a masking operation keeping only what has been actually
3844 // generated, consume it.
3845 def : Pat<(i32 (and (i32 (intOp (v4i16 V64:$Rn))), maski16_or_more)),
3846 (i32 (EXTRACT_SUBREG
3847 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3848 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3850 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3851 (i32 (EXTRACT_SUBREG
3852 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3853 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3855 // If there is a masking operation keeping only what has been actually
3856 // generated, consume it.
3857 def : Pat<(i32 (and (i32 (intOp (v8i16 V128:$Rn))), maski16_or_more)),
3858 (i32 (EXTRACT_SUBREG
3859 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3860 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3862 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3863 (i32 (EXTRACT_SUBREG
3864 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3865 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3868 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3869 (i32 (EXTRACT_SUBREG
3870 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3871 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3876 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
3877 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3879 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3880 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3882 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3884 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3885 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3888 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3889 (i32 (EXTRACT_SUBREG
3890 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3891 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3893 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3894 (i32 (EXTRACT_SUBREG
3895 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3896 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3899 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3900 (i64 (EXTRACT_SUBREG
3901 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3902 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3906 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
3908 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3909 (i32 (EXTRACT_SUBREG
3910 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3911 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3913 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3914 (i32 (EXTRACT_SUBREG
3915 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3916 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3919 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3920 (i32 (EXTRACT_SUBREG
3921 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3922 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3924 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3925 (i32 (EXTRACT_SUBREG
3926 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3927 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3930 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3931 (i64 (EXTRACT_SUBREG
3932 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3933 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3937 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", int_aarch64_neon_saddv>;
3938 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3939 def : Pat<(i32 (int_aarch64_neon_saddv (v2i32 V64:$Rn))),
3940 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3942 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", int_aarch64_neon_uaddv>;
3943 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3944 def : Pat<(i32 (int_aarch64_neon_uaddv (v2i32 V64:$Rn))),
3945 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3947 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", int_aarch64_neon_smaxv>;
3948 def : Pat<(i32 (int_aarch64_neon_smaxv (v2i32 V64:$Rn))),
3949 (EXTRACT_SUBREG (SMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3951 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", int_aarch64_neon_sminv>;
3952 def : Pat<(i32 (int_aarch64_neon_sminv (v2i32 V64:$Rn))),
3953 (EXTRACT_SUBREG (SMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3955 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", int_aarch64_neon_umaxv>;
3956 def : Pat<(i32 (int_aarch64_neon_umaxv (v2i32 V64:$Rn))),
3957 (EXTRACT_SUBREG (UMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3959 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", int_aarch64_neon_uminv>;
3960 def : Pat<(i32 (int_aarch64_neon_uminv (v2i32 V64:$Rn))),
3961 (EXTRACT_SUBREG (UMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3963 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_aarch64_neon_saddlv>;
3964 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_aarch64_neon_uaddlv>;
3966 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
3967 def : Pat<(i64 (int_aarch64_neon_saddlv (v2i32 V64:$Rn))),
3968 (i64 (EXTRACT_SUBREG
3969 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3970 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
3972 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
3973 def : Pat<(i64 (int_aarch64_neon_uaddlv (v2i32 V64:$Rn))),
3974 (i64 (EXTRACT_SUBREG
3975 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3976 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
3979 //------------------------------------------------------------------------------
3980 // AdvSIMD modified immediate instructions
3981 //------------------------------------------------------------------------------
3984 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
3986 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
3988 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
3989 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
3990 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
3991 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
3993 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3994 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3995 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3996 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3998 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
3999 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4000 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4001 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4003 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4004 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4005 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4006 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4009 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
4011 [(set (v2f64 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4012 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
4014 [(set (v2f32 V64:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4015 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
4017 [(set (v4f32 V128:$Rd), (AArch64fmov imm0_255:$imm8))]>;
4021 // EDIT byte mask: scalar
4022 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4023 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
4024 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
4025 // The movi_edit node has the immediate value already encoded, so we use
4026 // a plain imm0_255 here.
4027 def : Pat<(f64 (AArch64movi_edit imm0_255:$shift)),
4028 (MOVID imm0_255:$shift)>;
4030 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
4031 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
4032 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
4033 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
4035 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
4036 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
4037 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
4038 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
4040 // EDIT byte mask: 2d
4042 // The movi_edit node has the immediate value already encoded, so we use
4043 // a plain imm0_255 in the pattern
4044 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
4045 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
4048 [(set (v2i64 V128:$Rd), (AArch64movi_edit imm0_255:$imm8))]>;
4051 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
4052 // Complexity is added to break a tie with a plain MOVI.
4053 let AddedComplexity = 1 in {
4054 def : Pat<(f32 fpimm0),
4055 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
4057 def : Pat<(f64 fpimm0),
4058 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
4062 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4063 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4064 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4065 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
4067 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4068 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4069 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4070 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
4072 def : Pat<(v2f64 (AArch64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
4073 def : Pat<(v4f32 (AArch64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
4075 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4076 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
4078 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4079 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4080 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4081 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4083 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4084 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4085 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4086 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4088 def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4089 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
4090 def : Pat<(v4i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4091 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
4092 def : Pat<(v4i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4093 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
4094 def : Pat<(v8i16 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
4095 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
4097 // EDIT per word: 2s & 4s with MSL shifter
4098 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
4099 [(set (v2i32 V64:$Rd),
4100 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4101 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
4102 [(set (v4i32 V128:$Rd),
4103 (AArch64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4105 // Per byte: 8b & 16b
4106 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
4108 [(set (v8i8 V64:$Rd), (AArch64movi imm0_255:$imm8))]>;
4109 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
4111 [(set (v16i8 V128:$Rd), (AArch64movi imm0_255:$imm8))]>;
4115 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
4116 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
4118 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4119 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4120 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4121 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4123 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
4124 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
4125 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
4126 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
4128 def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4129 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
4130 def : Pat<(v4i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4131 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
4132 def : Pat<(v4i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4133 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
4134 def : Pat<(v8i16 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
4135 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
4137 // EDIT per word: 2s & 4s with MSL shifter
4138 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
4139 [(set (v2i32 V64:$Rd),
4140 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4141 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
4142 [(set (v4i32 V128:$Rd),
4143 (AArch64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
4145 //----------------------------------------------------------------------------
4146 // AdvSIMD indexed element
4147 //----------------------------------------------------------------------------
4149 let hasSideEffects = 0 in {
4150 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
4151 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
4154 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
4155 // instruction expects the addend first, while the intrinsic expects it last.
4157 // On the other hand, there are quite a few valid combinatorial options due to
4158 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
4159 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4160 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
4161 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
4162 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
4164 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4165 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
4166 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4167 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
4168 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4169 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
4170 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
4171 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
4173 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
4174 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4176 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4177 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4178 VectorIndexS:$idx))),
4179 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4180 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4181 (v2f32 (AArch64duplane32
4182 (v4f32 (insert_subvector undef,
4183 (v2f32 (fneg V64:$Rm)),
4185 VectorIndexS:$idx)))),
4186 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4187 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4188 VectorIndexS:$idx)>;
4189 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
4190 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4191 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
4192 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4194 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
4196 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4197 (AArch64duplane32 (v4f32 (fneg V128:$Rm)),
4198 VectorIndexS:$idx))),
4199 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
4200 VectorIndexS:$idx)>;
4201 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4202 (v4f32 (AArch64duplane32
4203 (v4f32 (insert_subvector undef,
4204 (v2f32 (fneg V64:$Rm)),
4206 VectorIndexS:$idx)))),
4207 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4208 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
4209 VectorIndexS:$idx)>;
4210 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
4211 (AArch64dup (f32 (fneg FPR32Op:$Rm))))),
4212 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
4213 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
4215 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
4216 // (DUPLANE from 64-bit would be trivial).
4217 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4218 (AArch64duplane64 (v2f64 (fneg V128:$Rm)),
4219 VectorIndexD:$idx))),
4221 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
4222 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
4223 (AArch64dup (f64 (fneg FPR64Op:$Rm))))),
4224 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
4225 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
4227 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
4228 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4229 (vector_extract (v4f32 (fneg V128:$Rm)),
4230 VectorIndexS:$idx))),
4231 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4232 V128:$Rm, VectorIndexS:$idx)>;
4233 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
4234 (vector_extract (v2f32 (fneg V64:$Rm)),
4235 VectorIndexS:$idx))),
4236 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
4237 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
4239 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
4240 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
4241 (vector_extract (v2f64 (fneg V128:$Rm)),
4242 VectorIndexS:$idx))),
4243 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
4244 V128:$Rm, VectorIndexS:$idx)>;
4247 defm : FMLSIndexedAfterNegPatterns<
4248 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
4249 defm : FMLSIndexedAfterNegPatterns<
4250 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
4252 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_aarch64_neon_fmulx>;
4253 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
4255 def : Pat<(v2f32 (fmul V64:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4256 (FMULv2i32_indexed V64:$Rn,
4257 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4259 def : Pat<(v4f32 (fmul V128:$Rn, (AArch64dup (f32 FPR32:$Rm)))),
4260 (FMULv4i32_indexed V128:$Rn,
4261 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
4263 def : Pat<(v2f64 (fmul V128:$Rn, (AArch64dup (f64 FPR64:$Rm)))),
4264 (FMULv2i64_indexed V128:$Rn,
4265 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
4268 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_aarch64_neon_sqdmulh>;
4269 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_aarch64_neon_sqrdmulh>;
4270 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
4271 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
4272 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
4273 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
4274 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
4275 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
4276 TriOpFrag<(add node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4277 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
4278 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_smull node:$MHS, node:$RHS))>>;
4279 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
4280 int_aarch64_neon_smull>;
4281 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
4282 int_aarch64_neon_sqadd>;
4283 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
4284 int_aarch64_neon_sqsub>;
4285 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_aarch64_neon_sqdmull>;
4286 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
4287 TriOpFrag<(add node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4288 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
4289 TriOpFrag<(sub node:$LHS, (int_aarch64_neon_umull node:$MHS, node:$RHS))>>;
4290 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
4291 int_aarch64_neon_umull>;
4293 // A scalar sqdmull with the second operand being a vector lane can be
4294 // handled directly with the indexed instruction encoding.
4295 def : Pat<(int_aarch64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
4296 (vector_extract (v4i32 V128:$Vm),
4297 VectorIndexS:$idx)),
4298 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
4300 //----------------------------------------------------------------------------
4301 // AdvSIMD scalar shift instructions
4302 //----------------------------------------------------------------------------
4303 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
4304 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
4305 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
4306 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
4307 // Codegen patterns for the above. We don't put these directly on the
4308 // instructions because TableGen's type inference can't handle the truth.
4309 // Having the same base pattern for fp <--> int totally freaks it out.
4310 def : Pat<(int_aarch64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
4311 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
4312 def : Pat<(int_aarch64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
4313 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
4314 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
4315 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4316 def : Pat<(i64 (int_aarch64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
4317 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4318 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
4320 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
4321 def : Pat<(v1i64 (int_aarch64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
4323 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
4324 def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
4325 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4326 def : Pat<(int_aarch64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
4327 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
4328 def : Pat<(f64 (int_aarch64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4329 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4330 def : Pat<(f64 (int_aarch64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
4331 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4332 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
4334 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4335 def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
4337 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4339 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;
4340 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
4341 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
4342 int_aarch64_neon_sqrshrn>;
4343 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
4344 int_aarch64_neon_sqrshrun>;
4345 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4346 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4347 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
4348 int_aarch64_neon_sqshrn>;
4349 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
4350 int_aarch64_neon_sqshrun>;
4351 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4352 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", AArch64srshri>;
4353 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4354 TriOpFrag<(add node:$LHS,
4355 (AArch64srshri node:$MHS, node:$RHS))>>;
4356 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", AArch64vashr>;
4357 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
4358 TriOpFrag<(add node:$LHS,
4359 (AArch64vashr node:$MHS, node:$RHS))>>;
4360 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
4361 int_aarch64_neon_uqrshrn>;
4362 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4363 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4364 int_aarch64_neon_uqshrn>;
4365 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", AArch64urshri>;
4366 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
4367 TriOpFrag<(add node:$LHS,
4368 (AArch64urshri node:$MHS, node:$RHS))>>;
4369 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", AArch64vlshr>;
4370 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
4371 TriOpFrag<(add node:$LHS,
4372 (AArch64vlshr node:$MHS, node:$RHS))>>;
4374 //----------------------------------------------------------------------------
4375 // AdvSIMD vector shift instructions
4376 //----------------------------------------------------------------------------
4377 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_aarch64_neon_vcvtfp2fxs>;
4378 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_aarch64_neon_vcvtfp2fxu>;
4379 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
4380 int_aarch64_neon_vcvtfxs2fp>;
4381 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
4382 int_aarch64_neon_rshrn>;
4383 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", AArch64vshl>;
4384 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
4385 BinOpFrag<(trunc (AArch64vashr node:$LHS, node:$RHS))>>;
4386 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_aarch64_neon_vsli>;
4387 def : Pat<(v1i64 (int_aarch64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4388 (i32 vecshiftL64:$imm))),
4389 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
4390 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
4391 int_aarch64_neon_sqrshrn>;
4392 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
4393 int_aarch64_neon_sqrshrun>;
4394 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", AArch64sqshlui>;
4395 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", AArch64sqshli>;
4396 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
4397 int_aarch64_neon_sqshrn>;
4398 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
4399 int_aarch64_neon_sqshrun>;
4400 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_aarch64_neon_vsri>;
4401 def : Pat<(v1i64 (int_aarch64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4402 (i32 vecshiftR64:$imm))),
4403 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
4404 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", AArch64srshri>;
4405 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
4406 TriOpFrag<(add node:$LHS,
4407 (AArch64srshri node:$MHS, node:$RHS))> >;
4408 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
4409 BinOpFrag<(AArch64vshl (sext node:$LHS), node:$RHS)>>;
4411 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", AArch64vashr>;
4412 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
4413 TriOpFrag<(add node:$LHS, (AArch64vashr node:$MHS, node:$RHS))>>;
4414 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
4415 int_aarch64_neon_vcvtfxu2fp>;
4416 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
4417 int_aarch64_neon_uqrshrn>;
4418 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", AArch64uqshli>;
4419 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
4420 int_aarch64_neon_uqshrn>;
4421 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", AArch64urshri>;
4422 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
4423 TriOpFrag<(add node:$LHS,
4424 (AArch64urshri node:$MHS, node:$RHS))> >;
4425 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
4426 BinOpFrag<(AArch64vshl (zext node:$LHS), node:$RHS)>>;
4427 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", AArch64vlshr>;
4428 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
4429 TriOpFrag<(add node:$LHS, (AArch64vlshr node:$MHS, node:$RHS))> >;
4431 // SHRN patterns for when a logical right shift was used instead of arithmetic
4432 // (the immediate guarantees no sign bits actually end up in the result so it
4434 def : Pat<(v8i8 (trunc (AArch64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
4435 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
4436 def : Pat<(v4i16 (trunc (AArch64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
4437 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
4438 def : Pat<(v2i32 (trunc (AArch64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
4439 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
4441 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
4442 (trunc (AArch64vlshr (v8i16 V128:$Rn),
4443 vecshiftR16Narrow:$imm)))),
4444 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4445 V128:$Rn, vecshiftR16Narrow:$imm)>;
4446 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
4447 (trunc (AArch64vlshr (v4i32 V128:$Rn),
4448 vecshiftR32Narrow:$imm)))),
4449 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4450 V128:$Rn, vecshiftR32Narrow:$imm)>;
4451 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
4452 (trunc (AArch64vlshr (v2i64 V128:$Rn),
4453 vecshiftR64Narrow:$imm)))),
4454 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4455 V128:$Rn, vecshiftR32Narrow:$imm)>;
4457 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
4458 // Anyexts are implemented as zexts.
4459 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
4460 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4461 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4462 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
4463 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4464 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4465 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
4466 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4467 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4468 // Also match an extend from the upper half of a 128 bit source register.
4469 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4470 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4471 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4472 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4473 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4474 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
4475 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4476 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4477 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4478 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4479 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4480 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
4481 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4482 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4483 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4484 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4485 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4486 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
4488 // Vector shift sxtl aliases
4489 def : InstAlias<"sxtl.8h $dst, $src1",
4490 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4491 def : InstAlias<"sxtl $dst.8h, $src1.8b",
4492 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4493 def : InstAlias<"sxtl.4s $dst, $src1",
4494 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4495 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4496 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4497 def : InstAlias<"sxtl.2d $dst, $src1",
4498 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4499 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4500 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4502 // Vector shift sxtl2 aliases
4503 def : InstAlias<"sxtl2.8h $dst, $src1",
4504 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4505 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4506 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4507 def : InstAlias<"sxtl2.4s $dst, $src1",
4508 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4509 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4510 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4511 def : InstAlias<"sxtl2.2d $dst, $src1",
4512 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4513 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4514 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4516 // Vector shift uxtl aliases
4517 def : InstAlias<"uxtl.8h $dst, $src1",
4518 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4519 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4520 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4521 def : InstAlias<"uxtl.4s $dst, $src1",
4522 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4523 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4524 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4525 def : InstAlias<"uxtl.2d $dst, $src1",
4526 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4527 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4528 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4530 // Vector shift uxtl2 aliases
4531 def : InstAlias<"uxtl2.8h $dst, $src1",
4532 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4533 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4534 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4535 def : InstAlias<"uxtl2.4s $dst, $src1",
4536 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4537 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4538 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4539 def : InstAlias<"uxtl2.2d $dst, $src1",
4540 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4541 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4542 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4544 // If an integer is about to be converted to a floating point value,
4545 // just load it on the floating point unit.
4546 // These patterns are more complex because floating point loads do not
4547 // support sign extension.
4548 // The sign extension has to be explicitly added and is only supported for
4549 // one step: byte-to-half, half-to-word, word-to-doubleword.
4550 // SCVTF GPR -> FPR is 9 cycles.
4551 // SCVTF FPR -> FPR is 4 cyclces.
4552 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4553 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4554 // and still being faster.
4555 // However, this is not good for code size.
4556 // 8-bits -> float. 2 sizes step-up.
4557 class SExtLoadi8CVTf32Pat<dag addrmode, dag INST>
4558 : Pat<(f32 (sint_to_fp (i32 (sextloadi8 addrmode)))),
4559 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4564 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4570 ssub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4572 def : SExtLoadi8CVTf32Pat<(ro8.Wpat GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext),
4573 (LDRBroW GPR64sp:$Rn, GPR32:$Rm, ro8.Wext:$ext)>;
4574 def : SExtLoadi8CVTf32Pat<(ro8.Xpat GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext),
4575 (LDRBroX GPR64sp:$Rn, GPR64:$Rm, ro8.Xext:$ext)>;
4576 def : SExtLoadi8CVTf32Pat<(am_indexed8 GPR64sp:$Rn, uimm12s1:$offset),
4577 (LDRBui GPR64sp:$Rn, uimm12s1:$offset)>;
4578 def : SExtLoadi8CVTf32Pat<(am_unscaled8 GPR64sp:$Rn, simm9:$offset),
4579 (LDURBi GPR64sp:$Rn, simm9:$offset)>;
4581 // 16-bits -> float. 1 size step-up.
4582 class SExtLoadi16CVTf32Pat<dag addrmode, dag INST>
4583 : Pat<(f32 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4584 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4586 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4590 ssub)))>, Requires<[NotForCodeSize]>;
4592 def : SExtLoadi16CVTf32Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4593 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4594 def : SExtLoadi16CVTf32Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4595 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4596 def : SExtLoadi16CVTf32Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4597 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4598 def : SExtLoadi16CVTf32Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4599 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4601 // 32-bits to 32-bits are handled in target specific dag combine:
4602 // performIntToFpCombine.
4603 // 64-bits integer to 32-bits floating point, not possible with
4604 // SCVTF on floating point registers (both source and destination
4605 // must have the same size).
4607 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4608 // 8-bits -> double. 3 size step-up: give up.
4609 // 16-bits -> double. 2 size step.
4610 class SExtLoadi16CVTf64Pat<dag addrmode, dag INST>
4611 : Pat <(f64 (sint_to_fp (i32 (sextloadi16 addrmode)))),
4612 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4617 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4623 dsub)))>, Requires<[NotForCodeSize, IsCyclone]>;
4625 def : SExtLoadi16CVTf64Pat<(ro16.Wpat GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext),
4626 (LDRHroW GPR64sp:$Rn, GPR32:$Rm, ro16.Wext:$ext)>;
4627 def : SExtLoadi16CVTf64Pat<(ro16.Xpat GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext),
4628 (LDRHroX GPR64sp:$Rn, GPR64:$Rm, ro16.Xext:$ext)>;
4629 def : SExtLoadi16CVTf64Pat<(am_indexed16 GPR64sp:$Rn, uimm12s2:$offset),
4630 (LDRHui GPR64sp:$Rn, uimm12s2:$offset)>;
4631 def : SExtLoadi16CVTf64Pat<(am_unscaled16 GPR64sp:$Rn, simm9:$offset),
4632 (LDURHi GPR64sp:$Rn, simm9:$offset)>;
4633 // 32-bits -> double. 1 size step-up.
4634 class SExtLoadi32CVTf64Pat<dag addrmode, dag INST>
4635 : Pat <(f64 (sint_to_fp (i32 (load addrmode)))),
4636 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4638 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4642 dsub)))>, Requires<[NotForCodeSize]>;
4644 def : SExtLoadi32CVTf64Pat<(ro32.Wpat GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext),
4645 (LDRSroW GPR64sp:$Rn, GPR32:$Rm, ro32.Wext:$ext)>;
4646 def : SExtLoadi32CVTf64Pat<(ro32.Xpat GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext),
4647 (LDRSroX GPR64sp:$Rn, GPR64:$Rm, ro32.Xext:$ext)>;
4648 def : SExtLoadi32CVTf64Pat<(am_indexed32 GPR64sp:$Rn, uimm12s4:$offset),
4649 (LDRSui GPR64sp:$Rn, uimm12s4:$offset)>;
4650 def : SExtLoadi32CVTf64Pat<(am_unscaled32 GPR64sp:$Rn, simm9:$offset),
4651 (LDURSi GPR64sp:$Rn, simm9:$offset)>;
4653 // 64-bits -> double are handled in target specific dag combine:
4654 // performIntToFpCombine.
4657 //----------------------------------------------------------------------------
4658 // AdvSIMD Load-Store Structure
4659 //----------------------------------------------------------------------------
4660 defm LD1 : SIMDLd1Multiple<"ld1">;
4661 defm LD2 : SIMDLd2Multiple<"ld2">;
4662 defm LD3 : SIMDLd3Multiple<"ld3">;
4663 defm LD4 : SIMDLd4Multiple<"ld4">;
4665 defm ST1 : SIMDSt1Multiple<"st1">;
4666 defm ST2 : SIMDSt2Multiple<"st2">;
4667 defm ST3 : SIMDSt3Multiple<"st3">;
4668 defm ST4 : SIMDSt4Multiple<"st4">;
4670 class Ld1Pat<ValueType ty, Instruction INST>
4671 : Pat<(ty (load GPR64sp:$Rn)), (INST GPR64sp:$Rn)>;
4673 def : Ld1Pat<v16i8, LD1Onev16b>;
4674 def : Ld1Pat<v8i16, LD1Onev8h>;
4675 def : Ld1Pat<v4i32, LD1Onev4s>;
4676 def : Ld1Pat<v2i64, LD1Onev2d>;
4677 def : Ld1Pat<v8i8, LD1Onev8b>;
4678 def : Ld1Pat<v4i16, LD1Onev4h>;
4679 def : Ld1Pat<v2i32, LD1Onev2s>;
4680 def : Ld1Pat<v1i64, LD1Onev1d>;
4682 class St1Pat<ValueType ty, Instruction INST>
4683 : Pat<(store ty:$Vt, GPR64sp:$Rn),
4684 (INST ty:$Vt, GPR64sp:$Rn)>;
4686 def : St1Pat<v16i8, ST1Onev16b>;
4687 def : St1Pat<v8i16, ST1Onev8h>;
4688 def : St1Pat<v4i32, ST1Onev4s>;
4689 def : St1Pat<v2i64, ST1Onev2d>;
4690 def : St1Pat<v8i8, ST1Onev8b>;
4691 def : St1Pat<v4i16, ST1Onev4h>;
4692 def : St1Pat<v2i32, ST1Onev2s>;
4693 def : St1Pat<v1i64, ST1Onev1d>;
4699 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4700 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4701 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4702 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4703 let mayLoad = 1, hasSideEffects = 0 in {
4704 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4705 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4706 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4707 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4708 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4709 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4710 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4711 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4712 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4713 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4714 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4715 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4716 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4717 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4718 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4719 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4722 def : Pat<(v8i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4723 (LD1Rv8b GPR64sp:$Rn)>;
4724 def : Pat<(v16i8 (AArch64dup (i32 (extloadi8 GPR64sp:$Rn)))),
4725 (LD1Rv16b GPR64sp:$Rn)>;
4726 def : Pat<(v4i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4727 (LD1Rv4h GPR64sp:$Rn)>;
4728 def : Pat<(v8i16 (AArch64dup (i32 (extloadi16 GPR64sp:$Rn)))),
4729 (LD1Rv8h GPR64sp:$Rn)>;
4730 def : Pat<(v2i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4731 (LD1Rv2s GPR64sp:$Rn)>;
4732 def : Pat<(v4i32 (AArch64dup (i32 (load GPR64sp:$Rn)))),
4733 (LD1Rv4s GPR64sp:$Rn)>;
4734 def : Pat<(v2i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4735 (LD1Rv2d GPR64sp:$Rn)>;
4736 def : Pat<(v1i64 (AArch64dup (i64 (load GPR64sp:$Rn)))),
4737 (LD1Rv1d GPR64sp:$Rn)>;
4738 // Grab the floating point version too
4739 def : Pat<(v2f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4740 (LD1Rv2s GPR64sp:$Rn)>;
4741 def : Pat<(v4f32 (AArch64dup (f32 (load GPR64sp:$Rn)))),
4742 (LD1Rv4s GPR64sp:$Rn)>;
4743 def : Pat<(v2f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4744 (LD1Rv2d GPR64sp:$Rn)>;
4745 def : Pat<(v1f64 (AArch64dup (f64 (load GPR64sp:$Rn)))),
4746 (LD1Rv1d GPR64sp:$Rn)>;
4747 def : Pat<(v4f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4748 (LD1Rv4h GPR64sp:$Rn)>;
4749 def : Pat<(v8f16 (AArch64dup (f16 (load GPR64sp:$Rn)))),
4750 (LD1Rv8h GPR64sp:$Rn)>;
4752 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4753 ValueType VTy, ValueType STy, Instruction LD1>
4754 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4755 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4756 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
4758 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4759 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4760 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4761 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4762 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4763 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4764 def : Ld1Lane128Pat<load, VectorIndexH, v8f16, f16, LD1i16>;
4766 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4767 ValueType VTy, ValueType STy, Instruction LD1>
4768 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4769 (STy (scalar_load GPR64sp:$Rn)), VecIndex:$idx),
4771 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4772 VecIndex:$idx, GPR64sp:$Rn),
4775 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4776 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4777 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4778 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4779 def : Ld1Lane64Pat<load, VectorIndexH, v4f16, f16, LD1i16>;
4782 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4783 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4784 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4785 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4788 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4789 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4790 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4791 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4793 let AddedComplexity = 15 in
4794 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4795 ValueType VTy, ValueType STy, Instruction ST1>
4797 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4799 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn)>;
4801 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4802 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
4803 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
4804 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
4805 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
4806 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
4807 def : St1Lane128Pat<store, VectorIndexH, v8f16, f16, ST1i16>;
4809 let AddedComplexity = 15 in
4810 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4811 ValueType VTy, ValueType STy, Instruction ST1>
4813 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4815 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4816 VecIndex:$idx, GPR64sp:$Rn)>;
4818 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
4819 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
4820 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
4821 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
4822 def : St1Lane64Pat<store, VectorIndexH, v4f16, f16, ST1i16>;
4824 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4825 ValueType VTy, ValueType STy, Instruction ST1,
4827 def : Pat<(scalar_store
4828 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4829 GPR64sp:$Rn, offset),
4830 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4831 VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4833 def : Pat<(scalar_store
4834 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4835 GPR64sp:$Rn, GPR64:$Rm),
4836 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4837 VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4840 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
4841 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
4843 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
4844 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
4845 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
4846 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
4847 defm : St1LanePost64Pat<post_store, VectorIndexH, v4f16, f16, ST1i16_POST, 2>;
4849 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4850 ValueType VTy, ValueType STy, Instruction ST1,
4852 def : Pat<(scalar_store
4853 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4854 GPR64sp:$Rn, offset),
4855 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, XZR)>;
4857 def : Pat<(scalar_store
4858 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4859 GPR64sp:$Rn, GPR64:$Rm),
4860 (ST1 VecListOne128:$Vt, VecIndex:$idx, GPR64sp:$Rn, $Rm)>;
4863 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
4865 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
4867 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
4868 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
4869 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
4870 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
4871 defm : St1LanePost128Pat<post_store, VectorIndexH, v8f16, f16, ST1i16_POST, 2>;
4873 let mayStore = 1, hasSideEffects = 0 in {
4874 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
4875 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
4876 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
4877 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
4878 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
4879 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
4880 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
4881 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
4882 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
4883 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
4884 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
4885 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
4888 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
4889 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
4890 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
4891 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
4893 //----------------------------------------------------------------------------
4894 // Crypto extensions
4895 //----------------------------------------------------------------------------
4897 def AESErr : AESTiedInst<0b0100, "aese", int_aarch64_crypto_aese>;
4898 def AESDrr : AESTiedInst<0b0101, "aesd", int_aarch64_crypto_aesd>;
4899 def AESMCrr : AESInst< 0b0110, "aesmc", int_aarch64_crypto_aesmc>;
4900 def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
4902 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_aarch64_crypto_sha1c>;
4903 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_aarch64_crypto_sha1p>;
4904 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_aarch64_crypto_sha1m>;
4905 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_aarch64_crypto_sha1su0>;
4906 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_aarch64_crypto_sha256h>;
4907 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_aarch64_crypto_sha256h2>;
4908 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_aarch64_crypto_sha256su1>;
4910 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_aarch64_crypto_sha1h>;
4911 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_aarch64_crypto_sha1su1>;
4912 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_aarch64_crypto_sha256su0>;
4914 //----------------------------------------------------------------------------
4916 //----------------------------------------------------------------------------
4917 // FIXME: Like for X86, these should go in their own separate .td file.
4919 // Any instruction that defines a 32-bit result leaves the high half of the
4920 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
4921 // be copying from a truncate. But any other 32-bit operation will zero-extend
4923 // FIXME: X86 also checks for CMOV here. Do we need something similar?
4924 def def32 : PatLeaf<(i32 GPR32:$src), [{
4925 return N->getOpcode() != ISD::TRUNCATE &&
4926 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
4927 N->getOpcode() != ISD::CopyFromReg;
4930 // In the case of a 32-bit def that is known to implicitly zero-extend,
4931 // we can use a SUBREG_TO_REG.
4932 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
4934 // For an anyext, we don't care what the high bits are, so we can perform an
4935 // INSERT_SUBREF into an IMPLICIT_DEF.
4936 def : Pat<(i64 (anyext GPR32:$src)),
4937 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
4939 // When we need to explicitly zero-extend, we use an unsigned bitfield move
4940 // instruction (UBFM) on the enclosing super-reg.
4941 def : Pat<(i64 (zext GPR32:$src)),
4942 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4944 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
4945 // containing super-reg.
4946 def : Pat<(i64 (sext GPR32:$src)),
4947 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4948 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
4949 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
4950 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
4951 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
4952 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
4953 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
4954 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
4956 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
4957 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4958 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
4959 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
4960 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4961 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
4963 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
4964 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4965 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
4966 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
4967 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4968 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
4970 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
4971 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4972 (i64 (i64shift_a imm0_63:$imm)),
4973 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
4975 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
4976 // AddedComplexity for the following patterns since we want to match sext + sra
4977 // patterns before we attempt to match a single sra node.
4978 let AddedComplexity = 20 in {
4979 // We support all sext + sra combinations which preserve at least one bit of the
4980 // original value which is to be sign extended. E.g. we support shifts up to
4982 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
4983 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
4984 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
4985 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
4987 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
4988 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
4989 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
4990 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
4992 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
4993 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4994 (i64 imm0_31:$imm), 31)>;
4995 } // AddedComplexity = 20
4997 // To truncate, we can simply extract from a subregister.
4998 def : Pat<(i32 (trunc GPR64sp:$src)),
4999 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
5001 // __builtin_trap() uses the BRK instruction on AArch64.
5002 def : Pat<(trap), (BRK 1)>;
5004 // Conversions within AdvSIMD types in the same register size are free.
5005 // But because we need a consistent lane ordering, in big endian many
5006 // conversions require one or more REV instructions.
5008 // Consider a simple memory load followed by a bitconvert then a store.
5010 // v1 = BITCAST v2i32 v0 to v4i16
5013 // In big endian mode every memory access has an implicit byte swap. LDR and
5014 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
5015 // is, they treat the vector as a sequence of elements to be byte-swapped.
5016 // The two pairs of instructions are fundamentally incompatible. We've decided
5017 // to use LD1/ST1 only to simplify compiler implementation.
5019 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
5020 // the original code sequence:
5022 // v1 = REV v2i32 (implicit)
5023 // v2 = BITCAST v2i32 v1 to v4i16
5024 // v3 = REV v4i16 v2 (implicit)
5027 // But this is now broken - the value stored is different to the value loaded
5028 // due to lane reordering. To fix this, on every BITCAST we must perform two
5031 // v1 = REV v2i32 (implicit)
5033 // v3 = BITCAST v2i32 v2 to v4i16
5035 // v5 = REV v4i16 v4 (implicit)
5038 // This means an extra two instructions, but actually in most cases the two REV
5039 // instructions can be combined into one. For example:
5040 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
5042 // There is also no 128-bit REV instruction. This must be synthesized with an
5045 // Most bitconverts require some sort of conversion. The only exceptions are:
5046 // a) Identity conversions - vNfX <-> vNiX
5047 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
5050 // Natural vector casts (64 bit)
5051 def : Pat<(v8i8 (AArch64NvCast (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5052 def : Pat<(v4i16 (AArch64NvCast (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5053 def : Pat<(v2i32 (AArch64NvCast (v2i32 FPR64:$src))), (v2i32 FPR64:$src)>;
5054 def : Pat<(v2f32 (AArch64NvCast (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5055 def : Pat<(v1i64 (AArch64NvCast (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5057 def : Pat<(v8i8 (AArch64NvCast (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5058 def : Pat<(v4i16 (AArch64NvCast (v4i16 FPR64:$src))), (v4i16 FPR64:$src)>;
5059 def : Pat<(v2i32 (AArch64NvCast (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5060 def : Pat<(v1i64 (AArch64NvCast (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5062 def : Pat<(v8i8 (AArch64NvCast (v8i8 FPR64:$src))), (v8i8 FPR64:$src)>;
5063 def : Pat<(v4i16 (AArch64NvCast (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5064 def : Pat<(v2i32 (AArch64NvCast (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5065 def : Pat<(v1i64 (AArch64NvCast (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5067 def : Pat<(v8i8 (AArch64NvCast (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5068 def : Pat<(v4i16 (AArch64NvCast (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5069 def : Pat<(v2i32 (AArch64NvCast (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5070 def : Pat<(v2f32 (AArch64NvCast (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5071 def : Pat<(v1i64 (AArch64NvCast (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5072 def : Pat<(v1f64 (AArch64NvCast (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5074 def : Pat<(v8i8 (AArch64NvCast (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5075 def : Pat<(v4i16 (AArch64NvCast (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5076 def : Pat<(v2i32 (AArch64NvCast (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5077 def : Pat<(v2f32 (AArch64NvCast (v2f32 FPR64:$src))), (v2f32 FPR64:$src)>;
5078 def : Pat<(v1i64 (AArch64NvCast (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5080 // Natural vector casts (128 bit)
5081 def : Pat<(v16i8 (AArch64NvCast (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5082 def : Pat<(v8i16 (AArch64NvCast (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5083 def : Pat<(v4i32 (AArch64NvCast (v4i32 FPR128:$src))), (v4i32 FPR128:$src)>;
5084 def : Pat<(v4f32 (AArch64NvCast (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5085 def : Pat<(v2i64 (AArch64NvCast (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5087 def : Pat<(v16i8 (AArch64NvCast (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5088 def : Pat<(v8i16 (AArch64NvCast (v8i16 FPR128:$src))), (v8i16 FPR128:$src)>;
5089 def : Pat<(v4i32 (AArch64NvCast (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5090 def : Pat<(v2i64 (AArch64NvCast (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5092 def : Pat<(v16i8 (AArch64NvCast (v16i8 FPR128:$src))), (v16i8 FPR128:$src)>;
5093 def : Pat<(v8i16 (AArch64NvCast (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5094 def : Pat<(v4i32 (AArch64NvCast (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5095 def : Pat<(v2i64 (AArch64NvCast (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5097 def : Pat<(v16i8 (AArch64NvCast (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5098 def : Pat<(v8i16 (AArch64NvCast (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5099 def : Pat<(v4i32 (AArch64NvCast (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5100 def : Pat<(v2i64 (AArch64NvCast (v2i64 FPR128:$src))), (v2i64 FPR128:$src)>;
5101 def : Pat<(v4f32 (AArch64NvCast (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5102 def : Pat<(v2f64 (AArch64NvCast (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5104 def : Pat<(v16i8 (AArch64NvCast (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5105 def : Pat<(v8i16 (AArch64NvCast (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5106 def : Pat<(v4i32 (AArch64NvCast (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5107 def : Pat<(v4f32 (AArch64NvCast (v4f32 FPR128:$src))), (v4f32 FPR128:$src)>;
5108 def : Pat<(v2i64 (AArch64NvCast (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5110 def : Pat<(v16i8 (AArch64NvCast (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5111 def : Pat<(v8i16 (AArch64NvCast (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5112 def : Pat<(v4i32 (AArch64NvCast (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5113 def : Pat<(v2i64 (AArch64NvCast (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5114 def : Pat<(v2f64 (AArch64NvCast (v2f64 FPR128:$src))), (v2f64 FPR128:$src)>;
5116 let Predicates = [IsLE] in {
5117 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5118 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5119 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5120 def : Pat<(v4f16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5121 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5123 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5124 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5125 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5126 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5127 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5128 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5129 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5130 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5131 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5132 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5133 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5134 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5136 let Predicates = [IsBE] in {
5137 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
5138 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5139 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
5140 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5141 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
5142 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5143 def : Pat<(v4f16 (bitconvert GPR64:$Xn)),
5144 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5145 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
5146 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
5148 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
5149 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5150 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
5151 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5152 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
5153 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5154 def : Pat<(i64 (bitconvert (v4f16 V64:$Vn))),
5155 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5156 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
5157 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
5159 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5160 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5161 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
5162 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5163 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
5164 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5165 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
5166 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5167 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
5169 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
5170 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
5171 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
5172 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
5173 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
5174 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
5175 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
5176 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
5177 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
5178 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
5180 let Predicates = [IsLE] in {
5181 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
5182 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
5183 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
5184 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))), (v1i64 FPR64:$src)>;
5185 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
5187 let Predicates = [IsBE] in {
5188 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
5189 (v1i64 (REV64v2i32 FPR64:$src))>;
5190 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
5191 (v1i64 (REV64v4i16 FPR64:$src))>;
5192 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
5193 (v1i64 (REV64v8i8 FPR64:$src))>;
5194 def : Pat<(v1i64 (bitconvert (v4f16 FPR64:$src))),
5195 (v1i64 (REV64v4i16 FPR64:$src))>;
5196 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
5197 (v1i64 (REV64v2i32 FPR64:$src))>;
5199 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5200 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
5202 let Predicates = [IsLE] in {
5203 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
5204 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
5205 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
5206 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5207 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
5208 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))), (v2i32 FPR64:$src)>;
5210 let Predicates = [IsBE] in {
5211 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
5212 (v2i32 (REV64v2i32 FPR64:$src))>;
5213 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
5214 (v2i32 (REV32v4i16 FPR64:$src))>;
5215 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
5216 (v2i32 (REV32v8i8 FPR64:$src))>;
5217 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
5218 (v2i32 (REV64v2i32 FPR64:$src))>;
5219 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
5220 (v2i32 (REV64v2i32 FPR64:$src))>;
5221 def : Pat<(v2i32 (bitconvert (v4f16 FPR64:$src))),
5222 (v2i32 (REV64v4i16 FPR64:$src))>;
5224 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
5226 let Predicates = [IsLE] in {
5227 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
5228 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
5229 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
5230 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5231 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))), (v4i16 FPR64:$src)>;
5232 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
5233 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
5235 let Predicates = [IsBE] in {
5236 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
5237 (v4i16 (REV64v4i16 FPR64:$src))>;
5238 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
5239 (v4i16 (REV32v4i16 FPR64:$src))>;
5240 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
5241 (v4i16 (REV16v8i8 FPR64:$src))>;
5242 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
5243 (v4i16 (REV64v4i16 FPR64:$src))>;
5244 def : Pat<(v4i16 (bitconvert (v4f16 FPR64:$src))),
5245 (v4i16 (REV32v4i16 FPR64:$src))>;
5246 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
5247 (v4i16 (REV32v4i16 FPR64:$src))>;
5248 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
5249 (v4i16 (REV64v4i16 FPR64:$src))>;
5252 let Predicates = [IsLE] in {
5253 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))), (v4f16 FPR64:$src)>;
5254 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))), (v4f16 FPR64:$src)>;
5255 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))), (v4f16 FPR64:$src)>;
5256 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))), (v4f16 FPR64:$src)>;
5257 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5258 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))), (v4f16 FPR64:$src)>;
5259 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))), (v4f16 FPR64:$src)>;
5261 let Predicates = [IsBE] in {
5262 def : Pat<(v4f16 (bitconvert (v1i64 FPR64:$src))),
5263 (v4f16 (REV64v4i16 FPR64:$src))>;
5264 def : Pat<(v4f16 (bitconvert (v2i32 FPR64:$src))),
5265 (v4f16 (REV64v4i16 FPR64:$src))>;
5266 def : Pat<(v4f16 (bitconvert (v4i16 FPR64:$src))),
5267 (v4f16 (REV64v4i16 FPR64:$src))>;
5268 def : Pat<(v4f16 (bitconvert (v8i8 FPR64:$src))),
5269 (v4f16 (REV16v8i8 FPR64:$src))>;
5270 def : Pat<(v4f16 (bitconvert (f64 FPR64:$src))),
5271 (v4f16 (REV64v4i16 FPR64:$src))>;
5272 def : Pat<(v4f16 (bitconvert (v2f32 FPR64:$src))),
5273 (v4f16 (REV64v4i16 FPR64:$src))>;
5274 def : Pat<(v4f16 (bitconvert (v1f64 FPR64:$src))),
5275 (v4f16 (REV64v4i16 FPR64:$src))>;
5280 let Predicates = [IsLE] in {
5281 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
5282 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
5283 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
5284 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5285 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
5286 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
5287 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))), (v8i8 FPR64:$src)>;
5289 let Predicates = [IsBE] in {
5290 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
5291 (v8i8 (REV64v8i8 FPR64:$src))>;
5292 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
5293 (v8i8 (REV32v8i8 FPR64:$src))>;
5294 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
5295 (v8i8 (REV16v8i8 FPR64:$src))>;
5296 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
5297 (v8i8 (REV64v8i8 FPR64:$src))>;
5298 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
5299 (v8i8 (REV32v8i8 FPR64:$src))>;
5300 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
5301 (v8i8 (REV64v8i8 FPR64:$src))>;
5302 def : Pat<(v8i8 (bitconvert (v4f16 FPR64:$src))),
5303 (v8i8 (REV16v8i8 FPR64:$src))>;
5306 let Predicates = [IsLE] in {
5307 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
5308 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
5309 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
5310 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
5311 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))), (f64 FPR64:$src)>;
5313 let Predicates = [IsBE] in {
5314 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
5315 (f64 (REV64v2i32 FPR64:$src))>;
5316 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
5317 (f64 (REV64v4i16 FPR64:$src))>;
5318 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
5319 (f64 (REV64v2i32 FPR64:$src))>;
5320 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
5321 (f64 (REV64v8i8 FPR64:$src))>;
5322 def : Pat<(f64 (bitconvert (v4f16 FPR64:$src))),
5323 (f64 (REV64v4i16 FPR64:$src))>;
5325 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
5326 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
5328 let Predicates = [IsLE] in {
5329 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
5330 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
5331 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
5332 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
5333 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))), (v1f64 FPR64:$src)>;
5335 let Predicates = [IsBE] in {
5336 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
5337 (v1f64 (REV64v2i32 FPR64:$src))>;
5338 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
5339 (v1f64 (REV64v4i16 FPR64:$src))>;
5340 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
5341 (v1f64 (REV64v8i8 FPR64:$src))>;
5342 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
5343 (v1f64 (REV64v2i32 FPR64:$src))>;
5344 def : Pat<(v1f64 (bitconvert (v4f16 FPR64:$src))),
5345 (v1f64 (REV64v4i16 FPR64:$src))>;
5347 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
5348 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
5350 let Predicates = [IsLE] in {
5351 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
5352 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
5353 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
5354 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5355 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
5356 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))), (v2f32 FPR64:$src)>;
5358 let Predicates = [IsBE] in {
5359 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
5360 (v2f32 (REV64v2i32 FPR64:$src))>;
5361 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
5362 (v2f32 (REV32v4i16 FPR64:$src))>;
5363 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
5364 (v2f32 (REV32v8i8 FPR64:$src))>;
5365 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
5366 (v2f32 (REV64v2i32 FPR64:$src))>;
5367 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
5368 (v2f32 (REV64v2i32 FPR64:$src))>;
5369 def : Pat<(v2f32 (bitconvert (v4f16 FPR64:$src))),
5370 (v2f32 (REV64v4i16 FPR64:$src))>;
5372 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
5374 let Predicates = [IsLE] in {
5375 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
5376 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
5377 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
5378 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
5379 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
5380 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))), (f128 FPR128:$src)>;
5381 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
5383 let Predicates = [IsBE] in {
5384 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
5385 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5386 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
5387 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5388 (REV64v4i32 FPR128:$src), (i32 8)))>;
5389 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
5390 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5391 (REV64v8i16 FPR128:$src), (i32 8)))>;
5392 def : Pat<(f128 (bitconvert (v8f16 FPR128:$src))),
5393 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
5394 (REV64v8i16 FPR128:$src), (i32 8)))>;
5395 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
5396 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
5397 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
5398 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
5399 (REV64v4i32 FPR128:$src), (i32 8)))>;
5400 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
5401 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
5402 (REV64v16i8 FPR128:$src), (i32 8)))>;
5405 let Predicates = [IsLE] in {
5406 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
5407 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
5408 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
5409 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))), (v2f64 FPR128:$src)>;
5410 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
5411 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
5413 let Predicates = [IsBE] in {
5414 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
5415 (v2f64 (EXTv16i8 FPR128:$src,
5416 FPR128:$src, (i32 8)))>;
5417 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
5418 (v2f64 (REV64v4i32 FPR128:$src))>;
5419 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
5420 (v2f64 (REV64v8i16 FPR128:$src))>;
5421 def : Pat<(v2f64 (bitconvert (v8f16 FPR128:$src))),
5422 (v2f64 (REV64v8i16 FPR128:$src))>;
5423 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
5424 (v2f64 (REV64v16i8 FPR128:$src))>;
5425 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
5426 (v2f64 (REV64v4i32 FPR128:$src))>;
5428 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
5430 let Predicates = [IsLE] in {
5431 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
5432 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5433 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))), (v4f32 FPR128:$src)>;
5434 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5435 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5436 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5438 let Predicates = [IsBE] in {
5439 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
5440 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5441 (REV64v4i32 FPR128:$src), (i32 8)))>;
5442 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
5443 (v4f32 (REV32v8i16 FPR128:$src))>;
5444 def : Pat<(v4f32 (bitconvert (v8f16 FPR128:$src))),
5445 (v4f32 (REV32v8i16 FPR128:$src))>;
5446 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
5447 (v4f32 (REV32v16i8 FPR128:$src))>;
5448 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
5449 (v4f32 (REV64v4i32 FPR128:$src))>;
5450 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
5451 (v4f32 (REV64v4i32 FPR128:$src))>;
5453 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5455 let Predicates = [IsLE] in {
5456 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5457 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5458 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5459 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5460 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5461 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))), (v2i64 FPR128:$src)>;
5463 let Predicates = [IsBE] in {
5464 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
5465 (v2i64 (EXTv16i8 FPR128:$src,
5466 FPR128:$src, (i32 8)))>;
5467 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
5468 (v2i64 (REV64v4i32 FPR128:$src))>;
5469 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
5470 (v2i64 (REV64v8i16 FPR128:$src))>;
5471 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
5472 (v2i64 (REV64v16i8 FPR128:$src))>;
5473 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
5474 (v2i64 (REV64v4i32 FPR128:$src))>;
5475 def : Pat<(v2i64 (bitconvert (v8f16 FPR128:$src))),
5476 (v2i64 (REV64v8i16 FPR128:$src))>;
5478 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5480 let Predicates = [IsLE] in {
5481 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5482 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5483 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5484 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5485 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5486 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))), (v4i32 FPR128:$src)>;
5488 let Predicates = [IsBE] in {
5489 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
5490 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5491 (REV64v4i32 FPR128:$src),
5493 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
5494 (v4i32 (REV64v4i32 FPR128:$src))>;
5495 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
5496 (v4i32 (REV32v8i16 FPR128:$src))>;
5497 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
5498 (v4i32 (REV32v16i8 FPR128:$src))>;
5499 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
5500 (v4i32 (REV64v4i32 FPR128:$src))>;
5501 def : Pat<(v4i32 (bitconvert (v8f16 FPR128:$src))),
5502 (v4i32 (REV32v8i16 FPR128:$src))>;
5504 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5506 let Predicates = [IsLE] in {
5507 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5508 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5509 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5510 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5511 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5512 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5513 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))), (v8i16 FPR128:$src)>;
5515 let Predicates = [IsBE] in {
5516 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
5517 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5518 (REV64v8i16 FPR128:$src),
5520 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
5521 (v8i16 (REV64v8i16 FPR128:$src))>;
5522 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
5523 (v8i16 (REV32v8i16 FPR128:$src))>;
5524 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
5525 (v8i16 (REV16v16i8 FPR128:$src))>;
5526 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
5527 (v8i16 (REV64v8i16 FPR128:$src))>;
5528 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
5529 (v8i16 (REV32v8i16 FPR128:$src))>;
5530 def : Pat<(v8i16 (bitconvert (v8f16 FPR128:$src))),
5531 (v8i16 (REV32v8i16 FPR128:$src))>;
5534 let Predicates = [IsLE] in {
5535 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))), (v8f16 FPR128:$src)>;
5536 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))), (v8f16 FPR128:$src)>;
5537 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))), (v8f16 FPR128:$src)>;
5538 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))), (v8f16 FPR128:$src)>;
5539 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))), (v8f16 FPR128:$src)>;
5540 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))), (v8f16 FPR128:$src)>;
5541 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))), (v8f16 FPR128:$src)>;
5543 let Predicates = [IsBE] in {
5544 def : Pat<(v8f16 (bitconvert (f128 FPR128:$src))),
5545 (v8f16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5546 (REV64v8i16 FPR128:$src),
5548 def : Pat<(v8f16 (bitconvert (v2i64 FPR128:$src))),
5549 (v8f16 (REV64v8i16 FPR128:$src))>;
5550 def : Pat<(v8f16 (bitconvert (v4i32 FPR128:$src))),
5551 (v8f16 (REV32v8i16 FPR128:$src))>;
5552 def : Pat<(v8f16 (bitconvert (v8i16 FPR128:$src))),
5553 (v8f16 (REV64v8i16 FPR128:$src))>;
5554 def : Pat<(v8f16 (bitconvert (v16i8 FPR128:$src))),
5555 (v8f16 (REV16v16i8 FPR128:$src))>;
5556 def : Pat<(v8f16 (bitconvert (v2f64 FPR128:$src))),
5557 (v8f16 (REV64v8i16 FPR128:$src))>;
5558 def : Pat<(v8f16 (bitconvert (v4f32 FPR128:$src))),
5559 (v8f16 (REV32v8i16 FPR128:$src))>;
5562 let Predicates = [IsLE] in {
5563 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5564 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5565 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5566 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5567 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5568 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5569 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))), (v16i8 FPR128:$src)>;
5571 let Predicates = [IsBE] in {
5572 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
5573 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
5574 (REV64v16i8 FPR128:$src),
5576 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
5577 (v16i8 (REV64v16i8 FPR128:$src))>;
5578 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
5579 (v16i8 (REV32v16i8 FPR128:$src))>;
5580 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
5581 (v16i8 (REV16v16i8 FPR128:$src))>;
5582 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
5583 (v16i8 (REV64v16i8 FPR128:$src))>;
5584 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
5585 (v16i8 (REV32v16i8 FPR128:$src))>;
5586 def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))),
5587 (v16i8 (REV16v16i8 FPR128:$src))>;
5590 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
5591 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5592 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
5593 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5594 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
5595 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5596 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
5597 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5599 // A 64-bit subvector insert to the first 128-bit vector position
5600 // is a subregister copy that needs no instruction.
5601 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
5602 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5603 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
5604 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5605 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
5606 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5607 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
5608 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5609 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
5610 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5611 def : Pat<(insert_subvector undef, (v4f16 FPR64:$src), (i32 0)),
5612 (INSERT_SUBREG (v8f16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5613 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
5614 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5616 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
5618 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
5619 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
5620 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
5621 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
5622 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
5623 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
5624 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
5625 // so we match on v4f32 here, not v2f32. This will also catch adding
5626 // the low two lanes of a true v4f32 vector.
5627 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
5628 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
5629 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
5631 // Scalar 64-bit shifts in FPR64 registers.
5632 def : Pat<(i64 (int_aarch64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5633 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5634 def : Pat<(i64 (int_aarch64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5635 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5636 def : Pat<(i64 (int_aarch64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5637 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5638 def : Pat<(i64 (int_aarch64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5639 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5641 // Tail call return handling. These are all compiler pseudo-instructions,
5642 // so no encoding information or anything like that.
5643 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
5644 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff),[]>;
5645 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>;
5648 def : Pat<(AArch64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
5649 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
5650 def : Pat<(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
5651 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5652 def : Pat<(AArch64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
5653 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5655 include "AArch64InstrAtomics.td"