1 //===- AArch64InstrFormats.td - AArch64 Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This file describes AArch64 instruction formats, down to the level of the
10 // instruction's overall class.
11 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // A64 Instruction Format Definitions.
16 //===----------------------------------------------------------------------===//
18 // A64 is currently the only instruction set supported by the AArch64
20 class A64Inst<dag outs, dag ins, string asmstr, list<dag> patterns,
23 // All A64 instructions are 32-bit. This field will be filled in
24 // gradually going down the hierarchy.
27 field bits<32> Unpredictable = 0;
28 // SoftFail is the generic name for this field, but we alias it so
29 // as to make it more obvious what it means in ARM-land.
30 field bits<32> SoftFail = Unpredictable;
32 // LLVM-level model of the AArch64/A64 distinction.
33 let Namespace = "AArch64";
34 let DecoderNamespace = "A64";
37 // Set the templated fields
38 let OutOperandList = outs;
39 let InOperandList = ins;
40 let AsmString = asmstr;
41 let Pattern = patterns;
45 class PseudoInst<dag outs, dag ins, list<dag> patterns> : Instruction {
46 let Namespace = "AArch64";
48 let OutOperandList = outs;
49 let InOperandList= ins;
50 let Pattern = patterns;
51 let isCodeGenOnly = 1;
55 // Represents a pseudo-instruction that represents a single A64 instruction for
56 // whatever reason, the eventual result will be a 32-bit real instruction.
57 class A64PseudoInst<dag outs, dag ins, list<dag> patterns>
58 : PseudoInst<outs, ins, patterns> {
62 // As above, this will be a single A64 instruction, but we can actually give the
63 // expansion in TableGen.
64 class A64PseudoExpand<dag outs, dag ins, list<dag> patterns, dag Result>
65 : A64PseudoInst<outs, ins, patterns>,
66 PseudoInstExpansion<Result>;
69 // First, some common cross-hierarchy register formats.
71 class A64InstRd<dag outs, dag ins, string asmstr,
72 list<dag> patterns, InstrItinClass itin>
73 : A64Inst<outs, ins, asmstr, patterns, itin> {
79 class A64InstRt<dag outs, dag ins, string asmstr,
80 list<dag> patterns, InstrItinClass itin>
81 : A64Inst<outs, ins, asmstr, patterns, itin> {
88 class A64InstRdn<dag outs, dag ins, string asmstr,
89 list<dag> patterns, InstrItinClass itin>
90 : A64InstRd<outs, ins, asmstr, patterns, itin> {
97 class A64InstRtn<dag outs, dag ins, string asmstr,
98 list<dag> patterns, InstrItinClass itin>
99 : A64InstRt<outs, ins, asmstr, patterns, itin> {
106 // Instructions taking Rt,Rt2,Rn
107 class A64InstRtt2n<dag outs, dag ins, string asmstr,
108 list<dag> patterns, InstrItinClass itin>
109 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
112 let Inst{14-10} = Rt2;
115 class A64InstRdnm<dag outs, dag ins, string asmstr,
116 list<dag> patterns, InstrItinClass itin>
117 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
120 let Inst{20-16} = Rm;
123 //===----------------------------------------------------------------------===//
125 // Actual A64 Instruction Formats
128 // Format for Add-subtract (extended register) instructions.
129 class A64I_addsubext<bit sf, bit op, bit S, bits<2> opt, bits<3> option,
130 dag outs, dag ins, string asmstr, list<dag> patterns,
132 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
138 let Inst{28-24} = 0b01011;
139 let Inst{23-22} = opt;
141 // Rm inherited in 20-16
142 let Inst{15-13} = option;
143 let Inst{12-10} = Imm3;
144 // Rn inherited in 9-5
145 // Rd inherited in 4-0
148 // Format for Add-subtract (immediate) instructions.
149 class A64I_addsubimm<bit sf, bit op, bit S, bits<2> shift,
150 dag outs, dag ins, string asmstr,
151 list<dag> patterns, InstrItinClass itin>
152 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
158 let Inst{28-24} = 0b10001;
159 let Inst{23-22} = shift;
160 let Inst{21-10} = Imm12;
163 // Format for Add-subtract (shifted register) instructions.
164 class A64I_addsubshift<bit sf, bit op, bit S, bits<2> shift,
165 dag outs, dag ins, string asmstr, list<dag> patterns,
167 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
173 let Inst{28-24} = 0b01011;
174 let Inst{23-22} = shift;
176 // Rm inherited in 20-16
177 let Inst{15-10} = Imm6;
178 // Rn inherited in 9-5
179 // Rd inherited in 4-0
182 // Format for Add-subtract (with carry) instructions.
183 class A64I_addsubcarry<bit sf, bit op, bit S, bits<6> opcode2,
184 dag outs, dag ins, string asmstr, list<dag> patterns,
186 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
190 let Inst{28-21} = 0b11010000;
191 // Rm inherited in 20-16
192 let Inst{15-10} = opcode2;
193 // Rn inherited in 9-5
194 // Rd inherited in 4-0
198 // Format for Bitfield instructions
199 class A64I_bitfield<bit sf, bits<2> opc, bit n,
200 dag outs, dag ins, string asmstr,
201 list<dag> patterns, InstrItinClass itin>
202 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
207 let Inst{30-29} = opc;
208 let Inst{28-23} = 0b100110;
210 let Inst{21-16} = ImmR;
211 let Inst{15-10} = ImmS;
216 // Format for compare and branch (immediate) instructions.
217 class A64I_cmpbr<bit sf, bit op,
218 dag outs, dag ins, string asmstr,
219 list<dag> patterns, InstrItinClass itin>
220 : A64InstRt<outs, ins, asmstr, patterns, itin> {
224 let Inst{30-25} = 0b011010;
226 let Inst{23-5} = Label;
230 // Format for conditional branch (immediate) instructions.
231 class A64I_condbr<bit o1, bit o0,
232 dag outs, dag ins, string asmstr,
233 list<dag> patterns, InstrItinClass itin>
234 : A64Inst<outs, ins, asmstr, patterns, itin> {
238 let Inst{31-25} = 0b0101010;
240 let Inst{23-5} = Label;
242 let Inst{3-0} = Cond;
245 // Format for conditional compare (immediate) instructions.
246 class A64I_condcmpimm<bit sf, bit op, bit o2, bit o3, bit s,
247 dag outs, dag ins, string asmstr,
248 list<dag> patterns, InstrItinClass itin>
249 : A64Inst<outs, ins, asmstr, patterns, itin> {
258 let Inst{28-21} = 0b11010010;
259 let Inst{20-16} = UImm5;
260 let Inst{15-12} = Cond;
265 let Inst{3-0} = NZCVImm;
268 // Format for conditional compare (register) instructions.
269 class A64I_condcmpreg<bit sf, bit op, bit o2, bit o3, bit s,
270 dag outs, dag ins, string asmstr,
271 list<dag> patterns, InstrItinClass itin>
272 : A64Inst<outs, ins, asmstr, patterns, itin> {
282 let Inst{28-21} = 0b11010010;
283 let Inst{20-16} = Rm;
284 let Inst{15-12} = Cond;
289 let Inst{3-0} = NZCVImm;
292 // Format for conditional select instructions.
293 class A64I_condsel<bit sf, bit op, bit s, bits<2> op2,
294 dag outs, dag ins, string asmstr,
295 list<dag> patterns, InstrItinClass itin>
296 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
302 let Inst{28-21} = 0b11010100;
303 // Inherit Rm in 20-16
304 let Inst{15-12} = Cond;
305 let Inst{11-10} = op2;
310 // Format for data processing (1 source) instructions
311 class A64I_dp_1src<bit sf, bit S, bits<5> opcode2, bits<6> opcode,
312 string asmstr, dag outs, dag ins,
313 list<dag> patterns, InstrItinClass itin>
314 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
318 let Inst{28-21} = 0b11010110;
319 let Inst{20-16} = opcode2;
320 let Inst{15-10} = opcode;
323 // Format for data processing (2 source) instructions
324 class A64I_dp_2src<bit sf, bits<6> opcode, bit S,
325 string asmstr, dag outs, dag ins,
326 list<dag> patterns, InstrItinClass itin>
327 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
331 let Inst{28-21} = 0b11010110;
332 let Inst{15-10} = opcode;
335 // Format for data-processing (3 source) instructions
337 class A64I_dp3<bit sf, bits<6> opcode,
338 dag outs, dag ins, string asmstr,
339 list<dag> patterns, InstrItinClass itin>
340 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
344 let Inst{30-29} = opcode{5-4};
345 let Inst{28-24} = 0b11011;
346 let Inst{23-21} = opcode{3-1};
347 // Inherits Rm in 20-16
348 let Inst{15} = opcode{0};
349 let Inst{14-10} = Ra;
350 // Inherits Rn in 9-5
351 // Inherits Rd in 4-0
354 // Format for exception generation instructions
355 class A64I_exception<bits<3> opc, bits<3> op2, bits<2> ll,
356 dag outs, dag ins, string asmstr,
357 list<dag> patterns, InstrItinClass itin>
358 : A64Inst<outs, ins, asmstr, patterns, itin> {
361 let Inst{31-24} = 0b11010100;
362 let Inst{23-21} = opc;
363 let Inst{20-5} = UImm16;
368 // Format for extract (immediate) instructions
369 class A64I_extract<bit sf, bits<3> op, bit n,
370 dag outs, dag ins, string asmstr,
371 list<dag> patterns, InstrItinClass itin>
372 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
376 let Inst{30-29} = op{2-1};
377 let Inst{28-23} = 0b100111;
379 let Inst{21} = op{0};
380 // Inherits Rm in bits 20-16
381 let Inst{15-10} = LSB;
382 // Inherits Rn in 9-5
383 // Inherits Rd in 4-0
386 let Predicates = [HasFPARMv8] in {
388 // Format for floating-point compare instructions.
389 class A64I_fpcmp<bit m, bit s, bits<2> type, bits<2> op, bits<5> opcode2,
390 dag outs, dag ins, string asmstr,
391 list<dag> patterns, InstrItinClass itin>
392 : A64Inst<outs, ins, asmstr, patterns, itin> {
399 let Inst{28-24} = 0b11110;
400 let Inst{23-22} = type;
402 let Inst{20-16} = Rm;
403 let Inst{15-14} = op;
404 let Inst{13-10} = 0b1000;
406 let Inst{4-0} = opcode2;
409 // Format for floating-point conditional compare instructions.
410 class A64I_fpccmp<bit m, bit s, bits<2> type, bit op,
411 dag outs, dag ins, string asmstr,
412 list<dag> patterns, InstrItinClass itin>
413 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
422 let Inst{28-24} = 0b11110;
423 let Inst{23-22} = type;
425 let Inst{20-16} = Rm;
426 let Inst{15-12} = Cond;
427 let Inst{11-10} = 0b01;
430 let Inst{3-0} = NZCVImm;
433 // Format for floating-point conditional select instructions.
434 class A64I_fpcondsel<bit m, bit s, bits<2> type,
435 dag outs, dag ins, string asmstr,
436 list<dag> patterns, InstrItinClass itin>
437 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
443 let Inst{28-24} = 0b11110;
444 let Inst{23-22} = type;
446 // Inherit Rm in 20-16
447 let Inst{15-12} = Cond;
448 let Inst{11-10} = 0b11;
454 // Format for floating-point data-processing (1 source) instructions.
455 class A64I_fpdp1<bit m, bit s, bits<2> type, bits<6> opcode,
456 dag outs, dag ins, string asmstr,
457 list<dag> patterns, InstrItinClass itin>
458 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
462 let Inst{28-24} = 0b11110;
463 let Inst{23-22} = type;
465 let Inst{20-15} = opcode;
466 let Inst{14-10} = 0b10000;
471 // Format for floating-point data-processing (2 sources) instructions.
472 class A64I_fpdp2<bit m, bit s, bits<2> type, bits<4> opcode,
473 dag outs, dag ins, string asmstr,
474 list<dag> patterns, InstrItinClass itin>
475 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
479 let Inst{28-24} = 0b11110;
480 let Inst{23-22} = type;
482 // Inherit Rm in 20-16
483 let Inst{15-12} = opcode;
484 let Inst{11-10} = 0b10;
489 // Format for floating-point data-processing (3 sources) instructions.
490 class A64I_fpdp3<bit m, bit s, bits<2> type, bit o1, bit o0,
491 dag outs, dag ins, string asmstr,
492 list<dag> patterns, InstrItinClass itin>
493 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
499 let Inst{28-24} = 0b11111;
500 let Inst{23-22} = type;
502 // Inherit Rm in 20-16
504 let Inst{14-10} = Ra;
509 // Format for floating-point <-> fixed-point conversion instructions.
510 class A64I_fpfixed<bit sf, bit s, bits<2> type, bits<2> mode, bits<3> opcode,
511 dag outs, dag ins, string asmstr,
512 list<dag> patterns, InstrItinClass itin>
513 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
519 let Inst{28-24} = 0b11110;
520 let Inst{23-22} = type;
522 let Inst{20-19} = mode;
523 let Inst{18-16} = opcode;
524 let Inst{15-10} = Scale;
529 // Format for floating-point <-> integer conversion instructions.
530 class A64I_fpint<bit sf, bit s, bits<2> type, bits<2> rmode, bits<3> opcode,
531 dag outs, dag ins, string asmstr,
532 list<dag> patterns, InstrItinClass itin>
533 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
537 let Inst{28-24} = 0b11110;
538 let Inst{23-22} = type;
540 let Inst{20-19} = rmode;
541 let Inst{18-16} = opcode;
542 let Inst{15-10} = 0b000000;
548 // Format for floating-point immediate instructions.
549 class A64I_fpimm<bit m, bit s, bits<2> type, bits<5> imm5,
550 dag outs, dag ins, string asmstr,
551 list<dag> patterns, InstrItinClass itin>
552 : A64InstRd<outs, ins, asmstr, patterns, itin> {
558 let Inst{28-24} = 0b11110;
559 let Inst{23-22} = type;
561 let Inst{20-13} = Imm8;
562 let Inst{12-10} = 0b100;
563 let Inst{9-5} = imm5;
569 // Format for load-register (literal) instructions.
570 class A64I_LDRlit<bits<2> opc, bit v,
571 dag outs, dag ins, string asmstr,
572 list<dag> patterns, InstrItinClass itin>
573 : A64InstRt<outs, ins, asmstr, patterns, itin> {
576 let Inst{31-30} = opc;
577 let Inst{29-27} = 0b011;
579 let Inst{25-24} = 0b00;
580 let Inst{23-5} = Imm19;
584 // Format for load-store exclusive instructions.
585 class A64I_LDSTex_tn<bits<2> size, bit o2, bit L, bit o1, bit o0,
586 dag outs, dag ins, string asmstr,
587 list <dag> patterns, InstrItinClass itin>
588 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
589 let Inst{31-30} = size;
590 let Inst{29-24} = 0b001000;
597 class A64I_LDSTex_tt2n<bits<2> size, bit o2, bit L, bit o1, bit o0,
598 dag outs, dag ins, string asmstr,
599 list <dag> patterns, InstrItinClass itin>:
600 A64I_LDSTex_tn<size, o2, L, o1, o0, outs, ins, asmstr, patterns, itin>{
602 let Inst{14-10} = Rt2;
605 class A64I_LDSTex_stn<bits<2> size, bit o2, bit L, bit o1, bit o0,
606 dag outs, dag ins, string asmstr,
607 list <dag> patterns, InstrItinClass itin>:
608 A64I_LDSTex_tn<size, o2, L, o1, o0, outs, ins, asmstr, patterns, itin>{
610 let Inst{20-16} = Rs;
613 class A64I_LDSTex_stt2n<bits<2> size, bit o2, bit L, bit o1, bit o0,
614 dag outs, dag ins, string asmstr,
615 list <dag> patterns, InstrItinClass itin>:
616 A64I_LDSTex_stn<size, o2, L, o1, o0, outs, ins, asmstr, patterns, itin>{
618 let Inst{14-10} = Rt2;
621 // Format for load-store register (immediate post-indexed) instructions
622 class A64I_LSpostind<bits<2> size, bit v, bits<2> opc,
623 dag outs, dag ins, string asmstr,
624 list<dag> patterns, InstrItinClass itin>
625 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
628 let Inst{31-30} = size;
629 let Inst{29-27} = 0b111;
631 let Inst{25-24} = 0b00;
632 let Inst{23-22} = opc;
634 let Inst{20-12} = SImm9;
635 let Inst{11-10} = 0b01;
640 // Format for load-store register (immediate pre-indexed) instructions
641 class A64I_LSpreind<bits<2> size, bit v, bits<2> opc,
642 dag outs, dag ins, string asmstr,
643 list<dag> patterns, InstrItinClass itin>
644 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
648 let Inst{31-30} = size;
649 let Inst{29-27} = 0b111;
651 let Inst{25-24} = 0b00;
652 let Inst{23-22} = opc;
654 let Inst{20-12} = SImm9;
655 let Inst{11-10} = 0b11;
660 // Format for load-store register (unprivileged) instructions
661 class A64I_LSunpriv<bits<2> size, bit v, bits<2> opc,
662 dag outs, dag ins, string asmstr,
663 list<dag> patterns, InstrItinClass itin>
664 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
668 let Inst{31-30} = size;
669 let Inst{29-27} = 0b111;
671 let Inst{25-24} = 0b00;
672 let Inst{23-22} = opc;
674 let Inst{20-12} = SImm9;
675 let Inst{11-10} = 0b10;
680 // Format for load-store (unscaled immediate) instructions.
681 class A64I_LSunalimm<bits<2> size, bit v, bits<2> opc,
682 dag outs, dag ins, string asmstr,
683 list<dag> patterns, InstrItinClass itin>
684 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
687 let Inst{31-30} = size;
688 let Inst{29-27} = 0b111;
690 let Inst{25-24} = 0b00;
691 let Inst{23-22} = opc;
693 let Inst{20-12} = SImm9;
694 let Inst{11-10} = 0b00;
700 // Format for load-store (unsigned immediate) instructions.
701 class A64I_LSunsigimm<bits<2> size, bit v, bits<2> opc,
702 dag outs, dag ins, string asmstr,
703 list<dag> patterns, InstrItinClass itin>
704 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
707 let Inst{31-30} = size;
708 let Inst{29-27} = 0b111;
710 let Inst{25-24} = 0b01;
711 let Inst{23-22} = opc;
712 let Inst{21-10} = UImm12;
715 // Format for load-store register (register offset) instructions.
716 class A64I_LSregoff<bits<2> size, bit v, bits<2> opc, bit optionlo,
717 dag outs, dag ins, string asmstr,
718 list<dag> patterns, InstrItinClass itin>
719 : A64InstRtn<outs, ins, asmstr, patterns, itin> {
722 // Complex operand selection needed for these instructions, so they
723 // need an "addr" field for encoding/decoding to be generated.
725 // OptionHi = Ext{2-1}
728 let Inst{31-30} = size;
729 let Inst{29-27} = 0b111;
731 let Inst{25-24} = 0b00;
732 let Inst{23-22} = opc;
734 let Inst{20-16} = Rm;
735 let Inst{15-14} = Ext{2-1};
736 let Inst{13} = optionlo;
737 let Inst{12} = Ext{0};
738 let Inst{11-10} = 0b10;
739 // Inherits Rn in 9-5
740 // Inherits Rt in 4-0
742 let AddedComplexity = 50;
745 // Format for Load-store register pair (offset) instructions
746 class A64I_LSPoffset<bits<2> opc, bit v, bit l,
747 dag outs, dag ins, string asmstr,
748 list<dag> patterns, InstrItinClass itin>
749 : A64InstRtt2n<outs, ins, asmstr, patterns, itin> {
752 let Inst{31-30} = opc;
753 let Inst{29-27} = 0b101;
755 let Inst{25-23} = 0b010;
757 let Inst{21-15} = SImm7;
758 // Inherit Rt2 in 14-10
763 // Format for Load-store register pair (post-indexed) instructions
764 class A64I_LSPpostind<bits<2> opc, bit v, bit l,
765 dag outs, dag ins, string asmstr,
766 list<dag> patterns, InstrItinClass itin>
767 : A64InstRtt2n<outs, ins, asmstr, patterns, itin> {
770 let Inst{31-30} = opc;
771 let Inst{29-27} = 0b101;
773 let Inst{25-23} = 0b001;
775 let Inst{21-15} = SImm7;
776 // Inherit Rt2 in 14-10
781 // Format for Load-store register pair (pre-indexed) instructions
782 class A64I_LSPpreind<bits<2> opc, bit v, bit l,
783 dag outs, dag ins, string asmstr,
784 list<dag> patterns, InstrItinClass itin>
785 : A64InstRtt2n<outs, ins, asmstr, patterns, itin> {
788 let Inst{31-30} = opc;
789 let Inst{29-27} = 0b101;
791 let Inst{25-23} = 0b011;
793 let Inst{21-15} = SImm7;
794 // Inherit Rt2 in 14-10
799 // Format for Load-store non-temporal register pair (offset) instructions
800 class A64I_LSPnontemp<bits<2> opc, bit v, bit l,
801 dag outs, dag ins, string asmstr,
802 list<dag> patterns, InstrItinClass itin>
803 : A64InstRtt2n<outs, ins, asmstr, patterns, itin> {
806 let Inst{31-30} = opc;
807 let Inst{29-27} = 0b101;
809 let Inst{25-23} = 0b000;
811 let Inst{21-15} = SImm7;
812 // Inherit Rt2 in 14-10
817 // Format for Logical (immediate) instructions
818 class A64I_logicalimm<bit sf, bits<2> opc,
819 dag outs, dag ins, string asmstr,
820 list<dag> patterns, InstrItinClass itin>
821 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
826 // N, ImmR and ImmS have no separate existence in any assembly syntax (or for
827 // selection), so we'll combine them into a single field here.
834 let Inst{30-29} = opc;
835 let Inst{28-23} = 0b100100;
836 let Inst{22} = Imm{12};
837 let Inst{21-16} = Imm{11-6};
838 let Inst{15-10} = Imm{5-0};
839 // Rn inherited in 9-5
840 // Rd inherited in 4-0
843 // Format for Logical (shifted register) instructions
844 class A64I_logicalshift<bit sf, bits<2> opc, bits<2> shift, bit N,
845 dag outs, dag ins, string asmstr,
846 list<dag> patterns, InstrItinClass itin>
847 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
851 let Inst{30-29} = opc;
852 let Inst{28-24} = 0b01010;
853 let Inst{23-22} = shift;
856 let Inst{15-10} = Imm6;
861 // Format for Move wide (immediate)
862 class A64I_movw<bit sf, bits<2> opc,
863 dag outs, dag ins, string asmstr,
864 list<dag> patterns, InstrItinClass itin>
865 : A64InstRd<outs, ins, asmstr, patterns, itin> {
867 bits<2> Shift; // Called "hw" officially
870 let Inst{30-29} = opc;
871 let Inst{28-23} = 0b100101;
872 let Inst{22-21} = Shift;
873 let Inst{20-5} = UImm16;
874 // Inherits Rd in 4-0
877 // Format for PC-relative addressing instructions, ADR and ADRP.
878 class A64I_PCADR<bit op,
879 dag outs, dag ins, string asmstr,
880 list<dag> patterns, InstrItinClass itin>
881 : A64InstRd<outs, ins, asmstr, patterns, itin> {
885 let Inst{30-29} = Label{1-0};
886 let Inst{28-24} = 0b10000;
887 let Inst{23-5} = Label{20-2};
890 // Format for system instructions
891 class A64I_system<bit l,
892 dag outs, dag ins, string asmstr,
893 list<dag> patterns, InstrItinClass itin>
894 : A64Inst<outs, ins, asmstr, patterns, itin> {
902 let Inst{31-22} = 0b1101010100;
904 let Inst{20-19} = Op0;
905 let Inst{18-16} = Op1;
906 let Inst{15-12} = CRn;
907 let Inst{11-8} = CRm;
911 // These instructions can do horrible things.
912 let hasSideEffects = 1;
915 // Format for unconditional branch (immediate) instructions
916 class A64I_Bimm<bit op,
917 dag outs, dag ins, string asmstr,
918 list<dag> patterns, InstrItinClass itin>
919 : A64Inst<outs, ins, asmstr, patterns, itin> {
920 // Doubly special in not even sharing register fields with other
921 // instructions, so we create our own Rn here.
925 let Inst{30-26} = 0b00101;
926 let Inst{25-0} = Label;
929 // Format for Test & branch (immediate) instructions
930 class A64I_TBimm<bit op,
931 dag outs, dag ins, string asmstr,
932 list<dag> patterns, InstrItinClass itin>
933 : A64InstRt<outs, ins, asmstr, patterns, itin> {
934 // Doubly special in not even sharing register fields with other
935 // instructions, so we create our own Rn here.
939 let Inst{31} = Imm{5};
940 let Inst{30-25} = 0b011011;
942 let Inst{23-19} = Imm{4-0};
943 let Inst{18-5} = Label;
947 // Format for Unconditional branch (register) instructions, including
948 // RET. Shares no fields with instructions further up the hierarchy
950 class A64I_Breg<bits<4> opc, bits<5> op2, bits<6> op3, bits<5> op4,
951 dag outs, dag ins, string asmstr,
952 list<dag> patterns, InstrItinClass itin>
953 : A64Inst<outs, ins, asmstr, patterns, itin> {
954 // Doubly special in not even sharing register fields with other
955 // instructions, so we create our own Rn here.
958 let Inst{31-25} = 0b1101011;
959 let Inst{24-21} = opc;
960 let Inst{20-16} = op2;
961 let Inst{15-10} = op3;
967 //===----------------------------------------------------------------------===//
969 // Neon Instruction Format Definitions.
972 let Predicates = [HasNEON] in {
974 class NeonInstAlias<string Asm, dag Result, bit Emit = 0b1>
975 : InstAlias<Asm, Result, Emit> {
978 // Format AdvSIMD 3 vector registers with same vector type
979 class NeonI_3VSame<bit q, bit u, bits<2> size, bits<5> opcode,
980 dag outs, dag ins, string asmstr,
981 list<dag> patterns, InstrItinClass itin>
982 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
986 let Inst{28-24} = 0b01110;
987 let Inst{23-22} = size;
989 // Inherit Rm in 20-16
990 let Inst{15-11} = opcode;
996 // Format AdvSIMD 3 vector registers with different vector type
997 class NeonI_3VDiff<bit q, bit u, bits<2> size, bits<4> opcode,
998 dag outs, dag ins, string asmstr,
999 list<dag> patterns, InstrItinClass itin>
1000 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
1004 let Inst{28-24} = 0b01110;
1005 let Inst{23-22} = size;
1007 // Inherit Rm in 20-16
1008 let Inst{15-12} = opcode;
1011 // Inherit Rn in 9-5
1012 // Inherit Rd in 4-0
1015 // Format AdvSIMD two registers and an element
1016 class NeonI_2VElem<bit q, bit u, bits<2> size, bits<4> opcode,
1017 dag outs, dag ins, string asmstr,
1018 list<dag> patterns, InstrItinClass itin>
1019 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
1023 let Inst{28-24} = 0b01111;
1024 let Inst{23-22} = size;
1027 // Inherit Rm in 19-16
1028 let Inst{15-12} = opcode;
1031 // Inherit Rn in 9-5
1032 // Inherit Rd in 4-0
1035 // Format AdvSIMD 1 vector register with modified immediate
1036 class NeonI_1VModImm<bit q, bit op,
1037 dag outs, dag ins, string asmstr,
1038 list<dag> patterns, InstrItinClass itin>
1039 : A64InstRd<outs,ins, asmstr, patterns, itin> {
1045 let Inst{28-19} = 0b0111100000;
1046 let Inst{15-12} = cmode;
1047 let Inst{11} = 0b0; // o2
1049 // Inherit Rd in 4-0
1050 let Inst{18-16} = Imm{7-5}; // imm a:b:c
1051 let Inst{9-5} = Imm{4-0}; // imm d:e:f:g:h
1054 // Format AdvSIMD 3 scalar registers with same type
1056 class NeonI_Scalar3Same<bit u, bits<2> size, bits<5> opcode,
1057 dag outs, dag ins, string asmstr,
1058 list<dag> patterns, InstrItinClass itin>
1059 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
1063 let Inst{28-24} = 0b11110;
1064 let Inst{23-22} = size;
1066 // Inherit Rm in 20-16
1067 let Inst{15-11} = opcode;
1069 // Inherit Rn in 9-5
1070 // Inherit Rd in 4-0
1074 // Format AdvSIMD 2 vector registers miscellaneous
1075 class NeonI_2VMisc<bit q, bit u, bits<2> size, bits<5> opcode,
1076 dag outs, dag ins, string asmstr,
1077 list<dag> patterns, InstrItinClass itin>
1078 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1082 let Inst{28-24} = 0b01110;
1083 let Inst{23-22} = size;
1084 let Inst{21-17} = 0b10000;
1085 let Inst{16-12} = opcode;
1086 let Inst{11-10} = 0b10;
1088 // Inherit Rn in 9-5
1089 // Inherit Rd in 4-0
1092 // Format AdvSIMD 2 vector 1 immediate shift
1093 class NeonI_2VShiftImm<bit q, bit u, bits<5> opcode,
1094 dag outs, dag ins, string asmstr,
1095 list<dag> patterns, InstrItinClass itin>
1096 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1101 let Inst{28-23} = 0b011110;
1102 let Inst{22-16} = Imm;
1103 let Inst{15-11} = opcode;
1106 // Inherit Rn in 9-5
1107 // Inherit Rd in 4-0
1110 // Format AdvSIMD duplicate and insert
1111 class NeonI_copy<bit q, bit op, bits<4> imm4,
1112 dag outs, dag ins, string asmstr,
1113 list<dag> patterns, InstrItinClass itin>
1114 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1119 let Inst{28-21} = 0b01110000;
1120 let Inst{20-16} = Imm5;
1122 let Inst{14-11} = imm4;
1125 // Inherit Rn in 9-5
1126 // Inherit Rd in 4-0
1128 // Format AdvSIMD insert from element to vector
1129 class NeonI_insert<bit q, bit op,
1130 dag outs, dag ins, string asmstr,
1131 list<dag> patterns, InstrItinClass itin>
1132 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1138 let Inst{28-21} = 0b01110000;
1139 let Inst{20-16} = Imm5;
1141 let Inst{14-11} = Imm4;
1144 // Inherit Rn in 9-5
1145 // Inherit Rd in 4-0
1148 // Format AdvSIMD scalar pairwise
1149 class NeonI_ScalarPair<bit u, bits<2> size, bits<5> opcode,
1150 dag outs, dag ins, string asmstr,
1151 list<dag> patterns, InstrItinClass itin>
1152 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1156 let Inst{28-24} = 0b11110;
1157 let Inst{23-22} = size;
1158 let Inst{21-17} = 0b11000;
1159 let Inst{16-12} = opcode;
1160 let Inst{11-10} = 0b10;
1162 // Inherit Rn in 9-5
1163 // Inherit Rd in 4-0
1166 // Format AdvSIMD 2 vector across lanes
1167 class NeonI_2VAcross<bit q, bit u, bits<2> size, bits<5> opcode,
1168 dag outs, dag ins, string asmstr,
1169 list<dag> patterns, InstrItinClass itin>
1170 : A64InstRdn<outs, ins, asmstr, patterns, itin>
1175 let Inst{28-24} = 0b01110;
1176 let Inst{23-22} = size;
1177 let Inst{21-17} = 0b11000;
1178 let Inst{16-12} = opcode;
1179 let Inst{11-10} = 0b10;
1181 // Inherit Rn in 9-5
1182 // Inherit Rd in 4-0
1185 // Format AdvSIMD scalar two registers miscellaneous
1186 class NeonI_Scalar2SameMisc<bit u, bits<2> size, bits<5> opcode, dag outs, dag ins,
1187 string asmstr, list<dag> patterns, InstrItinClass itin>
1188 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1192 let Inst{28-24} = 0b11110;
1193 let Inst{23-22} = size;
1194 let Inst{21-17} = 0b10000;
1195 let Inst{16-12} = opcode;
1196 let Inst{11-10} = 0b10;
1197 // Inherit Rn in 9-5
1198 // Inherit Rd in 4-0
1201 // Format AdvSIMD vector load/store multiple N-element structure
1202 class NeonI_LdStMult<bit q, bit l, bits<4> opcode, bits<2> size,
1203 dag outs, dag ins, string asmstr,
1204 list<dag> patterns, InstrItinClass itin>
1205 : A64InstRtn<outs, ins, asmstr, patterns, itin>
1209 let Inst{29-23} = 0b0011000;
1211 let Inst{21-16} = 0b000000;
1212 let Inst{15-12} = opcode;
1213 let Inst{11-10} = size;
1215 // Inherit Rn in 9-5
1216 // Inherit Rt in 4-0
1219 // Format AdvSIMD 3 scalar registers with different type
1221 class NeonI_Scalar3Diff<bit u, bits<2> size, bits<4> opcode,
1222 dag outs, dag ins, string asmstr,
1223 list<dag> patterns, InstrItinClass itin>
1224 : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
1225 let Inst{31-30} = 0b01;
1227 let Inst{28-24} = 0b11110;
1228 let Inst{23-22} = size;
1230 // Inherit Rm in 20-16
1231 let Inst{15-12} = opcode;
1232 let Inst{11-10} = 0b00;
1233 // Inherit Rn in 9-5
1234 // Inherit Rd in 4-0
1237 // Format AdvSIMD scalar shift by immediate
1239 class NeonI_ScalarShiftImm<bit u, bits<5> opcode,
1240 dag outs, dag ins, string asmstr,
1241 list<dag> patterns, InstrItinClass itin>
1242 : A64InstRdn<outs, ins, asmstr, patterns, itin> {
1245 let Inst{31-30} = 0b01;
1247 let Inst{28-23} = 0b111110;
1248 let Inst{22-19} = Imm4;
1249 let Inst{18-16} = Imm3;
1250 let Inst{15-11} = opcode;
1252 // Inherit Rn in 9-5
1253 // Inherit Rd in 4-0