1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "aarch64-isel"
17 #include "AArch64ISelLowering.h"
18 #include "AArch64MachineFunctionInfo.h"
19 #include "AArch64TargetMachine.h"
20 #include "AArch64TargetObjectFile.h"
21 #include "Utils/AArch64BaseInfo.h"
22 #include "llvm/CodeGen/Analysis.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/CallingConv.h"
32 static TargetLoweringObjectFile *createTLOF(AArch64TargetMachine &TM) {
33 assert (TM.getSubtarget<AArch64Subtarget>().isTargetELF() &&
34 "unknown subtarget type");
35 return new AArch64ElfTargetObjectFile();
38 AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
39 : TargetLowering(TM, createTLOF(TM)), Itins(TM.getInstrItineraryData()) {
41 const AArch64Subtarget *Subtarget = &TM.getSubtarget<AArch64Subtarget>();
43 // SIMD compares set the entire lane's bits to 1
44 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
46 // Scalar register <-> type mapping
47 addRegisterClass(MVT::i32, &AArch64::GPR32RegClass);
48 addRegisterClass(MVT::i64, &AArch64::GPR64RegClass);
50 if (Subtarget->hasFPARMv8()) {
51 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
52 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
53 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
54 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
57 if (Subtarget->hasNEON()) {
59 addRegisterClass(MVT::v1i8, &AArch64::FPR8RegClass);
60 addRegisterClass(MVT::v1i16, &AArch64::FPR16RegClass);
61 addRegisterClass(MVT::v1i32, &AArch64::FPR32RegClass);
62 addRegisterClass(MVT::v1i64, &AArch64::FPR64RegClass);
63 addRegisterClass(MVT::v1f64, &AArch64::FPR64RegClass);
64 addRegisterClass(MVT::v8i8, &AArch64::FPR64RegClass);
65 addRegisterClass(MVT::v4i16, &AArch64::FPR64RegClass);
66 addRegisterClass(MVT::v2i32, &AArch64::FPR64RegClass);
67 addRegisterClass(MVT::v1i64, &AArch64::FPR64RegClass);
68 addRegisterClass(MVT::v2f32, &AArch64::FPR64RegClass);
69 addRegisterClass(MVT::v16i8, &AArch64::FPR128RegClass);
70 addRegisterClass(MVT::v8i16, &AArch64::FPR128RegClass);
71 addRegisterClass(MVT::v4i32, &AArch64::FPR128RegClass);
72 addRegisterClass(MVT::v2i64, &AArch64::FPR128RegClass);
73 addRegisterClass(MVT::v4f32, &AArch64::FPR128RegClass);
74 addRegisterClass(MVT::v2f64, &AArch64::FPR128RegClass);
77 computeRegisterProperties();
79 // We combine OR nodes for bitfield and NEON BSL operations.
80 setTargetDAGCombine(ISD::OR);
82 setTargetDAGCombine(ISD::AND);
83 setTargetDAGCombine(ISD::SRA);
84 setTargetDAGCombine(ISD::SRL);
85 setTargetDAGCombine(ISD::SHL);
87 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
88 setTargetDAGCombine(ISD::INTRINSIC_VOID);
89 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
91 // AArch64 does not have i1 loads, or much of anything for i1 really.
92 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
93 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
94 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
96 setStackPointerRegisterToSaveRestore(AArch64::XSP);
97 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
98 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
99 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
101 // We'll lower globals to wrappers for selection.
102 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
103 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
105 // A64 instructions have the comparison predicate attached to the user of the
106 // result, but having a separate comparison is valuable for matching.
107 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
108 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
109 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
110 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
112 setOperationAction(ISD::SELECT, MVT::i32, Custom);
113 setOperationAction(ISD::SELECT, MVT::i64, Custom);
114 setOperationAction(ISD::SELECT, MVT::f32, Custom);
115 setOperationAction(ISD::SELECT, MVT::f64, Custom);
117 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
118 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
119 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
120 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
122 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
124 setOperationAction(ISD::SETCC, MVT::i32, Custom);
125 setOperationAction(ISD::SETCC, MVT::i64, Custom);
126 setOperationAction(ISD::SETCC, MVT::f32, Custom);
127 setOperationAction(ISD::SETCC, MVT::f64, Custom);
129 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
130 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
131 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
133 setOperationAction(ISD::VASTART, MVT::Other, Custom);
134 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
135 setOperationAction(ISD::VAEND, MVT::Other, Expand);
136 setOperationAction(ISD::VAARG, MVT::Other, Expand);
138 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
139 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
141 setOperationAction(ISD::ROTL, MVT::i32, Expand);
142 setOperationAction(ISD::ROTL, MVT::i64, Expand);
144 setOperationAction(ISD::UREM, MVT::i32, Expand);
145 setOperationAction(ISD::UREM, MVT::i64, Expand);
146 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
147 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
149 setOperationAction(ISD::SREM, MVT::i32, Expand);
150 setOperationAction(ISD::SREM, MVT::i64, Expand);
151 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
152 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
154 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
157 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
159 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
160 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
162 // Legal floating-point operations.
163 setOperationAction(ISD::FABS, MVT::f32, Legal);
164 setOperationAction(ISD::FABS, MVT::f64, Legal);
166 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
167 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
169 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
170 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
172 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
173 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
175 setOperationAction(ISD::FNEG, MVT::f32, Legal);
176 setOperationAction(ISD::FNEG, MVT::f64, Legal);
178 setOperationAction(ISD::FRINT, MVT::f32, Legal);
179 setOperationAction(ISD::FRINT, MVT::f64, Legal);
181 setOperationAction(ISD::FSQRT, MVT::f32, Legal);
182 setOperationAction(ISD::FSQRT, MVT::f64, Legal);
184 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
185 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
187 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
188 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
189 setOperationAction(ISD::ConstantFP, MVT::f128, Legal);
191 // Illegal floating-point operations.
192 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
195 setOperationAction(ISD::FCOS, MVT::f32, Expand);
196 setOperationAction(ISD::FCOS, MVT::f64, Expand);
198 setOperationAction(ISD::FEXP, MVT::f32, Expand);
199 setOperationAction(ISD::FEXP, MVT::f64, Expand);
201 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
202 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
204 setOperationAction(ISD::FLOG, MVT::f32, Expand);
205 setOperationAction(ISD::FLOG, MVT::f64, Expand);
207 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
208 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
210 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
211 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
213 setOperationAction(ISD::FPOW, MVT::f32, Expand);
214 setOperationAction(ISD::FPOW, MVT::f64, Expand);
216 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
217 setOperationAction(ISD::FPOWI, MVT::f64, Expand);
219 setOperationAction(ISD::FREM, MVT::f32, Expand);
220 setOperationAction(ISD::FREM, MVT::f64, Expand);
222 setOperationAction(ISD::FSIN, MVT::f32, Expand);
223 setOperationAction(ISD::FSIN, MVT::f64, Expand);
225 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
226 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
228 // Virtually no operation on f128 is legal, but LLVM can't expand them when
229 // there's a valid register class, so we need custom operations in most cases.
230 setOperationAction(ISD::FABS, MVT::f128, Expand);
231 setOperationAction(ISD::FADD, MVT::f128, Custom);
232 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
233 setOperationAction(ISD::FCOS, MVT::f128, Expand);
234 setOperationAction(ISD::FDIV, MVT::f128, Custom);
235 setOperationAction(ISD::FMA, MVT::f128, Expand);
236 setOperationAction(ISD::FMUL, MVT::f128, Custom);
237 setOperationAction(ISD::FNEG, MVT::f128, Expand);
238 setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand);
239 setOperationAction(ISD::FP_ROUND, MVT::f128, Expand);
240 setOperationAction(ISD::FPOW, MVT::f128, Expand);
241 setOperationAction(ISD::FREM, MVT::f128, Expand);
242 setOperationAction(ISD::FRINT, MVT::f128, Expand);
243 setOperationAction(ISD::FSIN, MVT::f128, Expand);
244 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
245 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
246 setOperationAction(ISD::FSUB, MVT::f128, Custom);
247 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
248 setOperationAction(ISD::SETCC, MVT::f128, Custom);
249 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
250 setOperationAction(ISD::SELECT, MVT::f128, Expand);
251 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
252 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
254 // Lowering for many of the conversions is actually specified by the non-f128
255 // type. The LowerXXX function will be trivial when f128 isn't involved.
256 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
257 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
258 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
259 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
260 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
261 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
262 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
263 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
264 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
265 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
266 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
267 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
268 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
269 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
271 // This prevents LLVM trying to compress double constants into a floating
272 // constant-pool entry and trying to load from there. It's of doubtful benefit
273 // for A64: we'd need LDR followed by FCVT, I believe.
274 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
275 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
276 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
278 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
279 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
280 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
281 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
282 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
283 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
285 setExceptionPointerRegister(AArch64::X0);
286 setExceptionSelectorRegister(AArch64::X1);
288 if (Subtarget->hasNEON()) {
289 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i8, Expand);
290 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
291 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand);
292 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v1i64, Expand);
293 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v16i8, Expand);
294 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Expand);
295 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Expand);
296 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Expand);
298 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i8, Custom);
299 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
300 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
301 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i16, Custom);
302 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
303 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
304 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i32, Custom);
305 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
306 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
307 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
308 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
309 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
310 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
311 setOperationAction(ISD::BUILD_VECTOR, MVT::v1f64, Custom);
312 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
314 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
315 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
316 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
317 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i16, Custom);
318 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
319 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i32, Custom);
320 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
321 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
322 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f32, Custom);
323 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
324 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1f64, Custom);
325 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
327 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i32, Legal);
328 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Legal);
329 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Legal);
330 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Legal);
331 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Legal);
332 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Legal);
333 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Legal);
335 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i8, Custom);
336 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i16, Custom);
337 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
338 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
339 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
341 setOperationAction(ISD::SETCC, MVT::v8i8, Custom);
342 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
343 setOperationAction(ISD::SETCC, MVT::v4i16, Custom);
344 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
345 setOperationAction(ISD::SETCC, MVT::v2i32, Custom);
346 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
347 setOperationAction(ISD::SETCC, MVT::v1i64, Custom);
348 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
349 setOperationAction(ISD::SETCC, MVT::v2f32, Custom);
350 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
351 setOperationAction(ISD::SETCC, MVT::v1f64, Custom);
352 setOperationAction(ISD::SETCC, MVT::v2f64, Custom);
354 setOperationAction(ISD::FFLOOR, MVT::v2f32, Legal);
355 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
356 setOperationAction(ISD::FFLOOR, MVT::v1f64, Legal);
357 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
359 setOperationAction(ISD::FCEIL, MVT::v2f32, Legal);
360 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
361 setOperationAction(ISD::FCEIL, MVT::v1f64, Legal);
362 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
364 setOperationAction(ISD::FTRUNC, MVT::v2f32, Legal);
365 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
366 setOperationAction(ISD::FTRUNC, MVT::v1f64, Legal);
367 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
369 setOperationAction(ISD::FRINT, MVT::v2f32, Legal);
370 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
371 setOperationAction(ISD::FRINT, MVT::v1f64, Legal);
372 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
374 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Legal);
375 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
376 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Legal);
377 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
379 setOperationAction(ISD::FROUND, MVT::v2f32, Legal);
380 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
381 setOperationAction(ISD::FROUND, MVT::v1f64, Legal);
382 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
384 setOperationAction(ISD::SINT_TO_FP, MVT::v1i8, Custom);
385 setOperationAction(ISD::SINT_TO_FP, MVT::v1i16, Custom);
386 setOperationAction(ISD::SINT_TO_FP, MVT::v1i32, Custom);
387 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
388 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
389 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
391 setOperationAction(ISD::UINT_TO_FP, MVT::v1i8, Custom);
392 setOperationAction(ISD::UINT_TO_FP, MVT::v1i16, Custom);
393 setOperationAction(ISD::UINT_TO_FP, MVT::v1i32, Custom);
394 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
395 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
396 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
398 setOperationAction(ISD::FP_TO_SINT, MVT::v1i8, Custom);
399 setOperationAction(ISD::FP_TO_SINT, MVT::v1i16, Custom);
400 setOperationAction(ISD::FP_TO_SINT, MVT::v1i32, Custom);
401 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
402 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
403 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Custom);
405 setOperationAction(ISD::FP_TO_UINT, MVT::v1i8, Custom);
406 setOperationAction(ISD::FP_TO_UINT, MVT::v1i16, Custom);
407 setOperationAction(ISD::FP_TO_UINT, MVT::v1i32, Custom);
408 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
409 setOperationAction(ISD::FP_TO_UINT, MVT::v2i32, Custom);
410 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Custom);
412 // Neon does not support vector divide/remainder operations except
413 // floating-point divide.
414 setOperationAction(ISD::SDIV, MVT::v1i8, Expand);
415 setOperationAction(ISD::SDIV, MVT::v8i8, Expand);
416 setOperationAction(ISD::SDIV, MVT::v16i8, Expand);
417 setOperationAction(ISD::SDIV, MVT::v1i16, Expand);
418 setOperationAction(ISD::SDIV, MVT::v4i16, Expand);
419 setOperationAction(ISD::SDIV, MVT::v8i16, Expand);
420 setOperationAction(ISD::SDIV, MVT::v1i32, Expand);
421 setOperationAction(ISD::SDIV, MVT::v2i32, Expand);
422 setOperationAction(ISD::SDIV, MVT::v4i32, Expand);
423 setOperationAction(ISD::SDIV, MVT::v1i64, Expand);
424 setOperationAction(ISD::SDIV, MVT::v2i64, Expand);
426 setOperationAction(ISD::UDIV, MVT::v1i8, Expand);
427 setOperationAction(ISD::UDIV, MVT::v8i8, Expand);
428 setOperationAction(ISD::UDIV, MVT::v16i8, Expand);
429 setOperationAction(ISD::UDIV, MVT::v1i16, Expand);
430 setOperationAction(ISD::UDIV, MVT::v4i16, Expand);
431 setOperationAction(ISD::UDIV, MVT::v8i16, Expand);
432 setOperationAction(ISD::UDIV, MVT::v1i32, Expand);
433 setOperationAction(ISD::UDIV, MVT::v2i32, Expand);
434 setOperationAction(ISD::UDIV, MVT::v4i32, Expand);
435 setOperationAction(ISD::UDIV, MVT::v1i64, Expand);
436 setOperationAction(ISD::UDIV, MVT::v2i64, Expand);
438 setOperationAction(ISD::SREM, MVT::v1i8, Expand);
439 setOperationAction(ISD::SREM, MVT::v8i8, Expand);
440 setOperationAction(ISD::SREM, MVT::v16i8, Expand);
441 setOperationAction(ISD::SREM, MVT::v1i16, Expand);
442 setOperationAction(ISD::SREM, MVT::v4i16, Expand);
443 setOperationAction(ISD::SREM, MVT::v8i16, Expand);
444 setOperationAction(ISD::SREM, MVT::v1i32, Expand);
445 setOperationAction(ISD::SREM, MVT::v2i32, Expand);
446 setOperationAction(ISD::SREM, MVT::v4i32, Expand);
447 setOperationAction(ISD::SREM, MVT::v1i64, Expand);
448 setOperationAction(ISD::SREM, MVT::v2i64, Expand);
450 setOperationAction(ISD::UREM, MVT::v1i8, Expand);
451 setOperationAction(ISD::UREM, MVT::v8i8, Expand);
452 setOperationAction(ISD::UREM, MVT::v16i8, Expand);
453 setOperationAction(ISD::UREM, MVT::v1i16, Expand);
454 setOperationAction(ISD::UREM, MVT::v4i16, Expand);
455 setOperationAction(ISD::UREM, MVT::v8i16, Expand);
456 setOperationAction(ISD::UREM, MVT::v1i32, Expand);
457 setOperationAction(ISD::UREM, MVT::v2i32, Expand);
458 setOperationAction(ISD::UREM, MVT::v4i32, Expand);
459 setOperationAction(ISD::UREM, MVT::v1i64, Expand);
460 setOperationAction(ISD::UREM, MVT::v2i64, Expand);
462 setOperationAction(ISD::FREM, MVT::v2f32, Expand);
463 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
464 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
465 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
467 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
468 setOperationAction(ISD::SELECT, MVT::v16i8, Expand);
469 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
470 setOperationAction(ISD::SELECT, MVT::v8i16, Expand);
471 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
472 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
473 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
474 setOperationAction(ISD::SELECT, MVT::v2i64, Expand);
475 setOperationAction(ISD::SELECT, MVT::v2f32, Expand);
476 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
477 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
478 setOperationAction(ISD::SELECT, MVT::v2f64, Expand);
480 setOperationAction(ISD::SELECT_CC, MVT::v8i8, Custom);
481 setOperationAction(ISD::SELECT_CC, MVT::v16i8, Custom);
482 setOperationAction(ISD::SELECT_CC, MVT::v4i16, Custom);
483 setOperationAction(ISD::SELECT_CC, MVT::v8i16, Custom);
484 setOperationAction(ISD::SELECT_CC, MVT::v2i32, Custom);
485 setOperationAction(ISD::SELECT_CC, MVT::v4i32, Custom);
486 setOperationAction(ISD::SELECT_CC, MVT::v1i64, Custom);
487 setOperationAction(ISD::SELECT_CC, MVT::v2i64, Custom);
488 setOperationAction(ISD::SELECT_CC, MVT::v2f32, Custom);
489 setOperationAction(ISD::SELECT_CC, MVT::v4f32, Custom);
490 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Custom);
491 setOperationAction(ISD::SELECT_CC, MVT::v2f64, Custom);
493 // Vector ExtLoad and TruncStore are expanded.
494 for (unsigned I = MVT::FIRST_VECTOR_VALUETYPE;
495 I <= MVT::LAST_VECTOR_VALUETYPE; ++I) {
496 MVT VT = (MVT::SimpleValueType) I;
497 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
498 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
499 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
500 for (unsigned II = MVT::FIRST_VECTOR_VALUETYPE;
501 II <= MVT::LAST_VECTOR_VALUETYPE; ++II) {
502 MVT VT1 = (MVT::SimpleValueType) II;
503 // A TruncStore has two vector types of the same number of elements
504 // and different element sizes.
505 if (VT.getVectorNumElements() == VT1.getVectorNumElements() &&
506 VT.getVectorElementType().getSizeInBits()
507 > VT1.getVectorElementType().getSizeInBits())
508 setTruncStoreAction(VT, VT1, Expand);
512 // There is no v1i64/v2i64 multiply, expand v1i64/v2i64 to GPR i64 multiply.
513 // FIXME: For a v2i64 multiply, we copy VPR to GPR and do 2 i64 multiplies,
514 // and then copy back to VPR. This solution may be optimized by Following 3
515 // NEON instructions:
516 // pmull v2.1q, v0.1d, v1.1d
517 // pmull2 v3.1q, v0.2d, v1.2d
518 // ins v2.d[1], v3.d[0]
519 // As currently we can't verify the correctness of such assumption, we can
520 // do such optimization in the future.
521 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
522 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
525 setTargetDAGCombine(ISD::SETCC);
526 setTargetDAGCombine(ISD::SIGN_EXTEND);
527 setTargetDAGCombine(ISD::VSELECT);
530 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
531 // It's reasonably important that this value matches the "natural" legal
532 // promotion from i1 for scalar types. Otherwise LegalizeTypes can get itself
533 // in a twist (e.g. inserting an any_extend which then becomes i64 -> i64).
534 if (!VT.isVector()) return MVT::i32;
535 return VT.changeVectorElementTypeToInteger();
538 static void getExclusiveOperation(unsigned Size, AtomicOrdering Ord,
541 static const unsigned LoadBares[] = {AArch64::LDXR_byte, AArch64::LDXR_hword,
542 AArch64::LDXR_word, AArch64::LDXR_dword};
543 static const unsigned LoadAcqs[] = {AArch64::LDAXR_byte, AArch64::LDAXR_hword,
544 AArch64::LDAXR_word, AArch64::LDAXR_dword};
545 static const unsigned StoreBares[] = {AArch64::STXR_byte, AArch64::STXR_hword,
546 AArch64::STXR_word, AArch64::STXR_dword};
547 static const unsigned StoreRels[] = {AArch64::STLXR_byte,AArch64::STLXR_hword,
548 AArch64::STLXR_word, AArch64::STLXR_dword};
550 const unsigned *LoadOps, *StoreOps;
551 if (Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent)
556 if (Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent)
557 StoreOps = StoreRels;
559 StoreOps = StoreBares;
561 assert(isPowerOf2_32(Size) && Size <= 8 &&
562 "unsupported size for atomic binary op!");
564 LdrOpc = LoadOps[Log2_32(Size)];
565 StrOpc = StoreOps[Log2_32(Size)];
568 // FIXME: AArch64::DTripleRegClass and AArch64::QTripleRegClass don't really
569 // have value type mapped, and they are both being defined as MVT::untyped.
570 // Without knowing the MVT type, MachineLICM::getRegisterClassIDAndCost
571 // would fail to figure out the register pressure correctly.
572 std::pair<const TargetRegisterClass*, uint8_t>
573 AArch64TargetLowering::findRepresentativeClass(MVT VT) const{
574 const TargetRegisterClass *RRC = 0;
576 switch (VT.SimpleTy) {
578 return TargetLowering::findRepresentativeClass(VT);
580 RRC = &AArch64::QPairRegClass;
584 RRC = &AArch64::QQuadRegClass;
588 return std::make_pair(RRC, Cost);
592 AArch64TargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
594 unsigned BinOpcode) const {
595 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
596 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
598 const BasicBlock *LLVM_BB = BB->getBasicBlock();
599 MachineFunction *MF = BB->getParent();
600 MachineFunction::iterator It = BB;
603 unsigned dest = MI->getOperand(0).getReg();
604 unsigned ptr = MI->getOperand(1).getReg();
605 unsigned incr = MI->getOperand(2).getReg();
606 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm());
607 DebugLoc dl = MI->getDebugLoc();
609 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
611 unsigned ldrOpc, strOpc;
612 getExclusiveOperation(Size, Ord, ldrOpc, strOpc);
614 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
615 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
616 MF->insert(It, loopMBB);
617 MF->insert(It, exitMBB);
619 // Transfer the remainder of BB and its successor edges to exitMBB.
620 exitMBB->splice(exitMBB->begin(), BB,
621 llvm::next(MachineBasicBlock::iterator(MI)),
623 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
625 const TargetRegisterClass *TRC
626 = Size == 8 ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
627 unsigned scratch = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
631 // fallthrough --> loopMBB
632 BB->addSuccessor(loopMBB);
636 // <binop> scratch, dest, incr
637 // stxr stxr_status, scratch, ptr
638 // cbnz stxr_status, loopMBB
639 // fallthrough --> exitMBB
641 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
643 // All arithmetic operations we'll be creating are designed to take an extra
644 // shift or extend operand, which we can conveniently set to zero.
646 // Operand order needs to go the other way for NAND.
647 if (BinOpcode == AArch64::BICwww_lsl || BinOpcode == AArch64::BICxxx_lsl)
648 BuildMI(BB, dl, TII->get(BinOpcode), scratch)
649 .addReg(incr).addReg(dest).addImm(0);
651 BuildMI(BB, dl, TII->get(BinOpcode), scratch)
652 .addReg(dest).addReg(incr).addImm(0);
655 // From the stxr, the register is GPR32; from the cmp it's GPR32wsp
656 unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
657 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
659 BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(scratch).addReg(ptr);
660 BuildMI(BB, dl, TII->get(AArch64::CBNZw))
661 .addReg(stxr_status).addMBB(loopMBB);
663 BB->addSuccessor(loopMBB);
664 BB->addSuccessor(exitMBB);
670 MI->eraseFromParent(); // The instruction is gone now.
676 AArch64TargetLowering::emitAtomicBinaryMinMax(MachineInstr *MI,
677 MachineBasicBlock *BB,
680 A64CC::CondCodes Cond) const {
681 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
683 const BasicBlock *LLVM_BB = BB->getBasicBlock();
684 MachineFunction *MF = BB->getParent();
685 MachineFunction::iterator It = BB;
688 unsigned dest = MI->getOperand(0).getReg();
689 unsigned ptr = MI->getOperand(1).getReg();
690 unsigned incr = MI->getOperand(2).getReg();
691 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm());
693 unsigned oldval = dest;
694 DebugLoc dl = MI->getDebugLoc();
696 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
697 const TargetRegisterClass *TRC, *TRCsp;
699 TRC = &AArch64::GPR64RegClass;
700 TRCsp = &AArch64::GPR64xspRegClass;
702 TRC = &AArch64::GPR32RegClass;
703 TRCsp = &AArch64::GPR32wspRegClass;
706 unsigned ldrOpc, strOpc;
707 getExclusiveOperation(Size, Ord, ldrOpc, strOpc);
709 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
710 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
711 MF->insert(It, loopMBB);
712 MF->insert(It, exitMBB);
714 // Transfer the remainder of BB and its successor edges to exitMBB.
715 exitMBB->splice(exitMBB->begin(), BB,
716 llvm::next(MachineBasicBlock::iterator(MI)),
718 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
720 unsigned scratch = MRI.createVirtualRegister(TRC);
721 MRI.constrainRegClass(scratch, TRCsp);
725 // fallthrough --> loopMBB
726 BB->addSuccessor(loopMBB);
730 // cmp incr, dest (, sign extend if necessary)
731 // csel scratch, dest, incr, cond
732 // stxr stxr_status, scratch, ptr
733 // cbnz stxr_status, loopMBB
734 // fallthrough --> exitMBB
736 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
738 // Build compare and cmov instructions.
739 MRI.constrainRegClass(incr, TRCsp);
740 BuildMI(BB, dl, TII->get(CmpOp))
741 .addReg(incr).addReg(oldval).addImm(0);
743 BuildMI(BB, dl, TII->get(Size == 8 ? AArch64::CSELxxxc : AArch64::CSELwwwc),
745 .addReg(oldval).addReg(incr).addImm(Cond);
747 unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
748 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
750 BuildMI(BB, dl, TII->get(strOpc), stxr_status)
751 .addReg(scratch).addReg(ptr);
752 BuildMI(BB, dl, TII->get(AArch64::CBNZw))
753 .addReg(stxr_status).addMBB(loopMBB);
755 BB->addSuccessor(loopMBB);
756 BB->addSuccessor(exitMBB);
762 MI->eraseFromParent(); // The instruction is gone now.
768 AArch64TargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
769 MachineBasicBlock *BB,
770 unsigned Size) const {
771 unsigned dest = MI->getOperand(0).getReg();
772 unsigned ptr = MI->getOperand(1).getReg();
773 unsigned oldval = MI->getOperand(2).getReg();
774 unsigned newval = MI->getOperand(3).getReg();
775 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(4).getImm());
776 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
777 DebugLoc dl = MI->getDebugLoc();
779 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
780 const TargetRegisterClass *TRCsp;
781 TRCsp = Size == 8 ? &AArch64::GPR64xspRegClass : &AArch64::GPR32wspRegClass;
783 unsigned ldrOpc, strOpc;
784 getExclusiveOperation(Size, Ord, ldrOpc, strOpc);
786 MachineFunction *MF = BB->getParent();
787 const BasicBlock *LLVM_BB = BB->getBasicBlock();
788 MachineFunction::iterator It = BB;
789 ++It; // insert the new blocks after the current block
791 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
792 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
793 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
794 MF->insert(It, loop1MBB);
795 MF->insert(It, loop2MBB);
796 MF->insert(It, exitMBB);
798 // Transfer the remainder of BB and its successor edges to exitMBB.
799 exitMBB->splice(exitMBB->begin(), BB,
800 llvm::next(MachineBasicBlock::iterator(MI)),
802 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
806 // fallthrough --> loop1MBB
807 BB->addSuccessor(loop1MBB);
814 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
816 unsigned CmpOp = Size == 8 ? AArch64::CMPxx_lsl : AArch64::CMPww_lsl;
817 MRI.constrainRegClass(dest, TRCsp);
818 BuildMI(BB, dl, TII->get(CmpOp))
819 .addReg(dest).addReg(oldval).addImm(0);
820 BuildMI(BB, dl, TII->get(AArch64::Bcc))
821 .addImm(A64CC::NE).addMBB(exitMBB);
822 BB->addSuccessor(loop2MBB);
823 BB->addSuccessor(exitMBB);
826 // strex stxr_status, newval, [ptr]
827 // cbnz stxr_status, loop1MBB
829 unsigned stxr_status = MRI.createVirtualRegister(&AArch64::GPR32RegClass);
830 MRI.constrainRegClass(stxr_status, &AArch64::GPR32wspRegClass);
832 BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(newval).addReg(ptr);
833 BuildMI(BB, dl, TII->get(AArch64::CBNZw))
834 .addReg(stxr_status).addMBB(loop1MBB);
835 BB->addSuccessor(loop1MBB);
836 BB->addSuccessor(exitMBB);
842 MI->eraseFromParent(); // The instruction is gone now.
848 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
849 MachineBasicBlock *MBB) const {
850 // We materialise the F128CSEL pseudo-instruction using conditional branches
851 // and loads, giving an instruciton sequence like:
860 // Using virtual registers would probably not be beneficial since COPY
861 // instructions are expensive for f128 (there's no actual instruction to
864 // An alternative would be to do an integer-CSEL on some address. E.g.:
869 // csel x0, x0, x1, ne
872 // It's unclear which approach is actually optimal.
873 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
874 MachineFunction *MF = MBB->getParent();
875 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
876 DebugLoc DL = MI->getDebugLoc();
877 MachineFunction::iterator It = MBB;
880 unsigned DestReg = MI->getOperand(0).getReg();
881 unsigned IfTrueReg = MI->getOperand(1).getReg();
882 unsigned IfFalseReg = MI->getOperand(2).getReg();
883 unsigned CondCode = MI->getOperand(3).getImm();
884 bool NZCVKilled = MI->getOperand(4).isKill();
886 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
887 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
888 MF->insert(It, TrueBB);
889 MF->insert(It, EndBB);
891 // Transfer rest of current basic-block to EndBB
892 EndBB->splice(EndBB->begin(), MBB,
893 llvm::next(MachineBasicBlock::iterator(MI)),
895 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
897 // We need somewhere to store the f128 value needed.
898 int ScratchFI = MF->getFrameInfo()->CreateSpillStackObject(16, 16);
900 // [... start of incoming MBB ...]
901 // str qIFFALSE, [sp]
904 BuildMI(MBB, DL, TII->get(AArch64::LSFP128_STR))
906 .addFrameIndex(ScratchFI)
908 BuildMI(MBB, DL, TII->get(AArch64::Bcc))
911 BuildMI(MBB, DL, TII->get(AArch64::Bimm))
913 MBB->addSuccessor(TrueBB);
914 MBB->addSuccessor(EndBB);
917 // NZCV is live-through TrueBB.
918 TrueBB->addLiveIn(AArch64::NZCV);
919 EndBB->addLiveIn(AArch64::NZCV);
924 BuildMI(TrueBB, DL, TII->get(AArch64::LSFP128_STR))
926 .addFrameIndex(ScratchFI)
929 // Note: fallthrough. We can rely on LLVM adding a branch if it reorders the
931 TrueBB->addSuccessor(EndBB);
935 // [... rest of incoming MBB ...]
936 MachineInstr *StartOfEnd = EndBB->begin();
937 BuildMI(*EndBB, StartOfEnd, DL, TII->get(AArch64::LSFP128_LDR), DestReg)
938 .addFrameIndex(ScratchFI)
941 MI->eraseFromParent();
946 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
947 MachineBasicBlock *MBB) const {
948 switch (MI->getOpcode()) {
949 default: llvm_unreachable("Unhandled instruction with custom inserter");
950 case AArch64::F128CSEL:
951 return EmitF128CSEL(MI, MBB);
952 case AArch64::ATOMIC_LOAD_ADD_I8:
953 return emitAtomicBinary(MI, MBB, 1, AArch64::ADDwww_lsl);
954 case AArch64::ATOMIC_LOAD_ADD_I16:
955 return emitAtomicBinary(MI, MBB, 2, AArch64::ADDwww_lsl);
956 case AArch64::ATOMIC_LOAD_ADD_I32:
957 return emitAtomicBinary(MI, MBB, 4, AArch64::ADDwww_lsl);
958 case AArch64::ATOMIC_LOAD_ADD_I64:
959 return emitAtomicBinary(MI, MBB, 8, AArch64::ADDxxx_lsl);
961 case AArch64::ATOMIC_LOAD_SUB_I8:
962 return emitAtomicBinary(MI, MBB, 1, AArch64::SUBwww_lsl);
963 case AArch64::ATOMIC_LOAD_SUB_I16:
964 return emitAtomicBinary(MI, MBB, 2, AArch64::SUBwww_lsl);
965 case AArch64::ATOMIC_LOAD_SUB_I32:
966 return emitAtomicBinary(MI, MBB, 4, AArch64::SUBwww_lsl);
967 case AArch64::ATOMIC_LOAD_SUB_I64:
968 return emitAtomicBinary(MI, MBB, 8, AArch64::SUBxxx_lsl);
970 case AArch64::ATOMIC_LOAD_AND_I8:
971 return emitAtomicBinary(MI, MBB, 1, AArch64::ANDwww_lsl);
972 case AArch64::ATOMIC_LOAD_AND_I16:
973 return emitAtomicBinary(MI, MBB, 2, AArch64::ANDwww_lsl);
974 case AArch64::ATOMIC_LOAD_AND_I32:
975 return emitAtomicBinary(MI, MBB, 4, AArch64::ANDwww_lsl);
976 case AArch64::ATOMIC_LOAD_AND_I64:
977 return emitAtomicBinary(MI, MBB, 8, AArch64::ANDxxx_lsl);
979 case AArch64::ATOMIC_LOAD_OR_I8:
980 return emitAtomicBinary(MI, MBB, 1, AArch64::ORRwww_lsl);
981 case AArch64::ATOMIC_LOAD_OR_I16:
982 return emitAtomicBinary(MI, MBB, 2, AArch64::ORRwww_lsl);
983 case AArch64::ATOMIC_LOAD_OR_I32:
984 return emitAtomicBinary(MI, MBB, 4, AArch64::ORRwww_lsl);
985 case AArch64::ATOMIC_LOAD_OR_I64:
986 return emitAtomicBinary(MI, MBB, 8, AArch64::ORRxxx_lsl);
988 case AArch64::ATOMIC_LOAD_XOR_I8:
989 return emitAtomicBinary(MI, MBB, 1, AArch64::EORwww_lsl);
990 case AArch64::ATOMIC_LOAD_XOR_I16:
991 return emitAtomicBinary(MI, MBB, 2, AArch64::EORwww_lsl);
992 case AArch64::ATOMIC_LOAD_XOR_I32:
993 return emitAtomicBinary(MI, MBB, 4, AArch64::EORwww_lsl);
994 case AArch64::ATOMIC_LOAD_XOR_I64:
995 return emitAtomicBinary(MI, MBB, 8, AArch64::EORxxx_lsl);
997 case AArch64::ATOMIC_LOAD_NAND_I8:
998 return emitAtomicBinary(MI, MBB, 1, AArch64::BICwww_lsl);
999 case AArch64::ATOMIC_LOAD_NAND_I16:
1000 return emitAtomicBinary(MI, MBB, 2, AArch64::BICwww_lsl);
1001 case AArch64::ATOMIC_LOAD_NAND_I32:
1002 return emitAtomicBinary(MI, MBB, 4, AArch64::BICwww_lsl);
1003 case AArch64::ATOMIC_LOAD_NAND_I64:
1004 return emitAtomicBinary(MI, MBB, 8, AArch64::BICxxx_lsl);
1006 case AArch64::ATOMIC_LOAD_MIN_I8:
1007 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_sxtb, A64CC::GT);
1008 case AArch64::ATOMIC_LOAD_MIN_I16:
1009 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_sxth, A64CC::GT);
1010 case AArch64::ATOMIC_LOAD_MIN_I32:
1011 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::GT);
1012 case AArch64::ATOMIC_LOAD_MIN_I64:
1013 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::GT);
1015 case AArch64::ATOMIC_LOAD_MAX_I8:
1016 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_sxtb, A64CC::LT);
1017 case AArch64::ATOMIC_LOAD_MAX_I16:
1018 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_sxth, A64CC::LT);
1019 case AArch64::ATOMIC_LOAD_MAX_I32:
1020 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::LT);
1021 case AArch64::ATOMIC_LOAD_MAX_I64:
1022 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::LT);
1024 case AArch64::ATOMIC_LOAD_UMIN_I8:
1025 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_uxtb, A64CC::HI);
1026 case AArch64::ATOMIC_LOAD_UMIN_I16:
1027 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_uxth, A64CC::HI);
1028 case AArch64::ATOMIC_LOAD_UMIN_I32:
1029 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::HI);
1030 case AArch64::ATOMIC_LOAD_UMIN_I64:
1031 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::HI);
1033 case AArch64::ATOMIC_LOAD_UMAX_I8:
1034 return emitAtomicBinaryMinMax(MI, MBB, 1, AArch64::CMPww_uxtb, A64CC::LO);
1035 case AArch64::ATOMIC_LOAD_UMAX_I16:
1036 return emitAtomicBinaryMinMax(MI, MBB, 2, AArch64::CMPww_uxth, A64CC::LO);
1037 case AArch64::ATOMIC_LOAD_UMAX_I32:
1038 return emitAtomicBinaryMinMax(MI, MBB, 4, AArch64::CMPww_lsl, A64CC::LO);
1039 case AArch64::ATOMIC_LOAD_UMAX_I64:
1040 return emitAtomicBinaryMinMax(MI, MBB, 8, AArch64::CMPxx_lsl, A64CC::LO);
1042 case AArch64::ATOMIC_SWAP_I8:
1043 return emitAtomicBinary(MI, MBB, 1, 0);
1044 case AArch64::ATOMIC_SWAP_I16:
1045 return emitAtomicBinary(MI, MBB, 2, 0);
1046 case AArch64::ATOMIC_SWAP_I32:
1047 return emitAtomicBinary(MI, MBB, 4, 0);
1048 case AArch64::ATOMIC_SWAP_I64:
1049 return emitAtomicBinary(MI, MBB, 8, 0);
1051 case AArch64::ATOMIC_CMP_SWAP_I8:
1052 return emitAtomicCmpSwap(MI, MBB, 1);
1053 case AArch64::ATOMIC_CMP_SWAP_I16:
1054 return emitAtomicCmpSwap(MI, MBB, 2);
1055 case AArch64::ATOMIC_CMP_SWAP_I32:
1056 return emitAtomicCmpSwap(MI, MBB, 4);
1057 case AArch64::ATOMIC_CMP_SWAP_I64:
1058 return emitAtomicCmpSwap(MI, MBB, 8);
1063 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
1065 case AArch64ISD::BR_CC: return "AArch64ISD::BR_CC";
1066 case AArch64ISD::Call: return "AArch64ISD::Call";
1067 case AArch64ISD::FPMOV: return "AArch64ISD::FPMOV";
1068 case AArch64ISD::GOTLoad: return "AArch64ISD::GOTLoad";
1069 case AArch64ISD::BFI: return "AArch64ISD::BFI";
1070 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
1071 case AArch64ISD::Ret: return "AArch64ISD::Ret";
1072 case AArch64ISD::SBFX: return "AArch64ISD::SBFX";
1073 case AArch64ISD::SELECT_CC: return "AArch64ISD::SELECT_CC";
1074 case AArch64ISD::SETCC: return "AArch64ISD::SETCC";
1075 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
1076 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
1077 case AArch64ISD::TLSDESCCALL: return "AArch64ISD::TLSDESCCALL";
1078 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
1079 case AArch64ISD::WrapperSmall: return "AArch64ISD::WrapperSmall";
1081 case AArch64ISD::NEON_MOVIMM:
1082 return "AArch64ISD::NEON_MOVIMM";
1083 case AArch64ISD::NEON_MVNIMM:
1084 return "AArch64ISD::NEON_MVNIMM";
1085 case AArch64ISD::NEON_FMOVIMM:
1086 return "AArch64ISD::NEON_FMOVIMM";
1087 case AArch64ISD::NEON_CMP:
1088 return "AArch64ISD::NEON_CMP";
1089 case AArch64ISD::NEON_CMPZ:
1090 return "AArch64ISD::NEON_CMPZ";
1091 case AArch64ISD::NEON_TST:
1092 return "AArch64ISD::NEON_TST";
1093 case AArch64ISD::NEON_QSHLs:
1094 return "AArch64ISD::NEON_QSHLs";
1095 case AArch64ISD::NEON_QSHLu:
1096 return "AArch64ISD::NEON_QSHLu";
1097 case AArch64ISD::NEON_VDUP:
1098 return "AArch64ISD::NEON_VDUP";
1099 case AArch64ISD::NEON_VDUPLANE:
1100 return "AArch64ISD::NEON_VDUPLANE";
1101 case AArch64ISD::NEON_REV16:
1102 return "AArch64ISD::NEON_REV16";
1103 case AArch64ISD::NEON_REV32:
1104 return "AArch64ISD::NEON_REV32";
1105 case AArch64ISD::NEON_REV64:
1106 return "AArch64ISD::NEON_REV64";
1107 case AArch64ISD::NEON_UZP1:
1108 return "AArch64ISD::NEON_UZP1";
1109 case AArch64ISD::NEON_UZP2:
1110 return "AArch64ISD::NEON_UZP2";
1111 case AArch64ISD::NEON_ZIP1:
1112 return "AArch64ISD::NEON_ZIP1";
1113 case AArch64ISD::NEON_ZIP2:
1114 return "AArch64ISD::NEON_ZIP2";
1115 case AArch64ISD::NEON_TRN1:
1116 return "AArch64ISD::NEON_TRN1";
1117 case AArch64ISD::NEON_TRN2:
1118 return "AArch64ISD::NEON_TRN2";
1119 case AArch64ISD::NEON_LD1_UPD:
1120 return "AArch64ISD::NEON_LD1_UPD";
1121 case AArch64ISD::NEON_LD2_UPD:
1122 return "AArch64ISD::NEON_LD2_UPD";
1123 case AArch64ISD::NEON_LD3_UPD:
1124 return "AArch64ISD::NEON_LD3_UPD";
1125 case AArch64ISD::NEON_LD4_UPD:
1126 return "AArch64ISD::NEON_LD4_UPD";
1127 case AArch64ISD::NEON_ST1_UPD:
1128 return "AArch64ISD::NEON_ST1_UPD";
1129 case AArch64ISD::NEON_ST2_UPD:
1130 return "AArch64ISD::NEON_ST2_UPD";
1131 case AArch64ISD::NEON_ST3_UPD:
1132 return "AArch64ISD::NEON_ST3_UPD";
1133 case AArch64ISD::NEON_ST4_UPD:
1134 return "AArch64ISD::NEON_ST4_UPD";
1135 case AArch64ISD::NEON_LD1x2_UPD:
1136 return "AArch64ISD::NEON_LD1x2_UPD";
1137 case AArch64ISD::NEON_LD1x3_UPD:
1138 return "AArch64ISD::NEON_LD1x3_UPD";
1139 case AArch64ISD::NEON_LD1x4_UPD:
1140 return "AArch64ISD::NEON_LD1x4_UPD";
1141 case AArch64ISD::NEON_ST1x2_UPD:
1142 return "AArch64ISD::NEON_ST1x2_UPD";
1143 case AArch64ISD::NEON_ST1x3_UPD:
1144 return "AArch64ISD::NEON_ST1x3_UPD";
1145 case AArch64ISD::NEON_ST1x4_UPD:
1146 return "AArch64ISD::NEON_ST1x4_UPD";
1147 case AArch64ISD::NEON_LD2DUP:
1148 return "AArch64ISD::NEON_LD2DUP";
1149 case AArch64ISD::NEON_LD3DUP:
1150 return "AArch64ISD::NEON_LD3DUP";
1151 case AArch64ISD::NEON_LD4DUP:
1152 return "AArch64ISD::NEON_LD4DUP";
1153 case AArch64ISD::NEON_LD2DUP_UPD:
1154 return "AArch64ISD::NEON_LD2DUP_UPD";
1155 case AArch64ISD::NEON_LD3DUP_UPD:
1156 return "AArch64ISD::NEON_LD3DUP_UPD";
1157 case AArch64ISD::NEON_LD4DUP_UPD:
1158 return "AArch64ISD::NEON_LD4DUP_UPD";
1159 case AArch64ISD::NEON_LD2LN_UPD:
1160 return "AArch64ISD::NEON_LD2LN_UPD";
1161 case AArch64ISD::NEON_LD3LN_UPD:
1162 return "AArch64ISD::NEON_LD3LN_UPD";
1163 case AArch64ISD::NEON_LD4LN_UPD:
1164 return "AArch64ISD::NEON_LD4LN_UPD";
1165 case AArch64ISD::NEON_ST2LN_UPD:
1166 return "AArch64ISD::NEON_ST2LN_UPD";
1167 case AArch64ISD::NEON_ST3LN_UPD:
1168 return "AArch64ISD::NEON_ST3LN_UPD";
1169 case AArch64ISD::NEON_ST4LN_UPD:
1170 return "AArch64ISD::NEON_ST4LN_UPD";
1171 case AArch64ISD::NEON_VEXTRACT:
1172 return "AArch64ISD::NEON_VEXTRACT";
1178 static const uint16_t AArch64FPRArgRegs[] = {
1179 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
1180 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
1182 static const unsigned NumFPRArgRegs = llvm::array_lengthof(AArch64FPRArgRegs);
1184 static const uint16_t AArch64ArgRegs[] = {
1185 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3,
1186 AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
1188 static const unsigned NumArgRegs = llvm::array_lengthof(AArch64ArgRegs);
1190 static bool CC_AArch64NoMoreRegs(unsigned ValNo, MVT ValVT, MVT LocVT,
1191 CCValAssign::LocInfo LocInfo,
1192 ISD::ArgFlagsTy ArgFlags, CCState &State) {
1193 // Mark all remaining general purpose registers as allocated. We don't
1194 // backtrack: if (for example) an i128 gets put on the stack, no subsequent
1195 // i64 will go in registers (C.11).
1196 for (unsigned i = 0; i < NumArgRegs; ++i)
1197 State.AllocateReg(AArch64ArgRegs[i]);
1202 #include "AArch64GenCallingConv.inc"
1204 CCAssignFn *AArch64TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1207 default: llvm_unreachable("Unsupported calling convention");
1208 case CallingConv::Fast:
1209 case CallingConv::C:
1215 AArch64TargetLowering::SaveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG,
1216 SDLoc DL, SDValue &Chain) const {
1217 MachineFunction &MF = DAG.getMachineFunction();
1218 MachineFrameInfo *MFI = MF.getFrameInfo();
1219 AArch64MachineFunctionInfo *FuncInfo
1220 = MF.getInfo<AArch64MachineFunctionInfo>();
1222 SmallVector<SDValue, 8> MemOps;
1224 unsigned FirstVariadicGPR = CCInfo.getFirstUnallocated(AArch64ArgRegs,
1226 unsigned FirstVariadicFPR = CCInfo.getFirstUnallocated(AArch64FPRArgRegs,
1229 unsigned GPRSaveSize = 8 * (NumArgRegs - FirstVariadicGPR);
1231 if (GPRSaveSize != 0) {
1232 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
1234 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
1236 for (unsigned i = FirstVariadicGPR; i < NumArgRegs; ++i) {
1237 unsigned VReg = MF.addLiveIn(AArch64ArgRegs[i], &AArch64::GPR64RegClass);
1238 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
1239 SDValue Store = DAG.getStore(Val.getValue(1), DL, Val, FIN,
1240 MachinePointerInfo::getStack(i * 8),
1242 MemOps.push_back(Store);
1243 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1244 DAG.getConstant(8, getPointerTy()));
1248 if (getSubtarget()->hasFPARMv8()) {
1249 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
1251 // According to the AArch64 Procedure Call Standard, section B.1/B.3, we
1252 // can omit a register save area if we know we'll never use registers of
1254 if (FPRSaveSize != 0) {
1255 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
1257 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
1259 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
1260 unsigned VReg = MF.addLiveIn(AArch64FPRArgRegs[i],
1261 &AArch64::FPR128RegClass);
1262 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
1263 SDValue Store = DAG.getStore(Val.getValue(1), DL, Val, FIN,
1264 MachinePointerInfo::getStack(i * 16),
1266 MemOps.push_back(Store);
1267 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1268 DAG.getConstant(16, getPointerTy()));
1271 FuncInfo->setVariadicFPRIdx(FPRIdx);
1272 FuncInfo->setVariadicFPRSize(FPRSaveSize);
1275 int StackIdx = MFI->CreateFixedObject(8, CCInfo.getNextStackOffset(), true);
1277 FuncInfo->setVariadicStackIdx(StackIdx);
1278 FuncInfo->setVariadicGPRIdx(GPRIdx);
1279 FuncInfo->setVariadicGPRSize(GPRSaveSize);
1281 if (!MemOps.empty()) {
1282 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
1289 AArch64TargetLowering::LowerFormalArguments(SDValue Chain,
1290 CallingConv::ID CallConv, bool isVarArg,
1291 const SmallVectorImpl<ISD::InputArg> &Ins,
1292 SDLoc dl, SelectionDAG &DAG,
1293 SmallVectorImpl<SDValue> &InVals) const {
1294 MachineFunction &MF = DAG.getMachineFunction();
1295 AArch64MachineFunctionInfo *FuncInfo
1296 = MF.getInfo<AArch64MachineFunctionInfo>();
1297 MachineFrameInfo *MFI = MF.getFrameInfo();
1298 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1300 SmallVector<CCValAssign, 16> ArgLocs;
1301 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1302 getTargetMachine(), ArgLocs, *DAG.getContext());
1303 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1305 SmallVector<SDValue, 16> ArgValues;
1308 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1309 CCValAssign &VA = ArgLocs[i];
1310 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1312 if (Flags.isByVal()) {
1313 // Byval is used for small structs and HFAs in the PCS, but the system
1314 // should work in a non-compliant manner for larger structs.
1315 EVT PtrTy = getPointerTy();
1316 int Size = Flags.getByValSize();
1317 unsigned NumRegs = (Size + 7) / 8;
1319 unsigned FrameIdx = MFI->CreateFixedObject(8 * NumRegs,
1320 VA.getLocMemOffset(),
1322 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
1323 InVals.push_back(FrameIdxN);
1326 } else if (VA.isRegLoc()) {
1327 MVT RegVT = VA.getLocVT();
1328 const TargetRegisterClass *RC = getRegClassFor(RegVT);
1329 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1331 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1332 } else { // VA.isRegLoc()
1333 assert(VA.isMemLoc());
1335 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
1336 VA.getLocMemOffset(), true);
1338 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1339 ArgValue = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
1340 MachinePointerInfo::getFixedStack(FI),
1341 false, false, false, 0);
1346 switch (VA.getLocInfo()) {
1347 default: llvm_unreachable("Unknown loc info!");
1348 case CCValAssign::Full: break;
1349 case CCValAssign::BCvt:
1350 ArgValue = DAG.getNode(ISD::BITCAST,dl, VA.getValVT(), ArgValue);
1352 case CCValAssign::SExt:
1353 case CCValAssign::ZExt:
1354 case CCValAssign::AExt:
1355 case CCValAssign::FPExt: {
1356 unsigned DestSize = VA.getValVT().getSizeInBits();
1357 unsigned DestSubReg;
1360 case 8: DestSubReg = AArch64::sub_8; break;
1361 case 16: DestSubReg = AArch64::sub_16; break;
1362 case 32: DestSubReg = AArch64::sub_32; break;
1363 case 64: DestSubReg = AArch64::sub_64; break;
1364 default: llvm_unreachable("Unexpected argument promotion");
1367 ArgValue = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl,
1368 VA.getValVT(), ArgValue,
1369 DAG.getTargetConstant(DestSubReg, MVT::i32)),
1375 InVals.push_back(ArgValue);
1379 SaveVarArgRegisters(CCInfo, DAG, dl, Chain);
1381 unsigned StackArgSize = CCInfo.getNextStackOffset();
1382 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
1383 // This is a non-standard ABI so by fiat I say we're allowed to make full
1384 // use of the stack area to be popped, which must be aligned to 16 bytes in
1386 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
1388 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
1389 // a multiple of 16.
1390 FuncInfo->setArgumentStackToRestore(StackArgSize);
1392 // This realignment carries over to the available bytes below. Our own
1393 // callers will guarantee the space is free by giving an aligned value to
1396 // Even if we're not expected to free up the space, it's useful to know how
1397 // much is there while considering tail calls (because we can reuse it).
1398 FuncInfo->setBytesInStackArgArea(StackArgSize);
1404 AArch64TargetLowering::LowerReturn(SDValue Chain,
1405 CallingConv::ID CallConv, bool isVarArg,
1406 const SmallVectorImpl<ISD::OutputArg> &Outs,
1407 const SmallVectorImpl<SDValue> &OutVals,
1408 SDLoc dl, SelectionDAG &DAG) const {
1409 // CCValAssign - represent the assignment of the return value to a location.
1410 SmallVector<CCValAssign, 16> RVLocs;
1412 // CCState - Info about the registers and stack slots.
1413 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1414 getTargetMachine(), RVLocs, *DAG.getContext());
1416 // Analyze outgoing return values.
1417 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv));
1420 SmallVector<SDValue, 4> RetOps(1, Chain);
1422 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1423 // PCS: "If the type, T, of the result of a function is such that
1424 // void func(T arg) would require that arg be passed as a value in a
1425 // register (or set of registers) according to the rules in 5.4, then the
1426 // result is returned in the same registers as would be used for such an
1429 // Otherwise, the caller shall reserve a block of memory of sufficient
1430 // size and alignment to hold the result. The address of the memory block
1431 // shall be passed as an additional argument to the function in x8."
1433 // This is implemented in two places. The register-return values are dealt
1434 // with here, more complex returns are passed as an sret parameter, which
1435 // means we don't have to worry about it during actual return.
1436 CCValAssign &VA = RVLocs[i];
1437 assert(VA.isRegLoc() && "Only register-returns should be created by PCS");
1440 SDValue Arg = OutVals[i];
1442 // There's no convenient note in the ABI about this as there is for normal
1443 // arguments, but it says return values are passed in the same registers as
1444 // an argument would be. I believe that includes the comments about
1445 // unspecified higher bits, putting the burden of widening on the *caller*
1446 // for return values.
1447 switch (VA.getLocInfo()) {
1448 default: llvm_unreachable("Unknown loc info");
1449 case CCValAssign::Full: break;
1450 case CCValAssign::SExt:
1451 case CCValAssign::ZExt:
1452 case CCValAssign::AExt:
1453 // Floating-point values should only be extended when they're going into
1454 // memory, which can't happen here so an integer extend is acceptable.
1455 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1457 case CCValAssign::BCvt:
1458 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1462 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1463 Flag = Chain.getValue(1);
1464 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1467 RetOps[0] = Chain; // Update chain.
1469 // Add the flag if we have it.
1471 RetOps.push_back(Flag);
1473 return DAG.getNode(AArch64ISD::Ret, dl, MVT::Other,
1474 &RetOps[0], RetOps.size());
1477 unsigned AArch64TargetLowering::getByValTypeAlignment(Type *Ty) const {
1478 // This is a new backend. For anything more precise than this a FE should
1479 // set an explicit alignment.
1484 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
1485 SmallVectorImpl<SDValue> &InVals) const {
1486 SelectionDAG &DAG = CLI.DAG;
1488 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1489 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1490 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1491 SDValue Chain = CLI.Chain;
1492 SDValue Callee = CLI.Callee;
1493 bool &IsTailCall = CLI.IsTailCall;
1494 CallingConv::ID CallConv = CLI.CallConv;
1495 bool IsVarArg = CLI.IsVarArg;
1497 MachineFunction &MF = DAG.getMachineFunction();
1498 AArch64MachineFunctionInfo *FuncInfo
1499 = MF.getInfo<AArch64MachineFunctionInfo>();
1500 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1501 bool IsStructRet = !Outs.empty() && Outs[0].Flags.isSRet();
1502 bool IsSibCall = false;
1505 IsTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1506 IsVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1507 Outs, OutVals, Ins, DAG);
1509 // A sibling call is one where we're under the usual C ABI and not planning
1510 // to change that but can still do a tail call:
1511 if (!TailCallOpt && IsTailCall)
1515 SmallVector<CCValAssign, 16> ArgLocs;
1516 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
1517 getTargetMachine(), ArgLocs, *DAG.getContext());
1518 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1520 // On AArch64 (and all other architectures I'm aware of) the most this has to
1521 // do is adjust the stack pointer.
1522 unsigned NumBytes = RoundUpToAlignment(CCInfo.getNextStackOffset(), 16);
1524 // Since we're not changing the ABI to make this a tail call, the memory
1525 // operands are already available in the caller's incoming argument space.
1529 // FPDiff is the byte offset of the call's argument area from the callee's.
1530 // Stores to callee stack arguments will be placed in FixedStackSlots offset
1531 // by this amount for a tail call. In a sibling call it must be 0 because the
1532 // caller will deallocate the entire stack and the callee still expects its
1533 // arguments to begin at SP+0. Completely unused for non-tail calls.
1536 if (IsTailCall && !IsSibCall) {
1537 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
1539 // FPDiff will be negative if this tail call requires more space than we
1540 // would automatically have in our incoming argument space. Positive if we
1541 // can actually shrink the stack.
1542 FPDiff = NumReusableBytes - NumBytes;
1544 // The stack pointer must be 16-byte aligned at all times it's used for a
1545 // memory operation, which in practice means at *all* times and in
1546 // particular across call boundaries. Therefore our own arguments started at
1547 // a 16-byte aligned SP and the delta applied for the tail call should
1548 // satisfy the same constraint.
1549 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
1553 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
1556 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, AArch64::XSP,
1559 SmallVector<SDValue, 8> MemOpChains;
1560 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1562 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1563 CCValAssign &VA = ArgLocs[i];
1564 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1565 SDValue Arg = OutVals[i];
1567 // Callee does the actual widening, so all extensions just use an implicit
1568 // definition of the rest of the Loc. Aesthetically, this would be nicer as
1569 // an ANY_EXTEND, but that isn't valid for floating-point types and this
1570 // alternative works on integer types too.
1571 switch (VA.getLocInfo()) {
1572 default: llvm_unreachable("Unknown loc info!");
1573 case CCValAssign::Full: break;
1574 case CCValAssign::SExt:
1575 case CCValAssign::ZExt:
1576 case CCValAssign::AExt:
1577 case CCValAssign::FPExt: {
1578 unsigned SrcSize = VA.getValVT().getSizeInBits();
1582 case 8: SrcSubReg = AArch64::sub_8; break;
1583 case 16: SrcSubReg = AArch64::sub_16; break;
1584 case 32: SrcSubReg = AArch64::sub_32; break;
1585 case 64: SrcSubReg = AArch64::sub_64; break;
1586 default: llvm_unreachable("Unexpected argument promotion");
1589 Arg = SDValue(DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
1591 DAG.getUNDEF(VA.getLocVT()),
1593 DAG.getTargetConstant(SrcSubReg, MVT::i32)),
1598 case CCValAssign::BCvt:
1599 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1603 if (VA.isRegLoc()) {
1604 // A normal register (sub-) argument. For now we just note it down because
1605 // we want to copy things into registers as late as possible to avoid
1606 // register-pressure (and possibly worse).
1607 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1611 assert(VA.isMemLoc() && "unexpected argument location");
1614 MachinePointerInfo DstInfo;
1616 uint32_t OpSize = Flags.isByVal() ? Flags.getByValSize() :
1617 VA.getLocVT().getSizeInBits();
1618 OpSize = (OpSize + 7) / 8;
1619 int32_t Offset = VA.getLocMemOffset() + FPDiff;
1620 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
1622 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
1623 DstInfo = MachinePointerInfo::getFixedStack(FI);
1625 // Make sure any stack arguments overlapping with where we're storing are
1626 // loaded before this eventual operation. Otherwise they'll be clobbered.
1627 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
1629 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset());
1631 DstAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1632 DstInfo = MachinePointerInfo::getStack(VA.getLocMemOffset());
1635 if (Flags.isByVal()) {
1636 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i64);
1637 SDValue Cpy = DAG.getMemcpy(Chain, dl, DstAddr, Arg, SizeNode,
1638 Flags.getByValAlign(),
1639 /*isVolatile = */ false,
1640 /*alwaysInline = */ false,
1641 DstInfo, MachinePointerInfo(0));
1642 MemOpChains.push_back(Cpy);
1644 // Normal stack argument, put it where it's needed.
1645 SDValue Store = DAG.getStore(Chain, dl, Arg, DstAddr, DstInfo,
1647 MemOpChains.push_back(Store);
1651 // The loads and stores generated above shouldn't clash with each
1652 // other. Combining them with this TokenFactor notes that fact for the rest of
1654 if (!MemOpChains.empty())
1655 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1656 &MemOpChains[0], MemOpChains.size());
1658 // Most of the rest of the instructions need to be glued together; we don't
1659 // want assignments to actual registers used by a call to be rearranged by a
1660 // well-meaning scheduler.
1663 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1664 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1665 RegsToPass[i].second, InFlag);
1666 InFlag = Chain.getValue(1);
1669 // The linker is responsible for inserting veneers when necessary to put a
1670 // function call destination in range, so we don't need to bother with a
1672 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1673 const GlobalValue *GV = G->getGlobal();
1674 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
1675 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1676 const char *Sym = S->getSymbol();
1677 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1680 // We don't usually want to end the call-sequence here because we would tidy
1681 // the frame up *after* the call, however in the ABI-changing tail-call case
1682 // we've carefully laid out the parameters so that when sp is reset they'll be
1683 // in the correct location.
1684 if (IsTailCall && !IsSibCall) {
1685 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1686 DAG.getIntPtrConstant(0, true), InFlag, dl);
1687 InFlag = Chain.getValue(1);
1690 // We produce the following DAG scheme for the actual call instruction:
1691 // (AArch64Call Chain, Callee, reg1, ..., regn, preserveMask, inflag?
1693 // Most arguments aren't going to be used and just keep the values live as
1694 // far as LLVM is concerned. It's expected to be selected as simply "bl
1695 // callee" (for a direct, non-tail call).
1696 std::vector<SDValue> Ops;
1697 Ops.push_back(Chain);
1698 Ops.push_back(Callee);
1701 // Each tail call may have to adjust the stack by a different amount, so
1702 // this information must travel along with the operation for eventual
1703 // consumption by emitEpilogue.
1704 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
1707 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1708 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1709 RegsToPass[i].second.getValueType()));
1712 // Add a register mask operand representing the call-preserved registers. This
1713 // is used later in codegen to constrain register-allocation.
1714 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1715 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
1716 assert(Mask && "Missing call preserved mask for calling convention");
1717 Ops.push_back(DAG.getRegisterMask(Mask));
1719 // If we needed glue, put it in as the last argument.
1720 if (InFlag.getNode())
1721 Ops.push_back(InFlag);
1723 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1726 return DAG.getNode(AArch64ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1729 Chain = DAG.getNode(AArch64ISD::Call, dl, NodeTys, &Ops[0], Ops.size());
1730 InFlag = Chain.getValue(1);
1732 // Now we can reclaim the stack, just as well do it before working out where
1733 // our return value is.
1735 uint64_t CalleePopBytes
1736 = DoesCalleeRestoreStack(CallConv, TailCallOpt) ? NumBytes : 0;
1738 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1739 DAG.getIntPtrConstant(CalleePopBytes, true),
1741 InFlag = Chain.getValue(1);
1744 return LowerCallResult(Chain, InFlag, CallConv,
1745 IsVarArg, Ins, dl, DAG, InVals);
1749 AArch64TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1750 CallingConv::ID CallConv, bool IsVarArg,
1751 const SmallVectorImpl<ISD::InputArg> &Ins,
1752 SDLoc dl, SelectionDAG &DAG,
1753 SmallVectorImpl<SDValue> &InVals) const {
1754 // Assign locations to each value returned by this call.
1755 SmallVector<CCValAssign, 16> RVLocs;
1756 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
1757 getTargetMachine(), RVLocs, *DAG.getContext());
1758 CCInfo.AnalyzeCallResult(Ins, CCAssignFnForNode(CallConv));
1760 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1761 CCValAssign VA = RVLocs[i];
1763 // Return values that are too big to fit into registers should use an sret
1764 // pointer, so this can be a lot simpler than the main argument code.
1765 assert(VA.isRegLoc() && "Memory locations not expected for call return");
1767 SDValue Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1769 Chain = Val.getValue(1);
1770 InFlag = Val.getValue(2);
1772 switch (VA.getLocInfo()) {
1773 default: llvm_unreachable("Unknown loc info!");
1774 case CCValAssign::Full: break;
1775 case CCValAssign::BCvt:
1776 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1778 case CCValAssign::ZExt:
1779 case CCValAssign::SExt:
1780 case CCValAssign::AExt:
1781 // Floating-point arguments only get extended/truncated if they're going
1782 // in memory, so using the integer operation is acceptable here.
1783 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
1787 InVals.push_back(Val);
1794 AArch64TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1795 CallingConv::ID CalleeCC,
1797 bool IsCalleeStructRet,
1798 bool IsCallerStructRet,
1799 const SmallVectorImpl<ISD::OutputArg> &Outs,
1800 const SmallVectorImpl<SDValue> &OutVals,
1801 const SmallVectorImpl<ISD::InputArg> &Ins,
1802 SelectionDAG& DAG) const {
1804 // For CallingConv::C this function knows whether the ABI needs
1805 // changing. That's not true for other conventions so they will have to opt in
1807 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1810 const MachineFunction &MF = DAG.getMachineFunction();
1811 const Function *CallerF = MF.getFunction();
1812 CallingConv::ID CallerCC = CallerF->getCallingConv();
1813 bool CCMatch = CallerCC == CalleeCC;
1815 // Byval parameters hand the function a pointer directly into the stack area
1816 // we want to reuse during a tail call. Working around this *is* possible (see
1817 // X86) but less efficient and uglier in LowerCall.
1818 for (Function::const_arg_iterator i = CallerF->arg_begin(),
1819 e = CallerF->arg_end(); i != e; ++i)
1820 if (i->hasByValAttr())
1823 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
1824 if (IsTailCallConvention(CalleeCC) && CCMatch)
1829 // Now we search for cases where we can use a tail call without changing the
1830 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
1833 // I want anyone implementing a new calling convention to think long and hard
1834 // about this assert.
1835 assert((!IsVarArg || CalleeCC == CallingConv::C)
1836 && "Unexpected variadic calling convention");
1838 if (IsVarArg && !Outs.empty()) {
1839 // At least two cases here: if caller is fastcc then we can't have any
1840 // memory arguments (we'd be expected to clean up the stack afterwards). If
1841 // caller is C then we could potentially use its argument area.
1843 // FIXME: for now we take the most conservative of these in both cases:
1844 // disallow all variadic memory operands.
1845 SmallVector<CCValAssign, 16> ArgLocs;
1846 CCState CCInfo(CalleeCC, IsVarArg, DAG.getMachineFunction(),
1847 getTargetMachine(), ArgLocs, *DAG.getContext());
1849 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
1850 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
1851 if (!ArgLocs[i].isRegLoc())
1855 // If the calling conventions do not match, then we'd better make sure the
1856 // results are returned in the same way as what the caller expects.
1858 SmallVector<CCValAssign, 16> RVLocs1;
1859 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
1860 getTargetMachine(), RVLocs1, *DAG.getContext());
1861 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC));
1863 SmallVector<CCValAssign, 16> RVLocs2;
1864 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
1865 getTargetMachine(), RVLocs2, *DAG.getContext());
1866 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC));
1868 if (RVLocs1.size() != RVLocs2.size())
1870 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1871 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1873 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1875 if (RVLocs1[i].isRegLoc()) {
1876 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1879 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1885 // Nothing more to check if the callee is taking no arguments
1889 SmallVector<CCValAssign, 16> ArgLocs;
1890 CCState CCInfo(CalleeCC, IsVarArg, DAG.getMachineFunction(),
1891 getTargetMachine(), ArgLocs, *DAG.getContext());
1893 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
1895 const AArch64MachineFunctionInfo *FuncInfo
1896 = MF.getInfo<AArch64MachineFunctionInfo>();
1898 // If the stack arguments for this call would fit into our own save area then
1899 // the call can be made tail.
1900 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
1903 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
1904 bool TailCallOpt) const {
1905 return CallCC == CallingConv::Fast && TailCallOpt;
1908 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
1909 return CallCC == CallingConv::Fast;
1912 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
1914 MachineFrameInfo *MFI,
1915 int ClobberedFI) const {
1916 SmallVector<SDValue, 8> ArgChains;
1917 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
1918 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
1920 // Include the original chain at the beginning of the list. When this is
1921 // used by target LowerCall hooks, this helps legalize find the
1922 // CALLSEQ_BEGIN node.
1923 ArgChains.push_back(Chain);
1925 // Add a chain value for each stack argument corresponding
1926 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
1927 UE = DAG.getEntryNode().getNode()->use_end(); U != UE; ++U)
1928 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
1929 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
1930 if (FI->getIndex() < 0) {
1931 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
1932 int64_t InLastByte = InFirstByte;
1933 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
1935 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
1936 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
1937 ArgChains.push_back(SDValue(L, 1));
1940 // Build a tokenfactor for all the chains.
1941 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other,
1942 &ArgChains[0], ArgChains.size());
1945 static A64CC::CondCodes IntCCToA64CC(ISD::CondCode CC) {
1947 case ISD::SETEQ: return A64CC::EQ;
1948 case ISD::SETGT: return A64CC::GT;
1949 case ISD::SETGE: return A64CC::GE;
1950 case ISD::SETLT: return A64CC::LT;
1951 case ISD::SETLE: return A64CC::LE;
1952 case ISD::SETNE: return A64CC::NE;
1953 case ISD::SETUGT: return A64CC::HI;
1954 case ISD::SETUGE: return A64CC::HS;
1955 case ISD::SETULT: return A64CC::LO;
1956 case ISD::SETULE: return A64CC::LS;
1957 default: llvm_unreachable("Unexpected condition code");
1961 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Val) const {
1962 // icmp is implemented using adds/subs immediate, which take an unsigned
1963 // 12-bit immediate, optionally shifted left by 12 bits.
1965 // Symmetric by using adds/subs
1969 return (Val & ~0xfff) == 0 || (Val & ~0xfff000) == 0;
1972 SDValue AArch64TargetLowering::getSelectableIntSetCC(SDValue LHS, SDValue RHS,
1973 ISD::CondCode CC, SDValue &A64cc,
1974 SelectionDAG &DAG, SDLoc &dl) const {
1975 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1977 EVT VT = RHSC->getValueType(0);
1978 bool knownInvalid = false;
1980 // I'm not convinced the rest of LLVM handles these edge cases properly, but
1981 // we can at least get it right.
1982 if (isSignedIntSetCC(CC)) {
1983 C = RHSC->getSExtValue();
1984 } else if (RHSC->getZExtValue() > INT64_MAX) {
1985 // A 64-bit constant not representable by a signed 64-bit integer is far
1986 // too big to fit into a SUBS immediate anyway.
1987 knownInvalid = true;
1989 C = RHSC->getZExtValue();
1992 if (!knownInvalid && !isLegalICmpImmediate(C)) {
1993 // Constant does not fit, try adjusting it by one?
1998 if (isLegalICmpImmediate(C-1)) {
1999 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2000 RHS = DAG.getConstant(C-1, VT);
2005 if (isLegalICmpImmediate(C-1)) {
2006 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2007 RHS = DAG.getConstant(C-1, VT);
2012 if (isLegalICmpImmediate(C+1)) {
2013 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2014 RHS = DAG.getConstant(C+1, VT);
2019 if (isLegalICmpImmediate(C+1)) {
2020 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2021 RHS = DAG.getConstant(C+1, VT);
2028 A64CC::CondCodes CondCode = IntCCToA64CC(CC);
2029 A64cc = DAG.getConstant(CondCode, MVT::i32);
2030 return DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
2031 DAG.getCondCode(CC));
2034 static A64CC::CondCodes FPCCToA64CC(ISD::CondCode CC,
2035 A64CC::CondCodes &Alternative) {
2036 A64CC::CondCodes CondCode = A64CC::Invalid;
2037 Alternative = A64CC::Invalid;
2040 default: llvm_unreachable("Unknown FP condition!");
2042 case ISD::SETOEQ: CondCode = A64CC::EQ; break;
2044 case ISD::SETOGT: CondCode = A64CC::GT; break;
2046 case ISD::SETOGE: CondCode = A64CC::GE; break;
2047 case ISD::SETOLT: CondCode = A64CC::MI; break;
2048 case ISD::SETOLE: CondCode = A64CC::LS; break;
2049 case ISD::SETONE: CondCode = A64CC::MI; Alternative = A64CC::GT; break;
2050 case ISD::SETO: CondCode = A64CC::VC; break;
2051 case ISD::SETUO: CondCode = A64CC::VS; break;
2052 case ISD::SETUEQ: CondCode = A64CC::EQ; Alternative = A64CC::VS; break;
2053 case ISD::SETUGT: CondCode = A64CC::HI; break;
2054 case ISD::SETUGE: CondCode = A64CC::PL; break;
2056 case ISD::SETULT: CondCode = A64CC::LT; break;
2058 case ISD::SETULE: CondCode = A64CC::LE; break;
2060 case ISD::SETUNE: CondCode = A64CC::NE; break;
2066 AArch64TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
2068 EVT PtrVT = getPointerTy();
2069 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2071 switch(getTargetMachine().getCodeModel()) {
2072 case CodeModel::Small:
2073 // The most efficient code is PC-relative anyway for the small memory model,
2074 // so we don't need to worry about relocation model.
2075 return DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2076 DAG.getTargetBlockAddress(BA, PtrVT, 0,
2077 AArch64II::MO_NO_FLAG),
2078 DAG.getTargetBlockAddress(BA, PtrVT, 0,
2079 AArch64II::MO_LO12),
2080 DAG.getConstant(/*Alignment=*/ 4, MVT::i32));
2081 case CodeModel::Large:
2083 AArch64ISD::WrapperLarge, DL, PtrVT,
2084 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G3),
2085 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G2_NC),
2086 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G1_NC),
2087 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_ABS_G0_NC));
2089 llvm_unreachable("Only small and large code models supported now");
2094 // (BRCOND chain, val, dest)
2096 AArch64TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
2098 SDValue Chain = Op.getOperand(0);
2099 SDValue TheBit = Op.getOperand(1);
2100 SDValue DestBB = Op.getOperand(2);
2102 // AArch64 BooleanContents is the default UndefinedBooleanContent, which means
2103 // that as the consumer we are responsible for ignoring rubbish in higher
2105 TheBit = DAG.getNode(ISD::AND, dl, MVT::i32, TheBit,
2106 DAG.getConstant(1, MVT::i32));
2108 SDValue A64CMP = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, TheBit,
2109 DAG.getConstant(0, TheBit.getValueType()),
2110 DAG.getCondCode(ISD::SETNE));
2112 return DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other, Chain,
2113 A64CMP, DAG.getConstant(A64CC::NE, MVT::i32),
2117 // (BR_CC chain, condcode, lhs, rhs, dest)
2119 AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2121 SDValue Chain = Op.getOperand(0);
2122 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2123 SDValue LHS = Op.getOperand(2);
2124 SDValue RHS = Op.getOperand(3);
2125 SDValue DestBB = Op.getOperand(4);
2127 if (LHS.getValueType() == MVT::f128) {
2128 // f128 comparisons are lowered to runtime calls by a routine which sets
2129 // LHS, RHS and CC appropriately for the rest of this function to continue.
2130 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2132 // If softenSetCCOperands returned a scalar, we need to compare the result
2133 // against zero to select between true and false values.
2134 if (RHS.getNode() == 0) {
2135 RHS = DAG.getConstant(0, LHS.getValueType());
2140 if (LHS.getValueType().isInteger()) {
2143 // Integers are handled in a separate function because the combinations of
2144 // immediates and tests can get hairy and we may want to fiddle things.
2145 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
2147 return DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
2148 Chain, CmpOp, A64cc, DestBB);
2151 // Note that some LLVM floating-point CondCodes can't be lowered to a single
2152 // conditional branch, hence FPCCToA64CC can set a second test, where either
2153 // passing is sufficient.
2154 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
2155 CondCode = FPCCToA64CC(CC, Alternative);
2156 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
2157 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
2158 DAG.getCondCode(CC));
2159 SDValue A64BR_CC = DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
2160 Chain, SetCC, A64cc, DestBB);
2162 if (Alternative != A64CC::Invalid) {
2163 A64cc = DAG.getConstant(Alternative, MVT::i32);
2164 A64BR_CC = DAG.getNode(AArch64ISD::BR_CC, dl, MVT::Other,
2165 A64BR_CC, SetCC, A64cc, DestBB);
2173 AArch64TargetLowering::LowerF128ToCall(SDValue Op, SelectionDAG &DAG,
2174 RTLIB::Libcall Call) const {
2177 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
2178 EVT ArgVT = Op.getOperand(i).getValueType();
2179 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2180 Entry.Node = Op.getOperand(i); Entry.Ty = ArgTy;
2181 Entry.isSExt = false;
2182 Entry.isZExt = false;
2183 Args.push_back(Entry);
2185 SDValue Callee = DAG.getExternalSymbol(getLibcallName(Call), getPointerTy());
2187 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
2189 // By default, the input chain to this libcall is the entry node of the
2190 // function. If the libcall is going to be emitted as a tail call then
2191 // isUsedByReturnOnly will change it to the right chain if the return
2192 // node which is being folded has a non-entry input chain.
2193 SDValue InChain = DAG.getEntryNode();
2195 // isTailCall may be true since the callee does not reference caller stack
2196 // frame. Check if it's in the right position.
2197 SDValue TCChain = InChain;
2198 bool isTailCall = isInTailCallPosition(DAG, Op.getNode(), TCChain);
2203 CallLoweringInfo CLI(InChain, RetTy, false, false, false, false,
2204 0, getLibcallCallingConv(Call), isTailCall,
2205 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
2206 Callee, Args, DAG, SDLoc(Op));
2207 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2209 if (!CallInfo.second.getNode())
2210 // It's a tailcall, return the chain (which is the DAG root).
2211 return DAG.getRoot();
2213 return CallInfo.first;
2217 AArch64TargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
2218 if (Op.getOperand(0).getValueType() != MVT::f128) {
2219 // It's legal except when f128 is involved
2224 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
2226 SDValue SrcVal = Op.getOperand(0);
2227 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
2228 /*isSigned*/ false, SDLoc(Op)).first;
2232 AArch64TargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
2233 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
2236 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
2238 return LowerF128ToCall(Op, DAG, LC);
2241 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG,
2244 EVT VT = Op.getValueType();
2245 SDValue Vec = Op.getOperand(0);
2246 EVT OpVT = Vec.getValueType();
2247 unsigned Opc = IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
2249 if (VT.getVectorNumElements() == 1) {
2250 assert(OpVT == MVT::v1f64 && "Unexpected vector type!");
2251 if (VT.getSizeInBits() == OpVT.getSizeInBits())
2253 return DAG.UnrollVectorOp(Op.getNode());
2256 if (VT.getSizeInBits() > OpVT.getSizeInBits()) {
2257 assert(Vec.getValueType() == MVT::v2f32 && VT == MVT::v2i64 &&
2258 "Unexpected vector type!");
2259 Vec = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v2f64, Vec);
2260 return DAG.getNode(Opc, dl, VT, Vec);
2261 } else if (VT.getSizeInBits() < OpVT.getSizeInBits()) {
2262 EVT CastVT = EVT::getIntegerVT(*DAG.getContext(),
2263 OpVT.getVectorElementType().getSizeInBits());
2265 EVT::getVectorVT(*DAG.getContext(), CastVT, VT.getVectorNumElements());
2266 Vec = DAG.getNode(Opc, dl, CastVT, Vec);
2267 return DAG.getNode(ISD::TRUNCATE, dl, VT, Vec);
2269 return DAG.getNode(Opc, dl, VT, Vec);
2272 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
2273 // We custom lower concat_vectors with 4, 8, or 16 operands that are all the
2274 // same operand and of type v1* using the DUP instruction.
2275 unsigned NumOps = Op->getNumOperands();
2276 if (NumOps != 4 && NumOps != 8 && NumOps != 16)
2279 // Must be a single value for VDUP.
2280 bool isConstant = true;
2281 SDValue Op0 = Op.getOperand(0);
2282 for (unsigned i = 1; i < NumOps; ++i) {
2283 SDValue OpN = Op.getOperand(i);
2287 if (!isa<ConstantSDNode>(OpN->getOperand(0)))
2291 // Verify the value type.
2292 EVT EltVT = Op0.getValueType();
2294 default: llvm_unreachable("Unexpected number of operands");
2296 if (EltVT != MVT::v1i16 && EltVT != MVT::v1i32)
2300 if (EltVT != MVT::v1i8 && EltVT != MVT::v1i16)
2304 if (EltVT != MVT::v1i8)
2310 EVT VT = Op.getValueType();
2311 // VDUP produces better code for constants.
2313 return DAG.getNode(AArch64ISD::NEON_VDUP, DL, VT, Op0->getOperand(0));
2314 return DAG.getNode(AArch64ISD::NEON_VDUPLANE, DL, VT, Op0,
2315 DAG.getConstant(0, MVT::i64));
2319 AArch64TargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
2320 bool IsSigned) const {
2321 if (Op.getValueType().isVector())
2322 return LowerVectorFP_TO_INT(Op, DAG, IsSigned);
2323 if (Op.getOperand(0).getValueType() != MVT::f128) {
2324 // It's legal except when f128 is involved
2330 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
2332 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
2334 return LowerF128ToCall(Op, DAG, LC);
2337 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2338 MachineFunction &MF = DAG.getMachineFunction();
2339 MachineFrameInfo *MFI = MF.getFrameInfo();
2340 MFI->setReturnAddressIsTaken(true);
2342 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
2345 EVT VT = Op.getValueType();
2347 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2349 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2350 SDValue Offset = DAG.getConstant(8, MVT::i64);
2351 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2352 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2353 MachinePointerInfo(), false, false, false, 0);
2356 // Return X30, which contains the return address. Mark it an implicit live-in.
2357 unsigned Reg = MF.addLiveIn(AArch64::X30, getRegClassFor(MVT::i64));
2358 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, MVT::i64);
2362 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG)
2364 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2365 MFI->setFrameAddressIsTaken(true);
2367 EVT VT = Op.getValueType();
2369 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2370 unsigned FrameReg = AArch64::X29;
2371 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2373 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
2374 MachinePointerInfo(),
2375 false, false, false, 0);
2380 AArch64TargetLowering::LowerGlobalAddressELFLarge(SDValue Op,
2381 SelectionDAG &DAG) const {
2382 assert(getTargetMachine().getCodeModel() == CodeModel::Large);
2383 assert(getTargetMachine().getRelocationModel() == Reloc::Static);
2385 EVT PtrVT = getPointerTy();
2387 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
2388 const GlobalValue *GV = GN->getGlobal();
2390 SDValue GlobalAddr = DAG.getNode(
2391 AArch64ISD::WrapperLarge, dl, PtrVT,
2392 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G3),
2393 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G2_NC),
2394 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G1_NC),
2395 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, AArch64II::MO_ABS_G0_NC));
2397 if (GN->getOffset() != 0)
2398 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalAddr,
2399 DAG.getConstant(GN->getOffset(), PtrVT));
2405 AArch64TargetLowering::LowerGlobalAddressELFSmall(SDValue Op,
2406 SelectionDAG &DAG) const {
2407 assert(getTargetMachine().getCodeModel() == CodeModel::Small);
2409 EVT PtrVT = getPointerTy();
2411 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
2412 const GlobalValue *GV = GN->getGlobal();
2413 unsigned Alignment = GV->getAlignment();
2414 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2415 if (GV->isWeakForLinker() && GV->isDeclaration() && RelocM == Reloc::Static) {
2416 // Weak undefined symbols can't use ADRP/ADD pair since they should evaluate
2417 // to zero when they remain undefined. In PIC mode the GOT can take care of
2418 // this, but in absolute mode we use a constant pool load.
2420 PoolAddr = DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT,
2421 DAG.getTargetConstantPool(GV, PtrVT, 0, 0,
2422 AArch64II::MO_NO_FLAG),
2423 DAG.getTargetConstantPool(GV, PtrVT, 0, 0,
2424 AArch64II::MO_LO12),
2425 DAG.getConstant(8, MVT::i32));
2426 SDValue GlobalAddr = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), PoolAddr,
2427 MachinePointerInfo::getConstantPool(),
2428 /*isVolatile=*/ false,
2429 /*isNonTemporal=*/ true,
2430 /*isInvariant=*/ true, 8);
2431 if (GN->getOffset() != 0)
2432 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalAddr,
2433 DAG.getConstant(GN->getOffset(), PtrVT));
2438 if (Alignment == 0) {
2439 const PointerType *GVPtrTy = cast<PointerType>(GV->getType());
2440 if (GVPtrTy->getElementType()->isSized()) {
2442 = getDataLayout()->getABITypeAlignment(GVPtrTy->getElementType());
2444 // Be conservative if we can't guess, not that it really matters:
2445 // functions and labels aren't valid for loads, and the methods used to
2446 // actually calculate an address work with any alignment.
2451 unsigned char HiFixup, LoFixup;
2452 bool UseGOT = getSubtarget()->GVIsIndirectSymbol(GV, RelocM);
2455 HiFixup = AArch64II::MO_GOT;
2456 LoFixup = AArch64II::MO_GOT_LO12;
2459 HiFixup = AArch64II::MO_NO_FLAG;
2460 LoFixup = AArch64II::MO_LO12;
2463 // AArch64's small model demands the following sequence:
2464 // ADRP x0, somewhere
2465 // ADD x0, x0, #:lo12:somewhere ; (or LDR directly).
2466 SDValue GlobalRef = DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT,
2467 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2469 DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2471 DAG.getConstant(Alignment, MVT::i32));
2474 GlobalRef = DAG.getNode(AArch64ISD::GOTLoad, dl, PtrVT, DAG.getEntryNode(),
2478 if (GN->getOffset() != 0)
2479 return DAG.getNode(ISD::ADD, dl, PtrVT, GlobalRef,
2480 DAG.getConstant(GN->getOffset(), PtrVT));
2486 AArch64TargetLowering::LowerGlobalAddressELF(SDValue Op,
2487 SelectionDAG &DAG) const {
2488 // TableGen doesn't have easy access to the CodeModel or RelocationModel, so
2489 // we make those distinctions here.
2491 switch (getTargetMachine().getCodeModel()) {
2492 case CodeModel::Small:
2493 return LowerGlobalAddressELFSmall(Op, DAG);
2494 case CodeModel::Large:
2495 return LowerGlobalAddressELFLarge(Op, DAG);
2497 llvm_unreachable("Only small and large code models supported now");
2502 AArch64TargetLowering::LowerConstantPool(SDValue Op,
2503 SelectionDAG &DAG) const {
2505 EVT PtrVT = getPointerTy();
2506 ConstantPoolSDNode *CN = cast<ConstantPoolSDNode>(Op);
2507 const Constant *C = CN->getConstVal();
2509 switch(getTargetMachine().getCodeModel()) {
2510 case CodeModel::Small:
2511 // The most efficient code is PC-relative anyway for the small memory model,
2512 // so we don't need to worry about relocation model.
2513 return DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2514 DAG.getTargetConstantPool(C, PtrVT, 0, 0,
2515 AArch64II::MO_NO_FLAG),
2516 DAG.getTargetConstantPool(C, PtrVT, 0, 0,
2517 AArch64II::MO_LO12),
2518 DAG.getConstant(CN->getAlignment(), MVT::i32));
2519 case CodeModel::Large:
2521 AArch64ISD::WrapperLarge, DL, PtrVT,
2522 DAG.getTargetConstantPool(C, PtrVT, 0, 0, AArch64II::MO_ABS_G3),
2523 DAG.getTargetConstantPool(C, PtrVT, 0, 0, AArch64II::MO_ABS_G2_NC),
2524 DAG.getTargetConstantPool(C, PtrVT, 0, 0, AArch64II::MO_ABS_G1_NC),
2525 DAG.getTargetConstantPool(C, PtrVT, 0, 0, AArch64II::MO_ABS_G0_NC));
2527 llvm_unreachable("Only small and large code models supported now");
2531 SDValue AArch64TargetLowering::LowerTLSDescCall(SDValue SymAddr,
2534 SelectionDAG &DAG) const {
2535 EVT PtrVT = getPointerTy();
2537 // The function we need to call is simply the first entry in the GOT for this
2538 // descriptor, load it in preparation.
2539 SDValue Func, Chain;
2540 Func = DAG.getNode(AArch64ISD::GOTLoad, DL, PtrVT, DAG.getEntryNode(),
2543 // The function takes only one argument: the address of the descriptor itself
2546 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
2547 Glue = Chain.getValue(1);
2549 // Finally, there's a special calling-convention which means that the lookup
2550 // must preserve all registers (except X0, obviously).
2551 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2552 const AArch64RegisterInfo *A64RI
2553 = static_cast<const AArch64RegisterInfo *>(TRI);
2554 const uint32_t *Mask = A64RI->getTLSDescCallPreservedMask();
2556 // We're now ready to populate the argument list, as with a normal call:
2557 std::vector<SDValue> Ops;
2558 Ops.push_back(Chain);
2559 Ops.push_back(Func);
2560 Ops.push_back(SymAddr);
2561 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
2562 Ops.push_back(DAG.getRegisterMask(Mask));
2563 Ops.push_back(Glue);
2565 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2566 Chain = DAG.getNode(AArch64ISD::TLSDESCCALL, DL, NodeTys, &Ops[0],
2568 Glue = Chain.getValue(1);
2570 // After the call, the offset from TPIDR_EL0 is in X0, copy it out and pass it
2571 // back to the generic handling code.
2572 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
2576 AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
2577 SelectionDAG &DAG) const {
2578 assert(getSubtarget()->isTargetELF() &&
2579 "TLS not implemented for non-ELF targets");
2580 assert(getTargetMachine().getCodeModel() == CodeModel::Small
2581 && "TLS only supported in small memory model");
2582 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2584 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
2587 EVT PtrVT = getPointerTy();
2589 const GlobalValue *GV = GA->getGlobal();
2591 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
2593 if (Model == TLSModel::InitialExec) {
2594 TPOff = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2595 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2596 AArch64II::MO_GOTTPREL),
2597 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2598 AArch64II::MO_GOTTPREL_LO12),
2599 DAG.getConstant(8, MVT::i32));
2600 TPOff = DAG.getNode(AArch64ISD::GOTLoad, DL, PtrVT, DAG.getEntryNode(),
2602 } else if (Model == TLSModel::LocalExec) {
2603 SDValue HiVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2604 AArch64II::MO_TPREL_G1);
2605 SDValue LoVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2606 AArch64II::MO_TPREL_G0_NC);
2608 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZxii, DL, PtrVT, HiVar,
2609 DAG.getTargetConstant(1, MVT::i32)), 0);
2610 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKxii, DL, PtrVT,
2612 DAG.getTargetConstant(0, MVT::i32)), 0);
2613 } else if (Model == TLSModel::GeneralDynamic) {
2614 // Accesses used in this sequence go via the TLS descriptor which lives in
2615 // the GOT. Prepare an address we can use to handle this.
2616 SDValue HiDesc = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2617 AArch64II::MO_TLSDESC);
2618 SDValue LoDesc = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2619 AArch64II::MO_TLSDESC_LO12);
2620 SDValue DescAddr = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2622 DAG.getConstant(8, MVT::i32));
2623 SDValue SymAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0);
2625 TPOff = LowerTLSDescCall(SymAddr, DescAddr, DL, DAG);
2626 } else if (Model == TLSModel::LocalDynamic) {
2627 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
2628 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
2629 // the beginning of the module's TLS region, followed by a DTPREL offset
2632 // These accesses will need deduplicating if there's more than one.
2633 AArch64MachineFunctionInfo* MFI = DAG.getMachineFunction()
2634 .getInfo<AArch64MachineFunctionInfo>();
2635 MFI->incNumLocalDynamicTLSAccesses();
2638 // Get the location of _TLS_MODULE_BASE_:
2639 SDValue HiDesc = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2640 AArch64II::MO_TLSDESC);
2641 SDValue LoDesc = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2642 AArch64II::MO_TLSDESC_LO12);
2643 SDValue DescAddr = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
2645 DAG.getConstant(8, MVT::i32));
2646 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT);
2648 ThreadBase = LowerTLSDescCall(SymAddr, DescAddr, DL, DAG);
2650 // Get the variable's offset from _TLS_MODULE_BASE_
2651 SDValue HiVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2652 AArch64II::MO_DTPREL_G1);
2653 SDValue LoVar = DAG.getTargetGlobalAddress(GV, DL, MVT::i64, 0,
2654 AArch64II::MO_DTPREL_G0_NC);
2656 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZxii, DL, PtrVT, HiVar,
2657 DAG.getTargetConstant(0, MVT::i32)), 0);
2658 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKxii, DL, PtrVT,
2660 DAG.getTargetConstant(0, MVT::i32)), 0);
2662 llvm_unreachable("Unsupported TLS access model");
2665 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
2668 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2671 EVT VT = Op.getValueType();
2672 SDValue Vec = Op.getOperand(0);
2673 unsigned Opc = IsSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
2675 if (VT.getVectorNumElements() == 1) {
2676 assert(VT == MVT::v1f64 && "Unexpected vector type!");
2677 if (VT.getSizeInBits() == Vec.getValueSizeInBits())
2679 return DAG.UnrollVectorOp(Op.getNode());
2682 if (VT.getSizeInBits() < Vec.getValueSizeInBits()) {
2683 assert(Vec.getValueType() == MVT::v2i64 && VT == MVT::v2f32 &&
2684 "Unexpected vector type!");
2685 Vec = DAG.getNode(Opc, dl, MVT::v2f64, Vec);
2686 return DAG.getNode(ISD::FP_ROUND, dl, VT, Vec, DAG.getIntPtrConstant(0));
2687 } else if (VT.getSizeInBits() > Vec.getValueSizeInBits()) {
2688 unsigned CastOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2689 EVT CastVT = EVT::getIntegerVT(*DAG.getContext(),
2690 VT.getVectorElementType().getSizeInBits());
2692 EVT::getVectorVT(*DAG.getContext(), CastVT, VT.getVectorNumElements());
2693 Vec = DAG.getNode(CastOpc, dl, CastVT, Vec);
2696 return DAG.getNode(Opc, dl, VT, Vec);
2700 AArch64TargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2701 bool IsSigned) const {
2702 if (Op.getValueType().isVector())
2703 return LowerVectorINT_TO_FP(Op, DAG, IsSigned);
2704 if (Op.getValueType() != MVT::f128) {
2705 // Legal for everything except f128.
2711 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
2713 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
2715 return LowerF128ToCall(Op, DAG, LC);
2720 AArch64TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2721 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2723 EVT PtrVT = getPointerTy();
2725 // When compiling PIC, jump tables get put in the code section so a static
2726 // relocation-style is acceptable for both cases.
2727 switch (getTargetMachine().getCodeModel()) {
2728 case CodeModel::Small:
2729 return DAG.getNode(AArch64ISD::WrapperSmall, dl, PtrVT,
2730 DAG.getTargetJumpTable(JT->getIndex(), PtrVT),
2731 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2732 AArch64II::MO_LO12),
2733 DAG.getConstant(1, MVT::i32));
2734 case CodeModel::Large:
2736 AArch64ISD::WrapperLarge, dl, PtrVT,
2737 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G3),
2738 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G2_NC),
2739 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G1_NC),
2740 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_ABS_G0_NC));
2742 llvm_unreachable("Only small and large code models supported now");
2746 // (SELECT testbit, iftrue, iffalse)
2748 AArch64TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2750 SDValue TheBit = Op.getOperand(0);
2751 SDValue IfTrue = Op.getOperand(1);
2752 SDValue IfFalse = Op.getOperand(2);
2754 // AArch64 BooleanContents is the default UndefinedBooleanContent, which means
2755 // that as the consumer we are responsible for ignoring rubbish in higher
2757 TheBit = DAG.getNode(ISD::AND, dl, MVT::i32, TheBit,
2758 DAG.getConstant(1, MVT::i32));
2759 SDValue A64CMP = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, TheBit,
2760 DAG.getConstant(0, TheBit.getValueType()),
2761 DAG.getCondCode(ISD::SETNE));
2763 return DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
2764 A64CMP, IfTrue, IfFalse,
2765 DAG.getConstant(A64CC::NE, MVT::i32));
2768 static SDValue LowerVectorSETCC(SDValue Op, SelectionDAG &DAG) {
2770 SDValue LHS = Op.getOperand(0);
2771 SDValue RHS = Op.getOperand(1);
2772 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2773 EVT VT = Op.getValueType();
2774 bool Invert = false;
2778 if (LHS.getValueType().isInteger()) {
2780 // Attempt to use Vector Integer Compare Mask Test instruction.
2781 // TST = icmp ne (and (op0, op1), zero).
2782 if (CC == ISD::SETNE) {
2783 if (((LHS.getOpcode() == ISD::AND) &&
2784 ISD::isBuildVectorAllZeros(RHS.getNode())) ||
2785 ((RHS.getOpcode() == ISD::AND) &&
2786 ISD::isBuildVectorAllZeros(LHS.getNode()))) {
2788 SDValue AndOp = (LHS.getOpcode() == ISD::AND) ? LHS : RHS;
2789 SDValue NewLHS = DAG.getNode(ISD::BITCAST, DL, VT, AndOp.getOperand(0));
2790 SDValue NewRHS = DAG.getNode(ISD::BITCAST, DL, VT, AndOp.getOperand(1));
2791 return DAG.getNode(AArch64ISD::NEON_TST, DL, VT, NewLHS, NewRHS);
2795 // Attempt to use Vector Integer Compare Mask against Zero instr (Signed).
2796 // Note: Compare against Zero does not support unsigned predicates.
2797 if ((ISD::isBuildVectorAllZeros(RHS.getNode()) ||
2798 ISD::isBuildVectorAllZeros(LHS.getNode())) &&
2799 !isUnsignedIntSetCC(CC)) {
2801 // If LHS is the zero value, swap operands and CondCode.
2802 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
2803 CC = getSetCCSwappedOperands(CC);
2808 // Ensure valid CondCode for Compare Mask against Zero instruction:
2809 // EQ, GE, GT, LE, LT.
2810 if (ISD::SETNE == CC) {
2815 // Using constant type to differentiate integer and FP compares with zero.
2816 Op1 = DAG.getConstant(0, MVT::i32);
2817 Opcode = AArch64ISD::NEON_CMPZ;
2820 // Attempt to use Vector Integer Compare Mask instr (Signed/Unsigned).
2821 // Ensure valid CondCode for Compare Mask instr: EQ, GE, GT, UGE, UGT.
2825 llvm_unreachable("Illegal integer comparison.");
2841 CC = getSetCCSwappedOperands(CC);
2845 std::swap(LHS, RHS);
2847 Opcode = AArch64ISD::NEON_CMP;
2852 // Generate Compare Mask instr or Compare Mask against Zero instr.
2854 DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(CC));
2857 NeonCmp = DAG.getNOT(DL, NeonCmp, VT);
2862 // Now handle Floating Point cases.
2863 // Attempt to use Vector Floating Point Compare Mask against Zero instruction.
2864 if (ISD::isBuildVectorAllZeros(RHS.getNode()) ||
2865 ISD::isBuildVectorAllZeros(LHS.getNode())) {
2867 // If LHS is the zero value, swap operands and CondCode.
2868 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
2869 CC = getSetCCSwappedOperands(CC);
2874 // Using constant type to differentiate integer and FP compares with zero.
2875 Op1 = DAG.getConstantFP(0, MVT::f32);
2876 Opcode = AArch64ISD::NEON_CMPZ;
2878 // Attempt to use Vector Floating Point Compare Mask instruction.
2881 Opcode = AArch64ISD::NEON_CMP;
2885 // Some register compares have to be implemented with swapped CC and operands,
2886 // e.g.: OLT implemented as OGT with swapped operands.
2887 bool SwapIfRegArgs = false;
2889 // Ensure valid CondCode for FP Compare Mask against Zero instruction:
2890 // EQ, GE, GT, LE, LT.
2891 // And ensure valid CondCode for FP Compare Mask instruction: EQ, GE, GT.
2894 llvm_unreachable("Illegal FP comparison");
2897 Invert = true; // Fallthrough
2905 SwapIfRegArgs = true;
2914 SwapIfRegArgs = true;
2923 SwapIfRegArgs = true;
2932 SwapIfRegArgs = true;
2939 Invert = true; // Fallthrough
2941 // Expand this to (OGT |OLT).
2943 DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(ISD::SETGT));
2945 SwapIfRegArgs = true;
2948 Invert = true; // Fallthrough
2950 // Expand this to (OGE | OLT).
2952 DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(ISD::SETGE));
2954 SwapIfRegArgs = true;
2958 if (Opcode == AArch64ISD::NEON_CMP && SwapIfRegArgs) {
2959 CC = getSetCCSwappedOperands(CC);
2960 std::swap(Op0, Op1);
2963 // Generate FP Compare Mask instr or FP Compare Mask against Zero instr
2964 SDValue NeonCmp = DAG.getNode(Opcode, DL, VT, Op0, Op1, DAG.getCondCode(CC));
2966 if (NeonCmpAlt.getNode())
2967 NeonCmp = DAG.getNode(ISD::OR, DL, VT, NeonCmp, NeonCmpAlt);
2970 NeonCmp = DAG.getNOT(DL, NeonCmp, VT);
2975 // (SETCC lhs, rhs, condcode)
2977 AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2979 SDValue LHS = Op.getOperand(0);
2980 SDValue RHS = Op.getOperand(1);
2981 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2982 EVT VT = Op.getValueType();
2985 return LowerVectorSETCC(Op, DAG);
2987 if (LHS.getValueType() == MVT::f128) {
2988 // f128 comparisons will be lowered to libcalls giving a valid LHS and RHS
2989 // for the rest of the function (some i32 or i64 values).
2990 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2992 // If softenSetCCOperands returned a scalar, use it.
2993 if (RHS.getNode() == 0) {
2994 assert(LHS.getValueType() == Op.getValueType() &&
2995 "Unexpected setcc expansion!");
3000 if (LHS.getValueType().isInteger()) {
3003 // Integers are handled in a separate function because the combinations of
3004 // immediates and tests can get hairy and we may want to fiddle things.
3005 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
3007 return DAG.getNode(AArch64ISD::SELECT_CC, dl, VT,
3008 CmpOp, DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3012 // Note that some LLVM floating-point CondCodes can't be lowered to a single
3013 // conditional branch, hence FPCCToA64CC can set a second test, where either
3014 // passing is sufficient.
3015 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
3016 CondCode = FPCCToA64CC(CC, Alternative);
3017 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
3018 SDValue CmpOp = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
3019 DAG.getCondCode(CC));
3020 SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, VT,
3021 CmpOp, DAG.getConstant(1, VT),
3022 DAG.getConstant(0, VT), A64cc);
3024 if (Alternative != A64CC::Invalid) {
3025 A64cc = DAG.getConstant(Alternative, MVT::i32);
3026 A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, VT, CmpOp,
3027 DAG.getConstant(1, VT), A64SELECT_CC, A64cc);
3030 return A64SELECT_CC;
3033 static SDValue LowerVectorSELECT_CC(SDValue Op, SelectionDAG &DAG) {
3035 SDValue LHS = Op.getOperand(0);
3036 SDValue RHS = Op.getOperand(1);
3037 SDValue IfTrue = Op.getOperand(2);
3038 SDValue IfFalse = Op.getOperand(3);
3039 EVT IfTrueVT = IfTrue.getValueType();
3040 EVT CondVT = IfTrueVT.changeVectorElementTypeToInteger();
3041 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3043 // If LHS & RHS are floating point and IfTrue & IfFalse are vectors, we will
3044 // use NEON compare.
3045 if ((LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64)) {
3046 EVT EltVT = LHS.getValueType();
3047 unsigned EltNum = 128 / EltVT.getSizeInBits();
3048 EVT VT = EVT::getVectorVT(*DAG.getContext(), EltVT, EltNum);
3049 unsigned SubConstant =
3050 (LHS.getValueType() == MVT::f32) ? AArch64::sub_32 :AArch64::sub_64;
3051 EVT CEltT = (LHS.getValueType() == MVT::f32) ? MVT::i32 : MVT::i64;
3052 EVT CVT = EVT::getVectorVT(*DAG.getContext(), CEltT, EltNum);
3055 = SDValue(DAG.getMachineNode(TargetOpcode::SUBREG_TO_REG, dl,
3056 VT, DAG.getTargetConstant(0, MVT::i32), LHS,
3057 DAG.getTargetConstant(SubConstant, MVT::i32)), 0);
3059 = SDValue(DAG.getMachineNode(TargetOpcode::SUBREG_TO_REG, dl,
3060 VT, DAG.getTargetConstant(0, MVT::i32), RHS,
3061 DAG.getTargetConstant(SubConstant, MVT::i32)), 0);
3063 SDValue VSetCC = DAG.getSetCC(dl, CVT, LHS, RHS, CC);
3064 SDValue ResCC = LowerVectorSETCC(VSetCC, DAG);
3065 if (CEltT.getSizeInBits() < IfTrueVT.getSizeInBits()) {
3067 EVT::getVectorVT(*DAG.getContext(), CEltT,
3068 IfTrueVT.getSizeInBits() / CEltT.getSizeInBits());
3069 ResCC = DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, DUPVT, ResCC,
3070 DAG.getConstant(0, MVT::i64, false));
3072 ResCC = DAG.getNode(ISD::BITCAST, dl, CondVT, ResCC);
3074 // FIXME: If IfTrue & IfFalse hold v1i8, v1i16 or v1i32, this function
3075 // can't handle them and will hit this assert.
3076 assert(CEltT.getSizeInBits() == IfTrueVT.getSizeInBits() &&
3077 "Vector of IfTrue & IfFalse is too small.");
3080 EltNum * IfTrueVT.getSizeInBits() / ResCC.getValueSizeInBits();
3081 EVT ExVT = EVT::getVectorVT(*DAG.getContext(), CEltT, ExEltNum);
3082 ResCC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ExVT, ResCC,
3083 DAG.getConstant(0, MVT::i64, false));
3084 ResCC = DAG.getNode(ISD::BITCAST, dl, CondVT, ResCC);
3086 SDValue VSelect = DAG.getNode(ISD::VSELECT, dl, IfTrue.getValueType(),
3087 ResCC, IfTrue, IfFalse);
3091 // Here we handle the case that LHS & RHS are integer and IfTrue & IfFalse are
3093 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
3094 CondCode = FPCCToA64CC(CC, Alternative);
3095 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
3096 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
3097 DAG.getCondCode(CC));
3098 EVT SEVT = MVT::i32;
3099 if (IfTrue.getValueType().getVectorElementType().getSizeInBits() > 32)
3101 SDValue AllOne = DAG.getConstant(-1, SEVT);
3102 SDValue AllZero = DAG.getConstant(0, SEVT);
3103 SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, SEVT, SetCC,
3104 AllOne, AllZero, A64cc);
3106 if (Alternative != A64CC::Invalid) {
3107 A64cc = DAG.getConstant(Alternative, MVT::i32);
3108 A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
3109 SetCC, AllOne, A64SELECT_CC, A64cc);
3112 if (IfTrue.getValueType().getVectorNumElements() == 1)
3113 VDup = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, CondVT, A64SELECT_CC);
3115 VDup = DAG.getNode(AArch64ISD::NEON_VDUP, dl, CondVT, A64SELECT_CC);
3116 SDValue VSelect = DAG.getNode(ISD::VSELECT, dl, IfTrue.getValueType(),
3117 VDup, IfTrue, IfFalse);
3121 // (SELECT_CC lhs, rhs, iftrue, iffalse, condcode)
3123 AArch64TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3125 SDValue LHS = Op.getOperand(0);
3126 SDValue RHS = Op.getOperand(1);
3127 SDValue IfTrue = Op.getOperand(2);
3128 SDValue IfFalse = Op.getOperand(3);
3129 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3131 if (IfTrue.getValueType().isVector())
3132 return LowerVectorSELECT_CC(Op, DAG);
3134 if (LHS.getValueType() == MVT::f128) {
3135 // f128 comparisons are lowered to libcalls, but slot in nicely here
3137 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3139 // If softenSetCCOperands returned a scalar, we need to compare the result
3140 // against zero to select between true and false values.
3141 if (RHS.getNode() == 0) {
3142 RHS = DAG.getConstant(0, LHS.getValueType());
3147 if (LHS.getValueType().isInteger()) {
3150 // Integers are handled in a separate function because the combinations of
3151 // immediates and tests can get hairy and we may want to fiddle things.
3152 SDValue CmpOp = getSelectableIntSetCC(LHS, RHS, CC, A64cc, DAG, dl);
3154 return DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(), CmpOp,
3155 IfTrue, IfFalse, A64cc);
3158 // Note that some LLVM floating-point CondCodes can't be lowered to a single
3159 // conditional branch, hence FPCCToA64CC can set a second test, where either
3160 // passing is sufficient.
3161 A64CC::CondCodes CondCode, Alternative = A64CC::Invalid;
3162 CondCode = FPCCToA64CC(CC, Alternative);
3163 SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
3164 SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
3165 DAG.getCondCode(CC));
3166 SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl,
3168 SetCC, IfTrue, IfFalse, A64cc);
3170 if (Alternative != A64CC::Invalid) {
3171 A64cc = DAG.getConstant(Alternative, MVT::i32);
3172 A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
3173 SetCC, IfTrue, A64SELECT_CC, A64cc);
3177 return A64SELECT_CC;
3181 AArch64TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
3182 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3183 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3185 // We have to make sure we copy the entire structure: 8+8+8+4+4 = 32 bytes
3186 // rather than just 8.
3187 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op),
3188 Op.getOperand(1), Op.getOperand(2),
3189 DAG.getConstant(32, MVT::i32), 8, false, false,
3190 MachinePointerInfo(DestSV), MachinePointerInfo(SrcSV));
3194 AArch64TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
3195 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3196 // Standard, section B.3.
3197 MachineFunction &MF = DAG.getMachineFunction();
3198 AArch64MachineFunctionInfo *FuncInfo
3199 = MF.getInfo<AArch64MachineFunctionInfo>();
3202 SDValue Chain = Op.getOperand(0);
3203 SDValue VAList = Op.getOperand(1);
3204 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3205 SmallVector<SDValue, 4> MemOps;
3207 // void *__stack at offset 0
3208 SDValue Stack = DAG.getFrameIndex(FuncInfo->getVariadicStackIdx(),
3210 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3211 MachinePointerInfo(SV), false, false, 0));
3213 // void *__gr_top at offset 8
3214 int GPRSize = FuncInfo->getVariadicGPRSize();
3216 SDValue GRTop, GRTopAddr;
3218 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3219 DAG.getConstant(8, getPointerTy()));
3221 GRTop = DAG.getFrameIndex(FuncInfo->getVariadicGPRIdx(), getPointerTy());
3222 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3223 DAG.getConstant(GPRSize, getPointerTy()));
3225 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3226 MachinePointerInfo(SV, 8),
3230 // void *__vr_top at offset 16
3231 int FPRSize = FuncInfo->getVariadicFPRSize();
3233 SDValue VRTop, VRTopAddr;
3234 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3235 DAG.getConstant(16, getPointerTy()));
3237 VRTop = DAG.getFrameIndex(FuncInfo->getVariadicFPRIdx(), getPointerTy());
3238 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3239 DAG.getConstant(FPRSize, getPointerTy()));
3241 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3242 MachinePointerInfo(SV, 16),
3246 // int __gr_offs at offset 24
3247 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3248 DAG.getConstant(24, getPointerTy()));
3249 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3250 GROffsAddr, MachinePointerInfo(SV, 24),
3253 // int __vr_offs at offset 28
3254 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3255 DAG.getConstant(28, getPointerTy()));
3256 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3257 VROffsAddr, MachinePointerInfo(SV, 28),
3260 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &MemOps[0],
3265 AArch64TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3266 switch (Op.getOpcode()) {
3267 default: llvm_unreachable("Don't know how to custom lower this!");
3268 case ISD::FADD: return LowerF128ToCall(Op, DAG, RTLIB::ADD_F128);
3269 case ISD::FSUB: return LowerF128ToCall(Op, DAG, RTLIB::SUB_F128);
3270 case ISD::FMUL: return LowerF128ToCall(Op, DAG, RTLIB::MUL_F128);
3271 case ISD::FDIV: return LowerF128ToCall(Op, DAG, RTLIB::DIV_F128);
3272 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, true);
3273 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG, false);
3274 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG, true);
3275 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG, false);
3276 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
3277 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
3278 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3279 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3281 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3282 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
3283 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3284 case ISD::GlobalAddress: return LowerGlobalAddressELF(Op, DAG);
3285 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3286 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3287 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3288 case ISD::SELECT: return LowerSELECT(Op, DAG);
3289 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3290 case ISD::SETCC: return LowerSETCC(Op, DAG);
3291 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
3292 case ISD::VASTART: return LowerVASTART(Op, DAG);
3293 case ISD::BUILD_VECTOR:
3294 return LowerBUILD_VECTOR(Op, DAG, getSubtarget());
3295 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3296 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3302 /// Check if the specified splat value corresponds to a valid vector constant
3303 /// for a Neon instruction with a "modified immediate" operand (e.g., MOVI). If
3304 /// so, return the encoded 8-bit immediate and the OpCmode instruction fields
3306 static bool isNeonModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3307 unsigned SplatBitSize, SelectionDAG &DAG,
3308 bool is128Bits, NeonModImmType type, EVT &VT,
3309 unsigned &Imm, unsigned &OpCmode) {
3310 switch (SplatBitSize) {
3312 llvm_unreachable("unexpected size for isNeonModifiedImm");
3314 if (type != Neon_Mov_Imm)
3316 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3317 // Neon movi per byte: Op=0, Cmode=1110.
3320 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3324 // Neon move inst per halfword
3325 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3326 if ((SplatBits & ~0xff) == 0) {
3327 // Value = 0x00nn is 0x00nn LSL 0
3328 // movi: Op=0, Cmode=1000; mvni: Op=1, Cmode=1000
3329 // bic: Op=1, Cmode=1001; orr: Op=0, Cmode=1001
3335 if ((SplatBits & ~0xff00) == 0) {
3336 // Value = 0xnn00 is 0x00nn LSL 8
3337 // movi: Op=0, Cmode=1010; mvni: Op=1, Cmode=1010
3338 // bic: Op=1, Cmode=1011; orr: Op=0, Cmode=1011
3340 Imm = SplatBits >> 8;
3344 // can't handle any other
3349 // First the LSL variants (MSL is unusable by some interested instructions).
3351 // Neon move instr per word, shift zeros
3352 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3353 if ((SplatBits & ~0xff) == 0) {
3354 // Value = 0x000000nn is 0x000000nn LSL 0
3355 // movi: Op=0, Cmode= 0000; mvni: Op=1, Cmode= 0000
3356 // bic: Op=1, Cmode= 0001; orr: Op=0, Cmode= 0001
3362 if ((SplatBits & ~0xff00) == 0) {
3363 // Value = 0x0000nn00 is 0x000000nn LSL 8
3364 // movi: Op=0, Cmode= 0010; mvni: Op=1, Cmode= 0010
3365 // bic: Op=1, Cmode= 0011; orr : Op=0, Cmode= 0011
3367 Imm = SplatBits >> 8;
3371 if ((SplatBits & ~0xff0000) == 0) {
3372 // Value = 0x00nn0000 is 0x000000nn LSL 16
3373 // movi: Op=0, Cmode= 0100; mvni: Op=1, Cmode= 0100
3374 // bic: Op=1, Cmode= 0101; orr: Op=0, Cmode= 0101
3376 Imm = SplatBits >> 16;
3380 if ((SplatBits & ~0xff000000) == 0) {
3381 // Value = 0xnn000000 is 0x000000nn LSL 24
3382 // movi: Op=0, Cmode= 0110; mvni: Op=1, Cmode= 0110
3383 // bic: Op=1, Cmode= 0111; orr: Op=0, Cmode= 0111
3385 Imm = SplatBits >> 24;
3390 // Now the MSL immediates.
3392 // Neon move instr per word, shift ones
3393 if ((SplatBits & ~0xffff) == 0 &&
3394 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3395 // Value = 0x0000nnff is 0x000000nn MSL 8
3396 // movi: Op=0, Cmode= 1100; mvni: Op=1, Cmode= 1100
3398 Imm = SplatBits >> 8;
3402 if ((SplatBits & ~0xffffff) == 0 &&
3403 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3404 // Value = 0x00nnffff is 0x000000nn MSL 16
3405 // movi: Op=1, Cmode= 1101; mvni: Op=1, Cmode= 1101
3407 Imm = SplatBits >> 16;
3411 // can't handle any other
3416 if (type != Neon_Mov_Imm)
3418 // Neon move instr bytemask, where each byte is either 0x00 or 0xff.
3419 // movi Op=1, Cmode=1110.
3421 uint64_t BitMask = 0xff;
3423 unsigned ImmMask = 1;
3425 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3426 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3429 } else if ((SplatBits & BitMask) != 0) {
3436 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3444 static SDValue PerformANDCombine(SDNode *N,
3445 TargetLowering::DAGCombinerInfo &DCI) {
3447 SelectionDAG &DAG = DCI.DAG;
3449 EVT VT = N->getValueType(0);
3451 // We're looking for an SRA/SHL pair which form an SBFX.
3453 if (VT != MVT::i32 && VT != MVT::i64)
3456 if (!isa<ConstantSDNode>(N->getOperand(1)))
3459 uint64_t TruncMask = N->getConstantOperandVal(1);
3460 if (!isMask_64(TruncMask))
3463 uint64_t Width = CountPopulation_64(TruncMask);
3464 SDValue Shift = N->getOperand(0);
3466 if (Shift.getOpcode() != ISD::SRL)
3469 if (!isa<ConstantSDNode>(Shift->getOperand(1)))
3471 uint64_t LSB = Shift->getConstantOperandVal(1);
3473 if (LSB > VT.getSizeInBits() || Width > VT.getSizeInBits())
3476 return DAG.getNode(AArch64ISD::UBFX, DL, VT, Shift.getOperand(0),
3477 DAG.getConstant(LSB, MVT::i64),
3478 DAG.getConstant(LSB + Width - 1, MVT::i64));
3481 /// For a true bitfield insert, the bits getting into that contiguous mask
3482 /// should come from the low part of an existing value: they must be formed from
3483 /// a compatible SHL operation (unless they're already low). This function
3484 /// checks that condition and returns the least-significant bit that's
3485 /// intended. If the operation not a field preparation, -1 is returned.
3486 static int32_t getLSBForBFI(SelectionDAG &DAG, SDLoc DL, EVT VT,
3487 SDValue &MaskedVal, uint64_t Mask) {
3488 if (!isShiftedMask_64(Mask))
3491 // Now we need to alter MaskedVal so that it is an appropriate input for a BFI
3492 // instruction. BFI will do a left-shift by LSB before applying the mask we've
3493 // spotted, so in general we should pre-emptively "undo" that by making sure
3494 // the incoming bits have had a right-shift applied to them.
3496 // This right shift, however, will combine with existing left/right shifts. In
3497 // the simplest case of a completely straight bitfield operation, it will be
3498 // expected to completely cancel out with an existing SHL. More complicated
3499 // cases (e.g. bitfield to bitfield copy) may still need a real shift before
3502 uint64_t LSB = countTrailingZeros(Mask);
3503 int64_t ShiftRightRequired = LSB;
3504 if (MaskedVal.getOpcode() == ISD::SHL &&
3505 isa<ConstantSDNode>(MaskedVal.getOperand(1))) {
3506 ShiftRightRequired -= MaskedVal.getConstantOperandVal(1);
3507 MaskedVal = MaskedVal.getOperand(0);
3508 } else if (MaskedVal.getOpcode() == ISD::SRL &&
3509 isa<ConstantSDNode>(MaskedVal.getOperand(1))) {
3510 ShiftRightRequired += MaskedVal.getConstantOperandVal(1);
3511 MaskedVal = MaskedVal.getOperand(0);
3514 if (ShiftRightRequired > 0)
3515 MaskedVal = DAG.getNode(ISD::SRL, DL, VT, MaskedVal,
3516 DAG.getConstant(ShiftRightRequired, MVT::i64));
3517 else if (ShiftRightRequired < 0) {
3518 // We could actually end up with a residual left shift, for example with
3519 // "struc.bitfield = val << 1".
3520 MaskedVal = DAG.getNode(ISD::SHL, DL, VT, MaskedVal,
3521 DAG.getConstant(-ShiftRightRequired, MVT::i64));
3527 /// Searches from N for an existing AArch64ISD::BFI node, possibly surrounded by
3528 /// a mask and an extension. Returns true if a BFI was found and provides
3529 /// information on its surroundings.
3530 static bool findMaskedBFI(SDValue N, SDValue &BFI, uint64_t &Mask,
3533 if (N.getOpcode() == ISD::ZERO_EXTEND) {
3535 N = N.getOperand(0);
3538 if (N.getOpcode() == ISD::AND && isa<ConstantSDNode>(N.getOperand(1))) {
3539 Mask = N->getConstantOperandVal(1);
3540 N = N.getOperand(0);
3542 // Mask is the whole width.
3543 Mask = -1ULL >> (64 - N.getValueType().getSizeInBits());
3546 if (N.getOpcode() == AArch64ISD::BFI) {
3554 /// Try to combine a subtree (rooted at an OR) into a "masked BFI" node, which
3555 /// is roughly equivalent to (and (BFI ...), mask). This form is used because it
3556 /// can often be further combined with a larger mask. Ultimately, we want mask
3557 /// to be 2^32-1 or 2^64-1 so the AND can be skipped.
3558 static SDValue tryCombineToBFI(SDNode *N,
3559 TargetLowering::DAGCombinerInfo &DCI,
3560 const AArch64Subtarget *Subtarget) {
3561 SelectionDAG &DAG = DCI.DAG;
3563 EVT VT = N->getValueType(0);
3565 assert(N->getOpcode() == ISD::OR && "Unexpected root");
3567 // We need the LHS to be (and SOMETHING, MASK). Find out what that mask is or
3568 // abandon the effort.
3569 SDValue LHS = N->getOperand(0);
3570 if (LHS.getOpcode() != ISD::AND)
3574 if (isa<ConstantSDNode>(LHS.getOperand(1)))
3575 LHSMask = LHS->getConstantOperandVal(1);
3579 // We also need the RHS to be (and SOMETHING, MASK). Find out what that mask
3580 // is or abandon the effort.
3581 SDValue RHS = N->getOperand(1);
3582 if (RHS.getOpcode() != ISD::AND)
3586 if (isa<ConstantSDNode>(RHS.getOperand(1)))
3587 RHSMask = RHS->getConstantOperandVal(1);
3591 // Can't do anything if the masks are incompatible.
3592 if (LHSMask & RHSMask)
3595 // Now we need one of the masks to be a contiguous field. Without loss of
3596 // generality that should be the RHS one.
3597 SDValue Bitfield = LHS.getOperand(0);
3598 if (getLSBForBFI(DAG, DL, VT, Bitfield, LHSMask) != -1) {
3599 // We know that LHS is a candidate new value, and RHS isn't already a better
3601 std::swap(LHS, RHS);
3602 std::swap(LHSMask, RHSMask);
3605 // We've done our best to put the right operands in the right places, all we
3606 // can do now is check whether a BFI exists.
3607 Bitfield = RHS.getOperand(0);
3608 int32_t LSB = getLSBForBFI(DAG, DL, VT, Bitfield, RHSMask);
3612 uint32_t Width = CountPopulation_64(RHSMask);
3613 assert(Width && "Expected non-zero bitfield width");
3615 SDValue BFI = DAG.getNode(AArch64ISD::BFI, DL, VT,
3616 LHS.getOperand(0), Bitfield,
3617 DAG.getConstant(LSB, MVT::i64),
3618 DAG.getConstant(Width, MVT::i64));
3621 if ((LHSMask | RHSMask) == (-1ULL >> (64 - VT.getSizeInBits())))
3624 return DAG.getNode(ISD::AND, DL, VT, BFI,
3625 DAG.getConstant(LHSMask | RHSMask, VT));
3628 /// Search for the bitwise combining (with careful masks) of a MaskedBFI and its
3629 /// original input. This is surprisingly common because SROA splits things up
3630 /// into i8 chunks, so the originally detected MaskedBFI may actually only act
3631 /// on the low (say) byte of a word. This is then orred into the rest of the
3632 /// word afterwards.
3634 /// Basic input: (or (and OLDFIELD, MASK1), (MaskedBFI MASK2, OLDFIELD, ...)).
3636 /// If MASK1 and MASK2 are compatible, we can fold the whole thing into the
3637 /// MaskedBFI. We can also deal with a certain amount of extend/truncate being
3639 static SDValue tryCombineToLargerBFI(SDNode *N,
3640 TargetLowering::DAGCombinerInfo &DCI,
3641 const AArch64Subtarget *Subtarget) {
3642 SelectionDAG &DAG = DCI.DAG;
3644 EVT VT = N->getValueType(0);
3646 // First job is to hunt for a MaskedBFI on either the left or right. Swap
3647 // operands if it's actually on the right.
3649 SDValue PossExtraMask;
3650 uint64_t ExistingMask = 0;
3651 bool Extended = false;
3652 if (findMaskedBFI(N->getOperand(0), BFI, ExistingMask, Extended))
3653 PossExtraMask = N->getOperand(1);
3654 else if (findMaskedBFI(N->getOperand(1), BFI, ExistingMask, Extended))
3655 PossExtraMask = N->getOperand(0);
3659 // We can only combine a BFI with another compatible mask.
3660 if (PossExtraMask.getOpcode() != ISD::AND ||
3661 !isa<ConstantSDNode>(PossExtraMask.getOperand(1)))
3664 uint64_t ExtraMask = PossExtraMask->getConstantOperandVal(1);
3666 // Masks must be compatible.
3667 if (ExtraMask & ExistingMask)
3670 SDValue OldBFIVal = BFI.getOperand(0);
3671 SDValue NewBFIVal = BFI.getOperand(1);
3673 // We skipped a ZERO_EXTEND above, so the input to the MaskedBFIs should be
3674 // 32-bit and we'll be forming a 64-bit MaskedBFI. The MaskedBFI arguments
3675 // need to be made compatible.
3676 assert(VT == MVT::i64 && BFI.getValueType() == MVT::i32
3677 && "Invalid types for BFI");
3678 OldBFIVal = DAG.getNode(ISD::ANY_EXTEND, DL, VT, OldBFIVal);
3679 NewBFIVal = DAG.getNode(ISD::ANY_EXTEND, DL, VT, NewBFIVal);
3682 // We need the MaskedBFI to be combined with a mask of the *same* value.
3683 if (PossExtraMask.getOperand(0) != OldBFIVal)
3686 BFI = DAG.getNode(AArch64ISD::BFI, DL, VT,
3687 OldBFIVal, NewBFIVal,
3688 BFI.getOperand(2), BFI.getOperand(3));
3690 // If the masking is trivial, we don't need to create it.
3691 if ((ExtraMask | ExistingMask) == (-1ULL >> (64 - VT.getSizeInBits())))
3694 return DAG.getNode(ISD::AND, DL, VT, BFI,
3695 DAG.getConstant(ExtraMask | ExistingMask, VT));
3698 /// An EXTR instruction is made up of two shifts, ORed together. This helper
3699 /// searches for and classifies those shifts.
3700 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
3702 if (N.getOpcode() == ISD::SHL)
3704 else if (N.getOpcode() == ISD::SRL)
3709 if (!isa<ConstantSDNode>(N.getOperand(1)))
3712 ShiftAmount = N->getConstantOperandVal(1);
3713 Src = N->getOperand(0);
3717 /// EXTR instruction extracts a contiguous chunk of bits from two existing
3718 /// registers viewed as a high/low pair. This function looks for the pattern:
3719 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
3720 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
3722 static SDValue tryCombineToEXTR(SDNode *N,
3723 TargetLowering::DAGCombinerInfo &DCI) {
3724 SelectionDAG &DAG = DCI.DAG;
3726 EVT VT = N->getValueType(0);
3728 assert(N->getOpcode() == ISD::OR && "Unexpected root");
3730 if (VT != MVT::i32 && VT != MVT::i64)
3734 uint32_t ShiftLHS = 0;
3736 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
3740 uint32_t ShiftRHS = 0;
3742 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
3745 // If they're both trying to come from the high part of the register, they're
3746 // not really an EXTR.
3747 if (LHSFromHi == RHSFromHi)
3750 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
3754 std::swap(LHS, RHS);
3755 std::swap(ShiftLHS, ShiftRHS);
3758 return DAG.getNode(AArch64ISD::EXTR, DL, VT,
3760 DAG.getConstant(ShiftRHS, MVT::i64));
3763 /// Target-specific dag combine xforms for ISD::OR
3764 static SDValue PerformORCombine(SDNode *N,
3765 TargetLowering::DAGCombinerInfo &DCI,
3766 const AArch64Subtarget *Subtarget) {
3768 SelectionDAG &DAG = DCI.DAG;
3770 EVT VT = N->getValueType(0);
3772 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
3775 // Attempt to recognise bitfield-insert operations.
3776 SDValue Res = tryCombineToBFI(N, DCI, Subtarget);
3780 // Attempt to combine an existing MaskedBFI operation into one with a larger
3782 Res = tryCombineToLargerBFI(N, DCI, Subtarget);
3786 Res = tryCombineToEXTR(N, DCI);
3790 if (!Subtarget->hasNEON())
3793 // Attempt to use vector immediate-form BSL
3794 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
3796 SDValue N0 = N->getOperand(0);
3797 if (N0.getOpcode() != ISD::AND)
3800 SDValue N1 = N->getOperand(1);
3801 if (N1.getOpcode() != ISD::AND)
3804 if (VT.isVector() && DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
3806 unsigned SplatBitSize;
3808 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
3810 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
3813 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
3815 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
3816 HasAnyUndefs) && !HasAnyUndefs &&
3817 SplatBits0.getBitWidth() == SplatBits1.getBitWidth() &&
3818 SplatBits0 == ~SplatBits1) {
3820 return DAG.getNode(ISD::VSELECT, DL, VT, N0->getOperand(1),
3821 N0->getOperand(0), N1->getOperand(0));
3829 /// Target-specific dag combine xforms for ISD::SRA
3830 static SDValue PerformSRACombine(SDNode *N,
3831 TargetLowering::DAGCombinerInfo &DCI) {
3833 SelectionDAG &DAG = DCI.DAG;
3835 EVT VT = N->getValueType(0);
3837 // We're looking for an SRA/SHL pair which form an SBFX.
3839 if (VT != MVT::i32 && VT != MVT::i64)
3842 if (!isa<ConstantSDNode>(N->getOperand(1)))
3845 uint64_t ExtraSignBits = N->getConstantOperandVal(1);
3846 SDValue Shift = N->getOperand(0);
3848 if (Shift.getOpcode() != ISD::SHL)
3851 if (!isa<ConstantSDNode>(Shift->getOperand(1)))
3854 uint64_t BitsOnLeft = Shift->getConstantOperandVal(1);
3855 uint64_t Width = VT.getSizeInBits() - ExtraSignBits;
3856 uint64_t LSB = VT.getSizeInBits() - Width - BitsOnLeft;
3858 if (LSB > VT.getSizeInBits() || Width > VT.getSizeInBits())
3861 return DAG.getNode(AArch64ISD::SBFX, DL, VT, Shift.getOperand(0),
3862 DAG.getConstant(LSB, MVT::i64),
3863 DAG.getConstant(LSB + Width - 1, MVT::i64));
3866 /// Check if this is a valid build_vector for the immediate operand of
3867 /// a vector shift operation, where all the elements of the build_vector
3868 /// must have the same constant integer value.
3869 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
3870 // Ignore bit_converts.
3871 while (Op.getOpcode() == ISD::BITCAST)
3872 Op = Op.getOperand(0);
3873 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3874 APInt SplatBits, SplatUndef;
3875 unsigned SplatBitSize;
3877 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
3878 HasAnyUndefs, ElementBits) ||
3879 SplatBitSize > ElementBits)
3881 Cnt = SplatBits.getSExtValue();
3885 /// Check if this is a valid build_vector for the immediate operand of
3886 /// a vector shift left operation. That value must be in the range:
3887 /// 0 <= Value < ElementBits
3888 static bool isVShiftLImm(SDValue Op, EVT VT, int64_t &Cnt) {
3889 assert(VT.isVector() && "vector shift count is not a vector type");
3890 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3891 if (!getVShiftImm(Op, ElementBits, Cnt))
3893 return (Cnt >= 0 && Cnt < ElementBits);
3896 /// Check if this is a valid build_vector for the immediate operand of a
3897 /// vector shift right operation. The value must be in the range:
3898 /// 1 <= Value <= ElementBits
3899 static bool isVShiftRImm(SDValue Op, EVT VT, int64_t &Cnt) {
3900 assert(VT.isVector() && "vector shift count is not a vector type");
3901 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3902 if (!getVShiftImm(Op, ElementBits, Cnt))
3904 return (Cnt >= 1 && Cnt <= ElementBits);
3907 static SDValue GenForSextInreg(SDNode *N,
3908 TargetLowering::DAGCombinerInfo &DCI,
3909 EVT SrcVT, EVT DestVT, EVT SubRegVT,
3910 const int *Mask, SDValue Src) {
3911 SelectionDAG &DAG = DCI.DAG;
3913 = DAG.getNode(ISD::BITCAST, SDLoc(N), SrcVT, Src);
3915 = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), DestVT, Bitcast);
3917 = DAG.getVectorShuffle(DestVT, SDLoc(N), Sext, DAG.getUNDEF(DestVT), Mask);
3918 SDValue ExtractSubreg
3919 = SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, SDLoc(N),
3920 SubRegVT, ShuffleVec,
3921 DAG.getTargetConstant(AArch64::sub_64, MVT::i32)), 0);
3922 return ExtractSubreg;
3925 /// Checks for vector shifts and lowers them.
3926 static SDValue PerformShiftCombine(SDNode *N,
3927 TargetLowering::DAGCombinerInfo &DCI,
3928 const AArch64Subtarget *ST) {
3929 SelectionDAG &DAG = DCI.DAG;
3930 EVT VT = N->getValueType(0);
3931 if (N->getOpcode() == ISD::SRA && (VT == MVT::i32 || VT == MVT::i64))
3932 return PerformSRACombine(N, DCI);
3934 // We're looking for an SRA/SHL pair to help generating instruction
3935 // sshll v0.8h, v0.8b, #0
3936 // The instruction STXL is also the alias of this instruction.
3938 // For example, for DAG like below,
3939 // v2i32 = sra (v2i32 (shl v2i32, 16)), 16
3940 // we can transform it into
3941 // v2i32 = EXTRACT_SUBREG
3942 // (v4i32 (suffle_vector
3943 // (v4i32 (sext (v4i16 (bitcast v2i32))),
3944 // undef, (0, 2, u, u)),
3947 // With this transformation we expect to generate "SSHLL + UZIP1"
3948 // Sometimes UZIP1 can be optimized away by combining with other context.
3949 int64_t ShrCnt, ShlCnt;
3950 if (N->getOpcode() == ISD::SRA
3951 && (VT == MVT::v2i32 || VT == MVT::v4i16)
3952 && isVShiftRImm(N->getOperand(1), VT, ShrCnt)
3953 && N->getOperand(0).getOpcode() == ISD::SHL
3954 && isVShiftRImm(N->getOperand(0).getOperand(1), VT, ShlCnt)) {
3955 SDValue Src = N->getOperand(0).getOperand(0);
3956 if (VT == MVT::v2i32 && ShrCnt == 16 && ShlCnt == 16) {
3957 // sext_inreg(v2i32, v2i16)
3958 // We essentially only care the Mask {0, 2, u, u}
3959 int Mask[4] = {0, 2, 4, 6};
3960 return GenForSextInreg(N, DCI, MVT::v4i16, MVT::v4i32, MVT::v2i32,
3963 else if (VT == MVT::v2i32 && ShrCnt == 24 && ShlCnt == 24) {
3964 // sext_inreg(v2i16, v2i8)
3965 // We essentially only care the Mask {0, u, 4, u, u, u, u, u, u, u, u, u}
3966 int Mask[8] = {0, 2, 4, 6, 8, 10, 12, 14};
3967 return GenForSextInreg(N, DCI, MVT::v8i8, MVT::v8i16, MVT::v2i32,
3970 else if (VT == MVT::v4i16 && ShrCnt == 8 && ShlCnt == 8) {
3971 // sext_inreg(v4i16, v4i8)
3972 // We essentially only care the Mask {0, 2, 4, 6, u, u, u, u, u, u, u, u}
3973 int Mask[8] = {0, 2, 4, 6, 8, 10, 12, 14};
3974 return GenForSextInreg(N, DCI, MVT::v8i8, MVT::v8i16, MVT::v4i16,
3979 // Nothing to be done for scalar shifts.
3980 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3981 if (!VT.isVector() || !TLI.isTypeLegal(VT))
3984 assert(ST->hasNEON() && "unexpected vector shift");
3987 switch (N->getOpcode()) {
3989 llvm_unreachable("unexpected shift opcode");
3992 if (isVShiftLImm(N->getOperand(1), VT, Cnt)) {
3994 DAG.getNode(AArch64ISD::NEON_VDUP, SDLoc(N->getOperand(1)), VT,
3995 DAG.getConstant(Cnt, MVT::i32));
3996 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0), RHS);
4002 if (isVShiftRImm(N->getOperand(1), VT, Cnt)) {
4004 DAG.getNode(AArch64ISD::NEON_VDUP, SDLoc(N->getOperand(1)), VT,
4005 DAG.getConstant(Cnt, MVT::i32));
4006 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N->getOperand(0), RHS);
4014 /// ARM-specific DAG combining for intrinsics.
4015 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
4016 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4020 // Don't do anything for most intrinsics.
4023 case Intrinsic::arm_neon_vqshifts:
4024 case Intrinsic::arm_neon_vqshiftu:
4025 EVT VT = N->getOperand(1).getValueType();
4027 if (!isVShiftLImm(N->getOperand(2), VT, Cnt))
4029 unsigned VShiftOpc = (IntNo == Intrinsic::arm_neon_vqshifts)
4030 ? AArch64ISD::NEON_QSHLs
4031 : AArch64ISD::NEON_QSHLu;
4032 return DAG.getNode(VShiftOpc, SDLoc(N), N->getValueType(0),
4033 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
4039 /// Target-specific DAG combine function for NEON load/store intrinsics
4040 /// to merge base address updates.
4041 static SDValue CombineBaseUpdate(SDNode *N,
4042 TargetLowering::DAGCombinerInfo &DCI) {
4043 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4046 SelectionDAG &DAG = DCI.DAG;
4047 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
4048 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
4049 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
4050 SDValue Addr = N->getOperand(AddrOpIdx);
4052 // Search for a use of the address operand that is an increment.
4053 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
4054 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
4056 if (User->getOpcode() != ISD::ADD ||
4057 UI.getUse().getResNo() != Addr.getResNo())
4060 // Check that the add is independent of the load/store. Otherwise, folding
4061 // it would create a cycle.
4062 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
4065 // Find the new opcode for the updating load/store.
4067 bool isLaneOp = false;
4068 unsigned NewOpc = 0;
4069 unsigned NumVecs = 0;
4071 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
4073 default: llvm_unreachable("unexpected intrinsic for Neon base update");
4074 case Intrinsic::arm_neon_vld1: NewOpc = AArch64ISD::NEON_LD1_UPD;
4076 case Intrinsic::arm_neon_vld2: NewOpc = AArch64ISD::NEON_LD2_UPD;
4078 case Intrinsic::arm_neon_vld3: NewOpc = AArch64ISD::NEON_LD3_UPD;
4080 case Intrinsic::arm_neon_vld4: NewOpc = AArch64ISD::NEON_LD4_UPD;
4082 case Intrinsic::arm_neon_vst1: NewOpc = AArch64ISD::NEON_ST1_UPD;
4083 NumVecs = 1; isLoad = false; break;
4084 case Intrinsic::arm_neon_vst2: NewOpc = AArch64ISD::NEON_ST2_UPD;
4085 NumVecs = 2; isLoad = false; break;
4086 case Intrinsic::arm_neon_vst3: NewOpc = AArch64ISD::NEON_ST3_UPD;
4087 NumVecs = 3; isLoad = false; break;
4088 case Intrinsic::arm_neon_vst4: NewOpc = AArch64ISD::NEON_ST4_UPD;
4089 NumVecs = 4; isLoad = false; break;
4090 case Intrinsic::aarch64_neon_vld1x2: NewOpc = AArch64ISD::NEON_LD1x2_UPD;
4092 case Intrinsic::aarch64_neon_vld1x3: NewOpc = AArch64ISD::NEON_LD1x3_UPD;
4094 case Intrinsic::aarch64_neon_vld1x4: NewOpc = AArch64ISD::NEON_LD1x4_UPD;
4096 case Intrinsic::aarch64_neon_vst1x2: NewOpc = AArch64ISD::NEON_ST1x2_UPD;
4097 NumVecs = 2; isLoad = false; break;
4098 case Intrinsic::aarch64_neon_vst1x3: NewOpc = AArch64ISD::NEON_ST1x3_UPD;
4099 NumVecs = 3; isLoad = false; break;
4100 case Intrinsic::aarch64_neon_vst1x4: NewOpc = AArch64ISD::NEON_ST1x4_UPD;
4101 NumVecs = 4; isLoad = false; break;
4102 case Intrinsic::arm_neon_vld2lane: NewOpc = AArch64ISD::NEON_LD2LN_UPD;
4103 NumVecs = 2; isLaneOp = true; break;
4104 case Intrinsic::arm_neon_vld3lane: NewOpc = AArch64ISD::NEON_LD3LN_UPD;
4105 NumVecs = 3; isLaneOp = true; break;
4106 case Intrinsic::arm_neon_vld4lane: NewOpc = AArch64ISD::NEON_LD4LN_UPD;
4107 NumVecs = 4; isLaneOp = true; break;
4108 case Intrinsic::arm_neon_vst2lane: NewOpc = AArch64ISD::NEON_ST2LN_UPD;
4109 NumVecs = 2; isLoad = false; isLaneOp = true; break;
4110 case Intrinsic::arm_neon_vst3lane: NewOpc = AArch64ISD::NEON_ST3LN_UPD;
4111 NumVecs = 3; isLoad = false; isLaneOp = true; break;
4112 case Intrinsic::arm_neon_vst4lane: NewOpc = AArch64ISD::NEON_ST4LN_UPD;
4113 NumVecs = 4; isLoad = false; isLaneOp = true; break;
4117 switch (N->getOpcode()) {
4118 default: llvm_unreachable("unexpected opcode for Neon base update");
4119 case AArch64ISD::NEON_LD2DUP: NewOpc = AArch64ISD::NEON_LD2DUP_UPD;
4121 case AArch64ISD::NEON_LD3DUP: NewOpc = AArch64ISD::NEON_LD3DUP_UPD;
4123 case AArch64ISD::NEON_LD4DUP: NewOpc = AArch64ISD::NEON_LD4DUP_UPD;
4128 // Find the size of memory referenced by the load/store.
4131 VecTy = N->getValueType(0);
4133 VecTy = N->getOperand(AddrOpIdx + 1).getValueType();
4134 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
4136 NumBytes /= VecTy.getVectorNumElements();
4138 // If the increment is a constant, it must match the memory ref size.
4139 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
4140 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
4141 uint32_t IncVal = CInc->getZExtValue();
4142 if (IncVal != NumBytes)
4144 Inc = DAG.getTargetConstant(IncVal, MVT::i32);
4147 // Create the new updating load/store node.
4149 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
4151 for (n = 0; n < NumResultVecs; ++n)
4153 Tys[n++] = MVT::i64;
4154 Tys[n] = MVT::Other;
4155 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs + 2);
4156 SmallVector<SDValue, 8> Ops;
4157 Ops.push_back(N->getOperand(0)); // incoming chain
4158 Ops.push_back(N->getOperand(AddrOpIdx));
4160 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
4161 Ops.push_back(N->getOperand(i));
4163 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
4164 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys,
4165 Ops.data(), Ops.size(),
4166 MemInt->getMemoryVT(),
4167 MemInt->getMemOperand());
4170 std::vector<SDValue> NewResults;
4171 for (unsigned i = 0; i < NumResultVecs; ++i) {
4172 NewResults.push_back(SDValue(UpdN.getNode(), i));
4174 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1)); // chain
4175 DCI.CombineTo(N, NewResults);
4176 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
4183 /// For a VDUPLANE node N, check if its source operand is a vldN-lane (N > 1)
4184 /// intrinsic, and if all the other uses of that intrinsic are also VDUPLANEs.
4185 /// If so, combine them to a vldN-dup operation and return true.
4186 static SDValue CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
4187 SelectionDAG &DAG = DCI.DAG;
4188 EVT VT = N->getValueType(0);
4190 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
4191 SDNode *VLD = N->getOperand(0).getNode();
4192 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
4194 unsigned NumVecs = 0;
4195 unsigned NewOpc = 0;
4196 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
4197 if (IntNo == Intrinsic::arm_neon_vld2lane) {
4199 NewOpc = AArch64ISD::NEON_LD2DUP;
4200 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
4202 NewOpc = AArch64ISD::NEON_LD3DUP;
4203 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
4205 NewOpc = AArch64ISD::NEON_LD4DUP;
4210 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
4211 // numbers match the load.
4212 unsigned VLDLaneNo =
4213 cast<ConstantSDNode>(VLD->getOperand(NumVecs + 3))->getZExtValue();
4214 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
4216 // Ignore uses of the chain result.
4217 if (UI.getUse().getResNo() == NumVecs)
4220 if (User->getOpcode() != AArch64ISD::NEON_VDUPLANE ||
4221 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
4225 // Create the vldN-dup node.
4228 for (n = 0; n < NumVecs; ++n)
4230 Tys[n] = MVT::Other;
4231 SDVTList SDTys = DAG.getVTList(Tys, NumVecs + 1);
4232 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
4233 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
4234 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys, Ops, 2,
4235 VLDMemInt->getMemoryVT(),
4236 VLDMemInt->getMemOperand());
4239 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
4241 unsigned ResNo = UI.getUse().getResNo();
4242 // Ignore uses of the chain result.
4243 if (ResNo == NumVecs)
4246 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
4249 // Now the vldN-lane intrinsic is dead except for its chain result.
4250 // Update uses of the chain.
4251 std::vector<SDValue> VLDDupResults;
4252 for (unsigned n = 0; n < NumVecs; ++n)
4253 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
4254 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
4255 DCI.CombineTo(VLD, VLDDupResults);
4257 return SDValue(N, 0);
4261 // v1i1 (bitcast (i1 setcc (extract_vector_elt, extract_vector_elt))
4262 // FIXME: Currently the type legalizer can't handle SETCC having v1i1 as result.
4263 // If it can legalize "v1i1 SETCC" correctly, no need to combine such SETCC.
4264 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
4265 EVT ResVT = N->getValueType(0);
4267 if (!ResVT.isVector() || ResVT.getVectorNumElements() != 1 ||
4268 ResVT.getVectorElementType() != MVT::i1)
4271 SDValue LHS = N->getOperand(0);
4272 SDValue RHS = N->getOperand(1);
4273 EVT CmpVT = LHS.getValueType();
4274 LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
4275 CmpVT.getVectorElementType(), LHS,
4276 DAG.getConstant(0, MVT::i64));
4277 RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
4278 CmpVT.getVectorElementType(), RHS,
4279 DAG.getConstant(0, MVT::i64));
4281 DAG.getSetCC(SDLoc(N), MVT::i1, LHS, RHS,
4282 cast<CondCodeSDNode>(N->getOperand(2))->get());
4283 return DAG.getNode(ISD::BITCAST, SDLoc(N), ResVT, SetCC);
4286 // vselect (v1i1 setcc) ->
4287 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
4288 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
4289 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
4291 static SDValue PerformVSelectCombine(SDNode *N, SelectionDAG &DAG) {
4292 SDValue N0 = N->getOperand(0);
4293 EVT CCVT = N0.getValueType();
4295 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
4296 CCVT.getVectorElementType() != MVT::i1)
4299 EVT ResVT = N->getValueType(0);
4300 EVT CmpVT = N0.getOperand(0).getValueType();
4301 // Only combine when the result type is of the same size as the compared
4303 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
4306 SDValue IfTrue = N->getOperand(1);
4307 SDValue IfFalse = N->getOperand(2);
4309 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
4310 N0.getOperand(0), N0.getOperand(1),
4311 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4312 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
4316 // sign_extend (extract_vector_elt (v1i1 setcc)) ->
4317 // extract_vector_elt (v1iXX setcc)
4318 // (XX is the size of the compared operand type)
4319 static SDValue PerformSignExtendCombine(SDNode *N, SelectionDAG &DAG) {
4320 SDValue N0 = N->getOperand(0);
4321 SDValue Vec = N0.getOperand(0);
4323 if (N0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4324 Vec.getOpcode() != ISD::SETCC)
4327 EVT ResVT = N->getValueType(0);
4328 EVT CmpVT = Vec.getOperand(0).getValueType();
4329 // Only optimize when the result type is of the same size as the element
4330 // type of the compared operand.
4331 if (ResVT.getSizeInBits() != CmpVT.getVectorElementType().getSizeInBits())
4334 SDValue Lane = N0.getOperand(1);
4336 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
4337 Vec.getOperand(0), Vec.getOperand(1),
4338 cast<CondCodeSDNode>(Vec.getOperand(2))->get());
4339 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), ResVT,
4344 AArch64TargetLowering::PerformDAGCombine(SDNode *N,
4345 DAGCombinerInfo &DCI) const {
4346 switch (N->getOpcode()) {
4348 case ISD::AND: return PerformANDCombine(N, DCI);
4349 case ISD::OR: return PerformORCombine(N, DCI, getSubtarget());
4353 return PerformShiftCombine(N, DCI, getSubtarget());
4354 case ISD::SETCC: return PerformSETCCCombine(N, DCI.DAG);
4355 case ISD::VSELECT: return PerformVSelectCombine(N, DCI.DAG);
4356 case ISD::SIGN_EXTEND: return PerformSignExtendCombine(N, DCI.DAG);
4357 case ISD::INTRINSIC_WO_CHAIN:
4358 return PerformIntrinsicCombine(N, DCI.DAG);
4359 case AArch64ISD::NEON_VDUPLANE:
4360 return CombineVLDDUP(N, DCI);
4361 case AArch64ISD::NEON_LD2DUP:
4362 case AArch64ISD::NEON_LD3DUP:
4363 case AArch64ISD::NEON_LD4DUP:
4364 return CombineBaseUpdate(N, DCI);
4365 case ISD::INTRINSIC_VOID:
4366 case ISD::INTRINSIC_W_CHAIN:
4367 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
4368 case Intrinsic::arm_neon_vld1:
4369 case Intrinsic::arm_neon_vld2:
4370 case Intrinsic::arm_neon_vld3:
4371 case Intrinsic::arm_neon_vld4:
4372 case Intrinsic::arm_neon_vst1:
4373 case Intrinsic::arm_neon_vst2:
4374 case Intrinsic::arm_neon_vst3:
4375 case Intrinsic::arm_neon_vst4:
4376 case Intrinsic::arm_neon_vld2lane:
4377 case Intrinsic::arm_neon_vld3lane:
4378 case Intrinsic::arm_neon_vld4lane:
4379 case Intrinsic::aarch64_neon_vld1x2:
4380 case Intrinsic::aarch64_neon_vld1x3:
4381 case Intrinsic::aarch64_neon_vld1x4:
4382 case Intrinsic::aarch64_neon_vst1x2:
4383 case Intrinsic::aarch64_neon_vst1x3:
4384 case Intrinsic::aarch64_neon_vst1x4:
4385 case Intrinsic::arm_neon_vst2lane:
4386 case Intrinsic::arm_neon_vst3lane:
4387 case Intrinsic::arm_neon_vst4lane:
4388 return CombineBaseUpdate(N, DCI);
4397 AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
4398 VT = VT.getScalarType();
4403 switch (VT.getSimpleVT().SimpleTy) {
4416 // Check whether a shuffle_vector could be presented as concat_vector.
4417 bool AArch64TargetLowering::isConcatVector(SDValue Op, SelectionDAG &DAG,
4418 SDValue V0, SDValue V1,
4420 SDValue &Res) const {
4422 EVT VT = Op.getValueType();
4423 if (VT.getSizeInBits() != 128)
4425 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4426 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4429 unsigned NumElts = VT.getVectorNumElements();
4430 bool isContactVector = true;
4431 bool splitV0 = false;
4432 if (V0.getValueType().getSizeInBits() == 128)
4435 for (int I = 0, E = NumElts / 2; I != E; I++) {
4437 isContactVector = false;
4442 if (isContactVector) {
4443 int offset = NumElts / 2;
4444 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4445 if (Mask[I] != I + splitV0 * offset) {
4446 isContactVector = false;
4452 if (isContactVector) {
4453 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4456 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4457 DAG.getConstant(0, MVT::i64));
4459 if (V1.getValueType().getSizeInBits() == 128) {
4460 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4461 DAG.getConstant(0, MVT::i64));
4463 Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4469 // Check whether a Build Vector could be presented as Shuffle Vector.
4470 // This Shuffle Vector maybe not legalized, so the length of its operand and
4471 // the length of result may not equal.
4472 bool AArch64TargetLowering::isKnownShuffleVector(SDValue Op, SelectionDAG &DAG,
4473 SDValue &V0, SDValue &V1,
4476 EVT VT = Op.getValueType();
4477 unsigned NumElts = VT.getVectorNumElements();
4478 unsigned V0NumElts = 0;
4480 // Check if all elements are extracted from less than 3 vectors.
4481 for (unsigned i = 0; i < NumElts; ++i) {
4482 SDValue Elt = Op.getOperand(i);
4483 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4484 Elt.getOperand(0).getValueType().getVectorElementType() !=
4485 VT.getVectorElementType())
4488 if (V0.getNode() == 0) {
4489 V0 = Elt.getOperand(0);
4490 V0NumElts = V0.getValueType().getVectorNumElements();
4492 if (Elt.getOperand(0) == V0) {
4493 Mask[i] = (cast<ConstantSDNode>(Elt->getOperand(1))->getZExtValue());
4495 } else if (V1.getNode() == 0) {
4496 V1 = Elt.getOperand(0);
4498 if (Elt.getOperand(0) == V1) {
4499 unsigned Lane = cast<ConstantSDNode>(Elt->getOperand(1))->getZExtValue();
4500 Mask[i] = (Lane + V0NumElts);
4509 // If this is a case we can't handle, return null and let the default
4510 // expansion code take care of it.
4512 AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
4513 const AArch64Subtarget *ST) const {
4515 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
4517 EVT VT = Op.getValueType();
4519 APInt SplatBits, SplatUndef;
4520 unsigned SplatBitSize;
4523 unsigned UseNeonMov = VT.getSizeInBits() >= 64;
4525 // Note we favor lowering MOVI over MVNI.
4526 // This has implications on the definition of patterns in TableGen to select
4527 // BIC immediate instructions but not ORR immediate instructions.
4528 // If this lowering order is changed, TableGen patterns for BIC immediate and
4529 // ORR immediate instructions have to be updated.
4531 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4532 if (SplatBitSize <= 64) {
4533 // First attempt to use vector immediate-form MOVI
4536 unsigned OpCmode = 0;
4538 if (isNeonModifiedImm(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
4539 SplatBitSize, DAG, VT.is128BitVector(),
4540 Neon_Mov_Imm, NeonMovVT, Imm, OpCmode)) {
4541 SDValue ImmVal = DAG.getTargetConstant(Imm, MVT::i32);
4542 SDValue OpCmodeVal = DAG.getConstant(OpCmode, MVT::i32);
4544 if (ImmVal.getNode() && OpCmodeVal.getNode()) {
4545 SDValue NeonMov = DAG.getNode(AArch64ISD::NEON_MOVIMM, DL, NeonMovVT,
4546 ImmVal, OpCmodeVal);
4547 return DAG.getNode(ISD::BITCAST, DL, VT, NeonMov);
4551 // Then attempt to use vector immediate-form MVNI
4552 uint64_t NegatedImm = (~SplatBits).getZExtValue();
4553 if (isNeonModifiedImm(NegatedImm, SplatUndef.getZExtValue(), SplatBitSize,
4554 DAG, VT.is128BitVector(), Neon_Mvn_Imm, NeonMovVT,
4556 SDValue ImmVal = DAG.getTargetConstant(Imm, MVT::i32);
4557 SDValue OpCmodeVal = DAG.getConstant(OpCmode, MVT::i32);
4558 if (ImmVal.getNode() && OpCmodeVal.getNode()) {
4559 SDValue NeonMov = DAG.getNode(AArch64ISD::NEON_MVNIMM, DL, NeonMovVT,
4560 ImmVal, OpCmodeVal);
4561 return DAG.getNode(ISD::BITCAST, DL, VT, NeonMov);
4565 // Attempt to use vector immediate-form FMOV
4566 if (((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) ||
4567 (VT == MVT::v2f64 && SplatBitSize == 64)) {
4569 SplatBitSize == 32 ? APFloat::IEEEsingle : APFloat::IEEEdouble,
4572 if (A64Imms::isFPImm(RealVal, ImmVal)) {
4573 SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32);
4574 return DAG.getNode(AArch64ISD::NEON_FMOVIMM, DL, VT, Val);
4580 unsigned NumElts = VT.getVectorNumElements();
4581 bool isOnlyLowElement = true;
4582 bool usesOnlyOneValue = true;
4583 bool hasDominantValue = false;
4584 bool isConstant = true;
4586 // Map of the number of times a particular SDValue appears in the
4588 DenseMap<SDValue, unsigned> ValueCounts;
4590 for (unsigned i = 0; i < NumElts; ++i) {
4591 SDValue V = Op.getOperand(i);
4592 if (V.getOpcode() == ISD::UNDEF)
4595 isOnlyLowElement = false;
4596 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
4599 ValueCounts.insert(std::make_pair(V, 0));
4600 unsigned &Count = ValueCounts[V];
4602 // Is this value dominant? (takes up more than half of the lanes)
4603 if (++Count > (NumElts / 2)) {
4604 hasDominantValue = true;
4608 if (ValueCounts.size() != 1)
4609 usesOnlyOneValue = false;
4610 if (!Value.getNode() && ValueCounts.size() > 0)
4611 Value = ValueCounts.begin()->first;
4613 if (ValueCounts.size() == 0)
4614 return DAG.getUNDEF(VT);
4616 if (isOnlyLowElement)
4617 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value);
4619 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4620 if (hasDominantValue && EltSize <= 64) {
4621 // Use VDUP for non-constant splats.
4625 // If we are DUPing a value that comes directly from a vector, we could
4626 // just use DUPLANE. We can only do this if the lane being extracted
4627 // is at a constant index, as the DUP from lane instructions only have
4628 // constant-index forms.
4630 // If there is a TRUNCATE between EXTRACT_VECTOR_ELT and DUP, we can
4631 // remove TRUNCATE for DUPLANE by apdating the source vector to
4632 // appropriate vector type and lane index.
4634 // FIXME: for now we have v1i8, v1i16, v1i32 legal vector types, if they
4635 // are not legal any more, no need to check the type size in bits should
4636 // be large than 64.
4638 if (Value->getOpcode() == ISD::TRUNCATE)
4639 V = Value->getOperand(0);
4640 if (V->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4641 isa<ConstantSDNode>(V->getOperand(1)) &&
4642 V->getOperand(0).getValueType().getSizeInBits() >= 64) {
4644 // If the element size of source vector is larger than DUPLANE
4645 // element size, we can do transformation by,
4646 // 1) bitcasting source register to smaller element vector
4647 // 2) mutiplying the lane index by SrcEltSize/ResEltSize
4648 // For example, we can lower
4649 // "v8i16 vdup_lane(v4i32, 1)"
4651 // "v8i16 vdup_lane(v8i16 bitcast(v4i32), 2)".
4652 SDValue SrcVec = V->getOperand(0);
4653 unsigned SrcEltSize =
4654 SrcVec.getValueType().getVectorElementType().getSizeInBits();
4655 unsigned ResEltSize = VT.getVectorElementType().getSizeInBits();
4656 if (SrcEltSize > ResEltSize) {
4657 assert((SrcEltSize % ResEltSize == 0) && "Invalid element size");
4659 unsigned SrcSize = SrcVec.getValueType().getSizeInBits();
4660 unsigned ResSize = VT.getSizeInBits();
4662 if (SrcSize > ResSize) {
4663 assert((SrcSize % ResSize == 0) && "Invalid vector size");
4665 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4666 SrcSize / ResEltSize);
4667 BitCast = DAG.getNode(ISD::BITCAST, DL, CastVT, SrcVec);
4669 assert((SrcSize == ResSize) && "Invalid vector size of source vec");
4670 BitCast = DAG.getNode(ISD::BITCAST, DL, VT, SrcVec);
4673 unsigned LaneIdx = V->getConstantOperandVal(1);
4675 DAG.getConstant((SrcEltSize / ResEltSize) * LaneIdx, MVT::i64);
4676 N = DAG.getNode(AArch64ISD::NEON_VDUPLANE, DL, VT, BitCast, Lane);
4678 assert((SrcEltSize == ResEltSize) &&
4679 "Invalid element size of source vec");
4680 N = DAG.getNode(AArch64ISD::NEON_VDUPLANE, DL, VT, V->getOperand(0),
4684 N = DAG.getNode(AArch64ISD::NEON_VDUP, DL, VT, Value);
4686 if (!usesOnlyOneValue) {
4687 // The dominant value was splatted as 'N', but we now have to insert
4688 // all differing elements.
4689 for (unsigned I = 0; I < NumElts; ++I) {
4690 if (Op.getOperand(I) == Value)
4692 SmallVector<SDValue, 3> Ops;
4694 Ops.push_back(Op.getOperand(I));
4695 Ops.push_back(DAG.getConstant(I, MVT::i64));
4696 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, &Ops[0], 3);
4701 if (usesOnlyOneValue && isConstant) {
4702 return DAG.getNode(AArch64ISD::NEON_VDUP, DL, VT, Value);
4705 // If all elements are constants and the case above didn't get hit, fall back
4706 // to the default expansion, which will generate a load from the constant
4711 // Try to lower this in lowering ShuffleVector way.
4714 if (isKnownShuffleVector(Op, DAG, V0, V1, Mask)) {
4715 unsigned V0NumElts = V0.getValueType().getVectorNumElements();
4716 if (!V1.getNode() && V0NumElts == NumElts * 2) {
4717 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V0,
4718 DAG.getConstant(NumElts, MVT::i64));
4719 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V0,
4720 DAG.getConstant(0, MVT::i64));
4721 V0NumElts = V0.getValueType().getVectorNumElements();
4724 if (V1.getNode() && NumElts == V0NumElts &&
4725 V0NumElts == V1.getValueType().getVectorNumElements()) {
4726 SDValue Shuffle = DAG.getVectorShuffle(VT, DL, V0, V1, Mask);
4727 if (Shuffle.getOpcode() != ISD::VECTOR_SHUFFLE)
4730 return LowerVECTOR_SHUFFLE(Shuffle, DAG);
4733 if (isConcatVector(Op, DAG, V0, V1, Mask, Res))
4738 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
4739 // know the default expansion would otherwise fall back on something even
4740 // worse. For a vector with one or two non-undef values, that's
4741 // scalar_to_vector for the elements followed by a shuffle (provided the
4742 // shuffle is valid for the target) and materialization element by element
4743 // on the stack followed by a load for everything else.
4744 if (!isConstant && !usesOnlyOneValue) {
4745 SDValue Vec = DAG.getUNDEF(VT);
4746 for (unsigned i = 0 ; i < NumElts; ++i) {
4747 SDValue V = Op.getOperand(i);
4748 if (V.getOpcode() == ISD::UNDEF)
4750 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
4751 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Vec, V, LaneIdx);
4758 /// isREVMask - Check if a vector shuffle corresponds to a REV
4759 /// instruction with the specified blocksize. (The order of the elements
4760 /// within each block of the vector is reversed.)
4761 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4762 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4763 "Only possible block sizes for REV are: 16, 32, 64");
4765 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4769 unsigned NumElts = VT.getVectorNumElements();
4770 unsigned BlockElts = M[0] + 1;
4771 // If the first shuffle index is UNDEF, be optimistic.
4773 BlockElts = BlockSize / EltSz;
4775 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4778 for (unsigned i = 0; i < NumElts; ++i) {
4780 continue; // ignore UNDEF indices
4781 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4788 // isPermuteMask - Check whether the vector shuffle matches to UZP, ZIP and
4790 static unsigned isPermuteMask(ArrayRef<int> M, EVT VT, bool isV2undef) {
4791 unsigned NumElts = VT.getVectorNumElements();
4795 bool ismatch = true;
4798 for (unsigned i = 0; i < NumElts; ++i) {
4799 unsigned answer = i * 2;
4800 if (isV2undef && answer >= NumElts)
4802 if (M[i] != -1 && (unsigned)M[i] != answer) {
4808 return AArch64ISD::NEON_UZP1;
4812 for (unsigned i = 0; i < NumElts; ++i) {
4813 unsigned answer = i * 2 + 1;
4814 if (isV2undef && answer >= NumElts)
4816 if (M[i] != -1 && (unsigned)M[i] != answer) {
4822 return AArch64ISD::NEON_UZP2;
4826 for (unsigned i = 0; i < NumElts; ++i) {
4827 unsigned answer = i / 2 + NumElts * (i % 2);
4828 if (isV2undef && answer >= NumElts)
4830 if (M[i] != -1 && (unsigned)M[i] != answer) {
4836 return AArch64ISD::NEON_ZIP1;
4840 for (unsigned i = 0; i < NumElts; ++i) {
4841 unsigned answer = (NumElts + i) / 2 + NumElts * (i % 2);
4842 if (isV2undef && answer >= NumElts)
4844 if (M[i] != -1 && (unsigned)M[i] != answer) {
4850 return AArch64ISD::NEON_ZIP2;
4854 for (unsigned i = 0; i < NumElts; ++i) {
4855 unsigned answer = i + (NumElts - 1) * (i % 2);
4856 if (isV2undef && answer >= NumElts)
4858 if (M[i] != -1 && (unsigned)M[i] != answer) {
4864 return AArch64ISD::NEON_TRN1;
4868 for (unsigned i = 0; i < NumElts; ++i) {
4869 unsigned answer = 1 + i + (NumElts - 1) * (i % 2);
4870 if (isV2undef && answer >= NumElts)
4872 if (M[i] != -1 && (unsigned)M[i] != answer) {
4878 return AArch64ISD::NEON_TRN2;
4884 AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4885 SelectionDAG &DAG) const {
4886 SDValue V1 = Op.getOperand(0);
4887 SDValue V2 = Op.getOperand(1);
4889 EVT VT = Op.getValueType();
4890 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4892 // Convert shuffles that are directly supported on NEON to target-specific
4893 // DAG nodes, instead of keeping them as shuffles and matching them again
4894 // during code selection. This is more efficient and avoids the possibility
4895 // of inconsistencies between legalization and selection.
4896 ArrayRef<int> ShuffleMask = SVN->getMask();
4898 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4902 if (isREVMask(ShuffleMask, VT, 64))
4903 return DAG.getNode(AArch64ISD::NEON_REV64, dl, VT, V1);
4904 if (isREVMask(ShuffleMask, VT, 32))
4905 return DAG.getNode(AArch64ISD::NEON_REV32, dl, VT, V1);
4906 if (isREVMask(ShuffleMask, VT, 16))
4907 return DAG.getNode(AArch64ISD::NEON_REV16, dl, VT, V1);
4910 if (V2.getOpcode() == ISD::UNDEF)
4911 ISDNo = isPermuteMask(ShuffleMask, VT, true);
4913 ISDNo = isPermuteMask(ShuffleMask, VT, false);
4916 if (V2.getOpcode() == ISD::UNDEF)
4917 return DAG.getNode(ISDNo, dl, VT, V1, V1);
4919 return DAG.getNode(ISDNo, dl, VT, V1, V2);
4923 if (isConcatVector(Op, DAG, V1, V2, &ShuffleMask[0], Res))
4926 // If the element of shuffle mask are all the same constant, we can
4927 // transform it into either NEON_VDUP or NEON_VDUPLANE
4928 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
4929 int Lane = SVN->getSplatIndex();
4930 // If this is undef splat, generate it via "just" vdup, if possible.
4931 if (Lane == -1) Lane = 0;
4933 // Test if V1 is a SCALAR_TO_VECTOR.
4934 if (V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4935 return DAG.getNode(AArch64ISD::NEON_VDUP, dl, VT, V1.getOperand(0));
4937 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR.
4938 if (V1.getOpcode() == ISD::BUILD_VECTOR) {
4939 bool IsScalarToVector = true;
4940 for (unsigned i = 0, e = V1.getNumOperands(); i != e; ++i)
4941 if (V1.getOperand(i).getOpcode() != ISD::UNDEF &&
4942 i != (unsigned)Lane) {
4943 IsScalarToVector = false;
4946 if (IsScalarToVector)
4947 return DAG.getNode(AArch64ISD::NEON_VDUP, dl, VT,
4948 V1.getOperand(Lane));
4951 // Test if V1 is a EXTRACT_SUBVECTOR.
4952 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
4953 int ExtLane = cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
4954 return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1.getOperand(0),
4955 DAG.getConstant(Lane + ExtLane, MVT::i64));
4957 // Test if V1 is a CONCAT_VECTORS.
4958 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
4959 V1.getOperand(1).getOpcode() == ISD::UNDEF) {
4960 SDValue Op0 = V1.getOperand(0);
4961 assert((unsigned)Lane < Op0.getValueType().getVectorNumElements() &&
4962 "Invalid vector lane access");
4963 return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, Op0,
4964 DAG.getConstant(Lane, MVT::i64));
4967 return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1,
4968 DAG.getConstant(Lane, MVT::i64));
4971 int Length = ShuffleMask.size();
4972 int V1EltNum = V1.getValueType().getVectorNumElements();
4974 // If the number of v1 elements is the same as the number of shuffle mask
4975 // element and the shuffle masks are sequential values, we can transform
4976 // it into NEON_VEXTRACT.
4977 if (V1EltNum == Length) {
4978 // Check if the shuffle mask is sequential.
4980 while (ShuffleMask[SkipUndef] == -1) {
4983 int CurMask = ShuffleMask[SkipUndef];
4984 if (CurMask >= SkipUndef) {
4985 bool IsSequential = true;
4986 for (int I = SkipUndef; I < Length; ++I) {
4987 if (ShuffleMask[I] != -1 && ShuffleMask[I] != CurMask) {
4988 IsSequential = false;
4994 assert((EltSize % 8 == 0) && "Bitsize of vector element is incorrect");
4995 unsigned VecSize = EltSize * V1EltNum;
4996 unsigned Index = (EltSize / 8) * (ShuffleMask[SkipUndef] - SkipUndef);
4997 if (VecSize == 64 || VecSize == 128)
4998 return DAG.getNode(AArch64ISD::NEON_VEXTRACT, dl, VT, V1, V2,
4999 DAG.getConstant(Index, MVT::i64));
5004 // For shuffle mask like "0, 1, 2, 3, 4, 5, 13, 7", try to generate insert
5005 // by element from V2 to V1 .
5006 // If shuffle mask is like "0, 1, 10, 11, 12, 13, 14, 15", V2 would be a
5007 // better choice to be inserted than V1 as less insert needed, so we count
5008 // element to be inserted for both V1 and V2, and select less one as insert
5011 // Collect elements need to be inserted and their index.
5012 SmallVector<int, 8> NV1Elt;
5013 SmallVector<int, 8> N1Index;
5014 SmallVector<int, 8> NV2Elt;
5015 SmallVector<int, 8> N2Index;
5016 for (int I = 0; I != Length; ++I) {
5017 if (ShuffleMask[I] != I) {
5018 NV1Elt.push_back(ShuffleMask[I]);
5019 N1Index.push_back(I);
5022 for (int I = 0; I != Length; ++I) {
5023 if (ShuffleMask[I] != (I + V1EltNum)) {
5024 NV2Elt.push_back(ShuffleMask[I]);
5025 N2Index.push_back(I);
5029 // Decide which to be inserted. If all lanes mismatch, neither V1 nor V2
5030 // will be inserted.
5032 SmallVector<int, 8> InsMasks = NV1Elt;
5033 SmallVector<int, 8> InsIndex = N1Index;
5034 if ((int)NV1Elt.size() != Length || (int)NV2Elt.size() != Length) {
5035 if (NV1Elt.size() > NV2Elt.size()) {
5041 InsV = DAG.getNode(ISD::UNDEF, dl, VT);
5044 for (int I = 0, E = InsMasks.size(); I != E; ++I) {
5046 int Mask = InsMasks[I];
5047 if (Mask >= V1EltNum) {
5051 // Any value type smaller than i32 is illegal in AArch64, and this lower
5052 // function is called after legalize pass, so we need to legalize
5055 if (VT.getVectorElementType().isFloatingPoint())
5056 EltVT = (EltSize == 64) ? MVT::f64 : MVT::f32;
5058 EltVT = (EltSize == 64) ? MVT::i64 : MVT::i32;
5061 ExtV = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, ExtV,
5062 DAG.getConstant(Mask, MVT::i64));
5063 InsV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, InsV, ExtV,
5064 DAG.getConstant(InsIndex[I], MVT::i64));
5070 AArch64TargetLowering::ConstraintType
5071 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
5072 if (Constraint.size() == 1) {
5073 switch (Constraint[0]) {
5075 case 'w': // An FP/SIMD vector register
5076 return C_RegisterClass;
5077 case 'I': // Constant that can be used with an ADD instruction
5078 case 'J': // Constant that can be used with a SUB instruction
5079 case 'K': // Constant that can be used with a 32-bit logical instruction
5080 case 'L': // Constant that can be used with a 64-bit logical instruction
5081 case 'M': // Constant that can be used as a 32-bit MOV immediate
5082 case 'N': // Constant that can be used as a 64-bit MOV immediate
5083 case 'Y': // Floating point constant zero
5084 case 'Z': // Integer constant zero
5086 case 'Q': // A memory reference with base register and no offset
5088 case 'S': // A symbolic address
5093 // FIXME: Ump, Utf, Usa, Ush
5094 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes,
5095 // whatever they may be
5096 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
5097 // Usa: An absolute symbolic address
5098 // Ush: The high part (bits 32:12) of a pc-relative symbolic address
5099 assert(Constraint != "Ump" && Constraint != "Utf" && Constraint != "Usa"
5100 && Constraint != "Ush" && "Unimplemented constraints");
5102 return TargetLowering::getConstraintType(Constraint);
5105 TargetLowering::ConstraintWeight
5106 AArch64TargetLowering::getSingleConstraintMatchWeight(AsmOperandInfo &Info,
5107 const char *Constraint) const {
5109 llvm_unreachable("Constraint weight unimplemented");
5113 AArch64TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5114 std::string &Constraint,
5115 std::vector<SDValue> &Ops,
5116 SelectionDAG &DAG) const {
5117 SDValue Result(0, 0);
5119 // Only length 1 constraints are C_Other.
5120 if (Constraint.size() != 1) return;
5122 // Only C_Other constraints get lowered like this. That means constants for us
5123 // so return early if there's no hope the constraint can be lowered.
5125 switch(Constraint[0]) {
5127 case 'I': case 'J': case 'K': case 'L':
5128 case 'M': case 'N': case 'Z': {
5129 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
5133 uint64_t CVal = C->getZExtValue();
5136 switch (Constraint[0]) {
5138 // FIXME: 'M' and 'N' are MOV pseudo-insts -- unsupported in assembly. 'J'
5139 // is a peculiarly useless SUB constraint.
5140 llvm_unreachable("Unimplemented C_Other constraint");
5146 if (A64Imms::isLogicalImm(32, CVal, Bits))
5150 if (A64Imms::isLogicalImm(64, CVal, Bits))
5159 Result = DAG.getTargetConstant(CVal, Op.getValueType());
5163 // An absolute symbolic address or label reference.
5164 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
5165 Result = DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op),
5166 GA->getValueType(0));
5167 } else if (const BlockAddressSDNode *BA
5168 = dyn_cast<BlockAddressSDNode>(Op)) {
5169 Result = DAG.getTargetBlockAddress(BA->getBlockAddress(),
5170 BA->getValueType(0));
5171 } else if (const ExternalSymbolSDNode *ES
5172 = dyn_cast<ExternalSymbolSDNode>(Op)) {
5173 Result = DAG.getTargetExternalSymbol(ES->getSymbol(),
5174 ES->getValueType(0));
5180 if (const ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) {
5181 if (CFP->isExactlyValue(0.0)) {
5182 Result = DAG.getTargetConstantFP(0.0, CFP->getValueType(0));
5189 if (Result.getNode()) {
5190 Ops.push_back(Result);
5194 // It's an unknown constraint for us. Let generic code have a go.
5195 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5198 std::pair<unsigned, const TargetRegisterClass*>
5199 AArch64TargetLowering::getRegForInlineAsmConstraint(
5200 const std::string &Constraint,
5202 if (Constraint.size() == 1) {
5203 switch (Constraint[0]) {
5205 if (VT.getSizeInBits() <= 32)
5206 return std::make_pair(0U, &AArch64::GPR32RegClass);
5207 else if (VT == MVT::i64)
5208 return std::make_pair(0U, &AArch64::GPR64RegClass);
5212 return std::make_pair(0U, &AArch64::FPR16RegClass);
5213 else if (VT == MVT::f32)
5214 return std::make_pair(0U, &AArch64::FPR32RegClass);
5215 else if (VT.getSizeInBits() == 64)
5216 return std::make_pair(0U, &AArch64::FPR64RegClass);
5217 else if (VT.getSizeInBits() == 128)
5218 return std::make_pair(0U, &AArch64::FPR128RegClass);
5223 // Use the default implementation in TargetLowering to convert the register
5224 // constraint into a member of a register class.
5225 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5228 /// Represent NEON load and store intrinsics as MemIntrinsicNodes.
5229 /// The associated MachineMemOperands record the alignment specified
5230 /// in the intrinsic calls.
5231 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5233 unsigned Intrinsic) const {
5234 switch (Intrinsic) {
5235 case Intrinsic::arm_neon_vld1:
5236 case Intrinsic::arm_neon_vld2:
5237 case Intrinsic::arm_neon_vld3:
5238 case Intrinsic::arm_neon_vld4:
5239 case Intrinsic::aarch64_neon_vld1x2:
5240 case Intrinsic::aarch64_neon_vld1x3:
5241 case Intrinsic::aarch64_neon_vld1x4:
5242 case Intrinsic::arm_neon_vld2lane:
5243 case Intrinsic::arm_neon_vld3lane:
5244 case Intrinsic::arm_neon_vld4lane: {
5245 Info.opc = ISD::INTRINSIC_W_CHAIN;
5246 // Conservatively set memVT to the entire set of vectors loaded.
5247 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
5248 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5249 Info.ptrVal = I.getArgOperand(0);
5251 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
5252 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
5253 Info.vol = false; // volatile loads with NEON intrinsics not supported
5254 Info.readMem = true;
5255 Info.writeMem = false;
5258 case Intrinsic::arm_neon_vst1:
5259 case Intrinsic::arm_neon_vst2:
5260 case Intrinsic::arm_neon_vst3:
5261 case Intrinsic::arm_neon_vst4:
5262 case Intrinsic::aarch64_neon_vst1x2:
5263 case Intrinsic::aarch64_neon_vst1x3:
5264 case Intrinsic::aarch64_neon_vst1x4:
5265 case Intrinsic::arm_neon_vst2lane:
5266 case Intrinsic::arm_neon_vst3lane:
5267 case Intrinsic::arm_neon_vst4lane: {
5268 Info.opc = ISD::INTRINSIC_VOID;
5269 // Conservatively set memVT to the entire set of vectors stored.
5270 unsigned NumElts = 0;
5271 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
5272 Type *ArgTy = I.getArgOperand(ArgI)->getType();
5273 if (!ArgTy->isVectorTy())
5275 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
5277 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5278 Info.ptrVal = I.getArgOperand(0);
5280 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
5281 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
5282 Info.vol = false; // volatile stores with NEON intrinsics not supported
5283 Info.readMem = false;
5284 Info.writeMem = true;