1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64PerfectShuffle.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64MachineFunctionInfo.h"
18 #include "AArch64TargetMachine.h"
19 #include "AArch64TargetObjectFile.h"
20 #include "MCTargetDesc/AArch64AddressingModes.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/Intrinsics.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
36 #define DEBUG_TYPE "aarch64-lower"
38 STATISTIC(NumTailCalls, "Number of tail calls");
39 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
46 static cl::opt<AlignMode>
47 Align(cl::desc("Load/store alignment support"),
48 cl::Hidden, cl::init(NoStrictAlign),
50 clEnumValN(StrictAlign, "aarch64-strict-align",
51 "Disallow all unaligned memory accesses"),
52 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
53 "Allow unaligned memory accesses"),
56 // Place holder until extr generation is tested fully.
58 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
59 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
63 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
64 cl::desc("Allow AArch64 SLI/SRI formation"),
67 //===----------------------------------------------------------------------===//
68 // AArch64 Lowering public interface.
69 //===----------------------------------------------------------------------===//
70 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
71 if (TT.isOSBinFormatMachO())
72 return new AArch64_MachoTargetObjectFile();
74 return new AArch64_ELFTargetObjectFile();
77 AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
78 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
79 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
81 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
82 // we have to make something up. Arbitrarily, choose ZeroOrOne.
83 setBooleanContents(ZeroOrOneBooleanContent);
84 // When comparing vectors the result sets the different elements in the
85 // vector to all-one or all-zero.
86 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
88 // Set up the register classes.
89 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
90 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
92 if (Subtarget->hasFPARMv8()) {
93 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
94 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
95 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
96 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
99 if (Subtarget->hasNEON()) {
100 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
101 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
102 // Someone set us up the NEON.
103 addDRTypeForNEON(MVT::v2f32);
104 addDRTypeForNEON(MVT::v8i8);
105 addDRTypeForNEON(MVT::v4i16);
106 addDRTypeForNEON(MVT::v2i32);
107 addDRTypeForNEON(MVT::v1i64);
108 addDRTypeForNEON(MVT::v1f64);
110 addQRTypeForNEON(MVT::v4f32);
111 addQRTypeForNEON(MVT::v2f64);
112 addQRTypeForNEON(MVT::v16i8);
113 addQRTypeForNEON(MVT::v8i16);
114 addQRTypeForNEON(MVT::v4i32);
115 addQRTypeForNEON(MVT::v2i64);
118 // Compute derived properties from the register classes
119 computeRegisterProperties();
121 // Provide all sorts of operation actions
122 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
123 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
124 setOperationAction(ISD::SETCC, MVT::i32, Custom);
125 setOperationAction(ISD::SETCC, MVT::i64, Custom);
126 setOperationAction(ISD::SETCC, MVT::f32, Custom);
127 setOperationAction(ISD::SETCC, MVT::f64, Custom);
128 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
129 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
130 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
131 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
132 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
133 setOperationAction(ISD::SELECT, MVT::i32, Custom);
134 setOperationAction(ISD::SELECT, MVT::i64, Custom);
135 setOperationAction(ISD::SELECT, MVT::f32, Custom);
136 setOperationAction(ISD::SELECT, MVT::f64, Custom);
137 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
138 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
139 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
140 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
141 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
142 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
144 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
145 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
146 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
148 setOperationAction(ISD::FREM, MVT::f32, Expand);
149 setOperationAction(ISD::FREM, MVT::f64, Expand);
150 setOperationAction(ISD::FREM, MVT::f80, Expand);
152 // Custom lowering hooks are needed for XOR
153 // to fold it into CSINC/CSINV.
154 setOperationAction(ISD::XOR, MVT::i32, Custom);
155 setOperationAction(ISD::XOR, MVT::i64, Custom);
157 // Virtually no operation on f128 is legal, but LLVM can't expand them when
158 // there's a valid register class, so we need custom operations in most cases.
159 setOperationAction(ISD::FABS, MVT::f128, Expand);
160 setOperationAction(ISD::FADD, MVT::f128, Custom);
161 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
162 setOperationAction(ISD::FCOS, MVT::f128, Expand);
163 setOperationAction(ISD::FDIV, MVT::f128, Custom);
164 setOperationAction(ISD::FMA, MVT::f128, Expand);
165 setOperationAction(ISD::FMUL, MVT::f128, Custom);
166 setOperationAction(ISD::FNEG, MVT::f128, Expand);
167 setOperationAction(ISD::FPOW, MVT::f128, Expand);
168 setOperationAction(ISD::FREM, MVT::f128, Expand);
169 setOperationAction(ISD::FRINT, MVT::f128, Expand);
170 setOperationAction(ISD::FSIN, MVT::f128, Expand);
171 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
172 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
173 setOperationAction(ISD::FSUB, MVT::f128, Custom);
174 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
175 setOperationAction(ISD::SETCC, MVT::f128, Custom);
176 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
177 setOperationAction(ISD::SELECT, MVT::f128, Custom);
178 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
179 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
181 // Lowering for many of the conversions is actually specified by the non-f128
182 // type. The LowerXXX function will be trivial when f128 isn't involved.
183 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
184 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
185 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
186 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
187 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
188 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
189 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
190 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
191 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
192 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
193 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
194 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
195 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
196 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
198 // Variable arguments.
199 setOperationAction(ISD::VASTART, MVT::Other, Custom);
200 setOperationAction(ISD::VAARG, MVT::Other, Custom);
201 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
202 setOperationAction(ISD::VAEND, MVT::Other, Expand);
204 // Variable-sized objects.
205 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
206 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
209 // Exception handling.
210 // FIXME: These are guesses. Has this been defined yet?
211 setExceptionPointerRegister(AArch64::X0);
212 setExceptionSelectorRegister(AArch64::X1);
214 // Constant pool entries
215 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
218 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
220 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
221 setOperationAction(ISD::ADDC, MVT::i32, Custom);
222 setOperationAction(ISD::ADDE, MVT::i32, Custom);
223 setOperationAction(ISD::SUBC, MVT::i32, Custom);
224 setOperationAction(ISD::SUBE, MVT::i32, Custom);
225 setOperationAction(ISD::ADDC, MVT::i64, Custom);
226 setOperationAction(ISD::ADDE, MVT::i64, Custom);
227 setOperationAction(ISD::SUBC, MVT::i64, Custom);
228 setOperationAction(ISD::SUBE, MVT::i64, Custom);
230 // AArch64 lacks both left-rotate and popcount instructions.
231 setOperationAction(ISD::ROTL, MVT::i32, Expand);
232 setOperationAction(ISD::ROTL, MVT::i64, Expand);
234 // AArch64 doesn't have {U|S}MUL_LOHI.
235 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
236 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
239 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
240 // counterparts, which AArch64 supports directly.
241 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
242 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
243 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
244 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
246 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
247 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
249 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
250 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
251 setOperationAction(ISD::SREM, MVT::i32, Expand);
252 setOperationAction(ISD::SREM, MVT::i64, Expand);
253 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
254 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
255 setOperationAction(ISD::UREM, MVT::i32, Expand);
256 setOperationAction(ISD::UREM, MVT::i64, Expand);
258 // Custom lower Add/Sub/Mul with overflow.
259 setOperationAction(ISD::SADDO, MVT::i32, Custom);
260 setOperationAction(ISD::SADDO, MVT::i64, Custom);
261 setOperationAction(ISD::UADDO, MVT::i32, Custom);
262 setOperationAction(ISD::UADDO, MVT::i64, Custom);
263 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
264 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
265 setOperationAction(ISD::USUBO, MVT::i32, Custom);
266 setOperationAction(ISD::USUBO, MVT::i64, Custom);
267 setOperationAction(ISD::SMULO, MVT::i32, Custom);
268 setOperationAction(ISD::SMULO, MVT::i64, Custom);
269 setOperationAction(ISD::UMULO, MVT::i32, Custom);
270 setOperationAction(ISD::UMULO, MVT::i64, Custom);
272 setOperationAction(ISD::FSIN, MVT::f32, Expand);
273 setOperationAction(ISD::FSIN, MVT::f64, Expand);
274 setOperationAction(ISD::FCOS, MVT::f32, Expand);
275 setOperationAction(ISD::FCOS, MVT::f64, Expand);
276 setOperationAction(ISD::FPOW, MVT::f32, Expand);
277 setOperationAction(ISD::FPOW, MVT::f64, Expand);
278 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
279 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
281 // AArch64 has implementations of a lot of rounding-like FP operations.
282 static MVT RoundingTypes[] = { MVT::f32, MVT::f64};
283 for (unsigned I = 0; I < array_lengthof(RoundingTypes); ++I) {
284 MVT Ty = RoundingTypes[I];
285 setOperationAction(ISD::FFLOOR, Ty, Legal);
286 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
287 setOperationAction(ISD::FCEIL, Ty, Legal);
288 setOperationAction(ISD::FRINT, Ty, Legal);
289 setOperationAction(ISD::FTRUNC, Ty, Legal);
290 setOperationAction(ISD::FROUND, Ty, Legal);
293 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
295 if (Subtarget->isTargetMachO()) {
296 // For iOS, we don't want to the normal expansion of a libcall to
297 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
299 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
300 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
302 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
303 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
306 // AArch64 does not have floating-point extending loads, i1 sign-extending
307 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
308 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
309 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
310 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
311 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
312 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
313 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
314 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
315 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
316 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
317 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
318 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
319 // Indexed loads and stores are supported.
320 for (unsigned im = (unsigned)ISD::PRE_INC;
321 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
322 setIndexedLoadAction(im, MVT::i8, Legal);
323 setIndexedLoadAction(im, MVT::i16, Legal);
324 setIndexedLoadAction(im, MVT::i32, Legal);
325 setIndexedLoadAction(im, MVT::i64, Legal);
326 setIndexedLoadAction(im, MVT::f64, Legal);
327 setIndexedLoadAction(im, MVT::f32, Legal);
328 setIndexedStoreAction(im, MVT::i8, Legal);
329 setIndexedStoreAction(im, MVT::i16, Legal);
330 setIndexedStoreAction(im, MVT::i32, Legal);
331 setIndexedStoreAction(im, MVT::i64, Legal);
332 setIndexedStoreAction(im, MVT::f64, Legal);
333 setIndexedStoreAction(im, MVT::f32, Legal);
337 setOperationAction(ISD::TRAP, MVT::Other, Legal);
339 // We combine OR nodes for bitfield operations.
340 setTargetDAGCombine(ISD::OR);
342 // Vector add and sub nodes may conceal a high-half opportunity.
343 // Also, try to fold ADD into CSINC/CSINV..
344 setTargetDAGCombine(ISD::ADD);
345 setTargetDAGCombine(ISD::SUB);
347 setTargetDAGCombine(ISD::XOR);
348 setTargetDAGCombine(ISD::SINT_TO_FP);
349 setTargetDAGCombine(ISD::UINT_TO_FP);
351 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
353 setTargetDAGCombine(ISD::ANY_EXTEND);
354 setTargetDAGCombine(ISD::ZERO_EXTEND);
355 setTargetDAGCombine(ISD::SIGN_EXTEND);
356 setTargetDAGCombine(ISD::BITCAST);
357 setTargetDAGCombine(ISD::CONCAT_VECTORS);
358 setTargetDAGCombine(ISD::STORE);
360 setTargetDAGCombine(ISD::MUL);
362 setTargetDAGCombine(ISD::SELECT);
363 setTargetDAGCombine(ISD::VSELECT);
365 setTargetDAGCombine(ISD::INTRINSIC_VOID);
366 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
367 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
369 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
370 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
371 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
373 setStackPointerRegisterToSaveRestore(AArch64::SP);
375 setSchedulingPreference(Sched::Hybrid);
378 MaskAndBranchFoldingIsLegal = true;
380 setMinFunctionAlignment(2);
382 RequireStrictAlign = (Align == StrictAlign);
384 setHasExtractBitsInsn(true);
386 if (Subtarget->hasNEON()) {
387 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
388 // silliness like this:
389 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
390 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
391 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
392 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
393 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
394 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
395 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
396 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
397 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
398 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
399 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
400 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
401 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
402 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
403 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
404 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
405 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
406 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
407 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
408 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
409 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
410 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
411 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
412 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
413 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
415 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
416 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
417 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
418 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
419 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
421 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
423 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
424 // elements smaller than i32, so promote the input to i32 first.
425 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
426 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
427 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
428 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
429 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
430 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
431 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
432 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
433 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
435 // AArch64 doesn't have MUL.2d:
436 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
437 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
438 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
439 // Likewise, narrowing and extending vector loads/stores aren't handled
441 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
442 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
444 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
447 setOperationAction(ISD::MULHS, (MVT::SimpleValueType)VT, Expand);
448 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
449 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand);
450 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
452 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
454 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
455 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
456 setTruncStoreAction((MVT::SimpleValueType)VT,
457 (MVT::SimpleValueType)InnerVT, Expand);
458 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
459 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
460 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
463 // AArch64 has implementations of a lot of rounding-like FP operations.
464 static MVT RoundingVecTypes[] = {MVT::v2f32, MVT::v4f32, MVT::v2f64 };
465 for (unsigned I = 0; I < array_lengthof(RoundingVecTypes); ++I) {
466 MVT Ty = RoundingVecTypes[I];
467 setOperationAction(ISD::FFLOOR, Ty, Legal);
468 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
469 setOperationAction(ISD::FCEIL, Ty, Legal);
470 setOperationAction(ISD::FRINT, Ty, Legal);
471 setOperationAction(ISD::FTRUNC, Ty, Legal);
472 setOperationAction(ISD::FROUND, Ty, Legal);
477 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
478 if (VT == MVT::v2f32) {
479 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
480 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
482 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
483 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
484 } else if (VT == MVT::v2f64 || VT == MVT::v4f32) {
485 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
486 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
488 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
489 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
492 // Mark vector float intrinsics as expand.
493 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
494 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
495 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
496 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
497 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
498 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
499 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
500 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
501 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
502 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
505 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
506 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
507 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
508 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
509 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
510 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
511 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
512 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
513 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
514 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
515 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
516 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
518 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
519 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
520 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
521 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
523 // CNT supports only B element sizes.
524 if (VT != MVT::v8i8 && VT != MVT::v16i8)
525 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
527 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
528 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
529 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
530 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
531 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
533 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
534 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
536 if (Subtarget->isLittleEndian()) {
537 for (unsigned im = (unsigned)ISD::PRE_INC;
538 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
539 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
540 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
545 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
546 addRegisterClass(VT, &AArch64::FPR64RegClass);
547 addTypeForNEON(VT, MVT::v2i32);
550 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
551 addRegisterClass(VT, &AArch64::FPR128RegClass);
552 addTypeForNEON(VT, MVT::v4i32);
555 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
558 return VT.changeVectorElementTypeToInteger();
561 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
562 /// Mask are known to be either zero or one and return them in the
563 /// KnownZero/KnownOne bitsets.
564 void AArch64TargetLowering::computeKnownBitsForTargetNode(
565 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
566 const SelectionDAG &DAG, unsigned Depth) const {
567 switch (Op.getOpcode()) {
570 case AArch64ISD::CSEL: {
571 APInt KnownZero2, KnownOne2;
572 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
573 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
574 KnownZero &= KnownZero2;
575 KnownOne &= KnownOne2;
578 case ISD::INTRINSIC_W_CHAIN: {
579 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
580 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
583 case Intrinsic::aarch64_ldaxr:
584 case Intrinsic::aarch64_ldxr: {
585 unsigned BitWidth = KnownOne.getBitWidth();
586 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
587 unsigned MemBits = VT.getScalarType().getSizeInBits();
588 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
594 case ISD::INTRINSIC_WO_CHAIN:
595 case ISD::INTRINSIC_VOID: {
596 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
600 case Intrinsic::aarch64_neon_umaxv:
601 case Intrinsic::aarch64_neon_uminv: {
602 // Figure out the datatype of the vector operand. The UMINV instruction
603 // will zero extend the result, so we can mark as known zero all the
604 // bits larger than the element datatype. 32-bit or larget doesn't need
605 // this as those are legal types and will be handled by isel directly.
606 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
607 unsigned BitWidth = KnownZero.getBitWidth();
608 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
609 assert(BitWidth >= 8 && "Unexpected width!");
610 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
612 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
613 assert(BitWidth >= 16 && "Unexpected width!");
614 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
624 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
628 unsigned AArch64TargetLowering::getMaximalGlobalOffset() const {
629 // FIXME: On AArch64, this depends on the type.
630 // Basically, the addressable offsets are o to 4095 * Ty.getSizeInBytes().
631 // and the offset has to be a multiple of the related size in bytes.
636 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
637 const TargetLibraryInfo *libInfo) const {
638 return AArch64::createFastISel(funcInfo, libInfo);
641 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
645 case AArch64ISD::CALL: return "AArch64ISD::CALL";
646 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
647 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
648 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
649 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
650 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
651 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
652 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
653 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
654 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
655 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
656 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
657 case AArch64ISD::TLSDESC_CALL: return "AArch64ISD::TLSDESC_CALL";
658 case AArch64ISD::ADC: return "AArch64ISD::ADC";
659 case AArch64ISD::SBC: return "AArch64ISD::SBC";
660 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
661 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
662 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
663 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
664 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
665 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
666 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
667 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
668 case AArch64ISD::DUP: return "AArch64ISD::DUP";
669 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
670 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
671 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
672 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
673 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
674 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
675 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
676 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
677 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
678 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
679 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
680 case AArch64ISD::BICi: return "AArch64ISD::BICi";
681 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
682 case AArch64ISD::BSL: return "AArch64ISD::BSL";
683 case AArch64ISD::NEG: return "AArch64ISD::NEG";
684 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
685 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
686 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
687 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
688 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
689 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
690 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
691 case AArch64ISD::REV16: return "AArch64ISD::REV16";
692 case AArch64ISD::REV32: return "AArch64ISD::REV32";
693 case AArch64ISD::REV64: return "AArch64ISD::REV64";
694 case AArch64ISD::EXT: return "AArch64ISD::EXT";
695 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
696 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
697 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
698 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
699 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
700 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
701 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
702 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
703 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
704 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
705 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
706 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
707 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
708 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
709 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
710 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
711 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
712 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
713 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
714 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
715 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
716 case AArch64ISD::NOT: return "AArch64ISD::NOT";
717 case AArch64ISD::BIT: return "AArch64ISD::BIT";
718 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
719 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
720 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
721 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
722 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
723 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
724 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
725 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
726 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
727 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
728 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
729 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
730 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
731 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
732 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
733 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
734 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
735 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
736 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
737 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
738 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
739 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
740 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
741 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
742 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
743 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
744 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
745 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
746 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
747 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
748 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
749 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
750 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
751 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
752 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
753 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
758 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
759 MachineBasicBlock *MBB) const {
760 // We materialise the F128CSEL pseudo-instruction as some control flow and a
764 // [... previous instrs leading to comparison ...]
770 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
772 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
773 MachineFunction *MF = MBB->getParent();
774 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
775 DebugLoc DL = MI->getDebugLoc();
776 MachineFunction::iterator It = MBB;
779 unsigned DestReg = MI->getOperand(0).getReg();
780 unsigned IfTrueReg = MI->getOperand(1).getReg();
781 unsigned IfFalseReg = MI->getOperand(2).getReg();
782 unsigned CondCode = MI->getOperand(3).getImm();
783 bool NZCVKilled = MI->getOperand(4).isKill();
785 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
786 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
787 MF->insert(It, TrueBB);
788 MF->insert(It, EndBB);
790 // Transfer rest of current basic-block to EndBB
791 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
793 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
795 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
796 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
797 MBB->addSuccessor(TrueBB);
798 MBB->addSuccessor(EndBB);
800 // TrueBB falls through to the end.
801 TrueBB->addSuccessor(EndBB);
804 TrueBB->addLiveIn(AArch64::NZCV);
805 EndBB->addLiveIn(AArch64::NZCV);
808 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
814 MI->eraseFromParent();
819 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
820 MachineBasicBlock *BB) const {
821 switch (MI->getOpcode()) {
826 assert(0 && "Unexpected instruction for custom inserter!");
829 case AArch64::F128CSEL:
830 return EmitF128CSEL(MI, BB);
832 case TargetOpcode::STACKMAP:
833 case TargetOpcode::PATCHPOINT:
834 return emitPatchPoint(MI, BB);
836 llvm_unreachable("Unexpected instruction for custom inserter!");
839 //===----------------------------------------------------------------------===//
840 // AArch64 Lowering private implementation.
841 //===----------------------------------------------------------------------===//
843 //===----------------------------------------------------------------------===//
845 //===----------------------------------------------------------------------===//
847 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
849 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
852 llvm_unreachable("Unknown condition code!");
854 return AArch64CC::NE;
856 return AArch64CC::EQ;
858 return AArch64CC::GT;
860 return AArch64CC::GE;
862 return AArch64CC::LT;
864 return AArch64CC::LE;
866 return AArch64CC::HI;
868 return AArch64CC::HS;
870 return AArch64CC::LO;
872 return AArch64CC::LS;
876 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
877 static void changeFPCCToAArch64CC(ISD::CondCode CC,
878 AArch64CC::CondCode &CondCode,
879 AArch64CC::CondCode &CondCode2) {
880 CondCode2 = AArch64CC::AL;
883 llvm_unreachable("Unknown FP condition!");
886 CondCode = AArch64CC::EQ;
890 CondCode = AArch64CC::GT;
894 CondCode = AArch64CC::GE;
897 CondCode = AArch64CC::MI;
900 CondCode = AArch64CC::LS;
903 CondCode = AArch64CC::MI;
904 CondCode2 = AArch64CC::GT;
907 CondCode = AArch64CC::VC;
910 CondCode = AArch64CC::VS;
913 CondCode = AArch64CC::EQ;
914 CondCode2 = AArch64CC::VS;
917 CondCode = AArch64CC::HI;
920 CondCode = AArch64CC::PL;
924 CondCode = AArch64CC::LT;
928 CondCode = AArch64CC::LE;
932 CondCode = AArch64CC::NE;
937 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
938 /// CC usable with the vector instructions. Fewer operations are available
939 /// without a real NZCV register, so we have to use less efficient combinations
940 /// to get the same effect.
941 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
942 AArch64CC::CondCode &CondCode,
943 AArch64CC::CondCode &CondCode2,
948 // Mostly the scalar mappings work fine.
949 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
952 Invert = true; // Fallthrough
954 CondCode = AArch64CC::MI;
955 CondCode2 = AArch64CC::GE;
962 // All of the compare-mask comparisons are ordered, but we can switch
963 // between the two by a double inversion. E.g. ULE == !OGT.
965 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
970 static bool isLegalArithImmed(uint64_t C) {
971 // Matches AArch64DAGToDAGISel::SelectArithImmed().
972 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
975 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
976 SDLoc dl, SelectionDAG &DAG) {
977 EVT VT = LHS.getValueType();
979 if (VT.isFloatingPoint())
980 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
982 // The CMP instruction is just an alias for SUBS, and representing it as
983 // SUBS means that it's possible to get CSE with subtract operations.
984 // A later phase can perform the optimization of setting the destination
985 // register to WZR/XZR if it ends up being unused.
986 unsigned Opcode = AArch64ISD::SUBS;
988 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
989 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
990 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
991 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
992 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
993 // can be set differently by this operation. It comes down to whether
994 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
995 // everything is fine. If not then the optimization is wrong. Thus general
996 // comparisons are only valid if op2 != 0.
998 // So, finally, the only LLVM-native comparisons that don't mention C and V
999 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1000 // the absence of information about op2.
1001 Opcode = AArch64ISD::ADDS;
1002 RHS = RHS.getOperand(1);
1003 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1004 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1005 !isUnsignedIntSetCC(CC)) {
1006 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1007 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1008 // of the signed comparisons.
1009 Opcode = AArch64ISD::ANDS;
1010 RHS = LHS.getOperand(1);
1011 LHS = LHS.getOperand(0);
1014 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1018 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1019 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1020 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1021 EVT VT = RHS.getValueType();
1022 uint64_t C = RHSC->getZExtValue();
1023 if (!isLegalArithImmed(C)) {
1024 // Constant does not fit, try adjusting it by one?
1030 if ((VT == MVT::i32 && C != 0x80000000 &&
1031 isLegalArithImmed((uint32_t)(C - 1))) ||
1032 (VT == MVT::i64 && C != 0x80000000ULL &&
1033 isLegalArithImmed(C - 1ULL))) {
1034 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1035 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1036 RHS = DAG.getConstant(C, VT);
1041 if ((VT == MVT::i32 && C != 0 &&
1042 isLegalArithImmed((uint32_t)(C - 1))) ||
1043 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1044 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1045 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1046 RHS = DAG.getConstant(C, VT);
1051 if ((VT == MVT::i32 && C != 0x7fffffff &&
1052 isLegalArithImmed((uint32_t)(C + 1))) ||
1053 (VT == MVT::i64 && C != 0x7ffffffffffffffULL &&
1054 isLegalArithImmed(C + 1ULL))) {
1055 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1056 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1057 RHS = DAG.getConstant(C, VT);
1062 if ((VT == MVT::i32 && C != 0xffffffff &&
1063 isLegalArithImmed((uint32_t)(C + 1))) ||
1064 (VT == MVT::i64 && C != 0xfffffffffffffffULL &&
1065 isLegalArithImmed(C + 1ULL))) {
1066 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1067 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1068 RHS = DAG.getConstant(C, VT);
1075 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1076 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
1077 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1081 static std::pair<SDValue, SDValue>
1082 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1083 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1084 "Unsupported value type");
1085 SDValue Value, Overflow;
1087 SDValue LHS = Op.getOperand(0);
1088 SDValue RHS = Op.getOperand(1);
1090 switch (Op.getOpcode()) {
1092 llvm_unreachable("Unknown overflow instruction!");
1094 Opc = AArch64ISD::ADDS;
1098 Opc = AArch64ISD::ADDS;
1102 Opc = AArch64ISD::SUBS;
1106 Opc = AArch64ISD::SUBS;
1109 // Multiply needs a little bit extra work.
1113 bool IsSigned = (Op.getOpcode() == ISD::SMULO) ? true : false;
1114 if (Op.getValueType() == MVT::i32) {
1115 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1116 // For a 32 bit multiply with overflow check we want the instruction
1117 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1118 // need to generate the following pattern:
1119 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1120 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1121 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1122 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1123 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1124 DAG.getConstant(0, MVT::i64));
1125 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1126 // operation. We need to clear out the upper 32 bits, because we used a
1127 // widening multiply that wrote all 64 bits. In the end this should be a
1129 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1131 // The signed overflow check requires more than just a simple check for
1132 // any bit set in the upper 32 bits of the result. These bits could be
1133 // just the sign bits of a negative number. To perform the overflow
1134 // check we have to arithmetic shift right the 32nd bit of the result by
1135 // 31 bits. Then we compare the result to the upper 32 bits.
1136 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1137 DAG.getConstant(32, MVT::i64));
1138 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1139 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1140 DAG.getConstant(31, MVT::i64));
1141 // It is important that LowerBits is last, otherwise the arithmetic
1142 // shift will not be folded into the compare (SUBS).
1143 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1144 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1147 // The overflow check for unsigned multiply is easy. We only need to
1148 // check if any of the upper 32 bits are set. This can be done with a
1149 // CMP (shifted register). For that we need to generate the following
1151 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1152 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1153 DAG.getConstant(32, MVT::i64));
1154 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1156 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1157 UpperBits).getValue(1);
1161 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1162 // For the 64 bit multiply
1163 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1165 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1166 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1167 DAG.getConstant(63, MVT::i64));
1168 // It is important that LowerBits is last, otherwise the arithmetic
1169 // shift will not be folded into the compare (SUBS).
1170 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1171 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1174 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1175 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1177 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1178 UpperBits).getValue(1);
1185 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1187 // Emit the AArch64 operation with overflow check.
1188 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1189 Overflow = Value.getValue(1);
1191 return std::make_pair(Value, Overflow);
1194 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1195 RTLIB::Libcall Call) const {
1196 SmallVector<SDValue, 2> Ops;
1197 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1198 Ops.push_back(Op.getOperand(i));
1200 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1204 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1205 SDValue Sel = Op.getOperand(0);
1206 SDValue Other = Op.getOperand(1);
1208 // If neither operand is a SELECT_CC, give up.
1209 if (Sel.getOpcode() != ISD::SELECT_CC)
1210 std::swap(Sel, Other);
1211 if (Sel.getOpcode() != ISD::SELECT_CC)
1214 // The folding we want to perform is:
1215 // (xor x, (select_cc a, b, cc, 0, -1) )
1217 // (csel x, (xor x, -1), cc ...)
1219 // The latter will get matched to a CSINV instruction.
1221 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1222 SDValue LHS = Sel.getOperand(0);
1223 SDValue RHS = Sel.getOperand(1);
1224 SDValue TVal = Sel.getOperand(2);
1225 SDValue FVal = Sel.getOperand(3);
1228 // FIXME: This could be generalized to non-integer comparisons.
1229 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1232 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1233 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1235 // The the values aren't constants, this isn't the pattern we're looking for.
1236 if (!CFVal || !CTVal)
1239 // We can commute the SELECT_CC by inverting the condition. This
1240 // might be needed to make this fit into a CSINV pattern.
1241 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1242 std::swap(TVal, FVal);
1243 std::swap(CTVal, CFVal);
1244 CC = ISD::getSetCCInverse(CC, true);
1247 // If the constants line up, perform the transform!
1248 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1250 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1253 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1254 DAG.getConstant(-1ULL, Other.getValueType()));
1256 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1263 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1264 EVT VT = Op.getValueType();
1266 // Let legalize expand this if it isn't a legal type yet.
1267 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1270 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1273 bool ExtraOp = false;
1274 switch (Op.getOpcode()) {
1276 assert(0 && "Invalid code");
1278 Opc = AArch64ISD::ADDS;
1281 Opc = AArch64ISD::SUBS;
1284 Opc = AArch64ISD::ADCS;
1288 Opc = AArch64ISD::SBCS;
1294 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1295 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1299 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1300 // Let legalize expand this if it isn't a legal type yet.
1301 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1304 AArch64CC::CondCode CC;
1305 // The actual operation that sets the overflow or carry flag.
1306 SDValue Value, Overflow;
1307 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1309 // We use 0 and 1 as false and true values.
1310 SDValue TVal = DAG.getConstant(1, MVT::i32);
1311 SDValue FVal = DAG.getConstant(0, MVT::i32);
1313 // We use an inverted condition, because the conditional select is inverted
1314 // too. This will allow it to be selected to a single instruction:
1315 // CSINC Wd, WZR, WZR, invert(cond).
1316 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32);
1317 Overflow = DAG.getNode(AArch64ISD::CSEL, SDLoc(Op), MVT::i32, FVal, TVal,
1320 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1321 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
1324 // Prefetch operands are:
1325 // 1: Address to prefetch
1327 // 3: int locality (0 = no locality ... 3 = extreme locality)
1328 // 4: bool isDataCache
1329 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1331 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1332 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1333 // The data thing is not used.
1334 // unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1336 bool IsStream = !Locality;
1337 // When the locality number is set
1339 // The front-end should have filtered out the out-of-range values
1340 assert(Locality <= 3 && "Prefetch locality out-of-range");
1341 // The locality degree is the opposite of the cache speed.
1342 // Put the number the other way around.
1343 // The encoding starts at 0 for level 1
1344 Locality = 3 - Locality;
1347 // built the mask value encoding the expected behavior.
1348 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1349 (Locality << 1) | // Cache level bits
1350 (unsigned)IsStream; // Stream bit
1351 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1352 DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1));
1355 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1356 SelectionDAG &DAG) const {
1357 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1360 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1362 return LowerF128Call(Op, DAG, LC);
1365 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1366 SelectionDAG &DAG) const {
1367 if (Op.getOperand(0).getValueType() != MVT::f128) {
1368 // It's legal except when f128 is involved
1373 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1375 // FP_ROUND node has a second operand indicating whether it is known to be
1376 // precise. That doesn't take part in the LibCall so we can't directly use
1378 SDValue SrcVal = Op.getOperand(0);
1379 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1380 /*isSigned*/ false, SDLoc(Op)).first;
1383 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1384 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1385 // Any additional optimization in this function should be recorded
1386 // in the cost tables.
1387 EVT InVT = Op.getOperand(0).getValueType();
1388 EVT VT = Op.getValueType();
1390 // FP_TO_XINT conversion from the same type are legal.
1391 if (VT.getSizeInBits() == InVT.getSizeInBits())
1394 if (InVT == MVT::v2f64 || InVT == MVT::v4f32) {
1397 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1399 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1400 } else if (InVT == MVT::v2f32) {
1402 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v2f64, Op.getOperand(0));
1403 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1406 // Type changing conversions are illegal.
1410 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1411 SelectionDAG &DAG) const {
1412 if (Op.getOperand(0).getValueType().isVector())
1413 return LowerVectorFP_TO_INT(Op, DAG);
1415 if (Op.getOperand(0).getValueType() != MVT::f128) {
1416 // It's legal except when f128 is involved
1421 if (Op.getOpcode() == ISD::FP_TO_SINT)
1422 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1424 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1426 SmallVector<SDValue, 2> Ops;
1427 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1428 Ops.push_back(Op.getOperand(i));
1430 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1434 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1435 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1436 // Any additional optimization in this function should be recorded
1437 // in the cost tables.
1438 EVT VT = Op.getValueType();
1440 SDValue In = Op.getOperand(0);
1441 EVT InVT = In.getValueType();
1443 // v2i32 to v2f32 is legal.
1444 if (VT == MVT::v2f32 && InVT == MVT::v2i32)
1447 // This function only handles v2f64 outputs.
1448 if (VT == MVT::v2f64) {
1449 // Extend the input argument to a v2i64 that we can feed into the
1450 // floating point conversion. Zero or sign extend based on whether
1451 // we're doing a signed or unsigned float conversion.
1453 Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
1454 assert(Op.getNumOperands() == 1 && "FP conversions take one argument");
1455 SDValue Promoted = DAG.getNode(Opc, dl, MVT::v2i64, Op.getOperand(0));
1456 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Promoted);
1459 // Scalarize v2i64 to v2f32 conversions.
1460 std::vector<SDValue> BuildVectorOps;
1461 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
1462 SDValue Sclr = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, In,
1463 DAG.getConstant(i, MVT::i64));
1464 Sclr = DAG.getNode(Op->getOpcode(), dl, MVT::f32, Sclr);
1465 BuildVectorOps.push_back(Sclr);
1468 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, BuildVectorOps);
1471 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1472 SelectionDAG &DAG) const {
1473 if (Op.getValueType().isVector())
1474 return LowerVectorINT_TO_FP(Op, DAG);
1476 // i128 conversions are libcalls.
1477 if (Op.getOperand(0).getValueType() == MVT::i128)
1480 // Other conversions are legal, unless it's to the completely software-based
1482 if (Op.getValueType() != MVT::f128)
1486 if (Op.getOpcode() == ISD::SINT_TO_FP)
1487 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1489 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1491 return LowerF128Call(Op, DAG, LC);
1494 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1495 SelectionDAG &DAG) const {
1496 // For iOS, we want to call an alternative entry point: __sincos_stret,
1497 // which returns the values in two S / D registers.
1499 SDValue Arg = Op.getOperand(0);
1500 EVT ArgVT = Arg.getValueType();
1501 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1508 Entry.isSExt = false;
1509 Entry.isZExt = false;
1510 Args.push_back(Entry);
1512 const char *LibcallName =
1513 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1514 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1516 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
1517 TargetLowering::CallLoweringInfo CLI(DAG);
1518 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1519 .setCallee(CallingConv::Fast, RetTy, Callee, &Args, 0);
1521 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1522 return CallResult.first;
1525 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1526 SelectionDAG &DAG) const {
1527 switch (Op.getOpcode()) {
1529 llvm_unreachable("unimplemented operand");
1531 case ISD::GlobalAddress:
1532 return LowerGlobalAddress(Op, DAG);
1533 case ISD::GlobalTLSAddress:
1534 return LowerGlobalTLSAddress(Op, DAG);
1536 return LowerSETCC(Op, DAG);
1538 return LowerBR_CC(Op, DAG);
1540 return LowerSELECT(Op, DAG);
1541 case ISD::SELECT_CC:
1542 return LowerSELECT_CC(Op, DAG);
1543 case ISD::JumpTable:
1544 return LowerJumpTable(Op, DAG);
1545 case ISD::ConstantPool:
1546 return LowerConstantPool(Op, DAG);
1547 case ISD::BlockAddress:
1548 return LowerBlockAddress(Op, DAG);
1550 return LowerVASTART(Op, DAG);
1552 return LowerVACOPY(Op, DAG);
1554 return LowerVAARG(Op, DAG);
1559 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1566 return LowerXALUO(Op, DAG);
1568 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1570 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1572 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1574 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1576 return LowerFP_ROUND(Op, DAG);
1577 case ISD::FP_EXTEND:
1578 return LowerFP_EXTEND(Op, DAG);
1579 case ISD::FRAMEADDR:
1580 return LowerFRAMEADDR(Op, DAG);
1581 case ISD::RETURNADDR:
1582 return LowerRETURNADDR(Op, DAG);
1583 case ISD::INSERT_VECTOR_ELT:
1584 return LowerINSERT_VECTOR_ELT(Op, DAG);
1585 case ISD::EXTRACT_VECTOR_ELT:
1586 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1587 case ISD::BUILD_VECTOR:
1588 return LowerBUILD_VECTOR(Op, DAG);
1589 case ISD::VECTOR_SHUFFLE:
1590 return LowerVECTOR_SHUFFLE(Op, DAG);
1591 case ISD::EXTRACT_SUBVECTOR:
1592 return LowerEXTRACT_SUBVECTOR(Op, DAG);
1596 return LowerVectorSRA_SRL_SHL(Op, DAG);
1597 case ISD::SHL_PARTS:
1598 return LowerShiftLeftParts(Op, DAG);
1599 case ISD::SRL_PARTS:
1600 case ISD::SRA_PARTS:
1601 return LowerShiftRightParts(Op, DAG);
1603 return LowerCTPOP(Op, DAG);
1604 case ISD::FCOPYSIGN:
1605 return LowerFCOPYSIGN(Op, DAG);
1607 return LowerVectorAND(Op, DAG);
1609 return LowerVectorOR(Op, DAG);
1611 return LowerXOR(Op, DAG);
1613 return LowerPREFETCH(Op, DAG);
1614 case ISD::SINT_TO_FP:
1615 case ISD::UINT_TO_FP:
1616 return LowerINT_TO_FP(Op, DAG);
1617 case ISD::FP_TO_SINT:
1618 case ISD::FP_TO_UINT:
1619 return LowerFP_TO_INT(Op, DAG);
1621 return LowerFSINCOS(Op, DAG);
1625 /// getFunctionAlignment - Return the Log2 alignment of this function.
1626 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
1630 //===----------------------------------------------------------------------===//
1631 // Calling Convention Implementation
1632 //===----------------------------------------------------------------------===//
1634 #include "AArch64GenCallingConv.inc"
1636 /// Selects the correct CCAssignFn for a the given CallingConvention
1638 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1639 bool IsVarArg) const {
1642 llvm_unreachable("Unsupported calling convention.");
1643 case CallingConv::WebKit_JS:
1644 return CC_AArch64_WebKit_JS;
1645 case CallingConv::C:
1646 case CallingConv::Fast:
1647 if (!Subtarget->isTargetDarwin())
1648 return CC_AArch64_AAPCS;
1649 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
1653 SDValue AArch64TargetLowering::LowerFormalArguments(
1654 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1655 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1656 SmallVectorImpl<SDValue> &InVals) const {
1657 MachineFunction &MF = DAG.getMachineFunction();
1658 MachineFrameInfo *MFI = MF.getFrameInfo();
1660 // Assign locations to all of the incoming arguments.
1661 SmallVector<CCValAssign, 16> ArgLocs;
1662 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1663 getTargetMachine(), ArgLocs, *DAG.getContext());
1665 // At this point, Ins[].VT may already be promoted to i32. To correctly
1666 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
1667 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
1668 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
1669 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
1671 unsigned NumArgs = Ins.size();
1672 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
1673 unsigned CurArgIdx = 0;
1674 for (unsigned i = 0; i != NumArgs; ++i) {
1675 MVT ValVT = Ins[i].VT;
1676 std::advance(CurOrigArg, Ins[i].OrigArgIndex - CurArgIdx);
1677 CurArgIdx = Ins[i].OrigArgIndex;
1679 // Get type of the original argument.
1680 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
1681 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
1682 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
1683 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
1685 else if (ActualMVT == MVT::i16)
1688 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
1690 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
1691 assert(!Res && "Call operand has unhandled type");
1694 assert(ArgLocs.size() == Ins.size());
1695 SmallVector<SDValue, 16> ArgValues;
1696 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1697 CCValAssign &VA = ArgLocs[i];
1699 if (Ins[i].Flags.isByVal()) {
1700 // Byval is used for HFAs in the PCS, but the system should work in a
1701 // non-compliant manner for larger structs.
1702 EVT PtrTy = getPointerTy();
1703 int Size = Ins[i].Flags.getByValSize();
1704 unsigned NumRegs = (Size + 7) / 8;
1706 // FIXME: This works on big-endian for composite byvals, which are the common
1707 // case. It should also work for fundamental types too.
1709 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
1710 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
1711 InVals.push_back(FrameIdxN);
1716 if (VA.isRegLoc()) {
1717 // Arguments stored in registers.
1718 EVT RegVT = VA.getLocVT();
1721 const TargetRegisterClass *RC;
1723 if (RegVT == MVT::i32)
1724 RC = &AArch64::GPR32RegClass;
1725 else if (RegVT == MVT::i64)
1726 RC = &AArch64::GPR64RegClass;
1727 else if (RegVT == MVT::f32)
1728 RC = &AArch64::FPR32RegClass;
1729 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
1730 RC = &AArch64::FPR64RegClass;
1731 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
1732 RC = &AArch64::FPR128RegClass;
1734 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1736 // Transform the arguments in physical registers into virtual ones.
1737 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1738 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
1740 // If this is an 8, 16 or 32-bit value, it is really passed promoted
1741 // to 64 bits. Insert an assert[sz]ext to capture this, then
1742 // truncate to the right size.
1743 switch (VA.getLocInfo()) {
1745 llvm_unreachable("Unknown loc info!");
1746 case CCValAssign::Full:
1748 case CCValAssign::BCvt:
1749 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
1751 case CCValAssign::AExt:
1752 case CCValAssign::SExt:
1753 case CCValAssign::ZExt:
1754 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
1755 // nodes after our lowering.
1756 assert(RegVT == Ins[i].VT && "incorrect register location selected");
1760 InVals.push_back(ArgValue);
1762 } else { // VA.isRegLoc()
1763 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
1764 unsigned ArgOffset = VA.getLocMemOffset();
1765 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1767 uint32_t BEAlign = 0;
1768 if (ArgSize < 8 && !Subtarget->isLittleEndian())
1769 BEAlign = 8 - ArgSize;
1771 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
1773 // Create load nodes to retrieve arguments from the stack.
1774 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1777 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
1778 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
1779 MVT MemVT = VA.getValVT();
1781 switch (VA.getLocInfo()) {
1784 case CCValAssign::BCvt:
1785 MemVT = VA.getLocVT();
1787 case CCValAssign::SExt:
1788 ExtType = ISD::SEXTLOAD;
1790 case CCValAssign::ZExt:
1791 ExtType = ISD::ZEXTLOAD;
1793 case CCValAssign::AExt:
1794 ExtType = ISD::EXTLOAD;
1798 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
1799 MachinePointerInfo::getFixedStack(FI),
1800 MemVT, false, false, false, nullptr);
1802 InVals.push_back(ArgValue);
1808 if (!Subtarget->isTargetDarwin()) {
1809 // The AAPCS variadic function ABI is identical to the non-variadic
1810 // one. As a result there may be more arguments in registers and we should
1811 // save them for future reference.
1812 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
1815 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
1816 // This will point to the next argument passed via stack.
1817 unsigned StackOffset = CCInfo.getNextStackOffset();
1818 // We currently pass all varargs at 8-byte alignment.
1819 StackOffset = ((StackOffset + 7) & ~7);
1820 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
1823 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
1824 unsigned StackArgSize = CCInfo.getNextStackOffset();
1825 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1826 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
1827 // This is a non-standard ABI so by fiat I say we're allowed to make full
1828 // use of the stack area to be popped, which must be aligned to 16 bytes in
1830 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
1832 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
1833 // a multiple of 16.
1834 FuncInfo->setArgumentStackToRestore(StackArgSize);
1836 // This realignment carries over to the available bytes below. Our own
1837 // callers will guarantee the space is free by giving an aligned value to
1840 // Even if we're not expected to free up the space, it's useful to know how
1841 // much is there while considering tail calls (because we can reuse it).
1842 FuncInfo->setBytesInStackArgArea(StackArgSize);
1847 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
1848 SelectionDAG &DAG, SDLoc DL,
1849 SDValue &Chain) const {
1850 MachineFunction &MF = DAG.getMachineFunction();
1851 MachineFrameInfo *MFI = MF.getFrameInfo();
1852 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
1854 SmallVector<SDValue, 8> MemOps;
1856 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
1857 AArch64::X3, AArch64::X4, AArch64::X5,
1858 AArch64::X6, AArch64::X7 };
1859 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
1860 unsigned FirstVariadicGPR =
1861 CCInfo.getFirstUnallocated(GPRArgRegs, NumGPRArgRegs);
1863 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
1865 if (GPRSaveSize != 0) {
1866 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
1868 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
1870 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
1871 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
1872 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
1874 DAG.getStore(Val.getValue(1), DL, Val, FIN,
1875 MachinePointerInfo::getStack(i * 8), false, false, 0);
1876 MemOps.push_back(Store);
1877 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1878 DAG.getConstant(8, getPointerTy()));
1881 FuncInfo->setVarArgsGPRIndex(GPRIdx);
1882 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
1884 if (Subtarget->hasFPARMv8()) {
1885 static const MCPhysReg FPRArgRegs[] = {
1886 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
1887 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
1888 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
1889 unsigned FirstVariadicFPR =
1890 CCInfo.getFirstUnallocated(FPRArgRegs, NumFPRArgRegs);
1892 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
1894 if (FPRSaveSize != 0) {
1895 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
1897 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
1899 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
1900 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
1901 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
1904 DAG.getStore(Val.getValue(1), DL, Val, FIN,
1905 MachinePointerInfo::getStack(i * 16), false, false, 0);
1906 MemOps.push_back(Store);
1907 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1908 DAG.getConstant(16, getPointerTy()));
1911 FuncInfo->setVarArgsFPRIndex(FPRIdx);
1912 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
1915 if (!MemOps.empty()) {
1916 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
1920 /// LowerCallResult - Lower the result values of a call into the
1921 /// appropriate copies out of appropriate physical registers.
1922 SDValue AArch64TargetLowering::LowerCallResult(
1923 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1924 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1925 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
1926 SDValue ThisVal) const {
1927 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
1928 ? RetCC_AArch64_WebKit_JS
1929 : RetCC_AArch64_AAPCS;
1930 // Assign locations to each value returned by this call.
1931 SmallVector<CCValAssign, 16> RVLocs;
1932 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1933 getTargetMachine(), RVLocs, *DAG.getContext());
1934 CCInfo.AnalyzeCallResult(Ins, RetCC);
1936 // Copy all of the result registers out of their specified physreg.
1937 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1938 CCValAssign VA = RVLocs[i];
1940 // Pass 'this' value directly from the argument to return value, to avoid
1941 // reg unit interference
1942 if (i == 0 && isThisReturn) {
1943 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
1944 "unexpected return calling convention register assignment");
1945 InVals.push_back(ThisVal);
1950 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
1951 Chain = Val.getValue(1);
1952 InFlag = Val.getValue(2);
1954 switch (VA.getLocInfo()) {
1956 llvm_unreachable("Unknown loc info!");
1957 case CCValAssign::Full:
1959 case CCValAssign::BCvt:
1960 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
1964 InVals.push_back(Val);
1970 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
1971 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
1972 bool isCalleeStructRet, bool isCallerStructRet,
1973 const SmallVectorImpl<ISD::OutputArg> &Outs,
1974 const SmallVectorImpl<SDValue> &OutVals,
1975 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
1976 // For CallingConv::C this function knows whether the ABI needs
1977 // changing. That's not true for other conventions so they will have to opt in
1979 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1982 const MachineFunction &MF = DAG.getMachineFunction();
1983 const Function *CallerF = MF.getFunction();
1984 CallingConv::ID CallerCC = CallerF->getCallingConv();
1985 bool CCMatch = CallerCC == CalleeCC;
1987 // Byval parameters hand the function a pointer directly into the stack area
1988 // we want to reuse during a tail call. Working around this *is* possible (see
1989 // X86) but less efficient and uglier in LowerCall.
1990 for (Function::const_arg_iterator i = CallerF->arg_begin(),
1991 e = CallerF->arg_end();
1993 if (i->hasByValAttr())
1996 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
1997 if (IsTailCallConvention(CalleeCC) && CCMatch)
2002 // Now we search for cases where we can use a tail call without changing the
2003 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2006 // I want anyone implementing a new calling convention to think long and hard
2007 // about this assert.
2008 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2009 "Unexpected variadic calling convention");
2011 if (isVarArg && !Outs.empty()) {
2012 // At least two cases here: if caller is fastcc then we can't have any
2013 // memory arguments (we'd be expected to clean up the stack afterwards). If
2014 // caller is C then we could potentially use its argument area.
2016 // FIXME: for now we take the most conservative of these in both cases:
2017 // disallow all variadic memory operands.
2018 SmallVector<CCValAssign, 16> ArgLocs;
2019 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2020 getTargetMachine(), ArgLocs, *DAG.getContext());
2022 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2023 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2024 if (!ArgLocs[i].isRegLoc())
2028 // If the calling conventions do not match, then we'd better make sure the
2029 // results are returned in the same way as what the caller expects.
2031 SmallVector<CCValAssign, 16> RVLocs1;
2032 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2033 getTargetMachine(), RVLocs1, *DAG.getContext());
2034 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2036 SmallVector<CCValAssign, 16> RVLocs2;
2037 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2038 getTargetMachine(), RVLocs2, *DAG.getContext());
2039 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2041 if (RVLocs1.size() != RVLocs2.size())
2043 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2044 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2046 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2048 if (RVLocs1[i].isRegLoc()) {
2049 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2052 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2058 // Nothing more to check if the callee is taking no arguments
2062 SmallVector<CCValAssign, 16> ArgLocs;
2063 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2064 getTargetMachine(), ArgLocs, *DAG.getContext());
2066 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2068 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2070 // If the stack arguments for this call would fit into our own save area then
2071 // the call can be made tail.
2072 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2075 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2077 MachineFrameInfo *MFI,
2078 int ClobberedFI) const {
2079 SmallVector<SDValue, 8> ArgChains;
2080 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2081 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2083 // Include the original chain at the beginning of the list. When this is
2084 // used by target LowerCall hooks, this helps legalize find the
2085 // CALLSEQ_BEGIN node.
2086 ArgChains.push_back(Chain);
2088 // Add a chain value for each stack argument corresponding
2089 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2090 UE = DAG.getEntryNode().getNode()->use_end();
2092 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2093 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2094 if (FI->getIndex() < 0) {
2095 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2096 int64_t InLastByte = InFirstByte;
2097 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2099 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2100 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2101 ArgChains.push_back(SDValue(L, 1));
2104 // Build a tokenfactor for all the chains.
2105 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2108 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2109 bool TailCallOpt) const {
2110 return CallCC == CallingConv::Fast && TailCallOpt;
2113 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2114 return CallCC == CallingConv::Fast;
2117 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2118 /// and add input and output parameter nodes.
2120 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2121 SmallVectorImpl<SDValue> &InVals) const {
2122 SelectionDAG &DAG = CLI.DAG;
2124 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2125 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2126 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2127 SDValue Chain = CLI.Chain;
2128 SDValue Callee = CLI.Callee;
2129 bool &IsTailCall = CLI.IsTailCall;
2130 CallingConv::ID CallConv = CLI.CallConv;
2131 bool IsVarArg = CLI.IsVarArg;
2133 MachineFunction &MF = DAG.getMachineFunction();
2134 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2135 bool IsThisReturn = false;
2137 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2138 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2139 bool IsSibCall = false;
2142 // Check if it's really possible to do a tail call.
2143 IsTailCall = isEligibleForTailCallOptimization(
2144 Callee, CallConv, IsVarArg, IsStructRet,
2145 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2146 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2147 report_fatal_error("failed to perform tail call elimination on a call "
2148 "site marked musttail");
2150 // A sibling call is one where we're under the usual C ABI and not planning
2151 // to change that but can still do a tail call:
2152 if (!TailCallOpt && IsTailCall)
2159 // Analyze operands of the call, assigning locations to each operand.
2160 SmallVector<CCValAssign, 16> ArgLocs;
2161 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2162 getTargetMachine(), ArgLocs, *DAG.getContext());
2165 // Handle fixed and variable vector arguments differently.
2166 // Variable vector arguments always go into memory.
2167 unsigned NumArgs = Outs.size();
2169 for (unsigned i = 0; i != NumArgs; ++i) {
2170 MVT ArgVT = Outs[i].VT;
2171 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2172 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2173 /*IsVarArg=*/ !Outs[i].IsFixed);
2174 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2175 assert(!Res && "Call operand has unhandled type");
2179 // At this point, Outs[].VT may already be promoted to i32. To correctly
2180 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2181 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2182 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2183 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2185 unsigned NumArgs = Outs.size();
2186 for (unsigned i = 0; i != NumArgs; ++i) {
2187 MVT ValVT = Outs[i].VT;
2188 // Get type of the original argument.
2189 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2190 /*AllowUnknown*/ true);
2191 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2192 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2193 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2194 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2196 else if (ActualMVT == MVT::i16)
2199 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2200 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2201 assert(!Res && "Call operand has unhandled type");
2206 // Get a count of how many bytes are to be pushed on the stack.
2207 unsigned NumBytes = CCInfo.getNextStackOffset();
2210 // Since we're not changing the ABI to make this a tail call, the memory
2211 // operands are already available in the caller's incoming argument space.
2215 // FPDiff is the byte offset of the call's argument area from the callee's.
2216 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2217 // by this amount for a tail call. In a sibling call it must be 0 because the
2218 // caller will deallocate the entire stack and the callee still expects its
2219 // arguments to begin at SP+0. Completely unused for non-tail calls.
2222 if (IsTailCall && !IsSibCall) {
2223 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2225 // Since callee will pop argument stack as a tail call, we must keep the
2226 // popped size 16-byte aligned.
2227 NumBytes = RoundUpToAlignment(NumBytes, 16);
2229 // FPDiff will be negative if this tail call requires more space than we
2230 // would automatically have in our incoming argument space. Positive if we
2231 // can actually shrink the stack.
2232 FPDiff = NumReusableBytes - NumBytes;
2234 // The stack pointer must be 16-byte aligned at all times it's used for a
2235 // memory operation, which in practice means at *all* times and in
2236 // particular across call boundaries. Therefore our own arguments started at
2237 // a 16-byte aligned SP and the delta applied for the tail call should
2238 // satisfy the same constraint.
2239 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2242 // Adjust the stack pointer for the new arguments...
2243 // These operations are automatically eliminated by the prolog/epilog pass
2246 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL);
2248 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2250 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2251 SmallVector<SDValue, 8> MemOpChains;
2253 // Walk the register/memloc assignments, inserting copies/loads.
2254 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2255 ++i, ++realArgIdx) {
2256 CCValAssign &VA = ArgLocs[i];
2257 SDValue Arg = OutVals[realArgIdx];
2258 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2260 // Promote the value if needed.
2261 switch (VA.getLocInfo()) {
2263 llvm_unreachable("Unknown loc info!");
2264 case CCValAssign::Full:
2266 case CCValAssign::SExt:
2267 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2269 case CCValAssign::ZExt:
2270 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2272 case CCValAssign::AExt:
2273 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2274 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2275 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2276 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2278 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2280 case CCValAssign::BCvt:
2281 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2283 case CCValAssign::FPExt:
2284 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2288 if (VA.isRegLoc()) {
2289 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2290 assert(VA.getLocVT() == MVT::i64 &&
2291 "unexpected calling convention register assignment");
2292 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2293 "unexpected use of 'returned'");
2294 IsThisReturn = true;
2296 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2298 assert(VA.isMemLoc());
2301 MachinePointerInfo DstInfo;
2303 // FIXME: This works on big-endian for composite byvals, which are the
2304 // common case. It should also work for fundamental types too.
2305 uint32_t BEAlign = 0;
2306 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2307 : VA.getLocVT().getSizeInBits();
2308 OpSize = (OpSize + 7) / 8;
2309 if (!Subtarget->isLittleEndian() && !Flags.isByVal()) {
2311 BEAlign = 8 - OpSize;
2313 unsigned LocMemOffset = VA.getLocMemOffset();
2314 int32_t Offset = LocMemOffset + BEAlign;
2315 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2316 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2319 Offset = Offset + FPDiff;
2320 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2322 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2323 DstInfo = MachinePointerInfo::getFixedStack(FI);
2325 // Make sure any stack arguments overlapping with where we're storing
2326 // are loaded before this eventual operation. Otherwise they'll be
2328 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2330 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2332 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2333 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2336 if (Outs[i].Flags.isByVal()) {
2338 DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64);
2339 SDValue Cpy = DAG.getMemcpy(
2340 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2341 /*isVolatile = */ false,
2342 /*alwaysInline = */ false, DstInfo, MachinePointerInfo());
2344 MemOpChains.push_back(Cpy);
2346 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2347 // promoted to a legal register type i32, we should truncate Arg back to
2349 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2350 VA.getValVT() == MVT::i16)
2351 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2354 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2355 MemOpChains.push_back(Store);
2360 if (!MemOpChains.empty())
2361 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2363 // Build a sequence of copy-to-reg nodes chained together with token chain
2364 // and flag operands which copy the outgoing args into the appropriate regs.
2366 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2367 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2368 RegsToPass[i].second, InFlag);
2369 InFlag = Chain.getValue(1);
2372 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2373 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2374 // node so that legalize doesn't hack it.
2375 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2376 Subtarget->isTargetMachO()) {
2377 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2378 const GlobalValue *GV = G->getGlobal();
2379 bool InternalLinkage = GV->hasInternalLinkage();
2380 if (InternalLinkage)
2381 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2383 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2385 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2387 } else if (ExternalSymbolSDNode *S =
2388 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2389 const char *Sym = S->getSymbol();
2391 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2392 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2394 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2395 const GlobalValue *GV = G->getGlobal();
2396 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2397 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2398 const char *Sym = S->getSymbol();
2399 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2402 // We don't usually want to end the call-sequence here because we would tidy
2403 // the frame up *after* the call, however in the ABI-changing tail-call case
2404 // we've carefully laid out the parameters so that when sp is reset they'll be
2405 // in the correct location.
2406 if (IsTailCall && !IsSibCall) {
2407 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2408 DAG.getIntPtrConstant(0, true), InFlag, DL);
2409 InFlag = Chain.getValue(1);
2412 std::vector<SDValue> Ops;
2413 Ops.push_back(Chain);
2414 Ops.push_back(Callee);
2417 // Each tail call may have to adjust the stack by a different amount, so
2418 // this information must travel along with the operation for eventual
2419 // consumption by emitEpilogue.
2420 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
2423 // Add argument registers to the end of the list so that they are known live
2425 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2426 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2427 RegsToPass[i].second.getValueType()));
2429 // Add a register mask operand representing the call-preserved registers.
2430 const uint32_t *Mask;
2431 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2432 const AArch64RegisterInfo *ARI =
2433 static_cast<const AArch64RegisterInfo *>(TRI);
2435 // For 'this' returns, use the X0-preserving mask if applicable
2436 Mask = ARI->getThisReturnPreservedMask(CallConv);
2438 IsThisReturn = false;
2439 Mask = ARI->getCallPreservedMask(CallConv);
2442 Mask = ARI->getCallPreservedMask(CallConv);
2444 assert(Mask && "Missing call preserved mask for calling convention");
2445 Ops.push_back(DAG.getRegisterMask(Mask));
2447 if (InFlag.getNode())
2448 Ops.push_back(InFlag);
2450 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2452 // If we're doing a tall call, use a TC_RETURN here rather than an
2453 // actual call instruction.
2455 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2457 // Returns a chain and a flag for retval copy to use.
2458 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2459 InFlag = Chain.getValue(1);
2461 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2462 ? RoundUpToAlignment(NumBytes, 16)
2465 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2466 DAG.getIntPtrConstant(CalleePopBytes, true),
2469 InFlag = Chain.getValue(1);
2471 // Handle result values, copying them out of physregs into vregs that we
2473 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2474 InVals, IsThisReturn,
2475 IsThisReturn ? OutVals[0] : SDValue());
2478 bool AArch64TargetLowering::CanLowerReturn(
2479 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2480 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2481 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2482 ? RetCC_AArch64_WebKit_JS
2483 : RetCC_AArch64_AAPCS;
2484 SmallVector<CCValAssign, 16> RVLocs;
2485 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
2486 return CCInfo.CheckReturn(Outs, RetCC);
2490 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2492 const SmallVectorImpl<ISD::OutputArg> &Outs,
2493 const SmallVectorImpl<SDValue> &OutVals,
2494 SDLoc DL, SelectionDAG &DAG) const {
2495 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2496 ? RetCC_AArch64_WebKit_JS
2497 : RetCC_AArch64_AAPCS;
2498 SmallVector<CCValAssign, 16> RVLocs;
2499 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2500 getTargetMachine(), RVLocs, *DAG.getContext());
2501 CCInfo.AnalyzeReturn(Outs, RetCC);
2503 // Copy the result values into the output registers.
2505 SmallVector<SDValue, 4> RetOps(1, Chain);
2506 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2507 ++i, ++realRVLocIdx) {
2508 CCValAssign &VA = RVLocs[i];
2509 assert(VA.isRegLoc() && "Can only return in registers!");
2510 SDValue Arg = OutVals[realRVLocIdx];
2512 switch (VA.getLocInfo()) {
2514 llvm_unreachable("Unknown loc info!");
2515 case CCValAssign::Full:
2516 if (Outs[i].ArgVT == MVT::i1) {
2517 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2518 // value. This is strictly redundant on Darwin (which uses "zeroext
2519 // i1"), but will be optimised out before ISel.
2520 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2521 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2524 case CCValAssign::BCvt:
2525 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2529 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2530 Flag = Chain.getValue(1);
2531 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2534 RetOps[0] = Chain; // Update chain.
2536 // Add the flag if we have it.
2538 RetOps.push_back(Flag);
2540 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2543 //===----------------------------------------------------------------------===//
2544 // Other Lowering Code
2545 //===----------------------------------------------------------------------===//
2547 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2548 SelectionDAG &DAG) const {
2549 EVT PtrVT = getPointerTy();
2551 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2552 unsigned char OpFlags =
2553 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2555 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2556 "unexpected offset in global node");
2558 // This also catched the large code model case for Darwin.
2559 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2560 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2561 // FIXME: Once remat is capable of dealing with instructions with register
2562 // operands, expand this into two nodes instead of using a wrapper node.
2563 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2566 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2567 const unsigned char MO_NC = AArch64II::MO_NC;
2569 AArch64ISD::WrapperLarge, DL, PtrVT,
2570 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
2571 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
2572 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
2573 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
2575 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
2576 // the only correct model on Darwin.
2577 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2578 OpFlags | AArch64II::MO_PAGE);
2579 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2580 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
2582 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2583 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2587 /// \brief Convert a TLS address reference into the correct sequence of loads
2588 /// and calls to compute the variable's address (for Darwin, currently) and
2589 /// return an SDValue containing the final node.
2591 /// Darwin only has one TLS scheme which must be capable of dealing with the
2592 /// fully general situation, in the worst case. This means:
2593 /// + "extern __thread" declaration.
2594 /// + Defined in a possibly unknown dynamic library.
2596 /// The general system is that each __thread variable has a [3 x i64] descriptor
2597 /// which contains information used by the runtime to calculate the address. The
2598 /// only part of this the compiler needs to know about is the first xword, which
2599 /// contains a function pointer that must be called with the address of the
2600 /// entire descriptor in "x0".
2602 /// Since this descriptor may be in a different unit, in general even the
2603 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
2605 /// adrp x0, _var@TLVPPAGE
2606 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
2607 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
2608 /// ; the function pointer
2609 /// blr x1 ; Uses descriptor address in x0
2610 /// ; Address of _var is now in x0.
2612 /// If the address of _var's descriptor *is* known to the linker, then it can
2613 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
2614 /// a slight efficiency gain.
2616 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
2617 SelectionDAG &DAG) const {
2618 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
2621 MVT PtrVT = getPointerTy();
2622 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2625 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2626 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
2628 // The first entry in the descriptor is a function pointer that we must call
2629 // to obtain the address of the variable.
2630 SDValue Chain = DAG.getEntryNode();
2631 SDValue FuncTLVGet =
2632 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
2633 false, true, true, 8);
2634 Chain = FuncTLVGet.getValue(1);
2636 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2637 MFI->setAdjustsStack(true);
2639 // TLS calls preserve all registers except those that absolutely must be
2640 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2642 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2643 const AArch64RegisterInfo *ARI =
2644 static_cast<const AArch64RegisterInfo *>(TRI);
2645 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2647 // Finally, we can make the call. This is just a degenerate version of a
2648 // normal AArch64 call node: x0 takes the address of the descriptor, and
2649 // returns the address of the variable in this thread.
2650 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
2652 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2653 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
2654 DAG.getRegisterMask(Mask), Chain.getValue(1));
2655 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
2658 /// When accessing thread-local variables under either the general-dynamic or
2659 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
2660 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
2661 /// is a function pointer to carry out the resolution. This function takes the
2662 /// address of the descriptor in X0 and returns the TPIDR_EL0 offset in X0. All
2663 /// other registers (except LR, NZCV) are preserved.
2665 /// Thus, the ideal call sequence on AArch64 is:
2667 /// adrp x0, :tlsdesc:thread_var
2668 /// ldr x8, [x0, :tlsdesc_lo12:thread_var]
2669 /// add x0, x0, :tlsdesc_lo12:thread_var
2670 /// .tlsdesccall thread_var
2672 /// (TPIDR_EL0 offset now in x0).
2674 /// The ".tlsdesccall" directive instructs the assembler to insert a particular
2675 /// relocation to help the linker relax this sequence if it turns out to be too
2678 /// FIXME: we currently produce an extra, duplicated, ADRP instruction, but this
2680 SDValue AArch64TargetLowering::LowerELFTLSDescCall(SDValue SymAddr,
2681 SDValue DescAddr, SDLoc DL,
2682 SelectionDAG &DAG) const {
2683 EVT PtrVT = getPointerTy();
2685 // The function we need to call is simply the first entry in the GOT for this
2686 // descriptor, load it in preparation.
2687 SDValue Func = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, SymAddr);
2689 // TLS calls preserve all registers except those that absolutely must be
2690 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2692 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2693 const AArch64RegisterInfo *ARI =
2694 static_cast<const AArch64RegisterInfo *>(TRI);
2695 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2697 // The function takes only one argument: the address of the descriptor itself
2699 SDValue Glue, Chain;
2700 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
2701 Glue = Chain.getValue(1);
2703 // We're now ready to populate the argument list, as with a normal call:
2704 SmallVector<SDValue, 6> Ops;
2705 Ops.push_back(Chain);
2706 Ops.push_back(Func);
2707 Ops.push_back(SymAddr);
2708 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
2709 Ops.push_back(DAG.getRegisterMask(Mask));
2710 Ops.push_back(Glue);
2712 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2713 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALL, DL, NodeTys, Ops);
2714 Glue = Chain.getValue(1);
2716 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
2720 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
2721 SelectionDAG &DAG) const {
2722 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
2723 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2724 "ELF TLS only supported in small memory model");
2725 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2727 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
2730 EVT PtrVT = getPointerTy();
2732 const GlobalValue *GV = GA->getGlobal();
2734 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
2736 if (Model == TLSModel::LocalExec) {
2737 SDValue HiVar = DAG.getTargetGlobalAddress(
2738 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
2739 SDValue LoVar = DAG.getTargetGlobalAddress(
2741 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
2743 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2744 DAG.getTargetConstant(16, MVT::i32)),
2746 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, TPOff, LoVar,
2747 DAG.getTargetConstant(0, MVT::i32)),
2749 } else if (Model == TLSModel::InitialExec) {
2750 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2751 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
2752 } else if (Model == TLSModel::LocalDynamic) {
2753 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
2754 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
2755 // the beginning of the module's TLS region, followed by a DTPREL offset
2758 // These accesses will need deduplicating if there's more than one.
2759 AArch64FunctionInfo *MFI =
2760 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
2761 MFI->incNumLocalDynamicTLSAccesses();
2763 // Accesses used in this sequence go via the TLS descriptor which lives in
2764 // the GOT. Prepare an address we can use to handle this.
2765 SDValue HiDesc = DAG.getTargetExternalSymbol(
2766 "_TLS_MODULE_BASE_", PtrVT, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2767 SDValue LoDesc = DAG.getTargetExternalSymbol(
2768 "_TLS_MODULE_BASE_", PtrVT,
2769 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
2771 // First argument to the descriptor call is the address of the descriptor
2773 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2774 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2776 // The call needs a relocation too for linker relaxation. It doesn't make
2777 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2779 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2782 // Now we can calculate the offset from TPIDR_EL0 to this module's
2783 // thread-local area.
2784 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2786 // Now use :dtprel_whatever: operations to calculate this variable's offset
2787 // in its thread-storage area.
2788 SDValue HiVar = DAG.getTargetGlobalAddress(
2789 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
2790 SDValue LoVar = DAG.getTargetGlobalAddress(
2791 GV, DL, MVT::i64, 0,
2792 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
2795 SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2796 DAG.getTargetConstant(16, MVT::i32)),
2799 SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, DTPOff, LoVar,
2800 DAG.getTargetConstant(0, MVT::i32)),
2803 TPOff = DAG.getNode(ISD::ADD, DL, PtrVT, TPOff, DTPOff);
2804 } else if (Model == TLSModel::GeneralDynamic) {
2805 // Accesses used in this sequence go via the TLS descriptor which lives in
2806 // the GOT. Prepare an address we can use to handle this.
2807 SDValue HiDesc = DAG.getTargetGlobalAddress(
2808 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2809 SDValue LoDesc = DAG.getTargetGlobalAddress(
2811 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
2813 // First argument to the descriptor call is the address of the descriptor
2815 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2816 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2818 // The call needs a relocation too for linker relaxation. It doesn't make
2819 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2822 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2824 // Finally we can make a call to calculate the offset from tpidr_el0.
2825 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2827 llvm_unreachable("Unsupported ELF TLS access model");
2829 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
2832 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
2833 SelectionDAG &DAG) const {
2834 if (Subtarget->isTargetDarwin())
2835 return LowerDarwinGlobalTLSAddress(Op, DAG);
2836 else if (Subtarget->isTargetELF())
2837 return LowerELFGlobalTLSAddress(Op, DAG);
2839 llvm_unreachable("Unexpected platform trying to use TLS");
2841 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2842 SDValue Chain = Op.getOperand(0);
2843 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2844 SDValue LHS = Op.getOperand(2);
2845 SDValue RHS = Op.getOperand(3);
2846 SDValue Dest = Op.getOperand(4);
2849 // Handle f128 first, since lowering it will result in comparing the return
2850 // value of a libcall against zero, which is just what the rest of LowerBR_CC
2851 // is expecting to deal with.
2852 if (LHS.getValueType() == MVT::f128) {
2853 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2855 // If softenSetCCOperands returned a scalar, we need to compare the result
2856 // against zero to select between true and false values.
2857 if (!RHS.getNode()) {
2858 RHS = DAG.getConstant(0, LHS.getValueType());
2863 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
2865 unsigned Opc = LHS.getOpcode();
2866 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
2867 cast<ConstantSDNode>(RHS)->isOne() &&
2868 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
2869 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
2870 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
2871 "Unexpected condition code.");
2872 // Only lower legal XALUO ops.
2873 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
2876 // The actual operation with overflow check.
2877 AArch64CC::CondCode OFCC;
2878 SDValue Value, Overflow;
2879 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
2881 if (CC == ISD::SETNE)
2882 OFCC = getInvertedCondCode(OFCC);
2883 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
2885 return DAG.getNode(AArch64ISD::BRCOND, SDLoc(LHS), MVT::Other, Chain, Dest,
2889 if (LHS.getValueType().isInteger()) {
2890 assert((LHS.getValueType() == RHS.getValueType()) &&
2891 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
2893 // If the RHS of the comparison is zero, we can potentially fold this
2894 // to a specialized branch.
2895 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
2896 if (RHSC && RHSC->getZExtValue() == 0) {
2897 if (CC == ISD::SETEQ) {
2898 // See if we can use a TBZ to fold in an AND as well.
2899 // TBZ has a smaller branch displacement than CBZ. If the offset is
2900 // out of bounds, a late MI-layer pass rewrites branches.
2901 // 403.gcc is an example that hits this case.
2902 if (LHS.getOpcode() == ISD::AND &&
2903 isa<ConstantSDNode>(LHS.getOperand(1)) &&
2904 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
2905 SDValue Test = LHS.getOperand(0);
2906 uint64_t Mask = LHS.getConstantOperandVal(1);
2908 // TBZ only operates on i64's, but the ext should be free.
2909 if (Test.getValueType() == MVT::i32)
2910 Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64);
2912 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
2913 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
2916 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
2917 } else if (CC == ISD::SETNE) {
2918 // See if we can use a TBZ to fold in an AND as well.
2919 // TBZ has a smaller branch displacement than CBZ. If the offset is
2920 // out of bounds, a late MI-layer pass rewrites branches.
2921 // 403.gcc is an example that hits this case.
2922 if (LHS.getOpcode() == ISD::AND &&
2923 isa<ConstantSDNode>(LHS.getOperand(1)) &&
2924 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
2925 SDValue Test = LHS.getOperand(0);
2926 uint64_t Mask = LHS.getConstantOperandVal(1);
2928 // TBNZ only operates on i64's, but the ext should be free.
2929 if (Test.getValueType() == MVT::i32)
2930 Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64);
2932 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
2933 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
2936 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
2941 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
2942 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
2946 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2948 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
2949 // clean. Some of them require two branches to implement.
2950 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
2951 AArch64CC::CondCode CC1, CC2;
2952 changeFPCCToAArch64CC(CC, CC1, CC2);
2953 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
2955 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
2956 if (CC2 != AArch64CC::AL) {
2957 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
2958 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
2965 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
2966 SelectionDAG &DAG) const {
2967 EVT VT = Op.getValueType();
2970 SDValue In1 = Op.getOperand(0);
2971 SDValue In2 = Op.getOperand(1);
2972 EVT SrcVT = In2.getValueType();
2974 if (SrcVT == MVT::f32 && VT == MVT::f64)
2975 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
2976 else if (SrcVT == MVT::f64 && VT == MVT::f32)
2977 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0));
2979 // FIXME: Src type is different, bail out for now. Can VT really be a
2986 SDValue EltMask, VecVal1, VecVal2;
2987 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
2990 EltMask = DAG.getConstant(0x80000000ULL, EltVT);
2992 if (!VT.isVector()) {
2993 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
2994 DAG.getUNDEF(VecVT), In1);
2995 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
2996 DAG.getUNDEF(VecVT), In2);
2998 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
2999 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3001 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3005 // We want to materialize a mask with the the high bit set, but the AdvSIMD
3006 // immediate moves cannot materialize that in a single instruction for
3007 // 64-bit elements. Instead, materialize zero and then negate it.
3008 EltMask = DAG.getConstant(0, EltVT);
3010 if (!VT.isVector()) {
3011 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3012 DAG.getUNDEF(VecVT), In1);
3013 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3014 DAG.getUNDEF(VecVT), In2);
3016 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3017 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3020 llvm_unreachable("Invalid type for copysign!");
3023 std::vector<SDValue> BuildVectorOps;
3024 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i)
3025 BuildVectorOps.push_back(EltMask);
3027 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, BuildVectorOps);
3029 // If we couldn't materialize the mask above, then the mask vector will be
3030 // the zero vector, and we need to negate it here.
3031 if (VT == MVT::f64 || VT == MVT::v2f64) {
3032 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3033 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3034 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3038 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3041 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3042 else if (VT == MVT::f64)
3043 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3045 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3048 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3049 if (DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
3050 AttributeSet::FunctionIndex, Attribute::NoImplicitFloat))
3053 // While there is no integer popcount instruction, it can
3054 // be more efficiently lowered to the following sequence that uses
3055 // AdvSIMD registers/instructions as long as the copies to/from
3056 // the AdvSIMD registers are cheap.
3057 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3058 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3059 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3060 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3061 SDValue Val = Op.getOperand(0);
3063 EVT VT = Op.getValueType();
3064 SDValue ZeroVec = DAG.getUNDEF(MVT::v8i8);
3067 if (VT == MVT::i32) {
3068 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val);
3069 VecVal = DAG.getTargetInsertSubreg(AArch64::ssub, DL, MVT::v8i8, ZeroVec,
3072 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3075 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, VecVal);
3076 SDValue UaddLV = DAG.getNode(
3077 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3078 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
3081 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3085 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3087 if (Op.getValueType().isVector())
3088 return LowerVSETCC(Op, DAG);
3090 SDValue LHS = Op.getOperand(0);
3091 SDValue RHS = Op.getOperand(1);
3092 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3095 // We chose ZeroOrOneBooleanContents, so use zero and one.
3096 EVT VT = Op.getValueType();
3097 SDValue TVal = DAG.getConstant(1, VT);
3098 SDValue FVal = DAG.getConstant(0, VT);
3100 // Handle f128 first, since one possible outcome is a normal integer
3101 // comparison which gets picked up by the next if statement.
3102 if (LHS.getValueType() == MVT::f128) {
3103 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3105 // If softenSetCCOperands returned a scalar, use it.
3106 if (!RHS.getNode()) {
3107 assert(LHS.getValueType() == Op.getValueType() &&
3108 "Unexpected setcc expansion!");
3113 if (LHS.getValueType().isInteger()) {
3116 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3118 // Note that we inverted the condition above, so we reverse the order of
3119 // the true and false operands here. This will allow the setcc to be
3120 // matched to a single CSINC instruction.
3121 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3124 // Now we know we're dealing with FP values.
3125 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3127 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3128 // and do the comparison.
3129 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3131 AArch64CC::CondCode CC1, CC2;
3132 changeFPCCToAArch64CC(CC, CC1, CC2);
3133 if (CC2 == AArch64CC::AL) {
3134 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3135 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3137 // Note that we inverted the condition above, so we reverse the order of
3138 // the true and false operands here. This will allow the setcc to be
3139 // matched to a single CSINC instruction.
3140 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3142 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3143 // totally clean. Some of them require two CSELs to implement. As is in
3144 // this case, we emit the first CSEL and then emit a second using the output
3145 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3147 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3148 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3150 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3152 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3153 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3157 /// A SELECT_CC operation is really some kind of max or min if both values being
3158 /// compared are, in some sense, equal to the results in either case. However,
3159 /// it is permissible to compare f32 values and produce directly extended f64
3162 /// Extending the comparison operands would also be allowed, but is less likely
3163 /// to happen in practice since their use is right here. Note that truncate
3164 /// operations would *not* be semantically equivalent.
3165 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3169 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3170 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3171 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3172 Result.getValueType() == MVT::f64) {
3174 APFloat CmpVal = CCmp->getValueAPF();
3175 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3176 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3179 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3182 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3183 SelectionDAG &DAG) const {
3184 SDValue CC = Op->getOperand(0);
3185 SDValue TVal = Op->getOperand(1);
3186 SDValue FVal = Op->getOperand(2);
3189 unsigned Opc = CC.getOpcode();
3190 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3192 if (CC.getResNo() == 1 &&
3193 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3194 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3195 // Only lower legal XALUO ops.
3196 if (!DAG.getTargetLoweringInfo().isTypeLegal(CC->getValueType(0)))
3199 AArch64CC::CondCode OFCC;
3200 SDValue Value, Overflow;
3201 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CC.getValue(0), DAG);
3202 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3204 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3208 if (CC.getOpcode() == ISD::SETCC)
3209 return DAG.getSelectCC(DL, CC.getOperand(0), CC.getOperand(1), TVal, FVal,
3210 cast<CondCodeSDNode>(CC.getOperand(2))->get());
3212 return DAG.getSelectCC(DL, CC, DAG.getConstant(0, CC.getValueType()), TVal,
3216 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3217 SelectionDAG &DAG) const {
3218 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3219 SDValue LHS = Op.getOperand(0);
3220 SDValue RHS = Op.getOperand(1);
3221 SDValue TVal = Op.getOperand(2);
3222 SDValue FVal = Op.getOperand(3);
3225 // Handle f128 first, because it will result in a comparison of some RTLIB
3226 // call result against zero.
3227 if (LHS.getValueType() == MVT::f128) {
3228 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3230 // If softenSetCCOperands returned a scalar, we need to compare the result
3231 // against zero to select between true and false values.
3232 if (!RHS.getNode()) {
3233 RHS = DAG.getConstant(0, LHS.getValueType());
3238 // Handle integers first.
3239 if (LHS.getValueType().isInteger()) {
3240 assert((LHS.getValueType() == RHS.getValueType()) &&
3241 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3243 unsigned Opcode = AArch64ISD::CSEL;
3245 // If both the TVal and the FVal are constants, see if we can swap them in
3246 // order to for a CSINV or CSINC out of them.
3247 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3248 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3250 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3251 std::swap(TVal, FVal);
3252 std::swap(CTVal, CFVal);
3253 CC = ISD::getSetCCInverse(CC, true);
3254 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3255 std::swap(TVal, FVal);
3256 std::swap(CTVal, CFVal);
3257 CC = ISD::getSetCCInverse(CC, true);
3258 } else if (TVal.getOpcode() == ISD::XOR) {
3259 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3260 // with a CSINV rather than a CSEL.
3261 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3263 if (CVal && CVal->isAllOnesValue()) {
3264 std::swap(TVal, FVal);
3265 std::swap(CTVal, CFVal);
3266 CC = ISD::getSetCCInverse(CC, true);
3268 } else if (TVal.getOpcode() == ISD::SUB) {
3269 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3270 // that we can match with a CSNEG rather than a CSEL.
3271 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3273 if (CVal && CVal->isNullValue()) {
3274 std::swap(TVal, FVal);
3275 std::swap(CTVal, CFVal);
3276 CC = ISD::getSetCCInverse(CC, true);
3278 } else if (CTVal && CFVal) {
3279 const int64_t TrueVal = CTVal->getSExtValue();
3280 const int64_t FalseVal = CFVal->getSExtValue();
3283 // If both TVal and FVal are constants, see if FVal is the
3284 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3285 // instead of a CSEL in that case.
3286 if (TrueVal == ~FalseVal) {
3287 Opcode = AArch64ISD::CSINV;
3288 } else if (TrueVal == -FalseVal) {
3289 Opcode = AArch64ISD::CSNEG;
3290 } else if (TVal.getValueType() == MVT::i32) {
3291 // If our operands are only 32-bit wide, make sure we use 32-bit
3292 // arithmetic for the check whether we can use CSINC. This ensures that
3293 // the addition in the check will wrap around properly in case there is
3294 // an overflow (which would not be the case if we do the check with
3295 // 64-bit arithmetic).
3296 const uint32_t TrueVal32 = CTVal->getZExtValue();
3297 const uint32_t FalseVal32 = CFVal->getZExtValue();
3299 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3300 Opcode = AArch64ISD::CSINC;
3302 if (TrueVal32 > FalseVal32) {
3306 // 64-bit check whether we can use CSINC.
3307 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3308 Opcode = AArch64ISD::CSINC;
3310 if (TrueVal > FalseVal) {
3315 // Swap TVal and FVal if necessary.
3317 std::swap(TVal, FVal);
3318 std::swap(CTVal, CFVal);
3319 CC = ISD::getSetCCInverse(CC, true);
3322 if (Opcode != AArch64ISD::CSEL) {
3323 // Drop FVal since we can get its value by simply inverting/negating
3330 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3332 EVT VT = Op.getValueType();
3333 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3336 // Now we know we're dealing with FP values.
3337 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3338 assert(LHS.getValueType() == RHS.getValueType());
3339 EVT VT = Op.getValueType();
3341 // Try to match this select into a max/min operation, which have dedicated
3342 // opcode in the instruction set.
3343 // FIXME: This is not correct in the presence of NaNs, so we only enable this
3345 if (getTargetMachine().Options.NoNaNsFPMath) {
3346 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
3347 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
3348 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
3349 CC = ISD::getSetCCSwappedOperands(CC);
3350 std::swap(MinMaxLHS, MinMaxRHS);
3353 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
3354 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
3364 return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
3372 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
3378 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3379 // and do the comparison.
3380 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3382 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3383 // clean. Some of them require two CSELs to implement.
3384 AArch64CC::CondCode CC1, CC2;
3385 changeFPCCToAArch64CC(CC, CC1, CC2);
3386 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3387 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3389 // If we need a second CSEL, emit it, using the output of the first as the
3390 // RHS. We're effectively OR'ing the two CC's together.
3391 if (CC2 != AArch64CC::AL) {
3392 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3393 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3396 // Otherwise, return the output of the first CSEL.
3400 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3401 SelectionDAG &DAG) const {
3402 // Jump table entries as PC relative offsets. No additional tweaking
3403 // is necessary here. Just get the address of the jump table.
3404 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3405 EVT PtrVT = getPointerTy();
3408 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3409 !Subtarget->isTargetMachO()) {
3410 const unsigned char MO_NC = AArch64II::MO_NC;
3412 AArch64ISD::WrapperLarge, DL, PtrVT,
3413 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3414 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3415 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3416 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3417 AArch64II::MO_G0 | MO_NC));
3421 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3422 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3423 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3424 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3425 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3428 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3429 SelectionDAG &DAG) const {
3430 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3431 EVT PtrVT = getPointerTy();
3434 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3435 // Use the GOT for the large code model on iOS.
3436 if (Subtarget->isTargetMachO()) {
3437 SDValue GotAddr = DAG.getTargetConstantPool(
3438 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3440 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3443 const unsigned char MO_NC = AArch64II::MO_NC;
3445 AArch64ISD::WrapperLarge, DL, PtrVT,
3446 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3447 CP->getOffset(), AArch64II::MO_G3),
3448 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3449 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3450 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3451 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3452 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3453 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3455 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3456 // ELF, the only valid one on Darwin.
3458 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3459 CP->getOffset(), AArch64II::MO_PAGE);
3460 SDValue Lo = DAG.getTargetConstantPool(
3461 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3462 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3464 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3465 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3469 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3470 SelectionDAG &DAG) const {
3471 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3472 EVT PtrVT = getPointerTy();
3474 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3475 !Subtarget->isTargetMachO()) {
3476 const unsigned char MO_NC = AArch64II::MO_NC;
3478 AArch64ISD::WrapperLarge, DL, PtrVT,
3479 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3480 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3481 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3482 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3484 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3485 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3487 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3488 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3492 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3493 SelectionDAG &DAG) const {
3494 AArch64FunctionInfo *FuncInfo =
3495 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3499 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3500 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3501 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3502 MachinePointerInfo(SV), false, false, 0);
3505 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3506 SelectionDAG &DAG) const {
3507 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3508 // Standard, section B.3.
3509 MachineFunction &MF = DAG.getMachineFunction();
3510 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3513 SDValue Chain = Op.getOperand(0);
3514 SDValue VAList = Op.getOperand(1);
3515 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3516 SmallVector<SDValue, 4> MemOps;
3518 // void *__stack at offset 0
3520 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3521 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3522 MachinePointerInfo(SV), false, false, 8));
3524 // void *__gr_top at offset 8
3525 int GPRSize = FuncInfo->getVarArgsGPRSize();
3527 SDValue GRTop, GRTopAddr;
3529 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3530 DAG.getConstant(8, getPointerTy()));
3532 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3533 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3534 DAG.getConstant(GPRSize, getPointerTy()));
3536 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3537 MachinePointerInfo(SV, 8), false, false, 8));
3540 // void *__vr_top at offset 16
3541 int FPRSize = FuncInfo->getVarArgsFPRSize();
3543 SDValue VRTop, VRTopAddr;
3544 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3545 DAG.getConstant(16, getPointerTy()));
3547 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3548 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3549 DAG.getConstant(FPRSize, getPointerTy()));
3551 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3552 MachinePointerInfo(SV, 16), false, false, 8));
3555 // int __gr_offs at offset 24
3556 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3557 DAG.getConstant(24, getPointerTy()));
3558 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3559 GROffsAddr, MachinePointerInfo(SV, 24), false,
3562 // int __vr_offs at offset 28
3563 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3564 DAG.getConstant(28, getPointerTy()));
3565 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3566 VROffsAddr, MachinePointerInfo(SV, 28), false,
3569 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3572 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3573 SelectionDAG &DAG) const {
3574 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3575 : LowerAAPCS_VASTART(Op, DAG);
3578 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3579 SelectionDAG &DAG) const {
3580 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3582 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3583 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3584 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3586 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1),
3587 Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32),
3588 8, false, false, MachinePointerInfo(DestSV),
3589 MachinePointerInfo(SrcSV));
3592 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3593 assert(Subtarget->isTargetDarwin() &&
3594 "automatic va_arg instruction only works on Darwin");
3596 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3597 EVT VT = Op.getValueType();
3599 SDValue Chain = Op.getOperand(0);
3600 SDValue Addr = Op.getOperand(1);
3601 unsigned Align = Op.getConstantOperandVal(3);
3603 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3604 MachinePointerInfo(V), false, false, false, 0);
3605 Chain = VAList.getValue(1);
3608 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
3609 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3610 DAG.getConstant(Align - 1, getPointerTy()));
3611 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
3612 DAG.getConstant(-(int64_t)Align, getPointerTy()));
3615 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
3616 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
3618 // Scalar integer and FP values smaller than 64 bits are implicitly extended
3619 // up to 64 bits. At the very least, we have to increase the striding of the
3620 // vaargs list to match this, and for FP values we need to introduce
3621 // FP_ROUND nodes as well.
3622 if (VT.isInteger() && !VT.isVector())
3624 bool NeedFPTrunc = false;
3625 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
3630 // Increment the pointer, VAList, to the next vaarg
3631 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3632 DAG.getConstant(ArgSize, getPointerTy()));
3633 // Store the incremented VAList to the legalized pointer
3634 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
3637 // Load the actual argument out of the pointer VAList
3639 // Load the value as an f64.
3640 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
3641 MachinePointerInfo(), false, false, false, 0);
3642 // Round the value down to an f32.
3643 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
3644 DAG.getIntPtrConstant(1));
3645 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
3646 // Merge the rounded value with the chain output of the load.
3647 return DAG.getMergeValues(Ops, DL);
3650 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
3654 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
3655 SelectionDAG &DAG) const {
3656 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3657 MFI->setFrameAddressIsTaken(true);
3659 EVT VT = Op.getValueType();
3661 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3663 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
3665 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
3666 MachinePointerInfo(), false, false, false, 0);
3670 // FIXME? Maybe this could be a TableGen attribute on some registers and
3671 // this table could be generated automatically from RegInfo.
3672 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
3674 unsigned Reg = StringSwitch<unsigned>(RegName)
3675 .Case("sp", AArch64::SP)
3679 report_fatal_error("Invalid register name global variable");
3682 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
3683 SelectionDAG &DAG) const {
3684 MachineFunction &MF = DAG.getMachineFunction();
3685 MachineFrameInfo *MFI = MF.getFrameInfo();
3686 MFI->setReturnAddressIsTaken(true);
3688 EVT VT = Op.getValueType();
3690 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3692 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3693 SDValue Offset = DAG.getConstant(8, getPointerTy());
3694 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
3695 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
3696 MachinePointerInfo(), false, false, false, 0);
3699 // Return LR, which contains the return address. Mark it an implicit live-in.
3700 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
3701 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
3704 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3705 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3706 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
3707 SelectionDAG &DAG) const {
3708 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3709 EVT VT = Op.getValueType();
3710 unsigned VTBits = VT.getSizeInBits();
3712 SDValue ShOpLo = Op.getOperand(0);
3713 SDValue ShOpHi = Op.getOperand(1);
3714 SDValue ShAmt = Op.getOperand(2);
3716 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3718 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3720 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3721 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3722 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3723 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3724 DAG.getConstant(VTBits, MVT::i64));
3725 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3727 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3728 ISD::SETGE, dl, DAG);
3729 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3731 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3732 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3734 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3736 // AArch64 shifts larger than the register width are wrapped rather than
3737 // clamped, so we can't just emit "hi >> x".
3738 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3739 SDValue TrueValHi = Opc == ISD::SRA
3740 ? DAG.getNode(Opc, dl, VT, ShOpHi,
3741 DAG.getConstant(VTBits - 1, MVT::i64))
3742 : DAG.getConstant(0, VT);
3744 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
3746 SDValue Ops[2] = { Lo, Hi };
3747 return DAG.getMergeValues(Ops, dl);
3750 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3751 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3752 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
3753 SelectionDAG &DAG) const {
3754 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3755 EVT VT = Op.getValueType();
3756 unsigned VTBits = VT.getSizeInBits();
3758 SDValue ShOpLo = Op.getOperand(0);
3759 SDValue ShOpHi = Op.getOperand(1);
3760 SDValue ShAmt = Op.getOperand(2);
3763 assert(Op.getOpcode() == ISD::SHL_PARTS);
3764 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3765 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3766 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3767 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3768 DAG.getConstant(VTBits, MVT::i64));
3769 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3770 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3772 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3774 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3775 ISD::SETGE, dl, DAG);
3776 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3778 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
3780 // AArch64 shifts of larger than register sizes are wrapped rather than
3781 // clamped, so we can't just emit "lo << a" if a is too big.
3782 SDValue TrueValLo = DAG.getConstant(0, VT);
3783 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3785 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3787 SDValue Ops[2] = { Lo, Hi };
3788 return DAG.getMergeValues(Ops, dl);
3791 bool AArch64TargetLowering::isOffsetFoldingLegal(
3792 const GlobalAddressSDNode *GA) const {
3793 // The AArch64 target doesn't support folding offsets into global addresses.
3797 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3798 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
3799 // FIXME: We should be able to handle f128 as well with a clever lowering.
3800 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
3804 return AArch64_AM::getFP64Imm(Imm) != -1;
3805 else if (VT == MVT::f32)
3806 return AArch64_AM::getFP32Imm(Imm) != -1;
3810 //===----------------------------------------------------------------------===//
3811 // AArch64 Optimization Hooks
3812 //===----------------------------------------------------------------------===//
3814 //===----------------------------------------------------------------------===//
3815 // AArch64 Inline Assembly Support
3816 //===----------------------------------------------------------------------===//
3818 // Table of Constraints
3819 // TODO: This is the current set of constraints supported by ARM for the
3820 // compiler, not all of them may make sense, e.g. S may be difficult to support.
3822 // r - A general register
3823 // w - An FP/SIMD register of some size in the range v0-v31
3824 // x - An FP/SIMD register of some size in the range v0-v15
3825 // I - Constant that can be used with an ADD instruction
3826 // J - Constant that can be used with a SUB instruction
3827 // K - Constant that can be used with a 32-bit logical instruction
3828 // L - Constant that can be used with a 64-bit logical instruction
3829 // M - Constant that can be used as a 32-bit MOV immediate
3830 // N - Constant that can be used as a 64-bit MOV immediate
3831 // Q - A memory reference with base register and no offset
3832 // S - A symbolic address
3833 // Y - Floating point constant zero
3834 // Z - Integer constant zero
3836 // Note that general register operands will be output using their 64-bit x
3837 // register name, whatever the size of the variable, unless the asm operand
3838 // is prefixed by the %w modifier. Floating-point and SIMD register operands
3839 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
3842 /// getConstraintType - Given a constraint letter, return the type of
3843 /// constraint it is for this target.
3844 AArch64TargetLowering::ConstraintType
3845 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
3846 if (Constraint.size() == 1) {
3847 switch (Constraint[0]) {
3854 return C_RegisterClass;
3855 // An address with a single base register. Due to the way we
3856 // currently handle addresses it is the same as 'r'.
3861 return TargetLowering::getConstraintType(Constraint);
3864 /// Examine constraint type and operand type and determine a weight value.
3865 /// This object must already have been set up with the operand type
3866 /// and the current alternative constraint selected.
3867 TargetLowering::ConstraintWeight
3868 AArch64TargetLowering::getSingleConstraintMatchWeight(
3869 AsmOperandInfo &info, const char *constraint) const {
3870 ConstraintWeight weight = CW_Invalid;
3871 Value *CallOperandVal = info.CallOperandVal;
3872 // If we don't have a value, we can't do a match,
3873 // but allow it at the lowest weight.
3874 if (!CallOperandVal)
3876 Type *type = CallOperandVal->getType();
3877 // Look at the constraint type.
3878 switch (*constraint) {
3880 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3884 if (type->isFloatingPointTy() || type->isVectorTy())
3885 weight = CW_Register;
3888 weight = CW_Constant;
3894 std::pair<unsigned, const TargetRegisterClass *>
3895 AArch64TargetLowering::getRegForInlineAsmConstraint(
3896 const std::string &Constraint, MVT VT) const {
3897 if (Constraint.size() == 1) {
3898 switch (Constraint[0]) {
3900 if (VT.getSizeInBits() == 64)
3901 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
3902 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
3905 return std::make_pair(0U, &AArch64::FPR32RegClass);
3906 if (VT.getSizeInBits() == 64)
3907 return std::make_pair(0U, &AArch64::FPR64RegClass);
3908 if (VT.getSizeInBits() == 128)
3909 return std::make_pair(0U, &AArch64::FPR128RegClass);
3911 // The instructions that this constraint is designed for can
3912 // only take 128-bit registers so just use that regclass.
3914 if (VT.getSizeInBits() == 128)
3915 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
3919 if (StringRef("{cc}").equals_lower(Constraint))
3920 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
3922 // Use the default implementation in TargetLowering to convert the register
3923 // constraint into a member of a register class.
3924 std::pair<unsigned, const TargetRegisterClass *> Res;
3925 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3927 // Not found as a standard register?
3929 unsigned Size = Constraint.size();
3930 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
3931 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
3932 const std::string Reg =
3933 std::string(&Constraint[2], &Constraint[Size - 1]);
3934 int RegNo = atoi(Reg.c_str());
3935 if (RegNo >= 0 && RegNo <= 31) {
3936 // v0 - v31 are aliases of q0 - q31.
3937 // By default we'll emit v0-v31 for this unless there's a modifier where
3938 // we'll emit the correct register as well.
3939 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
3940 Res.second = &AArch64::FPR128RegClass;
3948 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3949 /// vector. If it is invalid, don't add anything to Ops.
3950 void AArch64TargetLowering::LowerAsmOperandForConstraint(
3951 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
3952 SelectionDAG &DAG) const {
3955 // Currently only support length 1 constraints.
3956 if (Constraint.length() != 1)
3959 char ConstraintLetter = Constraint[0];
3960 switch (ConstraintLetter) {
3964 // This set of constraints deal with valid constants for various instructions.
3965 // Validate and return a target constant for them if we can.
3967 // 'z' maps to xzr or wzr so it needs an input of 0.
3968 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3969 if (!C || C->getZExtValue() != 0)
3972 if (Op.getValueType() == MVT::i64)
3973 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
3975 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
3985 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3989 // Grab the value and do some validation.
3990 uint64_t CVal = C->getZExtValue();
3991 switch (ConstraintLetter) {
3992 // The I constraint applies only to simple ADD or SUB immediate operands:
3993 // i.e. 0 to 4095 with optional shift by 12
3994 // The J constraint applies only to ADD or SUB immediates that would be
3995 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
3996 // instruction [or vice versa], in other words -1 to -4095 with optional
3997 // left shift by 12.
3999 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4003 uint64_t NVal = -C->getSExtValue();
4004 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal))
4008 // The K and L constraints apply *only* to logical immediates, including
4009 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4010 // been removed and MOV should be used). So these constraints have to
4011 // distinguish between bit patterns that are valid 32-bit or 64-bit
4012 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4013 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4016 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4020 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4023 // The M and N constraints are a superset of K and L respectively, for use
4024 // with the MOV (immediate) alias. As well as the logical immediates they
4025 // also match 32 or 64-bit immediates that can be loaded either using a
4026 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4027 // (M) or 64-bit 0x1234000000000000 (N) etc.
4028 // As a note some of this code is liberally stolen from the asm parser.
4030 if (!isUInt<32>(CVal))
4032 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4034 if ((CVal & 0xFFFF) == CVal)
4036 if ((CVal & 0xFFFF0000ULL) == CVal)
4038 uint64_t NCVal = ~(uint32_t)CVal;
4039 if ((NCVal & 0xFFFFULL) == NCVal)
4041 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4046 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4048 if ((CVal & 0xFFFFULL) == CVal)
4050 if ((CVal & 0xFFFF0000ULL) == CVal)
4052 if ((CVal & 0xFFFF00000000ULL) == CVal)
4054 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4056 uint64_t NCVal = ~CVal;
4057 if ((NCVal & 0xFFFFULL) == NCVal)
4059 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4061 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4063 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4071 // All assembler immediates are 64-bit integers.
4072 Result = DAG.getTargetConstant(CVal, MVT::i64);
4076 if (Result.getNode()) {
4077 Ops.push_back(Result);
4081 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4084 //===----------------------------------------------------------------------===//
4085 // AArch64 Advanced SIMD Support
4086 //===----------------------------------------------------------------------===//
4088 /// WidenVector - Given a value in the V64 register class, produce the
4089 /// equivalent value in the V128 register class.
4090 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4091 EVT VT = V64Reg.getValueType();
4092 unsigned NarrowSize = VT.getVectorNumElements();
4093 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4094 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4097 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4098 V64Reg, DAG.getConstant(0, MVT::i32));
4101 /// getExtFactor - Determine the adjustment factor for the position when
4102 /// generating an "extract from vector registers" instruction.
4103 static unsigned getExtFactor(SDValue &V) {
4104 EVT EltType = V.getValueType().getVectorElementType();
4105 return EltType.getSizeInBits() / 8;
4108 /// NarrowVector - Given a value in the V128 register class, produce the
4109 /// equivalent value in the V64 register class.
4110 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4111 EVT VT = V128Reg.getValueType();
4112 unsigned WideSize = VT.getVectorNumElements();
4113 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4114 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4117 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4120 // Gather data to see if the operation can be modelled as a
4121 // shuffle in combination with VEXTs.
4122 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4123 SelectionDAG &DAG) const {
4125 EVT VT = Op.getValueType();
4126 unsigned NumElts = VT.getVectorNumElements();
4128 SmallVector<SDValue, 2> SourceVecs;
4129 SmallVector<unsigned, 2> MinElts;
4130 SmallVector<unsigned, 2> MaxElts;
4132 for (unsigned i = 0; i < NumElts; ++i) {
4133 SDValue V = Op.getOperand(i);
4134 if (V.getOpcode() == ISD::UNDEF)
4136 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4137 // A shuffle can only come from building a vector from various
4138 // elements of other vectors.
4142 // Record this extraction against the appropriate vector if possible...
4143 SDValue SourceVec = V.getOperand(0);
4144 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4145 bool FoundSource = false;
4146 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4147 if (SourceVecs[j] == SourceVec) {
4148 if (MinElts[j] > EltNo)
4150 if (MaxElts[j] < EltNo)
4157 // Or record a new source if not...
4159 SourceVecs.push_back(SourceVec);
4160 MinElts.push_back(EltNo);
4161 MaxElts.push_back(EltNo);
4165 // Currently only do something sane when at most two source vectors
4167 if (SourceVecs.size() > 2)
4170 SDValue ShuffleSrcs[2] = { DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4171 int VEXTOffsets[2] = { 0, 0 };
4173 // This loop extracts the usage patterns of the source vectors
4174 // and prepares appropriate SDValues for a shuffle if possible.
4175 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4176 if (SourceVecs[i].getValueType() == VT) {
4177 // No VEXT necessary
4178 ShuffleSrcs[i] = SourceVecs[i];
4181 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
4182 // We can pad out the smaller vector for free, so if it's part of a
4184 ShuffleSrcs[i] = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, SourceVecs[i],
4185 DAG.getUNDEF(SourceVecs[i].getValueType()));
4189 // Don't attempt to extract subvectors from BUILD_VECTOR sources
4190 // that expand or trunc the original value.
4191 // TODO: We can try to bitcast and ANY_EXTEND the result but
4192 // we need to consider the cost of vector ANY_EXTEND, and the
4193 // legality of all the types.
4194 if (SourceVecs[i].getValueType().getVectorElementType() !=
4195 VT.getVectorElementType())
4198 // Since only 64-bit and 128-bit vectors are legal on ARM and
4199 // we've eliminated the other cases...
4200 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2 * NumElts &&
4201 "unexpected vector sizes in ReconstructShuffle");
4203 if (MaxElts[i] - MinElts[i] >= NumElts) {
4204 // Span too large for a VEXT to cope
4208 if (MinElts[i] >= NumElts) {
4209 // The extraction can just take the second half
4210 VEXTOffsets[i] = NumElts;
4212 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, SourceVecs[i],
4213 DAG.getIntPtrConstant(NumElts));
4214 } else if (MaxElts[i] < NumElts) {
4215 // The extraction can just take the first half
4217 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4218 SourceVecs[i], DAG.getIntPtrConstant(0));
4220 // An actual VEXT is needed
4221 VEXTOffsets[i] = MinElts[i];
4222 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4223 SourceVecs[i], DAG.getIntPtrConstant(0));
4225 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, SourceVecs[i],
4226 DAG.getIntPtrConstant(NumElts));
4227 unsigned Imm = VEXTOffsets[i] * getExtFactor(VEXTSrc1);
4228 ShuffleSrcs[i] = DAG.getNode(AArch64ISD::EXT, dl, VT, VEXTSrc1, VEXTSrc2,
4229 DAG.getConstant(Imm, MVT::i32));
4233 SmallVector<int, 8> Mask;
4235 for (unsigned i = 0; i < NumElts; ++i) {
4236 SDValue Entry = Op.getOperand(i);
4237 if (Entry.getOpcode() == ISD::UNDEF) {
4242 SDValue ExtractVec = Entry.getOperand(0);
4244 cast<ConstantSDNode>(Op.getOperand(i).getOperand(1))->getSExtValue();
4245 if (ExtractVec == SourceVecs[0]) {
4246 Mask.push_back(ExtractElt - VEXTOffsets[0]);
4248 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
4252 // Final check before we try to produce nonsense...
4253 if (isShuffleMaskLegal(Mask, VT))
4254 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4260 // check if an EXT instruction can handle the shuffle mask when the
4261 // vector sources of the shuffle are the same.
4262 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4263 unsigned NumElts = VT.getVectorNumElements();
4265 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4271 // If this is a VEXT shuffle, the immediate value is the index of the first
4272 // element. The other shuffle indices must be the successive elements after
4274 unsigned ExpectedElt = Imm;
4275 for (unsigned i = 1; i < NumElts; ++i) {
4276 // Increment the expected index. If it wraps around, just follow it
4277 // back to index zero and keep going.
4279 if (ExpectedElt == NumElts)
4283 continue; // ignore UNDEF indices
4284 if (ExpectedElt != static_cast<unsigned>(M[i]))
4291 // check if an EXT instruction can handle the shuffle mask when the
4292 // vector sources of the shuffle are different.
4293 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4295 // Look for the first non-undef element.
4296 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4297 [](int Elt) {return Elt >= 0;});
4299 // Benefit form APInt to handle overflow when calculating expected element.
4300 unsigned NumElts = VT.getVectorNumElements();
4301 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4302 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4303 // The following shuffle indices must be the successive elements after the
4304 // first real element.
4305 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4306 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4307 if (FirstWrongElt != M.end())
4310 // The index of an EXT is the first element if it is not UNDEF.
4311 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4312 // value of the first element. E.g.
4313 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4314 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4315 // ExpectedElt is the last mask index plus 1.
4316 Imm = ExpectedElt.getZExtValue();
4318 // There are two difference cases requiring to reverse input vectors.
4319 // For example, for vector <4 x i32> we have the following cases,
4320 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4321 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4322 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4323 // to reverse two input vectors.
4332 /// isREVMask - Check if a vector shuffle corresponds to a REV
4333 /// instruction with the specified blocksize. (The order of the elements
4334 /// within each block of the vector is reversed.)
4335 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4336 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4337 "Only possible block sizes for REV are: 16, 32, 64");
4339 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4343 unsigned NumElts = VT.getVectorNumElements();
4344 unsigned BlockElts = M[0] + 1;
4345 // If the first shuffle index is UNDEF, be optimistic.
4347 BlockElts = BlockSize / EltSz;
4349 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4352 for (unsigned i = 0; i < NumElts; ++i) {
4354 continue; // ignore UNDEF indices
4355 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4362 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4363 unsigned NumElts = VT.getVectorNumElements();
4364 WhichResult = (M[0] == 0 ? 0 : 1);
4365 unsigned Idx = WhichResult * NumElts / 2;
4366 for (unsigned i = 0; i != NumElts; i += 2) {
4367 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4368 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4376 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4377 unsigned NumElts = VT.getVectorNumElements();
4378 WhichResult = (M[0] == 0 ? 0 : 1);
4379 for (unsigned i = 0; i != NumElts; ++i) {
4381 continue; // ignore UNDEF indices
4382 if ((unsigned)M[i] != 2 * i + WhichResult)
4389 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4390 unsigned NumElts = VT.getVectorNumElements();
4391 WhichResult = (M[0] == 0 ? 0 : 1);
4392 for (unsigned i = 0; i < NumElts; i += 2) {
4393 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4394 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4400 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4401 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4402 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4403 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4404 unsigned NumElts = VT.getVectorNumElements();
4405 WhichResult = (M[0] == 0 ? 0 : 1);
4406 unsigned Idx = WhichResult * NumElts / 2;
4407 for (unsigned i = 0; i != NumElts; i += 2) {
4408 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4409 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4417 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4418 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4419 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4420 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4421 unsigned Half = VT.getVectorNumElements() / 2;
4422 WhichResult = (M[0] == 0 ? 0 : 1);
4423 for (unsigned j = 0; j != 2; ++j) {
4424 unsigned Idx = WhichResult;
4425 for (unsigned i = 0; i != Half; ++i) {
4426 int MIdx = M[i + j * Half];
4427 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4436 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4437 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4438 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4439 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4440 unsigned NumElts = VT.getVectorNumElements();
4441 WhichResult = (M[0] == 0 ? 0 : 1);
4442 for (unsigned i = 0; i < NumElts; i += 2) {
4443 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4444 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4450 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4451 bool &DstIsLeft, int &Anomaly) {
4452 if (M.size() != static_cast<size_t>(NumInputElements))
4455 int NumLHSMatch = 0, NumRHSMatch = 0;
4456 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4458 for (int i = 0; i < NumInputElements; ++i) {
4468 LastLHSMismatch = i;
4470 if (M[i] == i + NumInputElements)
4473 LastRHSMismatch = i;
4476 if (NumLHSMatch == NumInputElements - 1) {
4478 Anomaly = LastLHSMismatch;
4480 } else if (NumRHSMatch == NumInputElements - 1) {
4482 Anomaly = LastRHSMismatch;
4489 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4490 if (VT.getSizeInBits() != 128)
4493 unsigned NumElts = VT.getVectorNumElements();
4495 for (int I = 0, E = NumElts / 2; I != E; I++) {
4500 int Offset = NumElts / 2;
4501 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4502 if (Mask[I] != I + SplitLHS * Offset)
4509 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4511 EVT VT = Op.getValueType();
4512 SDValue V0 = Op.getOperand(0);
4513 SDValue V1 = Op.getOperand(1);
4514 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4516 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4517 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4520 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4522 if (!isConcatMask(Mask, VT, SplitV0))
4525 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4526 VT.getVectorNumElements() / 2);
4528 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4529 DAG.getConstant(0, MVT::i64));
4531 if (V1.getValueType().getSizeInBits() == 128) {
4532 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4533 DAG.getConstant(0, MVT::i64));
4535 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4538 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4539 /// the specified operations to build the shuffle.
4540 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4541 SDValue RHS, SelectionDAG &DAG,
4543 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4544 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
4545 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
4548 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4557 OP_VUZPL, // VUZP, left result
4558 OP_VUZPR, // VUZP, right result
4559 OP_VZIPL, // VZIP, left result
4560 OP_VZIPR, // VZIP, right result
4561 OP_VTRNL, // VTRN, left result
4562 OP_VTRNR // VTRN, right result
4565 if (OpNum == OP_COPY) {
4566 if (LHSID == (1 * 9 + 2) * 9 + 3)
4568 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
4572 SDValue OpLHS, OpRHS;
4573 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4574 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4575 EVT VT = OpLHS.getValueType();
4579 llvm_unreachable("Unknown shuffle opcode!");
4581 // VREV divides the vector in half and swaps within the half.
4582 if (VT.getVectorElementType() == MVT::i32 ||
4583 VT.getVectorElementType() == MVT::f32)
4584 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
4585 // vrev <4 x i16> -> REV32
4586 if (VT.getVectorElementType() == MVT::i16)
4587 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
4588 // vrev <4 x i8> -> REV16
4589 assert(VT.getVectorElementType() == MVT::i8);
4590 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
4595 EVT EltTy = VT.getVectorElementType();
4597 if (EltTy == MVT::i8)
4598 Opcode = AArch64ISD::DUPLANE8;
4599 else if (EltTy == MVT::i16)
4600 Opcode = AArch64ISD::DUPLANE16;
4601 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
4602 Opcode = AArch64ISD::DUPLANE32;
4603 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
4604 Opcode = AArch64ISD::DUPLANE64;
4606 llvm_unreachable("Invalid vector element type?");
4608 if (VT.getSizeInBits() == 64)
4609 OpLHS = WidenVector(OpLHS, DAG);
4610 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64);
4611 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
4616 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
4617 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
4618 DAG.getConstant(Imm, MVT::i32));
4621 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
4624 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
4627 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
4630 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
4633 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
4636 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
4641 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
4642 SelectionDAG &DAG) {
4643 // Check to see if we can use the TBL instruction.
4644 SDValue V1 = Op.getOperand(0);
4645 SDValue V2 = Op.getOperand(1);
4648 EVT EltVT = Op.getValueType().getVectorElementType();
4649 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
4651 SmallVector<SDValue, 8> TBLMask;
4652 for (int Val : ShuffleMask) {
4653 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
4654 unsigned Offset = Byte + Val * BytesPerElt;
4655 TBLMask.push_back(DAG.getConstant(Offset, MVT::i32));
4659 MVT IndexVT = MVT::v8i8;
4660 unsigned IndexLen = 8;
4661 if (Op.getValueType().getSizeInBits() == 128) {
4662 IndexVT = MVT::v16i8;
4666 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
4667 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
4670 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
4672 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
4673 Shuffle = DAG.getNode(
4674 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4675 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
4676 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4677 makeArrayRef(TBLMask.data(), IndexLen)));
4679 if (IndexLen == 8) {
4680 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
4681 Shuffle = DAG.getNode(
4682 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4683 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
4684 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4685 makeArrayRef(TBLMask.data(), IndexLen)));
4687 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
4688 // cannot currently represent the register constraints on the input
4690 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
4691 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4692 // &TBLMask[0], IndexLen));
4693 Shuffle = DAG.getNode(
4694 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4695 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
4696 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4697 makeArrayRef(TBLMask.data(), IndexLen)));
4700 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
4703 static unsigned getDUPLANEOp(EVT EltType) {
4704 if (EltType == MVT::i8)
4705 return AArch64ISD::DUPLANE8;
4706 if (EltType == MVT::i16)
4707 return AArch64ISD::DUPLANE16;
4708 if (EltType == MVT::i32 || EltType == MVT::f32)
4709 return AArch64ISD::DUPLANE32;
4710 if (EltType == MVT::i64 || EltType == MVT::f64)
4711 return AArch64ISD::DUPLANE64;
4713 llvm_unreachable("Invalid vector element type?");
4716 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4717 SelectionDAG &DAG) const {
4719 EVT VT = Op.getValueType();
4721 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4723 // Convert shuffles that are directly supported on NEON to target-specific
4724 // DAG nodes, instead of keeping them as shuffles and matching them again
4725 // during code selection. This is more efficient and avoids the possibility
4726 // of inconsistencies between legalization and selection.
4727 ArrayRef<int> ShuffleMask = SVN->getMask();
4729 SDValue V1 = Op.getOperand(0);
4730 SDValue V2 = Op.getOperand(1);
4732 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
4733 V1.getValueType().getSimpleVT())) {
4734 int Lane = SVN->getSplatIndex();
4735 // If this is undef splat, generate it via "just" vdup, if possible.
4739 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
4740 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
4742 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
4743 // constant. If so, we can just reference the lane's definition directly.
4744 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
4745 !isa<ConstantSDNode>(V1.getOperand(Lane)))
4746 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
4748 // Otherwise, duplicate from the lane of the input vector.
4749 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
4751 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
4752 // to make a vector of the same size as this SHUFFLE. We can ignore the
4753 // extract entirely, and canonicalise the concat using WidenVector.
4754 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
4755 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
4756 V1 = V1.getOperand(0);
4757 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
4758 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
4759 Lane -= Idx * VT.getVectorNumElements() / 2;
4760 V1 = WidenVector(V1.getOperand(Idx), DAG);
4761 } else if (VT.getSizeInBits() == 64)
4762 V1 = WidenVector(V1, DAG);
4764 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64));
4767 if (isREVMask(ShuffleMask, VT, 64))
4768 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
4769 if (isREVMask(ShuffleMask, VT, 32))
4770 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
4771 if (isREVMask(ShuffleMask, VT, 16))
4772 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
4774 bool ReverseEXT = false;
4776 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
4779 Imm *= getExtFactor(V1);
4780 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
4781 DAG.getConstant(Imm, MVT::i32));
4782 } else if (V2->getOpcode() == ISD::UNDEF &&
4783 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
4784 Imm *= getExtFactor(V1);
4785 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
4786 DAG.getConstant(Imm, MVT::i32));
4789 unsigned WhichResult;
4790 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
4791 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
4792 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4794 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
4795 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
4796 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4798 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
4799 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
4800 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4803 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4804 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
4805 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4807 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4808 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
4809 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4811 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4812 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
4813 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4816 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
4817 if (Concat.getNode())
4822 int NumInputElements = V1.getValueType().getVectorNumElements();
4823 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
4824 SDValue DstVec = DstIsLeft ? V1 : V2;
4825 SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64);
4827 SDValue SrcVec = V1;
4828 int SrcLane = ShuffleMask[Anomaly];
4829 if (SrcLane >= NumInputElements) {
4831 SrcLane -= VT.getVectorNumElements();
4833 SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64);
4835 EVT ScalarVT = VT.getVectorElementType();
4836 if (ScalarVT.getSizeInBits() < 32)
4837 ScalarVT = MVT::i32;
4840 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
4841 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
4845 // If the shuffle is not directly supported and it has 4 elements, use
4846 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4847 unsigned NumElts = VT.getVectorNumElements();
4849 unsigned PFIndexes[4];
4850 for (unsigned i = 0; i != 4; ++i) {
4851 if (ShuffleMask[i] < 0)
4854 PFIndexes[i] = ShuffleMask[i];
4857 // Compute the index in the perfect shuffle table.
4858 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
4859 PFIndexes[2] * 9 + PFIndexes[3];
4860 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4861 unsigned Cost = (PFEntry >> 30);
4864 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4867 return GenerateTBL(Op, ShuffleMask, DAG);
4870 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
4872 EVT VT = BVN->getValueType(0);
4873 APInt SplatBits, SplatUndef;
4874 unsigned SplatBitSize;
4876 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4877 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
4879 for (unsigned i = 0; i < NumSplats; ++i) {
4880 CnstBits <<= SplatBitSize;
4881 UndefBits <<= SplatBitSize;
4882 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
4883 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
4892 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
4893 SelectionDAG &DAG) const {
4894 BuildVectorSDNode *BVN =
4895 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
4896 SDValue LHS = Op.getOperand(0);
4898 EVT VT = Op.getValueType();
4903 APInt CnstBits(VT.getSizeInBits(), 0);
4904 APInt UndefBits(VT.getSizeInBits(), 0);
4905 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
4906 // We only have BIC vector immediate instruction, which is and-not.
4907 CnstBits = ~CnstBits;
4909 // We make use of a little bit of goto ickiness in order to avoid having to
4910 // duplicate the immediate matching logic for the undef toggled case.
4911 bool SecondTry = false;
4914 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
4915 CnstBits = CnstBits.zextOrTrunc(64);
4916 uint64_t CnstVal = CnstBits.getZExtValue();
4918 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
4919 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
4920 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4921 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4922 DAG.getConstant(CnstVal, MVT::i32),
4923 DAG.getConstant(0, MVT::i32));
4924 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4927 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
4928 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
4929 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4930 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4931 DAG.getConstant(CnstVal, MVT::i32),
4932 DAG.getConstant(8, MVT::i32));
4933 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4936 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
4937 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
4938 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4939 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4940 DAG.getConstant(CnstVal, MVT::i32),
4941 DAG.getConstant(16, MVT::i32));
4942 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4945 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
4946 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
4947 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4948 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4949 DAG.getConstant(CnstVal, MVT::i32),
4950 DAG.getConstant(24, MVT::i32));
4951 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4954 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
4955 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
4956 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
4957 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4958 DAG.getConstant(CnstVal, MVT::i32),
4959 DAG.getConstant(0, MVT::i32));
4960 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4963 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
4964 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
4965 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
4966 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4967 DAG.getConstant(CnstVal, MVT::i32),
4968 DAG.getConstant(8, MVT::i32));
4969 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4976 CnstBits = ~UndefBits;
4980 // We can always fall back to a non-immediate AND.
4985 // Specialized code to quickly find if PotentialBVec is a BuildVector that
4986 // consists of only the same constant int value, returned in reference arg
4988 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
4989 uint64_t &ConstVal) {
4990 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
4993 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
4996 EVT VT = Bvec->getValueType(0);
4997 unsigned NumElts = VT.getVectorNumElements();
4998 for (unsigned i = 1; i < NumElts; ++i)
4999 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5001 ConstVal = FirstElt->getZExtValue();
5005 static unsigned getIntrinsicID(const SDNode *N) {
5006 unsigned Opcode = N->getOpcode();
5009 return Intrinsic::not_intrinsic;
5010 case ISD::INTRINSIC_WO_CHAIN: {
5011 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5012 if (IID < Intrinsic::num_intrinsics)
5014 return Intrinsic::not_intrinsic;
5019 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5020 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5021 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5022 // Also, logical shift right -> sri, with the same structure.
5023 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5024 EVT VT = N->getValueType(0);
5031 // Is the first op an AND?
5032 const SDValue And = N->getOperand(0);
5033 if (And.getOpcode() != ISD::AND)
5036 // Is the second op an shl or lshr?
5037 SDValue Shift = N->getOperand(1);
5038 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5039 // or AArch64ISD::VLSHR vector, #shift
5040 unsigned ShiftOpc = Shift.getOpcode();
5041 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5043 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5045 // Is the shift amount constant?
5046 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5050 // Is the and mask vector all constant?
5052 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5055 // Is C1 == ~C2, taking into account how much one can shift elements of a
5057 uint64_t C2 = C2node->getZExtValue();
5058 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5059 if (C2 > ElemSizeInBits)
5061 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5062 if ((C1 & ElemMask) != (~C2 & ElemMask))
5065 SDValue X = And.getOperand(0);
5066 SDValue Y = Shift.getOperand(0);
5069 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5071 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5072 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
5074 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5075 DEBUG(N->dump(&DAG));
5076 DEBUG(dbgs() << "into: \n");
5077 DEBUG(ResultSLI->dump(&DAG));
5083 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5084 SelectionDAG &DAG) const {
5085 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5086 if (EnableAArch64SlrGeneration) {
5087 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5092 BuildVectorSDNode *BVN =
5093 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5094 SDValue LHS = Op.getOperand(1);
5096 EVT VT = Op.getValueType();
5098 // OR commutes, so try swapping the operands.
5100 LHS = Op.getOperand(0);
5101 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5106 APInt CnstBits(VT.getSizeInBits(), 0);
5107 APInt UndefBits(VT.getSizeInBits(), 0);
5108 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5109 // We make use of a little bit of goto ickiness in order to avoid having to
5110 // duplicate the immediate matching logic for the undef toggled case.
5111 bool SecondTry = false;
5114 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5115 CnstBits = CnstBits.zextOrTrunc(64);
5116 uint64_t CnstVal = CnstBits.getZExtValue();
5118 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5119 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5120 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5121 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5122 DAG.getConstant(CnstVal, MVT::i32),
5123 DAG.getConstant(0, MVT::i32));
5124 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5127 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5128 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5129 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5130 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5131 DAG.getConstant(CnstVal, MVT::i32),
5132 DAG.getConstant(8, MVT::i32));
5133 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5136 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5137 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5138 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5139 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5140 DAG.getConstant(CnstVal, MVT::i32),
5141 DAG.getConstant(16, MVT::i32));
5142 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5145 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5146 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5147 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5148 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5149 DAG.getConstant(CnstVal, MVT::i32),
5150 DAG.getConstant(24, MVT::i32));
5151 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5154 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5155 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5156 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5157 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5158 DAG.getConstant(CnstVal, MVT::i32),
5159 DAG.getConstant(0, MVT::i32));
5160 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5163 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5164 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5165 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5166 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5167 DAG.getConstant(CnstVal, MVT::i32),
5168 DAG.getConstant(8, MVT::i32));
5169 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5176 CnstBits = UndefBits;
5180 // We can always fall back to a non-immediate OR.
5185 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5186 SelectionDAG &DAG) const {
5187 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5189 EVT VT = Op.getValueType();
5191 APInt CnstBits(VT.getSizeInBits(), 0);
5192 APInt UndefBits(VT.getSizeInBits(), 0);
5193 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5194 // We make use of a little bit of goto ickiness in order to avoid having to
5195 // duplicate the immediate matching logic for the undef toggled case.
5196 bool SecondTry = false;
5199 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5200 CnstBits = CnstBits.zextOrTrunc(64);
5201 uint64_t CnstVal = CnstBits.getZExtValue();
5203 // Certain magic vector constants (used to express things like NOT
5204 // and NEG) are passed through unmodified. This allows codegen patterns
5205 // for these operations to match. Special-purpose patterns will lower
5206 // these immediates to MOVIs if it proves necessary.
5207 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5210 // The many faces of MOVI...
5211 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5212 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5213 if (VT.getSizeInBits() == 128) {
5214 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5215 DAG.getConstant(CnstVal, MVT::i32));
5216 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5219 // Support the V64 version via subregister insertion.
5220 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5221 DAG.getConstant(CnstVal, MVT::i32));
5222 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5225 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5226 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5227 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5228 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5229 DAG.getConstant(CnstVal, MVT::i32),
5230 DAG.getConstant(0, MVT::i32));
5231 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5234 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5235 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5236 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5237 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5238 DAG.getConstant(CnstVal, MVT::i32),
5239 DAG.getConstant(8, MVT::i32));
5240 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5243 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5244 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5245 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5246 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5247 DAG.getConstant(CnstVal, MVT::i32),
5248 DAG.getConstant(16, MVT::i32));
5249 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5252 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5253 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5254 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5255 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5256 DAG.getConstant(CnstVal, MVT::i32),
5257 DAG.getConstant(24, MVT::i32));
5258 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5261 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5262 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5263 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5264 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5265 DAG.getConstant(CnstVal, MVT::i32),
5266 DAG.getConstant(0, MVT::i32));
5267 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5270 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5271 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5272 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5273 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5274 DAG.getConstant(CnstVal, MVT::i32),
5275 DAG.getConstant(8, MVT::i32));
5276 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5279 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5280 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5281 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5282 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5283 DAG.getConstant(CnstVal, MVT::i32),
5284 DAG.getConstant(264, MVT::i32));
5285 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5288 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5289 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5290 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5291 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5292 DAG.getConstant(CnstVal, MVT::i32),
5293 DAG.getConstant(272, MVT::i32));
5294 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5297 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5298 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5299 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5300 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5301 DAG.getConstant(CnstVal, MVT::i32));
5302 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5305 // The few faces of FMOV...
5306 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5307 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5308 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5309 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5310 DAG.getConstant(CnstVal, MVT::i32));
5311 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5314 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5315 VT.getSizeInBits() == 128) {
5316 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5317 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5318 DAG.getConstant(CnstVal, MVT::i32));
5319 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5322 // The many faces of MVNI...
5324 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5325 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5326 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5327 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5328 DAG.getConstant(CnstVal, MVT::i32),
5329 DAG.getConstant(0, MVT::i32));
5330 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5333 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5334 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5335 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5336 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5337 DAG.getConstant(CnstVal, MVT::i32),
5338 DAG.getConstant(8, MVT::i32));
5339 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5342 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5343 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5344 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5345 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5346 DAG.getConstant(CnstVal, MVT::i32),
5347 DAG.getConstant(16, MVT::i32));
5348 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5351 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5352 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5353 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5354 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5355 DAG.getConstant(CnstVal, MVT::i32),
5356 DAG.getConstant(24, MVT::i32));
5357 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5360 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5361 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5362 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5363 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5364 DAG.getConstant(CnstVal, MVT::i32),
5365 DAG.getConstant(0, MVT::i32));
5366 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5369 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5370 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5371 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5372 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5373 DAG.getConstant(CnstVal, MVT::i32),
5374 DAG.getConstant(8, MVT::i32));
5375 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5378 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5379 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5380 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5381 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5382 DAG.getConstant(CnstVal, MVT::i32),
5383 DAG.getConstant(264, MVT::i32));
5384 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5387 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5388 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5389 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5390 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5391 DAG.getConstant(CnstVal, MVT::i32),
5392 DAG.getConstant(272, MVT::i32));
5393 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5400 CnstBits = UndefBits;
5405 // Scan through the operands to find some interesting properties we can
5407 // 1) If only one value is used, we can use a DUP, or
5408 // 2) if only the low element is not undef, we can just insert that, or
5409 // 3) if only one constant value is used (w/ some non-constant lanes),
5410 // we can splat the constant value into the whole vector then fill
5411 // in the non-constant lanes.
5412 // 4) FIXME: If different constant values are used, but we can intelligently
5413 // select the values we'll be overwriting for the non-constant
5414 // lanes such that we can directly materialize the vector
5415 // some other way (MOVI, e.g.), we can be sneaky.
5416 unsigned NumElts = VT.getVectorNumElements();
5417 bool isOnlyLowElement = true;
5418 bool usesOnlyOneValue = true;
5419 bool usesOnlyOneConstantValue = true;
5420 bool isConstant = true;
5421 unsigned NumConstantLanes = 0;
5423 SDValue ConstantValue;
5424 for (unsigned i = 0; i < NumElts; ++i) {
5425 SDValue V = Op.getOperand(i);
5426 if (V.getOpcode() == ISD::UNDEF)
5429 isOnlyLowElement = false;
5430 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5433 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5435 if (!ConstantValue.getNode())
5437 else if (ConstantValue != V)
5438 usesOnlyOneConstantValue = false;
5441 if (!Value.getNode())
5443 else if (V != Value)
5444 usesOnlyOneValue = false;
5447 if (!Value.getNode())
5448 return DAG.getUNDEF(VT);
5450 if (isOnlyLowElement)
5451 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5453 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5454 // i32 and try again.
5455 if (usesOnlyOneValue) {
5457 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5458 Value.getValueType() != VT)
5459 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5461 // This is actually a DUPLANExx operation, which keeps everything vectory.
5463 // DUPLANE works on 128-bit vectors, widen it if necessary.
5464 SDValue Lane = Value.getOperand(1);
5465 Value = Value.getOperand(0);
5466 if (Value.getValueType().getSizeInBits() == 64)
5467 Value = WidenVector(Value, DAG);
5469 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5470 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5473 if (VT.getVectorElementType().isFloatingPoint()) {
5474 SmallVector<SDValue, 8> Ops;
5476 (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
5477 for (unsigned i = 0; i < NumElts; ++i)
5478 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5479 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5480 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5481 Val = LowerBUILD_VECTOR(Val, DAG);
5483 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5487 // If there was only one constant value used and for more than one lane,
5488 // start by splatting that value, then replace the non-constant lanes. This
5489 // is better than the default, which will perform a separate initialization
5491 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5492 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5493 // Now insert the non-constant lanes.
5494 for (unsigned i = 0; i < NumElts; ++i) {
5495 SDValue V = Op.getOperand(i);
5496 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5497 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5498 // Note that type legalization likely mucked about with the VT of the
5499 // source operand, so we may have to convert it here before inserting.
5500 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5506 // If all elements are constants and the case above didn't get hit, fall back
5507 // to the default expansion, which will generate a load from the constant
5512 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5514 SDValue shuffle = ReconstructShuffle(Op, DAG);
5515 if (shuffle != SDValue())
5519 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5520 // know the default expansion would otherwise fall back on something even
5521 // worse. For a vector with one or two non-undef values, that's
5522 // scalar_to_vector for the elements followed by a shuffle (provided the
5523 // shuffle is valid for the target) and materialization element by element
5524 // on the stack followed by a load for everything else.
5525 if (!isConstant && !usesOnlyOneValue) {
5526 SDValue Vec = DAG.getUNDEF(VT);
5527 SDValue Op0 = Op.getOperand(0);
5528 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
5530 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
5531 // a) Avoid a RMW dependency on the full vector register, and
5532 // b) Allow the register coalescer to fold away the copy if the
5533 // value is already in an S or D register.
5534 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
5535 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
5537 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
5538 DAG.getTargetConstant(SubIdx, MVT::i32));
5539 Vec = SDValue(N, 0);
5542 for (; i < NumElts; ++i) {
5543 SDValue V = Op.getOperand(i);
5544 if (V.getOpcode() == ISD::UNDEF)
5546 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5547 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5552 // Just use the default expansion. We failed to find a better alternative.
5556 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
5557 SelectionDAG &DAG) const {
5558 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
5560 // Check for non-constant lane.
5561 if (!isa<ConstantSDNode>(Op.getOperand(2)))
5564 EVT VT = Op.getOperand(0).getValueType();
5566 // Insertion/extraction are legal for V128 types.
5567 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5568 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64)
5571 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5572 VT != MVT::v1i64 && VT != MVT::v2f32)
5575 // For V64 types, we perform insertion by expanding the value
5576 // to a V128 type and perform the insertion on that.
5578 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5579 EVT WideTy = WideVec.getValueType();
5581 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
5582 Op.getOperand(1), Op.getOperand(2));
5583 // Re-narrow the resultant vector.
5584 return NarrowVector(Node, DAG);
5588 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5589 SelectionDAG &DAG) const {
5590 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
5592 // Check for non-constant lane.
5593 if (!isa<ConstantSDNode>(Op.getOperand(1)))
5596 EVT VT = Op.getOperand(0).getValueType();
5598 // Insertion/extraction are legal for V128 types.
5599 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5600 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64)
5603 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5604 VT != MVT::v1i64 && VT != MVT::v2f32)
5607 // For V64 types, we perform extraction by expanding the value
5608 // to a V128 type and perform the extraction on that.
5610 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5611 EVT WideTy = WideVec.getValueType();
5613 EVT ExtrTy = WideTy.getVectorElementType();
5614 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
5617 // For extractions, we just return the result directly.
5618 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
5622 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
5623 SelectionDAG &DAG) const {
5624 EVT VT = Op.getOperand(0).getValueType();
5630 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5633 unsigned Val = Cst->getZExtValue();
5635 unsigned Size = Op.getValueType().getSizeInBits();
5639 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
5642 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
5645 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
5648 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
5651 llvm_unreachable("Unexpected vector type in extract_subvector!");
5654 // If this is extracting the upper 64-bits of a 128-bit vector, we match
5656 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
5662 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5664 if (VT.getVectorNumElements() == 4 &&
5665 (VT.is128BitVector() || VT.is64BitVector())) {
5666 unsigned PFIndexes[4];
5667 for (unsigned i = 0; i != 4; ++i) {
5671 PFIndexes[i] = M[i];
5674 // Compute the index in the perfect shuffle table.
5675 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5676 PFIndexes[2] * 9 + PFIndexes[3];
5677 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5678 unsigned Cost = (PFEntry >> 30);
5686 unsigned DummyUnsigned;
5688 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
5689 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
5690 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
5691 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
5692 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
5693 isZIPMask(M, VT, DummyUnsigned) ||
5694 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
5695 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
5696 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
5697 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
5698 isConcatMask(M, VT, VT.getSizeInBits() == 128));
5701 /// getVShiftImm - Check if this is a valid build_vector for the immediate
5702 /// operand of a vector shift operation, where all the elements of the
5703 /// build_vector must have the same constant integer value.
5704 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
5705 // Ignore bit_converts.
5706 while (Op.getOpcode() == ISD::BITCAST)
5707 Op = Op.getOperand(0);
5708 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5709 APInt SplatBits, SplatUndef;
5710 unsigned SplatBitSize;
5712 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
5713 HasAnyUndefs, ElementBits) ||
5714 SplatBitSize > ElementBits)
5716 Cnt = SplatBits.getSExtValue();
5720 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
5721 /// operand of a vector shift left operation. That value must be in the range:
5722 /// 0 <= Value < ElementBits for a left shift; or
5723 /// 0 <= Value <= ElementBits for a long left shift.
5724 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
5725 assert(VT.isVector() && "vector shift count is not a vector type");
5726 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5727 if (!getVShiftImm(Op, ElementBits, Cnt))
5729 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
5732 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
5733 /// operand of a vector shift right operation. For a shift opcode, the value
5734 /// is positive, but for an intrinsic the value count must be negative. The
5735 /// absolute value must be in the range:
5736 /// 1 <= |Value| <= ElementBits for a right shift; or
5737 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
5738 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
5740 assert(VT.isVector() && "vector shift count is not a vector type");
5741 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5742 if (!getVShiftImm(Op, ElementBits, Cnt))
5746 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
5749 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
5750 SelectionDAG &DAG) const {
5751 EVT VT = Op.getValueType();
5755 if (!Op.getOperand(1).getValueType().isVector())
5757 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5759 switch (Op.getOpcode()) {
5761 llvm_unreachable("unexpected shift opcode");
5764 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
5765 return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0),
5766 DAG.getConstant(Cnt, MVT::i32));
5767 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5768 DAG.getConstant(Intrinsic::aarch64_neon_ushl, MVT::i32),
5769 Op.getOperand(0), Op.getOperand(1));
5772 // Right shift immediate
5773 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
5776 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
5777 return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0),
5778 DAG.getConstant(Cnt, MVT::i32));
5781 // Right shift register. Note, there is not a shift right register
5782 // instruction, but the shift left register instruction takes a signed
5783 // value, where negative numbers specify a right shift.
5784 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
5785 : Intrinsic::aarch64_neon_ushl;
5786 // negate the shift amount
5787 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
5788 SDValue NegShiftLeft =
5789 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5790 DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift);
5791 return NegShiftLeft;
5797 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
5798 AArch64CC::CondCode CC, bool NoNans, EVT VT,
5799 SDLoc dl, SelectionDAG &DAG) {
5800 EVT SrcVT = LHS.getValueType();
5802 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
5803 APInt CnstBits(VT.getSizeInBits(), 0);
5804 APInt UndefBits(VT.getSizeInBits(), 0);
5805 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
5806 bool IsZero = IsCnst && (CnstBits == 0);
5808 if (SrcVT.getVectorElementType().isFloatingPoint()) {
5812 case AArch64CC::NE: {
5815 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
5817 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
5818 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
5822 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
5823 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
5826 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
5827 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
5830 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
5831 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
5834 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
5835 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
5839 // If we ignore NaNs then we can use to the MI implementation.
5843 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
5844 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
5851 case AArch64CC::NE: {
5854 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
5856 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
5857 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
5861 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
5862 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
5865 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
5866 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
5869 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
5870 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
5873 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
5874 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
5876 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
5878 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
5881 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
5882 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
5884 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
5886 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
5890 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
5891 SelectionDAG &DAG) const {
5892 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5893 SDValue LHS = Op.getOperand(0);
5894 SDValue RHS = Op.getOperand(1);
5897 if (LHS.getValueType().getVectorElementType().isInteger()) {
5898 assert(LHS.getValueType() == RHS.getValueType());
5899 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
5900 return EmitVectorComparison(LHS, RHS, AArch64CC, false, Op.getValueType(),
5904 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
5905 LHS.getValueType().getVectorElementType() == MVT::f64);
5907 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
5908 // clean. Some of them require two branches to implement.
5909 AArch64CC::CondCode CC1, CC2;
5911 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
5913 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
5915 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, Op.getValueType(), dl, DAG);
5919 if (CC2 != AArch64CC::AL) {
5921 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, Op.getValueType(), dl, DAG);
5922 if (!Cmp2.getNode())
5925 Cmp = DAG.getNode(ISD::OR, dl, Cmp.getValueType(), Cmp, Cmp2);
5929 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
5934 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
5935 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
5936 /// specified in the intrinsic calls.
5937 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5939 unsigned Intrinsic) const {
5940 switch (Intrinsic) {
5941 case Intrinsic::aarch64_neon_ld2:
5942 case Intrinsic::aarch64_neon_ld3:
5943 case Intrinsic::aarch64_neon_ld4:
5944 case Intrinsic::aarch64_neon_ld1x2:
5945 case Intrinsic::aarch64_neon_ld1x3:
5946 case Intrinsic::aarch64_neon_ld1x4:
5947 case Intrinsic::aarch64_neon_ld2lane:
5948 case Intrinsic::aarch64_neon_ld3lane:
5949 case Intrinsic::aarch64_neon_ld4lane:
5950 case Intrinsic::aarch64_neon_ld2r:
5951 case Intrinsic::aarch64_neon_ld3r:
5952 case Intrinsic::aarch64_neon_ld4r: {
5953 Info.opc = ISD::INTRINSIC_W_CHAIN;
5954 // Conservatively set memVT to the entire set of vectors loaded.
5955 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
5956 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5957 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
5960 Info.vol = false; // volatile loads with NEON intrinsics not supported
5961 Info.readMem = true;
5962 Info.writeMem = false;
5965 case Intrinsic::aarch64_neon_st2:
5966 case Intrinsic::aarch64_neon_st3:
5967 case Intrinsic::aarch64_neon_st4:
5968 case Intrinsic::aarch64_neon_st1x2:
5969 case Intrinsic::aarch64_neon_st1x3:
5970 case Intrinsic::aarch64_neon_st1x4:
5971 case Intrinsic::aarch64_neon_st2lane:
5972 case Intrinsic::aarch64_neon_st3lane:
5973 case Intrinsic::aarch64_neon_st4lane: {
5974 Info.opc = ISD::INTRINSIC_VOID;
5975 // Conservatively set memVT to the entire set of vectors stored.
5976 unsigned NumElts = 0;
5977 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
5978 Type *ArgTy = I.getArgOperand(ArgI)->getType();
5979 if (!ArgTy->isVectorTy())
5981 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
5983 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5984 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
5987 Info.vol = false; // volatile stores with NEON intrinsics not supported
5988 Info.readMem = false;
5989 Info.writeMem = true;
5992 case Intrinsic::aarch64_ldaxr:
5993 case Intrinsic::aarch64_ldxr: {
5994 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
5995 Info.opc = ISD::INTRINSIC_W_CHAIN;
5996 Info.memVT = MVT::getVT(PtrTy->getElementType());
5997 Info.ptrVal = I.getArgOperand(0);
5999 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6001 Info.readMem = true;
6002 Info.writeMem = false;
6005 case Intrinsic::aarch64_stlxr:
6006 case Intrinsic::aarch64_stxr: {
6007 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6008 Info.opc = ISD::INTRINSIC_W_CHAIN;
6009 Info.memVT = MVT::getVT(PtrTy->getElementType());
6010 Info.ptrVal = I.getArgOperand(1);
6012 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6014 Info.readMem = false;
6015 Info.writeMem = true;
6018 case Intrinsic::aarch64_ldaxp:
6019 case Intrinsic::aarch64_ldxp: {
6020 Info.opc = ISD::INTRINSIC_W_CHAIN;
6021 Info.memVT = MVT::i128;
6022 Info.ptrVal = I.getArgOperand(0);
6026 Info.readMem = true;
6027 Info.writeMem = false;
6030 case Intrinsic::aarch64_stlxp:
6031 case Intrinsic::aarch64_stxp: {
6032 Info.opc = ISD::INTRINSIC_W_CHAIN;
6033 Info.memVT = MVT::i128;
6034 Info.ptrVal = I.getArgOperand(2);
6038 Info.readMem = false;
6039 Info.writeMem = true;
6049 // Truncations from 64-bit GPR to 32-bit GPR is free.
6050 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6051 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6053 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6054 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6055 return NumBits1 > NumBits2;
6057 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6058 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6060 unsigned NumBits1 = VT1.getSizeInBits();
6061 unsigned NumBits2 = VT2.getSizeInBits();
6062 return NumBits1 > NumBits2;
6065 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6067 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6068 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6070 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6071 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6072 return NumBits1 == 32 && NumBits2 == 64;
6074 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6075 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6077 unsigned NumBits1 = VT1.getSizeInBits();
6078 unsigned NumBits2 = VT2.getSizeInBits();
6079 return NumBits1 == 32 && NumBits2 == 64;
6082 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6083 EVT VT1 = Val.getValueType();
6084 if (isZExtFree(VT1, VT2)) {
6088 if (Val.getOpcode() != ISD::LOAD)
6091 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6092 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6093 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6094 VT1.getSizeInBits() <= 32);
6097 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6098 unsigned &RequiredAligment) const {
6099 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6101 // Cyclone supports unaligned accesses.
6102 RequiredAligment = 0;
6103 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6104 return NumBits == 32 || NumBits == 64;
6107 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6108 unsigned &RequiredAligment) const {
6109 if (!LoadedType.isSimple() ||
6110 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6112 // Cyclone supports unaligned accesses.
6113 RequiredAligment = 0;
6114 unsigned NumBits = LoadedType.getSizeInBits();
6115 return NumBits == 32 || NumBits == 64;
6118 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6119 unsigned AlignCheck) {
6120 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6121 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6124 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6125 unsigned SrcAlign, bool IsMemset,
6128 MachineFunction &MF) const {
6129 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6130 // instruction to materialize the v2i64 zero and one store (with restrictive
6131 // addressing mode). Just do two i64 store of zero-registers.
6133 const Function *F = MF.getFunction();
6134 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6135 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
6136 Attribute::NoImplicitFloat) &&
6137 (memOpAlign(SrcAlign, DstAlign, 16) ||
6138 (allowsUnalignedMemoryAccesses(MVT::f128, 0, &Fast) && Fast)))
6141 return Size >= 8 ? MVT::i64 : MVT::i32;
6144 // 12-bit optionally shifted immediates are legal for adds.
6145 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6146 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6151 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6152 // immediates is the same as for an add or a sub.
6153 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6156 return isLegalAddImmediate(Immed);
6159 /// isLegalAddressingMode - Return true if the addressing mode represented
6160 /// by AM is legal for this target, for a load/store of the specified type.
6161 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6163 // AArch64 has five basic addressing modes:
6165 // reg + 9-bit signed offset
6166 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6168 // reg + SIZE_IN_BYTES * reg
6170 // No global is ever allowed as a base.
6174 // No reg+reg+imm addressing.
6175 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6178 // check reg + imm case:
6179 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6180 uint64_t NumBytes = 0;
6181 if (Ty->isSized()) {
6182 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6183 NumBytes = NumBits / 8;
6184 if (!isPowerOf2_64(NumBits))
6189 int64_t Offset = AM.BaseOffs;
6191 // 9-bit signed offset
6192 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6195 // 12-bit unsigned offset
6196 unsigned shift = Log2_64(NumBytes);
6197 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6198 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6199 (Offset >> shift) << shift == Offset)
6204 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6206 if (!AM.Scale || AM.Scale == 1 ||
6207 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6212 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6214 // Scaling factors are not free at all.
6215 // Operands | Rt Latency
6216 // -------------------------------------------
6218 // -------------------------------------------
6219 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6220 // Rt, [Xn, Wm, <extend> #imm] |
6221 if (isLegalAddressingMode(AM, Ty))
6222 // Scale represents reg2 * scale, thus account for 1 if
6223 // it is not equal to 0 or 1.
6224 return AM.Scale != 0 && AM.Scale != 1;
6228 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6229 VT = VT.getScalarType();
6234 switch (VT.getSimpleVT().SimpleTy) {
6246 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6247 // LR is a callee-save register, but we must treat it as clobbered by any call
6248 // site. Hence we include LR in the scratch registers, which are in turn added
6249 // as implicit-defs for stackmaps and patchpoints.
6250 static const MCPhysReg ScratchRegs[] = {
6251 AArch64::X16, AArch64::X17, AArch64::LR, 0
6257 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6258 EVT VT = N->getValueType(0);
6259 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6260 // it with shift to let it be lowered to UBFX.
6261 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6262 isa<ConstantSDNode>(N->getOperand(1))) {
6263 uint64_t TruncMask = N->getConstantOperandVal(1);
6264 if (isMask_64(TruncMask) &&
6265 N->getOperand(0).getOpcode() == ISD::SRL &&
6266 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6272 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
6274 assert(Ty->isIntegerTy());
6276 unsigned BitSize = Ty->getPrimitiveSizeInBits();
6280 int64_t Val = Imm.getSExtValue();
6281 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
6284 if ((int64_t)Val < 0)
6287 Val &= (1LL << 32) - 1;
6289 unsigned LZ = countLeadingZeros((uint64_t)Val);
6290 unsigned Shift = (63 - LZ) / 16;
6291 // MOVZ is free so return true for one or fewer MOVK.
6292 return (Shift < 3) ? true : false;
6295 // Generate SUBS and CSEL for integer abs.
6296 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
6297 EVT VT = N->getValueType(0);
6299 SDValue N0 = N->getOperand(0);
6300 SDValue N1 = N->getOperand(1);
6303 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
6304 // and change it to SUB and CSEL.
6305 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
6306 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6307 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6308 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6309 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
6310 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
6312 // Generate SUBS & CSEL.
6314 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
6315 N0.getOperand(0), DAG.getConstant(0, VT));
6316 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6317 DAG.getConstant(AArch64CC::PL, MVT::i32),
6318 SDValue(Cmp.getNode(), 1));
6323 // performXorCombine - Attempts to handle integer ABS.
6324 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
6325 TargetLowering::DAGCombinerInfo &DCI,
6326 const AArch64Subtarget *Subtarget) {
6327 if (DCI.isBeforeLegalizeOps())
6330 return performIntegerAbsCombine(N, DAG);
6333 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
6334 TargetLowering::DAGCombinerInfo &DCI,
6335 const AArch64Subtarget *Subtarget) {
6336 if (DCI.isBeforeLegalizeOps())
6339 // Multiplication of a power of two plus/minus one can be done more
6340 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6341 // future CPUs have a cheaper MADD instruction, this may need to be
6342 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
6343 // 64-bit is 5 cycles, so this is always a win.
6344 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6345 APInt Value = C->getAPIntValue();
6346 EVT VT = N->getValueType(0);
6347 APInt VM1 = Value - 1;
6348 if (VM1.isPowerOf2()) {
6349 // Multiplying by one more than a power of two, replace with a shift
6351 SDValue ShiftedVal =
6352 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6353 DAG.getConstant(VM1.logBase2(), MVT::i64));
6354 return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
6356 APInt VP1 = Value + 1;
6357 if (VP1.isPowerOf2()) {
6358 // Multiplying by one less than a power of two, replace with a shift
6360 SDValue ShiftedVal =
6361 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6362 DAG.getConstant(VP1.logBase2(), MVT::i64));
6363 return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
6369 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG) {
6370 EVT VT = N->getValueType(0);
6371 if (VT != MVT::f32 && VT != MVT::f64)
6373 // Only optimize when the source and destination types have the same width.
6374 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
6377 // If the result of an integer load is only used by an integer-to-float
6378 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
6379 // This eliminates an "integer-to-vector-move UOP and improve throughput.
6380 SDValue N0 = N->getOperand(0);
6381 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6382 // Do not change the width of a volatile load.
6383 !cast<LoadSDNode>(N0)->isVolatile()) {
6384 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6385 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
6386 LN0->getPointerInfo(), LN0->isVolatile(),
6387 LN0->isNonTemporal(), LN0->isInvariant(),
6388 LN0->getAlignment());
6390 // Make sure successors of the original load stay after it by updating them
6391 // to use the new Chain.
6392 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
6395 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
6396 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
6402 /// An EXTR instruction is made up of two shifts, ORed together. This helper
6403 /// searches for and classifies those shifts.
6404 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
6406 if (N.getOpcode() == ISD::SHL)
6408 else if (N.getOpcode() == ISD::SRL)
6413 if (!isa<ConstantSDNode>(N.getOperand(1)))
6416 ShiftAmount = N->getConstantOperandVal(1);
6417 Src = N->getOperand(0);
6421 /// EXTR instruction extracts a contiguous chunk of bits from two existing
6422 /// registers viewed as a high/low pair. This function looks for the pattern:
6423 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
6424 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
6426 static SDValue tryCombineToEXTR(SDNode *N,
6427 TargetLowering::DAGCombinerInfo &DCI) {
6428 SelectionDAG &DAG = DCI.DAG;
6430 EVT VT = N->getValueType(0);
6432 assert(N->getOpcode() == ISD::OR && "Unexpected root");
6434 if (VT != MVT::i32 && VT != MVT::i64)
6438 uint32_t ShiftLHS = 0;
6440 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
6444 uint32_t ShiftRHS = 0;
6446 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
6449 // If they're both trying to come from the high part of the register, they're
6450 // not really an EXTR.
6451 if (LHSFromHi == RHSFromHi)
6454 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
6458 std::swap(LHS, RHS);
6459 std::swap(ShiftLHS, ShiftRHS);
6462 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
6463 DAG.getConstant(ShiftRHS, MVT::i64));
6466 static SDValue tryCombineToBSL(SDNode *N,
6467 TargetLowering::DAGCombinerInfo &DCI) {
6468 EVT VT = N->getValueType(0);
6469 SelectionDAG &DAG = DCI.DAG;
6475 SDValue N0 = N->getOperand(0);
6476 if (N0.getOpcode() != ISD::AND)
6479 SDValue N1 = N->getOperand(1);
6480 if (N1.getOpcode() != ISD::AND)
6483 // We only have to look for constant vectors here since the general, variable
6484 // case can be handled in TableGen.
6485 unsigned Bits = VT.getVectorElementType().getSizeInBits();
6486 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
6487 for (int i = 1; i >= 0; --i)
6488 for (int j = 1; j >= 0; --j) {
6489 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
6490 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
6494 bool FoundMatch = true;
6495 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
6496 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
6497 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
6499 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
6506 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
6507 N0->getOperand(1 - i), N1->getOperand(1 - j));
6513 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
6514 const AArch64Subtarget *Subtarget) {
6515 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
6516 if (!EnableAArch64ExtrGeneration)
6518 SelectionDAG &DAG = DCI.DAG;
6519 EVT VT = N->getValueType(0);
6521 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
6524 SDValue Res = tryCombineToEXTR(N, DCI);
6528 Res = tryCombineToBSL(N, DCI);
6535 static SDValue performBitcastCombine(SDNode *N,
6536 TargetLowering::DAGCombinerInfo &DCI,
6537 SelectionDAG &DAG) {
6538 // Wait 'til after everything is legalized to try this. That way we have
6539 // legal vector types and such.
6540 if (DCI.isBeforeLegalizeOps())
6543 // Remove extraneous bitcasts around an extract_subvector.
6545 // (v4i16 (bitconvert
6546 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
6548 // (extract_subvector ((v8i16 ...), (i64 4)))
6550 // Only interested in 64-bit vectors as the ultimate result.
6551 EVT VT = N->getValueType(0);
6554 if (VT.getSimpleVT().getSizeInBits() != 64)
6556 // Is the operand an extract_subvector starting at the beginning or halfway
6557 // point of the vector? A low half may also come through as an
6558 // EXTRACT_SUBREG, so look for that, too.
6559 SDValue Op0 = N->getOperand(0);
6560 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
6561 !(Op0->isMachineOpcode() &&
6562 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
6564 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
6565 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
6566 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
6568 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
6569 if (idx != AArch64::dsub)
6571 // The dsub reference is equivalent to a lane zero subvector reference.
6574 // Look through the bitcast of the input to the extract.
6575 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
6577 SDValue Source = Op0->getOperand(0)->getOperand(0);
6578 // If the source type has twice the number of elements as our destination
6579 // type, we know this is an extract of the high or low half of the vector.
6580 EVT SVT = Source->getValueType(0);
6581 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
6584 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
6586 // Create the simplified form to just extract the low or high half of the
6587 // vector directly rather than bothering with the bitcasts.
6589 unsigned NumElements = VT.getVectorNumElements();
6591 SDValue HalfIdx = DAG.getConstant(NumElements, MVT::i64);
6592 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
6594 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32);
6595 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
6601 static SDValue performConcatVectorsCombine(SDNode *N,
6602 TargetLowering::DAGCombinerInfo &DCI,
6603 SelectionDAG &DAG) {
6604 // Wait 'til after everything is legalized to try this. That way we have
6605 // legal vector types and such.
6606 if (DCI.isBeforeLegalizeOps())
6610 EVT VT = N->getValueType(0);
6612 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
6613 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
6614 // canonicalise to that.
6615 if (N->getOperand(0) == N->getOperand(1) && VT.getVectorNumElements() == 2) {
6616 assert(VT.getVectorElementType().getSizeInBits() == 64);
6617 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT,
6618 WidenVector(N->getOperand(0), DAG),
6619 DAG.getConstant(0, MVT::i64));
6622 // Canonicalise concat_vectors so that the right-hand vector has as few
6623 // bit-casts as possible before its real operation. The primary matching
6624 // destination for these operations will be the narrowing "2" instructions,
6625 // which depend on the operation being performed on this right-hand vector.
6627 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
6629 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
6631 SDValue Op1 = N->getOperand(1);
6632 if (Op1->getOpcode() != ISD::BITCAST)
6634 SDValue RHS = Op1->getOperand(0);
6635 MVT RHSTy = RHS.getValueType().getSimpleVT();
6636 // If the RHS is not a vector, this is not the pattern we're looking for.
6637 if (!RHSTy.isVector())
6640 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
6642 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
6643 RHSTy.getVectorNumElements() * 2);
6645 ISD::BITCAST, dl, VT,
6646 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
6647 DAG.getNode(ISD::BITCAST, dl, RHSTy, N->getOperand(0)), RHS));
6650 static SDValue tryCombineFixedPointConvert(SDNode *N,
6651 TargetLowering::DAGCombinerInfo &DCI,
6652 SelectionDAG &DAG) {
6653 // Wait 'til after everything is legalized to try this. That way we have
6654 // legal vector types and such.
6655 if (DCI.isBeforeLegalizeOps())
6657 // Transform a scalar conversion of a value from a lane extract into a
6658 // lane extract of a vector conversion. E.g., from foo1 to foo2:
6659 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
6660 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
6662 // The second form interacts better with instruction selection and the
6663 // register allocator to avoid cross-class register copies that aren't
6664 // coalescable due to a lane reference.
6666 // Check the operand and see if it originates from a lane extract.
6667 SDValue Op1 = N->getOperand(1);
6668 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6669 // Yep, no additional predication needed. Perform the transform.
6670 SDValue IID = N->getOperand(0);
6671 SDValue Shift = N->getOperand(2);
6672 SDValue Vec = Op1.getOperand(0);
6673 SDValue Lane = Op1.getOperand(1);
6674 EVT ResTy = N->getValueType(0);
6678 // The vector width should be 128 bits by the time we get here, even
6679 // if it started as 64 bits (the extract_vector handling will have
6681 assert(Vec.getValueType().getSizeInBits() == 128 &&
6682 "unexpected vector size on extract_vector_elt!");
6683 if (Vec.getValueType() == MVT::v4i32)
6684 VecResTy = MVT::v4f32;
6685 else if (Vec.getValueType() == MVT::v2i64)
6686 VecResTy = MVT::v2f64;
6688 assert(0 && "unexpected vector type!");
6691 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
6692 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
6697 // AArch64 high-vector "long" operations are formed by performing the non-high
6698 // version on an extract_subvector of each operand which gets the high half:
6700 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
6702 // However, there are cases which don't have an extract_high explicitly, but
6703 // have another operation that can be made compatible with one for free. For
6706 // (dupv64 scalar) --> (extract_high (dup128 scalar))
6708 // This routine does the actual conversion of such DUPs, once outer routines
6709 // have determined that everything else is in order.
6710 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
6711 // We can handle most types of duplicate, but the lane ones have an extra
6712 // operand saying *which* lane, so we need to know.
6714 switch (N.getOpcode()) {
6715 case AArch64ISD::DUP:
6718 case AArch64ISD::DUPLANE8:
6719 case AArch64ISD::DUPLANE16:
6720 case AArch64ISD::DUPLANE32:
6721 case AArch64ISD::DUPLANE64:
6728 MVT NarrowTy = N.getSimpleValueType();
6729 if (!NarrowTy.is64BitVector())
6732 MVT ElementTy = NarrowTy.getVectorElementType();
6733 unsigned NumElems = NarrowTy.getVectorNumElements();
6734 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
6738 NewDUP = DAG.getNode(N.getOpcode(), SDLoc(N), NewDUPVT, N.getOperand(0),
6741 NewDUP = DAG.getNode(AArch64ISD::DUP, SDLoc(N), NewDUPVT, N.getOperand(0));
6743 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N.getNode()), NarrowTy,
6744 NewDUP, DAG.getConstant(NumElems, MVT::i64));
6747 static bool isEssentiallyExtractSubvector(SDValue N) {
6748 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
6751 return N.getOpcode() == ISD::BITCAST &&
6752 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
6755 /// \brief Helper structure to keep track of ISD::SET_CC operands.
6756 struct GenericSetCCInfo {
6757 const SDValue *Opnd0;
6758 const SDValue *Opnd1;
6762 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
6763 struct AArch64SetCCInfo {
6765 AArch64CC::CondCode CC;
6768 /// \brief Helper structure to keep track of SetCC information.
6770 GenericSetCCInfo Generic;
6771 AArch64SetCCInfo AArch64;
6774 /// \brief Helper structure to be able to read SetCC information. If set to
6775 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
6776 /// GenericSetCCInfo.
6777 struct SetCCInfoAndKind {
6782 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
6784 /// AArch64 lowered one.
6785 /// \p SetCCInfo is filled accordingly.
6786 /// \post SetCCInfo is meanginfull only when this function returns true.
6787 /// \return True when Op is a kind of SET_CC operation.
6788 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
6789 // If this is a setcc, this is straight forward.
6790 if (Op.getOpcode() == ISD::SETCC) {
6791 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
6792 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
6793 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6794 SetCCInfo.IsAArch64 = false;
6797 // Otherwise, check if this is a matching csel instruction.
6801 if (Op.getOpcode() != AArch64ISD::CSEL)
6803 // Set the information about the operands.
6804 // TODO: we want the operands of the Cmp not the csel
6805 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
6806 SetCCInfo.IsAArch64 = true;
6807 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
6808 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
6810 // Check that the operands matches the constraints:
6811 // (1) Both operands must be constants.
6812 // (2) One must be 1 and the other must be 0.
6813 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
6814 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6817 if (!TValue || !FValue)
6821 if (!TValue->isOne()) {
6822 // Update the comparison when we are interested in !cc.
6823 std::swap(TValue, FValue);
6824 SetCCInfo.Info.AArch64.CC =
6825 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
6827 return TValue->isOne() && FValue->isNullValue();
6830 // Returns true if Op is setcc or zext of setcc.
6831 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
6832 if (isSetCC(Op, Info))
6834 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
6835 isSetCC(Op->getOperand(0), Info));
6838 // The folding we want to perform is:
6839 // (add x, [zext] (setcc cc ...) )
6841 // (csel x, (add x, 1), !cc ...)
6843 // The latter will get matched to a CSINC instruction.
6844 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
6845 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
6846 SDValue LHS = Op->getOperand(0);
6847 SDValue RHS = Op->getOperand(1);
6848 SetCCInfoAndKind InfoAndKind;
6850 // If neither operand is a SET_CC, give up.
6851 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
6852 std::swap(LHS, RHS);
6853 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
6857 // FIXME: This could be generatized to work for FP comparisons.
6858 EVT CmpVT = InfoAndKind.IsAArch64
6859 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
6860 : InfoAndKind.Info.Generic.Opnd0->getValueType();
6861 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
6867 if (InfoAndKind.IsAArch64) {
6868 CCVal = DAG.getConstant(
6869 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), MVT::i32);
6870 Cmp = *InfoAndKind.Info.AArch64.Cmp;
6872 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
6873 *InfoAndKind.Info.Generic.Opnd1,
6874 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
6877 EVT VT = Op->getValueType(0);
6878 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, VT));
6879 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
6882 // The basic add/sub long vector instructions have variants with "2" on the end
6883 // which act on the high-half of their inputs. They are normally matched by
6886 // (add (zeroext (extract_high LHS)),
6887 // (zeroext (extract_high RHS)))
6888 // -> uaddl2 vD, vN, vM
6890 // However, if one of the extracts is something like a duplicate, this
6891 // instruction can still be used profitably. This function puts the DAG into a
6892 // more appropriate form for those patterns to trigger.
6893 static SDValue performAddSubLongCombine(SDNode *N,
6894 TargetLowering::DAGCombinerInfo &DCI,
6895 SelectionDAG &DAG) {
6896 if (DCI.isBeforeLegalizeOps())
6899 MVT VT = N->getSimpleValueType(0);
6900 if (!VT.is128BitVector()) {
6901 if (N->getOpcode() == ISD::ADD)
6902 return performSetccAddFolding(N, DAG);
6906 // Make sure both branches are extended in the same way.
6907 SDValue LHS = N->getOperand(0);
6908 SDValue RHS = N->getOperand(1);
6909 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
6910 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
6911 LHS.getOpcode() != RHS.getOpcode())
6914 unsigned ExtType = LHS.getOpcode();
6916 // It's not worth doing if at least one of the inputs isn't already an
6917 // extract, but we don't know which it'll be so we have to try both.
6918 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
6919 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
6923 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
6924 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
6925 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
6929 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
6932 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
6935 // Massage DAGs which we can use the high-half "long" operations on into
6936 // something isel will recognize better. E.g.
6938 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
6939 // (aarch64_neon_umull (extract_high (v2i64 vec)))
6940 // (extract_high (v2i64 (dup128 scalar)))))
6942 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
6943 TargetLowering::DAGCombinerInfo &DCI,
6944 SelectionDAG &DAG) {
6945 if (DCI.isBeforeLegalizeOps())
6948 SDValue LHS = N->getOperand(1);
6949 SDValue RHS = N->getOperand(2);
6950 assert(LHS.getValueType().is64BitVector() &&
6951 RHS.getValueType().is64BitVector() &&
6952 "unexpected shape for long operation");
6954 // Either node could be a DUP, but it's not worth doing both of them (you'd
6955 // just as well use the non-high version) so look for a corresponding extract
6956 // operation on the other "wing".
6957 if (isEssentiallyExtractSubvector(LHS)) {
6958 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
6961 } else if (isEssentiallyExtractSubvector(RHS)) {
6962 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
6967 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
6968 N->getOperand(0), LHS, RHS);
6971 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
6972 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
6973 unsigned ElemBits = ElemTy.getSizeInBits();
6975 int64_t ShiftAmount;
6976 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
6977 APInt SplatValue, SplatUndef;
6978 unsigned SplatBitSize;
6980 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
6981 HasAnyUndefs, ElemBits) ||
6982 SplatBitSize != ElemBits)
6985 ShiftAmount = SplatValue.getSExtValue();
6986 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
6987 ShiftAmount = CVN->getSExtValue();
6995 llvm_unreachable("Unknown shift intrinsic");
6996 case Intrinsic::aarch64_neon_sqshl:
6997 Opcode = AArch64ISD::SQSHL_I;
6998 IsRightShift = false;
7000 case Intrinsic::aarch64_neon_uqshl:
7001 Opcode = AArch64ISD::UQSHL_I;
7002 IsRightShift = false;
7004 case Intrinsic::aarch64_neon_srshl:
7005 Opcode = AArch64ISD::SRSHR_I;
7006 IsRightShift = true;
7008 case Intrinsic::aarch64_neon_urshl:
7009 Opcode = AArch64ISD::URSHR_I;
7010 IsRightShift = true;
7012 case Intrinsic::aarch64_neon_sqshlu:
7013 Opcode = AArch64ISD::SQSHLU_I;
7014 IsRightShift = false;
7018 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
7019 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7020 DAG.getConstant(-ShiftAmount, MVT::i32));
7021 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount <= ElemBits)
7022 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7023 DAG.getConstant(ShiftAmount, MVT::i32));
7028 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7029 // the intrinsics must be legal and take an i32, this means there's almost
7030 // certainly going to be a zext in the DAG which we can eliminate.
7031 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7032 SDValue AndN = N->getOperand(2);
7033 if (AndN.getOpcode() != ISD::AND)
7036 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7037 if (!CMask || CMask->getZExtValue() != Mask)
7040 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7041 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7044 static SDValue performIntrinsicCombine(SDNode *N,
7045 TargetLowering::DAGCombinerInfo &DCI,
7046 const AArch64Subtarget *Subtarget) {
7047 SelectionDAG &DAG = DCI.DAG;
7048 unsigned IID = getIntrinsicID(N);
7052 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7053 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7054 return tryCombineFixedPointConvert(N, DCI, DAG);
7056 case Intrinsic::aarch64_neon_fmax:
7057 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7058 N->getOperand(1), N->getOperand(2));
7059 case Intrinsic::aarch64_neon_fmin:
7060 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7061 N->getOperand(1), N->getOperand(2));
7062 case Intrinsic::aarch64_neon_smull:
7063 case Intrinsic::aarch64_neon_umull:
7064 case Intrinsic::aarch64_neon_pmull:
7065 case Intrinsic::aarch64_neon_sqdmull:
7066 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7067 case Intrinsic::aarch64_neon_sqshl:
7068 case Intrinsic::aarch64_neon_uqshl:
7069 case Intrinsic::aarch64_neon_sqshlu:
7070 case Intrinsic::aarch64_neon_srshl:
7071 case Intrinsic::aarch64_neon_urshl:
7072 return tryCombineShiftImm(IID, N, DAG);
7073 case Intrinsic::aarch64_crc32b:
7074 case Intrinsic::aarch64_crc32cb:
7075 return tryCombineCRC32(0xff, N, DAG);
7076 case Intrinsic::aarch64_crc32h:
7077 case Intrinsic::aarch64_crc32ch:
7078 return tryCombineCRC32(0xffff, N, DAG);
7083 static SDValue performExtendCombine(SDNode *N,
7084 TargetLowering::DAGCombinerInfo &DCI,
7085 SelectionDAG &DAG) {
7086 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
7087 // we can convert that DUP into another extract_high (of a bigger DUP), which
7088 // helps the backend to decide that an sabdl2 would be useful, saving a real
7089 // extract_high operation.
7090 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
7091 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
7092 SDNode *ABDNode = N->getOperand(0).getNode();
7093 unsigned IID = getIntrinsicID(ABDNode);
7094 if (IID == Intrinsic::aarch64_neon_sabd ||
7095 IID == Intrinsic::aarch64_neon_uabd) {
7096 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
7097 if (!NewABD.getNode())
7100 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
7105 // This is effectively a custom type legalization for AArch64.
7107 // Type legalization will split an extend of a small, legal, type to a larger
7108 // illegal type by first splitting the destination type, often creating
7109 // illegal source types, which then get legalized in isel-confusing ways,
7110 // leading to really terrible codegen. E.g.,
7111 // %result = v8i32 sext v8i8 %value
7113 // %losrc = extract_subreg %value, ...
7114 // %hisrc = extract_subreg %value, ...
7115 // %lo = v4i32 sext v4i8 %losrc
7116 // %hi = v4i32 sext v4i8 %hisrc
7117 // Things go rapidly downhill from there.
7119 // For AArch64, the [sz]ext vector instructions can only go up one element
7120 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
7121 // take two instructions.
7123 // This implies that the most efficient way to do the extend from v8i8
7124 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
7125 // the normal splitting to happen for the v8i16->v8i32.
7127 // This is pre-legalization to catch some cases where the default
7128 // type legalization will create ill-tempered code.
7129 if (!DCI.isBeforeLegalizeOps())
7132 // We're only interested in cleaning things up for non-legal vector types
7133 // here. If both the source and destination are legal, things will just
7134 // work naturally without any fiddling.
7135 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7136 EVT ResVT = N->getValueType(0);
7137 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7139 // If the vector type isn't a simple VT, it's beyond the scope of what
7140 // we're worried about here. Let legalization do its thing and hope for
7142 if (!ResVT.isSimple())
7145 SDValue Src = N->getOperand(0);
7146 MVT SrcVT = Src->getValueType(0).getSimpleVT();
7147 // If the source VT is a 64-bit vector, we can play games and get the
7148 // better results we want.
7149 if (SrcVT.getSizeInBits() != 64)
7152 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
7153 unsigned ElementCount = SrcVT.getVectorNumElements();
7154 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
7156 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
7158 // Now split the rest of the operation into two halves, each with a 64
7162 unsigned NumElements = ResVT.getVectorNumElements();
7163 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
7164 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
7165 ResVT.getVectorElementType(), NumElements / 2);
7167 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
7168 LoVT.getVectorNumElements());
7169 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7170 DAG.getIntPtrConstant(0));
7171 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7172 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
7173 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
7174 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
7176 // Now combine the parts back together so we still have a single result
7177 // like the combiner expects.
7178 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7181 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
7182 /// value. The load store optimizer pass will merge them to store pair stores.
7183 /// This has better performance than a splat of the scalar followed by a split
7184 /// vector store. Even if the stores are not merged it is four stores vs a dup,
7185 /// followed by an ext.b and two stores.
7186 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
7187 SDValue StVal = St->getValue();
7188 EVT VT = StVal.getValueType();
7190 // Don't replace floating point stores, they possibly won't be transformed to
7191 // stp because of the store pair suppress pass.
7192 if (VT.isFloatingPoint())
7195 // Check for insert vector elements.
7196 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
7199 // We can express a splat as store pair(s) for 2 or 4 elements.
7200 unsigned NumVecElts = VT.getVectorNumElements();
7201 if (NumVecElts != 4 && NumVecElts != 2)
7203 SDValue SplatVal = StVal.getOperand(1);
7204 unsigned RemainInsertElts = NumVecElts - 1;
7206 // Check that this is a splat.
7207 while (--RemainInsertElts) {
7208 SDValue NextInsertElt = StVal.getOperand(0);
7209 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
7211 if (NextInsertElt.getOperand(1) != SplatVal)
7213 StVal = NextInsertElt;
7215 unsigned OrigAlignment = St->getAlignment();
7216 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
7217 unsigned Alignment = std::min(OrigAlignment, EltOffset);
7219 // Create scalar stores. This is at least as good as the code sequence for a
7220 // split unaligned store wich is a dup.s, ext.b, and two stores.
7221 // Most of the time the three stores should be replaced by store pair
7222 // instructions (stp).
7224 SDValue BasePtr = St->getBasePtr();
7226 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
7227 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
7229 unsigned Offset = EltOffset;
7230 while (--NumVecElts) {
7231 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7232 DAG.getConstant(Offset, MVT::i64));
7233 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
7234 St->getPointerInfo(), St->isVolatile(),
7235 St->isNonTemporal(), Alignment);
7236 Offset += EltOffset;
7241 static SDValue performSTORECombine(SDNode *N,
7242 TargetLowering::DAGCombinerInfo &DCI,
7244 const AArch64Subtarget *Subtarget) {
7245 if (!DCI.isBeforeLegalize())
7248 StoreSDNode *S = cast<StoreSDNode>(N);
7249 if (S->isVolatile())
7252 // Cyclone has bad performance on unaligned 16B stores when crossing line and
7253 // page boundries. We want to split such stores.
7254 if (!Subtarget->isCyclone())
7257 // Don't split at Oz.
7258 MachineFunction &MF = DAG.getMachineFunction();
7259 bool IsMinSize = MF.getFunction()->getAttributes().hasAttribute(
7260 AttributeSet::FunctionIndex, Attribute::MinSize);
7264 SDValue StVal = S->getValue();
7265 EVT VT = StVal.getValueType();
7267 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
7268 // those up regresses performance on micro-benchmarks and olden/bh.
7269 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
7272 // Split unaligned 16B stores. They are terrible for performance.
7273 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
7274 // extensions can use this to mark that it does not want splitting to happen
7275 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
7276 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
7277 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
7278 S->getAlignment() <= 2)
7281 // If we get a splat of a scalar convert this vector store to a store of
7282 // scalars. They will be merged into store pairs thereby removing two
7284 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
7285 if (ReplacedSplat != SDValue())
7286 return ReplacedSplat;
7289 unsigned NumElts = VT.getVectorNumElements() / 2;
7290 // Split VT into two.
7292 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
7293 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7294 DAG.getIntPtrConstant(0));
7295 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7296 DAG.getIntPtrConstant(NumElts));
7297 SDValue BasePtr = S->getBasePtr();
7299 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
7300 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
7301 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7302 DAG.getConstant(8, MVT::i64));
7303 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
7304 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
7308 /// Target-specific DAG combine function for post-increment LD1 (lane) and
7309 /// post-increment LD1R.
7310 static SDValue performPostLD1Combine(SDNode *N,
7311 TargetLowering::DAGCombinerInfo &DCI,
7313 if (DCI.isBeforeLegalizeOps())
7316 SelectionDAG &DAG = DCI.DAG;
7317 EVT VT = N->getValueType(0);
7319 unsigned LoadIdx = IsLaneOp ? 1 : 0;
7320 SDNode *LD = N->getOperand(LoadIdx).getNode();
7321 // If it is not LOAD, can not do such combine.
7322 if (LD->getOpcode() != ISD::LOAD)
7325 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
7326 EVT MemVT = LoadSDN->getMemoryVT();
7327 // Check if memory operand is the same type as the vector element.
7328 if (MemVT != VT.getVectorElementType())
7331 // Check if there are other uses. If so, do not combine as it will introduce
7333 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
7335 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
7341 SDValue Addr = LD->getOperand(1);
7342 SDValue Vector = N->getOperand(0);
7343 // Search for a use of the address operand that is an increment.
7344 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
7345 Addr.getNode()->use_end(); UI != UE; ++UI) {
7347 if (User->getOpcode() != ISD::ADD
7348 || UI.getUse().getResNo() != Addr.getResNo())
7351 // Check that the add is independent of the load. Otherwise, folding it
7352 // would create a cycle.
7353 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
7355 // Also check that add is not used in the vector operand. This would also
7357 if (User->isPredecessorOf(Vector.getNode()))
7360 // If the increment is a constant, it must match the memory ref size.
7361 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7362 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7363 uint32_t IncVal = CInc->getZExtValue();
7364 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
7365 if (IncVal != NumBytes)
7367 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7370 SmallVector<SDValue, 8> Ops;
7371 Ops.push_back(LD->getOperand(0)); // Chain
7373 Ops.push_back(Vector); // The vector to be inserted
7374 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
7376 Ops.push_back(Addr);
7379 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
7380 SDVTList SDTys = DAG.getVTList(ArrayRef<EVT>(Tys, 3));
7381 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
7382 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
7384 LoadSDN->getMemOperand());
7387 std::vector<SDValue> NewResults;
7388 NewResults.push_back(SDValue(LD, 0)); // The result of load
7389 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
7390 DCI.CombineTo(LD, NewResults);
7391 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
7392 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
7399 /// Target-specific DAG combine function for NEON load/store intrinsics
7400 /// to merge base address updates.
7401 static SDValue performNEONPostLDSTCombine(SDNode *N,
7402 TargetLowering::DAGCombinerInfo &DCI,
7403 SelectionDAG &DAG) {
7404 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
7407 unsigned AddrOpIdx = N->getNumOperands() - 1;
7408 SDValue Addr = N->getOperand(AddrOpIdx);
7410 // Search for a use of the address operand that is an increment.
7411 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
7412 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
7414 if (User->getOpcode() != ISD::ADD ||
7415 UI.getUse().getResNo() != Addr.getResNo())
7418 // Check that the add is independent of the load/store. Otherwise, folding
7419 // it would create a cycle.
7420 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
7423 // Find the new opcode for the updating load/store.
7424 bool IsStore = false;
7425 bool IsLaneOp = false;
7426 bool IsDupOp = false;
7427 unsigned NewOpc = 0;
7428 unsigned NumVecs = 0;
7429 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7431 default: llvm_unreachable("unexpected intrinsic for Neon base update");
7432 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
7434 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
7436 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
7438 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
7439 NumVecs = 2; IsStore = true; break;
7440 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
7441 NumVecs = 3; IsStore = true; break;
7442 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
7443 NumVecs = 4; IsStore = true; break;
7444 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
7446 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
7448 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
7450 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
7451 NumVecs = 2; IsStore = true; break;
7452 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
7453 NumVecs = 3; IsStore = true; break;
7454 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
7455 NumVecs = 4; IsStore = true; break;
7456 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
7457 NumVecs = 2; IsDupOp = true; break;
7458 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
7459 NumVecs = 3; IsDupOp = true; break;
7460 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
7461 NumVecs = 4; IsDupOp = true; break;
7462 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
7463 NumVecs = 2; IsLaneOp = true; break;
7464 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
7465 NumVecs = 3; IsLaneOp = true; break;
7466 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
7467 NumVecs = 4; IsLaneOp = true; break;
7468 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
7469 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
7470 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
7471 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
7472 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
7473 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
7478 VecTy = N->getOperand(2).getValueType();
7480 VecTy = N->getValueType(0);
7482 // If the increment is a constant, it must match the memory ref size.
7483 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7484 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7485 uint32_t IncVal = CInc->getZExtValue();
7486 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
7487 if (IsLaneOp || IsDupOp)
7488 NumBytes /= VecTy.getVectorNumElements();
7489 if (IncVal != NumBytes)
7491 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7493 SmallVector<SDValue, 8> Ops;
7494 Ops.push_back(N->getOperand(0)); // Incoming chain
7495 // Load lane and store have vector list as input.
7496 if (IsLaneOp || IsStore)
7497 for (unsigned i = 2; i < AddrOpIdx; ++i)
7498 Ops.push_back(N->getOperand(i));
7499 Ops.push_back(Addr); // Base register
7504 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
7506 for (n = 0; n < NumResultVecs; ++n)
7508 Tys[n++] = MVT::i64; // Type of write back register
7509 Tys[n] = MVT::Other; // Type of the chain
7510 SDVTList SDTys = DAG.getVTList(ArrayRef<EVT>(Tys, NumResultVecs + 2));
7512 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
7513 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
7514 MemInt->getMemoryVT(),
7515 MemInt->getMemOperand());
7518 std::vector<SDValue> NewResults;
7519 for (unsigned i = 0; i < NumResultVecs; ++i) {
7520 NewResults.push_back(SDValue(UpdN.getNode(), i));
7522 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
7523 DCI.CombineTo(N, NewResults);
7524 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
7531 // Optimize compare with zero and branch.
7532 static SDValue performBRCONDCombine(SDNode *N,
7533 TargetLowering::DAGCombinerInfo &DCI,
7534 SelectionDAG &DAG) {
7535 SDValue Chain = N->getOperand(0);
7536 SDValue Dest = N->getOperand(1);
7537 SDValue CCVal = N->getOperand(2);
7538 SDValue Cmp = N->getOperand(3);
7540 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
7541 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
7542 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
7545 unsigned CmpOpc = Cmp.getOpcode();
7546 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
7549 // Only attempt folding if there is only one use of the flag and no use of the
7551 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
7554 SDValue LHS = Cmp.getOperand(0);
7555 SDValue RHS = Cmp.getOperand(1);
7557 assert(LHS.getValueType() == RHS.getValueType() &&
7558 "Expected the value type to be the same for both operands!");
7559 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
7562 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
7563 std::swap(LHS, RHS);
7565 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
7568 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
7569 LHS.getOpcode() == ISD::SRL)
7572 // Fold the compare into the branch instruction.
7574 if (CC == AArch64CC::EQ)
7575 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
7577 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
7579 // Do not add new nodes to DAG combiner worklist.
7580 DCI.CombineTo(N, BR, false);
7585 // vselect (v1i1 setcc) ->
7586 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
7587 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
7588 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
7590 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
7591 SDValue N0 = N->getOperand(0);
7592 EVT CCVT = N0.getValueType();
7594 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
7595 CCVT.getVectorElementType() != MVT::i1)
7598 EVT ResVT = N->getValueType(0);
7599 EVT CmpVT = N0.getOperand(0).getValueType();
7600 // Only combine when the result type is of the same size as the compared
7602 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
7605 SDValue IfTrue = N->getOperand(1);
7606 SDValue IfFalse = N->getOperand(2);
7608 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
7609 N0.getOperand(0), N0.getOperand(1),
7610 cast<CondCodeSDNode>(N0.getOperand(2))->get());
7611 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
7615 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
7616 /// the compare-mask instructions rather than going via NZCV, even if LHS and
7617 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
7618 /// with a vector one followed by a DUP shuffle on the result.
7619 static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
7620 SDValue N0 = N->getOperand(0);
7621 EVT ResVT = N->getValueType(0);
7623 if (!N->getOperand(1).getValueType().isVector())
7626 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
7631 EVT SrcVT = N0.getOperand(0).getValueType();
7632 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT,
7633 ResVT.getSizeInBits() / SrcVT.getSizeInBits());
7634 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
7636 // First perform a vector comparison, where lane 0 is the one we're interested
7639 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
7641 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
7642 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
7644 // Now duplicate the comparison mask we want across all other lanes.
7645 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
7646 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
7647 Mask = DAG.getNode(ISD::BITCAST, DL, ResVT.changeVectorElementTypeToInteger(),
7650 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
7653 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
7654 DAGCombinerInfo &DCI) const {
7655 SelectionDAG &DAG = DCI.DAG;
7656 switch (N->getOpcode()) {
7661 return performAddSubLongCombine(N, DCI, DAG);
7663 return performXorCombine(N, DAG, DCI, Subtarget);
7665 return performMulCombine(N, DAG, DCI, Subtarget);
7666 case ISD::SINT_TO_FP:
7667 case ISD::UINT_TO_FP:
7668 return performIntToFpCombine(N, DAG);
7670 return performORCombine(N, DCI, Subtarget);
7671 case ISD::INTRINSIC_WO_CHAIN:
7672 return performIntrinsicCombine(N, DCI, Subtarget);
7673 case ISD::ANY_EXTEND:
7674 case ISD::ZERO_EXTEND:
7675 case ISD::SIGN_EXTEND:
7676 return performExtendCombine(N, DCI, DAG);
7678 return performBitcastCombine(N, DCI, DAG);
7679 case ISD::CONCAT_VECTORS:
7680 return performConcatVectorsCombine(N, DCI, DAG);
7682 return performSelectCombine(N, DAG);
7684 return performVSelectCombine(N, DCI.DAG);
7686 return performSTORECombine(N, DCI, DAG, Subtarget);
7687 case AArch64ISD::BRCOND:
7688 return performBRCONDCombine(N, DCI, DAG);
7689 case AArch64ISD::DUP:
7690 return performPostLD1Combine(N, DCI, false);
7691 case ISD::INSERT_VECTOR_ELT:
7692 return performPostLD1Combine(N, DCI, true);
7693 case ISD::INTRINSIC_VOID:
7694 case ISD::INTRINSIC_W_CHAIN:
7695 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7696 case Intrinsic::aarch64_neon_ld2:
7697 case Intrinsic::aarch64_neon_ld3:
7698 case Intrinsic::aarch64_neon_ld4:
7699 case Intrinsic::aarch64_neon_ld1x2:
7700 case Intrinsic::aarch64_neon_ld1x3:
7701 case Intrinsic::aarch64_neon_ld1x4:
7702 case Intrinsic::aarch64_neon_ld2lane:
7703 case Intrinsic::aarch64_neon_ld3lane:
7704 case Intrinsic::aarch64_neon_ld4lane:
7705 case Intrinsic::aarch64_neon_ld2r:
7706 case Intrinsic::aarch64_neon_ld3r:
7707 case Intrinsic::aarch64_neon_ld4r:
7708 case Intrinsic::aarch64_neon_st2:
7709 case Intrinsic::aarch64_neon_st3:
7710 case Intrinsic::aarch64_neon_st4:
7711 case Intrinsic::aarch64_neon_st1x2:
7712 case Intrinsic::aarch64_neon_st1x3:
7713 case Intrinsic::aarch64_neon_st1x4:
7714 case Intrinsic::aarch64_neon_st2lane:
7715 case Intrinsic::aarch64_neon_st3lane:
7716 case Intrinsic::aarch64_neon_st4lane:
7717 return performNEONPostLDSTCombine(N, DCI, DAG);
7725 // Check if the return value is used as only a return value, as otherwise
7726 // we can't perform a tail-call. In particular, we need to check for
7727 // target ISD nodes that are returns and any other "odd" constructs
7728 // that the generic analysis code won't necessarily catch.
7729 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
7730 SDValue &Chain) const {
7731 if (N->getNumValues() != 1)
7733 if (!N->hasNUsesOfValue(1, 0))
7736 SDValue TCChain = Chain;
7737 SDNode *Copy = *N->use_begin();
7738 if (Copy->getOpcode() == ISD::CopyToReg) {
7739 // If the copy has a glue operand, we conservatively assume it isn't safe to
7740 // perform a tail call.
7741 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
7744 TCChain = Copy->getOperand(0);
7745 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
7748 bool HasRet = false;
7749 for (SDNode *Node : Copy->uses()) {
7750 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
7762 // Return whether the an instruction can potentially be optimized to a tail
7763 // call. This will cause the optimizers to attempt to move, or duplicate,
7764 // return instructions to help enable tail call optimizations for this
7766 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
7767 if (!CI->isTailCall())
7773 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
7775 ISD::MemIndexedMode &AM,
7777 SelectionDAG &DAG) const {
7778 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
7781 Base = Op->getOperand(0);
7782 // All of the indexed addressing mode instructions take a signed
7783 // 9 bit immediate offset.
7784 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
7785 int64_t RHSC = (int64_t)RHS->getZExtValue();
7786 if (RHSC >= 256 || RHSC <= -256)
7788 IsInc = (Op->getOpcode() == ISD::ADD);
7789 Offset = Op->getOperand(1);
7795 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
7797 ISD::MemIndexedMode &AM,
7798 SelectionDAG &DAG) const {
7801 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7802 VT = LD->getMemoryVT();
7803 Ptr = LD->getBasePtr();
7804 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7805 VT = ST->getMemoryVT();
7806 Ptr = ST->getBasePtr();
7811 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
7813 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
7817 bool AArch64TargetLowering::getPostIndexedAddressParts(
7818 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
7819 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
7822 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7823 VT = LD->getMemoryVT();
7824 Ptr = LD->getBasePtr();
7825 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7826 VT = ST->getMemoryVT();
7827 Ptr = ST->getBasePtr();
7832 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
7834 // Post-indexing updates the base, so it's not a valid transform
7835 // if that's not the same as the load's pointer.
7838 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
7842 void AArch64TargetLowering::ReplaceNodeResults(
7843 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
7844 switch (N->getOpcode()) {
7846 llvm_unreachable("Don't know how to custom expand this");
7847 case ISD::FP_TO_UINT:
7848 case ISD::FP_TO_SINT:
7849 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
7850 // Let normal code take care of it by not adding anything to Results.
7855 bool AArch64TargetLowering::shouldExpandAtomicInIR(Instruction *Inst) const {
7856 // Loads and stores less than 128-bits are already atomic; ones above that
7857 // are doomed anyway, so defer to the default libcall and blame the OS when
7859 if (StoreInst *SI = dyn_cast<StoreInst>(Inst))
7860 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() == 128;
7861 else if (LoadInst *LI = dyn_cast<LoadInst>(Inst))
7862 return LI->getType()->getPrimitiveSizeInBits() == 128;
7864 // For the real atomic operations, we have ldxr/stxr up to 128 bits.
7865 return Inst->getType()->getPrimitiveSizeInBits() <= 128;
7868 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
7869 AtomicOrdering Ord) const {
7870 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
7871 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
7873 Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent;
7875 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
7876 // intrinsic must return {i64, i64} and we have to recombine them into a
7877 // single i128 here.
7878 if (ValTy->getPrimitiveSizeInBits() == 128) {
7880 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
7881 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
7883 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
7884 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
7886 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
7887 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
7888 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
7889 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
7890 return Builder.CreateOr(
7891 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
7894 Type *Tys[] = { Addr->getType() };
7896 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
7897 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
7899 return Builder.CreateTruncOrBitCast(
7900 Builder.CreateCall(Ldxr, Addr),
7901 cast<PointerType>(Addr->getType())->getElementType());
7904 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
7905 Value *Val, Value *Addr,
7906 AtomicOrdering Ord) const {
7907 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
7909 Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent;
7911 // Since the intrinsics must have legal type, the i128 intrinsics take two
7912 // parameters: "i64, i64". We must marshal Val into the appropriate form
7914 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
7916 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
7917 Function *Stxr = Intrinsic::getDeclaration(M, Int);
7918 Type *Int64Ty = Type::getInt64Ty(M->getContext());
7920 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
7921 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
7922 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
7923 return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
7927 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
7928 Type *Tys[] = { Addr->getType() };
7929 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
7931 return Builder.CreateCall2(
7932 Stxr, Builder.CreateZExtOrBitCast(
7933 Val, Stxr->getFunctionType()->getParamType(0)),