1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64PerfectShuffle.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64MachineFunctionInfo.h"
18 #include "AArch64TargetMachine.h"
19 #include "AArch64TargetObjectFile.h"
20 #include "MCTargetDesc/AArch64AddressingModes.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/Intrinsics.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
36 #define DEBUG_TYPE "aarch64-lower"
38 STATISTIC(NumTailCalls, "Number of tail calls");
39 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
46 static cl::opt<AlignMode>
47 Align(cl::desc("Load/store alignment support"),
48 cl::Hidden, cl::init(NoStrictAlign),
50 clEnumValN(StrictAlign, "aarch64-strict-align",
51 "Disallow all unaligned memory accesses"),
52 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
53 "Allow unaligned memory accesses"),
56 // Place holder until extr generation is tested fully.
58 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
59 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
63 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
64 cl::desc("Allow AArch64 SLI/SRI formation"),
67 //===----------------------------------------------------------------------===//
68 // AArch64 Lowering public interface.
69 //===----------------------------------------------------------------------===//
70 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
71 if (TT.isOSBinFormatMachO())
72 return new AArch64_MachoTargetObjectFile();
74 return new AArch64_ELFTargetObjectFile();
77 AArch64TargetLowering::AArch64TargetLowering(TargetMachine &TM)
78 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
79 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
81 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
82 // we have to make something up. Arbitrarily, choose ZeroOrOne.
83 setBooleanContents(ZeroOrOneBooleanContent);
84 // When comparing vectors the result sets the different elements in the
85 // vector to all-one or all-zero.
86 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
88 // Set up the register classes.
89 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
90 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
92 if (Subtarget->hasFPARMv8()) {
93 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
94 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
95 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
96 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
99 if (Subtarget->hasNEON()) {
100 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
101 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
102 // Someone set us up the NEON.
103 addDRTypeForNEON(MVT::v2f32);
104 addDRTypeForNEON(MVT::v8i8);
105 addDRTypeForNEON(MVT::v4i16);
106 addDRTypeForNEON(MVT::v2i32);
107 addDRTypeForNEON(MVT::v1i64);
108 addDRTypeForNEON(MVT::v1f64);
110 addQRTypeForNEON(MVT::v4f32);
111 addQRTypeForNEON(MVT::v2f64);
112 addQRTypeForNEON(MVT::v16i8);
113 addQRTypeForNEON(MVT::v8i16);
114 addQRTypeForNEON(MVT::v4i32);
115 addQRTypeForNEON(MVT::v2i64);
118 // Compute derived properties from the register classes
119 computeRegisterProperties();
121 // Provide all sorts of operation actions
122 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
123 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
124 setOperationAction(ISD::SETCC, MVT::i32, Custom);
125 setOperationAction(ISD::SETCC, MVT::i64, Custom);
126 setOperationAction(ISD::SETCC, MVT::f32, Custom);
127 setOperationAction(ISD::SETCC, MVT::f64, Custom);
128 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
129 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
130 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
131 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
132 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
133 setOperationAction(ISD::SELECT, MVT::i32, Custom);
134 setOperationAction(ISD::SELECT, MVT::i64, Custom);
135 setOperationAction(ISD::SELECT, MVT::f32, Custom);
136 setOperationAction(ISD::SELECT, MVT::f64, Custom);
137 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
138 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
139 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
140 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
141 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
142 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
144 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
145 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
146 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
148 setOperationAction(ISD::FREM, MVT::f32, Expand);
149 setOperationAction(ISD::FREM, MVT::f64, Expand);
150 setOperationAction(ISD::FREM, MVT::f80, Expand);
152 // Custom lowering hooks are needed for XOR
153 // to fold it into CSINC/CSINV.
154 setOperationAction(ISD::XOR, MVT::i32, Custom);
155 setOperationAction(ISD::XOR, MVT::i64, Custom);
157 // Virtually no operation on f128 is legal, but LLVM can't expand them when
158 // there's a valid register class, so we need custom operations in most cases.
159 setOperationAction(ISD::FABS, MVT::f128, Expand);
160 setOperationAction(ISD::FADD, MVT::f128, Custom);
161 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
162 setOperationAction(ISD::FCOS, MVT::f128, Expand);
163 setOperationAction(ISD::FDIV, MVT::f128, Custom);
164 setOperationAction(ISD::FMA, MVT::f128, Expand);
165 setOperationAction(ISD::FMUL, MVT::f128, Custom);
166 setOperationAction(ISD::FNEG, MVT::f128, Expand);
167 setOperationAction(ISD::FPOW, MVT::f128, Expand);
168 setOperationAction(ISD::FREM, MVT::f128, Expand);
169 setOperationAction(ISD::FRINT, MVT::f128, Expand);
170 setOperationAction(ISD::FSIN, MVT::f128, Expand);
171 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
172 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
173 setOperationAction(ISD::FSUB, MVT::f128, Custom);
174 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
175 setOperationAction(ISD::SETCC, MVT::f128, Custom);
176 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
177 setOperationAction(ISD::SELECT, MVT::f128, Custom);
178 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
179 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
181 // Lowering for many of the conversions is actually specified by the non-f128
182 // type. The LowerXXX function will be trivial when f128 isn't involved.
183 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
184 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
185 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
186 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
187 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
188 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
189 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
190 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
191 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
192 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
193 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
194 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
195 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
196 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
198 // Variable arguments.
199 setOperationAction(ISD::VASTART, MVT::Other, Custom);
200 setOperationAction(ISD::VAARG, MVT::Other, Custom);
201 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
202 setOperationAction(ISD::VAEND, MVT::Other, Expand);
204 // Variable-sized objects.
205 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
206 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
209 // Exception handling.
210 // FIXME: These are guesses. Has this been defined yet?
211 setExceptionPointerRegister(AArch64::X0);
212 setExceptionSelectorRegister(AArch64::X1);
214 // Constant pool entries
215 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
218 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
220 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
221 setOperationAction(ISD::ADDC, MVT::i32, Custom);
222 setOperationAction(ISD::ADDE, MVT::i32, Custom);
223 setOperationAction(ISD::SUBC, MVT::i32, Custom);
224 setOperationAction(ISD::SUBE, MVT::i32, Custom);
225 setOperationAction(ISD::ADDC, MVT::i64, Custom);
226 setOperationAction(ISD::ADDE, MVT::i64, Custom);
227 setOperationAction(ISD::SUBC, MVT::i64, Custom);
228 setOperationAction(ISD::SUBE, MVT::i64, Custom);
230 // AArch64 lacks both left-rotate and popcount instructions.
231 setOperationAction(ISD::ROTL, MVT::i32, Expand);
232 setOperationAction(ISD::ROTL, MVT::i64, Expand);
234 // AArch64 doesn't have {U|S}MUL_LOHI.
235 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
236 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
239 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
240 // counterparts, which AArch64 supports directly.
241 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
242 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
243 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
244 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
246 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
247 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
249 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
250 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
251 setOperationAction(ISD::SREM, MVT::i32, Expand);
252 setOperationAction(ISD::SREM, MVT::i64, Expand);
253 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
254 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
255 setOperationAction(ISD::UREM, MVT::i32, Expand);
256 setOperationAction(ISD::UREM, MVT::i64, Expand);
258 // Custom lower Add/Sub/Mul with overflow.
259 setOperationAction(ISD::SADDO, MVT::i32, Custom);
260 setOperationAction(ISD::SADDO, MVT::i64, Custom);
261 setOperationAction(ISD::UADDO, MVT::i32, Custom);
262 setOperationAction(ISD::UADDO, MVT::i64, Custom);
263 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
264 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
265 setOperationAction(ISD::USUBO, MVT::i32, Custom);
266 setOperationAction(ISD::USUBO, MVT::i64, Custom);
267 setOperationAction(ISD::SMULO, MVT::i32, Custom);
268 setOperationAction(ISD::SMULO, MVT::i64, Custom);
269 setOperationAction(ISD::UMULO, MVT::i32, Custom);
270 setOperationAction(ISD::UMULO, MVT::i64, Custom);
272 setOperationAction(ISD::FSIN, MVT::f32, Expand);
273 setOperationAction(ISD::FSIN, MVT::f64, Expand);
274 setOperationAction(ISD::FCOS, MVT::f32, Expand);
275 setOperationAction(ISD::FCOS, MVT::f64, Expand);
276 setOperationAction(ISD::FPOW, MVT::f32, Expand);
277 setOperationAction(ISD::FPOW, MVT::f64, Expand);
278 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
279 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
281 // AArch64 has implementations of a lot of rounding-like FP operations.
282 static MVT RoundingTypes[] = { MVT::f32, MVT::f64};
283 for (unsigned I = 0; I < array_lengthof(RoundingTypes); ++I) {
284 MVT Ty = RoundingTypes[I];
285 setOperationAction(ISD::FFLOOR, Ty, Legal);
286 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
287 setOperationAction(ISD::FCEIL, Ty, Legal);
288 setOperationAction(ISD::FRINT, Ty, Legal);
289 setOperationAction(ISD::FTRUNC, Ty, Legal);
290 setOperationAction(ISD::FROUND, Ty, Legal);
293 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
295 if (Subtarget->isTargetMachO()) {
296 // For iOS, we don't want to the normal expansion of a libcall to
297 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
299 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
300 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
302 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
303 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
306 // AArch64 does not have floating-point extending loads, i1 sign-extending
307 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
308 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
309 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
310 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
311 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
312 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
313 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
314 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
315 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
316 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
317 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
318 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
319 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
320 // Indexed loads and stores are supported.
321 for (unsigned im = (unsigned)ISD::PRE_INC;
322 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
323 setIndexedLoadAction(im, MVT::i8, Legal);
324 setIndexedLoadAction(im, MVT::i16, Legal);
325 setIndexedLoadAction(im, MVT::i32, Legal);
326 setIndexedLoadAction(im, MVT::i64, Legal);
327 setIndexedLoadAction(im, MVT::f64, Legal);
328 setIndexedLoadAction(im, MVT::f32, Legal);
329 setIndexedStoreAction(im, MVT::i8, Legal);
330 setIndexedStoreAction(im, MVT::i16, Legal);
331 setIndexedStoreAction(im, MVT::i32, Legal);
332 setIndexedStoreAction(im, MVT::i64, Legal);
333 setIndexedStoreAction(im, MVT::f64, Legal);
334 setIndexedStoreAction(im, MVT::f32, Legal);
338 setOperationAction(ISD::TRAP, MVT::Other, Legal);
340 // We combine OR nodes for bitfield operations.
341 setTargetDAGCombine(ISD::OR);
343 // Vector add and sub nodes may conceal a high-half opportunity.
344 // Also, try to fold ADD into CSINC/CSINV..
345 setTargetDAGCombine(ISD::ADD);
346 setTargetDAGCombine(ISD::SUB);
348 setTargetDAGCombine(ISD::XOR);
349 setTargetDAGCombine(ISD::SINT_TO_FP);
350 setTargetDAGCombine(ISD::UINT_TO_FP);
352 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
354 setTargetDAGCombine(ISD::ANY_EXTEND);
355 setTargetDAGCombine(ISD::ZERO_EXTEND);
356 setTargetDAGCombine(ISD::SIGN_EXTEND);
357 setTargetDAGCombine(ISD::BITCAST);
358 setTargetDAGCombine(ISD::CONCAT_VECTORS);
359 setTargetDAGCombine(ISD::STORE);
361 setTargetDAGCombine(ISD::MUL);
363 setTargetDAGCombine(ISD::SELECT);
364 setTargetDAGCombine(ISD::VSELECT);
366 setTargetDAGCombine(ISD::INTRINSIC_VOID);
367 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
368 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
370 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
371 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
372 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
374 setStackPointerRegisterToSaveRestore(AArch64::SP);
376 setSchedulingPreference(Sched::Hybrid);
379 MaskAndBranchFoldingIsLegal = true;
381 setMinFunctionAlignment(2);
383 RequireStrictAlign = (Align == StrictAlign);
385 setHasExtractBitsInsn(true);
387 if (Subtarget->hasNEON()) {
388 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
389 // silliness like this:
390 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
391 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
392 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
393 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
394 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
395 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
396 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
397 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
398 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
399 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
400 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
401 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
402 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
403 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
404 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
405 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
406 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
407 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
408 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
409 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
410 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
411 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
412 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
413 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
414 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
416 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
417 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
418 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
419 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
420 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
422 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
424 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
425 // elements smaller than i32, so promote the input to i32 first.
426 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
427 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
428 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
429 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
430 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
431 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
432 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
433 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
434 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
436 // AArch64 doesn't have MUL.2d:
437 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
438 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
439 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
440 // Likewise, narrowing and extending vector loads/stores aren't handled
442 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
443 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
445 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
448 setOperationAction(ISD::MULHS, (MVT::SimpleValueType)VT, Expand);
449 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
450 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand);
451 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
453 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
455 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
456 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
457 setTruncStoreAction((MVT::SimpleValueType)VT,
458 (MVT::SimpleValueType)InnerVT, Expand);
459 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
460 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
461 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
464 // AArch64 has implementations of a lot of rounding-like FP operations.
465 static MVT RoundingVecTypes[] = {MVT::v2f32, MVT::v4f32, MVT::v2f64 };
466 for (unsigned I = 0; I < array_lengthof(RoundingVecTypes); ++I) {
467 MVT Ty = RoundingVecTypes[I];
468 setOperationAction(ISD::FFLOOR, Ty, Legal);
469 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
470 setOperationAction(ISD::FCEIL, Ty, Legal);
471 setOperationAction(ISD::FRINT, Ty, Legal);
472 setOperationAction(ISD::FTRUNC, Ty, Legal);
473 setOperationAction(ISD::FROUND, Ty, Legal);
478 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
479 if (VT == MVT::v2f32) {
480 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
481 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
483 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
484 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
485 } else if (VT == MVT::v2f64 || VT == MVT::v4f32) {
486 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
487 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
489 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
490 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
493 // Mark vector float intrinsics as expand.
494 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
495 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
496 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
497 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
498 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
499 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
500 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
501 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
502 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
503 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
506 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
507 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
508 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
509 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
510 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
511 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
512 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
513 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
514 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
515 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
516 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
517 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
519 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
520 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
521 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
522 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
524 // CNT supports only B element sizes.
525 if (VT != MVT::v8i8 && VT != MVT::v16i8)
526 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
528 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
529 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
530 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
531 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
532 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
534 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
535 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
537 if (Subtarget->isLittleEndian()) {
538 for (unsigned im = (unsigned)ISD::PRE_INC;
539 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
540 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
541 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
546 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
547 addRegisterClass(VT, &AArch64::FPR64RegClass);
548 addTypeForNEON(VT, MVT::v2i32);
551 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
552 addRegisterClass(VT, &AArch64::FPR128RegClass);
553 addTypeForNEON(VT, MVT::v4i32);
556 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
559 return VT.changeVectorElementTypeToInteger();
562 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
563 /// Mask are known to be either zero or one and return them in the
564 /// KnownZero/KnownOne bitsets.
565 void AArch64TargetLowering::computeKnownBitsForTargetNode(
566 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
567 const SelectionDAG &DAG, unsigned Depth) const {
568 switch (Op.getOpcode()) {
571 case AArch64ISD::CSEL: {
572 APInt KnownZero2, KnownOne2;
573 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
574 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
575 KnownZero &= KnownZero2;
576 KnownOne &= KnownOne2;
579 case ISD::INTRINSIC_W_CHAIN: {
580 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
581 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
584 case Intrinsic::aarch64_ldaxr:
585 case Intrinsic::aarch64_ldxr: {
586 unsigned BitWidth = KnownOne.getBitWidth();
587 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
588 unsigned MemBits = VT.getScalarType().getSizeInBits();
589 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
595 case ISD::INTRINSIC_WO_CHAIN:
596 case ISD::INTRINSIC_VOID: {
597 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
601 case Intrinsic::aarch64_neon_umaxv:
602 case Intrinsic::aarch64_neon_uminv: {
603 // Figure out the datatype of the vector operand. The UMINV instruction
604 // will zero extend the result, so we can mark as known zero all the
605 // bits larger than the element datatype. 32-bit or larget doesn't need
606 // this as those are legal types and will be handled by isel directly.
607 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
608 unsigned BitWidth = KnownZero.getBitWidth();
609 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
610 assert(BitWidth >= 8 && "Unexpected width!");
611 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
613 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
614 assert(BitWidth >= 16 && "Unexpected width!");
615 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
625 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
629 unsigned AArch64TargetLowering::getMaximalGlobalOffset() const {
630 // FIXME: On AArch64, this depends on the type.
631 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
632 // and the offset has to be a multiple of the related size in bytes.
637 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
638 const TargetLibraryInfo *libInfo) const {
639 return AArch64::createFastISel(funcInfo, libInfo);
642 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
646 case AArch64ISD::CALL: return "AArch64ISD::CALL";
647 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
648 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
649 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
650 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
651 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
652 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
653 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
654 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
655 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
656 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
657 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
658 case AArch64ISD::TLSDESC_CALL: return "AArch64ISD::TLSDESC_CALL";
659 case AArch64ISD::ADC: return "AArch64ISD::ADC";
660 case AArch64ISD::SBC: return "AArch64ISD::SBC";
661 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
662 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
663 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
664 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
665 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
666 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
667 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
668 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
669 case AArch64ISD::DUP: return "AArch64ISD::DUP";
670 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
671 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
672 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
673 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
674 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
675 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
676 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
677 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
678 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
679 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
680 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
681 case AArch64ISD::BICi: return "AArch64ISD::BICi";
682 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
683 case AArch64ISD::BSL: return "AArch64ISD::BSL";
684 case AArch64ISD::NEG: return "AArch64ISD::NEG";
685 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
686 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
687 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
688 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
689 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
690 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
691 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
692 case AArch64ISD::REV16: return "AArch64ISD::REV16";
693 case AArch64ISD::REV32: return "AArch64ISD::REV32";
694 case AArch64ISD::REV64: return "AArch64ISD::REV64";
695 case AArch64ISD::EXT: return "AArch64ISD::EXT";
696 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
697 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
698 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
699 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
700 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
701 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
702 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
703 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
704 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
705 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
706 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
707 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
708 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
709 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
710 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
711 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
712 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
713 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
714 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
715 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
716 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
717 case AArch64ISD::NOT: return "AArch64ISD::NOT";
718 case AArch64ISD::BIT: return "AArch64ISD::BIT";
719 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
720 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
721 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
722 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
723 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
724 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
725 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
726 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
727 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
728 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
729 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
730 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
731 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
732 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
733 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
734 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
735 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
736 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
737 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
738 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
739 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
740 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
741 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
742 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
743 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
744 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
745 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
746 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
747 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
748 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
749 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
750 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
751 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
752 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
753 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
754 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
759 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
760 MachineBasicBlock *MBB) const {
761 // We materialise the F128CSEL pseudo-instruction as some control flow and a
765 // [... previous instrs leading to comparison ...]
771 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
773 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
774 MachineFunction *MF = MBB->getParent();
775 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
776 DebugLoc DL = MI->getDebugLoc();
777 MachineFunction::iterator It = MBB;
780 unsigned DestReg = MI->getOperand(0).getReg();
781 unsigned IfTrueReg = MI->getOperand(1).getReg();
782 unsigned IfFalseReg = MI->getOperand(2).getReg();
783 unsigned CondCode = MI->getOperand(3).getImm();
784 bool NZCVKilled = MI->getOperand(4).isKill();
786 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
787 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
788 MF->insert(It, TrueBB);
789 MF->insert(It, EndBB);
791 // Transfer rest of current basic-block to EndBB
792 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
794 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
796 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
797 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
798 MBB->addSuccessor(TrueBB);
799 MBB->addSuccessor(EndBB);
801 // TrueBB falls through to the end.
802 TrueBB->addSuccessor(EndBB);
805 TrueBB->addLiveIn(AArch64::NZCV);
806 EndBB->addLiveIn(AArch64::NZCV);
809 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
815 MI->eraseFromParent();
820 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
821 MachineBasicBlock *BB) const {
822 switch (MI->getOpcode()) {
827 llvm_unreachable("Unexpected instruction for custom inserter!");
829 case AArch64::F128CSEL:
830 return EmitF128CSEL(MI, BB);
832 case TargetOpcode::STACKMAP:
833 case TargetOpcode::PATCHPOINT:
834 return emitPatchPoint(MI, BB);
838 //===----------------------------------------------------------------------===//
839 // AArch64 Lowering private implementation.
840 //===----------------------------------------------------------------------===//
842 //===----------------------------------------------------------------------===//
844 //===----------------------------------------------------------------------===//
846 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
848 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
851 llvm_unreachable("Unknown condition code!");
853 return AArch64CC::NE;
855 return AArch64CC::EQ;
857 return AArch64CC::GT;
859 return AArch64CC::GE;
861 return AArch64CC::LT;
863 return AArch64CC::LE;
865 return AArch64CC::HI;
867 return AArch64CC::HS;
869 return AArch64CC::LO;
871 return AArch64CC::LS;
875 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
876 static void changeFPCCToAArch64CC(ISD::CondCode CC,
877 AArch64CC::CondCode &CondCode,
878 AArch64CC::CondCode &CondCode2) {
879 CondCode2 = AArch64CC::AL;
882 llvm_unreachable("Unknown FP condition!");
885 CondCode = AArch64CC::EQ;
889 CondCode = AArch64CC::GT;
893 CondCode = AArch64CC::GE;
896 CondCode = AArch64CC::MI;
899 CondCode = AArch64CC::LS;
902 CondCode = AArch64CC::MI;
903 CondCode2 = AArch64CC::GT;
906 CondCode = AArch64CC::VC;
909 CondCode = AArch64CC::VS;
912 CondCode = AArch64CC::EQ;
913 CondCode2 = AArch64CC::VS;
916 CondCode = AArch64CC::HI;
919 CondCode = AArch64CC::PL;
923 CondCode = AArch64CC::LT;
927 CondCode = AArch64CC::LE;
931 CondCode = AArch64CC::NE;
936 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
937 /// CC usable with the vector instructions. Fewer operations are available
938 /// without a real NZCV register, so we have to use less efficient combinations
939 /// to get the same effect.
940 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
941 AArch64CC::CondCode &CondCode,
942 AArch64CC::CondCode &CondCode2,
947 // Mostly the scalar mappings work fine.
948 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
951 Invert = true; // Fallthrough
953 CondCode = AArch64CC::MI;
954 CondCode2 = AArch64CC::GE;
961 // All of the compare-mask comparisons are ordered, but we can switch
962 // between the two by a double inversion. E.g. ULE == !OGT.
964 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
969 static bool isLegalArithImmed(uint64_t C) {
970 // Matches AArch64DAGToDAGISel::SelectArithImmed().
971 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
974 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
975 SDLoc dl, SelectionDAG &DAG) {
976 EVT VT = LHS.getValueType();
978 if (VT.isFloatingPoint())
979 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
981 // The CMP instruction is just an alias for SUBS, and representing it as
982 // SUBS means that it's possible to get CSE with subtract operations.
983 // A later phase can perform the optimization of setting the destination
984 // register to WZR/XZR if it ends up being unused.
985 unsigned Opcode = AArch64ISD::SUBS;
987 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
988 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
989 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
990 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
991 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
992 // can be set differently by this operation. It comes down to whether
993 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
994 // everything is fine. If not then the optimization is wrong. Thus general
995 // comparisons are only valid if op2 != 0.
997 // So, finally, the only LLVM-native comparisons that don't mention C and V
998 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
999 // the absence of information about op2.
1000 Opcode = AArch64ISD::ADDS;
1001 RHS = RHS.getOperand(1);
1002 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1003 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1004 !isUnsignedIntSetCC(CC)) {
1005 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1006 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1007 // of the signed comparisons.
1008 Opcode = AArch64ISD::ANDS;
1009 RHS = LHS.getOperand(1);
1010 LHS = LHS.getOperand(0);
1013 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1017 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1018 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1019 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1020 EVT VT = RHS.getValueType();
1021 uint64_t C = RHSC->getZExtValue();
1022 if (!isLegalArithImmed(C)) {
1023 // Constant does not fit, try adjusting it by one?
1029 if ((VT == MVT::i32 && C != 0x80000000 &&
1030 isLegalArithImmed((uint32_t)(C - 1))) ||
1031 (VT == MVT::i64 && C != 0x80000000ULL &&
1032 isLegalArithImmed(C - 1ULL))) {
1033 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1034 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1035 RHS = DAG.getConstant(C, VT);
1040 if ((VT == MVT::i32 && C != 0 &&
1041 isLegalArithImmed((uint32_t)(C - 1))) ||
1042 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1043 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1044 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1045 RHS = DAG.getConstant(C, VT);
1050 if ((VT == MVT::i32 && C != 0x7fffffff &&
1051 isLegalArithImmed((uint32_t)(C + 1))) ||
1052 (VT == MVT::i64 && C != 0x7ffffffffffffffULL &&
1053 isLegalArithImmed(C + 1ULL))) {
1054 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1055 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1056 RHS = DAG.getConstant(C, VT);
1061 if ((VT == MVT::i32 && C != 0xffffffff &&
1062 isLegalArithImmed((uint32_t)(C + 1))) ||
1063 (VT == MVT::i64 && C != 0xfffffffffffffffULL &&
1064 isLegalArithImmed(C + 1ULL))) {
1065 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1066 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1067 RHS = DAG.getConstant(C, VT);
1074 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1075 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
1076 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1080 static std::pair<SDValue, SDValue>
1081 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1082 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1083 "Unsupported value type");
1084 SDValue Value, Overflow;
1086 SDValue LHS = Op.getOperand(0);
1087 SDValue RHS = Op.getOperand(1);
1089 switch (Op.getOpcode()) {
1091 llvm_unreachable("Unknown overflow instruction!");
1093 Opc = AArch64ISD::ADDS;
1097 Opc = AArch64ISD::ADDS;
1101 Opc = AArch64ISD::SUBS;
1105 Opc = AArch64ISD::SUBS;
1108 // Multiply needs a little bit extra work.
1112 bool IsSigned = (Op.getOpcode() == ISD::SMULO) ? true : false;
1113 if (Op.getValueType() == MVT::i32) {
1114 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1115 // For a 32 bit multiply with overflow check we want the instruction
1116 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1117 // need to generate the following pattern:
1118 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1119 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1120 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1121 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1122 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1123 DAG.getConstant(0, MVT::i64));
1124 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1125 // operation. We need to clear out the upper 32 bits, because we used a
1126 // widening multiply that wrote all 64 bits. In the end this should be a
1128 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1130 // The signed overflow check requires more than just a simple check for
1131 // any bit set in the upper 32 bits of the result. These bits could be
1132 // just the sign bits of a negative number. To perform the overflow
1133 // check we have to arithmetic shift right the 32nd bit of the result by
1134 // 31 bits. Then we compare the result to the upper 32 bits.
1135 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1136 DAG.getConstant(32, MVT::i64));
1137 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1138 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1139 DAG.getConstant(31, MVT::i64));
1140 // It is important that LowerBits is last, otherwise the arithmetic
1141 // shift will not be folded into the compare (SUBS).
1142 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1143 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1146 // The overflow check for unsigned multiply is easy. We only need to
1147 // check if any of the upper 32 bits are set. This can be done with a
1148 // CMP (shifted register). For that we need to generate the following
1150 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1151 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1152 DAG.getConstant(32, MVT::i64));
1153 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1155 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1156 UpperBits).getValue(1);
1160 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1161 // For the 64 bit multiply
1162 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1164 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1165 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1166 DAG.getConstant(63, MVT::i64));
1167 // It is important that LowerBits is last, otherwise the arithmetic
1168 // shift will not be folded into the compare (SUBS).
1169 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1170 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1173 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1174 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1176 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1177 UpperBits).getValue(1);
1184 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1186 // Emit the AArch64 operation with overflow check.
1187 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1188 Overflow = Value.getValue(1);
1190 return std::make_pair(Value, Overflow);
1193 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1194 RTLIB::Libcall Call) const {
1195 SmallVector<SDValue, 2> Ops;
1196 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1197 Ops.push_back(Op.getOperand(i));
1199 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1203 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1204 SDValue Sel = Op.getOperand(0);
1205 SDValue Other = Op.getOperand(1);
1207 // If neither operand is a SELECT_CC, give up.
1208 if (Sel.getOpcode() != ISD::SELECT_CC)
1209 std::swap(Sel, Other);
1210 if (Sel.getOpcode() != ISD::SELECT_CC)
1213 // The folding we want to perform is:
1214 // (xor x, (select_cc a, b, cc, 0, -1) )
1216 // (csel x, (xor x, -1), cc ...)
1218 // The latter will get matched to a CSINV instruction.
1220 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1221 SDValue LHS = Sel.getOperand(0);
1222 SDValue RHS = Sel.getOperand(1);
1223 SDValue TVal = Sel.getOperand(2);
1224 SDValue FVal = Sel.getOperand(3);
1227 // FIXME: This could be generalized to non-integer comparisons.
1228 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1231 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1232 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1234 // The the values aren't constants, this isn't the pattern we're looking for.
1235 if (!CFVal || !CTVal)
1238 // We can commute the SELECT_CC by inverting the condition. This
1239 // might be needed to make this fit into a CSINV pattern.
1240 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1241 std::swap(TVal, FVal);
1242 std::swap(CTVal, CFVal);
1243 CC = ISD::getSetCCInverse(CC, true);
1246 // If the constants line up, perform the transform!
1247 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1249 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1252 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1253 DAG.getConstant(-1ULL, Other.getValueType()));
1255 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1262 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1263 EVT VT = Op.getValueType();
1265 // Let legalize expand this if it isn't a legal type yet.
1266 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1269 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1272 bool ExtraOp = false;
1273 switch (Op.getOpcode()) {
1275 llvm_unreachable("Invalid code");
1277 Opc = AArch64ISD::ADDS;
1280 Opc = AArch64ISD::SUBS;
1283 Opc = AArch64ISD::ADCS;
1287 Opc = AArch64ISD::SBCS;
1293 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1294 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1298 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1299 // Let legalize expand this if it isn't a legal type yet.
1300 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1303 AArch64CC::CondCode CC;
1304 // The actual operation that sets the overflow or carry flag.
1305 SDValue Value, Overflow;
1306 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1308 // We use 0 and 1 as false and true values.
1309 SDValue TVal = DAG.getConstant(1, MVT::i32);
1310 SDValue FVal = DAG.getConstant(0, MVT::i32);
1312 // We use an inverted condition, because the conditional select is inverted
1313 // too. This will allow it to be selected to a single instruction:
1314 // CSINC Wd, WZR, WZR, invert(cond).
1315 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32);
1316 Overflow = DAG.getNode(AArch64ISD::CSEL, SDLoc(Op), MVT::i32, FVal, TVal,
1319 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1320 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
1323 // Prefetch operands are:
1324 // 1: Address to prefetch
1326 // 3: int locality (0 = no locality ... 3 = extreme locality)
1327 // 4: bool isDataCache
1328 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1330 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1331 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1332 // The data thing is not used.
1333 // unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1335 bool IsStream = !Locality;
1336 // When the locality number is set
1338 // The front-end should have filtered out the out-of-range values
1339 assert(Locality <= 3 && "Prefetch locality out-of-range");
1340 // The locality degree is the opposite of the cache speed.
1341 // Put the number the other way around.
1342 // The encoding starts at 0 for level 1
1343 Locality = 3 - Locality;
1346 // built the mask value encoding the expected behavior.
1347 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1348 (Locality << 1) | // Cache level bits
1349 (unsigned)IsStream; // Stream bit
1350 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1351 DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1));
1354 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1355 SelectionDAG &DAG) const {
1356 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1359 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1361 return LowerF128Call(Op, DAG, LC);
1364 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1365 SelectionDAG &DAG) const {
1366 if (Op.getOperand(0).getValueType() != MVT::f128) {
1367 // It's legal except when f128 is involved
1372 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1374 // FP_ROUND node has a second operand indicating whether it is known to be
1375 // precise. That doesn't take part in the LibCall so we can't directly use
1377 SDValue SrcVal = Op.getOperand(0);
1378 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1379 /*isSigned*/ false, SDLoc(Op)).first;
1382 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1383 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1384 // Any additional optimization in this function should be recorded
1385 // in the cost tables.
1386 EVT InVT = Op.getOperand(0).getValueType();
1387 EVT VT = Op.getValueType();
1389 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1392 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1394 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1397 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1399 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v2f64, Op.getOperand(0));
1400 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1403 // Type changing conversions are illegal.
1407 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1408 SelectionDAG &DAG) const {
1409 if (Op.getOperand(0).getValueType().isVector())
1410 return LowerVectorFP_TO_INT(Op, DAG);
1412 if (Op.getOperand(0).getValueType() != MVT::f128) {
1413 // It's legal except when f128 is involved
1418 if (Op.getOpcode() == ISD::FP_TO_SINT)
1419 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1421 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1423 SmallVector<SDValue, 2> Ops;
1424 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1425 Ops.push_back(Op.getOperand(i));
1427 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1431 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1432 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1433 // Any additional optimization in this function should be recorded
1434 // in the cost tables.
1435 EVT VT = Op.getValueType();
1437 SDValue In = Op.getOperand(0);
1438 EVT InVT = In.getValueType();
1440 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1442 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1443 InVT.getVectorNumElements());
1444 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1445 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0));
1448 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1450 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1451 EVT CastVT = VT.changeVectorElementTypeToInteger();
1452 In = DAG.getNode(CastOpc, dl, CastVT, In);
1453 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1459 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1460 SelectionDAG &DAG) const {
1461 if (Op.getValueType().isVector())
1462 return LowerVectorINT_TO_FP(Op, DAG);
1464 // i128 conversions are libcalls.
1465 if (Op.getOperand(0).getValueType() == MVT::i128)
1468 // Other conversions are legal, unless it's to the completely software-based
1470 if (Op.getValueType() != MVT::f128)
1474 if (Op.getOpcode() == ISD::SINT_TO_FP)
1475 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1477 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1479 return LowerF128Call(Op, DAG, LC);
1482 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1483 SelectionDAG &DAG) const {
1484 // For iOS, we want to call an alternative entry point: __sincos_stret,
1485 // which returns the values in two S / D registers.
1487 SDValue Arg = Op.getOperand(0);
1488 EVT ArgVT = Arg.getValueType();
1489 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1496 Entry.isSExt = false;
1497 Entry.isZExt = false;
1498 Args.push_back(Entry);
1500 const char *LibcallName =
1501 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1502 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1504 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
1505 TargetLowering::CallLoweringInfo CLI(DAG);
1506 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1507 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1509 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1510 return CallResult.first;
1513 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1514 SelectionDAG &DAG) const {
1515 switch (Op.getOpcode()) {
1517 llvm_unreachable("unimplemented operand");
1519 case ISD::GlobalAddress:
1520 return LowerGlobalAddress(Op, DAG);
1521 case ISD::GlobalTLSAddress:
1522 return LowerGlobalTLSAddress(Op, DAG);
1524 return LowerSETCC(Op, DAG);
1526 return LowerBR_CC(Op, DAG);
1528 return LowerSELECT(Op, DAG);
1529 case ISD::SELECT_CC:
1530 return LowerSELECT_CC(Op, DAG);
1531 case ISD::JumpTable:
1532 return LowerJumpTable(Op, DAG);
1533 case ISD::ConstantPool:
1534 return LowerConstantPool(Op, DAG);
1535 case ISD::BlockAddress:
1536 return LowerBlockAddress(Op, DAG);
1538 return LowerVASTART(Op, DAG);
1540 return LowerVACOPY(Op, DAG);
1542 return LowerVAARG(Op, DAG);
1547 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1554 return LowerXALUO(Op, DAG);
1556 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1558 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1560 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1562 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1564 return LowerFP_ROUND(Op, DAG);
1565 case ISD::FP_EXTEND:
1566 return LowerFP_EXTEND(Op, DAG);
1567 case ISD::FRAMEADDR:
1568 return LowerFRAMEADDR(Op, DAG);
1569 case ISD::RETURNADDR:
1570 return LowerRETURNADDR(Op, DAG);
1571 case ISD::INSERT_VECTOR_ELT:
1572 return LowerINSERT_VECTOR_ELT(Op, DAG);
1573 case ISD::EXTRACT_VECTOR_ELT:
1574 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1575 case ISD::BUILD_VECTOR:
1576 return LowerBUILD_VECTOR(Op, DAG);
1577 case ISD::VECTOR_SHUFFLE:
1578 return LowerVECTOR_SHUFFLE(Op, DAG);
1579 case ISD::EXTRACT_SUBVECTOR:
1580 return LowerEXTRACT_SUBVECTOR(Op, DAG);
1584 return LowerVectorSRA_SRL_SHL(Op, DAG);
1585 case ISD::SHL_PARTS:
1586 return LowerShiftLeftParts(Op, DAG);
1587 case ISD::SRL_PARTS:
1588 case ISD::SRA_PARTS:
1589 return LowerShiftRightParts(Op, DAG);
1591 return LowerCTPOP(Op, DAG);
1592 case ISD::FCOPYSIGN:
1593 return LowerFCOPYSIGN(Op, DAG);
1595 return LowerVectorAND(Op, DAG);
1597 return LowerVectorOR(Op, DAG);
1599 return LowerXOR(Op, DAG);
1601 return LowerPREFETCH(Op, DAG);
1602 case ISD::SINT_TO_FP:
1603 case ISD::UINT_TO_FP:
1604 return LowerINT_TO_FP(Op, DAG);
1605 case ISD::FP_TO_SINT:
1606 case ISD::FP_TO_UINT:
1607 return LowerFP_TO_INT(Op, DAG);
1609 return LowerFSINCOS(Op, DAG);
1613 /// getFunctionAlignment - Return the Log2 alignment of this function.
1614 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
1618 //===----------------------------------------------------------------------===//
1619 // Calling Convention Implementation
1620 //===----------------------------------------------------------------------===//
1622 #include "AArch64GenCallingConv.inc"
1624 /// Selects the correct CCAssignFn for a the given CallingConvention
1626 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1627 bool IsVarArg) const {
1630 llvm_unreachable("Unsupported calling convention.");
1631 case CallingConv::WebKit_JS:
1632 return CC_AArch64_WebKit_JS;
1633 case CallingConv::C:
1634 case CallingConv::Fast:
1635 if (!Subtarget->isTargetDarwin())
1636 return CC_AArch64_AAPCS;
1637 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
1641 SDValue AArch64TargetLowering::LowerFormalArguments(
1642 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1643 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1644 SmallVectorImpl<SDValue> &InVals) const {
1645 MachineFunction &MF = DAG.getMachineFunction();
1646 MachineFrameInfo *MFI = MF.getFrameInfo();
1648 // Assign locations to all of the incoming arguments.
1649 SmallVector<CCValAssign, 16> ArgLocs;
1650 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1651 getTargetMachine(), ArgLocs, *DAG.getContext());
1653 // At this point, Ins[].VT may already be promoted to i32. To correctly
1654 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
1655 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
1656 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
1657 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
1659 unsigned NumArgs = Ins.size();
1660 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
1661 unsigned CurArgIdx = 0;
1662 for (unsigned i = 0; i != NumArgs; ++i) {
1663 MVT ValVT = Ins[i].VT;
1664 std::advance(CurOrigArg, Ins[i].OrigArgIndex - CurArgIdx);
1665 CurArgIdx = Ins[i].OrigArgIndex;
1667 // Get type of the original argument.
1668 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
1669 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
1670 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
1671 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
1673 else if (ActualMVT == MVT::i16)
1676 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
1678 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
1679 assert(!Res && "Call operand has unhandled type");
1682 assert(ArgLocs.size() == Ins.size());
1683 SmallVector<SDValue, 16> ArgValues;
1684 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1685 CCValAssign &VA = ArgLocs[i];
1687 if (Ins[i].Flags.isByVal()) {
1688 // Byval is used for HFAs in the PCS, but the system should work in a
1689 // non-compliant manner for larger structs.
1690 EVT PtrTy = getPointerTy();
1691 int Size = Ins[i].Flags.getByValSize();
1692 unsigned NumRegs = (Size + 7) / 8;
1694 // FIXME: This works on big-endian for composite byvals, which are the common
1695 // case. It should also work for fundamental types too.
1697 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
1698 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
1699 InVals.push_back(FrameIdxN);
1704 if (VA.isRegLoc()) {
1705 // Arguments stored in registers.
1706 EVT RegVT = VA.getLocVT();
1709 const TargetRegisterClass *RC;
1711 if (RegVT == MVT::i32)
1712 RC = &AArch64::GPR32RegClass;
1713 else if (RegVT == MVT::i64)
1714 RC = &AArch64::GPR64RegClass;
1715 else if (RegVT == MVT::f16)
1716 RC = &AArch64::FPR16RegClass;
1717 else if (RegVT == MVT::f32)
1718 RC = &AArch64::FPR32RegClass;
1719 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
1720 RC = &AArch64::FPR64RegClass;
1721 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
1722 RC = &AArch64::FPR128RegClass;
1724 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1726 // Transform the arguments in physical registers into virtual ones.
1727 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1728 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
1730 // If this is an 8, 16 or 32-bit value, it is really passed promoted
1731 // to 64 bits. Insert an assert[sz]ext to capture this, then
1732 // truncate to the right size.
1733 switch (VA.getLocInfo()) {
1735 llvm_unreachable("Unknown loc info!");
1736 case CCValAssign::Full:
1738 case CCValAssign::BCvt:
1739 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
1741 case CCValAssign::AExt:
1742 case CCValAssign::SExt:
1743 case CCValAssign::ZExt:
1744 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
1745 // nodes after our lowering.
1746 assert(RegVT == Ins[i].VT && "incorrect register location selected");
1750 InVals.push_back(ArgValue);
1752 } else { // VA.isRegLoc()
1753 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
1754 unsigned ArgOffset = VA.getLocMemOffset();
1755 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1757 uint32_t BEAlign = 0;
1758 if (ArgSize < 8 && !Subtarget->isLittleEndian())
1759 BEAlign = 8 - ArgSize;
1761 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
1763 // Create load nodes to retrieve arguments from the stack.
1764 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1767 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
1768 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
1769 MVT MemVT = VA.getValVT();
1771 switch (VA.getLocInfo()) {
1774 case CCValAssign::BCvt:
1775 MemVT = VA.getLocVT();
1777 case CCValAssign::SExt:
1778 ExtType = ISD::SEXTLOAD;
1780 case CCValAssign::ZExt:
1781 ExtType = ISD::ZEXTLOAD;
1783 case CCValAssign::AExt:
1784 ExtType = ISD::EXTLOAD;
1788 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
1789 MachinePointerInfo::getFixedStack(FI),
1790 MemVT, false, false, false, nullptr);
1792 InVals.push_back(ArgValue);
1798 if (!Subtarget->isTargetDarwin()) {
1799 // The AAPCS variadic function ABI is identical to the non-variadic
1800 // one. As a result there may be more arguments in registers and we should
1801 // save them for future reference.
1802 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
1805 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
1806 // This will point to the next argument passed via stack.
1807 unsigned StackOffset = CCInfo.getNextStackOffset();
1808 // We currently pass all varargs at 8-byte alignment.
1809 StackOffset = ((StackOffset + 7) & ~7);
1810 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
1813 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
1814 unsigned StackArgSize = CCInfo.getNextStackOffset();
1815 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
1816 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
1817 // This is a non-standard ABI so by fiat I say we're allowed to make full
1818 // use of the stack area to be popped, which must be aligned to 16 bytes in
1820 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
1822 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
1823 // a multiple of 16.
1824 FuncInfo->setArgumentStackToRestore(StackArgSize);
1826 // This realignment carries over to the available bytes below. Our own
1827 // callers will guarantee the space is free by giving an aligned value to
1830 // Even if we're not expected to free up the space, it's useful to know how
1831 // much is there while considering tail calls (because we can reuse it).
1832 FuncInfo->setBytesInStackArgArea(StackArgSize);
1837 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
1838 SelectionDAG &DAG, SDLoc DL,
1839 SDValue &Chain) const {
1840 MachineFunction &MF = DAG.getMachineFunction();
1841 MachineFrameInfo *MFI = MF.getFrameInfo();
1842 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
1844 SmallVector<SDValue, 8> MemOps;
1846 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
1847 AArch64::X3, AArch64::X4, AArch64::X5,
1848 AArch64::X6, AArch64::X7 };
1849 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
1850 unsigned FirstVariadicGPR =
1851 CCInfo.getFirstUnallocated(GPRArgRegs, NumGPRArgRegs);
1853 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
1855 if (GPRSaveSize != 0) {
1856 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
1858 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
1860 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
1861 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
1862 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
1864 DAG.getStore(Val.getValue(1), DL, Val, FIN,
1865 MachinePointerInfo::getStack(i * 8), false, false, 0);
1866 MemOps.push_back(Store);
1867 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1868 DAG.getConstant(8, getPointerTy()));
1871 FuncInfo->setVarArgsGPRIndex(GPRIdx);
1872 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
1874 if (Subtarget->hasFPARMv8()) {
1875 static const MCPhysReg FPRArgRegs[] = {
1876 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
1877 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
1878 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
1879 unsigned FirstVariadicFPR =
1880 CCInfo.getFirstUnallocated(FPRArgRegs, NumFPRArgRegs);
1882 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
1884 if (FPRSaveSize != 0) {
1885 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
1887 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
1889 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
1890 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
1891 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
1894 DAG.getStore(Val.getValue(1), DL, Val, FIN,
1895 MachinePointerInfo::getStack(i * 16), false, false, 0);
1896 MemOps.push_back(Store);
1897 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
1898 DAG.getConstant(16, getPointerTy()));
1901 FuncInfo->setVarArgsFPRIndex(FPRIdx);
1902 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
1905 if (!MemOps.empty()) {
1906 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
1910 /// LowerCallResult - Lower the result values of a call into the
1911 /// appropriate copies out of appropriate physical registers.
1912 SDValue AArch64TargetLowering::LowerCallResult(
1913 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
1914 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1915 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
1916 SDValue ThisVal) const {
1917 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
1918 ? RetCC_AArch64_WebKit_JS
1919 : RetCC_AArch64_AAPCS;
1920 // Assign locations to each value returned by this call.
1921 SmallVector<CCValAssign, 16> RVLocs;
1922 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1923 getTargetMachine(), RVLocs, *DAG.getContext());
1924 CCInfo.AnalyzeCallResult(Ins, RetCC);
1926 // Copy all of the result registers out of their specified physreg.
1927 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1928 CCValAssign VA = RVLocs[i];
1930 // Pass 'this' value directly from the argument to return value, to avoid
1931 // reg unit interference
1932 if (i == 0 && isThisReturn) {
1933 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
1934 "unexpected return calling convention register assignment");
1935 InVals.push_back(ThisVal);
1940 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
1941 Chain = Val.getValue(1);
1942 InFlag = Val.getValue(2);
1944 switch (VA.getLocInfo()) {
1946 llvm_unreachable("Unknown loc info!");
1947 case CCValAssign::Full:
1949 case CCValAssign::BCvt:
1950 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
1954 InVals.push_back(Val);
1960 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
1961 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
1962 bool isCalleeStructRet, bool isCallerStructRet,
1963 const SmallVectorImpl<ISD::OutputArg> &Outs,
1964 const SmallVectorImpl<SDValue> &OutVals,
1965 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
1966 // For CallingConv::C this function knows whether the ABI needs
1967 // changing. That's not true for other conventions so they will have to opt in
1969 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1972 const MachineFunction &MF = DAG.getMachineFunction();
1973 const Function *CallerF = MF.getFunction();
1974 CallingConv::ID CallerCC = CallerF->getCallingConv();
1975 bool CCMatch = CallerCC == CalleeCC;
1977 // Byval parameters hand the function a pointer directly into the stack area
1978 // we want to reuse during a tail call. Working around this *is* possible (see
1979 // X86) but less efficient and uglier in LowerCall.
1980 for (Function::const_arg_iterator i = CallerF->arg_begin(),
1981 e = CallerF->arg_end();
1983 if (i->hasByValAttr())
1986 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
1987 if (IsTailCallConvention(CalleeCC) && CCMatch)
1992 // Now we search for cases where we can use a tail call without changing the
1993 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
1996 // I want anyone implementing a new calling convention to think long and hard
1997 // about this assert.
1998 assert((!isVarArg || CalleeCC == CallingConv::C) &&
1999 "Unexpected variadic calling convention");
2001 if (isVarArg && !Outs.empty()) {
2002 // At least two cases here: if caller is fastcc then we can't have any
2003 // memory arguments (we'd be expected to clean up the stack afterwards). If
2004 // caller is C then we could potentially use its argument area.
2006 // FIXME: for now we take the most conservative of these in both cases:
2007 // disallow all variadic memory operands.
2008 SmallVector<CCValAssign, 16> ArgLocs;
2009 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2010 getTargetMachine(), ArgLocs, *DAG.getContext());
2012 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2013 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2014 if (!ArgLocs[i].isRegLoc())
2018 // If the calling conventions do not match, then we'd better make sure the
2019 // results are returned in the same way as what the caller expects.
2021 SmallVector<CCValAssign, 16> RVLocs1;
2022 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2023 getTargetMachine(), RVLocs1, *DAG.getContext());
2024 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2026 SmallVector<CCValAssign, 16> RVLocs2;
2027 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2028 getTargetMachine(), RVLocs2, *DAG.getContext());
2029 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2031 if (RVLocs1.size() != RVLocs2.size())
2033 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2034 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2036 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2038 if (RVLocs1[i].isRegLoc()) {
2039 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2042 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2048 // Nothing more to check if the callee is taking no arguments
2052 SmallVector<CCValAssign, 16> ArgLocs;
2053 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2054 getTargetMachine(), ArgLocs, *DAG.getContext());
2056 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2058 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2060 // If the stack arguments for this call would fit into our own save area then
2061 // the call can be made tail.
2062 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2065 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2067 MachineFrameInfo *MFI,
2068 int ClobberedFI) const {
2069 SmallVector<SDValue, 8> ArgChains;
2070 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2071 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2073 // Include the original chain at the beginning of the list. When this is
2074 // used by target LowerCall hooks, this helps legalize find the
2075 // CALLSEQ_BEGIN node.
2076 ArgChains.push_back(Chain);
2078 // Add a chain value for each stack argument corresponding
2079 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2080 UE = DAG.getEntryNode().getNode()->use_end();
2082 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2083 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2084 if (FI->getIndex() < 0) {
2085 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2086 int64_t InLastByte = InFirstByte;
2087 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2089 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2090 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2091 ArgChains.push_back(SDValue(L, 1));
2094 // Build a tokenfactor for all the chains.
2095 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2098 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2099 bool TailCallOpt) const {
2100 return CallCC == CallingConv::Fast && TailCallOpt;
2103 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2104 return CallCC == CallingConv::Fast;
2107 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2108 /// and add input and output parameter nodes.
2110 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2111 SmallVectorImpl<SDValue> &InVals) const {
2112 SelectionDAG &DAG = CLI.DAG;
2114 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2115 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2116 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2117 SDValue Chain = CLI.Chain;
2118 SDValue Callee = CLI.Callee;
2119 bool &IsTailCall = CLI.IsTailCall;
2120 CallingConv::ID CallConv = CLI.CallConv;
2121 bool IsVarArg = CLI.IsVarArg;
2123 MachineFunction &MF = DAG.getMachineFunction();
2124 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2125 bool IsThisReturn = false;
2127 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2128 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2129 bool IsSibCall = false;
2132 // Check if it's really possible to do a tail call.
2133 IsTailCall = isEligibleForTailCallOptimization(
2134 Callee, CallConv, IsVarArg, IsStructRet,
2135 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2136 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2137 report_fatal_error("failed to perform tail call elimination on a call "
2138 "site marked musttail");
2140 // A sibling call is one where we're under the usual C ABI and not planning
2141 // to change that but can still do a tail call:
2142 if (!TailCallOpt && IsTailCall)
2149 // Analyze operands of the call, assigning locations to each operand.
2150 SmallVector<CCValAssign, 16> ArgLocs;
2151 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
2152 getTargetMachine(), ArgLocs, *DAG.getContext());
2155 // Handle fixed and variable vector arguments differently.
2156 // Variable vector arguments always go into memory.
2157 unsigned NumArgs = Outs.size();
2159 for (unsigned i = 0; i != NumArgs; ++i) {
2160 MVT ArgVT = Outs[i].VT;
2161 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2162 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2163 /*IsVarArg=*/ !Outs[i].IsFixed);
2164 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2165 assert(!Res && "Call operand has unhandled type");
2169 // At this point, Outs[].VT may already be promoted to i32. To correctly
2170 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2171 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2172 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2173 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2175 unsigned NumArgs = Outs.size();
2176 for (unsigned i = 0; i != NumArgs; ++i) {
2177 MVT ValVT = Outs[i].VT;
2178 // Get type of the original argument.
2179 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2180 /*AllowUnknown*/ true);
2181 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2182 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2183 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2184 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2186 else if (ActualMVT == MVT::i16)
2189 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2190 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2191 assert(!Res && "Call operand has unhandled type");
2196 // Get a count of how many bytes are to be pushed on the stack.
2197 unsigned NumBytes = CCInfo.getNextStackOffset();
2200 // Since we're not changing the ABI to make this a tail call, the memory
2201 // operands are already available in the caller's incoming argument space.
2205 // FPDiff is the byte offset of the call's argument area from the callee's.
2206 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2207 // by this amount for a tail call. In a sibling call it must be 0 because the
2208 // caller will deallocate the entire stack and the callee still expects its
2209 // arguments to begin at SP+0. Completely unused for non-tail calls.
2212 if (IsTailCall && !IsSibCall) {
2213 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2215 // Since callee will pop argument stack as a tail call, we must keep the
2216 // popped size 16-byte aligned.
2217 NumBytes = RoundUpToAlignment(NumBytes, 16);
2219 // FPDiff will be negative if this tail call requires more space than we
2220 // would automatically have in our incoming argument space. Positive if we
2221 // can actually shrink the stack.
2222 FPDiff = NumReusableBytes - NumBytes;
2224 // The stack pointer must be 16-byte aligned at all times it's used for a
2225 // memory operation, which in practice means at *all* times and in
2226 // particular across call boundaries. Therefore our own arguments started at
2227 // a 16-byte aligned SP and the delta applied for the tail call should
2228 // satisfy the same constraint.
2229 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2232 // Adjust the stack pointer for the new arguments...
2233 // These operations are automatically eliminated by the prolog/epilog pass
2236 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL);
2238 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2240 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2241 SmallVector<SDValue, 8> MemOpChains;
2243 // Walk the register/memloc assignments, inserting copies/loads.
2244 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2245 ++i, ++realArgIdx) {
2246 CCValAssign &VA = ArgLocs[i];
2247 SDValue Arg = OutVals[realArgIdx];
2248 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2250 // Promote the value if needed.
2251 switch (VA.getLocInfo()) {
2253 llvm_unreachable("Unknown loc info!");
2254 case CCValAssign::Full:
2256 case CCValAssign::SExt:
2257 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2259 case CCValAssign::ZExt:
2260 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2262 case CCValAssign::AExt:
2263 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2264 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2265 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2266 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2268 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2270 case CCValAssign::BCvt:
2271 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2273 case CCValAssign::FPExt:
2274 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2278 if (VA.isRegLoc()) {
2279 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2280 assert(VA.getLocVT() == MVT::i64 &&
2281 "unexpected calling convention register assignment");
2282 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2283 "unexpected use of 'returned'");
2284 IsThisReturn = true;
2286 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2288 assert(VA.isMemLoc());
2291 MachinePointerInfo DstInfo;
2293 // FIXME: This works on big-endian for composite byvals, which are the
2294 // common case. It should also work for fundamental types too.
2295 uint32_t BEAlign = 0;
2296 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2297 : VA.getLocVT().getSizeInBits();
2298 OpSize = (OpSize + 7) / 8;
2299 if (!Subtarget->isLittleEndian() && !Flags.isByVal()) {
2301 BEAlign = 8 - OpSize;
2303 unsigned LocMemOffset = VA.getLocMemOffset();
2304 int32_t Offset = LocMemOffset + BEAlign;
2305 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2306 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2309 Offset = Offset + FPDiff;
2310 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2312 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2313 DstInfo = MachinePointerInfo::getFixedStack(FI);
2315 // Make sure any stack arguments overlapping with where we're storing
2316 // are loaded before this eventual operation. Otherwise they'll be
2318 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2320 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2322 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2323 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2326 if (Outs[i].Flags.isByVal()) {
2328 DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64);
2329 SDValue Cpy = DAG.getMemcpy(
2330 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2331 /*isVolatile = */ false,
2332 /*alwaysInline = */ false, DstInfo, MachinePointerInfo());
2334 MemOpChains.push_back(Cpy);
2336 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2337 // promoted to a legal register type i32, we should truncate Arg back to
2339 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2340 VA.getValVT() == MVT::i16)
2341 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2344 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2345 MemOpChains.push_back(Store);
2350 if (!MemOpChains.empty())
2351 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2353 // Build a sequence of copy-to-reg nodes chained together with token chain
2354 // and flag operands which copy the outgoing args into the appropriate regs.
2356 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2357 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2358 RegsToPass[i].second, InFlag);
2359 InFlag = Chain.getValue(1);
2362 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2363 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2364 // node so that legalize doesn't hack it.
2365 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2366 Subtarget->isTargetMachO()) {
2367 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2368 const GlobalValue *GV = G->getGlobal();
2369 bool InternalLinkage = GV->hasInternalLinkage();
2370 if (InternalLinkage)
2371 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2373 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2375 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2377 } else if (ExternalSymbolSDNode *S =
2378 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2379 const char *Sym = S->getSymbol();
2381 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2382 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2384 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2385 const GlobalValue *GV = G->getGlobal();
2386 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2387 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2388 const char *Sym = S->getSymbol();
2389 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2392 // We don't usually want to end the call-sequence here because we would tidy
2393 // the frame up *after* the call, however in the ABI-changing tail-call case
2394 // we've carefully laid out the parameters so that when sp is reset they'll be
2395 // in the correct location.
2396 if (IsTailCall && !IsSibCall) {
2397 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2398 DAG.getIntPtrConstant(0, true), InFlag, DL);
2399 InFlag = Chain.getValue(1);
2402 std::vector<SDValue> Ops;
2403 Ops.push_back(Chain);
2404 Ops.push_back(Callee);
2407 // Each tail call may have to adjust the stack by a different amount, so
2408 // this information must travel along with the operation for eventual
2409 // consumption by emitEpilogue.
2410 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
2413 // Add argument registers to the end of the list so that they are known live
2415 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2416 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2417 RegsToPass[i].second.getValueType()));
2419 // Add a register mask operand representing the call-preserved registers.
2420 const uint32_t *Mask;
2421 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2422 const AArch64RegisterInfo *ARI =
2423 static_cast<const AArch64RegisterInfo *>(TRI);
2425 // For 'this' returns, use the X0-preserving mask if applicable
2426 Mask = ARI->getThisReturnPreservedMask(CallConv);
2428 IsThisReturn = false;
2429 Mask = ARI->getCallPreservedMask(CallConv);
2432 Mask = ARI->getCallPreservedMask(CallConv);
2434 assert(Mask && "Missing call preserved mask for calling convention");
2435 Ops.push_back(DAG.getRegisterMask(Mask));
2437 if (InFlag.getNode())
2438 Ops.push_back(InFlag);
2440 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2442 // If we're doing a tall call, use a TC_RETURN here rather than an
2443 // actual call instruction.
2445 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2447 // Returns a chain and a flag for retval copy to use.
2448 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2449 InFlag = Chain.getValue(1);
2451 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2452 ? RoundUpToAlignment(NumBytes, 16)
2455 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2456 DAG.getIntPtrConstant(CalleePopBytes, true),
2459 InFlag = Chain.getValue(1);
2461 // Handle result values, copying them out of physregs into vregs that we
2463 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2464 InVals, IsThisReturn,
2465 IsThisReturn ? OutVals[0] : SDValue());
2468 bool AArch64TargetLowering::CanLowerReturn(
2469 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2470 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2471 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2472 ? RetCC_AArch64_WebKit_JS
2473 : RetCC_AArch64_AAPCS;
2474 SmallVector<CCValAssign, 16> RVLocs;
2475 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
2476 return CCInfo.CheckReturn(Outs, RetCC);
2480 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2482 const SmallVectorImpl<ISD::OutputArg> &Outs,
2483 const SmallVectorImpl<SDValue> &OutVals,
2484 SDLoc DL, SelectionDAG &DAG) const {
2485 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2486 ? RetCC_AArch64_WebKit_JS
2487 : RetCC_AArch64_AAPCS;
2488 SmallVector<CCValAssign, 16> RVLocs;
2489 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2490 getTargetMachine(), RVLocs, *DAG.getContext());
2491 CCInfo.AnalyzeReturn(Outs, RetCC);
2493 // Copy the result values into the output registers.
2495 SmallVector<SDValue, 4> RetOps(1, Chain);
2496 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2497 ++i, ++realRVLocIdx) {
2498 CCValAssign &VA = RVLocs[i];
2499 assert(VA.isRegLoc() && "Can only return in registers!");
2500 SDValue Arg = OutVals[realRVLocIdx];
2502 switch (VA.getLocInfo()) {
2504 llvm_unreachable("Unknown loc info!");
2505 case CCValAssign::Full:
2506 if (Outs[i].ArgVT == MVT::i1) {
2507 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2508 // value. This is strictly redundant on Darwin (which uses "zeroext
2509 // i1"), but will be optimised out before ISel.
2510 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2511 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2514 case CCValAssign::BCvt:
2515 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2519 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2520 Flag = Chain.getValue(1);
2521 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2524 RetOps[0] = Chain; // Update chain.
2526 // Add the flag if we have it.
2528 RetOps.push_back(Flag);
2530 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2533 //===----------------------------------------------------------------------===//
2534 // Other Lowering Code
2535 //===----------------------------------------------------------------------===//
2537 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2538 SelectionDAG &DAG) const {
2539 EVT PtrVT = getPointerTy();
2541 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2542 unsigned char OpFlags =
2543 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2545 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2546 "unexpected offset in global node");
2548 // This also catched the large code model case for Darwin.
2549 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2550 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2551 // FIXME: Once remat is capable of dealing with instructions with register
2552 // operands, expand this into two nodes instead of using a wrapper node.
2553 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2556 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2557 const unsigned char MO_NC = AArch64II::MO_NC;
2559 AArch64ISD::WrapperLarge, DL, PtrVT,
2560 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
2561 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
2562 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
2563 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
2565 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
2566 // the only correct model on Darwin.
2567 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2568 OpFlags | AArch64II::MO_PAGE);
2569 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2570 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
2572 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2573 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2577 /// \brief Convert a TLS address reference into the correct sequence of loads
2578 /// and calls to compute the variable's address (for Darwin, currently) and
2579 /// return an SDValue containing the final node.
2581 /// Darwin only has one TLS scheme which must be capable of dealing with the
2582 /// fully general situation, in the worst case. This means:
2583 /// + "extern __thread" declaration.
2584 /// + Defined in a possibly unknown dynamic library.
2586 /// The general system is that each __thread variable has a [3 x i64] descriptor
2587 /// which contains information used by the runtime to calculate the address. The
2588 /// only part of this the compiler needs to know about is the first xword, which
2589 /// contains a function pointer that must be called with the address of the
2590 /// entire descriptor in "x0".
2592 /// Since this descriptor may be in a different unit, in general even the
2593 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
2595 /// adrp x0, _var@TLVPPAGE
2596 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
2597 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
2598 /// ; the function pointer
2599 /// blr x1 ; Uses descriptor address in x0
2600 /// ; Address of _var is now in x0.
2602 /// If the address of _var's descriptor *is* known to the linker, then it can
2603 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
2604 /// a slight efficiency gain.
2606 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
2607 SelectionDAG &DAG) const {
2608 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
2611 MVT PtrVT = getPointerTy();
2612 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2615 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2616 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
2618 // The first entry in the descriptor is a function pointer that we must call
2619 // to obtain the address of the variable.
2620 SDValue Chain = DAG.getEntryNode();
2621 SDValue FuncTLVGet =
2622 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
2623 false, true, true, 8);
2624 Chain = FuncTLVGet.getValue(1);
2626 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2627 MFI->setAdjustsStack(true);
2629 // TLS calls preserve all registers except those that absolutely must be
2630 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2632 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2633 const AArch64RegisterInfo *ARI =
2634 static_cast<const AArch64RegisterInfo *>(TRI);
2635 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2637 // Finally, we can make the call. This is just a degenerate version of a
2638 // normal AArch64 call node: x0 takes the address of the descriptor, and
2639 // returns the address of the variable in this thread.
2640 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
2642 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2643 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
2644 DAG.getRegisterMask(Mask), Chain.getValue(1));
2645 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
2648 /// When accessing thread-local variables under either the general-dynamic or
2649 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
2650 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
2651 /// is a function pointer to carry out the resolution. This function takes the
2652 /// address of the descriptor in X0 and returns the TPIDR_EL0 offset in X0. All
2653 /// other registers (except LR, NZCV) are preserved.
2655 /// Thus, the ideal call sequence on AArch64 is:
2657 /// adrp x0, :tlsdesc:thread_var
2658 /// ldr x8, [x0, :tlsdesc_lo12:thread_var]
2659 /// add x0, x0, :tlsdesc_lo12:thread_var
2660 /// .tlsdesccall thread_var
2662 /// (TPIDR_EL0 offset now in x0).
2664 /// The ".tlsdesccall" directive instructs the assembler to insert a particular
2665 /// relocation to help the linker relax this sequence if it turns out to be too
2668 /// FIXME: we currently produce an extra, duplicated, ADRP instruction, but this
2670 SDValue AArch64TargetLowering::LowerELFTLSDescCall(SDValue SymAddr,
2671 SDValue DescAddr, SDLoc DL,
2672 SelectionDAG &DAG) const {
2673 EVT PtrVT = getPointerTy();
2675 // The function we need to call is simply the first entry in the GOT for this
2676 // descriptor, load it in preparation.
2677 SDValue Func = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, SymAddr);
2679 // TLS calls preserve all registers except those that absolutely must be
2680 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
2682 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2683 const AArch64RegisterInfo *ARI =
2684 static_cast<const AArch64RegisterInfo *>(TRI);
2685 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
2687 // The function takes only one argument: the address of the descriptor itself
2689 SDValue Glue, Chain;
2690 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
2691 Glue = Chain.getValue(1);
2693 // We're now ready to populate the argument list, as with a normal call:
2694 SmallVector<SDValue, 6> Ops;
2695 Ops.push_back(Chain);
2696 Ops.push_back(Func);
2697 Ops.push_back(SymAddr);
2698 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
2699 Ops.push_back(DAG.getRegisterMask(Mask));
2700 Ops.push_back(Glue);
2702 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2703 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALL, DL, NodeTys, Ops);
2704 Glue = Chain.getValue(1);
2706 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
2710 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
2711 SelectionDAG &DAG) const {
2712 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
2713 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2714 "ELF TLS only supported in small memory model");
2715 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2717 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
2720 EVT PtrVT = getPointerTy();
2722 const GlobalValue *GV = GA->getGlobal();
2724 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
2726 if (Model == TLSModel::LocalExec) {
2727 SDValue HiVar = DAG.getTargetGlobalAddress(
2728 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
2729 SDValue LoVar = DAG.getTargetGlobalAddress(
2731 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
2733 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2734 DAG.getTargetConstant(16, MVT::i32)),
2736 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, TPOff, LoVar,
2737 DAG.getTargetConstant(0, MVT::i32)),
2739 } else if (Model == TLSModel::InitialExec) {
2740 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2741 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
2742 } else if (Model == TLSModel::LocalDynamic) {
2743 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
2744 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
2745 // the beginning of the module's TLS region, followed by a DTPREL offset
2748 // These accesses will need deduplicating if there's more than one.
2749 AArch64FunctionInfo *MFI =
2750 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
2751 MFI->incNumLocalDynamicTLSAccesses();
2753 // Accesses used in this sequence go via the TLS descriptor which lives in
2754 // the GOT. Prepare an address we can use to handle this.
2755 SDValue HiDesc = DAG.getTargetExternalSymbol(
2756 "_TLS_MODULE_BASE_", PtrVT, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2757 SDValue LoDesc = DAG.getTargetExternalSymbol(
2758 "_TLS_MODULE_BASE_", PtrVT,
2759 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
2761 // First argument to the descriptor call is the address of the descriptor
2763 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2764 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2766 // The call needs a relocation too for linker relaxation. It doesn't make
2767 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2769 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
2772 // Now we can calculate the offset from TPIDR_EL0 to this module's
2773 // thread-local area.
2774 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2776 // Now use :dtprel_whatever: operations to calculate this variable's offset
2777 // in its thread-storage area.
2778 SDValue HiVar = DAG.getTargetGlobalAddress(
2779 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
2780 SDValue LoVar = DAG.getTargetGlobalAddress(
2781 GV, DL, MVT::i64, 0,
2782 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
2785 SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
2786 DAG.getTargetConstant(16, MVT::i32)),
2789 SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, DTPOff, LoVar,
2790 DAG.getTargetConstant(0, MVT::i32)),
2793 TPOff = DAG.getNode(ISD::ADD, DL, PtrVT, TPOff, DTPOff);
2794 } else if (Model == TLSModel::GeneralDynamic) {
2795 // Accesses used in this sequence go via the TLS descriptor which lives in
2796 // the GOT. Prepare an address we can use to handle this.
2797 SDValue HiDesc = DAG.getTargetGlobalAddress(
2798 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_PAGE);
2799 SDValue LoDesc = DAG.getTargetGlobalAddress(
2801 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
2803 // First argument to the descriptor call is the address of the descriptor
2805 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
2806 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
2808 // The call needs a relocation too for linker relaxation. It doesn't make
2809 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
2812 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
2814 // Finally we can make a call to calculate the offset from tpidr_el0.
2815 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
2817 llvm_unreachable("Unsupported ELF TLS access model");
2819 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
2822 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
2823 SelectionDAG &DAG) const {
2824 if (Subtarget->isTargetDarwin())
2825 return LowerDarwinGlobalTLSAddress(Op, DAG);
2826 else if (Subtarget->isTargetELF())
2827 return LowerELFGlobalTLSAddress(Op, DAG);
2829 llvm_unreachable("Unexpected platform trying to use TLS");
2831 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2832 SDValue Chain = Op.getOperand(0);
2833 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2834 SDValue LHS = Op.getOperand(2);
2835 SDValue RHS = Op.getOperand(3);
2836 SDValue Dest = Op.getOperand(4);
2839 // Handle f128 first, since lowering it will result in comparing the return
2840 // value of a libcall against zero, which is just what the rest of LowerBR_CC
2841 // is expecting to deal with.
2842 if (LHS.getValueType() == MVT::f128) {
2843 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
2845 // If softenSetCCOperands returned a scalar, we need to compare the result
2846 // against zero to select between true and false values.
2847 if (!RHS.getNode()) {
2848 RHS = DAG.getConstant(0, LHS.getValueType());
2853 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
2855 unsigned Opc = LHS.getOpcode();
2856 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
2857 cast<ConstantSDNode>(RHS)->isOne() &&
2858 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
2859 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
2860 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
2861 "Unexpected condition code.");
2862 // Only lower legal XALUO ops.
2863 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
2866 // The actual operation with overflow check.
2867 AArch64CC::CondCode OFCC;
2868 SDValue Value, Overflow;
2869 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
2871 if (CC == ISD::SETNE)
2872 OFCC = getInvertedCondCode(OFCC);
2873 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
2875 return DAG.getNode(AArch64ISD::BRCOND, SDLoc(LHS), MVT::Other, Chain, Dest,
2879 if (LHS.getValueType().isInteger()) {
2880 assert((LHS.getValueType() == RHS.getValueType()) &&
2881 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
2883 // If the RHS of the comparison is zero, we can potentially fold this
2884 // to a specialized branch.
2885 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
2886 if (RHSC && RHSC->getZExtValue() == 0) {
2887 if (CC == ISD::SETEQ) {
2888 // See if we can use a TBZ to fold in an AND as well.
2889 // TBZ has a smaller branch displacement than CBZ. If the offset is
2890 // out of bounds, a late MI-layer pass rewrites branches.
2891 // 403.gcc is an example that hits this case.
2892 if (LHS.getOpcode() == ISD::AND &&
2893 isa<ConstantSDNode>(LHS.getOperand(1)) &&
2894 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
2895 SDValue Test = LHS.getOperand(0);
2896 uint64_t Mask = LHS.getConstantOperandVal(1);
2898 // TBZ only operates on i64's, but the ext should be free.
2899 if (Test.getValueType() == MVT::i32)
2900 Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64);
2902 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
2903 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
2906 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
2907 } else if (CC == ISD::SETNE) {
2908 // See if we can use a TBZ to fold in an AND as well.
2909 // TBZ has a smaller branch displacement than CBZ. If the offset is
2910 // out of bounds, a late MI-layer pass rewrites branches.
2911 // 403.gcc is an example that hits this case.
2912 if (LHS.getOpcode() == ISD::AND &&
2913 isa<ConstantSDNode>(LHS.getOperand(1)) &&
2914 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
2915 SDValue Test = LHS.getOperand(0);
2916 uint64_t Mask = LHS.getConstantOperandVal(1);
2918 // TBNZ only operates on i64's, but the ext should be free.
2919 if (Test.getValueType() == MVT::i32)
2920 Test = DAG.getAnyExtOrTrunc(Test, dl, MVT::i64);
2922 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
2923 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
2926 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
2931 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
2932 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
2936 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2938 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
2939 // clean. Some of them require two branches to implement.
2940 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
2941 AArch64CC::CondCode CC1, CC2;
2942 changeFPCCToAArch64CC(CC, CC1, CC2);
2943 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
2945 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
2946 if (CC2 != AArch64CC::AL) {
2947 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
2948 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
2955 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
2956 SelectionDAG &DAG) const {
2957 EVT VT = Op.getValueType();
2960 SDValue In1 = Op.getOperand(0);
2961 SDValue In2 = Op.getOperand(1);
2962 EVT SrcVT = In2.getValueType();
2964 if (SrcVT == MVT::f32 && VT == MVT::f64)
2965 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
2966 else if (SrcVT == MVT::f64 && VT == MVT::f32)
2967 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0));
2969 // FIXME: Src type is different, bail out for now. Can VT really be a
2976 SDValue EltMask, VecVal1, VecVal2;
2977 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
2980 EltMask = DAG.getConstant(0x80000000ULL, EltVT);
2982 if (!VT.isVector()) {
2983 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
2984 DAG.getUNDEF(VecVT), In1);
2985 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
2986 DAG.getUNDEF(VecVT), In2);
2988 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
2989 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
2991 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
2995 // We want to materialize a mask with the the high bit set, but the AdvSIMD
2996 // immediate moves cannot materialize that in a single instruction for
2997 // 64-bit elements. Instead, materialize zero and then negate it.
2998 EltMask = DAG.getConstant(0, EltVT);
3000 if (!VT.isVector()) {
3001 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3002 DAG.getUNDEF(VecVT), In1);
3003 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3004 DAG.getUNDEF(VecVT), In2);
3006 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3007 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3010 llvm_unreachable("Invalid type for copysign!");
3013 std::vector<SDValue> BuildVectorOps;
3014 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i)
3015 BuildVectorOps.push_back(EltMask);
3017 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, BuildVectorOps);
3019 // If we couldn't materialize the mask above, then the mask vector will be
3020 // the zero vector, and we need to negate it here.
3021 if (VT == MVT::f64 || VT == MVT::v2f64) {
3022 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3023 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3024 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3028 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3031 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3032 else if (VT == MVT::f64)
3033 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3035 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3038 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3039 if (DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
3040 AttributeSet::FunctionIndex, Attribute::NoImplicitFloat))
3043 // While there is no integer popcount instruction, it can
3044 // be more efficiently lowered to the following sequence that uses
3045 // AdvSIMD registers/instructions as long as the copies to/from
3046 // the AdvSIMD registers are cheap.
3047 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3048 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3049 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3050 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3051 SDValue Val = Op.getOperand(0);
3053 EVT VT = Op.getValueType();
3054 SDValue ZeroVec = DAG.getUNDEF(MVT::v8i8);
3057 if (VT == MVT::i32) {
3058 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val);
3059 VecVal = DAG.getTargetInsertSubreg(AArch64::ssub, DL, MVT::v8i8, ZeroVec,
3062 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3065 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, VecVal);
3066 SDValue UaddLV = DAG.getNode(
3067 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3068 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
3071 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3075 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3077 if (Op.getValueType().isVector())
3078 return LowerVSETCC(Op, DAG);
3080 SDValue LHS = Op.getOperand(0);
3081 SDValue RHS = Op.getOperand(1);
3082 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3085 // We chose ZeroOrOneBooleanContents, so use zero and one.
3086 EVT VT = Op.getValueType();
3087 SDValue TVal = DAG.getConstant(1, VT);
3088 SDValue FVal = DAG.getConstant(0, VT);
3090 // Handle f128 first, since one possible outcome is a normal integer
3091 // comparison which gets picked up by the next if statement.
3092 if (LHS.getValueType() == MVT::f128) {
3093 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3095 // If softenSetCCOperands returned a scalar, use it.
3096 if (!RHS.getNode()) {
3097 assert(LHS.getValueType() == Op.getValueType() &&
3098 "Unexpected setcc expansion!");
3103 if (LHS.getValueType().isInteger()) {
3106 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3108 // Note that we inverted the condition above, so we reverse the order of
3109 // the true and false operands here. This will allow the setcc to be
3110 // matched to a single CSINC instruction.
3111 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3114 // Now we know we're dealing with FP values.
3115 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3117 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3118 // and do the comparison.
3119 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3121 AArch64CC::CondCode CC1, CC2;
3122 changeFPCCToAArch64CC(CC, CC1, CC2);
3123 if (CC2 == AArch64CC::AL) {
3124 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3125 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3127 // Note that we inverted the condition above, so we reverse the order of
3128 // the true and false operands here. This will allow the setcc to be
3129 // matched to a single CSINC instruction.
3130 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3132 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3133 // totally clean. Some of them require two CSELs to implement. As is in
3134 // this case, we emit the first CSEL and then emit a second using the output
3135 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3137 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3138 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3140 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3142 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3143 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3147 /// A SELECT_CC operation is really some kind of max or min if both values being
3148 /// compared are, in some sense, equal to the results in either case. However,
3149 /// it is permissible to compare f32 values and produce directly extended f64
3152 /// Extending the comparison operands would also be allowed, but is less likely
3153 /// to happen in practice since their use is right here. Note that truncate
3154 /// operations would *not* be semantically equivalent.
3155 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3159 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3160 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3161 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3162 Result.getValueType() == MVT::f64) {
3164 APFloat CmpVal = CCmp->getValueAPF();
3165 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3166 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3169 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3172 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3173 SelectionDAG &DAG) const {
3174 SDValue CC = Op->getOperand(0);
3175 SDValue TVal = Op->getOperand(1);
3176 SDValue FVal = Op->getOperand(2);
3179 unsigned Opc = CC.getOpcode();
3180 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3182 if (CC.getResNo() == 1 &&
3183 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3184 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3185 // Only lower legal XALUO ops.
3186 if (!DAG.getTargetLoweringInfo().isTypeLegal(CC->getValueType(0)))
3189 AArch64CC::CondCode OFCC;
3190 SDValue Value, Overflow;
3191 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CC.getValue(0), DAG);
3192 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3194 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3198 if (CC.getOpcode() == ISD::SETCC)
3199 return DAG.getSelectCC(DL, CC.getOperand(0), CC.getOperand(1), TVal, FVal,
3200 cast<CondCodeSDNode>(CC.getOperand(2))->get());
3202 return DAG.getSelectCC(DL, CC, DAG.getConstant(0, CC.getValueType()), TVal,
3206 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3207 SelectionDAG &DAG) const {
3208 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3209 SDValue LHS = Op.getOperand(0);
3210 SDValue RHS = Op.getOperand(1);
3211 SDValue TVal = Op.getOperand(2);
3212 SDValue FVal = Op.getOperand(3);
3215 // Handle f128 first, because it will result in a comparison of some RTLIB
3216 // call result against zero.
3217 if (LHS.getValueType() == MVT::f128) {
3218 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3220 // If softenSetCCOperands returned a scalar, we need to compare the result
3221 // against zero to select between true and false values.
3222 if (!RHS.getNode()) {
3223 RHS = DAG.getConstant(0, LHS.getValueType());
3228 // Handle integers first.
3229 if (LHS.getValueType().isInteger()) {
3230 assert((LHS.getValueType() == RHS.getValueType()) &&
3231 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3233 unsigned Opcode = AArch64ISD::CSEL;
3235 // If both the TVal and the FVal are constants, see if we can swap them in
3236 // order to for a CSINV or CSINC out of them.
3237 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3238 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3240 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3241 std::swap(TVal, FVal);
3242 std::swap(CTVal, CFVal);
3243 CC = ISD::getSetCCInverse(CC, true);
3244 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3245 std::swap(TVal, FVal);
3246 std::swap(CTVal, CFVal);
3247 CC = ISD::getSetCCInverse(CC, true);
3248 } else if (TVal.getOpcode() == ISD::XOR) {
3249 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3250 // with a CSINV rather than a CSEL.
3251 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3253 if (CVal && CVal->isAllOnesValue()) {
3254 std::swap(TVal, FVal);
3255 std::swap(CTVal, CFVal);
3256 CC = ISD::getSetCCInverse(CC, true);
3258 } else if (TVal.getOpcode() == ISD::SUB) {
3259 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3260 // that we can match with a CSNEG rather than a CSEL.
3261 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3263 if (CVal && CVal->isNullValue()) {
3264 std::swap(TVal, FVal);
3265 std::swap(CTVal, CFVal);
3266 CC = ISD::getSetCCInverse(CC, true);
3268 } else if (CTVal && CFVal) {
3269 const int64_t TrueVal = CTVal->getSExtValue();
3270 const int64_t FalseVal = CFVal->getSExtValue();
3273 // If both TVal and FVal are constants, see if FVal is the
3274 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3275 // instead of a CSEL in that case.
3276 if (TrueVal == ~FalseVal) {
3277 Opcode = AArch64ISD::CSINV;
3278 } else if (TrueVal == -FalseVal) {
3279 Opcode = AArch64ISD::CSNEG;
3280 } else if (TVal.getValueType() == MVT::i32) {
3281 // If our operands are only 32-bit wide, make sure we use 32-bit
3282 // arithmetic for the check whether we can use CSINC. This ensures that
3283 // the addition in the check will wrap around properly in case there is
3284 // an overflow (which would not be the case if we do the check with
3285 // 64-bit arithmetic).
3286 const uint32_t TrueVal32 = CTVal->getZExtValue();
3287 const uint32_t FalseVal32 = CFVal->getZExtValue();
3289 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3290 Opcode = AArch64ISD::CSINC;
3292 if (TrueVal32 > FalseVal32) {
3296 // 64-bit check whether we can use CSINC.
3297 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3298 Opcode = AArch64ISD::CSINC;
3300 if (TrueVal > FalseVal) {
3305 // Swap TVal and FVal if necessary.
3307 std::swap(TVal, FVal);
3308 std::swap(CTVal, CFVal);
3309 CC = ISD::getSetCCInverse(CC, true);
3312 if (Opcode != AArch64ISD::CSEL) {
3313 // Drop FVal since we can get its value by simply inverting/negating
3320 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3322 EVT VT = Op.getValueType();
3323 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3326 // Now we know we're dealing with FP values.
3327 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3328 assert(LHS.getValueType() == RHS.getValueType());
3329 EVT VT = Op.getValueType();
3331 // Try to match this select into a max/min operation, which have dedicated
3332 // opcode in the instruction set.
3333 // FIXME: This is not correct in the presence of NaNs, so we only enable this
3335 if (getTargetMachine().Options.NoNaNsFPMath) {
3336 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
3337 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
3338 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
3339 CC = ISD::getSetCCSwappedOperands(CC);
3340 std::swap(MinMaxLHS, MinMaxRHS);
3343 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
3344 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
3354 return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
3362 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
3368 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3369 // and do the comparison.
3370 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3372 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3373 // clean. Some of them require two CSELs to implement.
3374 AArch64CC::CondCode CC1, CC2;
3375 changeFPCCToAArch64CC(CC, CC1, CC2);
3376 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3377 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3379 // If we need a second CSEL, emit it, using the output of the first as the
3380 // RHS. We're effectively OR'ing the two CC's together.
3381 if (CC2 != AArch64CC::AL) {
3382 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3383 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3386 // Otherwise, return the output of the first CSEL.
3390 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3391 SelectionDAG &DAG) const {
3392 // Jump table entries as PC relative offsets. No additional tweaking
3393 // is necessary here. Just get the address of the jump table.
3394 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3395 EVT PtrVT = getPointerTy();
3398 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3399 !Subtarget->isTargetMachO()) {
3400 const unsigned char MO_NC = AArch64II::MO_NC;
3402 AArch64ISD::WrapperLarge, DL, PtrVT,
3403 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3404 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3405 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3406 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3407 AArch64II::MO_G0 | MO_NC));
3411 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3412 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3413 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3414 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3415 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3418 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3419 SelectionDAG &DAG) const {
3420 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3421 EVT PtrVT = getPointerTy();
3424 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3425 // Use the GOT for the large code model on iOS.
3426 if (Subtarget->isTargetMachO()) {
3427 SDValue GotAddr = DAG.getTargetConstantPool(
3428 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3430 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3433 const unsigned char MO_NC = AArch64II::MO_NC;
3435 AArch64ISD::WrapperLarge, DL, PtrVT,
3436 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3437 CP->getOffset(), AArch64II::MO_G3),
3438 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3439 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3440 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3441 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3442 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3443 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3445 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3446 // ELF, the only valid one on Darwin.
3448 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3449 CP->getOffset(), AArch64II::MO_PAGE);
3450 SDValue Lo = DAG.getTargetConstantPool(
3451 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3452 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3454 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3455 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3459 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3460 SelectionDAG &DAG) const {
3461 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3462 EVT PtrVT = getPointerTy();
3464 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3465 !Subtarget->isTargetMachO()) {
3466 const unsigned char MO_NC = AArch64II::MO_NC;
3468 AArch64ISD::WrapperLarge, DL, PtrVT,
3469 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3470 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3471 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3472 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3474 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3475 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3477 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3478 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3482 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3483 SelectionDAG &DAG) const {
3484 AArch64FunctionInfo *FuncInfo =
3485 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3489 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3490 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3491 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3492 MachinePointerInfo(SV), false, false, 0);
3495 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3496 SelectionDAG &DAG) const {
3497 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3498 // Standard, section B.3.
3499 MachineFunction &MF = DAG.getMachineFunction();
3500 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3503 SDValue Chain = Op.getOperand(0);
3504 SDValue VAList = Op.getOperand(1);
3505 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3506 SmallVector<SDValue, 4> MemOps;
3508 // void *__stack at offset 0
3510 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3511 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3512 MachinePointerInfo(SV), false, false, 8));
3514 // void *__gr_top at offset 8
3515 int GPRSize = FuncInfo->getVarArgsGPRSize();
3517 SDValue GRTop, GRTopAddr;
3519 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3520 DAG.getConstant(8, getPointerTy()));
3522 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3523 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3524 DAG.getConstant(GPRSize, getPointerTy()));
3526 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3527 MachinePointerInfo(SV, 8), false, false, 8));
3530 // void *__vr_top at offset 16
3531 int FPRSize = FuncInfo->getVarArgsFPRSize();
3533 SDValue VRTop, VRTopAddr;
3534 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3535 DAG.getConstant(16, getPointerTy()));
3537 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3538 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3539 DAG.getConstant(FPRSize, getPointerTy()));
3541 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3542 MachinePointerInfo(SV, 16), false, false, 8));
3545 // int __gr_offs at offset 24
3546 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3547 DAG.getConstant(24, getPointerTy()));
3548 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3549 GROffsAddr, MachinePointerInfo(SV, 24), false,
3552 // int __vr_offs at offset 28
3553 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3554 DAG.getConstant(28, getPointerTy()));
3555 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3556 VROffsAddr, MachinePointerInfo(SV, 28), false,
3559 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3562 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3563 SelectionDAG &DAG) const {
3564 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3565 : LowerAAPCS_VASTART(Op, DAG);
3568 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3569 SelectionDAG &DAG) const {
3570 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3572 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3573 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3574 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3576 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1),
3577 Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32),
3578 8, false, false, MachinePointerInfo(DestSV),
3579 MachinePointerInfo(SrcSV));
3582 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3583 assert(Subtarget->isTargetDarwin() &&
3584 "automatic va_arg instruction only works on Darwin");
3586 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3587 EVT VT = Op.getValueType();
3589 SDValue Chain = Op.getOperand(0);
3590 SDValue Addr = Op.getOperand(1);
3591 unsigned Align = Op.getConstantOperandVal(3);
3593 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3594 MachinePointerInfo(V), false, false, false, 0);
3595 Chain = VAList.getValue(1);
3598 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
3599 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3600 DAG.getConstant(Align - 1, getPointerTy()));
3601 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
3602 DAG.getConstant(-(int64_t)Align, getPointerTy()));
3605 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
3606 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
3608 // Scalar integer and FP values smaller than 64 bits are implicitly extended
3609 // up to 64 bits. At the very least, we have to increase the striding of the
3610 // vaargs list to match this, and for FP values we need to introduce
3611 // FP_ROUND nodes as well.
3612 if (VT.isInteger() && !VT.isVector())
3614 bool NeedFPTrunc = false;
3615 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
3620 // Increment the pointer, VAList, to the next vaarg
3621 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3622 DAG.getConstant(ArgSize, getPointerTy()));
3623 // Store the incremented VAList to the legalized pointer
3624 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
3627 // Load the actual argument out of the pointer VAList
3629 // Load the value as an f64.
3630 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
3631 MachinePointerInfo(), false, false, false, 0);
3632 // Round the value down to an f32.
3633 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
3634 DAG.getIntPtrConstant(1));
3635 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
3636 // Merge the rounded value with the chain output of the load.
3637 return DAG.getMergeValues(Ops, DL);
3640 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
3644 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
3645 SelectionDAG &DAG) const {
3646 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3647 MFI->setFrameAddressIsTaken(true);
3649 EVT VT = Op.getValueType();
3651 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3653 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
3655 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
3656 MachinePointerInfo(), false, false, false, 0);
3660 // FIXME? Maybe this could be a TableGen attribute on some registers and
3661 // this table could be generated automatically from RegInfo.
3662 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
3664 unsigned Reg = StringSwitch<unsigned>(RegName)
3665 .Case("sp", AArch64::SP)
3669 report_fatal_error("Invalid register name global variable");
3672 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
3673 SelectionDAG &DAG) const {
3674 MachineFunction &MF = DAG.getMachineFunction();
3675 MachineFrameInfo *MFI = MF.getFrameInfo();
3676 MFI->setReturnAddressIsTaken(true);
3678 EVT VT = Op.getValueType();
3680 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3682 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3683 SDValue Offset = DAG.getConstant(8, getPointerTy());
3684 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
3685 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
3686 MachinePointerInfo(), false, false, false, 0);
3689 // Return LR, which contains the return address. Mark it an implicit live-in.
3690 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
3691 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
3694 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3695 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3696 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
3697 SelectionDAG &DAG) const {
3698 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3699 EVT VT = Op.getValueType();
3700 unsigned VTBits = VT.getSizeInBits();
3702 SDValue ShOpLo = Op.getOperand(0);
3703 SDValue ShOpHi = Op.getOperand(1);
3704 SDValue ShAmt = Op.getOperand(2);
3706 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3708 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3710 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3711 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3712 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3713 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3714 DAG.getConstant(VTBits, MVT::i64));
3715 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3717 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3718 ISD::SETGE, dl, DAG);
3719 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3721 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3722 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3724 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3726 // AArch64 shifts larger than the register width are wrapped rather than
3727 // clamped, so we can't just emit "hi >> x".
3728 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3729 SDValue TrueValHi = Opc == ISD::SRA
3730 ? DAG.getNode(Opc, dl, VT, ShOpHi,
3731 DAG.getConstant(VTBits - 1, MVT::i64))
3732 : DAG.getConstant(0, VT);
3734 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
3736 SDValue Ops[2] = { Lo, Hi };
3737 return DAG.getMergeValues(Ops, dl);
3740 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3741 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
3742 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
3743 SelectionDAG &DAG) const {
3744 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3745 EVT VT = Op.getValueType();
3746 unsigned VTBits = VT.getSizeInBits();
3748 SDValue ShOpLo = Op.getOperand(0);
3749 SDValue ShOpHi = Op.getOperand(1);
3750 SDValue ShAmt = Op.getOperand(2);
3753 assert(Op.getOpcode() == ISD::SHL_PARTS);
3754 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
3755 DAG.getConstant(VTBits, MVT::i64), ShAmt);
3756 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3757 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
3758 DAG.getConstant(VTBits, MVT::i64));
3759 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3760 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3762 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3764 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
3765 ISD::SETGE, dl, DAG);
3766 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
3768 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
3770 // AArch64 shifts of larger than register sizes are wrapped rather than
3771 // clamped, so we can't just emit "lo << a" if a is too big.
3772 SDValue TrueValLo = DAG.getConstant(0, VT);
3773 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3775 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
3777 SDValue Ops[2] = { Lo, Hi };
3778 return DAG.getMergeValues(Ops, dl);
3781 bool AArch64TargetLowering::isOffsetFoldingLegal(
3782 const GlobalAddressSDNode *GA) const {
3783 // The AArch64 target doesn't support folding offsets into global addresses.
3787 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3788 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
3789 // FIXME: We should be able to handle f128 as well with a clever lowering.
3790 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
3794 return AArch64_AM::getFP64Imm(Imm) != -1;
3795 else if (VT == MVT::f32)
3796 return AArch64_AM::getFP32Imm(Imm) != -1;
3800 //===----------------------------------------------------------------------===//
3801 // AArch64 Optimization Hooks
3802 //===----------------------------------------------------------------------===//
3804 //===----------------------------------------------------------------------===//
3805 // AArch64 Inline Assembly Support
3806 //===----------------------------------------------------------------------===//
3808 // Table of Constraints
3809 // TODO: This is the current set of constraints supported by ARM for the
3810 // compiler, not all of them may make sense, e.g. S may be difficult to support.
3812 // r - A general register
3813 // w - An FP/SIMD register of some size in the range v0-v31
3814 // x - An FP/SIMD register of some size in the range v0-v15
3815 // I - Constant that can be used with an ADD instruction
3816 // J - Constant that can be used with a SUB instruction
3817 // K - Constant that can be used with a 32-bit logical instruction
3818 // L - Constant that can be used with a 64-bit logical instruction
3819 // M - Constant that can be used as a 32-bit MOV immediate
3820 // N - Constant that can be used as a 64-bit MOV immediate
3821 // Q - A memory reference with base register and no offset
3822 // S - A symbolic address
3823 // Y - Floating point constant zero
3824 // Z - Integer constant zero
3826 // Note that general register operands will be output using their 64-bit x
3827 // register name, whatever the size of the variable, unless the asm operand
3828 // is prefixed by the %w modifier. Floating-point and SIMD register operands
3829 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
3832 /// getConstraintType - Given a constraint letter, return the type of
3833 /// constraint it is for this target.
3834 AArch64TargetLowering::ConstraintType
3835 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
3836 if (Constraint.size() == 1) {
3837 switch (Constraint[0]) {
3844 return C_RegisterClass;
3845 // An address with a single base register. Due to the way we
3846 // currently handle addresses it is the same as 'r'.
3851 return TargetLowering::getConstraintType(Constraint);
3854 /// Examine constraint type and operand type and determine a weight value.
3855 /// This object must already have been set up with the operand type
3856 /// and the current alternative constraint selected.
3857 TargetLowering::ConstraintWeight
3858 AArch64TargetLowering::getSingleConstraintMatchWeight(
3859 AsmOperandInfo &info, const char *constraint) const {
3860 ConstraintWeight weight = CW_Invalid;
3861 Value *CallOperandVal = info.CallOperandVal;
3862 // If we don't have a value, we can't do a match,
3863 // but allow it at the lowest weight.
3864 if (!CallOperandVal)
3866 Type *type = CallOperandVal->getType();
3867 // Look at the constraint type.
3868 switch (*constraint) {
3870 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3874 if (type->isFloatingPointTy() || type->isVectorTy())
3875 weight = CW_Register;
3878 weight = CW_Constant;
3884 std::pair<unsigned, const TargetRegisterClass *>
3885 AArch64TargetLowering::getRegForInlineAsmConstraint(
3886 const std::string &Constraint, MVT VT) const {
3887 if (Constraint.size() == 1) {
3888 switch (Constraint[0]) {
3890 if (VT.getSizeInBits() == 64)
3891 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
3892 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
3895 return std::make_pair(0U, &AArch64::FPR32RegClass);
3896 if (VT.getSizeInBits() == 64)
3897 return std::make_pair(0U, &AArch64::FPR64RegClass);
3898 if (VT.getSizeInBits() == 128)
3899 return std::make_pair(0U, &AArch64::FPR128RegClass);
3901 // The instructions that this constraint is designed for can
3902 // only take 128-bit registers so just use that regclass.
3904 if (VT.getSizeInBits() == 128)
3905 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
3909 if (StringRef("{cc}").equals_lower(Constraint))
3910 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
3912 // Use the default implementation in TargetLowering to convert the register
3913 // constraint into a member of a register class.
3914 std::pair<unsigned, const TargetRegisterClass *> Res;
3915 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3917 // Not found as a standard register?
3919 unsigned Size = Constraint.size();
3920 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
3921 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
3922 const std::string Reg =
3923 std::string(&Constraint[2], &Constraint[Size - 1]);
3924 int RegNo = atoi(Reg.c_str());
3925 if (RegNo >= 0 && RegNo <= 31) {
3926 // v0 - v31 are aliases of q0 - q31.
3927 // By default we'll emit v0-v31 for this unless there's a modifier where
3928 // we'll emit the correct register as well.
3929 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
3930 Res.second = &AArch64::FPR128RegClass;
3938 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3939 /// vector. If it is invalid, don't add anything to Ops.
3940 void AArch64TargetLowering::LowerAsmOperandForConstraint(
3941 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
3942 SelectionDAG &DAG) const {
3945 // Currently only support length 1 constraints.
3946 if (Constraint.length() != 1)
3949 char ConstraintLetter = Constraint[0];
3950 switch (ConstraintLetter) {
3954 // This set of constraints deal with valid constants for various instructions.
3955 // Validate and return a target constant for them if we can.
3957 // 'z' maps to xzr or wzr so it needs an input of 0.
3958 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3959 if (!C || C->getZExtValue() != 0)
3962 if (Op.getValueType() == MVT::i64)
3963 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
3965 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
3975 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3979 // Grab the value and do some validation.
3980 uint64_t CVal = C->getZExtValue();
3981 switch (ConstraintLetter) {
3982 // The I constraint applies only to simple ADD or SUB immediate operands:
3983 // i.e. 0 to 4095 with optional shift by 12
3984 // The J constraint applies only to ADD or SUB immediates that would be
3985 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
3986 // instruction [or vice versa], in other words -1 to -4095 with optional
3987 // left shift by 12.
3989 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
3993 uint64_t NVal = -C->getSExtValue();
3994 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal))
3998 // The K and L constraints apply *only* to logical immediates, including
3999 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4000 // been removed and MOV should be used). So these constraints have to
4001 // distinguish between bit patterns that are valid 32-bit or 64-bit
4002 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4003 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4006 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4010 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4013 // The M and N constraints are a superset of K and L respectively, for use
4014 // with the MOV (immediate) alias. As well as the logical immediates they
4015 // also match 32 or 64-bit immediates that can be loaded either using a
4016 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4017 // (M) or 64-bit 0x1234000000000000 (N) etc.
4018 // As a note some of this code is liberally stolen from the asm parser.
4020 if (!isUInt<32>(CVal))
4022 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4024 if ((CVal & 0xFFFF) == CVal)
4026 if ((CVal & 0xFFFF0000ULL) == CVal)
4028 uint64_t NCVal = ~(uint32_t)CVal;
4029 if ((NCVal & 0xFFFFULL) == NCVal)
4031 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4036 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4038 if ((CVal & 0xFFFFULL) == CVal)
4040 if ((CVal & 0xFFFF0000ULL) == CVal)
4042 if ((CVal & 0xFFFF00000000ULL) == CVal)
4044 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4046 uint64_t NCVal = ~CVal;
4047 if ((NCVal & 0xFFFFULL) == NCVal)
4049 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4051 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4053 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4061 // All assembler immediates are 64-bit integers.
4062 Result = DAG.getTargetConstant(CVal, MVT::i64);
4066 if (Result.getNode()) {
4067 Ops.push_back(Result);
4071 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4074 //===----------------------------------------------------------------------===//
4075 // AArch64 Advanced SIMD Support
4076 //===----------------------------------------------------------------------===//
4078 /// WidenVector - Given a value in the V64 register class, produce the
4079 /// equivalent value in the V128 register class.
4080 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4081 EVT VT = V64Reg.getValueType();
4082 unsigned NarrowSize = VT.getVectorNumElements();
4083 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4084 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4087 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4088 V64Reg, DAG.getConstant(0, MVT::i32));
4091 /// getExtFactor - Determine the adjustment factor for the position when
4092 /// generating an "extract from vector registers" instruction.
4093 static unsigned getExtFactor(SDValue &V) {
4094 EVT EltType = V.getValueType().getVectorElementType();
4095 return EltType.getSizeInBits() / 8;
4098 /// NarrowVector - Given a value in the V128 register class, produce the
4099 /// equivalent value in the V64 register class.
4100 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4101 EVT VT = V128Reg.getValueType();
4102 unsigned WideSize = VT.getVectorNumElements();
4103 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4104 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4107 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4110 // Gather data to see if the operation can be modelled as a
4111 // shuffle in combination with VEXTs.
4112 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4113 SelectionDAG &DAG) const {
4114 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4116 EVT VT = Op.getValueType();
4117 unsigned NumElts = VT.getVectorNumElements();
4119 SmallVector<SDValue, 2> SourceVecs;
4120 SmallVector<unsigned, 2> MinElts;
4121 SmallVector<unsigned, 2> MaxElts;
4123 for (unsigned i = 0; i < NumElts; ++i) {
4124 SDValue V = Op.getOperand(i);
4125 if (V.getOpcode() == ISD::UNDEF)
4127 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4128 // A shuffle can only come from building a vector from various
4129 // elements of other vectors.
4133 // Record this extraction against the appropriate vector if possible...
4134 SDValue SourceVec = V.getOperand(0);
4135 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4136 bool FoundSource = false;
4137 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4138 if (SourceVecs[j] == SourceVec) {
4139 if (MinElts[j] > EltNo)
4141 if (MaxElts[j] < EltNo)
4148 // Or record a new source if not...
4150 SourceVecs.push_back(SourceVec);
4151 MinElts.push_back(EltNo);
4152 MaxElts.push_back(EltNo);
4156 // Currently only do something sane when at most two source vectors
4158 if (SourceVecs.size() > 2)
4161 SDValue ShuffleSrcs[2] = { DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4162 int VEXTOffsets[2] = { 0, 0 };
4163 int OffsetMultipliers[2] = { 1, 1 };
4165 // This loop extracts the usage patterns of the source vectors
4166 // and prepares appropriate SDValues for a shuffle if possible.
4167 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4168 unsigned NumSrcElts = SourceVecs[i].getValueType().getVectorNumElements();
4169 SDValue CurSource = SourceVecs[i];
4170 if (SourceVecs[i].getValueType().getVectorElementType() !=
4171 VT.getVectorElementType()) {
4172 // It may hit this case if SourceVecs[i] is AssertSext/AssertZext.
4173 // Then bitcast it to the vector which holds asserted element type,
4174 // and record the multiplier of element width between SourceVecs and
4175 // Build_vector which is needed to extract the correct lanes later.
4177 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4178 SourceVecs[i].getValueSizeInBits() /
4179 VT.getVectorElementType().getSizeInBits());
4181 CurSource = DAG.getNode(ISD::BITCAST, dl, CastVT, SourceVecs[i]);
4182 OffsetMultipliers[i] = CastVT.getVectorNumElements() / NumSrcElts;
4183 NumSrcElts *= OffsetMultipliers[i];
4184 MaxElts[i] *= OffsetMultipliers[i];
4185 MinElts[i] *= OffsetMultipliers[i];
4188 if (CurSource.getValueType() == VT) {
4189 // No VEXT necessary
4190 ShuffleSrcs[i] = CurSource;
4193 } else if (NumSrcElts < NumElts) {
4194 // We can pad out the smaller vector for free, so if it's part of a
4196 ShuffleSrcs[i] = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, CurSource,
4197 DAG.getUNDEF(CurSource.getValueType()));
4201 // Since only 64-bit and 128-bit vectors are legal on ARM and
4202 // we've eliminated the other cases...
4203 assert(NumSrcElts == 2 * NumElts &&
4204 "unexpected vector sizes in ReconstructShuffle");
4206 if (MaxElts[i] - MinElts[i] >= NumElts) {
4207 // Span too large for a VEXT to cope
4211 if (MinElts[i] >= NumElts) {
4212 // The extraction can just take the second half
4213 VEXTOffsets[i] = NumElts;
4214 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CurSource,
4215 DAG.getIntPtrConstant(NumElts));
4216 } else if (MaxElts[i] < NumElts) {
4217 // The extraction can just take the first half
4219 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CurSource,
4220 DAG.getIntPtrConstant(0));
4222 // An actual VEXT is needed
4223 VEXTOffsets[i] = MinElts[i];
4224 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CurSource,
4225 DAG.getIntPtrConstant(0));
4226 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CurSource,
4227 DAG.getIntPtrConstant(NumElts));
4228 unsigned Imm = VEXTOffsets[i] * getExtFactor(VEXTSrc1);
4229 ShuffleSrcs[i] = DAG.getNode(AArch64ISD::EXT, dl, VT, VEXTSrc1, VEXTSrc2,
4230 DAG.getConstant(Imm, MVT::i32));
4234 SmallVector<int, 8> Mask;
4236 for (unsigned i = 0; i < NumElts; ++i) {
4237 SDValue Entry = Op.getOperand(i);
4238 if (Entry.getOpcode() == ISD::UNDEF) {
4243 SDValue ExtractVec = Entry.getOperand(0);
4245 cast<ConstantSDNode>(Op.getOperand(i).getOperand(1))->getSExtValue();
4246 if (ExtractVec == SourceVecs[0]) {
4247 Mask.push_back(ExtractElt * OffsetMultipliers[0] - VEXTOffsets[0]);
4249 Mask.push_back(ExtractElt * OffsetMultipliers[1] + NumElts -
4254 // Final check before we try to produce nonsense...
4255 if (isShuffleMaskLegal(Mask, VT))
4256 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4262 // check if an EXT instruction can handle the shuffle mask when the
4263 // vector sources of the shuffle are the same.
4264 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4265 unsigned NumElts = VT.getVectorNumElements();
4267 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4273 // If this is a VEXT shuffle, the immediate value is the index of the first
4274 // element. The other shuffle indices must be the successive elements after
4276 unsigned ExpectedElt = Imm;
4277 for (unsigned i = 1; i < NumElts; ++i) {
4278 // Increment the expected index. If it wraps around, just follow it
4279 // back to index zero and keep going.
4281 if (ExpectedElt == NumElts)
4285 continue; // ignore UNDEF indices
4286 if (ExpectedElt != static_cast<unsigned>(M[i]))
4293 // check if an EXT instruction can handle the shuffle mask when the
4294 // vector sources of the shuffle are different.
4295 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4297 // Look for the first non-undef element.
4298 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4299 [](int Elt) {return Elt >= 0;});
4301 // Benefit form APInt to handle overflow when calculating expected element.
4302 unsigned NumElts = VT.getVectorNumElements();
4303 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4304 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4305 // The following shuffle indices must be the successive elements after the
4306 // first real element.
4307 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4308 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4309 if (FirstWrongElt != M.end())
4312 // The index of an EXT is the first element if it is not UNDEF.
4313 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4314 // value of the first element. E.g.
4315 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4316 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4317 // ExpectedElt is the last mask index plus 1.
4318 Imm = ExpectedElt.getZExtValue();
4320 // There are two difference cases requiring to reverse input vectors.
4321 // For example, for vector <4 x i32> we have the following cases,
4322 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4323 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4324 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4325 // to reverse two input vectors.
4334 /// isREVMask - Check if a vector shuffle corresponds to a REV
4335 /// instruction with the specified blocksize. (The order of the elements
4336 /// within each block of the vector is reversed.)
4337 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4338 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4339 "Only possible block sizes for REV are: 16, 32, 64");
4341 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4345 unsigned NumElts = VT.getVectorNumElements();
4346 unsigned BlockElts = M[0] + 1;
4347 // If the first shuffle index is UNDEF, be optimistic.
4349 BlockElts = BlockSize / EltSz;
4351 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4354 for (unsigned i = 0; i < NumElts; ++i) {
4356 continue; // ignore UNDEF indices
4357 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4364 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4365 unsigned NumElts = VT.getVectorNumElements();
4366 WhichResult = (M[0] == 0 ? 0 : 1);
4367 unsigned Idx = WhichResult * NumElts / 2;
4368 for (unsigned i = 0; i != NumElts; i += 2) {
4369 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4370 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4378 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4379 unsigned NumElts = VT.getVectorNumElements();
4380 WhichResult = (M[0] == 0 ? 0 : 1);
4381 for (unsigned i = 0; i != NumElts; ++i) {
4383 continue; // ignore UNDEF indices
4384 if ((unsigned)M[i] != 2 * i + WhichResult)
4391 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4392 unsigned NumElts = VT.getVectorNumElements();
4393 WhichResult = (M[0] == 0 ? 0 : 1);
4394 for (unsigned i = 0; i < NumElts; i += 2) {
4395 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4396 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4402 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4403 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4404 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4405 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4406 unsigned NumElts = VT.getVectorNumElements();
4407 WhichResult = (M[0] == 0 ? 0 : 1);
4408 unsigned Idx = WhichResult * NumElts / 2;
4409 for (unsigned i = 0; i != NumElts; i += 2) {
4410 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4411 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4419 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4420 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4421 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4422 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4423 unsigned Half = VT.getVectorNumElements() / 2;
4424 WhichResult = (M[0] == 0 ? 0 : 1);
4425 for (unsigned j = 0; j != 2; ++j) {
4426 unsigned Idx = WhichResult;
4427 for (unsigned i = 0; i != Half; ++i) {
4428 int MIdx = M[i + j * Half];
4429 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4438 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4439 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4440 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4441 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4442 unsigned NumElts = VT.getVectorNumElements();
4443 WhichResult = (M[0] == 0 ? 0 : 1);
4444 for (unsigned i = 0; i < NumElts; i += 2) {
4445 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4446 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4452 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4453 bool &DstIsLeft, int &Anomaly) {
4454 if (M.size() != static_cast<size_t>(NumInputElements))
4457 int NumLHSMatch = 0, NumRHSMatch = 0;
4458 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4460 for (int i = 0; i < NumInputElements; ++i) {
4470 LastLHSMismatch = i;
4472 if (M[i] == i + NumInputElements)
4475 LastRHSMismatch = i;
4478 if (NumLHSMatch == NumInputElements - 1) {
4480 Anomaly = LastLHSMismatch;
4482 } else if (NumRHSMatch == NumInputElements - 1) {
4484 Anomaly = LastRHSMismatch;
4491 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4492 if (VT.getSizeInBits() != 128)
4495 unsigned NumElts = VT.getVectorNumElements();
4497 for (int I = 0, E = NumElts / 2; I != E; I++) {
4502 int Offset = NumElts / 2;
4503 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4504 if (Mask[I] != I + SplitLHS * Offset)
4511 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4513 EVT VT = Op.getValueType();
4514 SDValue V0 = Op.getOperand(0);
4515 SDValue V1 = Op.getOperand(1);
4516 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4518 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4519 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4522 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4524 if (!isConcatMask(Mask, VT, SplitV0))
4527 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4528 VT.getVectorNumElements() / 2);
4530 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4531 DAG.getConstant(0, MVT::i64));
4533 if (V1.getValueType().getSizeInBits() == 128) {
4534 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4535 DAG.getConstant(0, MVT::i64));
4537 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4540 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4541 /// the specified operations to build the shuffle.
4542 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4543 SDValue RHS, SelectionDAG &DAG,
4545 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4546 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
4547 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
4550 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4559 OP_VUZPL, // VUZP, left result
4560 OP_VUZPR, // VUZP, right result
4561 OP_VZIPL, // VZIP, left result
4562 OP_VZIPR, // VZIP, right result
4563 OP_VTRNL, // VTRN, left result
4564 OP_VTRNR // VTRN, right result
4567 if (OpNum == OP_COPY) {
4568 if (LHSID == (1 * 9 + 2) * 9 + 3)
4570 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
4574 SDValue OpLHS, OpRHS;
4575 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4576 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4577 EVT VT = OpLHS.getValueType();
4581 llvm_unreachable("Unknown shuffle opcode!");
4583 // VREV divides the vector in half and swaps within the half.
4584 if (VT.getVectorElementType() == MVT::i32 ||
4585 VT.getVectorElementType() == MVT::f32)
4586 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
4587 // vrev <4 x i16> -> REV32
4588 if (VT.getVectorElementType() == MVT::i16)
4589 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
4590 // vrev <4 x i8> -> REV16
4591 assert(VT.getVectorElementType() == MVT::i8);
4592 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
4597 EVT EltTy = VT.getVectorElementType();
4599 if (EltTy == MVT::i8)
4600 Opcode = AArch64ISD::DUPLANE8;
4601 else if (EltTy == MVT::i16)
4602 Opcode = AArch64ISD::DUPLANE16;
4603 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
4604 Opcode = AArch64ISD::DUPLANE32;
4605 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
4606 Opcode = AArch64ISD::DUPLANE64;
4608 llvm_unreachable("Invalid vector element type?");
4610 if (VT.getSizeInBits() == 64)
4611 OpLHS = WidenVector(OpLHS, DAG);
4612 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64);
4613 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
4618 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
4619 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
4620 DAG.getConstant(Imm, MVT::i32));
4623 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
4626 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
4629 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
4632 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
4635 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
4638 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
4643 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
4644 SelectionDAG &DAG) {
4645 // Check to see if we can use the TBL instruction.
4646 SDValue V1 = Op.getOperand(0);
4647 SDValue V2 = Op.getOperand(1);
4650 EVT EltVT = Op.getValueType().getVectorElementType();
4651 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
4653 SmallVector<SDValue, 8> TBLMask;
4654 for (int Val : ShuffleMask) {
4655 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
4656 unsigned Offset = Byte + Val * BytesPerElt;
4657 TBLMask.push_back(DAG.getConstant(Offset, MVT::i32));
4661 MVT IndexVT = MVT::v8i8;
4662 unsigned IndexLen = 8;
4663 if (Op.getValueType().getSizeInBits() == 128) {
4664 IndexVT = MVT::v16i8;
4668 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
4669 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
4672 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
4674 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
4675 Shuffle = DAG.getNode(
4676 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4677 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
4678 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4679 makeArrayRef(TBLMask.data(), IndexLen)));
4681 if (IndexLen == 8) {
4682 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
4683 Shuffle = DAG.getNode(
4684 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4685 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
4686 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4687 makeArrayRef(TBLMask.data(), IndexLen)));
4689 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
4690 // cannot currently represent the register constraints on the input
4692 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
4693 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4694 // &TBLMask[0], IndexLen));
4695 Shuffle = DAG.getNode(
4696 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
4697 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
4698 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
4699 makeArrayRef(TBLMask.data(), IndexLen)));
4702 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
4705 static unsigned getDUPLANEOp(EVT EltType) {
4706 if (EltType == MVT::i8)
4707 return AArch64ISD::DUPLANE8;
4708 if (EltType == MVT::i16)
4709 return AArch64ISD::DUPLANE16;
4710 if (EltType == MVT::i32 || EltType == MVT::f32)
4711 return AArch64ISD::DUPLANE32;
4712 if (EltType == MVT::i64 || EltType == MVT::f64)
4713 return AArch64ISD::DUPLANE64;
4715 llvm_unreachable("Invalid vector element type?");
4718 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4719 SelectionDAG &DAG) const {
4721 EVT VT = Op.getValueType();
4723 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4725 // Convert shuffles that are directly supported on NEON to target-specific
4726 // DAG nodes, instead of keeping them as shuffles and matching them again
4727 // during code selection. This is more efficient and avoids the possibility
4728 // of inconsistencies between legalization and selection.
4729 ArrayRef<int> ShuffleMask = SVN->getMask();
4731 SDValue V1 = Op.getOperand(0);
4732 SDValue V2 = Op.getOperand(1);
4734 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
4735 V1.getValueType().getSimpleVT())) {
4736 int Lane = SVN->getSplatIndex();
4737 // If this is undef splat, generate it via "just" vdup, if possible.
4741 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
4742 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
4744 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
4745 // constant. If so, we can just reference the lane's definition directly.
4746 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
4747 !isa<ConstantSDNode>(V1.getOperand(Lane)))
4748 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
4750 // Otherwise, duplicate from the lane of the input vector.
4751 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
4753 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
4754 // to make a vector of the same size as this SHUFFLE. We can ignore the
4755 // extract entirely, and canonicalise the concat using WidenVector.
4756 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
4757 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
4758 V1 = V1.getOperand(0);
4759 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
4760 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
4761 Lane -= Idx * VT.getVectorNumElements() / 2;
4762 V1 = WidenVector(V1.getOperand(Idx), DAG);
4763 } else if (VT.getSizeInBits() == 64)
4764 V1 = WidenVector(V1, DAG);
4766 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64));
4769 if (isREVMask(ShuffleMask, VT, 64))
4770 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
4771 if (isREVMask(ShuffleMask, VT, 32))
4772 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
4773 if (isREVMask(ShuffleMask, VT, 16))
4774 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
4776 bool ReverseEXT = false;
4778 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
4781 Imm *= getExtFactor(V1);
4782 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
4783 DAG.getConstant(Imm, MVT::i32));
4784 } else if (V2->getOpcode() == ISD::UNDEF &&
4785 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
4786 Imm *= getExtFactor(V1);
4787 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
4788 DAG.getConstant(Imm, MVT::i32));
4791 unsigned WhichResult;
4792 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
4793 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
4794 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4796 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
4797 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
4798 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4800 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
4801 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
4802 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
4805 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4806 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
4807 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4809 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4810 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
4811 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4813 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
4814 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
4815 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
4818 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
4819 if (Concat.getNode())
4824 int NumInputElements = V1.getValueType().getVectorNumElements();
4825 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
4826 SDValue DstVec = DstIsLeft ? V1 : V2;
4827 SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64);
4829 SDValue SrcVec = V1;
4830 int SrcLane = ShuffleMask[Anomaly];
4831 if (SrcLane >= NumInputElements) {
4833 SrcLane -= VT.getVectorNumElements();
4835 SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64);
4837 EVT ScalarVT = VT.getVectorElementType();
4838 if (ScalarVT.getSizeInBits() < 32)
4839 ScalarVT = MVT::i32;
4842 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
4843 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
4847 // If the shuffle is not directly supported and it has 4 elements, use
4848 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4849 unsigned NumElts = VT.getVectorNumElements();
4851 unsigned PFIndexes[4];
4852 for (unsigned i = 0; i != 4; ++i) {
4853 if (ShuffleMask[i] < 0)
4856 PFIndexes[i] = ShuffleMask[i];
4859 // Compute the index in the perfect shuffle table.
4860 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
4861 PFIndexes[2] * 9 + PFIndexes[3];
4862 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4863 unsigned Cost = (PFEntry >> 30);
4866 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4869 return GenerateTBL(Op, ShuffleMask, DAG);
4872 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
4874 EVT VT = BVN->getValueType(0);
4875 APInt SplatBits, SplatUndef;
4876 unsigned SplatBitSize;
4878 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4879 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
4881 for (unsigned i = 0; i < NumSplats; ++i) {
4882 CnstBits <<= SplatBitSize;
4883 UndefBits <<= SplatBitSize;
4884 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
4885 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
4894 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
4895 SelectionDAG &DAG) const {
4896 BuildVectorSDNode *BVN =
4897 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
4898 SDValue LHS = Op.getOperand(0);
4900 EVT VT = Op.getValueType();
4905 APInt CnstBits(VT.getSizeInBits(), 0);
4906 APInt UndefBits(VT.getSizeInBits(), 0);
4907 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
4908 // We only have BIC vector immediate instruction, which is and-not.
4909 CnstBits = ~CnstBits;
4911 // We make use of a little bit of goto ickiness in order to avoid having to
4912 // duplicate the immediate matching logic for the undef toggled case.
4913 bool SecondTry = false;
4916 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
4917 CnstBits = CnstBits.zextOrTrunc(64);
4918 uint64_t CnstVal = CnstBits.getZExtValue();
4920 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
4921 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
4922 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4923 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4924 DAG.getConstant(CnstVal, MVT::i32),
4925 DAG.getConstant(0, MVT::i32));
4926 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4929 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
4930 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
4931 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4932 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4933 DAG.getConstant(CnstVal, MVT::i32),
4934 DAG.getConstant(8, MVT::i32));
4935 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4938 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
4939 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
4940 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4941 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4942 DAG.getConstant(CnstVal, MVT::i32),
4943 DAG.getConstant(16, MVT::i32));
4944 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4947 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
4948 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
4949 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
4950 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4951 DAG.getConstant(CnstVal, MVT::i32),
4952 DAG.getConstant(24, MVT::i32));
4953 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4956 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
4957 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
4958 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
4959 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4960 DAG.getConstant(CnstVal, MVT::i32),
4961 DAG.getConstant(0, MVT::i32));
4962 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4965 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
4966 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
4967 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
4968 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
4969 DAG.getConstant(CnstVal, MVT::i32),
4970 DAG.getConstant(8, MVT::i32));
4971 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
4978 CnstBits = ~UndefBits;
4982 // We can always fall back to a non-immediate AND.
4987 // Specialized code to quickly find if PotentialBVec is a BuildVector that
4988 // consists of only the same constant int value, returned in reference arg
4990 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
4991 uint64_t &ConstVal) {
4992 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
4995 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
4998 EVT VT = Bvec->getValueType(0);
4999 unsigned NumElts = VT.getVectorNumElements();
5000 for (unsigned i = 1; i < NumElts; ++i)
5001 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5003 ConstVal = FirstElt->getZExtValue();
5007 static unsigned getIntrinsicID(const SDNode *N) {
5008 unsigned Opcode = N->getOpcode();
5011 return Intrinsic::not_intrinsic;
5012 case ISD::INTRINSIC_WO_CHAIN: {
5013 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5014 if (IID < Intrinsic::num_intrinsics)
5016 return Intrinsic::not_intrinsic;
5021 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5022 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5023 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5024 // Also, logical shift right -> sri, with the same structure.
5025 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5026 EVT VT = N->getValueType(0);
5033 // Is the first op an AND?
5034 const SDValue And = N->getOperand(0);
5035 if (And.getOpcode() != ISD::AND)
5038 // Is the second op an shl or lshr?
5039 SDValue Shift = N->getOperand(1);
5040 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5041 // or AArch64ISD::VLSHR vector, #shift
5042 unsigned ShiftOpc = Shift.getOpcode();
5043 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5045 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5047 // Is the shift amount constant?
5048 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5052 // Is the and mask vector all constant?
5054 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5057 // Is C1 == ~C2, taking into account how much one can shift elements of a
5059 uint64_t C2 = C2node->getZExtValue();
5060 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5061 if (C2 > ElemSizeInBits)
5063 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5064 if ((C1 & ElemMask) != (~C2 & ElemMask))
5067 SDValue X = And.getOperand(0);
5068 SDValue Y = Shift.getOperand(0);
5071 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5073 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5074 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
5076 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5077 DEBUG(N->dump(&DAG));
5078 DEBUG(dbgs() << "into: \n");
5079 DEBUG(ResultSLI->dump(&DAG));
5085 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5086 SelectionDAG &DAG) const {
5087 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5088 if (EnableAArch64SlrGeneration) {
5089 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5094 BuildVectorSDNode *BVN =
5095 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5096 SDValue LHS = Op.getOperand(1);
5098 EVT VT = Op.getValueType();
5100 // OR commutes, so try swapping the operands.
5102 LHS = Op.getOperand(0);
5103 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5108 APInt CnstBits(VT.getSizeInBits(), 0);
5109 APInt UndefBits(VT.getSizeInBits(), 0);
5110 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5111 // We make use of a little bit of goto ickiness in order to avoid having to
5112 // duplicate the immediate matching logic for the undef toggled case.
5113 bool SecondTry = false;
5116 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5117 CnstBits = CnstBits.zextOrTrunc(64);
5118 uint64_t CnstVal = CnstBits.getZExtValue();
5120 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5121 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5122 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5123 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5124 DAG.getConstant(CnstVal, MVT::i32),
5125 DAG.getConstant(0, MVT::i32));
5126 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5129 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5130 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5131 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5132 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5133 DAG.getConstant(CnstVal, MVT::i32),
5134 DAG.getConstant(8, MVT::i32));
5135 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5138 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5139 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5140 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5141 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5142 DAG.getConstant(CnstVal, MVT::i32),
5143 DAG.getConstant(16, MVT::i32));
5144 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5147 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5148 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5149 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5150 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5151 DAG.getConstant(CnstVal, MVT::i32),
5152 DAG.getConstant(24, MVT::i32));
5153 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5156 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5157 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5158 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5159 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5160 DAG.getConstant(CnstVal, MVT::i32),
5161 DAG.getConstant(0, MVT::i32));
5162 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5165 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5166 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5167 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5168 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5169 DAG.getConstant(CnstVal, MVT::i32),
5170 DAG.getConstant(8, MVT::i32));
5171 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5178 CnstBits = UndefBits;
5182 // We can always fall back to a non-immediate OR.
5187 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5188 // be truncated to fit element width.
5189 static SDValue NormalizeBuildVector(SDValue Op,
5190 SelectionDAG &DAG) {
5191 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5193 EVT VT = Op.getValueType();
5194 EVT EltTy= VT.getVectorElementType();
5196 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5199 SmallVector<SDValue, 16> Ops;
5200 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
5201 SDValue Lane = Op.getOperand(I);
5202 if (Lane.getOpcode() == ISD::Constant) {
5203 APInt LowBits(EltTy.getSizeInBits(),
5204 cast<ConstantSDNode>(Lane)->getZExtValue());
5205 Lane = DAG.getConstant(LowBits.getZExtValue(), MVT::i32);
5207 Ops.push_back(Lane);
5209 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5212 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5213 SelectionDAG &DAG) const {
5215 EVT VT = Op.getValueType();
5216 Op = NormalizeBuildVector(Op, DAG);
5217 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5219 APInt CnstBits(VT.getSizeInBits(), 0);
5220 APInt UndefBits(VT.getSizeInBits(), 0);
5221 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5222 // We make use of a little bit of goto ickiness in order to avoid having to
5223 // duplicate the immediate matching logic for the undef toggled case.
5224 bool SecondTry = false;
5227 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5228 CnstBits = CnstBits.zextOrTrunc(64);
5229 uint64_t CnstVal = CnstBits.getZExtValue();
5231 // Certain magic vector constants (used to express things like NOT
5232 // and NEG) are passed through unmodified. This allows codegen patterns
5233 // for these operations to match. Special-purpose patterns will lower
5234 // these immediates to MOVIs if it proves necessary.
5235 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5238 // The many faces of MOVI...
5239 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5240 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5241 if (VT.getSizeInBits() == 128) {
5242 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5243 DAG.getConstant(CnstVal, MVT::i32));
5244 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5247 // Support the V64 version via subregister insertion.
5248 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5249 DAG.getConstant(CnstVal, MVT::i32));
5250 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5253 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5254 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5255 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5256 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5257 DAG.getConstant(CnstVal, MVT::i32),
5258 DAG.getConstant(0, MVT::i32));
5259 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5262 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5263 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5264 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5265 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5266 DAG.getConstant(CnstVal, MVT::i32),
5267 DAG.getConstant(8, MVT::i32));
5268 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5271 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5272 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5273 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5274 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5275 DAG.getConstant(CnstVal, MVT::i32),
5276 DAG.getConstant(16, MVT::i32));
5277 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5280 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5281 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5282 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5283 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5284 DAG.getConstant(CnstVal, MVT::i32),
5285 DAG.getConstant(24, MVT::i32));
5286 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5289 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5290 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5291 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5292 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5293 DAG.getConstant(CnstVal, MVT::i32),
5294 DAG.getConstant(0, MVT::i32));
5295 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5298 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5299 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5300 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5301 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5302 DAG.getConstant(CnstVal, MVT::i32),
5303 DAG.getConstant(8, MVT::i32));
5304 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5307 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5308 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5309 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5310 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5311 DAG.getConstant(CnstVal, MVT::i32),
5312 DAG.getConstant(264, MVT::i32));
5313 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5316 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5317 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5318 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5319 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5320 DAG.getConstant(CnstVal, MVT::i32),
5321 DAG.getConstant(272, MVT::i32));
5322 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5325 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5326 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5327 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5328 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5329 DAG.getConstant(CnstVal, MVT::i32));
5330 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5333 // The few faces of FMOV...
5334 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5335 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5336 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5337 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5338 DAG.getConstant(CnstVal, MVT::i32));
5339 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5342 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5343 VT.getSizeInBits() == 128) {
5344 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5345 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5346 DAG.getConstant(CnstVal, MVT::i32));
5347 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5350 // The many faces of MVNI...
5352 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5353 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5354 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5355 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5356 DAG.getConstant(CnstVal, MVT::i32),
5357 DAG.getConstant(0, MVT::i32));
5358 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5361 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5362 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5363 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5364 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5365 DAG.getConstant(CnstVal, MVT::i32),
5366 DAG.getConstant(8, MVT::i32));
5367 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5370 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5371 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5372 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5373 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5374 DAG.getConstant(CnstVal, MVT::i32),
5375 DAG.getConstant(16, MVT::i32));
5376 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5379 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5380 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5381 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5382 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5383 DAG.getConstant(CnstVal, MVT::i32),
5384 DAG.getConstant(24, MVT::i32));
5385 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5388 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5389 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5390 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5391 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5392 DAG.getConstant(CnstVal, MVT::i32),
5393 DAG.getConstant(0, MVT::i32));
5394 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5397 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5398 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5399 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5400 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5401 DAG.getConstant(CnstVal, MVT::i32),
5402 DAG.getConstant(8, MVT::i32));
5403 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5406 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5407 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5408 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5409 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5410 DAG.getConstant(CnstVal, MVT::i32),
5411 DAG.getConstant(264, MVT::i32));
5412 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5415 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5416 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5417 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5418 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5419 DAG.getConstant(CnstVal, MVT::i32),
5420 DAG.getConstant(272, MVT::i32));
5421 return DAG.getNode(ISD::BITCAST, dl, VT, Mov);
5428 CnstBits = UndefBits;
5433 // Scan through the operands to find some interesting properties we can
5435 // 1) If only one value is used, we can use a DUP, or
5436 // 2) if only the low element is not undef, we can just insert that, or
5437 // 3) if only one constant value is used (w/ some non-constant lanes),
5438 // we can splat the constant value into the whole vector then fill
5439 // in the non-constant lanes.
5440 // 4) FIXME: If different constant values are used, but we can intelligently
5441 // select the values we'll be overwriting for the non-constant
5442 // lanes such that we can directly materialize the vector
5443 // some other way (MOVI, e.g.), we can be sneaky.
5444 unsigned NumElts = VT.getVectorNumElements();
5445 bool isOnlyLowElement = true;
5446 bool usesOnlyOneValue = true;
5447 bool usesOnlyOneConstantValue = true;
5448 bool isConstant = true;
5449 unsigned NumConstantLanes = 0;
5451 SDValue ConstantValue;
5452 for (unsigned i = 0; i < NumElts; ++i) {
5453 SDValue V = Op.getOperand(i);
5454 if (V.getOpcode() == ISD::UNDEF)
5457 isOnlyLowElement = false;
5458 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5461 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5463 if (!ConstantValue.getNode())
5465 else if (ConstantValue != V)
5466 usesOnlyOneConstantValue = false;
5469 if (!Value.getNode())
5471 else if (V != Value)
5472 usesOnlyOneValue = false;
5475 if (!Value.getNode())
5476 return DAG.getUNDEF(VT);
5478 if (isOnlyLowElement)
5479 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5481 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5482 // i32 and try again.
5483 if (usesOnlyOneValue) {
5485 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5486 Value.getValueType() != VT)
5487 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5489 // This is actually a DUPLANExx operation, which keeps everything vectory.
5491 // DUPLANE works on 128-bit vectors, widen it if necessary.
5492 SDValue Lane = Value.getOperand(1);
5493 Value = Value.getOperand(0);
5494 if (Value.getValueType().getSizeInBits() == 64)
5495 Value = WidenVector(Value, DAG);
5497 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5498 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5501 if (VT.getVectorElementType().isFloatingPoint()) {
5502 SmallVector<SDValue, 8> Ops;
5504 (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
5505 for (unsigned i = 0; i < NumElts; ++i)
5506 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5507 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5508 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5509 Val = LowerBUILD_VECTOR(Val, DAG);
5511 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5515 // If there was only one constant value used and for more than one lane,
5516 // start by splatting that value, then replace the non-constant lanes. This
5517 // is better than the default, which will perform a separate initialization
5519 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5520 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5521 // Now insert the non-constant lanes.
5522 for (unsigned i = 0; i < NumElts; ++i) {
5523 SDValue V = Op.getOperand(i);
5524 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5525 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5526 // Note that type legalization likely mucked about with the VT of the
5527 // source operand, so we may have to convert it here before inserting.
5528 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5534 // If all elements are constants and the case above didn't get hit, fall back
5535 // to the default expansion, which will generate a load from the constant
5540 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5542 SDValue shuffle = ReconstructShuffle(Op, DAG);
5543 if (shuffle != SDValue())
5547 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5548 // know the default expansion would otherwise fall back on something even
5549 // worse. For a vector with one or two non-undef values, that's
5550 // scalar_to_vector for the elements followed by a shuffle (provided the
5551 // shuffle is valid for the target) and materialization element by element
5552 // on the stack followed by a load for everything else.
5553 if (!isConstant && !usesOnlyOneValue) {
5554 SDValue Vec = DAG.getUNDEF(VT);
5555 SDValue Op0 = Op.getOperand(0);
5556 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
5558 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
5559 // a) Avoid a RMW dependency on the full vector register, and
5560 // b) Allow the register coalescer to fold away the copy if the
5561 // value is already in an S or D register.
5562 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
5563 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
5565 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
5566 DAG.getTargetConstant(SubIdx, MVT::i32));
5567 Vec = SDValue(N, 0);
5570 for (; i < NumElts; ++i) {
5571 SDValue V = Op.getOperand(i);
5572 if (V.getOpcode() == ISD::UNDEF)
5574 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5575 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5580 // Just use the default expansion. We failed to find a better alternative.
5584 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
5585 SelectionDAG &DAG) const {
5586 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
5588 // Check for non-constant or out of range lane.
5589 EVT VT = Op.getOperand(0).getValueType();
5590 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
5591 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
5595 // Insertion/extraction are legal for V128 types.
5596 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5597 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64)
5600 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5601 VT != MVT::v1i64 && VT != MVT::v2f32)
5604 // For V64 types, we perform insertion by expanding the value
5605 // to a V128 type and perform the insertion on that.
5607 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5608 EVT WideTy = WideVec.getValueType();
5610 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
5611 Op.getOperand(1), Op.getOperand(2));
5612 // Re-narrow the resultant vector.
5613 return NarrowVector(Node, DAG);
5617 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5618 SelectionDAG &DAG) const {
5619 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
5621 // Check for non-constant or out of range lane.
5622 EVT VT = Op.getOperand(0).getValueType();
5623 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5624 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
5628 // Insertion/extraction are legal for V128 types.
5629 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
5630 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64)
5633 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
5634 VT != MVT::v1i64 && VT != MVT::v2f32)
5637 // For V64 types, we perform extraction by expanding the value
5638 // to a V128 type and perform the extraction on that.
5640 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
5641 EVT WideTy = WideVec.getValueType();
5643 EVT ExtrTy = WideTy.getVectorElementType();
5644 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
5647 // For extractions, we just return the result directly.
5648 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
5652 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
5653 SelectionDAG &DAG) const {
5654 EVT VT = Op.getOperand(0).getValueType();
5660 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5663 unsigned Val = Cst->getZExtValue();
5665 unsigned Size = Op.getValueType().getSizeInBits();
5669 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
5672 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
5675 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
5678 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
5681 llvm_unreachable("Unexpected vector type in extract_subvector!");
5684 // If this is extracting the upper 64-bits of a 128-bit vector, we match
5686 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
5692 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5694 if (VT.getVectorNumElements() == 4 &&
5695 (VT.is128BitVector() || VT.is64BitVector())) {
5696 unsigned PFIndexes[4];
5697 for (unsigned i = 0; i != 4; ++i) {
5701 PFIndexes[i] = M[i];
5704 // Compute the index in the perfect shuffle table.
5705 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5706 PFIndexes[2] * 9 + PFIndexes[3];
5707 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5708 unsigned Cost = (PFEntry >> 30);
5716 unsigned DummyUnsigned;
5718 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
5719 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
5720 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
5721 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
5722 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
5723 isZIPMask(M, VT, DummyUnsigned) ||
5724 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
5725 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
5726 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
5727 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
5728 isConcatMask(M, VT, VT.getSizeInBits() == 128));
5731 /// getVShiftImm - Check if this is a valid build_vector for the immediate
5732 /// operand of a vector shift operation, where all the elements of the
5733 /// build_vector must have the same constant integer value.
5734 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
5735 // Ignore bit_converts.
5736 while (Op.getOpcode() == ISD::BITCAST)
5737 Op = Op.getOperand(0);
5738 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5739 APInt SplatBits, SplatUndef;
5740 unsigned SplatBitSize;
5742 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
5743 HasAnyUndefs, ElementBits) ||
5744 SplatBitSize > ElementBits)
5746 Cnt = SplatBits.getSExtValue();
5750 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
5751 /// operand of a vector shift left operation. That value must be in the range:
5752 /// 0 <= Value < ElementBits for a left shift; or
5753 /// 0 <= Value <= ElementBits for a long left shift.
5754 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
5755 assert(VT.isVector() && "vector shift count is not a vector type");
5756 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5757 if (!getVShiftImm(Op, ElementBits, Cnt))
5759 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
5762 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
5763 /// operand of a vector shift right operation. For a shift opcode, the value
5764 /// is positive, but for an intrinsic the value count must be negative. The
5765 /// absolute value must be in the range:
5766 /// 1 <= |Value| <= ElementBits for a right shift; or
5767 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
5768 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
5770 assert(VT.isVector() && "vector shift count is not a vector type");
5771 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5772 if (!getVShiftImm(Op, ElementBits, Cnt))
5776 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
5779 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
5780 SelectionDAG &DAG) const {
5781 EVT VT = Op.getValueType();
5785 if (!Op.getOperand(1).getValueType().isVector())
5787 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5789 switch (Op.getOpcode()) {
5791 llvm_unreachable("unexpected shift opcode");
5794 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
5795 return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0),
5796 DAG.getConstant(Cnt, MVT::i32));
5797 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5798 DAG.getConstant(Intrinsic::aarch64_neon_ushl, MVT::i32),
5799 Op.getOperand(0), Op.getOperand(1));
5802 // Right shift immediate
5803 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
5806 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
5807 return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0),
5808 DAG.getConstant(Cnt, MVT::i32));
5811 // Right shift register. Note, there is not a shift right register
5812 // instruction, but the shift left register instruction takes a signed
5813 // value, where negative numbers specify a right shift.
5814 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
5815 : Intrinsic::aarch64_neon_ushl;
5816 // negate the shift amount
5817 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
5818 SDValue NegShiftLeft =
5819 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5820 DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift);
5821 return NegShiftLeft;
5827 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
5828 AArch64CC::CondCode CC, bool NoNans, EVT VT,
5829 SDLoc dl, SelectionDAG &DAG) {
5830 EVT SrcVT = LHS.getValueType();
5832 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
5833 APInt CnstBits(VT.getSizeInBits(), 0);
5834 APInt UndefBits(VT.getSizeInBits(), 0);
5835 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
5836 bool IsZero = IsCnst && (CnstBits == 0);
5838 if (SrcVT.getVectorElementType().isFloatingPoint()) {
5842 case AArch64CC::NE: {
5845 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
5847 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
5848 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
5852 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
5853 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
5856 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
5857 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
5860 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
5861 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
5864 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
5865 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
5869 // If we ignore NaNs then we can use to the MI implementation.
5873 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
5874 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
5881 case AArch64CC::NE: {
5884 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
5886 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
5887 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
5891 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
5892 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
5895 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
5896 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
5899 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
5900 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
5903 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
5904 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
5906 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
5908 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
5911 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
5912 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
5914 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
5916 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
5920 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
5921 SelectionDAG &DAG) const {
5922 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5923 SDValue LHS = Op.getOperand(0);
5924 SDValue RHS = Op.getOperand(1);
5927 if (LHS.getValueType().getVectorElementType().isInteger()) {
5928 assert(LHS.getValueType() == RHS.getValueType());
5929 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
5930 return EmitVectorComparison(LHS, RHS, AArch64CC, false, Op.getValueType(),
5934 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
5935 LHS.getValueType().getVectorElementType() == MVT::f64);
5937 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
5938 // clean. Some of them require two branches to implement.
5939 AArch64CC::CondCode CC1, CC2;
5941 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
5943 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
5945 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, Op.getValueType(), dl, DAG);
5949 if (CC2 != AArch64CC::AL) {
5951 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, Op.getValueType(), dl, DAG);
5952 if (!Cmp2.getNode())
5955 Cmp = DAG.getNode(ISD::OR, dl, Cmp.getValueType(), Cmp, Cmp2);
5959 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
5964 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
5965 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
5966 /// specified in the intrinsic calls.
5967 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5969 unsigned Intrinsic) const {
5970 switch (Intrinsic) {
5971 case Intrinsic::aarch64_neon_ld2:
5972 case Intrinsic::aarch64_neon_ld3:
5973 case Intrinsic::aarch64_neon_ld4:
5974 case Intrinsic::aarch64_neon_ld1x2:
5975 case Intrinsic::aarch64_neon_ld1x3:
5976 case Intrinsic::aarch64_neon_ld1x4:
5977 case Intrinsic::aarch64_neon_ld2lane:
5978 case Intrinsic::aarch64_neon_ld3lane:
5979 case Intrinsic::aarch64_neon_ld4lane:
5980 case Intrinsic::aarch64_neon_ld2r:
5981 case Intrinsic::aarch64_neon_ld3r:
5982 case Intrinsic::aarch64_neon_ld4r: {
5983 Info.opc = ISD::INTRINSIC_W_CHAIN;
5984 // Conservatively set memVT to the entire set of vectors loaded.
5985 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
5986 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5987 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
5990 Info.vol = false; // volatile loads with NEON intrinsics not supported
5991 Info.readMem = true;
5992 Info.writeMem = false;
5995 case Intrinsic::aarch64_neon_st2:
5996 case Intrinsic::aarch64_neon_st3:
5997 case Intrinsic::aarch64_neon_st4:
5998 case Intrinsic::aarch64_neon_st1x2:
5999 case Intrinsic::aarch64_neon_st1x3:
6000 case Intrinsic::aarch64_neon_st1x4:
6001 case Intrinsic::aarch64_neon_st2lane:
6002 case Intrinsic::aarch64_neon_st3lane:
6003 case Intrinsic::aarch64_neon_st4lane: {
6004 Info.opc = ISD::INTRINSIC_VOID;
6005 // Conservatively set memVT to the entire set of vectors stored.
6006 unsigned NumElts = 0;
6007 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6008 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6009 if (!ArgTy->isVectorTy())
6011 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
6013 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6014 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6017 Info.vol = false; // volatile stores with NEON intrinsics not supported
6018 Info.readMem = false;
6019 Info.writeMem = true;
6022 case Intrinsic::aarch64_ldaxr:
6023 case Intrinsic::aarch64_ldxr: {
6024 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6025 Info.opc = ISD::INTRINSIC_W_CHAIN;
6026 Info.memVT = MVT::getVT(PtrTy->getElementType());
6027 Info.ptrVal = I.getArgOperand(0);
6029 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6031 Info.readMem = true;
6032 Info.writeMem = false;
6035 case Intrinsic::aarch64_stlxr:
6036 case Intrinsic::aarch64_stxr: {
6037 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6038 Info.opc = ISD::INTRINSIC_W_CHAIN;
6039 Info.memVT = MVT::getVT(PtrTy->getElementType());
6040 Info.ptrVal = I.getArgOperand(1);
6042 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6044 Info.readMem = false;
6045 Info.writeMem = true;
6048 case Intrinsic::aarch64_ldaxp:
6049 case Intrinsic::aarch64_ldxp: {
6050 Info.opc = ISD::INTRINSIC_W_CHAIN;
6051 Info.memVT = MVT::i128;
6052 Info.ptrVal = I.getArgOperand(0);
6056 Info.readMem = true;
6057 Info.writeMem = false;
6060 case Intrinsic::aarch64_stlxp:
6061 case Intrinsic::aarch64_stxp: {
6062 Info.opc = ISD::INTRINSIC_W_CHAIN;
6063 Info.memVT = MVT::i128;
6064 Info.ptrVal = I.getArgOperand(2);
6068 Info.readMem = false;
6069 Info.writeMem = true;
6079 // Truncations from 64-bit GPR to 32-bit GPR is free.
6080 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6081 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6083 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6084 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6085 return NumBits1 > NumBits2;
6087 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6088 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6090 unsigned NumBits1 = VT1.getSizeInBits();
6091 unsigned NumBits2 = VT2.getSizeInBits();
6092 return NumBits1 > NumBits2;
6095 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6097 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6098 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6100 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6101 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6102 return NumBits1 == 32 && NumBits2 == 64;
6104 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6105 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6107 unsigned NumBits1 = VT1.getSizeInBits();
6108 unsigned NumBits2 = VT2.getSizeInBits();
6109 return NumBits1 == 32 && NumBits2 == 64;
6112 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6113 EVT VT1 = Val.getValueType();
6114 if (isZExtFree(VT1, VT2)) {
6118 if (Val.getOpcode() != ISD::LOAD)
6121 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6122 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6123 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6124 VT1.getSizeInBits() <= 32);
6127 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6128 unsigned &RequiredAligment) const {
6129 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6131 // Cyclone supports unaligned accesses.
6132 RequiredAligment = 0;
6133 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6134 return NumBits == 32 || NumBits == 64;
6137 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6138 unsigned &RequiredAligment) const {
6139 if (!LoadedType.isSimple() ||
6140 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6142 // Cyclone supports unaligned accesses.
6143 RequiredAligment = 0;
6144 unsigned NumBits = LoadedType.getSizeInBits();
6145 return NumBits == 32 || NumBits == 64;
6148 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6149 unsigned AlignCheck) {
6150 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6151 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6154 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6155 unsigned SrcAlign, bool IsMemset,
6158 MachineFunction &MF) const {
6159 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6160 // instruction to materialize the v2i64 zero and one store (with restrictive
6161 // addressing mode). Just do two i64 store of zero-registers.
6163 const Function *F = MF.getFunction();
6164 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6165 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
6166 Attribute::NoImplicitFloat) &&
6167 (memOpAlign(SrcAlign, DstAlign, 16) ||
6168 (allowsUnalignedMemoryAccesses(MVT::f128, 0, &Fast) && Fast)))
6171 return Size >= 8 ? MVT::i64 : MVT::i32;
6174 // 12-bit optionally shifted immediates are legal for adds.
6175 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6176 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6181 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6182 // immediates is the same as for an add or a sub.
6183 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6186 return isLegalAddImmediate(Immed);
6189 /// isLegalAddressingMode - Return true if the addressing mode represented
6190 /// by AM is legal for this target, for a load/store of the specified type.
6191 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6193 // AArch64 has five basic addressing modes:
6195 // reg + 9-bit signed offset
6196 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6198 // reg + SIZE_IN_BYTES * reg
6200 // No global is ever allowed as a base.
6204 // No reg+reg+imm addressing.
6205 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6208 // check reg + imm case:
6209 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6210 uint64_t NumBytes = 0;
6211 if (Ty->isSized()) {
6212 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6213 NumBytes = NumBits / 8;
6214 if (!isPowerOf2_64(NumBits))
6219 int64_t Offset = AM.BaseOffs;
6221 // 9-bit signed offset
6222 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6225 // 12-bit unsigned offset
6226 unsigned shift = Log2_64(NumBytes);
6227 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6228 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6229 (Offset >> shift) << shift == Offset)
6234 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6236 if (!AM.Scale || AM.Scale == 1 ||
6237 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6242 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6244 // Scaling factors are not free at all.
6245 // Operands | Rt Latency
6246 // -------------------------------------------
6248 // -------------------------------------------
6249 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6250 // Rt, [Xn, Wm, <extend> #imm] |
6251 if (isLegalAddressingMode(AM, Ty))
6252 // Scale represents reg2 * scale, thus account for 1 if
6253 // it is not equal to 0 or 1.
6254 return AM.Scale != 0 && AM.Scale != 1;
6258 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6259 VT = VT.getScalarType();
6264 switch (VT.getSimpleVT().SimpleTy) {
6276 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6277 // LR is a callee-save register, but we must treat it as clobbered by any call
6278 // site. Hence we include LR in the scratch registers, which are in turn added
6279 // as implicit-defs for stackmaps and patchpoints.
6280 static const MCPhysReg ScratchRegs[] = {
6281 AArch64::X16, AArch64::X17, AArch64::LR, 0
6287 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6288 EVT VT = N->getValueType(0);
6289 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6290 // it with shift to let it be lowered to UBFX.
6291 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6292 isa<ConstantSDNode>(N->getOperand(1))) {
6293 uint64_t TruncMask = N->getConstantOperandVal(1);
6294 if (isMask_64(TruncMask) &&
6295 N->getOperand(0).getOpcode() == ISD::SRL &&
6296 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6302 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
6304 assert(Ty->isIntegerTy());
6306 unsigned BitSize = Ty->getPrimitiveSizeInBits();
6310 int64_t Val = Imm.getSExtValue();
6311 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
6314 if ((int64_t)Val < 0)
6317 Val &= (1LL << 32) - 1;
6319 unsigned LZ = countLeadingZeros((uint64_t)Val);
6320 unsigned Shift = (63 - LZ) / 16;
6321 // MOVZ is free so return true for one or fewer MOVK.
6322 return (Shift < 3) ? true : false;
6325 // Generate SUBS and CSEL for integer abs.
6326 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
6327 EVT VT = N->getValueType(0);
6329 SDValue N0 = N->getOperand(0);
6330 SDValue N1 = N->getOperand(1);
6333 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
6334 // and change it to SUB and CSEL.
6335 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
6336 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6337 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6338 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6339 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
6340 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
6342 // Generate SUBS & CSEL.
6344 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
6345 N0.getOperand(0), DAG.getConstant(0, VT));
6346 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6347 DAG.getConstant(AArch64CC::PL, MVT::i32),
6348 SDValue(Cmp.getNode(), 1));
6353 // performXorCombine - Attempts to handle integer ABS.
6354 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
6355 TargetLowering::DAGCombinerInfo &DCI,
6356 const AArch64Subtarget *Subtarget) {
6357 if (DCI.isBeforeLegalizeOps())
6360 return performIntegerAbsCombine(N, DAG);
6363 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
6364 TargetLowering::DAGCombinerInfo &DCI,
6365 const AArch64Subtarget *Subtarget) {
6366 if (DCI.isBeforeLegalizeOps())
6369 // Multiplication of a power of two plus/minus one can be done more
6370 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6371 // future CPUs have a cheaper MADD instruction, this may need to be
6372 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
6373 // 64-bit is 5 cycles, so this is always a win.
6374 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6375 APInt Value = C->getAPIntValue();
6376 EVT VT = N->getValueType(0);
6377 if (Value.isNonNegative()) {
6378 // (mul x, 2^N + 1) => (add (shl x, N), x)
6379 APInt VM1 = Value - 1;
6380 if (VM1.isPowerOf2()) {
6381 SDValue ShiftedVal =
6382 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6383 DAG.getConstant(VM1.logBase2(), MVT::i64));
6384 return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal,
6387 // (mul x, 2^N - 1) => (sub (shl x, N), x)
6388 APInt VP1 = Value + 1;
6389 if (VP1.isPowerOf2()) {
6390 SDValue ShiftedVal =
6391 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6392 DAG.getConstant(VP1.logBase2(), MVT::i64));
6393 return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal,
6397 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
6398 APInt VNM1 = -Value - 1;
6399 if (VNM1.isPowerOf2()) {
6400 SDValue ShiftedVal =
6401 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6402 DAG.getConstant(VNM1.logBase2(), MVT::i64));
6404 DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
6405 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), Add);
6407 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
6408 APInt VNP1 = -Value + 1;
6409 if (VNP1.isPowerOf2()) {
6410 SDValue ShiftedVal =
6411 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6412 DAG.getConstant(VNP1.logBase2(), MVT::i64));
6413 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0),
6421 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
6422 SelectionDAG &DAG) {
6423 // Take advantage of vector comparisons producing 0 or -1 in each lane to
6424 // optimize away operation when it's from a constant.
6426 // The general transformation is:
6427 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
6428 // AND(VECTOR_CMP(x,y), constant2)
6429 // constant2 = UNARYOP(constant)
6431 // Early exit if this isn't a vector operation or if the operand of the
6432 // unary operation isn't a bitwise AND.
6433 EVT VT = N->getValueType(0);
6434 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
6435 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC)
6438 // Now check that the other operand of the AND is a constant splat. We could
6439 // make the transformation for non-constant splats as well, but it's unclear
6440 // that would be a benefit as it would not eliminate any operations, just
6441 // perform one more step in scalar code before moving to the vector unit.
6442 if (BuildVectorSDNode *BV =
6443 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
6444 // Bail out if the vector isn't a constant splat.
6445 if (!BV->getConstantSplatNode())
6448 // Everything checks out. Build up the new and improved node.
6450 EVT IntVT = BV->getValueType(0);
6451 // Create a new constant of the appropriate type for the transformed
6453 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
6454 // The AND node needs bitcasts to/from an integer vector type around it.
6455 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
6456 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
6457 N->getOperand(0)->getOperand(0), MaskConst);
6458 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
6465 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG) {
6466 // First try to optimize away the conversion when it's conditionally from
6467 // a constant. Vectors only.
6468 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
6469 if (Res != SDValue())
6472 EVT VT = N->getValueType(0);
6473 if (VT != MVT::f32 && VT != MVT::f64)
6476 // Only optimize when the source and destination types have the same width.
6477 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
6480 // If the result of an integer load is only used by an integer-to-float
6481 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
6482 // This eliminates an "integer-to-vector-move UOP and improve throughput.
6483 SDValue N0 = N->getOperand(0);
6484 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6485 // Do not change the width of a volatile load.
6486 !cast<LoadSDNode>(N0)->isVolatile()) {
6487 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6488 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
6489 LN0->getPointerInfo(), LN0->isVolatile(),
6490 LN0->isNonTemporal(), LN0->isInvariant(),
6491 LN0->getAlignment());
6493 // Make sure successors of the original load stay after it by updating them
6494 // to use the new Chain.
6495 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
6498 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
6499 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
6505 /// An EXTR instruction is made up of two shifts, ORed together. This helper
6506 /// searches for and classifies those shifts.
6507 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
6509 if (N.getOpcode() == ISD::SHL)
6511 else if (N.getOpcode() == ISD::SRL)
6516 if (!isa<ConstantSDNode>(N.getOperand(1)))
6519 ShiftAmount = N->getConstantOperandVal(1);
6520 Src = N->getOperand(0);
6524 /// EXTR instruction extracts a contiguous chunk of bits from two existing
6525 /// registers viewed as a high/low pair. This function looks for the pattern:
6526 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
6527 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
6529 static SDValue tryCombineToEXTR(SDNode *N,
6530 TargetLowering::DAGCombinerInfo &DCI) {
6531 SelectionDAG &DAG = DCI.DAG;
6533 EVT VT = N->getValueType(0);
6535 assert(N->getOpcode() == ISD::OR && "Unexpected root");
6537 if (VT != MVT::i32 && VT != MVT::i64)
6541 uint32_t ShiftLHS = 0;
6543 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
6547 uint32_t ShiftRHS = 0;
6549 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
6552 // If they're both trying to come from the high part of the register, they're
6553 // not really an EXTR.
6554 if (LHSFromHi == RHSFromHi)
6557 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
6561 std::swap(LHS, RHS);
6562 std::swap(ShiftLHS, ShiftRHS);
6565 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
6566 DAG.getConstant(ShiftRHS, MVT::i64));
6569 static SDValue tryCombineToBSL(SDNode *N,
6570 TargetLowering::DAGCombinerInfo &DCI) {
6571 EVT VT = N->getValueType(0);
6572 SelectionDAG &DAG = DCI.DAG;
6578 SDValue N0 = N->getOperand(0);
6579 if (N0.getOpcode() != ISD::AND)
6582 SDValue N1 = N->getOperand(1);
6583 if (N1.getOpcode() != ISD::AND)
6586 // We only have to look for constant vectors here since the general, variable
6587 // case can be handled in TableGen.
6588 unsigned Bits = VT.getVectorElementType().getSizeInBits();
6589 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
6590 for (int i = 1; i >= 0; --i)
6591 for (int j = 1; j >= 0; --j) {
6592 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
6593 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
6597 bool FoundMatch = true;
6598 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
6599 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
6600 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
6602 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
6609 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
6610 N0->getOperand(1 - i), N1->getOperand(1 - j));
6616 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
6617 const AArch64Subtarget *Subtarget) {
6618 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
6619 if (!EnableAArch64ExtrGeneration)
6621 SelectionDAG &DAG = DCI.DAG;
6622 EVT VT = N->getValueType(0);
6624 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
6627 SDValue Res = tryCombineToEXTR(N, DCI);
6631 Res = tryCombineToBSL(N, DCI);
6638 static SDValue performBitcastCombine(SDNode *N,
6639 TargetLowering::DAGCombinerInfo &DCI,
6640 SelectionDAG &DAG) {
6641 // Wait 'til after everything is legalized to try this. That way we have
6642 // legal vector types and such.
6643 if (DCI.isBeforeLegalizeOps())
6646 // Remove extraneous bitcasts around an extract_subvector.
6648 // (v4i16 (bitconvert
6649 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
6651 // (extract_subvector ((v8i16 ...), (i64 4)))
6653 // Only interested in 64-bit vectors as the ultimate result.
6654 EVT VT = N->getValueType(0);
6657 if (VT.getSimpleVT().getSizeInBits() != 64)
6659 // Is the operand an extract_subvector starting at the beginning or halfway
6660 // point of the vector? A low half may also come through as an
6661 // EXTRACT_SUBREG, so look for that, too.
6662 SDValue Op0 = N->getOperand(0);
6663 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
6664 !(Op0->isMachineOpcode() &&
6665 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
6667 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
6668 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
6669 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
6671 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
6672 if (idx != AArch64::dsub)
6674 // The dsub reference is equivalent to a lane zero subvector reference.
6677 // Look through the bitcast of the input to the extract.
6678 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
6680 SDValue Source = Op0->getOperand(0)->getOperand(0);
6681 // If the source type has twice the number of elements as our destination
6682 // type, we know this is an extract of the high or low half of the vector.
6683 EVT SVT = Source->getValueType(0);
6684 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
6687 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
6689 // Create the simplified form to just extract the low or high half of the
6690 // vector directly rather than bothering with the bitcasts.
6692 unsigned NumElements = VT.getVectorNumElements();
6694 SDValue HalfIdx = DAG.getConstant(NumElements, MVT::i64);
6695 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
6697 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32);
6698 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
6704 static SDValue performConcatVectorsCombine(SDNode *N,
6705 TargetLowering::DAGCombinerInfo &DCI,
6706 SelectionDAG &DAG) {
6707 // Wait 'til after everything is legalized to try this. That way we have
6708 // legal vector types and such.
6709 if (DCI.isBeforeLegalizeOps())
6713 EVT VT = N->getValueType(0);
6715 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
6716 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
6717 // canonicalise to that.
6718 if (N->getOperand(0) == N->getOperand(1) && VT.getVectorNumElements() == 2) {
6719 assert(VT.getVectorElementType().getSizeInBits() == 64);
6720 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT,
6721 WidenVector(N->getOperand(0), DAG),
6722 DAG.getConstant(0, MVT::i64));
6725 // Canonicalise concat_vectors so that the right-hand vector has as few
6726 // bit-casts as possible before its real operation. The primary matching
6727 // destination for these operations will be the narrowing "2" instructions,
6728 // which depend on the operation being performed on this right-hand vector.
6730 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
6732 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
6734 SDValue Op1 = N->getOperand(1);
6735 if (Op1->getOpcode() != ISD::BITCAST)
6737 SDValue RHS = Op1->getOperand(0);
6738 MVT RHSTy = RHS.getValueType().getSimpleVT();
6739 // If the RHS is not a vector, this is not the pattern we're looking for.
6740 if (!RHSTy.isVector())
6743 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
6745 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
6746 RHSTy.getVectorNumElements() * 2);
6748 ISD::BITCAST, dl, VT,
6749 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
6750 DAG.getNode(ISD::BITCAST, dl, RHSTy, N->getOperand(0)), RHS));
6753 static SDValue tryCombineFixedPointConvert(SDNode *N,
6754 TargetLowering::DAGCombinerInfo &DCI,
6755 SelectionDAG &DAG) {
6756 // Wait 'til after everything is legalized to try this. That way we have
6757 // legal vector types and such.
6758 if (DCI.isBeforeLegalizeOps())
6760 // Transform a scalar conversion of a value from a lane extract into a
6761 // lane extract of a vector conversion. E.g., from foo1 to foo2:
6762 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
6763 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
6765 // The second form interacts better with instruction selection and the
6766 // register allocator to avoid cross-class register copies that aren't
6767 // coalescable due to a lane reference.
6769 // Check the operand and see if it originates from a lane extract.
6770 SDValue Op1 = N->getOperand(1);
6771 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6772 // Yep, no additional predication needed. Perform the transform.
6773 SDValue IID = N->getOperand(0);
6774 SDValue Shift = N->getOperand(2);
6775 SDValue Vec = Op1.getOperand(0);
6776 SDValue Lane = Op1.getOperand(1);
6777 EVT ResTy = N->getValueType(0);
6781 // The vector width should be 128 bits by the time we get here, even
6782 // if it started as 64 bits (the extract_vector handling will have
6784 assert(Vec.getValueType().getSizeInBits() == 128 &&
6785 "unexpected vector size on extract_vector_elt!");
6786 if (Vec.getValueType() == MVT::v4i32)
6787 VecResTy = MVT::v4f32;
6788 else if (Vec.getValueType() == MVT::v2i64)
6789 VecResTy = MVT::v2f64;
6791 llvm_unreachable("unexpected vector type!");
6794 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
6795 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
6800 // AArch64 high-vector "long" operations are formed by performing the non-high
6801 // version on an extract_subvector of each operand which gets the high half:
6803 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
6805 // However, there are cases which don't have an extract_high explicitly, but
6806 // have another operation that can be made compatible with one for free. For
6809 // (dupv64 scalar) --> (extract_high (dup128 scalar))
6811 // This routine does the actual conversion of such DUPs, once outer routines
6812 // have determined that everything else is in order.
6813 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
6814 // We can handle most types of duplicate, but the lane ones have an extra
6815 // operand saying *which* lane, so we need to know.
6817 switch (N.getOpcode()) {
6818 case AArch64ISD::DUP:
6821 case AArch64ISD::DUPLANE8:
6822 case AArch64ISD::DUPLANE16:
6823 case AArch64ISD::DUPLANE32:
6824 case AArch64ISD::DUPLANE64:
6831 MVT NarrowTy = N.getSimpleValueType();
6832 if (!NarrowTy.is64BitVector())
6835 MVT ElementTy = NarrowTy.getVectorElementType();
6836 unsigned NumElems = NarrowTy.getVectorNumElements();
6837 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
6841 NewDUP = DAG.getNode(N.getOpcode(), SDLoc(N), NewDUPVT, N.getOperand(0),
6844 NewDUP = DAG.getNode(AArch64ISD::DUP, SDLoc(N), NewDUPVT, N.getOperand(0));
6846 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N.getNode()), NarrowTy,
6847 NewDUP, DAG.getConstant(NumElems, MVT::i64));
6850 static bool isEssentiallyExtractSubvector(SDValue N) {
6851 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
6854 return N.getOpcode() == ISD::BITCAST &&
6855 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
6858 /// \brief Helper structure to keep track of ISD::SET_CC operands.
6859 struct GenericSetCCInfo {
6860 const SDValue *Opnd0;
6861 const SDValue *Opnd1;
6865 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
6866 struct AArch64SetCCInfo {
6868 AArch64CC::CondCode CC;
6871 /// \brief Helper structure to keep track of SetCC information.
6873 GenericSetCCInfo Generic;
6874 AArch64SetCCInfo AArch64;
6877 /// \brief Helper structure to be able to read SetCC information. If set to
6878 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
6879 /// GenericSetCCInfo.
6880 struct SetCCInfoAndKind {
6885 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
6887 /// AArch64 lowered one.
6888 /// \p SetCCInfo is filled accordingly.
6889 /// \post SetCCInfo is meanginfull only when this function returns true.
6890 /// \return True when Op is a kind of SET_CC operation.
6891 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
6892 // If this is a setcc, this is straight forward.
6893 if (Op.getOpcode() == ISD::SETCC) {
6894 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
6895 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
6896 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6897 SetCCInfo.IsAArch64 = false;
6900 // Otherwise, check if this is a matching csel instruction.
6904 if (Op.getOpcode() != AArch64ISD::CSEL)
6906 // Set the information about the operands.
6907 // TODO: we want the operands of the Cmp not the csel
6908 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
6909 SetCCInfo.IsAArch64 = true;
6910 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
6911 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
6913 // Check that the operands matches the constraints:
6914 // (1) Both operands must be constants.
6915 // (2) One must be 1 and the other must be 0.
6916 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
6917 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6920 if (!TValue || !FValue)
6924 if (!TValue->isOne()) {
6925 // Update the comparison when we are interested in !cc.
6926 std::swap(TValue, FValue);
6927 SetCCInfo.Info.AArch64.CC =
6928 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
6930 return TValue->isOne() && FValue->isNullValue();
6933 // Returns true if Op is setcc or zext of setcc.
6934 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
6935 if (isSetCC(Op, Info))
6937 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
6938 isSetCC(Op->getOperand(0), Info));
6941 // The folding we want to perform is:
6942 // (add x, [zext] (setcc cc ...) )
6944 // (csel x, (add x, 1), !cc ...)
6946 // The latter will get matched to a CSINC instruction.
6947 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
6948 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
6949 SDValue LHS = Op->getOperand(0);
6950 SDValue RHS = Op->getOperand(1);
6951 SetCCInfoAndKind InfoAndKind;
6953 // If neither operand is a SET_CC, give up.
6954 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
6955 std::swap(LHS, RHS);
6956 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
6960 // FIXME: This could be generatized to work for FP comparisons.
6961 EVT CmpVT = InfoAndKind.IsAArch64
6962 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
6963 : InfoAndKind.Info.Generic.Opnd0->getValueType();
6964 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
6970 if (InfoAndKind.IsAArch64) {
6971 CCVal = DAG.getConstant(
6972 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), MVT::i32);
6973 Cmp = *InfoAndKind.Info.AArch64.Cmp;
6975 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
6976 *InfoAndKind.Info.Generic.Opnd1,
6977 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
6980 EVT VT = Op->getValueType(0);
6981 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, VT));
6982 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
6985 // The basic add/sub long vector instructions have variants with "2" on the end
6986 // which act on the high-half of their inputs. They are normally matched by
6989 // (add (zeroext (extract_high LHS)),
6990 // (zeroext (extract_high RHS)))
6991 // -> uaddl2 vD, vN, vM
6993 // However, if one of the extracts is something like a duplicate, this
6994 // instruction can still be used profitably. This function puts the DAG into a
6995 // more appropriate form for those patterns to trigger.
6996 static SDValue performAddSubLongCombine(SDNode *N,
6997 TargetLowering::DAGCombinerInfo &DCI,
6998 SelectionDAG &DAG) {
6999 if (DCI.isBeforeLegalizeOps())
7002 MVT VT = N->getSimpleValueType(0);
7003 if (!VT.is128BitVector()) {
7004 if (N->getOpcode() == ISD::ADD)
7005 return performSetccAddFolding(N, DAG);
7009 // Make sure both branches are extended in the same way.
7010 SDValue LHS = N->getOperand(0);
7011 SDValue RHS = N->getOperand(1);
7012 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
7013 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
7014 LHS.getOpcode() != RHS.getOpcode())
7017 unsigned ExtType = LHS.getOpcode();
7019 // It's not worth doing if at least one of the inputs isn't already an
7020 // extract, but we don't know which it'll be so we have to try both.
7021 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
7022 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
7026 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
7027 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
7028 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
7032 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
7035 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
7038 // Massage DAGs which we can use the high-half "long" operations on into
7039 // something isel will recognize better. E.g.
7041 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
7042 // (aarch64_neon_umull (extract_high (v2i64 vec)))
7043 // (extract_high (v2i64 (dup128 scalar)))))
7045 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
7046 TargetLowering::DAGCombinerInfo &DCI,
7047 SelectionDAG &DAG) {
7048 if (DCI.isBeforeLegalizeOps())
7051 SDValue LHS = N->getOperand(1);
7052 SDValue RHS = N->getOperand(2);
7053 assert(LHS.getValueType().is64BitVector() &&
7054 RHS.getValueType().is64BitVector() &&
7055 "unexpected shape for long operation");
7057 // Either node could be a DUP, but it's not worth doing both of them (you'd
7058 // just as well use the non-high version) so look for a corresponding extract
7059 // operation on the other "wing".
7060 if (isEssentiallyExtractSubvector(LHS)) {
7061 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
7064 } else if (isEssentiallyExtractSubvector(RHS)) {
7065 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
7070 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
7071 N->getOperand(0), LHS, RHS);
7074 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
7075 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
7076 unsigned ElemBits = ElemTy.getSizeInBits();
7078 int64_t ShiftAmount;
7079 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
7080 APInt SplatValue, SplatUndef;
7081 unsigned SplatBitSize;
7083 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
7084 HasAnyUndefs, ElemBits) ||
7085 SplatBitSize != ElemBits)
7088 ShiftAmount = SplatValue.getSExtValue();
7089 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
7090 ShiftAmount = CVN->getSExtValue();
7098 llvm_unreachable("Unknown shift intrinsic");
7099 case Intrinsic::aarch64_neon_sqshl:
7100 Opcode = AArch64ISD::SQSHL_I;
7101 IsRightShift = false;
7103 case Intrinsic::aarch64_neon_uqshl:
7104 Opcode = AArch64ISD::UQSHL_I;
7105 IsRightShift = false;
7107 case Intrinsic::aarch64_neon_srshl:
7108 Opcode = AArch64ISD::SRSHR_I;
7109 IsRightShift = true;
7111 case Intrinsic::aarch64_neon_urshl:
7112 Opcode = AArch64ISD::URSHR_I;
7113 IsRightShift = true;
7115 case Intrinsic::aarch64_neon_sqshlu:
7116 Opcode = AArch64ISD::SQSHLU_I;
7117 IsRightShift = false;
7121 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
7122 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7123 DAG.getConstant(-ShiftAmount, MVT::i32));
7124 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits)
7125 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7126 DAG.getConstant(ShiftAmount, MVT::i32));
7131 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7132 // the intrinsics must be legal and take an i32, this means there's almost
7133 // certainly going to be a zext in the DAG which we can eliminate.
7134 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7135 SDValue AndN = N->getOperand(2);
7136 if (AndN.getOpcode() != ISD::AND)
7139 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7140 if (!CMask || CMask->getZExtValue() != Mask)
7143 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7144 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7147 static SDValue performIntrinsicCombine(SDNode *N,
7148 TargetLowering::DAGCombinerInfo &DCI,
7149 const AArch64Subtarget *Subtarget) {
7150 SelectionDAG &DAG = DCI.DAG;
7151 unsigned IID = getIntrinsicID(N);
7155 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7156 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7157 return tryCombineFixedPointConvert(N, DCI, DAG);
7159 case Intrinsic::aarch64_neon_fmax:
7160 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7161 N->getOperand(1), N->getOperand(2));
7162 case Intrinsic::aarch64_neon_fmin:
7163 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7164 N->getOperand(1), N->getOperand(2));
7165 case Intrinsic::aarch64_neon_smull:
7166 case Intrinsic::aarch64_neon_umull:
7167 case Intrinsic::aarch64_neon_pmull:
7168 case Intrinsic::aarch64_neon_sqdmull:
7169 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7170 case Intrinsic::aarch64_neon_sqshl:
7171 case Intrinsic::aarch64_neon_uqshl:
7172 case Intrinsic::aarch64_neon_sqshlu:
7173 case Intrinsic::aarch64_neon_srshl:
7174 case Intrinsic::aarch64_neon_urshl:
7175 return tryCombineShiftImm(IID, N, DAG);
7176 case Intrinsic::aarch64_crc32b:
7177 case Intrinsic::aarch64_crc32cb:
7178 return tryCombineCRC32(0xff, N, DAG);
7179 case Intrinsic::aarch64_crc32h:
7180 case Intrinsic::aarch64_crc32ch:
7181 return tryCombineCRC32(0xffff, N, DAG);
7186 static SDValue performExtendCombine(SDNode *N,
7187 TargetLowering::DAGCombinerInfo &DCI,
7188 SelectionDAG &DAG) {
7189 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
7190 // we can convert that DUP into another extract_high (of a bigger DUP), which
7191 // helps the backend to decide that an sabdl2 would be useful, saving a real
7192 // extract_high operation.
7193 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
7194 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
7195 SDNode *ABDNode = N->getOperand(0).getNode();
7196 unsigned IID = getIntrinsicID(ABDNode);
7197 if (IID == Intrinsic::aarch64_neon_sabd ||
7198 IID == Intrinsic::aarch64_neon_uabd) {
7199 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
7200 if (!NewABD.getNode())
7203 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
7208 // This is effectively a custom type legalization for AArch64.
7210 // Type legalization will split an extend of a small, legal, type to a larger
7211 // illegal type by first splitting the destination type, often creating
7212 // illegal source types, which then get legalized in isel-confusing ways,
7213 // leading to really terrible codegen. E.g.,
7214 // %result = v8i32 sext v8i8 %value
7216 // %losrc = extract_subreg %value, ...
7217 // %hisrc = extract_subreg %value, ...
7218 // %lo = v4i32 sext v4i8 %losrc
7219 // %hi = v4i32 sext v4i8 %hisrc
7220 // Things go rapidly downhill from there.
7222 // For AArch64, the [sz]ext vector instructions can only go up one element
7223 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
7224 // take two instructions.
7226 // This implies that the most efficient way to do the extend from v8i8
7227 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
7228 // the normal splitting to happen for the v8i16->v8i32.
7230 // This is pre-legalization to catch some cases where the default
7231 // type legalization will create ill-tempered code.
7232 if (!DCI.isBeforeLegalizeOps())
7235 // We're only interested in cleaning things up for non-legal vector types
7236 // here. If both the source and destination are legal, things will just
7237 // work naturally without any fiddling.
7238 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7239 EVT ResVT = N->getValueType(0);
7240 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7242 // If the vector type isn't a simple VT, it's beyond the scope of what
7243 // we're worried about here. Let legalization do its thing and hope for
7245 if (!ResVT.isSimple())
7248 SDValue Src = N->getOperand(0);
7249 MVT SrcVT = Src->getValueType(0).getSimpleVT();
7250 // If the source VT is a 64-bit vector, we can play games and get the
7251 // better results we want.
7252 if (SrcVT.getSizeInBits() != 64)
7255 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
7256 unsigned ElementCount = SrcVT.getVectorNumElements();
7257 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
7259 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
7261 // Now split the rest of the operation into two halves, each with a 64
7265 unsigned NumElements = ResVT.getVectorNumElements();
7266 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
7267 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
7268 ResVT.getVectorElementType(), NumElements / 2);
7270 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
7271 LoVT.getVectorNumElements());
7272 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7273 DAG.getIntPtrConstant(0));
7274 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7275 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
7276 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
7277 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
7279 // Now combine the parts back together so we still have a single result
7280 // like the combiner expects.
7281 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7284 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
7285 /// value. The load store optimizer pass will merge them to store pair stores.
7286 /// This has better performance than a splat of the scalar followed by a split
7287 /// vector store. Even if the stores are not merged it is four stores vs a dup,
7288 /// followed by an ext.b and two stores.
7289 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
7290 SDValue StVal = St->getValue();
7291 EVT VT = StVal.getValueType();
7293 // Don't replace floating point stores, they possibly won't be transformed to
7294 // stp because of the store pair suppress pass.
7295 if (VT.isFloatingPoint())
7298 // Check for insert vector elements.
7299 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
7302 // We can express a splat as store pair(s) for 2 or 4 elements.
7303 unsigned NumVecElts = VT.getVectorNumElements();
7304 if (NumVecElts != 4 && NumVecElts != 2)
7306 SDValue SplatVal = StVal.getOperand(1);
7307 unsigned RemainInsertElts = NumVecElts - 1;
7309 // Check that this is a splat.
7310 while (--RemainInsertElts) {
7311 SDValue NextInsertElt = StVal.getOperand(0);
7312 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
7314 if (NextInsertElt.getOperand(1) != SplatVal)
7316 StVal = NextInsertElt;
7318 unsigned OrigAlignment = St->getAlignment();
7319 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
7320 unsigned Alignment = std::min(OrigAlignment, EltOffset);
7322 // Create scalar stores. This is at least as good as the code sequence for a
7323 // split unaligned store wich is a dup.s, ext.b, and two stores.
7324 // Most of the time the three stores should be replaced by store pair
7325 // instructions (stp).
7327 SDValue BasePtr = St->getBasePtr();
7329 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
7330 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
7332 unsigned Offset = EltOffset;
7333 while (--NumVecElts) {
7334 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7335 DAG.getConstant(Offset, MVT::i64));
7336 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
7337 St->getPointerInfo(), St->isVolatile(),
7338 St->isNonTemporal(), Alignment);
7339 Offset += EltOffset;
7344 static SDValue performSTORECombine(SDNode *N,
7345 TargetLowering::DAGCombinerInfo &DCI,
7347 const AArch64Subtarget *Subtarget) {
7348 if (!DCI.isBeforeLegalize())
7351 StoreSDNode *S = cast<StoreSDNode>(N);
7352 if (S->isVolatile())
7355 // Cyclone has bad performance on unaligned 16B stores when crossing line and
7356 // page boundries. We want to split such stores.
7357 if (!Subtarget->isCyclone())
7360 // Don't split at Oz.
7361 MachineFunction &MF = DAG.getMachineFunction();
7362 bool IsMinSize = MF.getFunction()->getAttributes().hasAttribute(
7363 AttributeSet::FunctionIndex, Attribute::MinSize);
7367 SDValue StVal = S->getValue();
7368 EVT VT = StVal.getValueType();
7370 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
7371 // those up regresses performance on micro-benchmarks and olden/bh.
7372 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
7375 // Split unaligned 16B stores. They are terrible for performance.
7376 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
7377 // extensions can use this to mark that it does not want splitting to happen
7378 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
7379 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
7380 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
7381 S->getAlignment() <= 2)
7384 // If we get a splat of a scalar convert this vector store to a store of
7385 // scalars. They will be merged into store pairs thereby removing two
7387 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
7388 if (ReplacedSplat != SDValue())
7389 return ReplacedSplat;
7392 unsigned NumElts = VT.getVectorNumElements() / 2;
7393 // Split VT into two.
7395 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
7396 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7397 DAG.getIntPtrConstant(0));
7398 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7399 DAG.getIntPtrConstant(NumElts));
7400 SDValue BasePtr = S->getBasePtr();
7402 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
7403 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
7404 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7405 DAG.getConstant(8, MVT::i64));
7406 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
7407 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
7411 /// Target-specific DAG combine function for post-increment LD1 (lane) and
7412 /// post-increment LD1R.
7413 static SDValue performPostLD1Combine(SDNode *N,
7414 TargetLowering::DAGCombinerInfo &DCI,
7416 if (DCI.isBeforeLegalizeOps())
7419 SelectionDAG &DAG = DCI.DAG;
7420 EVT VT = N->getValueType(0);
7422 unsigned LoadIdx = IsLaneOp ? 1 : 0;
7423 SDNode *LD = N->getOperand(LoadIdx).getNode();
7424 // If it is not LOAD, can not do such combine.
7425 if (LD->getOpcode() != ISD::LOAD)
7428 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
7429 EVT MemVT = LoadSDN->getMemoryVT();
7430 // Check if memory operand is the same type as the vector element.
7431 if (MemVT != VT.getVectorElementType())
7434 // Check if there are other uses. If so, do not combine as it will introduce
7436 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
7438 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
7444 SDValue Addr = LD->getOperand(1);
7445 SDValue Vector = N->getOperand(0);
7446 // Search for a use of the address operand that is an increment.
7447 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
7448 Addr.getNode()->use_end(); UI != UE; ++UI) {
7450 if (User->getOpcode() != ISD::ADD
7451 || UI.getUse().getResNo() != Addr.getResNo())
7454 // Check that the add is independent of the load. Otherwise, folding it
7455 // would create a cycle.
7456 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
7458 // Also check that add is not used in the vector operand. This would also
7460 if (User->isPredecessorOf(Vector.getNode()))
7463 // If the increment is a constant, it must match the memory ref size.
7464 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7465 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7466 uint32_t IncVal = CInc->getZExtValue();
7467 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
7468 if (IncVal != NumBytes)
7470 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7473 SmallVector<SDValue, 8> Ops;
7474 Ops.push_back(LD->getOperand(0)); // Chain
7476 Ops.push_back(Vector); // The vector to be inserted
7477 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
7479 Ops.push_back(Addr);
7482 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
7483 SDVTList SDTys = DAG.getVTList(ArrayRef<EVT>(Tys, 3));
7484 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
7485 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
7487 LoadSDN->getMemOperand());
7490 std::vector<SDValue> NewResults;
7491 NewResults.push_back(SDValue(LD, 0)); // The result of load
7492 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
7493 DCI.CombineTo(LD, NewResults);
7494 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
7495 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
7502 /// Target-specific DAG combine function for NEON load/store intrinsics
7503 /// to merge base address updates.
7504 static SDValue performNEONPostLDSTCombine(SDNode *N,
7505 TargetLowering::DAGCombinerInfo &DCI,
7506 SelectionDAG &DAG) {
7507 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
7510 unsigned AddrOpIdx = N->getNumOperands() - 1;
7511 SDValue Addr = N->getOperand(AddrOpIdx);
7513 // Search for a use of the address operand that is an increment.
7514 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
7515 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
7517 if (User->getOpcode() != ISD::ADD ||
7518 UI.getUse().getResNo() != Addr.getResNo())
7521 // Check that the add is independent of the load/store. Otherwise, folding
7522 // it would create a cycle.
7523 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
7526 // Find the new opcode for the updating load/store.
7527 bool IsStore = false;
7528 bool IsLaneOp = false;
7529 bool IsDupOp = false;
7530 unsigned NewOpc = 0;
7531 unsigned NumVecs = 0;
7532 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7534 default: llvm_unreachable("unexpected intrinsic for Neon base update");
7535 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
7537 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
7539 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
7541 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
7542 NumVecs = 2; IsStore = true; break;
7543 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
7544 NumVecs = 3; IsStore = true; break;
7545 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
7546 NumVecs = 4; IsStore = true; break;
7547 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
7549 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
7551 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
7553 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
7554 NumVecs = 2; IsStore = true; break;
7555 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
7556 NumVecs = 3; IsStore = true; break;
7557 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
7558 NumVecs = 4; IsStore = true; break;
7559 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
7560 NumVecs = 2; IsDupOp = true; break;
7561 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
7562 NumVecs = 3; IsDupOp = true; break;
7563 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
7564 NumVecs = 4; IsDupOp = true; break;
7565 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
7566 NumVecs = 2; IsLaneOp = true; break;
7567 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
7568 NumVecs = 3; IsLaneOp = true; break;
7569 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
7570 NumVecs = 4; IsLaneOp = true; break;
7571 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
7572 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
7573 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
7574 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
7575 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
7576 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
7581 VecTy = N->getOperand(2).getValueType();
7583 VecTy = N->getValueType(0);
7585 // If the increment is a constant, it must match the memory ref size.
7586 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7587 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7588 uint32_t IncVal = CInc->getZExtValue();
7589 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
7590 if (IsLaneOp || IsDupOp)
7591 NumBytes /= VecTy.getVectorNumElements();
7592 if (IncVal != NumBytes)
7594 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7596 SmallVector<SDValue, 8> Ops;
7597 Ops.push_back(N->getOperand(0)); // Incoming chain
7598 // Load lane and store have vector list as input.
7599 if (IsLaneOp || IsStore)
7600 for (unsigned i = 2; i < AddrOpIdx; ++i)
7601 Ops.push_back(N->getOperand(i));
7602 Ops.push_back(Addr); // Base register
7607 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
7609 for (n = 0; n < NumResultVecs; ++n)
7611 Tys[n++] = MVT::i64; // Type of write back register
7612 Tys[n] = MVT::Other; // Type of the chain
7613 SDVTList SDTys = DAG.getVTList(ArrayRef<EVT>(Tys, NumResultVecs + 2));
7615 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
7616 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
7617 MemInt->getMemoryVT(),
7618 MemInt->getMemOperand());
7621 std::vector<SDValue> NewResults;
7622 for (unsigned i = 0; i < NumResultVecs; ++i) {
7623 NewResults.push_back(SDValue(UpdN.getNode(), i));
7625 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
7626 DCI.CombineTo(N, NewResults);
7627 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
7634 // Optimize compare with zero and branch.
7635 static SDValue performBRCONDCombine(SDNode *N,
7636 TargetLowering::DAGCombinerInfo &DCI,
7637 SelectionDAG &DAG) {
7638 SDValue Chain = N->getOperand(0);
7639 SDValue Dest = N->getOperand(1);
7640 SDValue CCVal = N->getOperand(2);
7641 SDValue Cmp = N->getOperand(3);
7643 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
7644 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
7645 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
7648 unsigned CmpOpc = Cmp.getOpcode();
7649 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
7652 // Only attempt folding if there is only one use of the flag and no use of the
7654 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
7657 SDValue LHS = Cmp.getOperand(0);
7658 SDValue RHS = Cmp.getOperand(1);
7660 assert(LHS.getValueType() == RHS.getValueType() &&
7661 "Expected the value type to be the same for both operands!");
7662 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
7665 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
7666 std::swap(LHS, RHS);
7668 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
7671 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
7672 LHS.getOpcode() == ISD::SRL)
7675 // Fold the compare into the branch instruction.
7677 if (CC == AArch64CC::EQ)
7678 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
7680 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
7682 // Do not add new nodes to DAG combiner worklist.
7683 DCI.CombineTo(N, BR, false);
7688 // vselect (v1i1 setcc) ->
7689 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
7690 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
7691 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
7693 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
7694 SDValue N0 = N->getOperand(0);
7695 EVT CCVT = N0.getValueType();
7697 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
7698 CCVT.getVectorElementType() != MVT::i1)
7701 EVT ResVT = N->getValueType(0);
7702 EVT CmpVT = N0.getOperand(0).getValueType();
7703 // Only combine when the result type is of the same size as the compared
7705 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
7708 SDValue IfTrue = N->getOperand(1);
7709 SDValue IfFalse = N->getOperand(2);
7711 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
7712 N0.getOperand(0), N0.getOperand(1),
7713 cast<CondCodeSDNode>(N0.getOperand(2))->get());
7714 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
7718 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
7719 /// the compare-mask instructions rather than going via NZCV, even if LHS and
7720 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
7721 /// with a vector one followed by a DUP shuffle on the result.
7722 static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
7723 SDValue N0 = N->getOperand(0);
7724 EVT ResVT = N->getValueType(0);
7726 if (!N->getOperand(1).getValueType().isVector())
7729 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
7734 EVT SrcVT = N0.getOperand(0).getValueType();
7735 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT,
7736 ResVT.getSizeInBits() / SrcVT.getSizeInBits());
7737 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
7739 // First perform a vector comparison, where lane 0 is the one we're interested
7742 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
7744 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
7745 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
7747 // Now duplicate the comparison mask we want across all other lanes.
7748 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
7749 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
7750 Mask = DAG.getNode(ISD::BITCAST, DL, ResVT.changeVectorElementTypeToInteger(),
7753 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
7756 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
7757 DAGCombinerInfo &DCI) const {
7758 SelectionDAG &DAG = DCI.DAG;
7759 switch (N->getOpcode()) {
7764 return performAddSubLongCombine(N, DCI, DAG);
7766 return performXorCombine(N, DAG, DCI, Subtarget);
7768 return performMulCombine(N, DAG, DCI, Subtarget);
7769 case ISD::SINT_TO_FP:
7770 case ISD::UINT_TO_FP:
7771 return performIntToFpCombine(N, DAG);
7773 return performORCombine(N, DCI, Subtarget);
7774 case ISD::INTRINSIC_WO_CHAIN:
7775 return performIntrinsicCombine(N, DCI, Subtarget);
7776 case ISD::ANY_EXTEND:
7777 case ISD::ZERO_EXTEND:
7778 case ISD::SIGN_EXTEND:
7779 return performExtendCombine(N, DCI, DAG);
7781 return performBitcastCombine(N, DCI, DAG);
7782 case ISD::CONCAT_VECTORS:
7783 return performConcatVectorsCombine(N, DCI, DAG);
7785 return performSelectCombine(N, DAG);
7787 return performVSelectCombine(N, DCI.DAG);
7789 return performSTORECombine(N, DCI, DAG, Subtarget);
7790 case AArch64ISD::BRCOND:
7791 return performBRCONDCombine(N, DCI, DAG);
7792 case AArch64ISD::DUP:
7793 return performPostLD1Combine(N, DCI, false);
7794 case ISD::INSERT_VECTOR_ELT:
7795 return performPostLD1Combine(N, DCI, true);
7796 case ISD::INTRINSIC_VOID:
7797 case ISD::INTRINSIC_W_CHAIN:
7798 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7799 case Intrinsic::aarch64_neon_ld2:
7800 case Intrinsic::aarch64_neon_ld3:
7801 case Intrinsic::aarch64_neon_ld4:
7802 case Intrinsic::aarch64_neon_ld1x2:
7803 case Intrinsic::aarch64_neon_ld1x3:
7804 case Intrinsic::aarch64_neon_ld1x4:
7805 case Intrinsic::aarch64_neon_ld2lane:
7806 case Intrinsic::aarch64_neon_ld3lane:
7807 case Intrinsic::aarch64_neon_ld4lane:
7808 case Intrinsic::aarch64_neon_ld2r:
7809 case Intrinsic::aarch64_neon_ld3r:
7810 case Intrinsic::aarch64_neon_ld4r:
7811 case Intrinsic::aarch64_neon_st2:
7812 case Intrinsic::aarch64_neon_st3:
7813 case Intrinsic::aarch64_neon_st4:
7814 case Intrinsic::aarch64_neon_st1x2:
7815 case Intrinsic::aarch64_neon_st1x3:
7816 case Intrinsic::aarch64_neon_st1x4:
7817 case Intrinsic::aarch64_neon_st2lane:
7818 case Intrinsic::aarch64_neon_st3lane:
7819 case Intrinsic::aarch64_neon_st4lane:
7820 return performNEONPostLDSTCombine(N, DCI, DAG);
7828 // Check if the return value is used as only a return value, as otherwise
7829 // we can't perform a tail-call. In particular, we need to check for
7830 // target ISD nodes that are returns and any other "odd" constructs
7831 // that the generic analysis code won't necessarily catch.
7832 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
7833 SDValue &Chain) const {
7834 if (N->getNumValues() != 1)
7836 if (!N->hasNUsesOfValue(1, 0))
7839 SDValue TCChain = Chain;
7840 SDNode *Copy = *N->use_begin();
7841 if (Copy->getOpcode() == ISD::CopyToReg) {
7842 // If the copy has a glue operand, we conservatively assume it isn't safe to
7843 // perform a tail call.
7844 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
7847 TCChain = Copy->getOperand(0);
7848 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
7851 bool HasRet = false;
7852 for (SDNode *Node : Copy->uses()) {
7853 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
7865 // Return whether the an instruction can potentially be optimized to a tail
7866 // call. This will cause the optimizers to attempt to move, or duplicate,
7867 // return instructions to help enable tail call optimizations for this
7869 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
7870 if (!CI->isTailCall())
7876 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
7878 ISD::MemIndexedMode &AM,
7880 SelectionDAG &DAG) const {
7881 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
7884 Base = Op->getOperand(0);
7885 // All of the indexed addressing mode instructions take a signed
7886 // 9 bit immediate offset.
7887 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
7888 int64_t RHSC = (int64_t)RHS->getZExtValue();
7889 if (RHSC >= 256 || RHSC <= -256)
7891 IsInc = (Op->getOpcode() == ISD::ADD);
7892 Offset = Op->getOperand(1);
7898 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
7900 ISD::MemIndexedMode &AM,
7901 SelectionDAG &DAG) const {
7904 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7905 VT = LD->getMemoryVT();
7906 Ptr = LD->getBasePtr();
7907 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7908 VT = ST->getMemoryVT();
7909 Ptr = ST->getBasePtr();
7914 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
7916 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
7920 bool AArch64TargetLowering::getPostIndexedAddressParts(
7921 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
7922 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
7925 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7926 VT = LD->getMemoryVT();
7927 Ptr = LD->getBasePtr();
7928 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7929 VT = ST->getMemoryVT();
7930 Ptr = ST->getBasePtr();
7935 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
7937 // Post-indexing updates the base, so it's not a valid transform
7938 // if that's not the same as the load's pointer.
7941 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
7945 void AArch64TargetLowering::ReplaceNodeResults(
7946 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
7947 switch (N->getOpcode()) {
7949 llvm_unreachable("Don't know how to custom expand this");
7950 case ISD::FP_TO_UINT:
7951 case ISD::FP_TO_SINT:
7952 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
7953 // Let normal code take care of it by not adding anything to Results.
7958 bool AArch64TargetLowering::shouldExpandAtomicInIR(Instruction *Inst) const {
7959 // Loads and stores less than 128-bits are already atomic; ones above that
7960 // are doomed anyway, so defer to the default libcall and blame the OS when
7962 if (StoreInst *SI = dyn_cast<StoreInst>(Inst))
7963 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() == 128;
7964 else if (LoadInst *LI = dyn_cast<LoadInst>(Inst))
7965 return LI->getType()->getPrimitiveSizeInBits() == 128;
7967 // For the real atomic operations, we have ldxr/stxr up to 128 bits.
7968 return Inst->getType()->getPrimitiveSizeInBits() <= 128;
7971 TargetLoweringBase::LegalizeTypeAction
7972 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
7973 MVT SVT = VT.getSimpleVT();
7974 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
7975 // v4i16, v2i32 instead of to promote.
7976 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
7977 || SVT == MVT::v1f32)
7978 return TypeWidenVector;
7980 return TargetLoweringBase::getPreferredVectorAction(VT);
7983 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
7984 AtomicOrdering Ord) const {
7985 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
7986 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
7988 Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent;
7990 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
7991 // intrinsic must return {i64, i64} and we have to recombine them into a
7992 // single i128 here.
7993 if (ValTy->getPrimitiveSizeInBits() == 128) {
7995 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
7996 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
7998 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
7999 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
8001 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
8002 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
8003 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
8004 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
8005 return Builder.CreateOr(
8006 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
8009 Type *Tys[] = { Addr->getType() };
8011 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
8012 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
8014 return Builder.CreateTruncOrBitCast(
8015 Builder.CreateCall(Ldxr, Addr),
8016 cast<PointerType>(Addr->getType())->getElementType());
8019 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
8020 Value *Val, Value *Addr,
8021 AtomicOrdering Ord) const {
8022 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8024 Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent;
8026 // Since the intrinsics must have legal type, the i128 intrinsics take two
8027 // parameters: "i64, i64". We must marshal Val into the appropriate form
8029 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
8031 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
8032 Function *Stxr = Intrinsic::getDeclaration(M, Int);
8033 Type *Int64Ty = Type::getInt64Ty(M->getContext());
8035 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
8036 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
8037 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8038 return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
8042 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
8043 Type *Tys[] = { Addr->getType() };
8044 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
8046 return Builder.CreateCall2(
8047 Stxr, Builder.CreateZExtOrBitCast(
8048 Val, Stxr->getFunctionType()->getParamType(0)),