1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64ISelLowering.h"
15 #include "AArch64MachineFunctionInfo.h"
16 #include "AArch64PerfectShuffle.h"
17 #include "AArch64Subtarget.h"
18 #include "AArch64TargetMachine.h"
19 #include "AArch64TargetObjectFile.h"
20 #include "MCTargetDesc/AArch64AddressingModes.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/Intrinsics.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetOptions.h"
36 #define DEBUG_TYPE "aarch64-lower"
38 STATISTIC(NumTailCalls, "Number of tail calls");
39 STATISTIC(NumShiftInserts, "Number of vector shift inserts");
48 static cl::opt<AlignMode>
49 Align(cl::desc("Load/store alignment support"),
50 cl::Hidden, cl::init(NoStrictAlign),
52 clEnumValN(StrictAlign, "aarch64-strict-align",
53 "Disallow all unaligned memory accesses"),
54 clEnumValN(NoStrictAlign, "aarch64-no-strict-align",
55 "Allow unaligned memory accesses"),
58 // Place holder until extr generation is tested fully.
60 EnableAArch64ExtrGeneration("aarch64-extr-generation", cl::Hidden,
61 cl::desc("Allow AArch64 (or (shift)(shift))->extract"),
65 EnableAArch64SlrGeneration("aarch64-shift-insert-generation", cl::Hidden,
66 cl::desc("Allow AArch64 SLI/SRI formation"),
70 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM)
71 : TargetLowering(TM) {
72 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
74 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
75 // we have to make something up. Arbitrarily, choose ZeroOrOne.
76 setBooleanContents(ZeroOrOneBooleanContent);
77 // When comparing vectors the result sets the different elements in the
78 // vector to all-one or all-zero.
79 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
81 // Set up the register classes.
82 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
83 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass);
85 if (Subtarget->hasFPARMv8()) {
86 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass);
87 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass);
88 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass);
89 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass);
92 if (Subtarget->hasNEON()) {
93 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass);
94 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
95 // Someone set us up the NEON.
96 addDRTypeForNEON(MVT::v2f32);
97 addDRTypeForNEON(MVT::v8i8);
98 addDRTypeForNEON(MVT::v4i16);
99 addDRTypeForNEON(MVT::v2i32);
100 addDRTypeForNEON(MVT::v1i64);
101 addDRTypeForNEON(MVT::v1f64);
102 addDRTypeForNEON(MVT::v4f16);
104 addQRTypeForNEON(MVT::v4f32);
105 addQRTypeForNEON(MVT::v2f64);
106 addQRTypeForNEON(MVT::v16i8);
107 addQRTypeForNEON(MVT::v8i16);
108 addQRTypeForNEON(MVT::v4i32);
109 addQRTypeForNEON(MVT::v2i64);
110 addQRTypeForNEON(MVT::v8f16);
113 // Compute derived properties from the register classes
114 computeRegisterProperties();
116 // Provide all sorts of operation actions
117 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
118 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
119 setOperationAction(ISD::SETCC, MVT::i32, Custom);
120 setOperationAction(ISD::SETCC, MVT::i64, Custom);
121 setOperationAction(ISD::SETCC, MVT::f32, Custom);
122 setOperationAction(ISD::SETCC, MVT::f64, Custom);
123 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
124 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
125 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
126 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
127 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
128 setOperationAction(ISD::SELECT, MVT::i32, Custom);
129 setOperationAction(ISD::SELECT, MVT::i64, Custom);
130 setOperationAction(ISD::SELECT, MVT::f32, Custom);
131 setOperationAction(ISD::SELECT, MVT::f64, Custom);
132 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
133 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
134 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
135 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
136 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
137 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
139 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
140 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
141 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
143 setOperationAction(ISD::FREM, MVT::f32, Expand);
144 setOperationAction(ISD::FREM, MVT::f64, Expand);
145 setOperationAction(ISD::FREM, MVT::f80, Expand);
147 // Custom lowering hooks are needed for XOR
148 // to fold it into CSINC/CSINV.
149 setOperationAction(ISD::XOR, MVT::i32, Custom);
150 setOperationAction(ISD::XOR, MVT::i64, Custom);
152 // Virtually no operation on f128 is legal, but LLVM can't expand them when
153 // there's a valid register class, so we need custom operations in most cases.
154 setOperationAction(ISD::FABS, MVT::f128, Expand);
155 setOperationAction(ISD::FADD, MVT::f128, Custom);
156 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
157 setOperationAction(ISD::FCOS, MVT::f128, Expand);
158 setOperationAction(ISD::FDIV, MVT::f128, Custom);
159 setOperationAction(ISD::FMA, MVT::f128, Expand);
160 setOperationAction(ISD::FMUL, MVT::f128, Custom);
161 setOperationAction(ISD::FNEG, MVT::f128, Expand);
162 setOperationAction(ISD::FPOW, MVT::f128, Expand);
163 setOperationAction(ISD::FREM, MVT::f128, Expand);
164 setOperationAction(ISD::FRINT, MVT::f128, Expand);
165 setOperationAction(ISD::FSIN, MVT::f128, Expand);
166 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
167 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
168 setOperationAction(ISD::FSUB, MVT::f128, Custom);
169 setOperationAction(ISD::FTRUNC, MVT::f128, Expand);
170 setOperationAction(ISD::SETCC, MVT::f128, Custom);
171 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
172 setOperationAction(ISD::SELECT, MVT::f128, Custom);
173 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
174 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
176 // Lowering for many of the conversions is actually specified by the non-f128
177 // type. The LowerXXX function will be trivial when f128 isn't involved.
178 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
179 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
180 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom);
181 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
182 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
183 setOperationAction(ISD::FP_TO_UINT, MVT::i128, Custom);
184 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
185 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
186 setOperationAction(ISD::SINT_TO_FP, MVT::i128, Custom);
187 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
188 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
189 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom);
190 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
191 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
193 // Variable arguments.
194 setOperationAction(ISD::VASTART, MVT::Other, Custom);
195 setOperationAction(ISD::VAARG, MVT::Other, Custom);
196 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
197 setOperationAction(ISD::VAEND, MVT::Other, Expand);
199 // Variable-sized objects.
200 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
201 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
202 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
204 // Exception handling.
205 // FIXME: These are guesses. Has this been defined yet?
206 setExceptionPointerRegister(AArch64::X0);
207 setExceptionSelectorRegister(AArch64::X1);
209 // Constant pool entries
210 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
213 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
215 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
216 setOperationAction(ISD::ADDC, MVT::i32, Custom);
217 setOperationAction(ISD::ADDE, MVT::i32, Custom);
218 setOperationAction(ISD::SUBC, MVT::i32, Custom);
219 setOperationAction(ISD::SUBE, MVT::i32, Custom);
220 setOperationAction(ISD::ADDC, MVT::i64, Custom);
221 setOperationAction(ISD::ADDE, MVT::i64, Custom);
222 setOperationAction(ISD::SUBC, MVT::i64, Custom);
223 setOperationAction(ISD::SUBE, MVT::i64, Custom);
225 // AArch64 lacks both left-rotate and popcount instructions.
226 setOperationAction(ISD::ROTL, MVT::i32, Expand);
227 setOperationAction(ISD::ROTL, MVT::i64, Expand);
229 // AArch64 doesn't have {U|S}MUL_LOHI.
230 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
231 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
234 // Expand the undefined-at-zero variants to cttz/ctlz to their defined-at-zero
235 // counterparts, which AArch64 supports directly.
236 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
237 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
238 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
239 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
241 setOperationAction(ISD::CTPOP, MVT::i32, Custom);
242 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
244 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
245 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
246 setOperationAction(ISD::SREM, MVT::i32, Expand);
247 setOperationAction(ISD::SREM, MVT::i64, Expand);
248 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
249 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
250 setOperationAction(ISD::UREM, MVT::i32, Expand);
251 setOperationAction(ISD::UREM, MVT::i64, Expand);
253 // Custom lower Add/Sub/Mul with overflow.
254 setOperationAction(ISD::SADDO, MVT::i32, Custom);
255 setOperationAction(ISD::SADDO, MVT::i64, Custom);
256 setOperationAction(ISD::UADDO, MVT::i32, Custom);
257 setOperationAction(ISD::UADDO, MVT::i64, Custom);
258 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
259 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
260 setOperationAction(ISD::USUBO, MVT::i32, Custom);
261 setOperationAction(ISD::USUBO, MVT::i64, Custom);
262 setOperationAction(ISD::SMULO, MVT::i32, Custom);
263 setOperationAction(ISD::SMULO, MVT::i64, Custom);
264 setOperationAction(ISD::UMULO, MVT::i32, Custom);
265 setOperationAction(ISD::UMULO, MVT::i64, Custom);
267 setOperationAction(ISD::FSIN, MVT::f32, Expand);
268 setOperationAction(ISD::FSIN, MVT::f64, Expand);
269 setOperationAction(ISD::FCOS, MVT::f32, Expand);
270 setOperationAction(ISD::FCOS, MVT::f64, Expand);
271 setOperationAction(ISD::FPOW, MVT::f32, Expand);
272 setOperationAction(ISD::FPOW, MVT::f64, Expand);
273 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
274 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
276 // f16 is storage-only, so we promote operations to f32 if we know this is
277 // valid, and ignore them otherwise. The operations not mentioned here will
278 // fail to select, but this is not a major problem as no source language
279 // should be emitting native f16 operations yet.
280 setOperationAction(ISD::FADD, MVT::f16, Promote);
281 setOperationAction(ISD::FDIV, MVT::f16, Promote);
282 setOperationAction(ISD::FMUL, MVT::f16, Promote);
283 setOperationAction(ISD::FSUB, MVT::f16, Promote);
285 // v4f16 is also a storage-only type, so promote it to v4f32 when that is
287 setOperationAction(ISD::FADD, MVT::v4f16, Promote);
288 setOperationAction(ISD::FSUB, MVT::v4f16, Promote);
289 setOperationAction(ISD::FMUL, MVT::v4f16, Promote);
290 setOperationAction(ISD::FDIV, MVT::v4f16, Promote);
291 setOperationAction(ISD::FP_EXTEND, MVT::v4f16, Promote);
292 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote);
293 AddPromotedToType(ISD::FADD, MVT::v4f16, MVT::v4f32);
294 AddPromotedToType(ISD::FSUB, MVT::v4f16, MVT::v4f32);
295 AddPromotedToType(ISD::FMUL, MVT::v4f16, MVT::v4f32);
296 AddPromotedToType(ISD::FDIV, MVT::v4f16, MVT::v4f32);
297 AddPromotedToType(ISD::FP_EXTEND, MVT::v4f16, MVT::v4f32);
298 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32);
300 // Expand all other v4f16 operations.
301 // FIXME: We could generate better code by promoting some operations to
303 setOperationAction(ISD::FABS, MVT::v4f16, Expand);
304 setOperationAction(ISD::FCEIL, MVT::v4f16, Expand);
305 setOperationAction(ISD::FCOPYSIGN, MVT::v4f16, Expand);
306 setOperationAction(ISD::FCOS, MVT::v4f16, Expand);
307 setOperationAction(ISD::FFLOOR, MVT::v4f16, Expand);
308 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
309 setOperationAction(ISD::FNEARBYINT, MVT::v4f16, Expand);
310 setOperationAction(ISD::FNEG, MVT::v4f16, Expand);
311 setOperationAction(ISD::FPOW, MVT::v4f16, Expand);
312 setOperationAction(ISD::FPOWI, MVT::v4f16, Expand);
313 setOperationAction(ISD::FREM, MVT::v4f16, Expand);
314 setOperationAction(ISD::FROUND, MVT::v4f16, Expand);
315 setOperationAction(ISD::FRINT, MVT::v4f16, Expand);
316 setOperationAction(ISD::FSIN, MVT::v4f16, Expand);
317 setOperationAction(ISD::FSINCOS, MVT::v4f16, Expand);
318 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
319 setOperationAction(ISD::FTRUNC, MVT::v4f16, Expand);
320 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
321 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand);
322 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
323 setOperationAction(ISD::SELECT_CC, MVT::v4f16, Expand);
324 setOperationAction(ISD::FEXP, MVT::v4f16, Expand);
325 setOperationAction(ISD::FEXP2, MVT::v4f16, Expand);
326 setOperationAction(ISD::FLOG, MVT::v4f16, Expand);
327 setOperationAction(ISD::FLOG2, MVT::v4f16, Expand);
328 setOperationAction(ISD::FLOG10, MVT::v4f16, Expand);
331 // v8f16 is also a storage-only type, so expand it.
332 setOperationAction(ISD::FABS, MVT::v8f16, Expand);
333 setOperationAction(ISD::FADD, MVT::v8f16, Expand);
334 setOperationAction(ISD::FCEIL, MVT::v8f16, Expand);
335 setOperationAction(ISD::FCOPYSIGN, MVT::v8f16, Expand);
336 setOperationAction(ISD::FCOS, MVT::v8f16, Expand);
337 setOperationAction(ISD::FDIV, MVT::v8f16, Expand);
338 setOperationAction(ISD::FFLOOR, MVT::v8f16, Expand);
339 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
340 setOperationAction(ISD::FMUL, MVT::v8f16, Expand);
341 setOperationAction(ISD::FNEARBYINT, MVT::v8f16, Expand);
342 setOperationAction(ISD::FNEG, MVT::v8f16, Expand);
343 setOperationAction(ISD::FPOW, MVT::v8f16, Expand);
344 setOperationAction(ISD::FPOWI, MVT::v8f16, Expand);
345 setOperationAction(ISD::FREM, MVT::v8f16, Expand);
346 setOperationAction(ISD::FROUND, MVT::v8f16, Expand);
347 setOperationAction(ISD::FRINT, MVT::v8f16, Expand);
348 setOperationAction(ISD::FSIN, MVT::v8f16, Expand);
349 setOperationAction(ISD::FSINCOS, MVT::v8f16, Expand);
350 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
351 setOperationAction(ISD::FSUB, MVT::v8f16, Expand);
352 setOperationAction(ISD::FTRUNC, MVT::v8f16, Expand);
353 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
354 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand);
355 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
356 setOperationAction(ISD::SELECT_CC, MVT::v8f16, Expand);
357 setOperationAction(ISD::FP_EXTEND, MVT::v8f16, Expand);
358 setOperationAction(ISD::FEXP, MVT::v8f16, Expand);
359 setOperationAction(ISD::FEXP2, MVT::v8f16, Expand);
360 setOperationAction(ISD::FLOG, MVT::v8f16, Expand);
361 setOperationAction(ISD::FLOG2, MVT::v8f16, Expand);
362 setOperationAction(ISD::FLOG10, MVT::v8f16, Expand);
364 // AArch64 has implementations of a lot of rounding-like FP operations.
365 static MVT RoundingTypes[] = { MVT::f32, MVT::f64};
366 for (unsigned I = 0; I < array_lengthof(RoundingTypes); ++I) {
367 MVT Ty = RoundingTypes[I];
368 setOperationAction(ISD::FFLOOR, Ty, Legal);
369 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
370 setOperationAction(ISD::FCEIL, Ty, Legal);
371 setOperationAction(ISD::FRINT, Ty, Legal);
372 setOperationAction(ISD::FTRUNC, Ty, Legal);
373 setOperationAction(ISD::FROUND, Ty, Legal);
376 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
378 if (Subtarget->isTargetMachO()) {
379 // For iOS, we don't want to the normal expansion of a libcall to
380 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
382 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
383 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
385 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
386 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
389 // AArch64 does not have floating-point extending loads, i1 sign-extending
390 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
391 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
392 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
393 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
394 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
395 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Expand);
396 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
397 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
398 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
399 setTruncStoreAction(MVT::f128, MVT::f80, Expand);
400 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
401 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
402 setTruncStoreAction(MVT::f128, MVT::f16, Expand);
404 setOperationAction(ISD::BITCAST, MVT::i16, Custom);
405 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
407 // Indexed loads and stores are supported.
408 for (unsigned im = (unsigned)ISD::PRE_INC;
409 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
410 setIndexedLoadAction(im, MVT::i8, Legal);
411 setIndexedLoadAction(im, MVT::i16, Legal);
412 setIndexedLoadAction(im, MVT::i32, Legal);
413 setIndexedLoadAction(im, MVT::i64, Legal);
414 setIndexedLoadAction(im, MVT::f64, Legal);
415 setIndexedLoadAction(im, MVT::f32, Legal);
416 setIndexedStoreAction(im, MVT::i8, Legal);
417 setIndexedStoreAction(im, MVT::i16, Legal);
418 setIndexedStoreAction(im, MVT::i32, Legal);
419 setIndexedStoreAction(im, MVT::i64, Legal);
420 setIndexedStoreAction(im, MVT::f64, Legal);
421 setIndexedStoreAction(im, MVT::f32, Legal);
425 setOperationAction(ISD::TRAP, MVT::Other, Legal);
427 // We combine OR nodes for bitfield operations.
428 setTargetDAGCombine(ISD::OR);
430 // Vector add and sub nodes may conceal a high-half opportunity.
431 // Also, try to fold ADD into CSINC/CSINV..
432 setTargetDAGCombine(ISD::ADD);
433 setTargetDAGCombine(ISD::SUB);
435 setTargetDAGCombine(ISD::XOR);
436 setTargetDAGCombine(ISD::SINT_TO_FP);
437 setTargetDAGCombine(ISD::UINT_TO_FP);
439 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
441 setTargetDAGCombine(ISD::ANY_EXTEND);
442 setTargetDAGCombine(ISD::ZERO_EXTEND);
443 setTargetDAGCombine(ISD::SIGN_EXTEND);
444 setTargetDAGCombine(ISD::BITCAST);
445 setTargetDAGCombine(ISD::CONCAT_VECTORS);
446 setTargetDAGCombine(ISD::STORE);
448 setTargetDAGCombine(ISD::MUL);
450 setTargetDAGCombine(ISD::SELECT);
451 setTargetDAGCombine(ISD::VSELECT);
453 setTargetDAGCombine(ISD::INTRINSIC_VOID);
454 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
455 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
457 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;
458 MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 4;
459 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 4;
461 setStackPointerRegisterToSaveRestore(AArch64::SP);
463 setSchedulingPreference(Sched::Hybrid);
466 MaskAndBranchFoldingIsLegal = true;
468 setMinFunctionAlignment(2);
470 RequireStrictAlign = (Align == StrictAlign);
472 setHasExtractBitsInsn(true);
474 if (Subtarget->hasNEON()) {
475 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
476 // silliness like this:
477 setOperationAction(ISD::FABS, MVT::v1f64, Expand);
478 setOperationAction(ISD::FADD, MVT::v1f64, Expand);
479 setOperationAction(ISD::FCEIL, MVT::v1f64, Expand);
480 setOperationAction(ISD::FCOPYSIGN, MVT::v1f64, Expand);
481 setOperationAction(ISD::FCOS, MVT::v1f64, Expand);
482 setOperationAction(ISD::FDIV, MVT::v1f64, Expand);
483 setOperationAction(ISD::FFLOOR, MVT::v1f64, Expand);
484 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
485 setOperationAction(ISD::FMUL, MVT::v1f64, Expand);
486 setOperationAction(ISD::FNEARBYINT, MVT::v1f64, Expand);
487 setOperationAction(ISD::FNEG, MVT::v1f64, Expand);
488 setOperationAction(ISD::FPOW, MVT::v1f64, Expand);
489 setOperationAction(ISD::FREM, MVT::v1f64, Expand);
490 setOperationAction(ISD::FROUND, MVT::v1f64, Expand);
491 setOperationAction(ISD::FRINT, MVT::v1f64, Expand);
492 setOperationAction(ISD::FSIN, MVT::v1f64, Expand);
493 setOperationAction(ISD::FSINCOS, MVT::v1f64, Expand);
494 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
495 setOperationAction(ISD::FSUB, MVT::v1f64, Expand);
496 setOperationAction(ISD::FTRUNC, MVT::v1f64, Expand);
497 setOperationAction(ISD::SETCC, MVT::v1f64, Expand);
498 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand);
499 setOperationAction(ISD::SELECT, MVT::v1f64, Expand);
500 setOperationAction(ISD::SELECT_CC, MVT::v1f64, Expand);
501 setOperationAction(ISD::FP_EXTEND, MVT::v1f64, Expand);
503 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand);
504 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand);
505 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand);
506 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand);
507 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand);
509 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
511 // AArch64 doesn't have a direct vector ->f32 conversion instructions for
512 // elements smaller than i32, so promote the input to i32 first.
513 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Promote);
514 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Promote);
515 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote);
516 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote);
517 // Similarly, there is no direct i32 -> f64 vector conversion instruction.
518 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
519 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
520 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Custom);
521 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Custom);
523 // AArch64 doesn't have MUL.2d:
524 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
525 // Custom handling for some quad-vector types to detect MULL.
526 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
527 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
528 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
530 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
531 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
532 // Likewise, narrowing and extending vector loads/stores aren't handled
534 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
535 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
537 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
540 setOperationAction(ISD::MULHS, (MVT::SimpleValueType)VT, Expand);
541 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
542 setOperationAction(ISD::MULHU, (MVT::SimpleValueType)VT, Expand);
543 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
545 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
547 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
548 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
549 setTruncStoreAction((MVT::SimpleValueType)VT,
550 (MVT::SimpleValueType)InnerVT, Expand);
551 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
552 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
553 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
556 // AArch64 has implementations of a lot of rounding-like FP operations.
557 static MVT RoundingVecTypes[] = {MVT::v2f32, MVT::v4f32, MVT::v2f64 };
558 for (unsigned I = 0; I < array_lengthof(RoundingVecTypes); ++I) {
559 MVT Ty = RoundingVecTypes[I];
560 setOperationAction(ISD::FFLOOR, Ty, Legal);
561 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
562 setOperationAction(ISD::FCEIL, Ty, Legal);
563 setOperationAction(ISD::FRINT, Ty, Legal);
564 setOperationAction(ISD::FTRUNC, Ty, Legal);
565 setOperationAction(ISD::FROUND, Ty, Legal);
569 // Prefer likely predicted branches to selects on out-of-order cores.
570 if (Subtarget->isCortexA57())
571 PredictableSelectIsExpensive = true;
574 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) {
575 if (VT == MVT::v2f32 || VT == MVT::v4f16) {
576 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
577 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
579 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
580 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
581 } else if (VT == MVT::v2f64 || VT == MVT::v4f32 || VT == MVT::v8f16) {
582 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
583 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i64);
585 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
586 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i64);
589 // Mark vector float intrinsics as expand.
590 if (VT == MVT::v2f32 || VT == MVT::v4f32 || VT == MVT::v2f64) {
591 setOperationAction(ISD::FSIN, VT.getSimpleVT(), Expand);
592 setOperationAction(ISD::FCOS, VT.getSimpleVT(), Expand);
593 setOperationAction(ISD::FPOWI, VT.getSimpleVT(), Expand);
594 setOperationAction(ISD::FPOW, VT.getSimpleVT(), Expand);
595 setOperationAction(ISD::FLOG, VT.getSimpleVT(), Expand);
596 setOperationAction(ISD::FLOG2, VT.getSimpleVT(), Expand);
597 setOperationAction(ISD::FLOG10, VT.getSimpleVT(), Expand);
598 setOperationAction(ISD::FEXP, VT.getSimpleVT(), Expand);
599 setOperationAction(ISD::FEXP2, VT.getSimpleVT(), Expand);
602 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
603 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
604 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
605 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
606 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Custom);
607 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
608 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
609 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
610 setOperationAction(ISD::AND, VT.getSimpleVT(), Custom);
611 setOperationAction(ISD::OR, VT.getSimpleVT(), Custom);
612 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
613 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
615 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
616 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
617 setOperationAction(ISD::VSELECT, VT.getSimpleVT(), Expand);
618 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
620 // CNT supports only B element sizes.
621 if (VT != MVT::v8i8 && VT != MVT::v16i8)
622 setOperationAction(ISD::CTPOP, VT.getSimpleVT(), Expand);
624 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
625 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
626 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
627 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
628 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
630 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
631 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
633 if (Subtarget->isLittleEndian()) {
634 for (unsigned im = (unsigned)ISD::PRE_INC;
635 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
636 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
637 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
642 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
643 addRegisterClass(VT, &AArch64::FPR64RegClass);
644 addTypeForNEON(VT, MVT::v2i32);
647 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
648 addRegisterClass(VT, &AArch64::FPR128RegClass);
649 addTypeForNEON(VT, MVT::v4i32);
652 EVT AArch64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
655 return VT.changeVectorElementTypeToInteger();
658 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
659 /// Mask are known to be either zero or one and return them in the
660 /// KnownZero/KnownOne bitsets.
661 void AArch64TargetLowering::computeKnownBitsForTargetNode(
662 const SDValue Op, APInt &KnownZero, APInt &KnownOne,
663 const SelectionDAG &DAG, unsigned Depth) const {
664 switch (Op.getOpcode()) {
667 case AArch64ISD::CSEL: {
668 APInt KnownZero2, KnownOne2;
669 DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
670 DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
671 KnownZero &= KnownZero2;
672 KnownOne &= KnownOne2;
675 case ISD::INTRINSIC_W_CHAIN: {
676 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
677 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
680 case Intrinsic::aarch64_ldaxr:
681 case Intrinsic::aarch64_ldxr: {
682 unsigned BitWidth = KnownOne.getBitWidth();
683 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
684 unsigned MemBits = VT.getScalarType().getSizeInBits();
685 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
691 case ISD::INTRINSIC_WO_CHAIN:
692 case ISD::INTRINSIC_VOID: {
693 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
697 case Intrinsic::aarch64_neon_umaxv:
698 case Intrinsic::aarch64_neon_uminv: {
699 // Figure out the datatype of the vector operand. The UMINV instruction
700 // will zero extend the result, so we can mark as known zero all the
701 // bits larger than the element datatype. 32-bit or larget doesn't need
702 // this as those are legal types and will be handled by isel directly.
703 MVT VT = Op.getOperand(1).getValueType().getSimpleVT();
704 unsigned BitWidth = KnownZero.getBitWidth();
705 if (VT == MVT::v8i8 || VT == MVT::v16i8) {
706 assert(BitWidth >= 8 && "Unexpected width!");
707 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 8);
709 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) {
710 assert(BitWidth >= 16 && "Unexpected width!");
711 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
721 MVT AArch64TargetLowering::getScalarShiftAmountTy(EVT LHSTy) const {
725 unsigned AArch64TargetLowering::getMaximalGlobalOffset() const {
726 // FIXME: On AArch64, this depends on the type.
727 // Basically, the addressable offsets are up to 4095 * Ty.getSizeInBytes().
728 // and the offset has to be a multiple of the related size in bytes.
733 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
734 const TargetLibraryInfo *libInfo) const {
735 return AArch64::createFastISel(funcInfo, libInfo);
738 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
742 case AArch64ISD::CALL: return "AArch64ISD::CALL";
743 case AArch64ISD::ADRP: return "AArch64ISD::ADRP";
744 case AArch64ISD::ADDlow: return "AArch64ISD::ADDlow";
745 case AArch64ISD::LOADgot: return "AArch64ISD::LOADgot";
746 case AArch64ISD::RET_FLAG: return "AArch64ISD::RET_FLAG";
747 case AArch64ISD::BRCOND: return "AArch64ISD::BRCOND";
748 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
749 case AArch64ISD::FCSEL: return "AArch64ISD::FCSEL";
750 case AArch64ISD::CSINV: return "AArch64ISD::CSINV";
751 case AArch64ISD::CSNEG: return "AArch64ISD::CSNEG";
752 case AArch64ISD::CSINC: return "AArch64ISD::CSINC";
753 case AArch64ISD::THREAD_POINTER: return "AArch64ISD::THREAD_POINTER";
754 case AArch64ISD::TLSDESC_CALL: return "AArch64ISD::TLSDESC_CALL";
755 case AArch64ISD::ADC: return "AArch64ISD::ADC";
756 case AArch64ISD::SBC: return "AArch64ISD::SBC";
757 case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
758 case AArch64ISD::SUBS: return "AArch64ISD::SUBS";
759 case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
760 case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
761 case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
762 case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
763 case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
764 case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
765 case AArch64ISD::DUP: return "AArch64ISD::DUP";
766 case AArch64ISD::DUPLANE8: return "AArch64ISD::DUPLANE8";
767 case AArch64ISD::DUPLANE16: return "AArch64ISD::DUPLANE16";
768 case AArch64ISD::DUPLANE32: return "AArch64ISD::DUPLANE32";
769 case AArch64ISD::DUPLANE64: return "AArch64ISD::DUPLANE64";
770 case AArch64ISD::MOVI: return "AArch64ISD::MOVI";
771 case AArch64ISD::MOVIshift: return "AArch64ISD::MOVIshift";
772 case AArch64ISD::MOVIedit: return "AArch64ISD::MOVIedit";
773 case AArch64ISD::MOVImsl: return "AArch64ISD::MOVImsl";
774 case AArch64ISD::FMOV: return "AArch64ISD::FMOV";
775 case AArch64ISD::MVNIshift: return "AArch64ISD::MVNIshift";
776 case AArch64ISD::MVNImsl: return "AArch64ISD::MVNImsl";
777 case AArch64ISD::BICi: return "AArch64ISD::BICi";
778 case AArch64ISD::ORRi: return "AArch64ISD::ORRi";
779 case AArch64ISD::BSL: return "AArch64ISD::BSL";
780 case AArch64ISD::NEG: return "AArch64ISD::NEG";
781 case AArch64ISD::EXTR: return "AArch64ISD::EXTR";
782 case AArch64ISD::ZIP1: return "AArch64ISD::ZIP1";
783 case AArch64ISD::ZIP2: return "AArch64ISD::ZIP2";
784 case AArch64ISD::UZP1: return "AArch64ISD::UZP1";
785 case AArch64ISD::UZP2: return "AArch64ISD::UZP2";
786 case AArch64ISD::TRN1: return "AArch64ISD::TRN1";
787 case AArch64ISD::TRN2: return "AArch64ISD::TRN2";
788 case AArch64ISD::REV16: return "AArch64ISD::REV16";
789 case AArch64ISD::REV32: return "AArch64ISD::REV32";
790 case AArch64ISD::REV64: return "AArch64ISD::REV64";
791 case AArch64ISD::EXT: return "AArch64ISD::EXT";
792 case AArch64ISD::VSHL: return "AArch64ISD::VSHL";
793 case AArch64ISD::VLSHR: return "AArch64ISD::VLSHR";
794 case AArch64ISD::VASHR: return "AArch64ISD::VASHR";
795 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
796 case AArch64ISD::CMGE: return "AArch64ISD::CMGE";
797 case AArch64ISD::CMGT: return "AArch64ISD::CMGT";
798 case AArch64ISD::CMHI: return "AArch64ISD::CMHI";
799 case AArch64ISD::CMHS: return "AArch64ISD::CMHS";
800 case AArch64ISD::FCMEQ: return "AArch64ISD::FCMEQ";
801 case AArch64ISD::FCMGE: return "AArch64ISD::FCMGE";
802 case AArch64ISD::FCMGT: return "AArch64ISD::FCMGT";
803 case AArch64ISD::CMEQz: return "AArch64ISD::CMEQz";
804 case AArch64ISD::CMGEz: return "AArch64ISD::CMGEz";
805 case AArch64ISD::CMGTz: return "AArch64ISD::CMGTz";
806 case AArch64ISD::CMLEz: return "AArch64ISD::CMLEz";
807 case AArch64ISD::CMLTz: return "AArch64ISD::CMLTz";
808 case AArch64ISD::FCMEQz: return "AArch64ISD::FCMEQz";
809 case AArch64ISD::FCMGEz: return "AArch64ISD::FCMGEz";
810 case AArch64ISD::FCMGTz: return "AArch64ISD::FCMGTz";
811 case AArch64ISD::FCMLEz: return "AArch64ISD::FCMLEz";
812 case AArch64ISD::FCMLTz: return "AArch64ISD::FCMLTz";
813 case AArch64ISD::NOT: return "AArch64ISD::NOT";
814 case AArch64ISD::BIT: return "AArch64ISD::BIT";
815 case AArch64ISD::CBZ: return "AArch64ISD::CBZ";
816 case AArch64ISD::CBNZ: return "AArch64ISD::CBNZ";
817 case AArch64ISD::TBZ: return "AArch64ISD::TBZ";
818 case AArch64ISD::TBNZ: return "AArch64ISD::TBNZ";
819 case AArch64ISD::TC_RETURN: return "AArch64ISD::TC_RETURN";
820 case AArch64ISD::SITOF: return "AArch64ISD::SITOF";
821 case AArch64ISD::UITOF: return "AArch64ISD::UITOF";
822 case AArch64ISD::NVCAST: return "AArch64ISD::NVCAST";
823 case AArch64ISD::SQSHL_I: return "AArch64ISD::SQSHL_I";
824 case AArch64ISD::UQSHL_I: return "AArch64ISD::UQSHL_I";
825 case AArch64ISD::SRSHR_I: return "AArch64ISD::SRSHR_I";
826 case AArch64ISD::URSHR_I: return "AArch64ISD::URSHR_I";
827 case AArch64ISD::SQSHLU_I: return "AArch64ISD::SQSHLU_I";
828 case AArch64ISD::WrapperLarge: return "AArch64ISD::WrapperLarge";
829 case AArch64ISD::LD2post: return "AArch64ISD::LD2post";
830 case AArch64ISD::LD3post: return "AArch64ISD::LD3post";
831 case AArch64ISD::LD4post: return "AArch64ISD::LD4post";
832 case AArch64ISD::ST2post: return "AArch64ISD::ST2post";
833 case AArch64ISD::ST3post: return "AArch64ISD::ST3post";
834 case AArch64ISD::ST4post: return "AArch64ISD::ST4post";
835 case AArch64ISD::LD1x2post: return "AArch64ISD::LD1x2post";
836 case AArch64ISD::LD1x3post: return "AArch64ISD::LD1x3post";
837 case AArch64ISD::LD1x4post: return "AArch64ISD::LD1x4post";
838 case AArch64ISD::ST1x2post: return "AArch64ISD::ST1x2post";
839 case AArch64ISD::ST1x3post: return "AArch64ISD::ST1x3post";
840 case AArch64ISD::ST1x4post: return "AArch64ISD::ST1x4post";
841 case AArch64ISD::LD1DUPpost: return "AArch64ISD::LD1DUPpost";
842 case AArch64ISD::LD2DUPpost: return "AArch64ISD::LD2DUPpost";
843 case AArch64ISD::LD3DUPpost: return "AArch64ISD::LD3DUPpost";
844 case AArch64ISD::LD4DUPpost: return "AArch64ISD::LD4DUPpost";
845 case AArch64ISD::LD1LANEpost: return "AArch64ISD::LD1LANEpost";
846 case AArch64ISD::LD2LANEpost: return "AArch64ISD::LD2LANEpost";
847 case AArch64ISD::LD3LANEpost: return "AArch64ISD::LD3LANEpost";
848 case AArch64ISD::LD4LANEpost: return "AArch64ISD::LD4LANEpost";
849 case AArch64ISD::ST2LANEpost: return "AArch64ISD::ST2LANEpost";
850 case AArch64ISD::ST3LANEpost: return "AArch64ISD::ST3LANEpost";
851 case AArch64ISD::ST4LANEpost: return "AArch64ISD::ST4LANEpost";
852 case AArch64ISD::SMULL: return "AArch64ISD::SMULL";
853 case AArch64ISD::UMULL: return "AArch64ISD::UMULL";
858 AArch64TargetLowering::EmitF128CSEL(MachineInstr *MI,
859 MachineBasicBlock *MBB) const {
860 // We materialise the F128CSEL pseudo-instruction as some control flow and a
864 // [... previous instrs leading to comparison ...]
870 // Dest = PHI [IfTrue, TrueBB], [IfFalse, OrigBB]
872 const TargetInstrInfo *TII =
873 getTargetMachine().getSubtargetImpl()->getInstrInfo();
874 MachineFunction *MF = MBB->getParent();
875 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
876 DebugLoc DL = MI->getDebugLoc();
877 MachineFunction::iterator It = MBB;
880 unsigned DestReg = MI->getOperand(0).getReg();
881 unsigned IfTrueReg = MI->getOperand(1).getReg();
882 unsigned IfFalseReg = MI->getOperand(2).getReg();
883 unsigned CondCode = MI->getOperand(3).getImm();
884 bool NZCVKilled = MI->getOperand(4).isKill();
886 MachineBasicBlock *TrueBB = MF->CreateMachineBasicBlock(LLVM_BB);
887 MachineBasicBlock *EndBB = MF->CreateMachineBasicBlock(LLVM_BB);
888 MF->insert(It, TrueBB);
889 MF->insert(It, EndBB);
891 // Transfer rest of current basic-block to EndBB
892 EndBB->splice(EndBB->begin(), MBB, std::next(MachineBasicBlock::iterator(MI)),
894 EndBB->transferSuccessorsAndUpdatePHIs(MBB);
896 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
897 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
898 MBB->addSuccessor(TrueBB);
899 MBB->addSuccessor(EndBB);
901 // TrueBB falls through to the end.
902 TrueBB->addSuccessor(EndBB);
905 TrueBB->addLiveIn(AArch64::NZCV);
906 EndBB->addLiveIn(AArch64::NZCV);
909 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
915 MI->eraseFromParent();
920 AArch64TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
921 MachineBasicBlock *BB) const {
922 switch (MI->getOpcode()) {
927 llvm_unreachable("Unexpected instruction for custom inserter!");
929 case AArch64::F128CSEL:
930 return EmitF128CSEL(MI, BB);
932 case TargetOpcode::STACKMAP:
933 case TargetOpcode::PATCHPOINT:
934 return emitPatchPoint(MI, BB);
938 //===----------------------------------------------------------------------===//
939 // AArch64 Lowering private implementation.
940 //===----------------------------------------------------------------------===//
942 //===----------------------------------------------------------------------===//
944 //===----------------------------------------------------------------------===//
946 /// changeIntCCToAArch64CC - Convert a DAG integer condition code to an AArch64
948 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) {
951 llvm_unreachable("Unknown condition code!");
953 return AArch64CC::NE;
955 return AArch64CC::EQ;
957 return AArch64CC::GT;
959 return AArch64CC::GE;
961 return AArch64CC::LT;
963 return AArch64CC::LE;
965 return AArch64CC::HI;
967 return AArch64CC::HS;
969 return AArch64CC::LO;
971 return AArch64CC::LS;
975 /// changeFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64 CC.
976 static void changeFPCCToAArch64CC(ISD::CondCode CC,
977 AArch64CC::CondCode &CondCode,
978 AArch64CC::CondCode &CondCode2) {
979 CondCode2 = AArch64CC::AL;
982 llvm_unreachable("Unknown FP condition!");
985 CondCode = AArch64CC::EQ;
989 CondCode = AArch64CC::GT;
993 CondCode = AArch64CC::GE;
996 CondCode = AArch64CC::MI;
999 CondCode = AArch64CC::LS;
1002 CondCode = AArch64CC::MI;
1003 CondCode2 = AArch64CC::GT;
1006 CondCode = AArch64CC::VC;
1009 CondCode = AArch64CC::VS;
1012 CondCode = AArch64CC::EQ;
1013 CondCode2 = AArch64CC::VS;
1016 CondCode = AArch64CC::HI;
1019 CondCode = AArch64CC::PL;
1023 CondCode = AArch64CC::LT;
1027 CondCode = AArch64CC::LE;
1031 CondCode = AArch64CC::NE;
1036 /// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
1037 /// CC usable with the vector instructions. Fewer operations are available
1038 /// without a real NZCV register, so we have to use less efficient combinations
1039 /// to get the same effect.
1040 static void changeVectorFPCCToAArch64CC(ISD::CondCode CC,
1041 AArch64CC::CondCode &CondCode,
1042 AArch64CC::CondCode &CondCode2,
1047 // Mostly the scalar mappings work fine.
1048 changeFPCCToAArch64CC(CC, CondCode, CondCode2);
1051 Invert = true; // Fallthrough
1053 CondCode = AArch64CC::MI;
1054 CondCode2 = AArch64CC::GE;
1061 // All of the compare-mask comparisons are ordered, but we can switch
1062 // between the two by a double inversion. E.g. ULE == !OGT.
1064 changeFPCCToAArch64CC(getSetCCInverse(CC, false), CondCode, CondCode2);
1069 static bool isLegalArithImmed(uint64_t C) {
1070 // Matches AArch64DAGToDAGISel::SelectArithImmed().
1071 return (C >> 12 == 0) || ((C & 0xFFFULL) == 0 && C >> 24 == 0);
1074 static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1075 SDLoc dl, SelectionDAG &DAG) {
1076 EVT VT = LHS.getValueType();
1078 if (VT.isFloatingPoint())
1079 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS);
1081 // The CMP instruction is just an alias for SUBS, and representing it as
1082 // SUBS means that it's possible to get CSE with subtract operations.
1083 // A later phase can perform the optimization of setting the destination
1084 // register to WZR/XZR if it ends up being unused.
1085 unsigned Opcode = AArch64ISD::SUBS;
1087 if (RHS.getOpcode() == ISD::SUB && isa<ConstantSDNode>(RHS.getOperand(0)) &&
1088 cast<ConstantSDNode>(RHS.getOperand(0))->getZExtValue() == 0 &&
1089 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1090 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1091 // the grounds that "op1 - (-op2) == op1 + op2". However, the C and V flags
1092 // can be set differently by this operation. It comes down to whether
1093 // "SInt(~op2)+1 == SInt(~op2+1)" (and the same for UInt). If they are then
1094 // everything is fine. If not then the optimization is wrong. Thus general
1095 // comparisons are only valid if op2 != 0.
1097 // So, finally, the only LLVM-native comparisons that don't mention C and V
1098 // are SETEQ and SETNE. They're the only ones we can safely use CMN for in
1099 // the absence of information about op2.
1100 Opcode = AArch64ISD::ADDS;
1101 RHS = RHS.getOperand(1);
1102 } else if (LHS.getOpcode() == ISD::AND && isa<ConstantSDNode>(RHS) &&
1103 cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
1104 !isUnsignedIntSetCC(CC)) {
1105 // Similarly, (CMP (and X, Y), 0) can be implemented with a TST
1106 // (a.k.a. ANDS) except that the flags are only guaranteed to work for one
1107 // of the signed comparisons.
1108 Opcode = AArch64ISD::ANDS;
1109 RHS = LHS.getOperand(1);
1110 LHS = LHS.getOperand(0);
1113 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
1117 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1118 SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
1120 AArch64CC::CondCode AArch64CC;
1121 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1122 EVT VT = RHS.getValueType();
1123 uint64_t C = RHSC->getZExtValue();
1124 if (!isLegalArithImmed(C)) {
1125 // Constant does not fit, try adjusting it by one?
1131 if ((VT == MVT::i32 && C != 0x80000000 &&
1132 isLegalArithImmed((uint32_t)(C - 1))) ||
1133 (VT == MVT::i64 && C != 0x80000000ULL &&
1134 isLegalArithImmed(C - 1ULL))) {
1135 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1136 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1137 RHS = DAG.getConstant(C, VT);
1142 if ((VT == MVT::i32 && C != 0 &&
1143 isLegalArithImmed((uint32_t)(C - 1))) ||
1144 (VT == MVT::i64 && C != 0ULL && isLegalArithImmed(C - 1ULL))) {
1145 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1146 C = (VT == MVT::i32) ? (uint32_t)(C - 1) : C - 1;
1147 RHS = DAG.getConstant(C, VT);
1152 if ((VT == MVT::i32 && C != INT32_MAX &&
1153 isLegalArithImmed((uint32_t)(C + 1))) ||
1154 (VT == MVT::i64 && C != INT64_MAX &&
1155 isLegalArithImmed(C + 1ULL))) {
1156 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1157 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1158 RHS = DAG.getConstant(C, VT);
1163 if ((VT == MVT::i32 && C != UINT32_MAX &&
1164 isLegalArithImmed((uint32_t)(C + 1))) ||
1165 (VT == MVT::i64 && C != UINT64_MAX &&
1166 isLegalArithImmed(C + 1ULL))) {
1167 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1168 C = (VT == MVT::i32) ? (uint32_t)(C + 1) : C + 1;
1169 RHS = DAG.getConstant(C, VT);
1175 // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
1176 // For the i8 operand, the largest immediate is 255, so this can be easily
1177 // encoded in the compare instruction. For the i16 operand, however, the
1178 // largest immediate cannot be encoded in the compare.
1179 // Therefore, use a sign extending load and cmn to avoid materializing the -1
1180 // constant. For example,
1182 // ldrh w0, [x0, #0]
1185 // ldrsh w0, [x0, #0]
1187 // Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
1188 // if and only if (sext LHS) == (sext RHS). The checks are in place to ensure
1189 // both the LHS and RHS are truely zero extended and to make sure the
1190 // transformation is profitable.
1191 if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
1192 if ((cast<ConstantSDNode>(RHS)->getZExtValue() >> 16 == 0) &&
1193 isa<LoadSDNode>(LHS)) {
1194 if (cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
1195 cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
1196 LHS.getNode()->hasNUsesOfValue(1, 0)) {
1197 int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
1198 if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
1200 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
1201 DAG.getValueType(MVT::i16));
1202 Cmp = emitComparison(SExt,
1203 DAG.getConstant(ValueofRHS, RHS.getValueType()),
1205 AArch64CC = changeIntCCToAArch64CC(CC);
1206 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1212 Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
1213 AArch64CC = changeIntCCToAArch64CC(CC);
1214 AArch64cc = DAG.getConstant(AArch64CC, MVT::i32);
1218 static std::pair<SDValue, SDValue>
1219 getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
1220 assert((Op.getValueType() == MVT::i32 || Op.getValueType() == MVT::i64) &&
1221 "Unsupported value type");
1222 SDValue Value, Overflow;
1224 SDValue LHS = Op.getOperand(0);
1225 SDValue RHS = Op.getOperand(1);
1227 switch (Op.getOpcode()) {
1229 llvm_unreachable("Unknown overflow instruction!");
1231 Opc = AArch64ISD::ADDS;
1235 Opc = AArch64ISD::ADDS;
1239 Opc = AArch64ISD::SUBS;
1243 Opc = AArch64ISD::SUBS;
1246 // Multiply needs a little bit extra work.
1250 bool IsSigned = (Op.getOpcode() == ISD::SMULO) ? true : false;
1251 if (Op.getValueType() == MVT::i32) {
1252 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1253 // For a 32 bit multiply with overflow check we want the instruction
1254 // selector to generate a widening multiply (SMADDL/UMADDL). For that we
1255 // need to generate the following pattern:
1256 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1257 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS);
1258 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS);
1259 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1260 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1261 DAG.getConstant(0, MVT::i64));
1262 // On AArch64 the upper 32 bits are always zero extended for a 32 bit
1263 // operation. We need to clear out the upper 32 bits, because we used a
1264 // widening multiply that wrote all 64 bits. In the end this should be a
1266 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1268 // The signed overflow check requires more than just a simple check for
1269 // any bit set in the upper 32 bits of the result. These bits could be
1270 // just the sign bits of a negative number. To perform the overflow
1271 // check we have to arithmetic shift right the 32nd bit of the result by
1272 // 31 bits. Then we compare the result to the upper 32 bits.
1273 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
1274 DAG.getConstant(32, MVT::i64));
1275 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits);
1276 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value,
1277 DAG.getConstant(31, MVT::i64));
1278 // It is important that LowerBits is last, otherwise the arithmetic
1279 // shift will not be folded into the compare (SUBS).
1280 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32);
1281 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1284 // The overflow check for unsigned multiply is easy. We only need to
1285 // check if any of the upper 32 bits are set. This can be done with a
1286 // CMP (shifted register). For that we need to generate the following
1288 // (i64 AArch64ISD::SUBS i64 0, (i64 srl i64 %Mul, i64 32)
1289 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
1290 DAG.getConstant(32, MVT::i64));
1291 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1293 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1294 UpperBits).getValue(1);
1298 assert(Op.getValueType() == MVT::i64 && "Expected an i64 value type");
1299 // For the 64 bit multiply
1300 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS);
1302 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS);
1303 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value,
1304 DAG.getConstant(63, MVT::i64));
1305 // It is important that LowerBits is last, otherwise the arithmetic
1306 // shift will not be folded into the compare (SUBS).
1307 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1308 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits)
1311 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS);
1312 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::i32);
1314 DAG.getNode(AArch64ISD::SUBS, DL, VTs, DAG.getConstant(0, MVT::i64),
1315 UpperBits).getValue(1);
1322 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::i32);
1324 // Emit the AArch64 operation with overflow check.
1325 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS);
1326 Overflow = Value.getValue(1);
1328 return std::make_pair(Value, Overflow);
1331 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1332 RTLIB::Libcall Call) const {
1333 SmallVector<SDValue, 2> Ops;
1334 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1335 Ops.push_back(Op.getOperand(i));
1337 return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false,
1341 static SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) {
1342 SDValue Sel = Op.getOperand(0);
1343 SDValue Other = Op.getOperand(1);
1345 // If neither operand is a SELECT_CC, give up.
1346 if (Sel.getOpcode() != ISD::SELECT_CC)
1347 std::swap(Sel, Other);
1348 if (Sel.getOpcode() != ISD::SELECT_CC)
1351 // The folding we want to perform is:
1352 // (xor x, (select_cc a, b, cc, 0, -1) )
1354 // (csel x, (xor x, -1), cc ...)
1356 // The latter will get matched to a CSINV instruction.
1358 ISD::CondCode CC = cast<CondCodeSDNode>(Sel.getOperand(4))->get();
1359 SDValue LHS = Sel.getOperand(0);
1360 SDValue RHS = Sel.getOperand(1);
1361 SDValue TVal = Sel.getOperand(2);
1362 SDValue FVal = Sel.getOperand(3);
1365 // FIXME: This could be generalized to non-integer comparisons.
1366 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
1369 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
1370 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
1372 // The the values aren't constants, this isn't the pattern we're looking for.
1373 if (!CFVal || !CTVal)
1376 // We can commute the SELECT_CC by inverting the condition. This
1377 // might be needed to make this fit into a CSINV pattern.
1378 if (CTVal->isAllOnesValue() && CFVal->isNullValue()) {
1379 std::swap(TVal, FVal);
1380 std::swap(CTVal, CFVal);
1381 CC = ISD::getSetCCInverse(CC, true);
1384 // If the constants line up, perform the transform!
1385 if (CTVal->isNullValue() && CFVal->isAllOnesValue()) {
1387 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
1390 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
1391 DAG.getConstant(-1ULL, Other.getValueType()));
1393 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1400 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
1401 EVT VT = Op.getValueType();
1403 // Let legalize expand this if it isn't a legal type yet.
1404 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
1407 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
1410 bool ExtraOp = false;
1411 switch (Op.getOpcode()) {
1413 llvm_unreachable("Invalid code");
1415 Opc = AArch64ISD::ADDS;
1418 Opc = AArch64ISD::SUBS;
1421 Opc = AArch64ISD::ADCS;
1425 Opc = AArch64ISD::SBCS;
1431 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1));
1432 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1),
1436 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
1437 // Let legalize expand this if it isn't a legal type yet.
1438 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
1441 AArch64CC::CondCode CC;
1442 // The actual operation that sets the overflow or carry flag.
1443 SDValue Value, Overflow;
1444 std::tie(Value, Overflow) = getAArch64XALUOOp(CC, Op, DAG);
1446 // We use 0 and 1 as false and true values.
1447 SDValue TVal = DAG.getConstant(1, MVT::i32);
1448 SDValue FVal = DAG.getConstant(0, MVT::i32);
1450 // We use an inverted condition, because the conditional select is inverted
1451 // too. This will allow it to be selected to a single instruction:
1452 // CSINC Wd, WZR, WZR, invert(cond).
1453 SDValue CCVal = DAG.getConstant(getInvertedCondCode(CC), MVT::i32);
1454 Overflow = DAG.getNode(AArch64ISD::CSEL, SDLoc(Op), MVT::i32, FVal, TVal,
1457 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
1458 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), VTs, Value, Overflow);
1461 // Prefetch operands are:
1462 // 1: Address to prefetch
1464 // 3: int locality (0 = no locality ... 3 = extreme locality)
1465 // 4: bool isDataCache
1466 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
1468 unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
1469 unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
1470 unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
1472 bool IsStream = !Locality;
1473 // When the locality number is set
1475 // The front-end should have filtered out the out-of-range values
1476 assert(Locality <= 3 && "Prefetch locality out-of-range");
1477 // The locality degree is the opposite of the cache speed.
1478 // Put the number the other way around.
1479 // The encoding starts at 0 for level 1
1480 Locality = 3 - Locality;
1483 // built the mask value encoding the expected behavior.
1484 unsigned PrfOp = (IsWrite << 4) | // Load/Store bit
1485 (!IsData << 3) | // IsDataCache bit
1486 (Locality << 1) | // Cache level bits
1487 (unsigned)IsStream; // Stream bit
1488 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0),
1489 DAG.getConstant(PrfOp, MVT::i32), Op.getOperand(1));
1492 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1493 SelectionDAG &DAG) const {
1494 assert(Op.getValueType() == MVT::f128 && "Unexpected lowering");
1497 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
1499 return LowerF128Call(Op, DAG, LC);
1502 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1503 SelectionDAG &DAG) const {
1504 if (Op.getOperand(0).getValueType() != MVT::f128) {
1505 // It's legal except when f128 is involved
1510 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
1512 // FP_ROUND node has a second operand indicating whether it is known to be
1513 // precise. That doesn't take part in the LibCall so we can't directly use
1515 SDValue SrcVal = Op.getOperand(0);
1516 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
1517 /*isSigned*/ false, SDLoc(Op)).first;
1520 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1521 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1522 // Any additional optimization in this function should be recorded
1523 // in the cost tables.
1524 EVT InVT = Op.getOperand(0).getValueType();
1525 EVT VT = Op.getValueType();
1527 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1530 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
1532 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
1535 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1538 MVT::getVectorVT(MVT::getFloatingPointVT(VT.getScalarSizeInBits()),
1539 VT.getVectorNumElements());
1540 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0));
1541 return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
1544 // Type changing conversions are illegal.
1548 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
1549 SelectionDAG &DAG) const {
1550 if (Op.getOperand(0).getValueType().isVector())
1551 return LowerVectorFP_TO_INT(Op, DAG);
1553 if (Op.getOperand(0).getValueType() != MVT::f128) {
1554 // It's legal except when f128 is involved
1559 if (Op.getOpcode() == ISD::FP_TO_SINT)
1560 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(), Op.getValueType());
1562 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType());
1564 SmallVector<SDValue, 2> Ops;
1565 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i)
1566 Ops.push_back(Op.getOperand(i));
1568 return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false,
1572 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1573 // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
1574 // Any additional optimization in this function should be recorded
1575 // in the cost tables.
1576 EVT VT = Op.getValueType();
1578 SDValue In = Op.getOperand(0);
1579 EVT InVT = In.getValueType();
1581 if (VT.getSizeInBits() < InVT.getSizeInBits()) {
1583 MVT::getVectorVT(MVT::getFloatingPointVT(InVT.getScalarSizeInBits()),
1584 InVT.getVectorNumElements());
1585 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In);
1586 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0));
1589 if (VT.getSizeInBits() > InVT.getSizeInBits()) {
1591 Op.getOpcode() == ISD::SINT_TO_FP ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1592 EVT CastVT = VT.changeVectorElementTypeToInteger();
1593 In = DAG.getNode(CastOpc, dl, CastVT, In);
1594 return DAG.getNode(Op.getOpcode(), dl, VT, In);
1600 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
1601 SelectionDAG &DAG) const {
1602 if (Op.getValueType().isVector())
1603 return LowerVectorINT_TO_FP(Op, DAG);
1605 // i128 conversions are libcalls.
1606 if (Op.getOperand(0).getValueType() == MVT::i128)
1609 // Other conversions are legal, unless it's to the completely software-based
1611 if (Op.getValueType() != MVT::f128)
1615 if (Op.getOpcode() == ISD::SINT_TO_FP)
1616 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1618 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(), Op.getValueType());
1620 return LowerF128Call(Op, DAG, LC);
1623 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
1624 SelectionDAG &DAG) const {
1625 // For iOS, we want to call an alternative entry point: __sincos_stret,
1626 // which returns the values in two S / D registers.
1628 SDValue Arg = Op.getOperand(0);
1629 EVT ArgVT = Arg.getValueType();
1630 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1637 Entry.isSExt = false;
1638 Entry.isZExt = false;
1639 Args.push_back(Entry);
1641 const char *LibcallName =
1642 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
1643 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
1645 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
1646 TargetLowering::CallLoweringInfo CLI(DAG);
1647 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1648 .setCallee(CallingConv::Fast, RetTy, Callee, std::move(Args), 0);
1650 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1651 return CallResult.first;
1654 static SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) {
1655 if (Op.getValueType() != MVT::f16)
1658 assert(Op.getOperand(0).getValueType() == MVT::i16);
1661 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0));
1662 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);
1664 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f16, Op,
1665 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
1669 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
1670 if (OrigVT.getSizeInBits() >= 64)
1673 assert(OrigVT.isSimple() && "Expecting a simple value type");
1675 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
1676 switch (OrigSimpleTy) {
1677 default: llvm_unreachable("Unexpected Vector Type");
1686 static SDValue addRequiredExtensionForVectorMULL(SDValue N, SelectionDAG &DAG,
1689 unsigned ExtOpcode) {
1690 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
1691 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
1692 // 64-bits we need to insert a new extension so that it will be 64-bits.
1693 assert(ExtTy.is128BitVector() && "Unexpected extension size");
1694 if (OrigTy.getSizeInBits() >= 64)
1697 // Must extend size to at least 64 bits to be used as an operand for VMULL.
1698 EVT NewVT = getExtensionTo64Bits(OrigTy);
1700 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
1703 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
1705 EVT VT = N->getValueType(0);
1707 if (N->getOpcode() != ISD::BUILD_VECTOR)
1710 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1711 SDNode *Elt = N->getOperand(i).getNode();
1712 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
1713 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1714 unsigned HalfSize = EltSize / 2;
1716 if (!isIntN(HalfSize, C->getSExtValue()))
1719 if (!isUIntN(HalfSize, C->getZExtValue()))
1730 static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
1731 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
1732 return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
1733 N->getOperand(0)->getValueType(0),
1737 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
1738 EVT VT = N->getValueType(0);
1739 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
1740 unsigned NumElts = VT.getVectorNumElements();
1741 MVT TruncVT = MVT::getIntegerVT(EltSize);
1742 SmallVector<SDValue, 8> Ops;
1743 for (unsigned i = 0; i != NumElts; ++i) {
1744 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
1745 const APInt &CInt = C->getAPIntValue();
1746 // Element types smaller than 32 bits are not legal, so use i32 elements.
1747 // The values are implicitly truncated so sext vs. zext doesn't matter.
1748 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
1750 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
1751 MVT::getVectorVT(TruncVT, NumElts), Ops);
1754 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
1755 if (N->getOpcode() == ISD::SIGN_EXTEND)
1757 if (isExtendedBUILD_VECTOR(N, DAG, true))
1762 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
1763 if (N->getOpcode() == ISD::ZERO_EXTEND)
1765 if (isExtendedBUILD_VECTOR(N, DAG, false))
1770 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
1771 unsigned Opcode = N->getOpcode();
1772 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1773 SDNode *N0 = N->getOperand(0).getNode();
1774 SDNode *N1 = N->getOperand(1).getNode();
1775 return N0->hasOneUse() && N1->hasOneUse() &&
1776 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
1781 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
1782 unsigned Opcode = N->getOpcode();
1783 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
1784 SDNode *N0 = N->getOperand(0).getNode();
1785 SDNode *N1 = N->getOperand(1).getNode();
1786 return N0->hasOneUse() && N1->hasOneUse() &&
1787 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
1792 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
1793 // Multiplications are only custom-lowered for 128-bit vectors so that
1794 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
1795 EVT VT = Op.getValueType();
1796 assert(VT.is128BitVector() && VT.isInteger() &&
1797 "unexpected type for custom-lowering ISD::MUL");
1798 SDNode *N0 = Op.getOperand(0).getNode();
1799 SDNode *N1 = Op.getOperand(1).getNode();
1800 unsigned NewOpc = 0;
1802 bool isN0SExt = isSignExtended(N0, DAG);
1803 bool isN1SExt = isSignExtended(N1, DAG);
1804 if (isN0SExt && isN1SExt)
1805 NewOpc = AArch64ISD::SMULL;
1807 bool isN0ZExt = isZeroExtended(N0, DAG);
1808 bool isN1ZExt = isZeroExtended(N1, DAG);
1809 if (isN0ZExt && isN1ZExt)
1810 NewOpc = AArch64ISD::UMULL;
1811 else if (isN1SExt || isN1ZExt) {
1812 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
1813 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
1814 if (isN1SExt && isAddSubSExt(N0, DAG)) {
1815 NewOpc = AArch64ISD::SMULL;
1817 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
1818 NewOpc = AArch64ISD::UMULL;
1820 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
1822 NewOpc = AArch64ISD::UMULL;
1828 if (VT == MVT::v2i64)
1829 // Fall through to expand this. It is not legal.
1832 // Other vector multiplications are legal.
1837 // Legalize to a S/UMULL instruction
1840 SDValue Op1 = skipExtensionForVectorMULL(N1, DAG);
1842 Op0 = skipExtensionForVectorMULL(N0, DAG);
1843 assert(Op0.getValueType().is64BitVector() &&
1844 Op1.getValueType().is64BitVector() &&
1845 "unexpected types for extended operands to VMULL");
1846 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
1848 // Optimizing (zext A + zext B) * C, to (S/UMULL A, C) + (S/UMULL B, C) during
1849 // isel lowering to take advantage of no-stall back to back s/umul + s/umla.
1850 // This is true for CPUs with accumulate forwarding such as Cortex-A53/A57
1851 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG);
1852 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG);
1853 EVT Op1VT = Op1.getValueType();
1854 return DAG.getNode(N0->getOpcode(), DL, VT,
1855 DAG.getNode(NewOpc, DL, VT,
1856 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
1857 DAG.getNode(NewOpc, DL, VT,
1858 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
1861 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
1862 SelectionDAG &DAG) const {
1863 switch (Op.getOpcode()) {
1865 llvm_unreachable("unimplemented operand");
1868 return LowerBITCAST(Op, DAG);
1869 case ISD::GlobalAddress:
1870 return LowerGlobalAddress(Op, DAG);
1871 case ISD::GlobalTLSAddress:
1872 return LowerGlobalTLSAddress(Op, DAG);
1874 return LowerSETCC(Op, DAG);
1876 return LowerBR_CC(Op, DAG);
1878 return LowerSELECT(Op, DAG);
1879 case ISD::SELECT_CC:
1880 return LowerSELECT_CC(Op, DAG);
1881 case ISD::JumpTable:
1882 return LowerJumpTable(Op, DAG);
1883 case ISD::ConstantPool:
1884 return LowerConstantPool(Op, DAG);
1885 case ISD::BlockAddress:
1886 return LowerBlockAddress(Op, DAG);
1888 return LowerVASTART(Op, DAG);
1890 return LowerVACOPY(Op, DAG);
1892 return LowerVAARG(Op, DAG);
1897 return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
1904 return LowerXALUO(Op, DAG);
1906 return LowerF128Call(Op, DAG, RTLIB::ADD_F128);
1908 return LowerF128Call(Op, DAG, RTLIB::SUB_F128);
1910 return LowerF128Call(Op, DAG, RTLIB::MUL_F128);
1912 return LowerF128Call(Op, DAG, RTLIB::DIV_F128);
1914 return LowerFP_ROUND(Op, DAG);
1915 case ISD::FP_EXTEND:
1916 return LowerFP_EXTEND(Op, DAG);
1917 case ISD::FRAMEADDR:
1918 return LowerFRAMEADDR(Op, DAG);
1919 case ISD::RETURNADDR:
1920 return LowerRETURNADDR(Op, DAG);
1921 case ISD::INSERT_VECTOR_ELT:
1922 return LowerINSERT_VECTOR_ELT(Op, DAG);
1923 case ISD::EXTRACT_VECTOR_ELT:
1924 return LowerEXTRACT_VECTOR_ELT(Op, DAG);
1925 case ISD::BUILD_VECTOR:
1926 return LowerBUILD_VECTOR(Op, DAG);
1927 case ISD::VECTOR_SHUFFLE:
1928 return LowerVECTOR_SHUFFLE(Op, DAG);
1929 case ISD::EXTRACT_SUBVECTOR:
1930 return LowerEXTRACT_SUBVECTOR(Op, DAG);
1934 return LowerVectorSRA_SRL_SHL(Op, DAG);
1935 case ISD::SHL_PARTS:
1936 return LowerShiftLeftParts(Op, DAG);
1937 case ISD::SRL_PARTS:
1938 case ISD::SRA_PARTS:
1939 return LowerShiftRightParts(Op, DAG);
1941 return LowerCTPOP(Op, DAG);
1942 case ISD::FCOPYSIGN:
1943 return LowerFCOPYSIGN(Op, DAG);
1945 return LowerVectorAND(Op, DAG);
1947 return LowerVectorOR(Op, DAG);
1949 return LowerXOR(Op, DAG);
1951 return LowerPREFETCH(Op, DAG);
1952 case ISD::SINT_TO_FP:
1953 case ISD::UINT_TO_FP:
1954 return LowerINT_TO_FP(Op, DAG);
1955 case ISD::FP_TO_SINT:
1956 case ISD::FP_TO_UINT:
1957 return LowerFP_TO_INT(Op, DAG);
1959 return LowerFSINCOS(Op, DAG);
1961 return LowerMUL(Op, DAG);
1965 /// getFunctionAlignment - Return the Log2 alignment of this function.
1966 unsigned AArch64TargetLowering::getFunctionAlignment(const Function *F) const {
1970 //===----------------------------------------------------------------------===//
1971 // Calling Convention Implementation
1972 //===----------------------------------------------------------------------===//
1974 #include "AArch64GenCallingConv.inc"
1976 /// Selects the correct CCAssignFn for a given CallingConvention value.
1977 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
1978 bool IsVarArg) const {
1981 llvm_unreachable("Unsupported calling convention.");
1982 case CallingConv::WebKit_JS:
1983 return CC_AArch64_WebKit_JS;
1984 case CallingConv::C:
1985 case CallingConv::Fast:
1986 if (!Subtarget->isTargetDarwin())
1987 return CC_AArch64_AAPCS;
1988 return IsVarArg ? CC_AArch64_DarwinPCS_VarArg : CC_AArch64_DarwinPCS;
1992 SDValue AArch64TargetLowering::LowerFormalArguments(
1993 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1994 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
1995 SmallVectorImpl<SDValue> &InVals) const {
1996 MachineFunction &MF = DAG.getMachineFunction();
1997 MachineFrameInfo *MFI = MF.getFrameInfo();
1999 // Assign locations to all of the incoming arguments.
2000 SmallVector<CCValAssign, 16> ArgLocs;
2001 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2004 // At this point, Ins[].VT may already be promoted to i32. To correctly
2005 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2006 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2007 // Since AnalyzeFormalArguments uses Ins[].VT for both ValVT and LocVT, here
2008 // we use a special version of AnalyzeFormalArguments to pass in ValVT and
2010 unsigned NumArgs = Ins.size();
2011 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2012 unsigned CurArgIdx = 0;
2013 for (unsigned i = 0; i != NumArgs; ++i) {
2014 MVT ValVT = Ins[i].VT;
2015 std::advance(CurOrigArg, Ins[i].OrigArgIndex - CurArgIdx);
2016 CurArgIdx = Ins[i].OrigArgIndex;
2018 // Get type of the original argument.
2019 EVT ActualVT = getValueType(CurOrigArg->getType(), /*AllowUnknown*/ true);
2020 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : MVT::Other;
2021 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2022 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2024 else if (ActualMVT == MVT::i16)
2027 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2029 AssignFn(i, ValVT, ValVT, CCValAssign::Full, Ins[i].Flags, CCInfo);
2030 assert(!Res && "Call operand has unhandled type");
2033 assert(ArgLocs.size() == Ins.size());
2034 SmallVector<SDValue, 16> ArgValues;
2035 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2036 CCValAssign &VA = ArgLocs[i];
2038 if (Ins[i].Flags.isByVal()) {
2039 // Byval is used for HFAs in the PCS, but the system should work in a
2040 // non-compliant manner for larger structs.
2041 EVT PtrTy = getPointerTy();
2042 int Size = Ins[i].Flags.getByValSize();
2043 unsigned NumRegs = (Size + 7) / 8;
2045 // FIXME: This works on big-endian for composite byvals, which are the common
2046 // case. It should also work for fundamental types too.
2048 MFI->CreateFixedObject(8 * NumRegs, VA.getLocMemOffset(), false);
2049 SDValue FrameIdxN = DAG.getFrameIndex(FrameIdx, PtrTy);
2050 InVals.push_back(FrameIdxN);
2055 if (VA.isRegLoc()) {
2056 // Arguments stored in registers.
2057 EVT RegVT = VA.getLocVT();
2060 const TargetRegisterClass *RC;
2062 if (RegVT == MVT::i32)
2063 RC = &AArch64::GPR32RegClass;
2064 else if (RegVT == MVT::i64)
2065 RC = &AArch64::GPR64RegClass;
2066 else if (RegVT == MVT::f16)
2067 RC = &AArch64::FPR16RegClass;
2068 else if (RegVT == MVT::f32)
2069 RC = &AArch64::FPR32RegClass;
2070 else if (RegVT == MVT::f64 || RegVT.is64BitVector())
2071 RC = &AArch64::FPR64RegClass;
2072 else if (RegVT == MVT::f128 || RegVT.is128BitVector())
2073 RC = &AArch64::FPR128RegClass;
2075 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2077 // Transform the arguments in physical registers into virtual ones.
2078 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2079 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
2081 // If this is an 8, 16 or 32-bit value, it is really passed promoted
2082 // to 64 bits. Insert an assert[sz]ext to capture this, then
2083 // truncate to the right size.
2084 switch (VA.getLocInfo()) {
2086 llvm_unreachable("Unknown loc info!");
2087 case CCValAssign::Full:
2089 case CCValAssign::BCvt:
2090 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);
2092 case CCValAssign::AExt:
2093 case CCValAssign::SExt:
2094 case CCValAssign::ZExt:
2095 // SelectionDAGBuilder will insert appropriate AssertZExt & AssertSExt
2096 // nodes after our lowering.
2097 assert(RegVT == Ins[i].VT && "incorrect register location selected");
2101 InVals.push_back(ArgValue);
2103 } else { // VA.isRegLoc()
2104 assert(VA.isMemLoc() && "CCValAssign is neither reg nor mem");
2105 unsigned ArgOffset = VA.getLocMemOffset();
2106 unsigned ArgSize = VA.getValVT().getSizeInBits() / 8;
2108 uint32_t BEAlign = 0;
2109 if (ArgSize < 8 && !Subtarget->isLittleEndian())
2110 BEAlign = 8 - ArgSize;
2112 int FI = MFI->CreateFixedObject(ArgSize, ArgOffset + BEAlign, true);
2114 // Create load nodes to retrieve arguments from the stack.
2115 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2118 // For NON_EXTLOAD, generic code in getLoad assert(ValVT == MemVT)
2119 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2120 MVT MemVT = VA.getValVT();
2122 switch (VA.getLocInfo()) {
2125 case CCValAssign::BCvt:
2126 MemVT = VA.getLocVT();
2128 case CCValAssign::SExt:
2129 ExtType = ISD::SEXTLOAD;
2131 case CCValAssign::ZExt:
2132 ExtType = ISD::ZEXTLOAD;
2134 case CCValAssign::AExt:
2135 ExtType = ISD::EXTLOAD;
2139 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
2140 MachinePointerInfo::getFixedStack(FI),
2141 MemVT, false, false, false, 0);
2143 InVals.push_back(ArgValue);
2149 if (!Subtarget->isTargetDarwin()) {
2150 // The AAPCS variadic function ABI is identical to the non-variadic
2151 // one. As a result there may be more arguments in registers and we should
2152 // save them for future reference.
2153 saveVarArgRegisters(CCInfo, DAG, DL, Chain);
2156 AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
2157 // This will point to the next argument passed via stack.
2158 unsigned StackOffset = CCInfo.getNextStackOffset();
2159 // We currently pass all varargs at 8-byte alignment.
2160 StackOffset = ((StackOffset + 7) & ~7);
2161 AFI->setVarArgsStackIndex(MFI->CreateFixedObject(4, StackOffset, true));
2164 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2165 unsigned StackArgSize = CCInfo.getNextStackOffset();
2166 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2167 if (DoesCalleeRestoreStack(CallConv, TailCallOpt)) {
2168 // This is a non-standard ABI so by fiat I say we're allowed to make full
2169 // use of the stack area to be popped, which must be aligned to 16 bytes in
2171 StackArgSize = RoundUpToAlignment(StackArgSize, 16);
2173 // If we're expected to restore the stack (e.g. fastcc) then we'll be adding
2174 // a multiple of 16.
2175 FuncInfo->setArgumentStackToRestore(StackArgSize);
2177 // This realignment carries over to the available bytes below. Our own
2178 // callers will guarantee the space is free by giving an aligned value to
2181 // Even if we're not expected to free up the space, it's useful to know how
2182 // much is there while considering tail calls (because we can reuse it).
2183 FuncInfo->setBytesInStackArgArea(StackArgSize);
2188 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
2189 SelectionDAG &DAG, SDLoc DL,
2190 SDValue &Chain) const {
2191 MachineFunction &MF = DAG.getMachineFunction();
2192 MachineFrameInfo *MFI = MF.getFrameInfo();
2193 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2195 SmallVector<SDValue, 8> MemOps;
2197 static const MCPhysReg GPRArgRegs[] = { AArch64::X0, AArch64::X1, AArch64::X2,
2198 AArch64::X3, AArch64::X4, AArch64::X5,
2199 AArch64::X6, AArch64::X7 };
2200 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
2201 unsigned FirstVariadicGPR =
2202 CCInfo.getFirstUnallocated(GPRArgRegs, NumGPRArgRegs);
2204 unsigned GPRSaveSize = 8 * (NumGPRArgRegs - FirstVariadicGPR);
2206 if (GPRSaveSize != 0) {
2207 GPRIdx = MFI->CreateStackObject(GPRSaveSize, 8, false);
2209 SDValue FIN = DAG.getFrameIndex(GPRIdx, getPointerTy());
2211 for (unsigned i = FirstVariadicGPR; i < NumGPRArgRegs; ++i) {
2212 unsigned VReg = MF.addLiveIn(GPRArgRegs[i], &AArch64::GPR64RegClass);
2213 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
2215 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2216 MachinePointerInfo::getStack(i * 8), false, false, 0);
2217 MemOps.push_back(Store);
2218 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2219 DAG.getConstant(8, getPointerTy()));
2222 FuncInfo->setVarArgsGPRIndex(GPRIdx);
2223 FuncInfo->setVarArgsGPRSize(GPRSaveSize);
2225 if (Subtarget->hasFPARMv8()) {
2226 static const MCPhysReg FPRArgRegs[] = {
2227 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
2228 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7};
2229 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
2230 unsigned FirstVariadicFPR =
2231 CCInfo.getFirstUnallocated(FPRArgRegs, NumFPRArgRegs);
2233 unsigned FPRSaveSize = 16 * (NumFPRArgRegs - FirstVariadicFPR);
2235 if (FPRSaveSize != 0) {
2236 FPRIdx = MFI->CreateStackObject(FPRSaveSize, 16, false);
2238 SDValue FIN = DAG.getFrameIndex(FPRIdx, getPointerTy());
2240 for (unsigned i = FirstVariadicFPR; i < NumFPRArgRegs; ++i) {
2241 unsigned VReg = MF.addLiveIn(FPRArgRegs[i], &AArch64::FPR128RegClass);
2242 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
2245 DAG.getStore(Val.getValue(1), DL, Val, FIN,
2246 MachinePointerInfo::getStack(i * 16), false, false, 0);
2247 MemOps.push_back(Store);
2248 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), FIN,
2249 DAG.getConstant(16, getPointerTy()));
2252 FuncInfo->setVarArgsFPRIndex(FPRIdx);
2253 FuncInfo->setVarArgsFPRSize(FPRSaveSize);
2256 if (!MemOps.empty()) {
2257 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2261 /// LowerCallResult - Lower the result values of a call into the
2262 /// appropriate copies out of appropriate physical registers.
2263 SDValue AArch64TargetLowering::LowerCallResult(
2264 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg,
2265 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2266 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
2267 SDValue ThisVal) const {
2268 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2269 ? RetCC_AArch64_WebKit_JS
2270 : RetCC_AArch64_AAPCS;
2271 // Assign locations to each value returned by this call.
2272 SmallVector<CCValAssign, 16> RVLocs;
2273 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2275 CCInfo.AnalyzeCallResult(Ins, RetCC);
2277 // Copy all of the result registers out of their specified physreg.
2278 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2279 CCValAssign VA = RVLocs[i];
2281 // Pass 'this' value directly from the argument to return value, to avoid
2282 // reg unit interference
2283 if (i == 0 && isThisReturn) {
2284 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i64 &&
2285 "unexpected return calling convention register assignment");
2286 InVals.push_back(ThisVal);
2291 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), InFlag);
2292 Chain = Val.getValue(1);
2293 InFlag = Val.getValue(2);
2295 switch (VA.getLocInfo()) {
2297 llvm_unreachable("Unknown loc info!");
2298 case CCValAssign::Full:
2300 case CCValAssign::BCvt:
2301 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2305 InVals.push_back(Val);
2311 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2312 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
2313 bool isCalleeStructRet, bool isCallerStructRet,
2314 const SmallVectorImpl<ISD::OutputArg> &Outs,
2315 const SmallVectorImpl<SDValue> &OutVals,
2316 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
2317 // For CallingConv::C this function knows whether the ABI needs
2318 // changing. That's not true for other conventions so they will have to opt in
2320 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
2323 const MachineFunction &MF = DAG.getMachineFunction();
2324 const Function *CallerF = MF.getFunction();
2325 CallingConv::ID CallerCC = CallerF->getCallingConv();
2326 bool CCMatch = CallerCC == CalleeCC;
2328 // Byval parameters hand the function a pointer directly into the stack area
2329 // we want to reuse during a tail call. Working around this *is* possible (see
2330 // X86) but less efficient and uglier in LowerCall.
2331 for (Function::const_arg_iterator i = CallerF->arg_begin(),
2332 e = CallerF->arg_end();
2334 if (i->hasByValAttr())
2337 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2338 if (IsTailCallConvention(CalleeCC) && CCMatch)
2343 // Externally-defined functions with weak linkage should not be
2344 // tail-called on AArch64 when the OS does not support dynamic
2345 // pre-emption of symbols, as the AAELF spec requires normal calls
2346 // to undefined weak functions to be replaced with a NOP or jump to the
2347 // next instruction. The behaviour of branch instructions in this
2348 // situation (as used for tail calls) is implementation-defined, so we
2349 // cannot rely on the linker replacing the tail call with a return.
2350 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2351 const GlobalValue *GV = G->getGlobal();
2352 if (GV->hasExternalWeakLinkage())
2356 // Now we search for cases where we can use a tail call without changing the
2357 // ABI. Sibcall is used in some places (particularly gcc) to refer to this
2360 // I want anyone implementing a new calling convention to think long and hard
2361 // about this assert.
2362 assert((!isVarArg || CalleeCC == CallingConv::C) &&
2363 "Unexpected variadic calling convention");
2365 if (isVarArg && !Outs.empty()) {
2366 // At least two cases here: if caller is fastcc then we can't have any
2367 // memory arguments (we'd be expected to clean up the stack afterwards). If
2368 // caller is C then we could potentially use its argument area.
2370 // FIXME: for now we take the most conservative of these in both cases:
2371 // disallow all variadic memory operands.
2372 SmallVector<CCValAssign, 16> ArgLocs;
2373 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2376 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, true));
2377 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2378 if (!ArgLocs[i].isRegLoc())
2382 // If the calling conventions do not match, then we'd better make sure the
2383 // results are returned in the same way as what the caller expects.
2385 SmallVector<CCValAssign, 16> RVLocs1;
2386 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2388 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForCall(CalleeCC, isVarArg));
2390 SmallVector<CCValAssign, 16> RVLocs2;
2391 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2393 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForCall(CallerCC, isVarArg));
2395 if (RVLocs1.size() != RVLocs2.size())
2397 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2398 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2400 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2402 if (RVLocs1[i].isRegLoc()) {
2403 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2406 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2412 // Nothing more to check if the callee is taking no arguments
2416 SmallVector<CCValAssign, 16> ArgLocs;
2417 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2420 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForCall(CalleeCC, isVarArg));
2422 const AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2424 // If the stack arguments for this call would fit into our own save area then
2425 // the call can be made tail.
2426 return CCInfo.getNextStackOffset() <= FuncInfo->getBytesInStackArgArea();
2429 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2431 MachineFrameInfo *MFI,
2432 int ClobberedFI) const {
2433 SmallVector<SDValue, 8> ArgChains;
2434 int64_t FirstByte = MFI->getObjectOffset(ClobberedFI);
2435 int64_t LastByte = FirstByte + MFI->getObjectSize(ClobberedFI) - 1;
2437 // Include the original chain at the beginning of the list. When this is
2438 // used by target LowerCall hooks, this helps legalize find the
2439 // CALLSEQ_BEGIN node.
2440 ArgChains.push_back(Chain);
2442 // Add a chain value for each stack argument corresponding
2443 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),
2444 UE = DAG.getEntryNode().getNode()->use_end();
2446 if (LoadSDNode *L = dyn_cast<LoadSDNode>(*U))
2447 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(L->getBasePtr()))
2448 if (FI->getIndex() < 0) {
2449 int64_t InFirstByte = MFI->getObjectOffset(FI->getIndex());
2450 int64_t InLastByte = InFirstByte;
2451 InLastByte += MFI->getObjectSize(FI->getIndex()) - 1;
2453 if ((InFirstByte <= FirstByte && FirstByte <= InLastByte) ||
2454 (FirstByte <= InFirstByte && InFirstByte <= LastByte))
2455 ArgChains.push_back(SDValue(L, 1));
2458 // Build a tokenfactor for all the chains.
2459 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);
2462 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2463 bool TailCallOpt) const {
2464 return CallCC == CallingConv::Fast && TailCallOpt;
2467 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2468 return CallCC == CallingConv::Fast;
2471 /// LowerCall - Lower a call to a callseq_start + CALL + callseq_end chain,
2472 /// and add input and output parameter nodes.
2474 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
2475 SmallVectorImpl<SDValue> &InVals) const {
2476 SelectionDAG &DAG = CLI.DAG;
2478 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2479 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2480 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2481 SDValue Chain = CLI.Chain;
2482 SDValue Callee = CLI.Callee;
2483 bool &IsTailCall = CLI.IsTailCall;
2484 CallingConv::ID CallConv = CLI.CallConv;
2485 bool IsVarArg = CLI.IsVarArg;
2487 MachineFunction &MF = DAG.getMachineFunction();
2488 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
2489 bool IsThisReturn = false;
2491 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
2492 bool TailCallOpt = MF.getTarget().Options.GuaranteedTailCallOpt;
2493 bool IsSibCall = false;
2496 // Check if it's really possible to do a tail call.
2497 IsTailCall = isEligibleForTailCallOptimization(
2498 Callee, CallConv, IsVarArg, IsStructRet,
2499 MF.getFunction()->hasStructRetAttr(), Outs, OutVals, Ins, DAG);
2500 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2501 report_fatal_error("failed to perform tail call elimination on a call "
2502 "site marked musttail");
2504 // A sibling call is one where we're under the usual C ABI and not planning
2505 // to change that but can still do a tail call:
2506 if (!TailCallOpt && IsTailCall)
2513 // Analyze operands of the call, assigning locations to each operand.
2514 SmallVector<CCValAssign, 16> ArgLocs;
2515 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2519 // Handle fixed and variable vector arguments differently.
2520 // Variable vector arguments always go into memory.
2521 unsigned NumArgs = Outs.size();
2523 for (unsigned i = 0; i != NumArgs; ++i) {
2524 MVT ArgVT = Outs[i].VT;
2525 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2526 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv,
2527 /*IsVarArg=*/ !Outs[i].IsFixed);
2528 bool Res = AssignFn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo);
2529 assert(!Res && "Call operand has unhandled type");
2533 // At this point, Outs[].VT may already be promoted to i32. To correctly
2534 // handle passing i8 as i8 instead of i32 on stack, we pass in both i32 and
2535 // i8 to CC_AArch64_AAPCS with i32 being ValVT and i8 being LocVT.
2536 // Since AnalyzeCallOperands uses Ins[].VT for both ValVT and LocVT, here
2537 // we use a special version of AnalyzeCallOperands to pass in ValVT and
2539 unsigned NumArgs = Outs.size();
2540 for (unsigned i = 0; i != NumArgs; ++i) {
2541 MVT ValVT = Outs[i].VT;
2542 // Get type of the original argument.
2543 EVT ActualVT = getValueType(CLI.getArgs()[Outs[i].OrigArgIndex].Ty,
2544 /*AllowUnknown*/ true);
2545 MVT ActualMVT = ActualVT.isSimple() ? ActualVT.getSimpleVT() : ValVT;
2546 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2547 // If ActualMVT is i1/i8/i16, we should set LocVT to i8/i8/i16.
2548 if (ActualMVT == MVT::i1 || ActualMVT == MVT::i8)
2550 else if (ActualMVT == MVT::i16)
2553 CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, /*IsVarArg=*/false);
2554 bool Res = AssignFn(i, ValVT, ValVT, CCValAssign::Full, ArgFlags, CCInfo);
2555 assert(!Res && "Call operand has unhandled type");
2560 // Get a count of how many bytes are to be pushed on the stack.
2561 unsigned NumBytes = CCInfo.getNextStackOffset();
2564 // Since we're not changing the ABI to make this a tail call, the memory
2565 // operands are already available in the caller's incoming argument space.
2569 // FPDiff is the byte offset of the call's argument area from the callee's.
2570 // Stores to callee stack arguments will be placed in FixedStackSlots offset
2571 // by this amount for a tail call. In a sibling call it must be 0 because the
2572 // caller will deallocate the entire stack and the callee still expects its
2573 // arguments to begin at SP+0. Completely unused for non-tail calls.
2576 if (IsTailCall && !IsSibCall) {
2577 unsigned NumReusableBytes = FuncInfo->getBytesInStackArgArea();
2579 // Since callee will pop argument stack as a tail call, we must keep the
2580 // popped size 16-byte aligned.
2581 NumBytes = RoundUpToAlignment(NumBytes, 16);
2583 // FPDiff will be negative if this tail call requires more space than we
2584 // would automatically have in our incoming argument space. Positive if we
2585 // can actually shrink the stack.
2586 FPDiff = NumReusableBytes - NumBytes;
2588 // The stack pointer must be 16-byte aligned at all times it's used for a
2589 // memory operation, which in practice means at *all* times and in
2590 // particular across call boundaries. Therefore our own arguments started at
2591 // a 16-byte aligned SP and the delta applied for the tail call should
2592 // satisfy the same constraint.
2593 assert(FPDiff % 16 == 0 && "unaligned stack on tail call");
2596 // Adjust the stack pointer for the new arguments...
2597 // These operations are automatically eliminated by the prolog/epilog pass
2600 DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true), DL);
2602 SDValue StackPtr = DAG.getCopyFromReg(Chain, DL, AArch64::SP, getPointerTy());
2604 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2605 SmallVector<SDValue, 8> MemOpChains;
2607 // Walk the register/memloc assignments, inserting copies/loads.
2608 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); i != e;
2609 ++i, ++realArgIdx) {
2610 CCValAssign &VA = ArgLocs[i];
2611 SDValue Arg = OutVals[realArgIdx];
2612 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2614 // Promote the value if needed.
2615 switch (VA.getLocInfo()) {
2617 llvm_unreachable("Unknown loc info!");
2618 case CCValAssign::Full:
2620 case CCValAssign::SExt:
2621 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
2623 case CCValAssign::ZExt:
2624 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2626 case CCValAssign::AExt:
2627 if (Outs[realArgIdx].ArgVT == MVT::i1) {
2628 // AAPCS requires i1 to be zero-extended to 8-bits by the caller.
2629 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2630 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg);
2632 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
2634 case CCValAssign::BCvt:
2635 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2637 case CCValAssign::FPExt:
2638 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg);
2642 if (VA.isRegLoc()) {
2643 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
2644 assert(VA.getLocVT() == MVT::i64 &&
2645 "unexpected calling convention register assignment");
2646 assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
2647 "unexpected use of 'returned'");
2648 IsThisReturn = true;
2650 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2652 assert(VA.isMemLoc());
2655 MachinePointerInfo DstInfo;
2657 // FIXME: This works on big-endian for composite byvals, which are the
2658 // common case. It should also work for fundamental types too.
2659 uint32_t BEAlign = 0;
2660 unsigned OpSize = Flags.isByVal() ? Flags.getByValSize() * 8
2661 : VA.getValVT().getSizeInBits();
2662 OpSize = (OpSize + 7) / 8;
2663 if (!Subtarget->isLittleEndian() && !Flags.isByVal()) {
2665 BEAlign = 8 - OpSize;
2667 unsigned LocMemOffset = VA.getLocMemOffset();
2668 int32_t Offset = LocMemOffset + BEAlign;
2669 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2670 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2673 Offset = Offset + FPDiff;
2674 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2676 DstAddr = DAG.getFrameIndex(FI, getPointerTy());
2677 DstInfo = MachinePointerInfo::getFixedStack(FI);
2679 // Make sure any stack arguments overlapping with where we're storing
2680 // are loaded before this eventual operation. Otherwise they'll be
2682 Chain = addTokenForArgument(Chain, DAG, MF.getFrameInfo(), FI);
2684 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
2686 DstAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
2687 DstInfo = MachinePointerInfo::getStack(LocMemOffset);
2690 if (Outs[i].Flags.isByVal()) {
2692 DAG.getConstant(Outs[i].Flags.getByValSize(), MVT::i64);
2693 SDValue Cpy = DAG.getMemcpy(
2694 Chain, DL, DstAddr, Arg, SizeNode, Outs[i].Flags.getByValAlign(),
2696 /*AlwaysInline = */ false, DstInfo, MachinePointerInfo());
2698 MemOpChains.push_back(Cpy);
2700 // Since we pass i1/i8/i16 as i1/i8/i16 on stack and Arg is already
2701 // promoted to a legal register type i32, we should truncate Arg back to
2703 if (VA.getValVT() == MVT::i1 || VA.getValVT() == MVT::i8 ||
2704 VA.getValVT() == MVT::i16)
2705 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
2708 DAG.getStore(Chain, DL, Arg, DstAddr, DstInfo, false, false, 0);
2709 MemOpChains.push_back(Store);
2714 if (!MemOpChains.empty())
2715 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2717 // Build a sequence of copy-to-reg nodes chained together with token chain
2718 // and flag operands which copy the outgoing args into the appropriate regs.
2720 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2721 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first,
2722 RegsToPass[i].second, InFlag);
2723 InFlag = Chain.getValue(1);
2726 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2727 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2728 // node so that legalize doesn't hack it.
2729 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
2730 Subtarget->isTargetMachO()) {
2731 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2732 const GlobalValue *GV = G->getGlobal();
2733 bool InternalLinkage = GV->hasInternalLinkage();
2734 if (InternalLinkage)
2735 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2737 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0,
2739 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2741 } else if (ExternalSymbolSDNode *S =
2742 dyn_cast<ExternalSymbolSDNode>(Callee)) {
2743 const char *Sym = S->getSymbol();
2745 DAG.getTargetExternalSymbol(Sym, getPointerTy(), AArch64II::MO_GOT);
2746 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, getPointerTy(), Callee);
2748 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2749 const GlobalValue *GV = G->getGlobal();
2750 Callee = DAG.getTargetGlobalAddress(GV, DL, getPointerTy(), 0, 0);
2751 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2752 const char *Sym = S->getSymbol();
2753 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), 0);
2756 // We don't usually want to end the call-sequence here because we would tidy
2757 // the frame up *after* the call, however in the ABI-changing tail-call case
2758 // we've carefully laid out the parameters so that when sp is reset they'll be
2759 // in the correct location.
2760 if (IsTailCall && !IsSibCall) {
2761 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2762 DAG.getIntPtrConstant(0, true), InFlag, DL);
2763 InFlag = Chain.getValue(1);
2766 std::vector<SDValue> Ops;
2767 Ops.push_back(Chain);
2768 Ops.push_back(Callee);
2771 // Each tail call may have to adjust the stack by a different amount, so
2772 // this information must travel along with the operation for eventual
2773 // consumption by emitEpilogue.
2774 Ops.push_back(DAG.getTargetConstant(FPDiff, MVT::i32));
2777 // Add argument registers to the end of the list so that they are known live
2779 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2780 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2781 RegsToPass[i].second.getValueType()));
2783 // Add a register mask operand representing the call-preserved registers.
2784 const uint32_t *Mask;
2785 const TargetRegisterInfo *TRI =
2786 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
2787 const AArch64RegisterInfo *ARI =
2788 static_cast<const AArch64RegisterInfo *>(TRI);
2790 // For 'this' returns, use the X0-preserving mask if applicable
2791 Mask = ARI->getThisReturnPreservedMask(CallConv);
2793 IsThisReturn = false;
2794 Mask = ARI->getCallPreservedMask(CallConv);
2797 Mask = ARI->getCallPreservedMask(CallConv);
2799 assert(Mask && "Missing call preserved mask for calling convention");
2800 Ops.push_back(DAG.getRegisterMask(Mask));
2802 if (InFlag.getNode())
2803 Ops.push_back(InFlag);
2805 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2807 // If we're doing a tall call, use a TC_RETURN here rather than an
2808 // actual call instruction.
2810 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
2812 // Returns a chain and a flag for retval copy to use.
2813 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops);
2814 InFlag = Chain.getValue(1);
2816 uint64_t CalleePopBytes = DoesCalleeRestoreStack(CallConv, TailCallOpt)
2817 ? RoundUpToAlignment(NumBytes, 16)
2820 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2821 DAG.getIntPtrConstant(CalleePopBytes, true),
2824 InFlag = Chain.getValue(1);
2826 // Handle result values, copying them out of physregs into vregs that we
2828 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2829 InVals, IsThisReturn,
2830 IsThisReturn ? OutVals[0] : SDValue());
2833 bool AArch64TargetLowering::CanLowerReturn(
2834 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2835 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2836 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2837 ? RetCC_AArch64_WebKit_JS
2838 : RetCC_AArch64_AAPCS;
2839 SmallVector<CCValAssign, 16> RVLocs;
2840 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2841 return CCInfo.CheckReturn(Outs, RetCC);
2845 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2847 const SmallVectorImpl<ISD::OutputArg> &Outs,
2848 const SmallVectorImpl<SDValue> &OutVals,
2849 SDLoc DL, SelectionDAG &DAG) const {
2850 CCAssignFn *RetCC = CallConv == CallingConv::WebKit_JS
2851 ? RetCC_AArch64_WebKit_JS
2852 : RetCC_AArch64_AAPCS;
2853 SmallVector<CCValAssign, 16> RVLocs;
2854 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2856 CCInfo.AnalyzeReturn(Outs, RetCC);
2858 // Copy the result values into the output registers.
2860 SmallVector<SDValue, 4> RetOps(1, Chain);
2861 for (unsigned i = 0, realRVLocIdx = 0; i != RVLocs.size();
2862 ++i, ++realRVLocIdx) {
2863 CCValAssign &VA = RVLocs[i];
2864 assert(VA.isRegLoc() && "Can only return in registers!");
2865 SDValue Arg = OutVals[realRVLocIdx];
2867 switch (VA.getLocInfo()) {
2869 llvm_unreachable("Unknown loc info!");
2870 case CCValAssign::Full:
2871 if (Outs[i].ArgVT == MVT::i1) {
2872 // AAPCS requires i1 to be zero-extended to i8 by the producer of the
2873 // value. This is strictly redundant on Darwin (which uses "zeroext
2874 // i1"), but will be optimised out before ISel.
2875 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg);
2876 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
2879 case CCValAssign::BCvt:
2880 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
2884 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
2885 Flag = Chain.getValue(1);
2886 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2889 RetOps[0] = Chain; // Update chain.
2891 // Add the flag if we have it.
2893 RetOps.push_back(Flag);
2895 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps);
2898 //===----------------------------------------------------------------------===//
2899 // Other Lowering Code
2900 //===----------------------------------------------------------------------===//
2902 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
2903 SelectionDAG &DAG) const {
2904 EVT PtrVT = getPointerTy();
2906 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
2907 const GlobalValue *GV = GN->getGlobal();
2908 unsigned char OpFlags =
2909 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
2911 assert(cast<GlobalAddressSDNode>(Op)->getOffset() == 0 &&
2912 "unexpected offset in global node");
2914 // This also catched the large code model case for Darwin.
2915 if ((OpFlags & AArch64II::MO_GOT) != 0) {
2916 SDValue GotAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
2917 // FIXME: Once remat is capable of dealing with instructions with register
2918 // operands, expand this into two nodes instead of using a wrapper node.
2919 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
2922 if ((OpFlags & AArch64II::MO_CONSTPOOL) != 0) {
2923 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
2924 "use of MO_CONSTPOOL only supported on small model");
2925 SDValue Hi = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, AArch64II::MO_PAGE);
2926 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2927 unsigned char LoFlags = AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2928 SDValue Lo = DAG.getTargetConstantPool(GV, PtrVT, 0, 0, LoFlags);
2929 SDValue PoolAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2930 SDValue GlobalAddr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), PoolAddr,
2931 MachinePointerInfo::getConstantPool(),
2932 /*isVolatile=*/ false,
2933 /*isNonTemporal=*/ true,
2934 /*isInvariant=*/ true, 8);
2935 if (GN->getOffset() != 0)
2936 return DAG.getNode(ISD::ADD, DL, PtrVT, GlobalAddr,
2937 DAG.getConstant(GN->getOffset(), PtrVT));
2941 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2942 const unsigned char MO_NC = AArch64II::MO_NC;
2944 AArch64ISD::WrapperLarge, DL, PtrVT,
2945 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G3),
2946 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
2947 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
2948 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
2950 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
2951 // the only correct model on Darwin.
2952 SDValue Hi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2953 OpFlags | AArch64II::MO_PAGE);
2954 unsigned char LoFlags = OpFlags | AArch64II::MO_PAGEOFF | AArch64II::MO_NC;
2955 SDValue Lo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, LoFlags);
2957 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
2958 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
2962 /// \brief Convert a TLS address reference into the correct sequence of loads
2963 /// and calls to compute the variable's address (for Darwin, currently) and
2964 /// return an SDValue containing the final node.
2966 /// Darwin only has one TLS scheme which must be capable of dealing with the
2967 /// fully general situation, in the worst case. This means:
2968 /// + "extern __thread" declaration.
2969 /// + Defined in a possibly unknown dynamic library.
2971 /// The general system is that each __thread variable has a [3 x i64] descriptor
2972 /// which contains information used by the runtime to calculate the address. The
2973 /// only part of this the compiler needs to know about is the first xword, which
2974 /// contains a function pointer that must be called with the address of the
2975 /// entire descriptor in "x0".
2977 /// Since this descriptor may be in a different unit, in general even the
2978 /// descriptor must be accessed via an indirect load. The "ideal" code sequence
2980 /// adrp x0, _var@TLVPPAGE
2981 /// ldr x0, [x0, _var@TLVPPAGEOFF] ; x0 now contains address of descriptor
2982 /// ldr x1, [x0] ; x1 contains 1st entry of descriptor,
2983 /// ; the function pointer
2984 /// blr x1 ; Uses descriptor address in x0
2985 /// ; Address of _var is now in x0.
2987 /// If the address of _var's descriptor *is* known to the linker, then it can
2988 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
2989 /// a slight efficiency gain.
2991 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
2992 SelectionDAG &DAG) const {
2993 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
2996 MVT PtrVT = getPointerTy();
2997 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3000 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3001 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr);
3003 // The first entry in the descriptor is a function pointer that we must call
3004 // to obtain the address of the variable.
3005 SDValue Chain = DAG.getEntryNode();
3006 SDValue FuncTLVGet =
3007 DAG.getLoad(MVT::i64, DL, Chain, DescAddr, MachinePointerInfo::getGOT(),
3008 false, true, true, 8);
3009 Chain = FuncTLVGet.getValue(1);
3011 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3012 MFI->setAdjustsStack(true);
3014 // TLS calls preserve all registers except those that absolutely must be
3015 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3017 const TargetRegisterInfo *TRI =
3018 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
3019 const AArch64RegisterInfo *ARI =
3020 static_cast<const AArch64RegisterInfo *>(TRI);
3021 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
3023 // Finally, we can make the call. This is just a degenerate version of a
3024 // normal AArch64 call node: x0 takes the address of the descriptor, and
3025 // returns the address of the variable in this thread.
3026 Chain = DAG.getCopyToReg(Chain, DL, AArch64::X0, DescAddr, SDValue());
3028 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
3029 Chain, FuncTLVGet, DAG.getRegister(AArch64::X0, MVT::i64),
3030 DAG.getRegisterMask(Mask), Chain.getValue(1));
3031 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Chain.getValue(1));
3034 /// When accessing thread-local variables under either the general-dynamic or
3035 /// local-dynamic system, we make a "TLS-descriptor" call. The variable will
3036 /// have a descriptor, accessible via a PC-relative ADRP, and whose first entry
3037 /// is a function pointer to carry out the resolution. This function takes the
3038 /// address of the descriptor in X0 and returns the TPIDR_EL0 offset in X0. All
3039 /// other registers (except LR, NZCV) are preserved.
3041 /// Thus, the ideal call sequence on AArch64 is:
3043 /// adrp x0, :tlsdesc:thread_var
3044 /// ldr x8, [x0, :tlsdesc_lo12:thread_var]
3045 /// add x0, x0, :tlsdesc_lo12:thread_var
3046 /// .tlsdesccall thread_var
3048 /// (TPIDR_EL0 offset now in x0).
3050 /// The ".tlsdesccall" directive instructs the assembler to insert a particular
3051 /// relocation to help the linker relax this sequence if it turns out to be too
3054 /// FIXME: we currently produce an extra, duplicated, ADRP instruction, but this
3056 SDValue AArch64TargetLowering::LowerELFTLSDescCall(SDValue SymAddr,
3057 SDValue DescAddr, SDLoc DL,
3058 SelectionDAG &DAG) const {
3059 EVT PtrVT = getPointerTy();
3061 // The function we need to call is simply the first entry in the GOT for this
3062 // descriptor, load it in preparation.
3063 SDValue Func = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, SymAddr);
3065 // TLS calls preserve all registers except those that absolutely must be
3066 // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
3068 const TargetRegisterInfo *TRI =
3069 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
3070 const AArch64RegisterInfo *ARI =
3071 static_cast<const AArch64RegisterInfo *>(TRI);
3072 const uint32_t *Mask = ARI->getTLSCallPreservedMask();
3074 // The function takes only one argument: the address of the descriptor itself
3076 SDValue Glue, Chain;
3077 Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, AArch64::X0, DescAddr, Glue);
3078 Glue = Chain.getValue(1);
3080 // We're now ready to populate the argument list, as with a normal call:
3081 SmallVector<SDValue, 6> Ops;
3082 Ops.push_back(Chain);
3083 Ops.push_back(Func);
3084 Ops.push_back(SymAddr);
3085 Ops.push_back(DAG.getRegister(AArch64::X0, PtrVT));
3086 Ops.push_back(DAG.getRegisterMask(Mask));
3087 Ops.push_back(Glue);
3089 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3090 Chain = DAG.getNode(AArch64ISD::TLSDESC_CALL, DL, NodeTys, Ops);
3091 Glue = Chain.getValue(1);
3093 return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
3097 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
3098 SelectionDAG &DAG) const {
3099 assert(Subtarget->isTargetELF() && "This function expects an ELF target");
3100 assert(getTargetMachine().getCodeModel() == CodeModel::Small &&
3101 "ELF TLS only supported in small memory model");
3102 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3104 TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
3107 EVT PtrVT = getPointerTy();
3109 const GlobalValue *GV = GA->getGlobal();
3111 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT);
3113 if (Model == TLSModel::LocalExec) {
3114 SDValue HiVar = DAG.getTargetGlobalAddress(
3115 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
3116 SDValue LoVar = DAG.getTargetGlobalAddress(
3118 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
3120 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
3121 DAG.getTargetConstant(16, MVT::i32)),
3123 TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, TPOff, LoVar,
3124 DAG.getTargetConstant(0, MVT::i32)),
3126 } else if (Model == TLSModel::InitialExec) {
3127 TPOff = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3128 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff);
3129 } else if (Model == TLSModel::LocalDynamic) {
3130 // Local-dynamic accesses proceed in two phases. A general-dynamic TLS
3131 // descriptor call against the special symbol _TLS_MODULE_BASE_ to calculate
3132 // the beginning of the module's TLS region, followed by a DTPREL offset
3135 // These accesses will need deduplicating if there's more than one.
3136 AArch64FunctionInfo *MFI =
3137 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3138 MFI->incNumLocalDynamicTLSAccesses();
3140 // Accesses used in this sequence go via the TLS descriptor which lives in
3141 // the GOT. Prepare an address we can use to handle this.
3142 SDValue HiDesc = DAG.getTargetExternalSymbol(
3143 "_TLS_MODULE_BASE_", PtrVT, AArch64II::MO_TLS | AArch64II::MO_PAGE);
3144 SDValue LoDesc = DAG.getTargetExternalSymbol(
3145 "_TLS_MODULE_BASE_", PtrVT,
3146 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3148 // First argument to the descriptor call is the address of the descriptor
3150 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
3151 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
3153 // The call needs a relocation too for linker relaxation. It doesn't make
3154 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3156 SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
3159 // Now we can calculate the offset from TPIDR_EL0 to this module's
3160 // thread-local area.
3161 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
3163 // Now use :dtprel_whatever: operations to calculate this variable's offset
3164 // in its thread-storage area.
3165 SDValue HiVar = DAG.getTargetGlobalAddress(
3166 GV, DL, MVT::i64, 0, AArch64II::MO_TLS | AArch64II::MO_G1);
3167 SDValue LoVar = DAG.getTargetGlobalAddress(
3168 GV, DL, MVT::i64, 0,
3169 AArch64II::MO_TLS | AArch64II::MO_G0 | AArch64II::MO_NC);
3172 SDValue(DAG.getMachineNode(AArch64::MOVZXi, DL, PtrVT, HiVar,
3173 DAG.getTargetConstant(16, MVT::i32)),
3176 SDValue(DAG.getMachineNode(AArch64::MOVKXi, DL, PtrVT, DTPOff, LoVar,
3177 DAG.getTargetConstant(0, MVT::i32)),
3180 TPOff = DAG.getNode(ISD::ADD, DL, PtrVT, TPOff, DTPOff);
3181 } else if (Model == TLSModel::GeneralDynamic) {
3182 // Accesses used in this sequence go via the TLS descriptor which lives in
3183 // the GOT. Prepare an address we can use to handle this.
3184 SDValue HiDesc = DAG.getTargetGlobalAddress(
3185 GV, DL, PtrVT, 0, AArch64II::MO_TLS | AArch64II::MO_PAGE);
3186 SDValue LoDesc = DAG.getTargetGlobalAddress(
3188 AArch64II::MO_TLS | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3190 // First argument to the descriptor call is the address of the descriptor
3192 SDValue DescAddr = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, HiDesc);
3193 DescAddr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, DescAddr, LoDesc);
3195 // The call needs a relocation too for linker relaxation. It doesn't make
3196 // sense to call it MO_PAGE or MO_PAGEOFF though so we need another copy of
3199 DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, AArch64II::MO_TLS);
3201 // Finally we can make a call to calculate the offset from tpidr_el0.
3202 TPOff = LowerELFTLSDescCall(SymAddr, DescAddr, DL, DAG);
3204 llvm_unreachable("Unsupported ELF TLS access model");
3206 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
3209 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
3210 SelectionDAG &DAG) const {
3211 if (Subtarget->isTargetDarwin())
3212 return LowerDarwinGlobalTLSAddress(Op, DAG);
3213 else if (Subtarget->isTargetELF())
3214 return LowerELFGlobalTLSAddress(Op, DAG);
3216 llvm_unreachable("Unexpected platform trying to use TLS");
3218 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3219 SDValue Chain = Op.getOperand(0);
3220 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3221 SDValue LHS = Op.getOperand(2);
3222 SDValue RHS = Op.getOperand(3);
3223 SDValue Dest = Op.getOperand(4);
3226 // Handle f128 first, since lowering it will result in comparing the return
3227 // value of a libcall against zero, which is just what the rest of LowerBR_CC
3228 // is expecting to deal with.
3229 if (LHS.getValueType() == MVT::f128) {
3230 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3232 // If softenSetCCOperands returned a scalar, we need to compare the result
3233 // against zero to select between true and false values.
3234 if (!RHS.getNode()) {
3235 RHS = DAG.getConstant(0, LHS.getValueType());
3240 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
3242 unsigned Opc = LHS.getOpcode();
3243 if (LHS.getResNo() == 1 && isa<ConstantSDNode>(RHS) &&
3244 cast<ConstantSDNode>(RHS)->isOne() &&
3245 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3246 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3247 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
3248 "Unexpected condition code.");
3249 // Only lower legal XALUO ops.
3250 if (!DAG.getTargetLoweringInfo().isTypeLegal(LHS->getValueType(0)))
3253 // The actual operation with overflow check.
3254 AArch64CC::CondCode OFCC;
3255 SDValue Value, Overflow;
3256 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, LHS.getValue(0), DAG);
3258 if (CC == ISD::SETNE)
3259 OFCC = getInvertedCondCode(OFCC);
3260 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3262 return DAG.getNode(AArch64ISD::BRCOND, SDLoc(LHS), MVT::Other, Chain, Dest,
3266 if (LHS.getValueType().isInteger()) {
3267 assert((LHS.getValueType() == RHS.getValueType()) &&
3268 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3270 // If the RHS of the comparison is zero, we can potentially fold this
3271 // to a specialized branch.
3272 const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
3273 if (RHSC && RHSC->getZExtValue() == 0) {
3274 if (CC == ISD::SETEQ) {
3275 // See if we can use a TBZ to fold in an AND as well.
3276 // TBZ has a smaller branch displacement than CBZ. If the offset is
3277 // out of bounds, a late MI-layer pass rewrites branches.
3278 // 403.gcc is an example that hits this case.
3279 if (LHS.getOpcode() == ISD::AND &&
3280 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3281 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3282 SDValue Test = LHS.getOperand(0);
3283 uint64_t Mask = LHS.getConstantOperandVal(1);
3284 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test,
3285 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3288 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest);
3289 } else if (CC == ISD::SETNE) {
3290 // See if we can use a TBZ to fold in an AND as well.
3291 // TBZ has a smaller branch displacement than CBZ. If the offset is
3292 // out of bounds, a late MI-layer pass rewrites branches.
3293 // 403.gcc is an example that hits this case.
3294 if (LHS.getOpcode() == ISD::AND &&
3295 isa<ConstantSDNode>(LHS.getOperand(1)) &&
3296 isPowerOf2_64(LHS.getConstantOperandVal(1))) {
3297 SDValue Test = LHS.getOperand(0);
3298 uint64_t Mask = LHS.getConstantOperandVal(1);
3299 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test,
3300 DAG.getConstant(Log2_64(Mask), MVT::i64), Dest);
3303 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest);
3304 } else if (CC == ISD::SETLT && LHS.getOpcode() != ISD::AND) {
3305 // Don't combine AND since emitComparison converts the AND to an ANDS
3306 // (a.k.a. TST) and the test in the test bit and branch instruction
3307 // becomes redundant. This would also increase register pressure.
3308 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3309 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS,
3310 DAG.getConstant(Mask, MVT::i64), Dest);
3313 if (RHSC && RHSC->getSExtValue() == -1 && CC == ISD::SETGT &&
3314 LHS.getOpcode() != ISD::AND) {
3315 // Don't combine AND since emitComparison converts the AND to an ANDS
3316 // (a.k.a. TST) and the test in the test bit and branch instruction
3317 // becomes redundant. This would also increase register pressure.
3318 uint64_t Mask = LHS.getValueType().getSizeInBits() - 1;
3319 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS,
3320 DAG.getConstant(Mask, MVT::i64), Dest);
3324 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3325 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
3329 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3331 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3332 // clean. Some of them require two branches to implement.
3333 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3334 AArch64CC::CondCode CC1, CC2;
3335 changeFPCCToAArch64CC(CC, CC1, CC2);
3336 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3338 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp);
3339 if (CC2 != AArch64CC::AL) {
3340 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3341 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val,
3348 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3349 SelectionDAG &DAG) const {
3350 EVT VT = Op.getValueType();
3353 SDValue In1 = Op.getOperand(0);
3354 SDValue In2 = Op.getOperand(1);
3355 EVT SrcVT = In2.getValueType();
3357 if (SrcVT == MVT::f32 && VT == MVT::f64)
3358 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
3359 else if (SrcVT == MVT::f64 && VT == MVT::f32)
3360 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0));
3362 // FIXME: Src type is different, bail out for now. Can VT really be a
3369 SDValue EltMask, VecVal1, VecVal2;
3370 if (VT == MVT::f32 || VT == MVT::v2f32 || VT == MVT::v4f32) {
3373 EltMask = DAG.getConstant(0x80000000ULL, EltVT);
3375 if (!VT.isVector()) {
3376 VecVal1 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3377 DAG.getUNDEF(VecVT), In1);
3378 VecVal2 = DAG.getTargetInsertSubreg(AArch64::ssub, DL, VecVT,
3379 DAG.getUNDEF(VecVT), In2);
3381 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3382 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3384 } else if (VT == MVT::f64 || VT == MVT::v2f64) {
3388 // We want to materialize a mask with the the high bit set, but the AdvSIMD
3389 // immediate moves cannot materialize that in a single instruction for
3390 // 64-bit elements. Instead, materialize zero and then negate it.
3391 EltMask = DAG.getConstant(0, EltVT);
3393 if (!VT.isVector()) {
3394 VecVal1 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3395 DAG.getUNDEF(VecVT), In1);
3396 VecVal2 = DAG.getTargetInsertSubreg(AArch64::dsub, DL, VecVT,
3397 DAG.getUNDEF(VecVT), In2);
3399 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);
3400 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);
3403 llvm_unreachable("Invalid type for copysign!");
3406 std::vector<SDValue> BuildVectorOps;
3407 for (unsigned i = 0; i < VecVT.getVectorNumElements(); ++i)
3408 BuildVectorOps.push_back(EltMask);
3410 SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, BuildVectorOps);
3412 // If we couldn't materialize the mask above, then the mask vector will be
3413 // the zero vector, and we need to negate it here.
3414 if (VT == MVT::f64 || VT == MVT::v2f64) {
3415 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);
3416 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec);
3417 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);
3421 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec);
3424 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel);
3425 else if (VT == MVT::f64)
3426 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel);
3428 return DAG.getNode(ISD::BITCAST, DL, VT, Sel);
3431 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3432 if (DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
3433 AttributeSet::FunctionIndex, Attribute::NoImplicitFloat))
3436 if (!Subtarget->hasNEON())
3439 // While there is no integer popcount instruction, it can
3440 // be more efficiently lowered to the following sequence that uses
3441 // AdvSIMD registers/instructions as long as the copies to/from
3442 // the AdvSIMD registers are cheap.
3443 // FMOV D0, X0 // copy 64-bit int to vector, high bits zero'd
3444 // CNT V0.8B, V0.8B // 8xbyte pop-counts
3445 // ADDV B0, V0.8B // sum 8xbyte pop-counts
3446 // UMOV X0, V0.B[0] // copy byte result back to integer reg
3447 SDValue Val = Op.getOperand(0);
3449 EVT VT = Op.getValueType();
3450 SDValue ZeroVec = DAG.getUNDEF(MVT::v8i8);
3453 if (VT == MVT::i32) {
3454 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val);
3455 VecVal = DAG.getTargetInsertSubreg(AArch64::ssub, DL, MVT::v8i8, ZeroVec,
3458 VecVal = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);
3461 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, VecVal);
3462 SDValue UaddLV = DAG.getNode(
3463 ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
3464 DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, MVT::i32), CtPop);
3467 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV);
3471 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3473 if (Op.getValueType().isVector())
3474 return LowerVSETCC(Op, DAG);
3476 SDValue LHS = Op.getOperand(0);
3477 SDValue RHS = Op.getOperand(1);
3478 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
3481 // We chose ZeroOrOneBooleanContents, so use zero and one.
3482 EVT VT = Op.getValueType();
3483 SDValue TVal = DAG.getConstant(1, VT);
3484 SDValue FVal = DAG.getConstant(0, VT);
3486 // Handle f128 first, since one possible outcome is a normal integer
3487 // comparison which gets picked up by the next if statement.
3488 if (LHS.getValueType() == MVT::f128) {
3489 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3491 // If softenSetCCOperands returned a scalar, use it.
3492 if (!RHS.getNode()) {
3493 assert(LHS.getValueType() == Op.getValueType() &&
3494 "Unexpected setcc expansion!");
3499 if (LHS.getValueType().isInteger()) {
3502 getAArch64Cmp(LHS, RHS, ISD::getSetCCInverse(CC, true), CCVal, DAG, dl);
3504 // Note that we inverted the condition above, so we reverse the order of
3505 // the true and false operands here. This will allow the setcc to be
3506 // matched to a single CSINC instruction.
3507 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3510 // Now we know we're dealing with FP values.
3511 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3513 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3514 // and do the comparison.
3515 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3517 AArch64CC::CondCode CC1, CC2;
3518 changeFPCCToAArch64CC(CC, CC1, CC2);
3519 if (CC2 == AArch64CC::AL) {
3520 changeFPCCToAArch64CC(ISD::getSetCCInverse(CC, false), CC1, CC2);
3521 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3523 // Note that we inverted the condition above, so we reverse the order of
3524 // the true and false operands here. This will allow the setcc to be
3525 // matched to a single CSINC instruction.
3526 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3528 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't
3529 // totally clean. Some of them require two CSELs to implement. As is in
3530 // this case, we emit the first CSEL and then emit a second using the output
3531 // of the first as the RHS. We're effectively OR'ing the two CC's together.
3533 // FIXME: It would be nice if we could match the two CSELs to two CSINCs.
3534 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3536 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3538 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3539 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3543 /// A SELECT_CC operation is really some kind of max or min if both values being
3544 /// compared are, in some sense, equal to the results in either case. However,
3545 /// it is permissible to compare f32 values and produce directly extended f64
3548 /// Extending the comparison operands would also be allowed, but is less likely
3549 /// to happen in practice since their use is right here. Note that truncate
3550 /// operations would *not* be semantically equivalent.
3551 static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
3555 ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
3556 ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
3557 if (CCmp && CResult && Cmp.getValueType() == MVT::f32 &&
3558 Result.getValueType() == MVT::f64) {
3560 APFloat CmpVal = CCmp->getValueAPF();
3561 CmpVal.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven, &Lossy);
3562 return CResult->getValueAPF().bitwiseIsEqual(CmpVal);
3565 return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
3568 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
3569 SelectionDAG &DAG) const {
3570 SDValue CC = Op->getOperand(0);
3571 SDValue TVal = Op->getOperand(1);
3572 SDValue FVal = Op->getOperand(2);
3575 unsigned Opc = CC.getOpcode();
3576 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
3578 if (CC.getResNo() == 1 &&
3579 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3580 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
3581 // Only lower legal XALUO ops.
3582 if (!DAG.getTargetLoweringInfo().isTypeLegal(CC->getValueType(0)))
3585 AArch64CC::CondCode OFCC;
3586 SDValue Value, Overflow;
3587 std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CC.getValue(0), DAG);
3588 SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
3590 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
3594 if (CC.getOpcode() == ISD::SETCC)
3595 return DAG.getSelectCC(DL, CC.getOperand(0), CC.getOperand(1), TVal, FVal,
3596 cast<CondCodeSDNode>(CC.getOperand(2))->get());
3598 return DAG.getSelectCC(DL, CC, DAG.getConstant(0, CC.getValueType()), TVal,
3602 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
3603 SelectionDAG &DAG) const {
3604 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3605 SDValue LHS = Op.getOperand(0);
3606 SDValue RHS = Op.getOperand(1);
3607 SDValue TVal = Op.getOperand(2);
3608 SDValue FVal = Op.getOperand(3);
3611 // Handle f128 first, because it will result in a comparison of some RTLIB
3612 // call result against zero.
3613 if (LHS.getValueType() == MVT::f128) {
3614 softenSetCCOperands(DAG, MVT::f128, LHS, RHS, CC, dl);
3616 // If softenSetCCOperands returned a scalar, we need to compare the result
3617 // against zero to select between true and false values.
3618 if (!RHS.getNode()) {
3619 RHS = DAG.getConstant(0, LHS.getValueType());
3624 // Handle integers first.
3625 if (LHS.getValueType().isInteger()) {
3626 assert((LHS.getValueType() == RHS.getValueType()) &&
3627 (LHS.getValueType() == MVT::i32 || LHS.getValueType() == MVT::i64));
3629 unsigned Opcode = AArch64ISD::CSEL;
3631 // If both the TVal and the FVal are constants, see if we can swap them in
3632 // order to for a CSINV or CSINC out of them.
3633 ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
3634 ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
3636 if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
3637 std::swap(TVal, FVal);
3638 std::swap(CTVal, CFVal);
3639 CC = ISD::getSetCCInverse(CC, true);
3640 } else if (CTVal && CFVal && CTVal->isOne() && CFVal->isNullValue()) {
3641 std::swap(TVal, FVal);
3642 std::swap(CTVal, CFVal);
3643 CC = ISD::getSetCCInverse(CC, true);
3644 } else if (TVal.getOpcode() == ISD::XOR) {
3645 // If TVal is a NOT we want to swap TVal and FVal so that we can match
3646 // with a CSINV rather than a CSEL.
3647 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(1));
3649 if (CVal && CVal->isAllOnesValue()) {
3650 std::swap(TVal, FVal);
3651 std::swap(CTVal, CFVal);
3652 CC = ISD::getSetCCInverse(CC, true);
3654 } else if (TVal.getOpcode() == ISD::SUB) {
3655 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
3656 // that we can match with a CSNEG rather than a CSEL.
3657 ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(TVal.getOperand(0));
3659 if (CVal && CVal->isNullValue()) {
3660 std::swap(TVal, FVal);
3661 std::swap(CTVal, CFVal);
3662 CC = ISD::getSetCCInverse(CC, true);
3664 } else if (CTVal && CFVal) {
3665 const int64_t TrueVal = CTVal->getSExtValue();
3666 const int64_t FalseVal = CFVal->getSExtValue();
3669 // If both TVal and FVal are constants, see if FVal is the
3670 // inverse/negation/increment of TVal and generate a CSINV/CSNEG/CSINC
3671 // instead of a CSEL in that case.
3672 if (TrueVal == ~FalseVal) {
3673 Opcode = AArch64ISD::CSINV;
3674 } else if (TrueVal == -FalseVal) {
3675 Opcode = AArch64ISD::CSNEG;
3676 } else if (TVal.getValueType() == MVT::i32) {
3677 // If our operands are only 32-bit wide, make sure we use 32-bit
3678 // arithmetic for the check whether we can use CSINC. This ensures that
3679 // the addition in the check will wrap around properly in case there is
3680 // an overflow (which would not be the case if we do the check with
3681 // 64-bit arithmetic).
3682 const uint32_t TrueVal32 = CTVal->getZExtValue();
3683 const uint32_t FalseVal32 = CFVal->getZExtValue();
3685 if ((TrueVal32 == FalseVal32 + 1) || (TrueVal32 + 1 == FalseVal32)) {
3686 Opcode = AArch64ISD::CSINC;
3688 if (TrueVal32 > FalseVal32) {
3692 // 64-bit check whether we can use CSINC.
3693 } else if ((TrueVal == FalseVal + 1) || (TrueVal + 1 == FalseVal)) {
3694 Opcode = AArch64ISD::CSINC;
3696 if (TrueVal > FalseVal) {
3701 // Swap TVal and FVal if necessary.
3703 std::swap(TVal, FVal);
3704 std::swap(CTVal, CFVal);
3705 CC = ISD::getSetCCInverse(CC, true);
3708 if (Opcode != AArch64ISD::CSEL) {
3709 // Drop FVal since we can get its value by simply inverting/negating
3716 SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
3718 EVT VT = Op.getValueType();
3719 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
3722 // Now we know we're dealing with FP values.
3723 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3724 assert(LHS.getValueType() == RHS.getValueType());
3725 EVT VT = Op.getValueType();
3727 // Try to match this select into a max/min operation, which have dedicated
3728 // opcode in the instruction set.
3729 // FIXME: This is not correct in the presence of NaNs, so we only enable this
3731 if (getTargetMachine().Options.NoNaNsFPMath) {
3732 SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
3733 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
3734 selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
3735 CC = ISD::getSetCCSwappedOperands(CC);
3736 std::swap(MinMaxLHS, MinMaxRHS);
3739 if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
3740 selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
3750 return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
3758 return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
3764 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3765 // and do the comparison.
3766 SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
3768 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
3769 // clean. Some of them require two CSELs to implement.
3770 AArch64CC::CondCode CC1, CC2;
3771 changeFPCCToAArch64CC(CC, CC1, CC2);
3772 SDValue CC1Val = DAG.getConstant(CC1, MVT::i32);
3773 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3775 // If we need a second CSEL, emit it, using the output of the first as the
3776 // RHS. We're effectively OR'ing the two CC's together.
3777 if (CC2 != AArch64CC::AL) {
3778 SDValue CC2Val = DAG.getConstant(CC2, MVT::i32);
3779 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3782 // Otherwise, return the output of the first CSEL.
3786 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
3787 SelectionDAG &DAG) const {
3788 // Jump table entries as PC relative offsets. No additional tweaking
3789 // is necessary here. Just get the address of the jump table.
3790 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3791 EVT PtrVT = getPointerTy();
3794 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3795 !Subtarget->isTargetMachO()) {
3796 const unsigned char MO_NC = AArch64II::MO_NC;
3798 AArch64ISD::WrapperLarge, DL, PtrVT,
3799 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G3),
3800 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G2 | MO_NC),
3801 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_G1 | MO_NC),
3802 DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3803 AArch64II::MO_G0 | MO_NC));
3807 DAG.getTargetJumpTable(JT->getIndex(), PtrVT, AArch64II::MO_PAGE);
3808 SDValue Lo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
3809 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3810 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3811 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3814 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
3815 SelectionDAG &DAG) const {
3816 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3817 EVT PtrVT = getPointerTy();
3820 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
3821 // Use the GOT for the large code model on iOS.
3822 if (Subtarget->isTargetMachO()) {
3823 SDValue GotAddr = DAG.getTargetConstantPool(
3824 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3826 return DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, GotAddr);
3829 const unsigned char MO_NC = AArch64II::MO_NC;
3831 AArch64ISD::WrapperLarge, DL, PtrVT,
3832 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3833 CP->getOffset(), AArch64II::MO_G3),
3834 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3835 CP->getOffset(), AArch64II::MO_G2 | MO_NC),
3836 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3837 CP->getOffset(), AArch64II::MO_G1 | MO_NC),
3838 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3839 CP->getOffset(), AArch64II::MO_G0 | MO_NC));
3841 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
3842 // ELF, the only valid one on Darwin.
3844 DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment(),
3845 CP->getOffset(), AArch64II::MO_PAGE);
3846 SDValue Lo = DAG.getTargetConstantPool(
3847 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(),
3848 AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3850 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3851 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3855 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
3856 SelectionDAG &DAG) const {
3857 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
3858 EVT PtrVT = getPointerTy();
3860 if (getTargetMachine().getCodeModel() == CodeModel::Large &&
3861 !Subtarget->isTargetMachO()) {
3862 const unsigned char MO_NC = AArch64II::MO_NC;
3864 AArch64ISD::WrapperLarge, DL, PtrVT,
3865 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G3),
3866 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G2 | MO_NC),
3867 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G1 | MO_NC),
3868 DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_G0 | MO_NC));
3870 SDValue Hi = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGE);
3871 SDValue Lo = DAG.getTargetBlockAddress(BA, PtrVT, 0, AArch64II::MO_PAGEOFF |
3873 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, Hi);
3874 return DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, Lo);
3878 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
3879 SelectionDAG &DAG) const {
3880 AArch64FunctionInfo *FuncInfo =
3881 DAG.getMachineFunction().getInfo<AArch64FunctionInfo>();
3885 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3886 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3887 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
3888 MachinePointerInfo(SV), false, false, 0);
3891 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
3892 SelectionDAG &DAG) const {
3893 // The layout of the va_list struct is specified in the AArch64 Procedure Call
3894 // Standard, section B.3.
3895 MachineFunction &MF = DAG.getMachineFunction();
3896 AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
3899 SDValue Chain = Op.getOperand(0);
3900 SDValue VAList = Op.getOperand(1);
3901 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3902 SmallVector<SDValue, 4> MemOps;
3904 // void *__stack at offset 0
3906 DAG.getFrameIndex(FuncInfo->getVarArgsStackIndex(), getPointerTy());
3907 MemOps.push_back(DAG.getStore(Chain, DL, Stack, VAList,
3908 MachinePointerInfo(SV), false, false, 8));
3910 // void *__gr_top at offset 8
3911 int GPRSize = FuncInfo->getVarArgsGPRSize();
3913 SDValue GRTop, GRTopAddr;
3915 GRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3916 DAG.getConstant(8, getPointerTy()));
3918 GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), getPointerTy());
3919 GRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), GRTop,
3920 DAG.getConstant(GPRSize, getPointerTy()));
3922 MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
3923 MachinePointerInfo(SV, 8), false, false, 8));
3926 // void *__vr_top at offset 16
3927 int FPRSize = FuncInfo->getVarArgsFPRSize();
3929 SDValue VRTop, VRTopAddr;
3930 VRTopAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3931 DAG.getConstant(16, getPointerTy()));
3933 VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), getPointerTy());
3934 VRTop = DAG.getNode(ISD::ADD, DL, getPointerTy(), VRTop,
3935 DAG.getConstant(FPRSize, getPointerTy()));
3937 MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
3938 MachinePointerInfo(SV, 16), false, false, 8));
3941 // int __gr_offs at offset 24
3942 SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3943 DAG.getConstant(24, getPointerTy()));
3944 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, MVT::i32),
3945 GROffsAddr, MachinePointerInfo(SV, 24), false,
3948 // int __vr_offs at offset 28
3949 SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3950 DAG.getConstant(28, getPointerTy()));
3951 MemOps.push_back(DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, MVT::i32),
3952 VROffsAddr, MachinePointerInfo(SV, 28), false,
3955 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
3958 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
3959 SelectionDAG &DAG) const {
3960 return Subtarget->isTargetDarwin() ? LowerDarwin_VASTART(Op, DAG)
3961 : LowerAAPCS_VASTART(Op, DAG);
3964 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
3965 SelectionDAG &DAG) const {
3966 // AAPCS has three pointers and two ints (= 32 bytes), Darwin has single
3968 unsigned VaListSize = Subtarget->isTargetDarwin() ? 8 : 32;
3969 const Value *DestSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
3970 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
3972 return DAG.getMemcpy(Op.getOperand(0), SDLoc(Op), Op.getOperand(1),
3973 Op.getOperand(2), DAG.getConstant(VaListSize, MVT::i32),
3974 8, false, false, MachinePointerInfo(DestSV),
3975 MachinePointerInfo(SrcSV));
3978 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
3979 assert(Subtarget->isTargetDarwin() &&
3980 "automatic va_arg instruction only works on Darwin");
3982 const Value *V = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3983 EVT VT = Op.getValueType();
3985 SDValue Chain = Op.getOperand(0);
3986 SDValue Addr = Op.getOperand(1);
3987 unsigned Align = Op.getConstantOperandVal(3);
3989 SDValue VAList = DAG.getLoad(getPointerTy(), DL, Chain, Addr,
3990 MachinePointerInfo(V), false, false, false, 0);
3991 Chain = VAList.getValue(1);
3994 assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
3995 VAList = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
3996 DAG.getConstant(Align - 1, getPointerTy()));
3997 VAList = DAG.getNode(ISD::AND, DL, getPointerTy(), VAList,
3998 DAG.getConstant(-(int64_t)Align, getPointerTy()));
4001 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
4002 uint64_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
4004 // Scalar integer and FP values smaller than 64 bits are implicitly extended
4005 // up to 64 bits. At the very least, we have to increase the striding of the
4006 // vaargs list to match this, and for FP values we need to introduce
4007 // FP_ROUND nodes as well.
4008 if (VT.isInteger() && !VT.isVector())
4010 bool NeedFPTrunc = false;
4011 if (VT.isFloatingPoint() && !VT.isVector() && VT != MVT::f64) {
4016 // Increment the pointer, VAList, to the next vaarg
4017 SDValue VANext = DAG.getNode(ISD::ADD, DL, getPointerTy(), VAList,
4018 DAG.getConstant(ArgSize, getPointerTy()));
4019 // Store the incremented VAList to the legalized pointer
4020 SDValue APStore = DAG.getStore(Chain, DL, VANext, Addr, MachinePointerInfo(V),
4023 // Load the actual argument out of the pointer VAList
4025 // Load the value as an f64.
4026 SDValue WideFP = DAG.getLoad(MVT::f64, DL, APStore, VAList,
4027 MachinePointerInfo(), false, false, false, 0);
4028 // Round the value down to an f32.
4029 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0),
4030 DAG.getIntPtrConstant(1));
4031 SDValue Ops[] = { NarrowFP, WideFP.getValue(1) };
4032 // Merge the rounded value with the chain output of the load.
4033 return DAG.getMergeValues(Ops, DL);
4036 return DAG.getLoad(VT, DL, APStore, VAList, MachinePointerInfo(), false,
4040 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
4041 SelectionDAG &DAG) const {
4042 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4043 MFI->setFrameAddressIsTaken(true);
4045 EVT VT = Op.getValueType();
4047 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4049 DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
4051 FrameAddr = DAG.getLoad(VT, DL, DAG.getEntryNode(), FrameAddr,
4052 MachinePointerInfo(), false, false, false, 0);
4056 // FIXME? Maybe this could be a TableGen attribute on some registers and
4057 // this table could be generated automatically from RegInfo.
4058 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName,
4060 unsigned Reg = StringSwitch<unsigned>(RegName)
4061 .Case("sp", AArch64::SP)
4065 report_fatal_error("Invalid register name global variable");
4068 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
4069 SelectionDAG &DAG) const {
4070 MachineFunction &MF = DAG.getMachineFunction();
4071 MachineFrameInfo *MFI = MF.getFrameInfo();
4072 MFI->setReturnAddressIsTaken(true);
4074 EVT VT = Op.getValueType();
4076 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4078 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4079 SDValue Offset = DAG.getConstant(8, getPointerTy());
4080 return DAG.getLoad(VT, DL, DAG.getEntryNode(),
4081 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
4082 MachinePointerInfo(), false, false, false, 0);
4085 // Return LR, which contains the return address. Mark it an implicit live-in.
4086 unsigned Reg = MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass);
4087 return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, VT);
4090 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4091 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4092 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
4093 SelectionDAG &DAG) const {
4094 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4095 EVT VT = Op.getValueType();
4096 unsigned VTBits = VT.getSizeInBits();
4098 SDValue ShOpLo = Op.getOperand(0);
4099 SDValue ShOpHi = Op.getOperand(1);
4100 SDValue ShAmt = Op.getOperand(2);
4102 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4104 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4106 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4107 DAG.getConstant(VTBits, MVT::i64), ShAmt);
4108 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4109 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4110 DAG.getConstant(VTBits, MVT::i64));
4111 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4113 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
4114 ISD::SETGE, dl, DAG);
4115 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
4117 SDValue FalseValLo = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4118 SDValue TrueValLo = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4120 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4122 // AArch64 shifts larger than the register width are wrapped rather than
4123 // clamped, so we can't just emit "hi >> x".
4124 SDValue FalseValHi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4125 SDValue TrueValHi = Opc == ISD::SRA
4126 ? DAG.getNode(Opc, dl, VT, ShOpHi,
4127 DAG.getConstant(VTBits - 1, MVT::i64))
4128 : DAG.getConstant(0, VT);
4130 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValHi, FalseValHi, CCVal, Cmp);
4132 SDValue Ops[2] = { Lo, Hi };
4133 return DAG.getMergeValues(Ops, dl);
4136 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4137 /// i64 values and take a 2 x i64 value to shift plus a shift amount.
4138 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
4139 SelectionDAG &DAG) const {
4140 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4141 EVT VT = Op.getValueType();
4142 unsigned VTBits = VT.getSizeInBits();
4144 SDValue ShOpLo = Op.getOperand(0);
4145 SDValue ShOpHi = Op.getOperand(1);
4146 SDValue ShAmt = Op.getOperand(2);
4149 assert(Op.getOpcode() == ISD::SHL_PARTS);
4150 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4151 DAG.getConstant(VTBits, MVT::i64), ShAmt);
4152 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4153 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4154 DAG.getConstant(VTBits, MVT::i64));
4155 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4156 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4158 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4160 SDValue Cmp = emitComparison(ExtraShAmt, DAG.getConstant(0, MVT::i64),
4161 ISD::SETGE, dl, DAG);
4162 SDValue CCVal = DAG.getConstant(AArch64CC::GE, MVT::i32);
4164 DAG.getNode(AArch64ISD::CSEL, dl, VT, Tmp3, FalseVal, CCVal, Cmp);
4166 // AArch64 shifts of larger than register sizes are wrapped rather than
4167 // clamped, so we can't just emit "lo << a" if a is too big.
4168 SDValue TrueValLo = DAG.getConstant(0, VT);
4169 SDValue FalseValLo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4171 DAG.getNode(AArch64ISD::CSEL, dl, VT, TrueValLo, FalseValLo, CCVal, Cmp);
4173 SDValue Ops[2] = { Lo, Hi };
4174 return DAG.getMergeValues(Ops, dl);
4177 bool AArch64TargetLowering::isOffsetFoldingLegal(
4178 const GlobalAddressSDNode *GA) const {
4179 // The AArch64 target doesn't support folding offsets into global addresses.
4183 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4184 // We can materialize #0.0 as fmov $Rd, XZR for 64-bit and 32-bit cases.
4185 // FIXME: We should be able to handle f128 as well with a clever lowering.
4186 if (Imm.isPosZero() && (VT == MVT::f64 || VT == MVT::f32))
4190 return AArch64_AM::getFP64Imm(Imm) != -1;
4191 else if (VT == MVT::f32)
4192 return AArch64_AM::getFP32Imm(Imm) != -1;
4196 //===----------------------------------------------------------------------===//
4197 // AArch64 Optimization Hooks
4198 //===----------------------------------------------------------------------===//
4200 //===----------------------------------------------------------------------===//
4201 // AArch64 Inline Assembly Support
4202 //===----------------------------------------------------------------------===//
4204 // Table of Constraints
4205 // TODO: This is the current set of constraints supported by ARM for the
4206 // compiler, not all of them may make sense, e.g. S may be difficult to support.
4208 // r - A general register
4209 // w - An FP/SIMD register of some size in the range v0-v31
4210 // x - An FP/SIMD register of some size in the range v0-v15
4211 // I - Constant that can be used with an ADD instruction
4212 // J - Constant that can be used with a SUB instruction
4213 // K - Constant that can be used with a 32-bit logical instruction
4214 // L - Constant that can be used with a 64-bit logical instruction
4215 // M - Constant that can be used as a 32-bit MOV immediate
4216 // N - Constant that can be used as a 64-bit MOV immediate
4217 // Q - A memory reference with base register and no offset
4218 // S - A symbolic address
4219 // Y - Floating point constant zero
4220 // Z - Integer constant zero
4222 // Note that general register operands will be output using their 64-bit x
4223 // register name, whatever the size of the variable, unless the asm operand
4224 // is prefixed by the %w modifier. Floating-point and SIMD register operands
4225 // will be output with the v prefix unless prefixed by the %b, %h, %s, %d or
4228 /// getConstraintType - Given a constraint letter, return the type of
4229 /// constraint it is for this target.
4230 AArch64TargetLowering::ConstraintType
4231 AArch64TargetLowering::getConstraintType(const std::string &Constraint) const {
4232 if (Constraint.size() == 1) {
4233 switch (Constraint[0]) {
4240 return C_RegisterClass;
4241 // An address with a single base register. Due to the way we
4242 // currently handle addresses it is the same as 'r'.
4247 return TargetLowering::getConstraintType(Constraint);
4250 /// Examine constraint type and operand type and determine a weight value.
4251 /// This object must already have been set up with the operand type
4252 /// and the current alternative constraint selected.
4253 TargetLowering::ConstraintWeight
4254 AArch64TargetLowering::getSingleConstraintMatchWeight(
4255 AsmOperandInfo &info, const char *constraint) const {
4256 ConstraintWeight weight = CW_Invalid;
4257 Value *CallOperandVal = info.CallOperandVal;
4258 // If we don't have a value, we can't do a match,
4259 // but allow it at the lowest weight.
4260 if (!CallOperandVal)
4262 Type *type = CallOperandVal->getType();
4263 // Look at the constraint type.
4264 switch (*constraint) {
4266 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4270 if (type->isFloatingPointTy() || type->isVectorTy())
4271 weight = CW_Register;
4274 weight = CW_Constant;
4280 std::pair<unsigned, const TargetRegisterClass *>
4281 AArch64TargetLowering::getRegForInlineAsmConstraint(
4282 const std::string &Constraint, MVT VT) const {
4283 if (Constraint.size() == 1) {
4284 switch (Constraint[0]) {
4286 if (VT.getSizeInBits() == 64)
4287 return std::make_pair(0U, &AArch64::GPR64commonRegClass);
4288 return std::make_pair(0U, &AArch64::GPR32commonRegClass);
4291 return std::make_pair(0U, &AArch64::FPR32RegClass);
4292 if (VT.getSizeInBits() == 64)
4293 return std::make_pair(0U, &AArch64::FPR64RegClass);
4294 if (VT.getSizeInBits() == 128)
4295 return std::make_pair(0U, &AArch64::FPR128RegClass);
4297 // The instructions that this constraint is designed for can
4298 // only take 128-bit registers so just use that regclass.
4300 if (VT.getSizeInBits() == 128)
4301 return std::make_pair(0U, &AArch64::FPR128_loRegClass);
4305 if (StringRef("{cc}").equals_lower(Constraint))
4306 return std::make_pair(unsigned(AArch64::NZCV), &AArch64::CCRRegClass);
4308 // Use the default implementation in TargetLowering to convert the register
4309 // constraint into a member of a register class.
4310 std::pair<unsigned, const TargetRegisterClass *> Res;
4311 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4313 // Not found as a standard register?
4315 unsigned Size = Constraint.size();
4316 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4317 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4318 const std::string Reg =
4319 std::string(&Constraint[2], &Constraint[Size - 1]);
4320 int RegNo = atoi(Reg.c_str());
4321 if (RegNo >= 0 && RegNo <= 31) {
4322 // v0 - v31 are aliases of q0 - q31.
4323 // By default we'll emit v0-v31 for this unless there's a modifier where
4324 // we'll emit the correct register as well.
4325 Res.first = AArch64::FPR128RegClass.getRegister(RegNo);
4326 Res.second = &AArch64::FPR128RegClass;
4334 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4335 /// vector. If it is invalid, don't add anything to Ops.
4336 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4337 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4338 SelectionDAG &DAG) const {
4341 // Currently only support length 1 constraints.
4342 if (Constraint.length() != 1)
4345 char ConstraintLetter = Constraint[0];
4346 switch (ConstraintLetter) {
4350 // This set of constraints deal with valid constants for various instructions.
4351 // Validate and return a target constant for them if we can.
4353 // 'z' maps to xzr or wzr so it needs an input of 0.
4354 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4355 if (!C || C->getZExtValue() != 0)
4358 if (Op.getValueType() == MVT::i64)
4359 Result = DAG.getRegister(AArch64::XZR, MVT::i64);
4361 Result = DAG.getRegister(AArch64::WZR, MVT::i32);
4371 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4375 // Grab the value and do some validation.
4376 uint64_t CVal = C->getZExtValue();
4377 switch (ConstraintLetter) {
4378 // The I constraint applies only to simple ADD or SUB immediate operands:
4379 // i.e. 0 to 4095 with optional shift by 12
4380 // The J constraint applies only to ADD or SUB immediates that would be
4381 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4382 // instruction [or vice versa], in other words -1 to -4095 with optional
4383 // left shift by 12.
4385 if (isUInt<12>(CVal) || isShiftedUInt<12, 12>(CVal))
4389 uint64_t NVal = -C->getSExtValue();
4390 if (isUInt<12>(NVal) || isShiftedUInt<12, 12>(NVal)) {
4391 CVal = C->getSExtValue();
4396 // The K and L constraints apply *only* to logical immediates, including
4397 // what used to be the MOVI alias for ORR (though the MOVI alias has now
4398 // been removed and MOV should be used). So these constraints have to
4399 // distinguish between bit patterns that are valid 32-bit or 64-bit
4400 // "bitmask immediates": for example 0xaaaaaaaa is a valid bimm32 (K), but
4401 // not a valid bimm64 (L) where 0xaaaaaaaaaaaaaaaa would be valid, and vice
4404 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4408 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4411 // The M and N constraints are a superset of K and L respectively, for use
4412 // with the MOV (immediate) alias. As well as the logical immediates they
4413 // also match 32 or 64-bit immediates that can be loaded either using a
4414 // *single* MOVZ or MOVN , such as 32-bit 0x12340000, 0x00001234, 0xffffedca
4415 // (M) or 64-bit 0x1234000000000000 (N) etc.
4416 // As a note some of this code is liberally stolen from the asm parser.
4418 if (!isUInt<32>(CVal))
4420 if (AArch64_AM::isLogicalImmediate(CVal, 32))
4422 if ((CVal & 0xFFFF) == CVal)
4424 if ((CVal & 0xFFFF0000ULL) == CVal)
4426 uint64_t NCVal = ~(uint32_t)CVal;
4427 if ((NCVal & 0xFFFFULL) == NCVal)
4429 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4434 if (AArch64_AM::isLogicalImmediate(CVal, 64))
4436 if ((CVal & 0xFFFFULL) == CVal)
4438 if ((CVal & 0xFFFF0000ULL) == CVal)
4440 if ((CVal & 0xFFFF00000000ULL) == CVal)
4442 if ((CVal & 0xFFFF000000000000ULL) == CVal)
4444 uint64_t NCVal = ~CVal;
4445 if ((NCVal & 0xFFFFULL) == NCVal)
4447 if ((NCVal & 0xFFFF0000ULL) == NCVal)
4449 if ((NCVal & 0xFFFF00000000ULL) == NCVal)
4451 if ((NCVal & 0xFFFF000000000000ULL) == NCVal)
4459 // All assembler immediates are 64-bit integers.
4460 Result = DAG.getTargetConstant(CVal, MVT::i64);
4464 if (Result.getNode()) {
4465 Ops.push_back(Result);
4469 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4472 //===----------------------------------------------------------------------===//
4473 // AArch64 Advanced SIMD Support
4474 //===----------------------------------------------------------------------===//
4476 /// WidenVector - Given a value in the V64 register class, produce the
4477 /// equivalent value in the V128 register class.
4478 static SDValue WidenVector(SDValue V64Reg, SelectionDAG &DAG) {
4479 EVT VT = V64Reg.getValueType();
4480 unsigned NarrowSize = VT.getVectorNumElements();
4481 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4482 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
4485 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy),
4486 V64Reg, DAG.getConstant(0, MVT::i32));
4489 /// getExtFactor - Determine the adjustment factor for the position when
4490 /// generating an "extract from vector registers" instruction.
4491 static unsigned getExtFactor(SDValue &V) {
4492 EVT EltType = V.getValueType().getVectorElementType();
4493 return EltType.getSizeInBits() / 8;
4496 /// NarrowVector - Given a value in the V128 register class, produce the
4497 /// equivalent value in the V64 register class.
4498 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
4499 EVT VT = V128Reg.getValueType();
4500 unsigned WideSize = VT.getVectorNumElements();
4501 MVT EltTy = VT.getVectorElementType().getSimpleVT();
4502 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
4505 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg);
4508 // Gather data to see if the operation can be modelled as a
4509 // shuffle in combination with VEXTs.
4510 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
4511 SelectionDAG &DAG) const {
4512 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
4514 EVT VT = Op.getValueType();
4515 unsigned NumElts = VT.getVectorNumElements();
4517 struct ShuffleSourceInfo {
4522 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
4523 // be compatible with the shuffle we intend to construct. As a result
4524 // ShuffleVec will be some sliding window into the original Vec.
4527 // Code should guarantee that element i in Vec starts at element "WindowBase
4528 // + i * WindowScale in ShuffleVec".
4532 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
4533 ShuffleSourceInfo(SDValue Vec)
4534 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
4538 // First gather all vectors used as an immediate source for this BUILD_VECTOR
4540 SmallVector<ShuffleSourceInfo, 2> Sources;
4541 for (unsigned i = 0; i < NumElts; ++i) {
4542 SDValue V = Op.getOperand(i);
4543 if (V.getOpcode() == ISD::UNDEF)
4545 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4546 // A shuffle can only come from building a vector from various
4547 // elements of other vectors.
4551 // Add this element source to the list if it's not already there.
4552 SDValue SourceVec = V.getOperand(0);
4553 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
4554 if (Source == Sources.end())
4555 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
4557 // Update the minimum and maximum lane number seen.
4558 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4559 Source->MinElt = std::min(Source->MinElt, EltNo);
4560 Source->MaxElt = std::max(Source->MaxElt, EltNo);
4563 // Currently only do something sane when at most two source vectors
4565 if (Sources.size() > 2)
4568 // Find out the smallest element size among result and two sources, and use
4569 // it as element size to build the shuffle_vector.
4570 EVT SmallestEltTy = VT.getVectorElementType();
4571 for (auto &Source : Sources) {
4572 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
4573 if (SrcEltTy.bitsLT(SmallestEltTy)) {
4574 SmallestEltTy = SrcEltTy;
4577 unsigned ResMultiplier =
4578 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
4579 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
4580 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
4582 // If the source vector is too wide or too narrow, we may nevertheless be able
4583 // to construct a compatible shuffle either by concatenating it with UNDEF or
4584 // extracting a suitable range of elements.
4585 for (auto &Src : Sources) {
4586 EVT SrcVT = Src.ShuffleVec.getValueType();
4588 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
4591 // This stage of the search produces a source with the same element type as
4592 // the original, but with a total width matching the BUILD_VECTOR output.
4593 EVT EltVT = SrcVT.getVectorElementType();
4594 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
4595 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
4597 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
4598 assert(2 * SrcVT.getSizeInBits() == VT.getSizeInBits());
4599 // We can pad out the smaller vector for free, so if it's part of a
4602 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
4603 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
4607 assert(SrcVT.getSizeInBits() == 2 * VT.getSizeInBits());
4609 if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
4610 // Span too large for a VEXT to cope
4614 if (Src.MinElt >= NumSrcElts) {
4615 // The extraction can just take the second half
4617 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4618 DAG.getIntPtrConstant(NumSrcElts));
4619 Src.WindowBase = -NumSrcElts;
4620 } else if (Src.MaxElt < NumSrcElts) {
4621 // The extraction can just take the first half
4622 Src.ShuffleVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT,
4623 Src.ShuffleVec, DAG.getIntPtrConstant(0));
4625 // An actual VEXT is needed
4626 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT,
4627 Src.ShuffleVec, DAG.getIntPtrConstant(0));
4629 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
4630 DAG.getIntPtrConstant(NumSrcElts));
4631 unsigned Imm = Src.MinElt * getExtFactor(VEXTSrc1);
4633 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
4634 VEXTSrc2, DAG.getConstant(Imm, MVT::i32));
4635 Src.WindowBase = -Src.MinElt;
4639 // Another possible incompatibility occurs from the vector element types. We
4640 // can fix this by bitcasting the source vectors to the same type we intend
4642 for (auto &Src : Sources) {
4643 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
4644 if (SrcEltTy == SmallestEltTy)
4646 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
4647 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
4648 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
4649 Src.WindowBase *= Src.WindowScale;
4652 // Final sanity check before we try to actually produce a shuffle.
4654 for (auto Src : Sources)
4655 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
4658 // The stars all align, our next step is to produce the mask for the shuffle.
4659 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
4660 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
4661 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
4662 SDValue Entry = Op.getOperand(i);
4663 if (Entry.getOpcode() == ISD::UNDEF)
4666 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
4667 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
4669 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
4670 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
4672 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
4673 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
4674 VT.getVectorElementType().getSizeInBits());
4675 int LanesDefined = BitsDefined / BitsPerShuffleLane;
4677 // This source is expected to fill ResMultiplier lanes of the final shuffle,
4678 // starting at the appropriate offset.
4679 int *LaneMask = &Mask[i * ResMultiplier];
4681 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
4682 ExtractBase += NumElts * (Src - Sources.begin());
4683 for (int j = 0; j < LanesDefined; ++j)
4684 LaneMask[j] = ExtractBase + j;
4687 // Final check before we try to produce nonsense...
4688 if (!isShuffleMaskLegal(Mask, ShuffleVT))
4691 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
4692 for (unsigned i = 0; i < Sources.size(); ++i)
4693 ShuffleOps[i] = Sources[i].ShuffleVec;
4695 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
4696 ShuffleOps[1], &Mask[0]);
4697 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
4700 // check if an EXT instruction can handle the shuffle mask when the
4701 // vector sources of the shuffle are the same.
4702 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4703 unsigned NumElts = VT.getVectorNumElements();
4705 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4711 // If this is a VEXT shuffle, the immediate value is the index of the first
4712 // element. The other shuffle indices must be the successive elements after
4714 unsigned ExpectedElt = Imm;
4715 for (unsigned i = 1; i < NumElts; ++i) {
4716 // Increment the expected index. If it wraps around, just follow it
4717 // back to index zero and keep going.
4719 if (ExpectedElt == NumElts)
4723 continue; // ignore UNDEF indices
4724 if (ExpectedElt != static_cast<unsigned>(M[i]))
4731 // check if an EXT instruction can handle the shuffle mask when the
4732 // vector sources of the shuffle are different.
4733 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
4735 // Look for the first non-undef element.
4736 const int *FirstRealElt = std::find_if(M.begin(), M.end(),
4737 [](int Elt) {return Elt >= 0;});
4739 // Benefit form APInt to handle overflow when calculating expected element.
4740 unsigned NumElts = VT.getVectorNumElements();
4741 unsigned MaskBits = APInt(32, NumElts * 2).logBase2();
4742 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1);
4743 // The following shuffle indices must be the successive elements after the
4744 // first real element.
4745 const int *FirstWrongElt = std::find_if(FirstRealElt + 1, M.end(),
4746 [&](int Elt) {return Elt != ExpectedElt++ && Elt != -1;});
4747 if (FirstWrongElt != M.end())
4750 // The index of an EXT is the first element if it is not UNDEF.
4751 // Watch out for the beginning UNDEFs. The EXT index should be the expected
4752 // value of the first element. E.g.
4753 // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
4754 // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
4755 // ExpectedElt is the last mask index plus 1.
4756 Imm = ExpectedElt.getZExtValue();
4758 // There are two difference cases requiring to reverse input vectors.
4759 // For example, for vector <4 x i32> we have the following cases,
4760 // Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
4761 // Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
4762 // For both cases, we finally use mask <5, 6, 7, 0>, which requires
4763 // to reverse two input vectors.
4772 /// isREVMask - Check if a vector shuffle corresponds to a REV
4773 /// instruction with the specified blocksize. (The order of the elements
4774 /// within each block of the vector is reversed.)
4775 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4776 assert((BlockSize == 16 || BlockSize == 32 || BlockSize == 64) &&
4777 "Only possible block sizes for REV are: 16, 32, 64");
4779 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4783 unsigned NumElts = VT.getVectorNumElements();
4784 unsigned BlockElts = M[0] + 1;
4785 // If the first shuffle index is UNDEF, be optimistic.
4787 BlockElts = BlockSize / EltSz;
4789 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4792 for (unsigned i = 0; i < NumElts; ++i) {
4794 continue; // ignore UNDEF indices
4795 if ((unsigned)M[i] != (i - i % BlockElts) + (BlockElts - 1 - i % BlockElts))
4802 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4803 unsigned NumElts = VT.getVectorNumElements();
4804 WhichResult = (M[0] == 0 ? 0 : 1);
4805 unsigned Idx = WhichResult * NumElts / 2;
4806 for (unsigned i = 0; i != NumElts; i += 2) {
4807 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4808 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx + NumElts))
4816 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4817 unsigned NumElts = VT.getVectorNumElements();
4818 WhichResult = (M[0] == 0 ? 0 : 1);
4819 for (unsigned i = 0; i != NumElts; ++i) {
4821 continue; // ignore UNDEF indices
4822 if ((unsigned)M[i] != 2 * i + WhichResult)
4829 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4830 unsigned NumElts = VT.getVectorNumElements();
4831 WhichResult = (M[0] == 0 ? 0 : 1);
4832 for (unsigned i = 0; i < NumElts; i += 2) {
4833 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4834 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))
4840 /// isZIP_v_undef_Mask - Special case of isZIPMask for canonical form of
4841 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4842 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4843 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4844 unsigned NumElts = VT.getVectorNumElements();
4845 WhichResult = (M[0] == 0 ? 0 : 1);
4846 unsigned Idx = WhichResult * NumElts / 2;
4847 for (unsigned i = 0; i != NumElts; i += 2) {
4848 if ((M[i] >= 0 && (unsigned)M[i] != Idx) ||
4849 (M[i + 1] >= 0 && (unsigned)M[i + 1] != Idx))
4857 /// isUZP_v_undef_Mask - Special case of isUZPMask for canonical form of
4858 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4859 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4860 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4861 unsigned Half = VT.getVectorNumElements() / 2;
4862 WhichResult = (M[0] == 0 ? 0 : 1);
4863 for (unsigned j = 0; j != 2; ++j) {
4864 unsigned Idx = WhichResult;
4865 for (unsigned i = 0; i != Half; ++i) {
4866 int MIdx = M[i + j * Half];
4867 if (MIdx >= 0 && (unsigned)MIdx != Idx)
4876 /// isTRN_v_undef_Mask - Special case of isTRNMask for canonical form of
4877 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4878 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4879 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4880 unsigned NumElts = VT.getVectorNumElements();
4881 WhichResult = (M[0] == 0 ? 0 : 1);
4882 for (unsigned i = 0; i < NumElts; i += 2) {
4883 if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||
4884 (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))
4890 static bool isINSMask(ArrayRef<int> M, int NumInputElements,
4891 bool &DstIsLeft, int &Anomaly) {
4892 if (M.size() != static_cast<size_t>(NumInputElements))
4895 int NumLHSMatch = 0, NumRHSMatch = 0;
4896 int LastLHSMismatch = -1, LastRHSMismatch = -1;
4898 for (int i = 0; i < NumInputElements; ++i) {
4908 LastLHSMismatch = i;
4910 if (M[i] == i + NumInputElements)
4913 LastRHSMismatch = i;
4916 if (NumLHSMatch == NumInputElements - 1) {
4918 Anomaly = LastLHSMismatch;
4920 } else if (NumRHSMatch == NumInputElements - 1) {
4922 Anomaly = LastRHSMismatch;
4929 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {
4930 if (VT.getSizeInBits() != 128)
4933 unsigned NumElts = VT.getVectorNumElements();
4935 for (int I = 0, E = NumElts / 2; I != E; I++) {
4940 int Offset = NumElts / 2;
4941 for (int I = NumElts / 2, E = NumElts; I != E; I++) {
4942 if (Mask[I] != I + SplitLHS * Offset)
4949 static SDValue tryFormConcatFromShuffle(SDValue Op, SelectionDAG &DAG) {
4951 EVT VT = Op.getValueType();
4952 SDValue V0 = Op.getOperand(0);
4953 SDValue V1 = Op.getOperand(1);
4954 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();
4956 if (VT.getVectorElementType() != V0.getValueType().getVectorElementType() ||
4957 VT.getVectorElementType() != V1.getValueType().getVectorElementType())
4960 bool SplitV0 = V0.getValueType().getSizeInBits() == 128;
4962 if (!isConcatMask(Mask, VT, SplitV0))
4965 EVT CastVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
4966 VT.getVectorNumElements() / 2);
4968 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
4969 DAG.getConstant(0, MVT::i64));
4971 if (V1.getValueType().getSizeInBits() == 128) {
4972 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
4973 DAG.getConstant(0, MVT::i64));
4975 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
4978 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4979 /// the specified operations to build the shuffle.
4980 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4981 SDValue RHS, SelectionDAG &DAG,
4983 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4984 unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1);
4985 unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1);
4988 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4997 OP_VUZPL, // VUZP, left result
4998 OP_VUZPR, // VUZP, right result
4999 OP_VZIPL, // VZIP, left result
5000 OP_VZIPR, // VZIP, right result
5001 OP_VTRNL, // VTRN, left result
5002 OP_VTRNR // VTRN, right result
5005 if (OpNum == OP_COPY) {
5006 if (LHSID == (1 * 9 + 2) * 9 + 3)
5008 assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!");
5012 SDValue OpLHS, OpRHS;
5013 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5014 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5015 EVT VT = OpLHS.getValueType();
5019 llvm_unreachable("Unknown shuffle opcode!");
5021 // VREV divides the vector in half and swaps within the half.
5022 if (VT.getVectorElementType() == MVT::i32 ||
5023 VT.getVectorElementType() == MVT::f32)
5024 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS);
5025 // vrev <4 x i16> -> REV32
5026 if (VT.getVectorElementType() == MVT::i16 ||
5027 VT.getVectorElementType() == MVT::f16)
5028 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS);
5029 // vrev <4 x i8> -> REV16
5030 assert(VT.getVectorElementType() == MVT::i8);
5031 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS);
5036 EVT EltTy = VT.getVectorElementType();
5038 if (EltTy == MVT::i8)
5039 Opcode = AArch64ISD::DUPLANE8;
5040 else if (EltTy == MVT::i16)
5041 Opcode = AArch64ISD::DUPLANE16;
5042 else if (EltTy == MVT::i32 || EltTy == MVT::f32)
5043 Opcode = AArch64ISD::DUPLANE32;
5044 else if (EltTy == MVT::i64 || EltTy == MVT::f64)
5045 Opcode = AArch64ISD::DUPLANE64;
5047 llvm_unreachable("Invalid vector element type?");
5049 if (VT.getSizeInBits() == 64)
5050 OpLHS = WidenVector(OpLHS, DAG);
5051 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, MVT::i64);
5052 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane);
5057 unsigned Imm = (OpNum - OP_VEXT1 + 1) * getExtFactor(OpLHS);
5058 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
5059 DAG.getConstant(Imm, MVT::i32));
5062 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS,
5065 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS,
5068 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS,
5071 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS,
5074 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS,
5077 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS,
5082 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,
5083 SelectionDAG &DAG) {
5084 // Check to see if we can use the TBL instruction.
5085 SDValue V1 = Op.getOperand(0);
5086 SDValue V2 = Op.getOperand(1);
5089 EVT EltVT = Op.getValueType().getVectorElementType();
5090 unsigned BytesPerElt = EltVT.getSizeInBits() / 8;
5092 SmallVector<SDValue, 8> TBLMask;
5093 for (int Val : ShuffleMask) {
5094 for (unsigned Byte = 0; Byte < BytesPerElt; ++Byte) {
5095 unsigned Offset = Byte + Val * BytesPerElt;
5096 TBLMask.push_back(DAG.getConstant(Offset, MVT::i32));
5100 MVT IndexVT = MVT::v8i8;
5101 unsigned IndexLen = 8;
5102 if (Op.getValueType().getSizeInBits() == 128) {
5103 IndexVT = MVT::v16i8;
5107 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);
5108 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);
5111 if (V2.getNode()->getOpcode() == ISD::UNDEF) {
5113 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst);
5114 Shuffle = DAG.getNode(
5115 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5116 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
5117 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5118 makeArrayRef(TBLMask.data(), IndexLen)));
5120 if (IndexLen == 8) {
5121 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst);
5122 Shuffle = DAG.getNode(
5123 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5124 DAG.getConstant(Intrinsic::aarch64_neon_tbl1, MVT::i32), V1Cst,
5125 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5126 makeArrayRef(TBLMask.data(), IndexLen)));
5128 // FIXME: We cannot, for the moment, emit a TBL2 instruction because we
5129 // cannot currently represent the register constraints on the input
5131 // Shuffle = DAG.getNode(AArch64ISD::TBL2, DL, IndexVT, V1Cst, V2Cst,
5132 // DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5133 // &TBLMask[0], IndexLen));
5134 Shuffle = DAG.getNode(
5135 ISD::INTRINSIC_WO_CHAIN, DL, IndexVT,
5136 DAG.getConstant(Intrinsic::aarch64_neon_tbl2, MVT::i32), V1Cst, V2Cst,
5137 DAG.getNode(ISD::BUILD_VECTOR, DL, IndexVT,
5138 makeArrayRef(TBLMask.data(), IndexLen)));
5141 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);
5144 static unsigned getDUPLANEOp(EVT EltType) {
5145 if (EltType == MVT::i8)
5146 return AArch64ISD::DUPLANE8;
5147 if (EltType == MVT::i16 || EltType == MVT::f16)
5148 return AArch64ISD::DUPLANE16;
5149 if (EltType == MVT::i32 || EltType == MVT::f32)
5150 return AArch64ISD::DUPLANE32;
5151 if (EltType == MVT::i64 || EltType == MVT::f64)
5152 return AArch64ISD::DUPLANE64;
5154 llvm_unreachable("Invalid vector element type?");
5157 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5158 SelectionDAG &DAG) const {
5160 EVT VT = Op.getValueType();
5162 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5164 // Convert shuffles that are directly supported on NEON to target-specific
5165 // DAG nodes, instead of keeping them as shuffles and matching them again
5166 // during code selection. This is more efficient and avoids the possibility
5167 // of inconsistencies between legalization and selection.
5168 ArrayRef<int> ShuffleMask = SVN->getMask();
5170 SDValue V1 = Op.getOperand(0);
5171 SDValue V2 = Op.getOperand(1);
5173 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0],
5174 V1.getValueType().getSimpleVT())) {
5175 int Lane = SVN->getSplatIndex();
5176 // If this is undef splat, generate it via "just" vdup, if possible.
5180 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
5181 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(),
5183 // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
5184 // constant. If so, we can just reference the lane's definition directly.
5185 if (V1.getOpcode() == ISD::BUILD_VECTOR &&
5186 !isa<ConstantSDNode>(V1.getOperand(Lane)))
5187 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
5189 // Otherwise, duplicate from the lane of the input vector.
5190 unsigned Opcode = getDUPLANEOp(V1.getValueType().getVectorElementType());
5192 // SelectionDAGBuilder may have "helpfully" already extracted or conatenated
5193 // to make a vector of the same size as this SHUFFLE. We can ignore the
5194 // extract entirely, and canonicalise the concat using WidenVector.
5195 if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
5196 Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
5197 V1 = V1.getOperand(0);
5198 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
5199 unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
5200 Lane -= Idx * VT.getVectorNumElements() / 2;
5201 V1 = WidenVector(V1.getOperand(Idx), DAG);
5202 } else if (VT.getSizeInBits() == 64)
5203 V1 = WidenVector(V1, DAG);
5205 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, MVT::i64));
5208 if (isREVMask(ShuffleMask, VT, 64))
5209 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2);
5210 if (isREVMask(ShuffleMask, VT, 32))
5211 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2);
5212 if (isREVMask(ShuffleMask, VT, 16))
5213 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2);
5215 bool ReverseEXT = false;
5217 if (isEXTMask(ShuffleMask, VT, ReverseEXT, Imm)) {
5220 Imm *= getExtFactor(V1);
5221 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5222 DAG.getConstant(Imm, MVT::i32));
5223 } else if (V2->getOpcode() == ISD::UNDEF &&
5224 isSingletonEXTMask(ShuffleMask, VT, Imm)) {
5225 Imm *= getExtFactor(V1);
5226 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1,
5227 DAG.getConstant(Imm, MVT::i32));
5230 unsigned WhichResult;
5231 if (isZIPMask(ShuffleMask, VT, WhichResult)) {
5232 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5233 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5235 if (isUZPMask(ShuffleMask, VT, WhichResult)) {
5236 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5237 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5239 if (isTRNMask(ShuffleMask, VT, WhichResult)) {
5240 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5241 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2);
5244 if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5245 unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;
5246 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5248 if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5249 unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;
5250 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5252 if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {
5253 unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;
5254 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1);
5257 SDValue Concat = tryFormConcatFromShuffle(Op, DAG);
5258 if (Concat.getNode())
5263 int NumInputElements = V1.getValueType().getVectorNumElements();
5264 if (isINSMask(ShuffleMask, NumInputElements, DstIsLeft, Anomaly)) {
5265 SDValue DstVec = DstIsLeft ? V1 : V2;
5266 SDValue DstLaneV = DAG.getConstant(Anomaly, MVT::i64);
5268 SDValue SrcVec = V1;
5269 int SrcLane = ShuffleMask[Anomaly];
5270 if (SrcLane >= NumInputElements) {
5272 SrcLane -= VT.getVectorNumElements();
5274 SDValue SrcLaneV = DAG.getConstant(SrcLane, MVT::i64);
5276 EVT ScalarVT = VT.getVectorElementType();
5278 if (ScalarVT.getSizeInBits() < 32 && ScalarVT.isInteger())
5279 ScalarVT = MVT::i32;
5282 ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5283 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV),
5287 // If the shuffle is not directly supported and it has 4 elements, use
5288 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5289 unsigned NumElts = VT.getVectorNumElements();
5291 unsigned PFIndexes[4];
5292 for (unsigned i = 0; i != 4; ++i) {
5293 if (ShuffleMask[i] < 0)
5296 PFIndexes[i] = ShuffleMask[i];
5299 // Compute the index in the perfect shuffle table.
5300 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
5301 PFIndexes[2] * 9 + PFIndexes[3];
5302 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5303 unsigned Cost = (PFEntry >> 30);
5306 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5309 return GenerateTBL(Op, ShuffleMask, DAG);
5312 static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
5314 EVT VT = BVN->getValueType(0);
5315 APInt SplatBits, SplatUndef;
5316 unsigned SplatBitSize;
5318 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5319 unsigned NumSplats = VT.getSizeInBits() / SplatBitSize;
5321 for (unsigned i = 0; i < NumSplats; ++i) {
5322 CnstBits <<= SplatBitSize;
5323 UndefBits <<= SplatBitSize;
5324 CnstBits |= SplatBits.zextOrTrunc(VT.getSizeInBits());
5325 UndefBits |= (SplatBits ^ SplatUndef).zextOrTrunc(VT.getSizeInBits());
5334 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5335 SelectionDAG &DAG) const {
5336 BuildVectorSDNode *BVN =
5337 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5338 SDValue LHS = Op.getOperand(0);
5340 EVT VT = Op.getValueType();
5345 APInt CnstBits(VT.getSizeInBits(), 0);
5346 APInt UndefBits(VT.getSizeInBits(), 0);
5347 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5348 // We only have BIC vector immediate instruction, which is and-not.
5349 CnstBits = ~CnstBits;
5351 // We make use of a little bit of goto ickiness in order to avoid having to
5352 // duplicate the immediate matching logic for the undef toggled case.
5353 bool SecondTry = false;
5356 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5357 CnstBits = CnstBits.zextOrTrunc(64);
5358 uint64_t CnstVal = CnstBits.getZExtValue();
5360 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5361 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5362 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5363 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5364 DAG.getConstant(CnstVal, MVT::i32),
5365 DAG.getConstant(0, MVT::i32));
5366 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5369 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5370 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5371 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5372 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5373 DAG.getConstant(CnstVal, MVT::i32),
5374 DAG.getConstant(8, MVT::i32));
5375 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5378 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5379 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5380 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5381 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5382 DAG.getConstant(CnstVal, MVT::i32),
5383 DAG.getConstant(16, MVT::i32));
5384 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5387 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5388 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5389 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5390 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5391 DAG.getConstant(CnstVal, MVT::i32),
5392 DAG.getConstant(24, MVT::i32));
5393 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5396 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5397 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5398 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5399 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5400 DAG.getConstant(CnstVal, MVT::i32),
5401 DAG.getConstant(0, MVT::i32));
5402 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5405 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5406 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5407 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5408 SDValue Mov = DAG.getNode(AArch64ISD::BICi, dl, MovTy, LHS,
5409 DAG.getConstant(CnstVal, MVT::i32),
5410 DAG.getConstant(8, MVT::i32));
5411 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5418 CnstBits = ~UndefBits;
5422 // We can always fall back to a non-immediate AND.
5427 // Specialized code to quickly find if PotentialBVec is a BuildVector that
5428 // consists of only the same constant int value, returned in reference arg
5430 static bool isAllConstantBuildVector(const SDValue &PotentialBVec,
5431 uint64_t &ConstVal) {
5432 BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
5435 ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
5438 EVT VT = Bvec->getValueType(0);
5439 unsigned NumElts = VT.getVectorNumElements();
5440 for (unsigned i = 1; i < NumElts; ++i)
5441 if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
5443 ConstVal = FirstElt->getZExtValue();
5447 static unsigned getIntrinsicID(const SDNode *N) {
5448 unsigned Opcode = N->getOpcode();
5451 return Intrinsic::not_intrinsic;
5452 case ISD::INTRINSIC_WO_CHAIN: {
5453 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5454 if (IID < Intrinsic::num_intrinsics)
5456 return Intrinsic::not_intrinsic;
5461 // Attempt to form a vector S[LR]I from (or (and X, BvecC1), (lsl Y, C2)),
5462 // to (SLI X, Y, C2), where X and Y have matching vector types, BvecC1 is a
5463 // BUILD_VECTORs with constant element C1, C2 is a constant, and C1 == ~C2.
5464 // Also, logical shift right -> sri, with the same structure.
5465 static SDValue tryLowerToSLI(SDNode *N, SelectionDAG &DAG) {
5466 EVT VT = N->getValueType(0);
5473 // Is the first op an AND?
5474 const SDValue And = N->getOperand(0);
5475 if (And.getOpcode() != ISD::AND)
5478 // Is the second op an shl or lshr?
5479 SDValue Shift = N->getOperand(1);
5480 // This will have been turned into: AArch64ISD::VSHL vector, #shift
5481 // or AArch64ISD::VLSHR vector, #shift
5482 unsigned ShiftOpc = Shift.getOpcode();
5483 if ((ShiftOpc != AArch64ISD::VSHL && ShiftOpc != AArch64ISD::VLSHR))
5485 bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
5487 // Is the shift amount constant?
5488 ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
5492 // Is the and mask vector all constant?
5494 if (!isAllConstantBuildVector(And.getOperand(1), C1))
5497 // Is C1 == ~C2, taking into account how much one can shift elements of a
5499 uint64_t C2 = C2node->getZExtValue();
5500 unsigned ElemSizeInBits = VT.getVectorElementType().getSizeInBits();
5501 if (C2 > ElemSizeInBits)
5503 unsigned ElemMask = (1 << ElemSizeInBits) - 1;
5504 if ((C1 & ElemMask) != (~C2 & ElemMask))
5507 SDValue X = And.getOperand(0);
5508 SDValue Y = Shift.getOperand(0);
5511 IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
5513 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
5514 DAG.getConstant(Intrin, MVT::i32), X, Y, Shift.getOperand(1));
5516 DEBUG(dbgs() << "aarch64-lower: transformed: \n");
5517 DEBUG(N->dump(&DAG));
5518 DEBUG(dbgs() << "into: \n");
5519 DEBUG(ResultSLI->dump(&DAG));
5525 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
5526 SelectionDAG &DAG) const {
5527 // Attempt to form a vector S[LR]I from (or (and X, C1), (lsl Y, C2))
5528 if (EnableAArch64SlrGeneration) {
5529 SDValue Res = tryLowerToSLI(Op.getNode(), DAG);
5534 BuildVectorSDNode *BVN =
5535 dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode());
5536 SDValue LHS = Op.getOperand(1);
5538 EVT VT = Op.getValueType();
5540 // OR commutes, so try swapping the operands.
5542 LHS = Op.getOperand(0);
5543 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode());
5548 APInt CnstBits(VT.getSizeInBits(), 0);
5549 APInt UndefBits(VT.getSizeInBits(), 0);
5550 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5551 // We make use of a little bit of goto ickiness in order to avoid having to
5552 // duplicate the immediate matching logic for the undef toggled case.
5553 bool SecondTry = false;
5556 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5557 CnstBits = CnstBits.zextOrTrunc(64);
5558 uint64_t CnstVal = CnstBits.getZExtValue();
5560 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5561 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5562 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5563 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5564 DAG.getConstant(CnstVal, MVT::i32),
5565 DAG.getConstant(0, MVT::i32));
5566 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5569 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5570 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5571 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5572 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5573 DAG.getConstant(CnstVal, MVT::i32),
5574 DAG.getConstant(8, MVT::i32));
5575 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5578 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5579 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5580 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5581 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5582 DAG.getConstant(CnstVal, MVT::i32),
5583 DAG.getConstant(16, MVT::i32));
5584 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5587 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5588 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5589 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5590 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5591 DAG.getConstant(CnstVal, MVT::i32),
5592 DAG.getConstant(24, MVT::i32));
5593 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5596 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5597 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5598 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5599 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5600 DAG.getConstant(CnstVal, MVT::i32),
5601 DAG.getConstant(0, MVT::i32));
5602 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5605 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5606 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5607 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5608 SDValue Mov = DAG.getNode(AArch64ISD::ORRi, dl, MovTy, LHS,
5609 DAG.getConstant(CnstVal, MVT::i32),
5610 DAG.getConstant(8, MVT::i32));
5611 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5618 CnstBits = UndefBits;
5622 // We can always fall back to a non-immediate OR.
5627 // Normalize the operands of BUILD_VECTOR. The value of constant operands will
5628 // be truncated to fit element width.
5629 static SDValue NormalizeBuildVector(SDValue Op,
5630 SelectionDAG &DAG) {
5631 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5633 EVT VT = Op.getValueType();
5634 EVT EltTy= VT.getVectorElementType();
5636 if (EltTy.isFloatingPoint() || EltTy.getSizeInBits() > 16)
5639 SmallVector<SDValue, 16> Ops;
5640 for (unsigned I = 0, E = VT.getVectorNumElements(); I != E; ++I) {
5641 SDValue Lane = Op.getOperand(I);
5642 if (Lane.getOpcode() == ISD::Constant) {
5643 APInt LowBits(EltTy.getSizeInBits(),
5644 cast<ConstantSDNode>(Lane)->getZExtValue());
5645 Lane = DAG.getConstant(LowBits.getZExtValue(), MVT::i32);
5647 Ops.push_back(Lane);
5649 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5652 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
5653 SelectionDAG &DAG) const {
5655 EVT VT = Op.getValueType();
5656 Op = NormalizeBuildVector(Op, DAG);
5657 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5659 APInt CnstBits(VT.getSizeInBits(), 0);
5660 APInt UndefBits(VT.getSizeInBits(), 0);
5661 if (resolveBuildVector(BVN, CnstBits, UndefBits)) {
5662 // We make use of a little bit of goto ickiness in order to avoid having to
5663 // duplicate the immediate matching logic for the undef toggled case.
5664 bool SecondTry = false;
5667 if (CnstBits.getHiBits(64) == CnstBits.getLoBits(64)) {
5668 CnstBits = CnstBits.zextOrTrunc(64);
5669 uint64_t CnstVal = CnstBits.getZExtValue();
5671 // Certain magic vector constants (used to express things like NOT
5672 // and NEG) are passed through unmodified. This allows codegen patterns
5673 // for these operations to match. Special-purpose patterns will lower
5674 // these immediates to MOVIs if it proves necessary.
5675 if (VT.isInteger() && (CnstVal == 0 || CnstVal == ~0ULL))
5678 // The many faces of MOVI...
5679 if (AArch64_AM::isAdvSIMDModImmType10(CnstVal)) {
5680 CnstVal = AArch64_AM::encodeAdvSIMDModImmType10(CnstVal);
5681 if (VT.getSizeInBits() == 128) {
5682 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::v2i64,
5683 DAG.getConstant(CnstVal, MVT::i32));
5684 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5687 // Support the V64 version via subregister insertion.
5688 SDValue Mov = DAG.getNode(AArch64ISD::MOVIedit, dl, MVT::f64,
5689 DAG.getConstant(CnstVal, MVT::i32));
5690 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5693 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5694 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5695 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5696 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5697 DAG.getConstant(CnstVal, MVT::i32),
5698 DAG.getConstant(0, MVT::i32));
5699 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5702 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5703 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5704 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5705 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5706 DAG.getConstant(CnstVal, MVT::i32),
5707 DAG.getConstant(8, MVT::i32));
5708 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5711 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5712 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5713 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5714 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5715 DAG.getConstant(CnstVal, MVT::i32),
5716 DAG.getConstant(16, MVT::i32));
5717 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5720 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5721 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5722 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5723 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5724 DAG.getConstant(CnstVal, MVT::i32),
5725 DAG.getConstant(24, MVT::i32));
5726 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5729 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5730 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5731 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5732 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5733 DAG.getConstant(CnstVal, MVT::i32),
5734 DAG.getConstant(0, MVT::i32));
5735 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5738 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5739 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5740 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5741 SDValue Mov = DAG.getNode(AArch64ISD::MOVIshift, dl, MovTy,
5742 DAG.getConstant(CnstVal, MVT::i32),
5743 DAG.getConstant(8, MVT::i32));
5744 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5747 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5748 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5749 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5750 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5751 DAG.getConstant(CnstVal, MVT::i32),
5752 DAG.getConstant(264, MVT::i32));
5753 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5756 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5757 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5758 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5759 SDValue Mov = DAG.getNode(AArch64ISD::MOVImsl, dl, MovTy,
5760 DAG.getConstant(CnstVal, MVT::i32),
5761 DAG.getConstant(272, MVT::i32));
5762 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5765 if (AArch64_AM::isAdvSIMDModImmType9(CnstVal)) {
5766 CnstVal = AArch64_AM::encodeAdvSIMDModImmType9(CnstVal);
5767 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v16i8 : MVT::v8i8;
5768 SDValue Mov = DAG.getNode(AArch64ISD::MOVI, dl, MovTy,
5769 DAG.getConstant(CnstVal, MVT::i32));
5770 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5773 // The few faces of FMOV...
5774 if (AArch64_AM::isAdvSIMDModImmType11(CnstVal)) {
5775 CnstVal = AArch64_AM::encodeAdvSIMDModImmType11(CnstVal);
5776 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4f32 : MVT::v2f32;
5777 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MovTy,
5778 DAG.getConstant(CnstVal, MVT::i32));
5779 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5782 if (AArch64_AM::isAdvSIMDModImmType12(CnstVal) &&
5783 VT.getSizeInBits() == 128) {
5784 CnstVal = AArch64_AM::encodeAdvSIMDModImmType12(CnstVal);
5785 SDValue Mov = DAG.getNode(AArch64ISD::FMOV, dl, MVT::v2f64,
5786 DAG.getConstant(CnstVal, MVT::i32));
5787 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5790 // The many faces of MVNI...
5792 if (AArch64_AM::isAdvSIMDModImmType1(CnstVal)) {
5793 CnstVal = AArch64_AM::encodeAdvSIMDModImmType1(CnstVal);
5794 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5795 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5796 DAG.getConstant(CnstVal, MVT::i32),
5797 DAG.getConstant(0, MVT::i32));
5798 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5801 if (AArch64_AM::isAdvSIMDModImmType2(CnstVal)) {
5802 CnstVal = AArch64_AM::encodeAdvSIMDModImmType2(CnstVal);
5803 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5804 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5805 DAG.getConstant(CnstVal, MVT::i32),
5806 DAG.getConstant(8, MVT::i32));
5807 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5810 if (AArch64_AM::isAdvSIMDModImmType3(CnstVal)) {
5811 CnstVal = AArch64_AM::encodeAdvSIMDModImmType3(CnstVal);
5812 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5813 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5814 DAG.getConstant(CnstVal, MVT::i32),
5815 DAG.getConstant(16, MVT::i32));
5816 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5819 if (AArch64_AM::isAdvSIMDModImmType4(CnstVal)) {
5820 CnstVal = AArch64_AM::encodeAdvSIMDModImmType4(CnstVal);
5821 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5822 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5823 DAG.getConstant(CnstVal, MVT::i32),
5824 DAG.getConstant(24, MVT::i32));
5825 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5828 if (AArch64_AM::isAdvSIMDModImmType5(CnstVal)) {
5829 CnstVal = AArch64_AM::encodeAdvSIMDModImmType5(CnstVal);
5830 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5831 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5832 DAG.getConstant(CnstVal, MVT::i32),
5833 DAG.getConstant(0, MVT::i32));
5834 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5837 if (AArch64_AM::isAdvSIMDModImmType6(CnstVal)) {
5838 CnstVal = AArch64_AM::encodeAdvSIMDModImmType6(CnstVal);
5839 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16;
5840 SDValue Mov = DAG.getNode(AArch64ISD::MVNIshift, dl, MovTy,
5841 DAG.getConstant(CnstVal, MVT::i32),
5842 DAG.getConstant(8, MVT::i32));
5843 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5846 if (AArch64_AM::isAdvSIMDModImmType7(CnstVal)) {
5847 CnstVal = AArch64_AM::encodeAdvSIMDModImmType7(CnstVal);
5848 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5849 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5850 DAG.getConstant(CnstVal, MVT::i32),
5851 DAG.getConstant(264, MVT::i32));
5852 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5855 if (AArch64_AM::isAdvSIMDModImmType8(CnstVal)) {
5856 CnstVal = AArch64_AM::encodeAdvSIMDModImmType8(CnstVal);
5857 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v4i32 : MVT::v2i32;
5858 SDValue Mov = DAG.getNode(AArch64ISD::MVNImsl, dl, MovTy,
5859 DAG.getConstant(CnstVal, MVT::i32),
5860 DAG.getConstant(272, MVT::i32));
5861 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov);
5868 CnstBits = UndefBits;
5873 // Scan through the operands to find some interesting properties we can
5875 // 1) If only one value is used, we can use a DUP, or
5876 // 2) if only the low element is not undef, we can just insert that, or
5877 // 3) if only one constant value is used (w/ some non-constant lanes),
5878 // we can splat the constant value into the whole vector then fill
5879 // in the non-constant lanes.
5880 // 4) FIXME: If different constant values are used, but we can intelligently
5881 // select the values we'll be overwriting for the non-constant
5882 // lanes such that we can directly materialize the vector
5883 // some other way (MOVI, e.g.), we can be sneaky.
5884 unsigned NumElts = VT.getVectorNumElements();
5885 bool isOnlyLowElement = true;
5886 bool usesOnlyOneValue = true;
5887 bool usesOnlyOneConstantValue = true;
5888 bool isConstant = true;
5889 unsigned NumConstantLanes = 0;
5891 SDValue ConstantValue;
5892 for (unsigned i = 0; i < NumElts; ++i) {
5893 SDValue V = Op.getOperand(i);
5894 if (V.getOpcode() == ISD::UNDEF)
5897 isOnlyLowElement = false;
5898 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5901 if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
5903 if (!ConstantValue.getNode())
5905 else if (ConstantValue != V)
5906 usesOnlyOneConstantValue = false;
5909 if (!Value.getNode())
5911 else if (V != Value)
5912 usesOnlyOneValue = false;
5915 if (!Value.getNode())
5916 return DAG.getUNDEF(VT);
5918 if (isOnlyLowElement)
5919 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5921 // Use DUP for non-constant splats. For f32 constant splats, reduce to
5922 // i32 and try again.
5923 if (usesOnlyOneValue) {
5925 if (Value.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5926 Value.getValueType() != VT)
5927 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value);
5929 // This is actually a DUPLANExx operation, which keeps everything vectory.
5931 // DUPLANE works on 128-bit vectors, widen it if necessary.
5932 SDValue Lane = Value.getOperand(1);
5933 Value = Value.getOperand(0);
5934 if (Value.getValueType().getSizeInBits() == 64)
5935 Value = WidenVector(Value, DAG);
5937 unsigned Opcode = getDUPLANEOp(VT.getVectorElementType());
5938 return DAG.getNode(Opcode, dl, VT, Value, Lane);
5941 if (VT.getVectorElementType().isFloatingPoint()) {
5942 SmallVector<SDValue, 8> Ops;
5944 (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
5945 for (unsigned i = 0; i < NumElts; ++i)
5946 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));
5947 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), NewType, NumElts);
5948 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5949 Val = LowerBUILD_VECTOR(Val, DAG);
5951 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5955 // If there was only one constant value used and for more than one lane,
5956 // start by splatting that value, then replace the non-constant lanes. This
5957 // is better than the default, which will perform a separate initialization
5959 if (NumConstantLanes > 0 && usesOnlyOneConstantValue) {
5960 SDValue Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue);
5961 // Now insert the non-constant lanes.
5962 for (unsigned i = 0; i < NumElts; ++i) {
5963 SDValue V = Op.getOperand(i);
5964 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
5965 if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
5966 // Note that type legalization likely mucked about with the VT of the
5967 // source operand, so we may have to convert it here before inserting.
5968 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
5974 // If all elements are constants and the case above didn't get hit, fall back
5975 // to the default expansion, which will generate a load from the constant
5980 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5982 SDValue shuffle = ReconstructShuffle(Op, DAG);
5983 if (shuffle != SDValue())
5987 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5988 // know the default expansion would otherwise fall back on something even
5989 // worse. For a vector with one or two non-undef values, that's
5990 // scalar_to_vector for the elements followed by a shuffle (provided the
5991 // shuffle is valid for the target) and materialization element by element
5992 // on the stack followed by a load for everything else.
5993 if (!isConstant && !usesOnlyOneValue) {
5994 SDValue Vec = DAG.getUNDEF(VT);
5995 SDValue Op0 = Op.getOperand(0);
5996 unsigned ElemSize = VT.getVectorElementType().getSizeInBits();
5998 // For 32 and 64 bit types, use INSERT_SUBREG for lane zero to
5999 // a) Avoid a RMW dependency on the full vector register, and
6000 // b) Allow the register coalescer to fold away the copy if the
6001 // value is already in an S or D register.
6002 if (Op0.getOpcode() != ISD::UNDEF && (ElemSize == 32 || ElemSize == 64)) {
6003 unsigned SubIdx = ElemSize == 32 ? AArch64::ssub : AArch64::dsub;
6005 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, VT, Vec, Op0,
6006 DAG.getTargetConstant(SubIdx, MVT::i32));
6007 Vec = SDValue(N, 0);
6010 for (; i < NumElts; ++i) {
6011 SDValue V = Op.getOperand(i);
6012 if (V.getOpcode() == ISD::UNDEF)
6014 SDValue LaneIdx = DAG.getConstant(i, MVT::i64);
6015 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
6020 // Just use the default expansion. We failed to find a better alternative.
6024 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
6025 SelectionDAG &DAG) const {
6026 assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT && "Unknown opcode!");
6028 // Check for non-constant or out of range lane.
6029 EVT VT = Op.getOperand(0).getValueType();
6030 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
6031 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6035 // Insertion/extraction are legal for V128 types.
6036 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6037 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6041 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6042 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6045 // For V64 types, we perform insertion by expanding the value
6046 // to a V128 type and perform the insertion on that.
6048 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6049 EVT WideTy = WideVec.getValueType();
6051 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec,
6052 Op.getOperand(1), Op.getOperand(2));
6053 // Re-narrow the resultant vector.
6054 return NarrowVector(Node, DAG);
6058 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6059 SelectionDAG &DAG) const {
6060 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!");
6062 // Check for non-constant or out of range lane.
6063 EVT VT = Op.getOperand(0).getValueType();
6064 ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6065 if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
6069 // Insertion/extraction are legal for V128 types.
6070 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 ||
6071 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64 ||
6075 if (VT != MVT::v8i8 && VT != MVT::v4i16 && VT != MVT::v2i32 &&
6076 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16)
6079 // For V64 types, we perform extraction by expanding the value
6080 // to a V128 type and perform the extraction on that.
6082 SDValue WideVec = WidenVector(Op.getOperand(0), DAG);
6083 EVT WideTy = WideVec.getValueType();
6085 EVT ExtrTy = WideTy.getVectorElementType();
6086 if (ExtrTy == MVT::i16 || ExtrTy == MVT::i8)
6089 // For extractions, we just return the result directly.
6090 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec,
6094 SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
6095 SelectionDAG &DAG) const {
6096 EVT VT = Op.getOperand(0).getValueType();
6102 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
6105 unsigned Val = Cst->getZExtValue();
6107 unsigned Size = Op.getValueType().getSizeInBits();
6111 return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
6114 return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
6117 return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
6120 return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
6123 llvm_unreachable("Unexpected vector type in extract_subvector!");
6126 // If this is extracting the upper 64-bits of a 128-bit vector, we match
6128 if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)
6134 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
6136 if (VT.getVectorNumElements() == 4 &&
6137 (VT.is128BitVector() || VT.is64BitVector())) {
6138 unsigned PFIndexes[4];
6139 for (unsigned i = 0; i != 4; ++i) {
6143 PFIndexes[i] = M[i];
6146 // Compute the index in the perfect shuffle table.
6147 unsigned PFTableIndex = PFIndexes[0] * 9 * 9 * 9 + PFIndexes[1] * 9 * 9 +
6148 PFIndexes[2] * 9 + PFIndexes[3];
6149 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6150 unsigned Cost = (PFEntry >> 30);
6158 unsigned DummyUnsigned;
6160 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) || isREVMask(M, VT, 64) ||
6161 isREVMask(M, VT, 32) || isREVMask(M, VT, 16) ||
6162 isEXTMask(M, VT, DummyBool, DummyUnsigned) ||
6163 // isTBLMask(M, VT) || // FIXME: Port TBL support from ARM.
6164 isTRNMask(M, VT, DummyUnsigned) || isUZPMask(M, VT, DummyUnsigned) ||
6165 isZIPMask(M, VT, DummyUnsigned) ||
6166 isTRN_v_undef_Mask(M, VT, DummyUnsigned) ||
6167 isUZP_v_undef_Mask(M, VT, DummyUnsigned) ||
6168 isZIP_v_undef_Mask(M, VT, DummyUnsigned) ||
6169 isINSMask(M, VT.getVectorNumElements(), DummyBool, DummyInt) ||
6170 isConcatMask(M, VT, VT.getSizeInBits() == 128));
6173 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6174 /// operand of a vector shift operation, where all the elements of the
6175 /// build_vector must have the same constant integer value.
6176 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6177 // Ignore bit_converts.
6178 while (Op.getOpcode() == ISD::BITCAST)
6179 Op = Op.getOperand(0);
6180 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6181 APInt SplatBits, SplatUndef;
6182 unsigned SplatBitSize;
6184 if (!BVN || !BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6185 HasAnyUndefs, ElementBits) ||
6186 SplatBitSize > ElementBits)
6188 Cnt = SplatBits.getSExtValue();
6192 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6193 /// operand of a vector shift left operation. That value must be in the range:
6194 /// 0 <= Value < ElementBits for a left shift; or
6195 /// 0 <= Value <= ElementBits for a long left shift.
6196 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6197 assert(VT.isVector() && "vector shift count is not a vector type");
6198 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6199 if (!getVShiftImm(Op, ElementBits, Cnt))
6201 return (Cnt >= 0 && (isLong ? Cnt - 1 : Cnt) < ElementBits);
6204 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6205 /// operand of a vector shift right operation. For a shift opcode, the value
6206 /// is positive, but for an intrinsic the value count must be negative. The
6207 /// absolute value must be in the range:
6208 /// 1 <= |Value| <= ElementBits for a right shift; or
6209 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
6210 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
6212 assert(VT.isVector() && "vector shift count is not a vector type");
6213 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6214 if (!getVShiftImm(Op, ElementBits, Cnt))
6218 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
6221 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
6222 SelectionDAG &DAG) const {
6223 EVT VT = Op.getValueType();
6227 if (!Op.getOperand(1).getValueType().isVector())
6229 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6231 switch (Op.getOpcode()) {
6233 llvm_unreachable("unexpected shift opcode");
6236 if (isVShiftLImm(Op.getOperand(1), VT, false, Cnt) && Cnt < EltSize)
6237 return DAG.getNode(AArch64ISD::VSHL, SDLoc(Op), VT, Op.getOperand(0),
6238 DAG.getConstant(Cnt, MVT::i32));
6239 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6240 DAG.getConstant(Intrinsic::aarch64_neon_ushl, MVT::i32),
6241 Op.getOperand(0), Op.getOperand(1));
6244 // Right shift immediate
6245 if (isVShiftRImm(Op.getOperand(1), VT, false, false, Cnt) &&
6248 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR;
6249 return DAG.getNode(Opc, SDLoc(Op), VT, Op.getOperand(0),
6250 DAG.getConstant(Cnt, MVT::i32));
6253 // Right shift register. Note, there is not a shift right register
6254 // instruction, but the shift left register instruction takes a signed
6255 // value, where negative numbers specify a right shift.
6256 unsigned Opc = (Op.getOpcode() == ISD::SRA) ? Intrinsic::aarch64_neon_sshl
6257 : Intrinsic::aarch64_neon_ushl;
6258 // negate the shift amount
6259 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1));
6260 SDValue NegShiftLeft =
6261 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
6262 DAG.getConstant(Opc, MVT::i32), Op.getOperand(0), NegShift);
6263 return NegShiftLeft;
6269 static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
6270 AArch64CC::CondCode CC, bool NoNans, EVT VT,
6271 SDLoc dl, SelectionDAG &DAG) {
6272 EVT SrcVT = LHS.getValueType();
6274 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode());
6275 APInt CnstBits(VT.getSizeInBits(), 0);
6276 APInt UndefBits(VT.getSizeInBits(), 0);
6277 bool IsCnst = BVN && resolveBuildVector(BVN, CnstBits, UndefBits);
6278 bool IsZero = IsCnst && (CnstBits == 0);
6280 if (SrcVT.getVectorElementType().isFloatingPoint()) {
6284 case AArch64CC::NE: {
6287 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6289 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6290 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq);
6294 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS);
6295 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS);
6298 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS);
6299 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS);
6302 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS);
6303 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS);
6306 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS);
6307 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS);
6311 // If we ignore NaNs then we can use to the MI implementation.
6315 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS);
6316 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS);
6323 case AArch64CC::NE: {
6326 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6328 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6329 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq);
6333 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS);
6334 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS);
6337 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS);
6338 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS);
6341 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS);
6342 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS);
6345 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS);
6346 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS);
6348 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS);
6350 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS);
6353 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS);
6354 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS);
6356 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS);
6358 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS);
6362 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6363 SelectionDAG &DAG) const {
6364 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
6365 SDValue LHS = Op.getOperand(0);
6366 SDValue RHS = Op.getOperand(1);
6369 if (LHS.getValueType().getVectorElementType().isInteger()) {
6370 assert(LHS.getValueType() == RHS.getValueType());
6371 AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
6372 return EmitVectorComparison(LHS, RHS, AArch64CC, false, Op.getValueType(),
6376 assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
6377 LHS.getValueType().getVectorElementType() == MVT::f64);
6379 // Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
6380 // clean. Some of them require two branches to implement.
6381 AArch64CC::CondCode CC1, CC2;
6383 changeVectorFPCCToAArch64CC(CC, CC1, CC2, ShouldInvert);
6385 bool NoNaNs = getTargetMachine().Options.NoNaNsFPMath;
6387 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, Op.getValueType(), dl, DAG);
6391 if (CC2 != AArch64CC::AL) {
6393 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, Op.getValueType(), dl, DAG);
6394 if (!Cmp2.getNode())
6397 Cmp = DAG.getNode(ISD::OR, dl, Cmp.getValueType(), Cmp, Cmp2);
6401 return Cmp = DAG.getNOT(dl, Cmp, Cmp.getValueType());
6406 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6407 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6408 /// specified in the intrinsic calls.
6409 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6411 unsigned Intrinsic) const {
6412 switch (Intrinsic) {
6413 case Intrinsic::aarch64_neon_ld2:
6414 case Intrinsic::aarch64_neon_ld3:
6415 case Intrinsic::aarch64_neon_ld4:
6416 case Intrinsic::aarch64_neon_ld1x2:
6417 case Intrinsic::aarch64_neon_ld1x3:
6418 case Intrinsic::aarch64_neon_ld1x4:
6419 case Intrinsic::aarch64_neon_ld2lane:
6420 case Intrinsic::aarch64_neon_ld3lane:
6421 case Intrinsic::aarch64_neon_ld4lane:
6422 case Intrinsic::aarch64_neon_ld2r:
6423 case Intrinsic::aarch64_neon_ld3r:
6424 case Intrinsic::aarch64_neon_ld4r: {
6425 Info.opc = ISD::INTRINSIC_W_CHAIN;
6426 // Conservatively set memVT to the entire set of vectors loaded.
6427 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
6428 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6429 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6432 Info.vol = false; // volatile loads with NEON intrinsics not supported
6433 Info.readMem = true;
6434 Info.writeMem = false;
6437 case Intrinsic::aarch64_neon_st2:
6438 case Intrinsic::aarch64_neon_st3:
6439 case Intrinsic::aarch64_neon_st4:
6440 case Intrinsic::aarch64_neon_st1x2:
6441 case Intrinsic::aarch64_neon_st1x3:
6442 case Intrinsic::aarch64_neon_st1x4:
6443 case Intrinsic::aarch64_neon_st2lane:
6444 case Intrinsic::aarch64_neon_st3lane:
6445 case Intrinsic::aarch64_neon_st4lane: {
6446 Info.opc = ISD::INTRINSIC_VOID;
6447 // Conservatively set memVT to the entire set of vectors stored.
6448 unsigned NumElts = 0;
6449 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6450 Type *ArgTy = I.getArgOperand(ArgI)->getType();
6451 if (!ArgTy->isVectorTy())
6453 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
6455 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6456 Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
6459 Info.vol = false; // volatile stores with NEON intrinsics not supported
6460 Info.readMem = false;
6461 Info.writeMem = true;
6464 case Intrinsic::aarch64_ldaxr:
6465 case Intrinsic::aarch64_ldxr: {
6466 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
6467 Info.opc = ISD::INTRINSIC_W_CHAIN;
6468 Info.memVT = MVT::getVT(PtrTy->getElementType());
6469 Info.ptrVal = I.getArgOperand(0);
6471 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6473 Info.readMem = true;
6474 Info.writeMem = false;
6477 case Intrinsic::aarch64_stlxr:
6478 case Intrinsic::aarch64_stxr: {
6479 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
6480 Info.opc = ISD::INTRINSIC_W_CHAIN;
6481 Info.memVT = MVT::getVT(PtrTy->getElementType());
6482 Info.ptrVal = I.getArgOperand(1);
6484 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
6486 Info.readMem = false;
6487 Info.writeMem = true;
6490 case Intrinsic::aarch64_ldaxp:
6491 case Intrinsic::aarch64_ldxp: {
6492 Info.opc = ISD::INTRINSIC_W_CHAIN;
6493 Info.memVT = MVT::i128;
6494 Info.ptrVal = I.getArgOperand(0);
6498 Info.readMem = true;
6499 Info.writeMem = false;
6502 case Intrinsic::aarch64_stlxp:
6503 case Intrinsic::aarch64_stxp: {
6504 Info.opc = ISD::INTRINSIC_W_CHAIN;
6505 Info.memVT = MVT::i128;
6506 Info.ptrVal = I.getArgOperand(2);
6510 Info.readMem = false;
6511 Info.writeMem = true;
6521 // Truncations from 64-bit GPR to 32-bit GPR is free.
6522 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6523 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6525 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6526 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6527 return NumBits1 > NumBits2;
6529 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6530 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6532 unsigned NumBits1 = VT1.getSizeInBits();
6533 unsigned NumBits2 = VT2.getSizeInBits();
6534 return NumBits1 > NumBits2;
6537 // All 32-bit GPR operations implicitly zero the high-half of the corresponding
6539 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6540 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
6542 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6543 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6544 return NumBits1 == 32 && NumBits2 == 64;
6546 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6547 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger())
6549 unsigned NumBits1 = VT1.getSizeInBits();
6550 unsigned NumBits2 = VT2.getSizeInBits();
6551 return NumBits1 == 32 && NumBits2 == 64;
6554 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
6555 EVT VT1 = Val.getValueType();
6556 if (isZExtFree(VT1, VT2)) {
6560 if (Val.getOpcode() != ISD::LOAD)
6563 // 8-, 16-, and 32-bit integer loads all implicitly zero-extend.
6564 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() &&
6565 VT2.isSimple() && !VT2.isVector() && VT2.isInteger() &&
6566 VT1.getSizeInBits() <= 32);
6569 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
6570 unsigned &RequiredAligment) const {
6571 if (!LoadedType->isIntegerTy() && !LoadedType->isFloatTy())
6573 // Cyclone supports unaligned accesses.
6574 RequiredAligment = 0;
6575 unsigned NumBits = LoadedType->getPrimitiveSizeInBits();
6576 return NumBits == 32 || NumBits == 64;
6579 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
6580 unsigned &RequiredAligment) const {
6581 if (!LoadedType.isSimple() ||
6582 (!LoadedType.isInteger() && !LoadedType.isFloatingPoint()))
6584 // Cyclone supports unaligned accesses.
6585 RequiredAligment = 0;
6586 unsigned NumBits = LoadedType.getSizeInBits();
6587 return NumBits == 32 || NumBits == 64;
6590 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
6591 unsigned AlignCheck) {
6592 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
6593 (DstAlign == 0 || DstAlign % AlignCheck == 0));
6596 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
6597 unsigned SrcAlign, bool IsMemset,
6600 MachineFunction &MF) const {
6601 // Don't use AdvSIMD to implement 16-byte memset. It would have taken one
6602 // instruction to materialize the v2i64 zero and one store (with restrictive
6603 // addressing mode). Just do two i64 store of zero-registers.
6605 const Function *F = MF.getFunction();
6606 if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
6607 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
6608 Attribute::NoImplicitFloat) &&
6609 (memOpAlign(SrcAlign, DstAlign, 16) ||
6610 (allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
6613 return Size >= 8 ? MVT::i64 : MVT::i32;
6616 // 12-bit optionally shifted immediates are legal for adds.
6617 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
6618 if ((Immed >> 12) == 0 || ((Immed & 0xfff) == 0 && Immed >> 24 == 0))
6623 // Integer comparisons are implemented with ADDS/SUBS, so the range of valid
6624 // immediates is the same as for an add or a sub.
6625 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
6628 return isLegalAddImmediate(Immed);
6631 /// isLegalAddressingMode - Return true if the addressing mode represented
6632 /// by AM is legal for this target, for a load/store of the specified type.
6633 bool AArch64TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6635 // AArch64 has five basic addressing modes:
6637 // reg + 9-bit signed offset
6638 // reg + SIZE_IN_BYTES * 12-bit unsigned offset
6640 // reg + SIZE_IN_BYTES * reg
6642 // No global is ever allowed as a base.
6646 // No reg+reg+imm addressing.
6647 if (AM.HasBaseReg && AM.BaseOffs && AM.Scale)
6650 // check reg + imm case:
6651 // i.e., reg + 0, reg + imm9, reg + SIZE_IN_BYTES * uimm12
6652 uint64_t NumBytes = 0;
6653 if (Ty->isSized()) {
6654 uint64_t NumBits = getDataLayout()->getTypeSizeInBits(Ty);
6655 NumBytes = NumBits / 8;
6656 if (!isPowerOf2_64(NumBits))
6661 int64_t Offset = AM.BaseOffs;
6663 // 9-bit signed offset
6664 if (Offset >= -(1LL << 9) && Offset <= (1LL << 9) - 1)
6667 // 12-bit unsigned offset
6668 unsigned shift = Log2_64(NumBytes);
6669 if (NumBytes && Offset > 0 && (Offset / NumBytes) <= (1LL << 12) - 1 &&
6670 // Must be a multiple of NumBytes (NumBytes is a power of 2)
6671 (Offset >> shift) << shift == Offset)
6676 // Check reg1 + SIZE_IN_BYTES * reg2 and reg1 + reg2
6678 if (!AM.Scale || AM.Scale == 1 ||
6679 (AM.Scale > 0 && (uint64_t)AM.Scale == NumBytes))
6684 int AArch64TargetLowering::getScalingFactorCost(const AddrMode &AM,
6686 // Scaling factors are not free at all.
6687 // Operands | Rt Latency
6688 // -------------------------------------------
6690 // -------------------------------------------
6691 // Rt, [Xn, Xm, lsl #imm] | Rn: 4 Rm: 5
6692 // Rt, [Xn, Wm, <extend> #imm] |
6693 if (isLegalAddressingMode(AM, Ty))
6694 // Scale represents reg2 * scale, thus account for 1 if
6695 // it is not equal to 0 or 1.
6696 return AM.Scale != 0 && AM.Scale != 1;
6700 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
6701 VT = VT.getScalarType();
6706 switch (VT.getSimpleVT().SimpleTy) {
6718 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
6719 // LR is a callee-save register, but we must treat it as clobbered by any call
6720 // site. Hence we include LR in the scratch registers, which are in turn added
6721 // as implicit-defs for stackmaps and patchpoints.
6722 static const MCPhysReg ScratchRegs[] = {
6723 AArch64::X16, AArch64::X17, AArch64::LR, 0
6729 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
6730 EVT VT = N->getValueType(0);
6731 // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
6732 // it with shift to let it be lowered to UBFX.
6733 if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
6734 isa<ConstantSDNode>(N->getOperand(1))) {
6735 uint64_t TruncMask = N->getConstantOperandVal(1);
6736 if (isMask_64(TruncMask) &&
6737 N->getOperand(0).getOpcode() == ISD::SRL &&
6738 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
6744 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
6746 assert(Ty->isIntegerTy());
6748 unsigned BitSize = Ty->getPrimitiveSizeInBits();
6752 int64_t Val = Imm.getSExtValue();
6753 if (Val == 0 || AArch64_AM::isLogicalImmediate(Val, BitSize))
6756 if ((int64_t)Val < 0)
6759 Val &= (1LL << 32) - 1;
6761 unsigned LZ = countLeadingZeros((uint64_t)Val);
6762 unsigned Shift = (63 - LZ) / 16;
6763 // MOVZ is free so return true for one or fewer MOVK.
6764 return (Shift < 3) ? true : false;
6767 // Generate SUBS and CSEL for integer abs.
6768 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
6769 EVT VT = N->getValueType(0);
6771 SDValue N0 = N->getOperand(0);
6772 SDValue N1 = N->getOperand(1);
6775 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
6776 // and change it to SUB and CSEL.
6777 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
6778 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
6779 N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
6780 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
6781 if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
6782 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
6784 // Generate SUBS & CSEL.
6786 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32),
6787 N0.getOperand(0), DAG.getConstant(0, VT));
6788 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
6789 DAG.getConstant(AArch64CC::PL, MVT::i32),
6790 SDValue(Cmp.getNode(), 1));
6795 // performXorCombine - Attempts to handle integer ABS.
6796 static SDValue performXorCombine(SDNode *N, SelectionDAG &DAG,
6797 TargetLowering::DAGCombinerInfo &DCI,
6798 const AArch64Subtarget *Subtarget) {
6799 if (DCI.isBeforeLegalizeOps())
6802 return performIntegerAbsCombine(N, DAG);
6806 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
6808 std::vector<SDNode *> *Created) const {
6809 // fold (sdiv X, pow2)
6810 EVT VT = N->getValueType(0);
6811 if ((VT != MVT::i32 && VT != MVT::i64) ||
6812 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
6816 SDValue N0 = N->getOperand(0);
6817 unsigned Lg2 = Divisor.countTrailingZeros();
6818 SDValue Zero = DAG.getConstant(0, VT);
6819 SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, VT);
6821 // Add (N0 < 0) ? Pow2 - 1 : 0;
6823 SDValue Cmp = getAArch64Cmp(N0, Zero, ISD::SETLT, CCVal, DAG, DL);
6824 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
6825 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
6828 Created->push_back(Cmp.getNode());
6829 Created->push_back(Add.getNode());
6830 Created->push_back(CSel.getNode());
6835 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, MVT::i64));
6837 // If we're dividing by a positive value, we're done. Otherwise, we must
6838 // negate the result.
6839 if (Divisor.isNonNegative())
6843 Created->push_back(SRA.getNode());
6844 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), SRA);
6847 static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
6848 TargetLowering::DAGCombinerInfo &DCI,
6849 const AArch64Subtarget *Subtarget) {
6850 if (DCI.isBeforeLegalizeOps())
6853 // Multiplication of a power of two plus/minus one can be done more
6854 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
6855 // future CPUs have a cheaper MADD instruction, this may need to be
6856 // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
6857 // 64-bit is 5 cycles, so this is always a win.
6858 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
6859 APInt Value = C->getAPIntValue();
6860 EVT VT = N->getValueType(0);
6861 if (Value.isNonNegative()) {
6862 // (mul x, 2^N + 1) => (add (shl x, N), x)
6863 APInt VM1 = Value - 1;
6864 if (VM1.isPowerOf2()) {
6865 SDValue ShiftedVal =
6866 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6867 DAG.getConstant(VM1.logBase2(), MVT::i64));
6868 return DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal,
6871 // (mul x, 2^N - 1) => (sub (shl x, N), x)
6872 APInt VP1 = Value + 1;
6873 if (VP1.isPowerOf2()) {
6874 SDValue ShiftedVal =
6875 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6876 DAG.getConstant(VP1.logBase2(), MVT::i64));
6877 return DAG.getNode(ISD::SUB, SDLoc(N), VT, ShiftedVal,
6881 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
6882 APInt VNM1 = -Value - 1;
6883 if (VNM1.isPowerOf2()) {
6884 SDValue ShiftedVal =
6885 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6886 DAG.getConstant(VNM1.logBase2(), MVT::i64));
6888 DAG.getNode(ISD::ADD, SDLoc(N), VT, ShiftedVal, N->getOperand(0));
6889 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), Add);
6891 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
6892 APInt VNP1 = -Value + 1;
6893 if (VNP1.isPowerOf2()) {
6894 SDValue ShiftedVal =
6895 DAG.getNode(ISD::SHL, SDLoc(N), VT, N->getOperand(0),
6896 DAG.getConstant(VNP1.logBase2(), MVT::i64));
6897 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N->getOperand(0),
6905 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
6906 SelectionDAG &DAG) {
6907 // Take advantage of vector comparisons producing 0 or -1 in each lane to
6908 // optimize away operation when it's from a constant.
6910 // The general transformation is:
6911 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
6912 // AND(VECTOR_CMP(x,y), constant2)
6913 // constant2 = UNARYOP(constant)
6915 // Early exit if this isn't a vector operation, the operand of the
6916 // unary operation isn't a bitwise AND, or if the sizes of the operations
6918 EVT VT = N->getValueType(0);
6919 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
6920 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
6921 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
6924 // Now check that the other operand of the AND is a constant. We could
6925 // make the transformation for non-constant splats as well, but it's unclear
6926 // that would be a benefit as it would not eliminate any operations, just
6927 // perform one more step in scalar code before moving to the vector unit.
6928 if (BuildVectorSDNode *BV =
6929 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
6930 // Bail out if the vector isn't a constant.
6931 if (!BV->isConstant())
6934 // Everything checks out. Build up the new and improved node.
6936 EVT IntVT = BV->getValueType(0);
6937 // Create a new constant of the appropriate type for the transformed
6939 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
6940 // The AND node needs bitcasts to/from an integer vector type around it.
6941 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
6942 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
6943 N->getOperand(0)->getOperand(0), MaskConst);
6944 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
6951 static SDValue performIntToFpCombine(SDNode *N, SelectionDAG &DAG) {
6952 // First try to optimize away the conversion when it's conditionally from
6953 // a constant. Vectors only.
6954 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
6955 if (Res != SDValue())
6958 EVT VT = N->getValueType(0);
6959 if (VT != MVT::f32 && VT != MVT::f64)
6962 // Only optimize when the source and destination types have the same width.
6963 if (VT.getSizeInBits() != N->getOperand(0).getValueType().getSizeInBits())
6966 // If the result of an integer load is only used by an integer-to-float
6967 // conversion, use a fp load instead and a AdvSIMD scalar {S|U}CVTF instead.
6968 // This eliminates an "integer-to-vector-move UOP and improve throughput.
6969 SDValue N0 = N->getOperand(0);
6970 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6971 // Do not change the width of a volatile load.
6972 !cast<LoadSDNode>(N0)->isVolatile()) {
6973 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6974 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), LN0->getBasePtr(),
6975 LN0->getPointerInfo(), LN0->isVolatile(),
6976 LN0->isNonTemporal(), LN0->isInvariant(),
6977 LN0->getAlignment());
6979 // Make sure successors of the original load stay after it by updating them
6980 // to use the new Chain.
6981 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), Load.getValue(1));
6984 (N->getOpcode() == ISD::SINT_TO_FP) ? AArch64ISD::SITOF : AArch64ISD::UITOF;
6985 return DAG.getNode(Opcode, SDLoc(N), VT, Load);
6991 /// An EXTR instruction is made up of two shifts, ORed together. This helper
6992 /// searches for and classifies those shifts.
6993 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
6995 if (N.getOpcode() == ISD::SHL)
6997 else if (N.getOpcode() == ISD::SRL)
7002 if (!isa<ConstantSDNode>(N.getOperand(1)))
7005 ShiftAmount = N->getConstantOperandVal(1);
7006 Src = N->getOperand(0);
7010 /// EXTR instruction extracts a contiguous chunk of bits from two existing
7011 /// registers viewed as a high/low pair. This function looks for the pattern:
7012 /// (or (shl VAL1, #N), (srl VAL2, #RegWidth-N)) and replaces it with an
7013 /// EXTR. Can't quite be done in TableGen because the two immediates aren't
7015 static SDValue tryCombineToEXTR(SDNode *N,
7016 TargetLowering::DAGCombinerInfo &DCI) {
7017 SelectionDAG &DAG = DCI.DAG;
7019 EVT VT = N->getValueType(0);
7021 assert(N->getOpcode() == ISD::OR && "Unexpected root");
7023 if (VT != MVT::i32 && VT != MVT::i64)
7027 uint32_t ShiftLHS = 0;
7029 if (!findEXTRHalf(N->getOperand(0), LHS, ShiftLHS, LHSFromHi))
7033 uint32_t ShiftRHS = 0;
7035 if (!findEXTRHalf(N->getOperand(1), RHS, ShiftRHS, RHSFromHi))
7038 // If they're both trying to come from the high part of the register, they're
7039 // not really an EXTR.
7040 if (LHSFromHi == RHSFromHi)
7043 if (ShiftLHS + ShiftRHS != VT.getSizeInBits())
7047 std::swap(LHS, RHS);
7048 std::swap(ShiftLHS, ShiftRHS);
7051 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS,
7052 DAG.getConstant(ShiftRHS, MVT::i64));
7055 static SDValue tryCombineToBSL(SDNode *N,
7056 TargetLowering::DAGCombinerInfo &DCI) {
7057 EVT VT = N->getValueType(0);
7058 SelectionDAG &DAG = DCI.DAG;
7064 SDValue N0 = N->getOperand(0);
7065 if (N0.getOpcode() != ISD::AND)
7068 SDValue N1 = N->getOperand(1);
7069 if (N1.getOpcode() != ISD::AND)
7072 // We only have to look for constant vectors here since the general, variable
7073 // case can be handled in TableGen.
7074 unsigned Bits = VT.getVectorElementType().getSizeInBits();
7075 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1);
7076 for (int i = 1; i >= 0; --i)
7077 for (int j = 1; j >= 0; --j) {
7078 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(i));
7079 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(j));
7083 bool FoundMatch = true;
7084 for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
7085 ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
7086 ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
7088 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
7095 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0),
7096 N0->getOperand(1 - i), N1->getOperand(1 - j));
7102 static SDValue performORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
7103 const AArch64Subtarget *Subtarget) {
7104 // Attempt to form an EXTR from (or (shl VAL1, #N), (srl VAL2, #RegWidth-N))
7105 if (!EnableAArch64ExtrGeneration)
7107 SelectionDAG &DAG = DCI.DAG;
7108 EVT VT = N->getValueType(0);
7110 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7113 SDValue Res = tryCombineToEXTR(N, DCI);
7117 Res = tryCombineToBSL(N, DCI);
7124 static SDValue performBitcastCombine(SDNode *N,
7125 TargetLowering::DAGCombinerInfo &DCI,
7126 SelectionDAG &DAG) {
7127 // Wait 'til after everything is legalized to try this. That way we have
7128 // legal vector types and such.
7129 if (DCI.isBeforeLegalizeOps())
7132 // Remove extraneous bitcasts around an extract_subvector.
7134 // (v4i16 (bitconvert
7135 // (extract_subvector (v2i64 (bitconvert (v8i16 ...)), (i64 1)))))
7137 // (extract_subvector ((v8i16 ...), (i64 4)))
7139 // Only interested in 64-bit vectors as the ultimate result.
7140 EVT VT = N->getValueType(0);
7143 if (VT.getSimpleVT().getSizeInBits() != 64)
7145 // Is the operand an extract_subvector starting at the beginning or halfway
7146 // point of the vector? A low half may also come through as an
7147 // EXTRACT_SUBREG, so look for that, too.
7148 SDValue Op0 = N->getOperand(0);
7149 if (Op0->getOpcode() != ISD::EXTRACT_SUBVECTOR &&
7150 !(Op0->isMachineOpcode() &&
7151 Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
7153 uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
7154 if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
7155 if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
7157 } else if (Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG) {
7158 if (idx != AArch64::dsub)
7160 // The dsub reference is equivalent to a lane zero subvector reference.
7163 // Look through the bitcast of the input to the extract.
7164 if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)
7166 SDValue Source = Op0->getOperand(0)->getOperand(0);
7167 // If the source type has twice the number of elements as our destination
7168 // type, we know this is an extract of the high or low half of the vector.
7169 EVT SVT = Source->getValueType(0);
7170 if (SVT.getVectorNumElements() != VT.getVectorNumElements() * 2)
7173 DEBUG(dbgs() << "aarch64-lower: bitcast extract_subvector simplification\n");
7175 // Create the simplified form to just extract the low or high half of the
7176 // vector directly rather than bothering with the bitcasts.
7178 unsigned NumElements = VT.getVectorNumElements();
7180 SDValue HalfIdx = DAG.getConstant(NumElements, MVT::i64);
7181 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx);
7183 SDValue SubReg = DAG.getTargetConstant(AArch64::dsub, MVT::i32);
7184 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, dl, VT,
7190 static SDValue performConcatVectorsCombine(SDNode *N,
7191 TargetLowering::DAGCombinerInfo &DCI,
7192 SelectionDAG &DAG) {
7193 // Wait 'til after everything is legalized to try this. That way we have
7194 // legal vector types and such.
7195 if (DCI.isBeforeLegalizeOps())
7199 EVT VT = N->getValueType(0);
7201 // If we see a (concat_vectors (v1x64 A), (v1x64 A)) it's really a vector
7202 // splat. The indexed instructions are going to be expecting a DUPLANE64, so
7203 // canonicalise to that.
7204 if (N->getOperand(0) == N->getOperand(1) && VT.getVectorNumElements() == 2) {
7205 assert(VT.getVectorElementType().getSizeInBits() == 64);
7206 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT,
7207 WidenVector(N->getOperand(0), DAG),
7208 DAG.getConstant(0, MVT::i64));
7211 // Canonicalise concat_vectors so that the right-hand vector has as few
7212 // bit-casts as possible before its real operation. The primary matching
7213 // destination for these operations will be the narrowing "2" instructions,
7214 // which depend on the operation being performed on this right-hand vector.
7216 // (concat_vectors LHS, (v1i64 (bitconvert (v4i16 RHS))))
7218 // (bitconvert (concat_vectors (v4i16 (bitconvert LHS)), RHS))
7220 SDValue Op1 = N->getOperand(1);
7221 if (Op1->getOpcode() != ISD::BITCAST)
7223 SDValue RHS = Op1->getOperand(0);
7224 MVT RHSTy = RHS.getValueType().getSimpleVT();
7225 // If the RHS is not a vector, this is not the pattern we're looking for.
7226 if (!RHSTy.isVector())
7229 DEBUG(dbgs() << "aarch64-lower: concat_vectors bitcast simplification\n");
7231 MVT ConcatTy = MVT::getVectorVT(RHSTy.getVectorElementType(),
7232 RHSTy.getVectorNumElements() * 2);
7234 ISD::BITCAST, dl, VT,
7235 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy,
7236 DAG.getNode(ISD::BITCAST, dl, RHSTy, N->getOperand(0)), RHS));
7239 static SDValue tryCombineFixedPointConvert(SDNode *N,
7240 TargetLowering::DAGCombinerInfo &DCI,
7241 SelectionDAG &DAG) {
7242 // Wait 'til after everything is legalized to try this. That way we have
7243 // legal vector types and such.
7244 if (DCI.isBeforeLegalizeOps())
7246 // Transform a scalar conversion of a value from a lane extract into a
7247 // lane extract of a vector conversion. E.g., from foo1 to foo2:
7248 // double foo1(int64x2_t a) { return vcvtd_n_f64_s64(a[1], 9); }
7249 // double foo2(int64x2_t a) { return vcvtq_n_f64_s64(a, 9)[1]; }
7251 // The second form interacts better with instruction selection and the
7252 // register allocator to avoid cross-class register copies that aren't
7253 // coalescable due to a lane reference.
7255 // Check the operand and see if it originates from a lane extract.
7256 SDValue Op1 = N->getOperand(1);
7257 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7258 // Yep, no additional predication needed. Perform the transform.
7259 SDValue IID = N->getOperand(0);
7260 SDValue Shift = N->getOperand(2);
7261 SDValue Vec = Op1.getOperand(0);
7262 SDValue Lane = Op1.getOperand(1);
7263 EVT ResTy = N->getValueType(0);
7267 // The vector width should be 128 bits by the time we get here, even
7268 // if it started as 64 bits (the extract_vector handling will have
7270 assert(Vec.getValueType().getSizeInBits() == 128 &&
7271 "unexpected vector size on extract_vector_elt!");
7272 if (Vec.getValueType() == MVT::v4i32)
7273 VecResTy = MVT::v4f32;
7274 else if (Vec.getValueType() == MVT::v2i64)
7275 VecResTy = MVT::v2f64;
7277 llvm_unreachable("unexpected vector type!");
7280 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift);
7281 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane);
7286 // AArch64 high-vector "long" operations are formed by performing the non-high
7287 // version on an extract_subvector of each operand which gets the high half:
7289 // (longop2 LHS, RHS) == (longop (extract_high LHS), (extract_high RHS))
7291 // However, there are cases which don't have an extract_high explicitly, but
7292 // have another operation that can be made compatible with one for free. For
7295 // (dupv64 scalar) --> (extract_high (dup128 scalar))
7297 // This routine does the actual conversion of such DUPs, once outer routines
7298 // have determined that everything else is in order.
7299 static SDValue tryExtendDUPToExtractHigh(SDValue N, SelectionDAG &DAG) {
7300 // We can handle most types of duplicate, but the lane ones have an extra
7301 // operand saying *which* lane, so we need to know.
7303 switch (N.getOpcode()) {
7304 case AArch64ISD::DUP:
7307 case AArch64ISD::DUPLANE8:
7308 case AArch64ISD::DUPLANE16:
7309 case AArch64ISD::DUPLANE32:
7310 case AArch64ISD::DUPLANE64:
7317 MVT NarrowTy = N.getSimpleValueType();
7318 if (!NarrowTy.is64BitVector())
7321 MVT ElementTy = NarrowTy.getVectorElementType();
7322 unsigned NumElems = NarrowTy.getVectorNumElements();
7323 MVT NewDUPVT = MVT::getVectorVT(ElementTy, NumElems * 2);
7327 NewDUP = DAG.getNode(N.getOpcode(), SDLoc(N), NewDUPVT, N.getOperand(0),
7330 NewDUP = DAG.getNode(AArch64ISD::DUP, SDLoc(N), NewDUPVT, N.getOperand(0));
7332 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N.getNode()), NarrowTy,
7333 NewDUP, DAG.getConstant(NumElems, MVT::i64));
7336 static bool isEssentiallyExtractSubvector(SDValue N) {
7337 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR)
7340 return N.getOpcode() == ISD::BITCAST &&
7341 N.getOperand(0).getOpcode() == ISD::EXTRACT_SUBVECTOR;
7344 /// \brief Helper structure to keep track of ISD::SET_CC operands.
7345 struct GenericSetCCInfo {
7346 const SDValue *Opnd0;
7347 const SDValue *Opnd1;
7351 /// \brief Helper structure to keep track of a SET_CC lowered into AArch64 code.
7352 struct AArch64SetCCInfo {
7354 AArch64CC::CondCode CC;
7357 /// \brief Helper structure to keep track of SetCC information.
7359 GenericSetCCInfo Generic;
7360 AArch64SetCCInfo AArch64;
7363 /// \brief Helper structure to be able to read SetCC information. If set to
7364 /// true, IsAArch64 field, Info is a AArch64SetCCInfo, otherwise Info is a
7365 /// GenericSetCCInfo.
7366 struct SetCCInfoAndKind {
7371 /// \brief Check whether or not \p Op is a SET_CC operation, either a generic or
7373 /// AArch64 lowered one.
7374 /// \p SetCCInfo is filled accordingly.
7375 /// \post SetCCInfo is meanginfull only when this function returns true.
7376 /// \return True when Op is a kind of SET_CC operation.
7377 static bool isSetCC(SDValue Op, SetCCInfoAndKind &SetCCInfo) {
7378 // If this is a setcc, this is straight forward.
7379 if (Op.getOpcode() == ISD::SETCC) {
7380 SetCCInfo.Info.Generic.Opnd0 = &Op.getOperand(0);
7381 SetCCInfo.Info.Generic.Opnd1 = &Op.getOperand(1);
7382 SetCCInfo.Info.Generic.CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7383 SetCCInfo.IsAArch64 = false;
7386 // Otherwise, check if this is a matching csel instruction.
7390 if (Op.getOpcode() != AArch64ISD::CSEL)
7392 // Set the information about the operands.
7393 // TODO: we want the operands of the Cmp not the csel
7394 SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
7395 SetCCInfo.IsAArch64 = true;
7396 SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
7397 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
7399 // Check that the operands matches the constraints:
7400 // (1) Both operands must be constants.
7401 // (2) One must be 1 and the other must be 0.
7402 ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
7403 ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7406 if (!TValue || !FValue)
7410 if (!TValue->isOne()) {
7411 // Update the comparison when we are interested in !cc.
7412 std::swap(TValue, FValue);
7413 SetCCInfo.Info.AArch64.CC =
7414 AArch64CC::getInvertedCondCode(SetCCInfo.Info.AArch64.CC);
7416 return TValue->isOne() && FValue->isNullValue();
7419 // Returns true if Op is setcc or zext of setcc.
7420 static bool isSetCCOrZExtSetCC(const SDValue& Op, SetCCInfoAndKind &Info) {
7421 if (isSetCC(Op, Info))
7423 return ((Op.getOpcode() == ISD::ZERO_EXTEND) &&
7424 isSetCC(Op->getOperand(0), Info));
7427 // The folding we want to perform is:
7428 // (add x, [zext] (setcc cc ...) )
7430 // (csel x, (add x, 1), !cc ...)
7432 // The latter will get matched to a CSINC instruction.
7433 static SDValue performSetccAddFolding(SDNode *Op, SelectionDAG &DAG) {
7434 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
7435 SDValue LHS = Op->getOperand(0);
7436 SDValue RHS = Op->getOperand(1);
7437 SetCCInfoAndKind InfoAndKind;
7439 // If neither operand is a SET_CC, give up.
7440 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind)) {
7441 std::swap(LHS, RHS);
7442 if (!isSetCCOrZExtSetCC(LHS, InfoAndKind))
7446 // FIXME: This could be generatized to work for FP comparisons.
7447 EVT CmpVT = InfoAndKind.IsAArch64
7448 ? InfoAndKind.Info.AArch64.Cmp->getOperand(0).getValueType()
7449 : InfoAndKind.Info.Generic.Opnd0->getValueType();
7450 if (CmpVT != MVT::i32 && CmpVT != MVT::i64)
7456 if (InfoAndKind.IsAArch64) {
7457 CCVal = DAG.getConstant(
7458 AArch64CC::getInvertedCondCode(InfoAndKind.Info.AArch64.CC), MVT::i32);
7459 Cmp = *InfoAndKind.Info.AArch64.Cmp;
7461 Cmp = getAArch64Cmp(*InfoAndKind.Info.Generic.Opnd0,
7462 *InfoAndKind.Info.Generic.Opnd1,
7463 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, true),
7466 EVT VT = Op->getValueType(0);
7467 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, VT));
7468 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
7471 // The basic add/sub long vector instructions have variants with "2" on the end
7472 // which act on the high-half of their inputs. They are normally matched by
7475 // (add (zeroext (extract_high LHS)),
7476 // (zeroext (extract_high RHS)))
7477 // -> uaddl2 vD, vN, vM
7479 // However, if one of the extracts is something like a duplicate, this
7480 // instruction can still be used profitably. This function puts the DAG into a
7481 // more appropriate form for those patterns to trigger.
7482 static SDValue performAddSubLongCombine(SDNode *N,
7483 TargetLowering::DAGCombinerInfo &DCI,
7484 SelectionDAG &DAG) {
7485 if (DCI.isBeforeLegalizeOps())
7488 MVT VT = N->getSimpleValueType(0);
7489 if (!VT.is128BitVector()) {
7490 if (N->getOpcode() == ISD::ADD)
7491 return performSetccAddFolding(N, DAG);
7495 // Make sure both branches are extended in the same way.
7496 SDValue LHS = N->getOperand(0);
7497 SDValue RHS = N->getOperand(1);
7498 if ((LHS.getOpcode() != ISD::ZERO_EXTEND &&
7499 LHS.getOpcode() != ISD::SIGN_EXTEND) ||
7500 LHS.getOpcode() != RHS.getOpcode())
7503 unsigned ExtType = LHS.getOpcode();
7505 // It's not worth doing if at least one of the inputs isn't already an
7506 // extract, but we don't know which it'll be so we have to try both.
7507 if (isEssentiallyExtractSubvector(LHS.getOperand(0))) {
7508 RHS = tryExtendDUPToExtractHigh(RHS.getOperand(0), DAG);
7512 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
7513 } else if (isEssentiallyExtractSubvector(RHS.getOperand(0))) {
7514 LHS = tryExtendDUPToExtractHigh(LHS.getOperand(0), DAG);
7518 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
7521 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS);
7524 // Massage DAGs which we can use the high-half "long" operations on into
7525 // something isel will recognize better. E.g.
7527 // (aarch64_neon_umull (extract_high vec) (dupv64 scalar)) -->
7528 // (aarch64_neon_umull (extract_high (v2i64 vec)))
7529 // (extract_high (v2i64 (dup128 scalar)))))
7531 static SDValue tryCombineLongOpWithDup(unsigned IID, SDNode *N,
7532 TargetLowering::DAGCombinerInfo &DCI,
7533 SelectionDAG &DAG) {
7534 if (DCI.isBeforeLegalizeOps())
7537 SDValue LHS = N->getOperand(1);
7538 SDValue RHS = N->getOperand(2);
7539 assert(LHS.getValueType().is64BitVector() &&
7540 RHS.getValueType().is64BitVector() &&
7541 "unexpected shape for long operation");
7543 // Either node could be a DUP, but it's not worth doing both of them (you'd
7544 // just as well use the non-high version) so look for a corresponding extract
7545 // operation on the other "wing".
7546 if (isEssentiallyExtractSubvector(LHS)) {
7547 RHS = tryExtendDUPToExtractHigh(RHS, DAG);
7550 } else if (isEssentiallyExtractSubvector(RHS)) {
7551 LHS = tryExtendDUPToExtractHigh(LHS, DAG);
7556 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0),
7557 N->getOperand(0), LHS, RHS);
7560 static SDValue tryCombineShiftImm(unsigned IID, SDNode *N, SelectionDAG &DAG) {
7561 MVT ElemTy = N->getSimpleValueType(0).getScalarType();
7562 unsigned ElemBits = ElemTy.getSizeInBits();
7564 int64_t ShiftAmount;
7565 if (BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(2))) {
7566 APInt SplatValue, SplatUndef;
7567 unsigned SplatBitSize;
7569 if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
7570 HasAnyUndefs, ElemBits) ||
7571 SplatBitSize != ElemBits)
7574 ShiftAmount = SplatValue.getSExtValue();
7575 } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
7576 ShiftAmount = CVN->getSExtValue();
7584 llvm_unreachable("Unknown shift intrinsic");
7585 case Intrinsic::aarch64_neon_sqshl:
7586 Opcode = AArch64ISD::SQSHL_I;
7587 IsRightShift = false;
7589 case Intrinsic::aarch64_neon_uqshl:
7590 Opcode = AArch64ISD::UQSHL_I;
7591 IsRightShift = false;
7593 case Intrinsic::aarch64_neon_srshl:
7594 Opcode = AArch64ISD::SRSHR_I;
7595 IsRightShift = true;
7597 case Intrinsic::aarch64_neon_urshl:
7598 Opcode = AArch64ISD::URSHR_I;
7599 IsRightShift = true;
7601 case Intrinsic::aarch64_neon_sqshlu:
7602 Opcode = AArch64ISD::SQSHLU_I;
7603 IsRightShift = false;
7607 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
7608 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7609 DAG.getConstant(-ShiftAmount, MVT::i32));
7610 else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits)
7611 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), N->getOperand(1),
7612 DAG.getConstant(ShiftAmount, MVT::i32));
7617 // The CRC32[BH] instructions ignore the high bits of their data operand. Since
7618 // the intrinsics must be legal and take an i32, this means there's almost
7619 // certainly going to be a zext in the DAG which we can eliminate.
7620 static SDValue tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) {
7621 SDValue AndN = N->getOperand(2);
7622 if (AndN.getOpcode() != ISD::AND)
7625 ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
7626 if (!CMask || CMask->getZExtValue() != Mask)
7629 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32,
7630 N->getOperand(0), N->getOperand(1), AndN.getOperand(0));
7633 static SDValue performIntrinsicCombine(SDNode *N,
7634 TargetLowering::DAGCombinerInfo &DCI,
7635 const AArch64Subtarget *Subtarget) {
7636 SelectionDAG &DAG = DCI.DAG;
7637 unsigned IID = getIntrinsicID(N);
7641 case Intrinsic::aarch64_neon_vcvtfxs2fp:
7642 case Intrinsic::aarch64_neon_vcvtfxu2fp:
7643 return tryCombineFixedPointConvert(N, DCI, DAG);
7645 case Intrinsic::aarch64_neon_fmax:
7646 return DAG.getNode(AArch64ISD::FMAX, SDLoc(N), N->getValueType(0),
7647 N->getOperand(1), N->getOperand(2));
7648 case Intrinsic::aarch64_neon_fmin:
7649 return DAG.getNode(AArch64ISD::FMIN, SDLoc(N), N->getValueType(0),
7650 N->getOperand(1), N->getOperand(2));
7651 case Intrinsic::aarch64_neon_smull:
7652 case Intrinsic::aarch64_neon_umull:
7653 case Intrinsic::aarch64_neon_pmull:
7654 case Intrinsic::aarch64_neon_sqdmull:
7655 return tryCombineLongOpWithDup(IID, N, DCI, DAG);
7656 case Intrinsic::aarch64_neon_sqshl:
7657 case Intrinsic::aarch64_neon_uqshl:
7658 case Intrinsic::aarch64_neon_sqshlu:
7659 case Intrinsic::aarch64_neon_srshl:
7660 case Intrinsic::aarch64_neon_urshl:
7661 return tryCombineShiftImm(IID, N, DAG);
7662 case Intrinsic::aarch64_crc32b:
7663 case Intrinsic::aarch64_crc32cb:
7664 return tryCombineCRC32(0xff, N, DAG);
7665 case Intrinsic::aarch64_crc32h:
7666 case Intrinsic::aarch64_crc32ch:
7667 return tryCombineCRC32(0xffff, N, DAG);
7672 static SDValue performExtendCombine(SDNode *N,
7673 TargetLowering::DAGCombinerInfo &DCI,
7674 SelectionDAG &DAG) {
7675 // If we see something like (zext (sabd (extract_high ...), (DUP ...))) then
7676 // we can convert that DUP into another extract_high (of a bigger DUP), which
7677 // helps the backend to decide that an sabdl2 would be useful, saving a real
7678 // extract_high operation.
7679 if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&
7680 N->getOperand(0).getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
7681 SDNode *ABDNode = N->getOperand(0).getNode();
7682 unsigned IID = getIntrinsicID(ABDNode);
7683 if (IID == Intrinsic::aarch64_neon_sabd ||
7684 IID == Intrinsic::aarch64_neon_uabd) {
7685 SDValue NewABD = tryCombineLongOpWithDup(IID, ABDNode, DCI, DAG);
7686 if (!NewABD.getNode())
7689 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0),
7694 // This is effectively a custom type legalization for AArch64.
7696 // Type legalization will split an extend of a small, legal, type to a larger
7697 // illegal type by first splitting the destination type, often creating
7698 // illegal source types, which then get legalized in isel-confusing ways,
7699 // leading to really terrible codegen. E.g.,
7700 // %result = v8i32 sext v8i8 %value
7702 // %losrc = extract_subreg %value, ...
7703 // %hisrc = extract_subreg %value, ...
7704 // %lo = v4i32 sext v4i8 %losrc
7705 // %hi = v4i32 sext v4i8 %hisrc
7706 // Things go rapidly downhill from there.
7708 // For AArch64, the [sz]ext vector instructions can only go up one element
7709 // size, so we can, e.g., extend from i8 to i16, but to go from i8 to i32
7710 // take two instructions.
7712 // This implies that the most efficient way to do the extend from v8i8
7713 // to two v4i32 values is to first extend the v8i8 to v8i16, then do
7714 // the normal splitting to happen for the v8i16->v8i32.
7716 // This is pre-legalization to catch some cases where the default
7717 // type legalization will create ill-tempered code.
7718 if (!DCI.isBeforeLegalizeOps())
7721 // We're only interested in cleaning things up for non-legal vector types
7722 // here. If both the source and destination are legal, things will just
7723 // work naturally without any fiddling.
7724 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7725 EVT ResVT = N->getValueType(0);
7726 if (!ResVT.isVector() || TLI.isTypeLegal(ResVT))
7728 // If the vector type isn't a simple VT, it's beyond the scope of what
7729 // we're worried about here. Let legalization do its thing and hope for
7731 SDValue Src = N->getOperand(0);
7732 EVT SrcVT = Src->getValueType(0);
7733 if (!ResVT.isSimple() || !SrcVT.isSimple())
7736 // If the source VT is a 64-bit vector, we can play games and get the
7737 // better results we want.
7738 if (SrcVT.getSizeInBits() != 64)
7741 unsigned SrcEltSize = SrcVT.getVectorElementType().getSizeInBits();
7742 unsigned ElementCount = SrcVT.getVectorNumElements();
7743 SrcVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize * 2), ElementCount);
7745 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src);
7747 // Now split the rest of the operation into two halves, each with a 64
7751 unsigned NumElements = ResVT.getVectorNumElements();
7752 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
7753 LoVT = HiVT = EVT::getVectorVT(*DAG.getContext(),
7754 ResVT.getVectorElementType(), NumElements / 2);
7756 EVT InNVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
7757 LoVT.getVectorNumElements());
7758 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7759 DAG.getIntPtrConstant(0));
7760 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src,
7761 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
7762 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo);
7763 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi);
7765 // Now combine the parts back together so we still have a single result
7766 // like the combiner expects.
7767 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
7770 /// Replace a splat of a scalar to a vector store by scalar stores of the scalar
7771 /// value. The load store optimizer pass will merge them to store pair stores.
7772 /// This has better performance than a splat of the scalar followed by a split
7773 /// vector store. Even if the stores are not merged it is four stores vs a dup,
7774 /// followed by an ext.b and two stores.
7775 static SDValue replaceSplatVectorStore(SelectionDAG &DAG, StoreSDNode *St) {
7776 SDValue StVal = St->getValue();
7777 EVT VT = StVal.getValueType();
7779 // Don't replace floating point stores, they possibly won't be transformed to
7780 // stp because of the store pair suppress pass.
7781 if (VT.isFloatingPoint())
7784 // Check for insert vector elements.
7785 if (StVal.getOpcode() != ISD::INSERT_VECTOR_ELT)
7788 // We can express a splat as store pair(s) for 2 or 4 elements.
7789 unsigned NumVecElts = VT.getVectorNumElements();
7790 if (NumVecElts != 4 && NumVecElts != 2)
7792 SDValue SplatVal = StVal.getOperand(1);
7793 unsigned RemainInsertElts = NumVecElts - 1;
7795 // Check that this is a splat.
7796 while (--RemainInsertElts) {
7797 SDValue NextInsertElt = StVal.getOperand(0);
7798 if (NextInsertElt.getOpcode() != ISD::INSERT_VECTOR_ELT)
7800 if (NextInsertElt.getOperand(1) != SplatVal)
7802 StVal = NextInsertElt;
7804 unsigned OrigAlignment = St->getAlignment();
7805 unsigned EltOffset = NumVecElts == 4 ? 4 : 8;
7806 unsigned Alignment = std::min(OrigAlignment, EltOffset);
7808 // Create scalar stores. This is at least as good as the code sequence for a
7809 // split unaligned store wich is a dup.s, ext.b, and two stores.
7810 // Most of the time the three stores should be replaced by store pair
7811 // instructions (stp).
7813 SDValue BasePtr = St->getBasePtr();
7815 DAG.getStore(St->getChain(), DL, SplatVal, BasePtr, St->getPointerInfo(),
7816 St->isVolatile(), St->isNonTemporal(), St->getAlignment());
7818 unsigned Offset = EltOffset;
7819 while (--NumVecElts) {
7820 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7821 DAG.getConstant(Offset, MVT::i64));
7822 NewST1 = DAG.getStore(NewST1.getValue(0), DL, SplatVal, OffsetPtr,
7823 St->getPointerInfo(), St->isVolatile(),
7824 St->isNonTemporal(), Alignment);
7825 Offset += EltOffset;
7830 static SDValue performSTORECombine(SDNode *N,
7831 TargetLowering::DAGCombinerInfo &DCI,
7833 const AArch64Subtarget *Subtarget) {
7834 if (!DCI.isBeforeLegalize())
7837 StoreSDNode *S = cast<StoreSDNode>(N);
7838 if (S->isVolatile())
7841 // Cyclone has bad performance on unaligned 16B stores when crossing line and
7842 // page boundries. We want to split such stores.
7843 if (!Subtarget->isCyclone())
7846 // Don't split at Oz.
7847 MachineFunction &MF = DAG.getMachineFunction();
7848 bool IsMinSize = MF.getFunction()->getAttributes().hasAttribute(
7849 AttributeSet::FunctionIndex, Attribute::MinSize);
7853 SDValue StVal = S->getValue();
7854 EVT VT = StVal.getValueType();
7856 // Don't split v2i64 vectors. Memcpy lowering produces those and splitting
7857 // those up regresses performance on micro-benchmarks and olden/bh.
7858 if (!VT.isVector() || VT.getVectorNumElements() < 2 || VT == MVT::v2i64)
7861 // Split unaligned 16B stores. They are terrible for performance.
7862 // Don't split stores with alignment of 1 or 2. Code that uses clang vector
7863 // extensions can use this to mark that it does not want splitting to happen
7864 // (by underspecifying alignment to be 1 or 2). Furthermore, the chance of
7865 // eliminating alignment hazards is only 1 in 8 for alignment of 2.
7866 if (VT.getSizeInBits() != 128 || S->getAlignment() >= 16 ||
7867 S->getAlignment() <= 2)
7870 // If we get a splat of a scalar convert this vector store to a store of
7871 // scalars. They will be merged into store pairs thereby removing two
7873 SDValue ReplacedSplat = replaceSplatVectorStore(DAG, S);
7874 if (ReplacedSplat != SDValue())
7875 return ReplacedSplat;
7878 unsigned NumElts = VT.getVectorNumElements() / 2;
7879 // Split VT into two.
7881 EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(), NumElts);
7882 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7883 DAG.getIntPtrConstant(0));
7884 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal,
7885 DAG.getIntPtrConstant(NumElts));
7886 SDValue BasePtr = S->getBasePtr();
7888 DAG.getStore(S->getChain(), DL, SubVector0, BasePtr, S->getPointerInfo(),
7889 S->isVolatile(), S->isNonTemporal(), S->getAlignment());
7890 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
7891 DAG.getConstant(8, MVT::i64));
7892 return DAG.getStore(NewST1.getValue(0), DL, SubVector1, OffsetPtr,
7893 S->getPointerInfo(), S->isVolatile(), S->isNonTemporal(),
7897 /// Target-specific DAG combine function for post-increment LD1 (lane) and
7898 /// post-increment LD1R.
7899 static SDValue performPostLD1Combine(SDNode *N,
7900 TargetLowering::DAGCombinerInfo &DCI,
7902 if (DCI.isBeforeLegalizeOps())
7905 SelectionDAG &DAG = DCI.DAG;
7906 EVT VT = N->getValueType(0);
7908 unsigned LoadIdx = IsLaneOp ? 1 : 0;
7909 SDNode *LD = N->getOperand(LoadIdx).getNode();
7910 // If it is not LOAD, can not do such combine.
7911 if (LD->getOpcode() != ISD::LOAD)
7914 LoadSDNode *LoadSDN = cast<LoadSDNode>(LD);
7915 EVT MemVT = LoadSDN->getMemoryVT();
7916 // Check if memory operand is the same type as the vector element.
7917 if (MemVT != VT.getVectorElementType())
7920 // Check if there are other uses. If so, do not combine as it will introduce
7922 for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE;
7924 if (UI.getUse().getResNo() == 1) // Ignore uses of the chain result.
7930 SDValue Addr = LD->getOperand(1);
7931 SDValue Vector = N->getOperand(0);
7932 // Search for a use of the address operand that is an increment.
7933 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
7934 Addr.getNode()->use_end(); UI != UE; ++UI) {
7936 if (User->getOpcode() != ISD::ADD
7937 || UI.getUse().getResNo() != Addr.getResNo())
7940 // Check that the add is independent of the load. Otherwise, folding it
7941 // would create a cycle.
7942 if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
7944 // Also check that add is not used in the vector operand. This would also
7946 if (User->isPredecessorOf(Vector.getNode()))
7949 // If the increment is a constant, it must match the memory ref size.
7950 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7951 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7952 uint32_t IncVal = CInc->getZExtValue();
7953 unsigned NumBytes = VT.getScalarSizeInBits() / 8;
7954 if (IncVal != NumBytes)
7956 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
7959 SmallVector<SDValue, 8> Ops;
7960 Ops.push_back(LD->getOperand(0)); // Chain
7962 Ops.push_back(Vector); // The vector to be inserted
7963 Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
7965 Ops.push_back(Addr);
7968 EVT Tys[3] = { VT, MVT::i64, MVT::Other };
7969 SDVTList SDTys = DAG.getVTList(Tys);
7970 unsigned NewOp = IsLaneOp ? AArch64ISD::LD1LANEpost : AArch64ISD::LD1DUPpost;
7971 SDValue UpdN = DAG.getMemIntrinsicNode(NewOp, SDLoc(N), SDTys, Ops,
7973 LoadSDN->getMemOperand());
7976 std::vector<SDValue> NewResults;
7977 NewResults.push_back(SDValue(LD, 0)); // The result of load
7978 NewResults.push_back(SDValue(UpdN.getNode(), 2)); // Chain
7979 DCI.CombineTo(LD, NewResults);
7980 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result
7981 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register
7988 /// Target-specific DAG combine function for NEON load/store intrinsics
7989 /// to merge base address updates.
7990 static SDValue performNEONPostLDSTCombine(SDNode *N,
7991 TargetLowering::DAGCombinerInfo &DCI,
7992 SelectionDAG &DAG) {
7993 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
7996 unsigned AddrOpIdx = N->getNumOperands() - 1;
7997 SDValue Addr = N->getOperand(AddrOpIdx);
7999 // Search for a use of the address operand that is an increment.
8000 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8001 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8003 if (User->getOpcode() != ISD::ADD ||
8004 UI.getUse().getResNo() != Addr.getResNo())
8007 // Check that the add is independent of the load/store. Otherwise, folding
8008 // it would create a cycle.
8009 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8012 // Find the new opcode for the updating load/store.
8013 bool IsStore = false;
8014 bool IsLaneOp = false;
8015 bool IsDupOp = false;
8016 unsigned NewOpc = 0;
8017 unsigned NumVecs = 0;
8018 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8020 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8021 case Intrinsic::aarch64_neon_ld2: NewOpc = AArch64ISD::LD2post;
8023 case Intrinsic::aarch64_neon_ld3: NewOpc = AArch64ISD::LD3post;
8025 case Intrinsic::aarch64_neon_ld4: NewOpc = AArch64ISD::LD4post;
8027 case Intrinsic::aarch64_neon_st2: NewOpc = AArch64ISD::ST2post;
8028 NumVecs = 2; IsStore = true; break;
8029 case Intrinsic::aarch64_neon_st3: NewOpc = AArch64ISD::ST3post;
8030 NumVecs = 3; IsStore = true; break;
8031 case Intrinsic::aarch64_neon_st4: NewOpc = AArch64ISD::ST4post;
8032 NumVecs = 4; IsStore = true; break;
8033 case Intrinsic::aarch64_neon_ld1x2: NewOpc = AArch64ISD::LD1x2post;
8035 case Intrinsic::aarch64_neon_ld1x3: NewOpc = AArch64ISD::LD1x3post;
8037 case Intrinsic::aarch64_neon_ld1x4: NewOpc = AArch64ISD::LD1x4post;
8039 case Intrinsic::aarch64_neon_st1x2: NewOpc = AArch64ISD::ST1x2post;
8040 NumVecs = 2; IsStore = true; break;
8041 case Intrinsic::aarch64_neon_st1x3: NewOpc = AArch64ISD::ST1x3post;
8042 NumVecs = 3; IsStore = true; break;
8043 case Intrinsic::aarch64_neon_st1x4: NewOpc = AArch64ISD::ST1x4post;
8044 NumVecs = 4; IsStore = true; break;
8045 case Intrinsic::aarch64_neon_ld2r: NewOpc = AArch64ISD::LD2DUPpost;
8046 NumVecs = 2; IsDupOp = true; break;
8047 case Intrinsic::aarch64_neon_ld3r: NewOpc = AArch64ISD::LD3DUPpost;
8048 NumVecs = 3; IsDupOp = true; break;
8049 case Intrinsic::aarch64_neon_ld4r: NewOpc = AArch64ISD::LD4DUPpost;
8050 NumVecs = 4; IsDupOp = true; break;
8051 case Intrinsic::aarch64_neon_ld2lane: NewOpc = AArch64ISD::LD2LANEpost;
8052 NumVecs = 2; IsLaneOp = true; break;
8053 case Intrinsic::aarch64_neon_ld3lane: NewOpc = AArch64ISD::LD3LANEpost;
8054 NumVecs = 3; IsLaneOp = true; break;
8055 case Intrinsic::aarch64_neon_ld4lane: NewOpc = AArch64ISD::LD4LANEpost;
8056 NumVecs = 4; IsLaneOp = true; break;
8057 case Intrinsic::aarch64_neon_st2lane: NewOpc = AArch64ISD::ST2LANEpost;
8058 NumVecs = 2; IsStore = true; IsLaneOp = true; break;
8059 case Intrinsic::aarch64_neon_st3lane: NewOpc = AArch64ISD::ST3LANEpost;
8060 NumVecs = 3; IsStore = true; IsLaneOp = true; break;
8061 case Intrinsic::aarch64_neon_st4lane: NewOpc = AArch64ISD::ST4LANEpost;
8062 NumVecs = 4; IsStore = true; IsLaneOp = true; break;
8067 VecTy = N->getOperand(2).getValueType();
8069 VecTy = N->getValueType(0);
8071 // If the increment is a constant, it must match the memory ref size.
8072 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8073 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8074 uint32_t IncVal = CInc->getZExtValue();
8075 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8076 if (IsLaneOp || IsDupOp)
8077 NumBytes /= VecTy.getVectorNumElements();
8078 if (IncVal != NumBytes)
8080 Inc = DAG.getRegister(AArch64::XZR, MVT::i64);
8082 SmallVector<SDValue, 8> Ops;
8083 Ops.push_back(N->getOperand(0)); // Incoming chain
8084 // Load lane and store have vector list as input.
8085 if (IsLaneOp || IsStore)
8086 for (unsigned i = 2; i < AddrOpIdx; ++i)
8087 Ops.push_back(N->getOperand(i));
8088 Ops.push_back(Addr); // Base register
8093 unsigned NumResultVecs = (IsStore ? 0 : NumVecs);
8095 for (n = 0; n < NumResultVecs; ++n)
8097 Tys[n++] = MVT::i64; // Type of write back register
8098 Tys[n] = MVT::Other; // Type of the chain
8099 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs + 2));
8101 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
8102 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys, Ops,
8103 MemInt->getMemoryVT(),
8104 MemInt->getMemOperand());
8107 std::vector<SDValue> NewResults;
8108 for (unsigned i = 0; i < NumResultVecs; ++i) {
8109 NewResults.push_back(SDValue(UpdN.getNode(), i));
8111 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1));
8112 DCI.CombineTo(N, NewResults);
8113 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
8120 // Checks to see if the value is the prescribed width and returns information
8121 // about its extension mode.
8123 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) {
8124 ExtType = ISD::NON_EXTLOAD;
8125 switch(V.getNode()->getOpcode()) {
8129 LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
8130 if ((LoadNode->getMemoryVT() == MVT::i8 && width == 8)
8131 || (LoadNode->getMemoryVT() == MVT::i16 && width == 16)) {
8132 ExtType = LoadNode->getExtensionType();
8137 case ISD::AssertSext: {
8138 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8139 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8140 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8141 ExtType = ISD::SEXTLOAD;
8146 case ISD::AssertZext: {
8147 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
8148 if ((TypeNode->getVT() == MVT::i8 && width == 8)
8149 || (TypeNode->getVT() == MVT::i16 && width == 16)) {
8150 ExtType = ISD::ZEXTLOAD;
8156 case ISD::TargetConstant: {
8157 if (std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
8167 // This function does a whole lot of voodoo to determine if the tests are
8168 // equivalent without and with a mask. Essentially what happens is that given a
8171 // +-------------+ +-------------+ +-------------+ +-------------+
8172 // | Input | | AddConstant | | CompConstant| | CC |
8173 // +-------------+ +-------------+ +-------------+ +-------------+
8175 // V V | +----------+
8176 // +-------------+ +----+ | |
8177 // | ADD | |0xff| | |
8178 // +-------------+ +----+ | |
8181 // +-------------+ | |
8183 // +-------------+ | |
8192 // The AND node may be safely removed for some combinations of inputs. In
8193 // particular we need to take into account the extension type of the Input,
8194 // the exact values of AddConstant, CompConstant, and CC, along with the nominal
8195 // width of the input (this can work for any width inputs, the above graph is
8196 // specific to 8 bits.
8198 // The specific equations were worked out by generating output tables for each
8199 // AArch64CC value in terms of and AddConstant (w1), CompConstant(w2). The
8200 // problem was simplified by working with 4 bit inputs, which means we only
8201 // needed to reason about 24 distinct bit patterns: 8 patterns unique to zero
8202 // extension (8,15), 8 patterns unique to sign extensions (-8,-1), and 8
8203 // patterns present in both extensions (0,7). For every distinct set of
8204 // AddConstant and CompConstants bit patterns we can consider the masked and
8205 // unmasked versions to be equivalent if the result of this function is true for
8206 // all 16 distinct bit patterns of for the current extension type of Input (w0).
8209 // and w10, w8, #0x0f
8211 // cset w9, AArch64CC
8213 // cset w11, AArch64CC
8218 // Since the above function shows when the outputs are equivalent it defines
8219 // when it is safe to remove the AND. Unfortunately it only runs on AArch64 and
8220 // would be expensive to run during compiles. The equations below were written
8221 // in a test harness that confirmed they gave equivalent outputs to the above
8222 // for all inputs function, so they can be used determine if the removal is
8225 // isEquivalentMaskless() is the code for testing if the AND can be removed
8226 // factored out of the DAG recognition as the DAG can take several forms.
8229 bool isEquivalentMaskless(unsigned CC, unsigned width,
8230 ISD::LoadExtType ExtType, signed AddConstant,
8231 signed CompConstant) {
8232 // By being careful about our equations and only writing the in term
8233 // symbolic values and well known constants (0, 1, -1, MaxUInt) we can
8234 // make them generally applicable to all bit widths.
8235 signed MaxUInt = (1 << width);
8237 // For the purposes of these comparisons sign extending the type is
8238 // equivalent to zero extending the add and displacing it by half the integer
8239 // width. Provided we are careful and make sure our equations are valid over
8240 // the whole range we can just adjust the input and avoid writing equations
8241 // for sign extended inputs.
8242 if (ExtType == ISD::SEXTLOAD)
8243 AddConstant -= (1 << (width-1));
8247 case AArch64CC::GT: {
8248 if ((AddConstant == 0) ||
8249 (CompConstant == MaxUInt - 1 && AddConstant < 0) ||
8250 (AddConstant >= 0 && CompConstant < 0) ||
8251 (AddConstant <= 0 && CompConstant <= 0 && CompConstant < AddConstant))
8255 case AArch64CC::GE: {
8256 if ((AddConstant == 0) ||
8257 (AddConstant >= 0 && CompConstant <= 0) ||
8258 (AddConstant <= 0 && CompConstant <= 0 && CompConstant <= AddConstant))
8262 case AArch64CC::LS: {
8263 if ((AddConstant >= 0 && CompConstant < 0) ||
8264 (AddConstant <= 0 && CompConstant >= -1 &&
8265 CompConstant < AddConstant + MaxUInt))
8269 case AArch64CC::MI: {
8270 if ((AddConstant == 0) ||
8271 (AddConstant > 0 && CompConstant <= 0) ||
8272 (AddConstant < 0 && CompConstant <= AddConstant))
8276 case AArch64CC::HS: {
8277 if ((AddConstant >= 0 && CompConstant <= 0) ||
8278 (AddConstant <= 0 && CompConstant >= 0 &&
8279 CompConstant <= AddConstant + MaxUInt))
8283 case AArch64CC::NE: {
8284 if ((AddConstant > 0 && CompConstant < 0) ||
8285 (AddConstant < 0 && CompConstant >= 0 &&
8286 CompConstant < AddConstant + MaxUInt) ||
8287 (AddConstant >= 0 && CompConstant >= 0 &&
8288 CompConstant >= AddConstant) ||
8289 (AddConstant <= 0 && CompConstant < 0 && CompConstant < AddConstant))
8298 case AArch64CC::Invalid:
8306 SDValue performCONDCombine(SDNode *N,
8307 TargetLowering::DAGCombinerInfo &DCI,
8308 SelectionDAG &DAG, unsigned CCIndex,
8309 unsigned CmpIndex) {
8310 unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
8311 SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
8312 unsigned CondOpcode = SubsNode->getOpcode();
8314 if (CondOpcode != AArch64ISD::SUBS)
8317 // There is a SUBS feeding this condition. Is it fed by a mask we can
8320 SDNode *AndNode = SubsNode->getOperand(0).getNode();
8321 unsigned MaskBits = 0;
8323 if (AndNode->getOpcode() != ISD::AND)
8326 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
8327 uint32_t CNV = CN->getZExtValue();
8330 else if (CNV == 65535)
8337 SDValue AddValue = AndNode->getOperand(0);
8339 if (AddValue.getOpcode() != ISD::ADD)
8342 // The basic dag structure is correct, grab the inputs and validate them.
8344 SDValue AddInputValue1 = AddValue.getNode()->getOperand(0);
8345 SDValue AddInputValue2 = AddValue.getNode()->getOperand(1);
8346 SDValue SubsInputValue = SubsNode->getOperand(1);
8348 // The mask is present and the provenance of all the values is a smaller type,
8349 // lets see if the mask is superfluous.
8351 if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
8352 !isa<ConstantSDNode>(SubsInputValue.getNode()))
8355 ISD::LoadExtType ExtType;
8357 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) ||
8358 !checkValueWidth(AddInputValue2, MaskBits, ExtType) ||
8359 !checkValueWidth(AddInputValue1, MaskBits, ExtType) )
8362 if(!isEquivalentMaskless(CC, MaskBits, ExtType,
8363 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
8364 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
8367 // The AND is not necessary, remove it.
8369 SDVTList VTs = DAG.getVTList(SubsNode->getValueType(0),
8370 SubsNode->getValueType(1));
8371 SDValue Ops[] = { AddValue, SubsNode->getOperand(1) };
8373 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops);
8374 DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode());
8376 return SDValue(N, 0);
8379 // Optimize compare with zero and branch.
8380 static SDValue performBRCONDCombine(SDNode *N,
8381 TargetLowering::DAGCombinerInfo &DCI,
8382 SelectionDAG &DAG) {
8383 SDValue NV = performCONDCombine(N, DCI, DAG, 2, 3);
8386 SDValue Chain = N->getOperand(0);
8387 SDValue Dest = N->getOperand(1);
8388 SDValue CCVal = N->getOperand(2);
8389 SDValue Cmp = N->getOperand(3);
8391 assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
8392 unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
8393 if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
8396 unsigned CmpOpc = Cmp.getOpcode();
8397 if (CmpOpc != AArch64ISD::ADDS && CmpOpc != AArch64ISD::SUBS)
8400 // Only attempt folding if there is only one use of the flag and no use of the
8402 if (!Cmp->hasNUsesOfValue(0, 0) || !Cmp->hasNUsesOfValue(1, 1))
8405 SDValue LHS = Cmp.getOperand(0);
8406 SDValue RHS = Cmp.getOperand(1);
8408 assert(LHS.getValueType() == RHS.getValueType() &&
8409 "Expected the value type to be the same for both operands!");
8410 if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
8413 if (isa<ConstantSDNode>(LHS) && cast<ConstantSDNode>(LHS)->isNullValue())
8414 std::swap(LHS, RHS);
8416 if (!isa<ConstantSDNode>(RHS) || !cast<ConstantSDNode>(RHS)->isNullValue())
8419 if (LHS.getOpcode() == ISD::SHL || LHS.getOpcode() == ISD::SRA ||
8420 LHS.getOpcode() == ISD::SRL)
8423 // Fold the compare into the branch instruction.
8425 if (CC == AArch64CC::EQ)
8426 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8428 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest);
8430 // Do not add new nodes to DAG combiner worklist.
8431 DCI.CombineTo(N, BR, false);
8436 // vselect (v1i1 setcc) ->
8437 // vselect (v1iXX setcc) (XX is the size of the compared operand type)
8438 // FIXME: Currently the type legalizer can't handle VSELECT having v1i1 as
8439 // condition. If it can legalize "VSELECT v1i1" correctly, no need to combine
8441 static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
8442 SDValue N0 = N->getOperand(0);
8443 EVT CCVT = N0.getValueType();
8445 if (N0.getOpcode() != ISD::SETCC || CCVT.getVectorNumElements() != 1 ||
8446 CCVT.getVectorElementType() != MVT::i1)
8449 EVT ResVT = N->getValueType(0);
8450 EVT CmpVT = N0.getOperand(0).getValueType();
8451 // Only combine when the result type is of the same size as the compared
8453 if (ResVT.getSizeInBits() != CmpVT.getSizeInBits())
8456 SDValue IfTrue = N->getOperand(1);
8457 SDValue IfFalse = N->getOperand(2);
8459 DAG.getSetCC(SDLoc(N), CmpVT.changeVectorElementTypeToInteger(),
8460 N0.getOperand(0), N0.getOperand(1),
8461 cast<CondCodeSDNode>(N0.getOperand(2))->get());
8462 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC,
8466 /// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with
8467 /// the compare-mask instructions rather than going via NZCV, even if LHS and
8468 /// RHS are really scalar. This replaces any scalar setcc in the above pattern
8469 /// with a vector one followed by a DUP shuffle on the result.
8470 static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
8471 SDValue N0 = N->getOperand(0);
8472 EVT ResVT = N->getValueType(0);
8474 if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
8477 // If NumMaskElts == 0, the comparison is larger than select result. The
8478 // largest real NEON comparison is 64-bits per lane, which means the result is
8479 // at most 32-bits and an illegal vector. Just bail out for now.
8480 EVT SrcVT = N0.getOperand(0).getValueType();
8481 int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
8482 if (!ResVT.isVector() || NumMaskElts == 0)
8485 SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
8486 EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
8488 // First perform a vector comparison, where lane 0 is the one we're interested
8492 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
8494 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));
8495 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));
8497 // Now duplicate the comparison mask we want across all other lanes.
8498 SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
8499 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
8500 Mask = DAG.getNode(ISD::BITCAST, DL,
8501 ResVT.changeVectorElementTypeToInteger(), Mask);
8503 return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
8506 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
8507 DAGCombinerInfo &DCI) const {
8508 SelectionDAG &DAG = DCI.DAG;
8509 switch (N->getOpcode()) {
8514 return performAddSubLongCombine(N, DCI, DAG);
8516 return performXorCombine(N, DAG, DCI, Subtarget);
8518 return performMulCombine(N, DAG, DCI, Subtarget);
8519 case ISD::SINT_TO_FP:
8520 case ISD::UINT_TO_FP:
8521 return performIntToFpCombine(N, DAG);
8523 return performORCombine(N, DCI, Subtarget);
8524 case ISD::INTRINSIC_WO_CHAIN:
8525 return performIntrinsicCombine(N, DCI, Subtarget);
8526 case ISD::ANY_EXTEND:
8527 case ISD::ZERO_EXTEND:
8528 case ISD::SIGN_EXTEND:
8529 return performExtendCombine(N, DCI, DAG);
8531 return performBitcastCombine(N, DCI, DAG);
8532 case ISD::CONCAT_VECTORS:
8533 return performConcatVectorsCombine(N, DCI, DAG);
8535 return performSelectCombine(N, DAG);
8537 return performVSelectCombine(N, DCI.DAG);
8539 return performSTORECombine(N, DCI, DAG, Subtarget);
8540 case AArch64ISD::BRCOND:
8541 return performBRCONDCombine(N, DCI, DAG);
8542 case AArch64ISD::CSEL:
8543 return performCONDCombine(N, DCI, DAG, 2, 3);
8544 case AArch64ISD::DUP:
8545 return performPostLD1Combine(N, DCI, false);
8546 case ISD::INSERT_VECTOR_ELT:
8547 return performPostLD1Combine(N, DCI, true);
8548 case ISD::INTRINSIC_VOID:
8549 case ISD::INTRINSIC_W_CHAIN:
8550 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8551 case Intrinsic::aarch64_neon_ld2:
8552 case Intrinsic::aarch64_neon_ld3:
8553 case Intrinsic::aarch64_neon_ld4:
8554 case Intrinsic::aarch64_neon_ld1x2:
8555 case Intrinsic::aarch64_neon_ld1x3:
8556 case Intrinsic::aarch64_neon_ld1x4:
8557 case Intrinsic::aarch64_neon_ld2lane:
8558 case Intrinsic::aarch64_neon_ld3lane:
8559 case Intrinsic::aarch64_neon_ld4lane:
8560 case Intrinsic::aarch64_neon_ld2r:
8561 case Intrinsic::aarch64_neon_ld3r:
8562 case Intrinsic::aarch64_neon_ld4r:
8563 case Intrinsic::aarch64_neon_st2:
8564 case Intrinsic::aarch64_neon_st3:
8565 case Intrinsic::aarch64_neon_st4:
8566 case Intrinsic::aarch64_neon_st1x2:
8567 case Intrinsic::aarch64_neon_st1x3:
8568 case Intrinsic::aarch64_neon_st1x4:
8569 case Intrinsic::aarch64_neon_st2lane:
8570 case Intrinsic::aarch64_neon_st3lane:
8571 case Intrinsic::aarch64_neon_st4lane:
8572 return performNEONPostLDSTCombine(N, DCI, DAG);
8580 // Check if the return value is used as only a return value, as otherwise
8581 // we can't perform a tail-call. In particular, we need to check for
8582 // target ISD nodes that are returns and any other "odd" constructs
8583 // that the generic analysis code won't necessarily catch.
8584 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
8585 SDValue &Chain) const {
8586 if (N->getNumValues() != 1)
8588 if (!N->hasNUsesOfValue(1, 0))
8591 SDValue TCChain = Chain;
8592 SDNode *Copy = *N->use_begin();
8593 if (Copy->getOpcode() == ISD::CopyToReg) {
8594 // If the copy has a glue operand, we conservatively assume it isn't safe to
8595 // perform a tail call.
8596 if (Copy->getOperand(Copy->getNumOperands() - 1).getValueType() ==
8599 TCChain = Copy->getOperand(0);
8600 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
8603 bool HasRet = false;
8604 for (SDNode *Node : Copy->uses()) {
8605 if (Node->getOpcode() != AArch64ISD::RET_FLAG)
8617 // Return whether the an instruction can potentially be optimized to a tail
8618 // call. This will cause the optimizers to attempt to move, or duplicate,
8619 // return instructions to help enable tail call optimizations for this
8621 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
8622 if (!CI->isTailCall())
8628 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
8630 ISD::MemIndexedMode &AM,
8632 SelectionDAG &DAG) const {
8633 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
8636 Base = Op->getOperand(0);
8637 // All of the indexed addressing mode instructions take a signed
8638 // 9 bit immediate offset.
8639 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
8640 int64_t RHSC = (int64_t)RHS->getZExtValue();
8641 if (RHSC >= 256 || RHSC <= -256)
8643 IsInc = (Op->getOpcode() == ISD::ADD);
8644 Offset = Op->getOperand(1);
8650 bool AArch64TargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
8652 ISD::MemIndexedMode &AM,
8653 SelectionDAG &DAG) const {
8656 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8657 VT = LD->getMemoryVT();
8658 Ptr = LD->getBasePtr();
8659 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8660 VT = ST->getMemoryVT();
8661 Ptr = ST->getBasePtr();
8666 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG))
8668 AM = IsInc ? ISD::PRE_INC : ISD::PRE_DEC;
8672 bool AArch64TargetLowering::getPostIndexedAddressParts(
8673 SDNode *N, SDNode *Op, SDValue &Base, SDValue &Offset,
8674 ISD::MemIndexedMode &AM, SelectionDAG &DAG) const {
8677 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8678 VT = LD->getMemoryVT();
8679 Ptr = LD->getBasePtr();
8680 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8681 VT = ST->getMemoryVT();
8682 Ptr = ST->getBasePtr();
8687 if (!getIndexedAddressParts(Op, Base, Offset, AM, IsInc, DAG))
8689 // Post-indexing updates the base, so it's not a valid transform
8690 // if that's not the same as the load's pointer.
8693 AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
8697 static void ReplaceBITCASTResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
8698 SelectionDAG &DAG) {
8699 if (N->getValueType(0) != MVT::i16)
8703 SDValue Op = N->getOperand(0);
8704 assert(Op.getValueType() == MVT::f16 &&
8705 "Inconsistent bitcast? Only 16-bit types should be i16 or f16");
8707 DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, MVT::f32,
8708 DAG.getUNDEF(MVT::i32), Op,
8709 DAG.getTargetConstant(AArch64::hsub, MVT::i32)),
8711 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);
8712 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op));
8715 void AArch64TargetLowering::ReplaceNodeResults(
8716 SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
8717 switch (N->getOpcode()) {
8719 llvm_unreachable("Don't know how to custom expand this");
8721 ReplaceBITCASTResults(N, Results, DAG);
8723 case ISD::FP_TO_UINT:
8724 case ISD::FP_TO_SINT:
8725 assert(N->getValueType(0) == MVT::i128 && "unexpected illegal conversion");
8726 // Let normal code take care of it by not adding anything to Results.
8731 bool AArch64TargetLowering::useLoadStackGuardNode() const {
8735 bool AArch64TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
8736 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
8737 // reciprocal if there are three or more FDIVs.
8738 return NumUsers > 2;
8741 TargetLoweringBase::LegalizeTypeAction
8742 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
8743 MVT SVT = VT.getSimpleVT();
8744 // During type legalization, we prefer to widen v1i8, v1i16, v1i32 to v8i8,
8745 // v4i16, v2i32 instead of to promote.
8746 if (SVT == MVT::v1i8 || SVT == MVT::v1i16 || SVT == MVT::v1i32
8747 || SVT == MVT::v1f32)
8748 return TypeWidenVector;
8750 return TargetLoweringBase::getPreferredVectorAction(VT);
8753 // Loads and stores less than 128-bits are already atomic; ones above that
8754 // are doomed anyway, so defer to the default libcall and blame the OS when
8756 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
8757 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
8761 // Loads and stores less than 128-bits are already atomic; ones above that
8762 // are doomed anyway, so defer to the default libcall and blame the OS when
8764 bool AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
8765 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
8769 // For the real atomic operations, we have ldxr/stxr up to 128 bits,
8770 bool AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
8771 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
8775 bool AArch64TargetLowering::hasLoadLinkedStoreConditional() const {
8779 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
8780 AtomicOrdering Ord) const {
8781 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8782 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
8783 bool IsAcquire = isAtLeastAcquire(Ord);
8785 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
8786 // intrinsic must return {i64, i64} and we have to recombine them into a
8787 // single i128 here.
8788 if (ValTy->getPrimitiveSizeInBits() == 128) {
8790 IsAcquire ? Intrinsic::aarch64_ldaxp : Intrinsic::aarch64_ldxp;
8791 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int);
8793 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8794 Value *LoHi = Builder.CreateCall(Ldxr, Addr, "lohi");
8796 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
8797 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
8798 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
8799 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
8800 return Builder.CreateOr(
8801 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
8804 Type *Tys[] = { Addr->getType() };
8806 IsAcquire ? Intrinsic::aarch64_ldaxr : Intrinsic::aarch64_ldxr;
8807 Function *Ldxr = llvm::Intrinsic::getDeclaration(M, Int, Tys);
8809 return Builder.CreateTruncOrBitCast(
8810 Builder.CreateCall(Ldxr, Addr),
8811 cast<PointerType>(Addr->getType())->getElementType());
8814 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
8815 Value *Val, Value *Addr,
8816 AtomicOrdering Ord) const {
8817 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8818 bool IsRelease = isAtLeastRelease(Ord);
8820 // Since the intrinsics must have legal type, the i128 intrinsics take two
8821 // parameters: "i64, i64". We must marshal Val into the appropriate form
8823 if (Val->getType()->getPrimitiveSizeInBits() == 128) {
8825 IsRelease ? Intrinsic::aarch64_stlxp : Intrinsic::aarch64_stxp;
8826 Function *Stxr = Intrinsic::getDeclaration(M, Int);
8827 Type *Int64Ty = Type::getInt64Ty(M->getContext());
8829 Value *Lo = Builder.CreateTrunc(Val, Int64Ty, "lo");
8830 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 64), Int64Ty, "hi");
8831 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
8832 return Builder.CreateCall3(Stxr, Lo, Hi, Addr);
8836 IsRelease ? Intrinsic::aarch64_stlxr : Intrinsic::aarch64_stxr;
8837 Type *Tys[] = { Addr->getType() };
8838 Function *Stxr = Intrinsic::getDeclaration(M, Int, Tys);
8840 return Builder.CreateCall2(
8841 Stxr, Builder.CreateZExtOrBitCast(
8842 Val, Stxr->getFunctionType()->getParamType(0)),