1 //===-- AArch6464FastISel.cpp - AArch64 FastISel implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the AArch64-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // AArch64GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "AArch64Subtarget.h"
18 #include "AArch64TargetMachine.h"
19 #include "MCTargetDesc/AArch64AddressingModes.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/FunctionLoweringInfo.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/GetElementPtrTypeIterator.h"
33 #include "llvm/IR/GlobalAlias.h"
34 #include "llvm/IR/GlobalVariable.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/IR/IntrinsicInst.h"
37 #include "llvm/IR/Operator.h"
38 #include "llvm/Support/CommandLine.h"
43 class AArch64FastISel : public FastISel {
59 const GlobalValue *GV;
62 Address() : Kind(RegBase), Offset(0), GV(nullptr) { Base.Reg = 0; }
63 void setKind(BaseKind K) { Kind = K; }
64 BaseKind getKind() const { return Kind; }
65 bool isRegBase() const { return Kind == RegBase; }
66 bool isFIBase() const { return Kind == FrameIndexBase; }
67 void setReg(unsigned Reg) {
68 assert(isRegBase() && "Invalid base register access!");
71 unsigned getReg() const {
72 assert(isRegBase() && "Invalid base register access!");
75 void setFI(unsigned FI) {
76 assert(isFIBase() && "Invalid base frame index access!");
79 unsigned getFI() const {
80 assert(isFIBase() && "Invalid base frame index access!");
83 void setOffset(int64_t O) { Offset = O; }
84 int64_t getOffset() { return Offset; }
86 void setGlobalValue(const GlobalValue *G) { GV = G; }
87 const GlobalValue *getGlobalValue() { return GV; }
89 bool isValid() { return isFIBase() || (isRegBase() && getReg() != 0); }
92 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
93 /// make the right decision when generating code for different targets.
94 const AArch64Subtarget *Subtarget;
97 bool FastLowerCall(CallLoweringInfo &CLI) override;
98 bool FastLowerIntrinsicCall(const IntrinsicInst *II) override;
101 // Selection routines.
102 bool SelectLoad(const Instruction *I);
103 bool SelectStore(const Instruction *I);
104 bool SelectBranch(const Instruction *I);
105 bool SelectIndirectBr(const Instruction *I);
106 bool SelectCmp(const Instruction *I);
107 bool SelectSelect(const Instruction *I);
108 bool SelectFPExt(const Instruction *I);
109 bool SelectFPTrunc(const Instruction *I);
110 bool SelectFPToInt(const Instruction *I, bool Signed);
111 bool SelectIntToFP(const Instruction *I, bool Signed);
112 bool SelectRem(const Instruction *I, unsigned ISDOpcode);
113 bool SelectRet(const Instruction *I);
114 bool SelectTrunc(const Instruction *I);
115 bool SelectIntExt(const Instruction *I);
116 bool SelectMul(const Instruction *I);
117 bool SelectShift(const Instruction *I, bool IsLeftShift, bool IsArithmetic);
118 bool SelectBitCast(const Instruction *I);
120 // Utility helper routines.
121 bool isTypeLegal(Type *Ty, MVT &VT);
122 bool isLoadStoreTypeLegal(Type *Ty, MVT &VT);
123 bool ComputeAddress(const Value *Obj, Address &Addr);
124 bool ComputeCallAddress(const Value *V, Address &Addr);
125 bool SimplifyAddress(Address &Addr, MVT VT, int64_t ScaleFactor,
127 void AddLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
128 unsigned Flags, bool UseUnscaled);
129 bool IsMemCpySmall(uint64_t Len, unsigned Alignment);
130 bool TryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
132 bool foldXALUIntrinsic(AArch64CC::CondCode &CC, const Instruction *I,
136 bool EmitCmp(Value *Src1Value, Value *Src2Value, bool isZExt);
137 bool EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
138 bool UseUnscaled = false);
139 bool EmitStore(MVT VT, unsigned SrcReg, Address Addr,
140 bool UseUnscaled = false);
141 unsigned EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
142 unsigned Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
143 unsigned Emit_MUL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
144 unsigned Op1, bool Op1IsKill);
145 unsigned Emit_SMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
146 unsigned Op1, bool Op1IsKill);
147 unsigned Emit_UMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
148 unsigned Op1, bool Op1IsKill);
149 unsigned Emit_LSL_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t Imm);
150 unsigned Emit_LSR_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t Imm);
151 unsigned Emit_ASR_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t Imm);
153 unsigned AArch64MaterializeFP(const ConstantFP *CFP, MVT VT);
154 unsigned AArch64MaterializeGV(const GlobalValue *GV);
156 // Call handling routines.
158 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
159 bool ProcessCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
161 bool FinishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
164 // Backend specific FastISel code.
165 unsigned TargetMaterializeAlloca(const AllocaInst *AI) override;
166 unsigned TargetMaterializeConstant(const Constant *C) override;
168 explicit AArch64FastISel(FunctionLoweringInfo &funcInfo,
169 const TargetLibraryInfo *libInfo)
170 : FastISel(funcInfo, libInfo) {
171 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
172 Context = &funcInfo.Fn->getContext();
175 bool TargetSelectInstruction(const Instruction *I) override;
177 #include "AArch64GenFastISel.inc"
180 } // end anonymous namespace
182 #include "AArch64GenCallingConv.inc"
184 CCAssignFn *AArch64FastISel::CCAssignFnForCall(CallingConv::ID CC) const {
185 if (CC == CallingConv::WebKit_JS)
186 return CC_AArch64_WebKit_JS;
187 return Subtarget->isTargetDarwin() ? CC_AArch64_DarwinPCS : CC_AArch64_AAPCS;
190 unsigned AArch64FastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
191 assert(TLI.getValueType(AI->getType(), true) == MVT::i64 &&
192 "Alloca should always return a pointer.");
194 // Don't handle dynamic allocas.
195 if (!FuncInfo.StaticAllocaMap.count(AI))
198 DenseMap<const AllocaInst *, int>::iterator SI =
199 FuncInfo.StaticAllocaMap.find(AI);
201 if (SI != FuncInfo.StaticAllocaMap.end()) {
202 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
203 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
205 .addFrameIndex(SI->second)
214 unsigned AArch64FastISel::AArch64MaterializeFP(const ConstantFP *CFP, MVT VT) {
215 if (VT != MVT::f32 && VT != MVT::f64)
218 const APFloat Val = CFP->getValueAPF();
219 bool is64bit = (VT == MVT::f64);
221 // This checks to see if we can use FMOV instructions to materialize
222 // a constant, otherwise we have to materialize via the constant pool.
223 if (TLI.isFPImmLegal(Val, VT)) {
227 Imm = AArch64_AM::getFP64Imm(Val);
228 Opc = AArch64::FMOVDi;
230 Imm = AArch64_AM::getFP32Imm(Val);
231 Opc = AArch64::FMOVSi;
233 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
234 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
239 // Materialize via constant pool. MachineConstantPool wants an explicit
241 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
243 Align = DL.getTypeAllocSize(CFP->getType());
245 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
246 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
247 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
248 ADRPReg).addConstantPoolIndex(Idx, 0, AArch64II::MO_PAGE);
250 unsigned Opc = is64bit ? AArch64::LDRDui : AArch64::LDRSui;
251 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
252 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
254 .addConstantPoolIndex(Idx, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
258 unsigned AArch64FastISel::AArch64MaterializeGV(const GlobalValue *GV) {
259 // We can't handle thread-local variables quickly yet.
260 if (GV->isThreadLocal())
263 // MachO still uses GOT for large code-model accesses, but ELF requires
264 // movz/movk sequences, which FastISel doesn't handle yet.
265 if (TM.getCodeModel() != CodeModel::Small && !Subtarget->isTargetMachO())
268 unsigned char OpFlags = Subtarget->ClassifyGlobalReference(GV, TM);
270 EVT DestEVT = TLI.getValueType(GV->getType(), true);
271 if (!DestEVT.isSimple())
274 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
277 if (OpFlags & AArch64II::MO_GOT) {
279 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
281 .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGE);
283 ResultReg = createResultReg(&AArch64::GPR64RegClass);
284 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui),
287 .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF |
291 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
292 ADRPReg).addGlobalAddress(GV, 0, AArch64II::MO_PAGE);
294 ResultReg = createResultReg(&AArch64::GPR64spRegClass);
295 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
298 .addGlobalAddress(GV, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC)
304 unsigned AArch64FastISel::TargetMaterializeConstant(const Constant *C) {
305 EVT CEVT = TLI.getValueType(C->getType(), true);
307 // Only handle simple types.
308 if (!CEVT.isSimple())
310 MVT VT = CEVT.getSimpleVT();
312 // FIXME: Handle ConstantInt.
313 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
314 return AArch64MaterializeFP(CFP, VT);
315 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
316 return AArch64MaterializeGV(GV);
321 // Computes the address to get to an object.
322 bool AArch64FastISel::ComputeAddress(const Value *Obj, Address &Addr) {
323 const User *U = nullptr;
324 unsigned Opcode = Instruction::UserOp1;
325 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
326 // Don't walk into other basic blocks unless the object is an alloca from
327 // another block, otherwise it may not have a virtual register assigned.
328 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
329 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
330 Opcode = I->getOpcode();
333 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
334 Opcode = C->getOpcode();
338 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
339 if (Ty->getAddressSpace() > 255)
340 // Fast instruction selection doesn't support the special
347 case Instruction::BitCast: {
348 // Look through bitcasts.
349 return ComputeAddress(U->getOperand(0), Addr);
351 case Instruction::IntToPtr: {
352 // Look past no-op inttoptrs.
353 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
354 return ComputeAddress(U->getOperand(0), Addr);
357 case Instruction::PtrToInt: {
358 // Look past no-op ptrtoints.
359 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
360 return ComputeAddress(U->getOperand(0), Addr);
363 case Instruction::GetElementPtr: {
364 Address SavedAddr = Addr;
365 uint64_t TmpOffset = Addr.getOffset();
367 // Iterate through the GEP folding the constants into offsets where
369 gep_type_iterator GTI = gep_type_begin(U);
370 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
372 const Value *Op = *i;
373 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
374 const StructLayout *SL = DL.getStructLayout(STy);
375 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
376 TmpOffset += SL->getElementOffset(Idx);
378 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
380 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
381 // Constant-offset addressing.
382 TmpOffset += CI->getSExtValue() * S;
385 if (canFoldAddIntoGEP(U, Op)) {
386 // A compatible add with a constant operand. Fold the constant.
388 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
389 TmpOffset += CI->getSExtValue() * S;
390 // Iterate on the other operand.
391 Op = cast<AddOperator>(Op)->getOperand(0);
395 goto unsupported_gep;
400 // Try to grab the base operand now.
401 Addr.setOffset(TmpOffset);
402 if (ComputeAddress(U->getOperand(0), Addr))
405 // We failed, restore everything and try the other options.
411 case Instruction::Alloca: {
412 const AllocaInst *AI = cast<AllocaInst>(Obj);
413 DenseMap<const AllocaInst *, int>::iterator SI =
414 FuncInfo.StaticAllocaMap.find(AI);
415 if (SI != FuncInfo.StaticAllocaMap.end()) {
416 Addr.setKind(Address::FrameIndexBase);
417 Addr.setFI(SI->second);
422 case Instruction::Add:
423 // Adds of constants are common and easy enough.
424 if (const ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
425 Addr.setOffset(Addr.getOffset() + (uint64_t)CI->getSExtValue());
426 return ComputeAddress(U->getOperand(0), Addr);
431 // Try to get this in a register if nothing else has worked.
433 Addr.setReg(getRegForValue(Obj));
434 return Addr.isValid();
437 bool AArch64FastISel::ComputeCallAddress(const Value *V, Address &Addr) {
438 const User *U = nullptr;
439 unsigned Opcode = Instruction::UserOp1;
442 if (const auto *I = dyn_cast<Instruction>(V)) {
443 Opcode = I->getOpcode();
445 InMBB = I->getParent() == FuncInfo.MBB->getBasicBlock();
446 } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
447 Opcode = C->getOpcode();
453 case Instruction::BitCast:
454 // Look past bitcasts if its operand is in the same BB.
456 return ComputeCallAddress(U->getOperand(0), Addr);
458 case Instruction::IntToPtr:
459 // Look past no-op inttoptrs if its operand is in the same BB.
461 TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
462 return ComputeCallAddress(U->getOperand(0), Addr);
464 case Instruction::PtrToInt:
465 // Look past no-op ptrtoints if its operand is in the same BB.
467 TLI.getValueType(U->getType()) == TLI.getPointerTy())
468 return ComputeCallAddress(U->getOperand(0), Addr);
472 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
473 Addr.setGlobalValue(GV);
477 // If all else fails, try to materialize the value in a register.
478 if (!Addr.getGlobalValue()) {
479 Addr.setReg(getRegForValue(V));
480 return Addr.getReg() != 0;
487 bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) {
488 EVT evt = TLI.getValueType(Ty, true);
490 // Only handle simple types.
491 if (evt == MVT::Other || !evt.isSimple())
493 VT = evt.getSimpleVT();
495 // This is a legal type, but it's not something we handle in fast-isel.
499 // Handle all other legal types, i.e. a register that will directly hold this
501 return TLI.isTypeLegal(VT);
504 bool AArch64FastISel::isLoadStoreTypeLegal(Type *Ty, MVT &VT) {
505 if (isTypeLegal(Ty, VT))
508 // If this is a type than can be sign or zero-extended to a basic operation
509 // go ahead and accept it now. For stores, this reflects truncation.
510 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
516 bool AArch64FastISel::SimplifyAddress(Address &Addr, MVT VT,
517 int64_t ScaleFactor, bool UseUnscaled) {
518 bool needsLowering = false;
519 int64_t Offset = Addr.getOffset();
520 switch (VT.SimpleTy) {
531 // Using scaled, 12-bit, unsigned immediate offsets.
532 needsLowering = ((Offset & 0xfff) != Offset);
534 // Using unscaled, 9-bit, signed immediate offsets.
535 needsLowering = (Offset > 256 || Offset < -256);
539 //If this is a stack pointer and the offset needs to be simplified then put
540 // the alloca address into a register, set the base type back to register and
541 // continue. This should almost never happen.
542 if (needsLowering && Addr.getKind() == Address::FrameIndexBase) {
543 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
544 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
546 .addFrameIndex(Addr.getFI())
549 Addr.setKind(Address::RegBase);
550 Addr.setReg(ResultReg);
553 // Since the offset is too large for the load/store instruction get the
554 // reg+offset into a register.
556 uint64_t UnscaledOffset = Addr.getOffset() * ScaleFactor;
557 unsigned ResultReg = FastEmit_ri_(MVT::i64, ISD::ADD, Addr.getReg(), false,
558 UnscaledOffset, MVT::i64);
561 Addr.setReg(ResultReg);
567 void AArch64FastISel::AddLoadStoreOperands(Address &Addr,
568 const MachineInstrBuilder &MIB,
569 unsigned Flags, bool UseUnscaled) {
570 int64_t Offset = Addr.getOffset();
571 // Frame base works a bit differently. Handle it separately.
572 if (Addr.getKind() == Address::FrameIndexBase) {
573 int FI = Addr.getFI();
574 // FIXME: We shouldn't be using getObjectSize/getObjectAlignment. The size
575 // and alignment should be based on the VT.
576 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
577 MachinePointerInfo::getFixedStack(FI, Offset), Flags,
578 MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
579 // Now add the rest of the operands.
580 MIB.addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
582 // Now add the rest of the operands.
583 MIB.addReg(Addr.getReg());
588 bool AArch64FastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
590 // Negative offsets require unscaled, 9-bit, signed immediate offsets.
591 // Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
592 if (!UseUnscaled && Addr.getOffset() < 0)
596 const TargetRegisterClass *RC;
598 int64_t ScaleFactor = 0;
599 switch (VT.SimpleTy) {
604 // Intentional fall-through.
606 Opc = UseUnscaled ? AArch64::LDURBBi : AArch64::LDRBBui;
607 RC = &AArch64::GPR32RegClass;
611 Opc = UseUnscaled ? AArch64::LDURHHi : AArch64::LDRHHui;
612 RC = &AArch64::GPR32RegClass;
616 Opc = UseUnscaled ? AArch64::LDURWi : AArch64::LDRWui;
617 RC = &AArch64::GPR32RegClass;
621 Opc = UseUnscaled ? AArch64::LDURXi : AArch64::LDRXui;
622 RC = &AArch64::GPR64RegClass;
626 Opc = UseUnscaled ? AArch64::LDURSi : AArch64::LDRSui;
627 RC = TLI.getRegClassFor(VT);
631 Opc = UseUnscaled ? AArch64::LDURDi : AArch64::LDRDui;
632 RC = TLI.getRegClassFor(VT);
638 int64_t Offset = Addr.getOffset();
639 if (Offset & (ScaleFactor - 1))
640 // Retry using an unscaled, 9-bit, signed immediate offset.
641 return EmitLoad(VT, ResultReg, Addr, /*UseUnscaled*/ true);
643 Addr.setOffset(Offset / ScaleFactor);
646 // Simplify this down to something we can handle.
647 if (!SimplifyAddress(Addr, VT, UseUnscaled ? 1 : ScaleFactor, UseUnscaled))
650 // Create the base instruction, then add the operands.
651 ResultReg = createResultReg(RC);
652 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
653 TII.get(Opc), ResultReg);
654 AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOLoad, UseUnscaled);
656 // Loading an i1 requires special handling.
658 MRI.constrainRegClass(ResultReg, &AArch64::GPR32RegClass);
659 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
660 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
663 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
669 bool AArch64FastISel::SelectLoad(const Instruction *I) {
671 // Verify we have a legal type before going any further. Currently, we handle
672 // simple types that will directly fit in a register (i32/f32/i64/f64) or
673 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
674 if (!isLoadStoreTypeLegal(I->getType(), VT) || cast<LoadInst>(I)->isAtomic())
677 // See if we can handle this address.
679 if (!ComputeAddress(I->getOperand(0), Addr))
683 if (!EmitLoad(VT, ResultReg, Addr))
686 UpdateValueMap(I, ResultReg);
690 bool AArch64FastISel::EmitStore(MVT VT, unsigned SrcReg, Address Addr,
692 // Negative offsets require unscaled, 9-bit, signed immediate offsets.
693 // Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
694 if (!UseUnscaled && Addr.getOffset() < 0)
699 int64_t ScaleFactor = 0;
700 // Using scaled, 12-bit, unsigned immediate offsets.
701 switch (VT.SimpleTy) {
707 StrOpc = UseUnscaled ? AArch64::STURBBi : AArch64::STRBBui;
711 StrOpc = UseUnscaled ? AArch64::STURHHi : AArch64::STRHHui;
715 StrOpc = UseUnscaled ? AArch64::STURWi : AArch64::STRWui;
719 StrOpc = UseUnscaled ? AArch64::STURXi : AArch64::STRXui;
723 StrOpc = UseUnscaled ? AArch64::STURSi : AArch64::STRSui;
727 StrOpc = UseUnscaled ? AArch64::STURDi : AArch64::STRDui;
733 int64_t Offset = Addr.getOffset();
734 if (Offset & (ScaleFactor - 1))
735 // Retry using an unscaled, 9-bit, signed immediate offset.
736 return EmitStore(VT, SrcReg, Addr, /*UseUnscaled*/ true);
738 Addr.setOffset(Offset / ScaleFactor);
741 // Simplify this down to something we can handle.
742 if (!SimplifyAddress(Addr, VT, UseUnscaled ? 1 : ScaleFactor, UseUnscaled))
745 // Storing an i1 requires special handling.
747 MRI.constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
748 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
749 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
752 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
755 // Create the base instruction, then add the operands.
756 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
757 TII.get(StrOpc)).addReg(SrcReg);
758 AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOStore, UseUnscaled);
762 bool AArch64FastISel::SelectStore(const Instruction *I) {
764 Value *Op0 = I->getOperand(0);
765 // Verify we have a legal type before going any further. Currently, we handle
766 // simple types that will directly fit in a register (i32/f32/i64/f64) or
767 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
768 if (!isLoadStoreTypeLegal(Op0->getType(), VT) ||
769 cast<StoreInst>(I)->isAtomic())
772 // Get the value to be stored into a register.
773 unsigned SrcReg = getRegForValue(Op0);
777 // See if we can handle this address.
779 if (!ComputeAddress(I->getOperand(1), Addr))
782 if (!EmitStore(VT, SrcReg, Addr))
787 static AArch64CC::CondCode getCompareCC(CmpInst::Predicate Pred) {
789 case CmpInst::FCMP_ONE:
790 case CmpInst::FCMP_UEQ:
792 // AL is our "false" for now. The other two need more compares.
793 return AArch64CC::AL;
794 case CmpInst::ICMP_EQ:
795 case CmpInst::FCMP_OEQ:
796 return AArch64CC::EQ;
797 case CmpInst::ICMP_SGT:
798 case CmpInst::FCMP_OGT:
799 return AArch64CC::GT;
800 case CmpInst::ICMP_SGE:
801 case CmpInst::FCMP_OGE:
802 return AArch64CC::GE;
803 case CmpInst::ICMP_UGT:
804 case CmpInst::FCMP_UGT:
805 return AArch64CC::HI;
806 case CmpInst::FCMP_OLT:
807 return AArch64CC::MI;
808 case CmpInst::ICMP_ULE:
809 case CmpInst::FCMP_OLE:
810 return AArch64CC::LS;
811 case CmpInst::FCMP_ORD:
812 return AArch64CC::VC;
813 case CmpInst::FCMP_UNO:
814 return AArch64CC::VS;
815 case CmpInst::FCMP_UGE:
816 return AArch64CC::PL;
817 case CmpInst::ICMP_SLT:
818 case CmpInst::FCMP_ULT:
819 return AArch64CC::LT;
820 case CmpInst::ICMP_SLE:
821 case CmpInst::FCMP_ULE:
822 return AArch64CC::LE;
823 case CmpInst::FCMP_UNE:
824 case CmpInst::ICMP_NE:
825 return AArch64CC::NE;
826 case CmpInst::ICMP_UGE:
827 return AArch64CC::HS;
828 case CmpInst::ICMP_ULT:
829 return AArch64CC::LO;
833 bool AArch64FastISel::SelectBranch(const Instruction *I) {
834 const BranchInst *BI = cast<BranchInst>(I);
835 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
836 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
838 AArch64CC::CondCode CC = AArch64CC::NE;
839 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
840 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
841 // We may not handle every CC for now.
842 CC = getCompareCC(CI->getPredicate());
843 if (CC == AArch64CC::AL)
847 if (!EmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
851 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
855 // Obtain the branch weight and add the TrueBB to the successor list.
856 uint32_t BranchWeight = 0;
858 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
859 TBB->getBasicBlock());
860 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
862 FastEmitBranch(FBB, DbgLoc);
865 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
867 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
868 (isLoadStoreTypeLegal(TI->getOperand(0)->getType(), SrcVT))) {
869 unsigned CondReg = getRegForValue(TI->getOperand(0));
873 // Issue an extract_subreg to get the lower 32-bits.
874 if (SrcVT == MVT::i64)
875 CondReg = FastEmitInst_extractsubreg(MVT::i32, CondReg, /*Kill=*/true,
878 MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass);
879 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
880 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
881 TII.get(AArch64::ANDWri), ANDReg)
883 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
884 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
885 TII.get(AArch64::SUBSWri))
891 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
895 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
899 // Obtain the branch weight and add the TrueBB to the successor list.
900 uint32_t BranchWeight = 0;
902 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
903 TBB->getBasicBlock());
904 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
906 FastEmitBranch(FBB, DbgLoc);
909 } else if (const ConstantInt *CI =
910 dyn_cast<ConstantInt>(BI->getCondition())) {
911 uint64_t Imm = CI->getZExtValue();
912 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
913 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::B))
916 // Obtain the branch weight and add the target to the successor list.
917 uint32_t BranchWeight = 0;
919 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
920 Target->getBasicBlock());
921 FuncInfo.MBB->addSuccessor(Target, BranchWeight);
923 } else if (foldXALUIntrinsic(CC, I, BI->getCondition())) {
924 // Fake request the condition, otherwise the intrinsic might be completely
926 unsigned CondReg = getRegForValue(BI->getCondition());
931 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
935 // Obtain the branch weight and add the TrueBB to the successor list.
936 uint32_t BranchWeight = 0;
938 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
939 TBB->getBasicBlock());
940 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
942 FastEmitBranch(FBB, DbgLoc);
946 unsigned CondReg = getRegForValue(BI->getCondition());
950 // We've been divorced from our compare! Our block was split, and
951 // now our compare lives in a predecessor block. We musn't
952 // re-compare here, as the children of the compare aren't guaranteed
953 // live across the block boundary (we *could* check for this).
954 // Regardless, the compare has been done in the predecessor block,
955 // and it left a value for us in a virtual register. Ergo, we test
956 // the one-bit value left in the virtual register.
957 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SUBSWri),
963 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
968 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
972 // Obtain the branch weight and add the TrueBB to the successor list.
973 uint32_t BranchWeight = 0;
975 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
976 TBB->getBasicBlock());
977 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
979 FastEmitBranch(FBB, DbgLoc);
983 bool AArch64FastISel::SelectIndirectBr(const Instruction *I) {
984 const IndirectBrInst *BI = cast<IndirectBrInst>(I);
985 unsigned AddrReg = getRegForValue(BI->getOperand(0));
989 // Emit the indirect branch.
990 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BR))
993 // Make sure the CFG is up-to-date.
994 for (unsigned i = 0, e = BI->getNumSuccessors(); i != e; ++i)
995 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[BI->getSuccessor(i)]);
1000 bool AArch64FastISel::EmitCmp(Value *Src1Value, Value *Src2Value, bool isZExt) {
1001 Type *Ty = Src1Value->getType();
1002 EVT SrcEVT = TLI.getValueType(Ty, true);
1003 if (!SrcEVT.isSimple())
1005 MVT SrcVT = SrcEVT.getSimpleVT();
1007 // Check to see if the 2nd operand is a constant that we can encode directly
1010 bool UseImm = false;
1011 bool isNegativeImm = false;
1012 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1013 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
1014 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
1015 const APInt &CIVal = ConstInt->getValue();
1017 Imm = (isZExt) ? CIVal.getZExtValue() : CIVal.getSExtValue();
1018 if (CIVal.isNegative()) {
1019 isNegativeImm = true;
1022 // FIXME: We can handle more immediates using shifts.
1023 UseImm = ((Imm & 0xfff) == Imm);
1025 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1026 if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1027 if (ConstFP->isZero() && !ConstFP->isNegative())
1034 bool needsExt = false;
1035 switch (SrcVT.SimpleTy) {
1042 // Intentional fall-through.
1044 ZReg = AArch64::WZR;
1046 CmpOpc = isNegativeImm ? AArch64::ADDSWri : AArch64::SUBSWri;
1048 CmpOpc = AArch64::SUBSWrr;
1051 ZReg = AArch64::XZR;
1053 CmpOpc = isNegativeImm ? AArch64::ADDSXri : AArch64::SUBSXri;
1055 CmpOpc = AArch64::SUBSXrr;
1059 CmpOpc = UseImm ? AArch64::FCMPSri : AArch64::FCMPSrr;
1063 CmpOpc = UseImm ? AArch64::FCMPDri : AArch64::FCMPDrr;
1067 unsigned SrcReg1 = getRegForValue(Src1Value);
1073 SrcReg2 = getRegForValue(Src2Value);
1078 // We have i1, i8, or i16, we need to either zero extend or sign extend.
1080 SrcReg1 = EmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1084 SrcReg2 = EmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1092 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
1098 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
1104 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
1107 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc))
1114 bool AArch64FastISel::SelectCmp(const Instruction *I) {
1115 const CmpInst *CI = cast<CmpInst>(I);
1117 // We may not handle every CC for now.
1118 AArch64CC::CondCode CC = getCompareCC(CI->getPredicate());
1119 if (CC == AArch64CC::AL)
1123 if (!EmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1126 // Now set a register based on the comparison.
1127 AArch64CC::CondCode invertedCC = getInvertedCondCode(CC);
1128 unsigned ResultReg = createResultReg(&AArch64::GPR32RegClass);
1129 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
1131 .addReg(AArch64::WZR)
1132 .addReg(AArch64::WZR)
1133 .addImm(invertedCC);
1135 UpdateValueMap(I, ResultReg);
1139 bool AArch64FastISel::SelectSelect(const Instruction *I) {
1140 const SelectInst *SI = cast<SelectInst>(I);
1142 EVT DestEVT = TLI.getValueType(SI->getType(), true);
1143 if (!DestEVT.isSimple())
1146 MVT DestVT = DestEVT.getSimpleVT();
1147 if (DestVT != MVT::i32 && DestVT != MVT::i64 && DestVT != MVT::f32 &&
1152 switch (DestVT.SimpleTy) {
1153 default: return false;
1154 case MVT::i32: SelectOpc = AArch64::CSELWr; break;
1155 case MVT::i64: SelectOpc = AArch64::CSELXr; break;
1156 case MVT::f32: SelectOpc = AArch64::FCSELSrrr; break;
1157 case MVT::f64: SelectOpc = AArch64::FCSELDrrr; break;
1160 const Value *Cond = SI->getCondition();
1161 bool NeedTest = true;
1162 AArch64CC::CondCode CC = AArch64CC::NE;
1163 if (foldXALUIntrinsic(CC, I, Cond))
1166 unsigned CondReg = getRegForValue(Cond);
1169 bool CondIsKill = hasTrivialKill(Cond);
1172 MRI.constrainRegClass(CondReg, &AArch64::GPR32RegClass);
1173 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
1174 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
1176 .addReg(CondReg, getKillRegState(CondIsKill))
1177 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
1179 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SUBSWri))
1186 unsigned TrueReg = getRegForValue(SI->getTrueValue());
1187 bool TrueIsKill = hasTrivialKill(SI->getTrueValue());
1189 unsigned FalseReg = getRegForValue(SI->getFalseValue());
1190 bool FalseIsKill = hasTrivialKill(SI->getFalseValue());
1192 if (!TrueReg || !FalseReg)
1195 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1196 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SelectOpc),
1198 .addReg(TrueReg, getKillRegState(TrueIsKill))
1199 .addReg(FalseReg, getKillRegState(FalseIsKill))
1202 UpdateValueMap(I, ResultReg);
1206 bool AArch64FastISel::SelectFPExt(const Instruction *I) {
1207 Value *V = I->getOperand(0);
1208 if (!I->getType()->isDoubleTy() || !V->getType()->isFloatTy())
1211 unsigned Op = getRegForValue(V);
1215 unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass);
1216 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTDSr),
1217 ResultReg).addReg(Op);
1218 UpdateValueMap(I, ResultReg);
1222 bool AArch64FastISel::SelectFPTrunc(const Instruction *I) {
1223 Value *V = I->getOperand(0);
1224 if (!I->getType()->isFloatTy() || !V->getType()->isDoubleTy())
1227 unsigned Op = getRegForValue(V);
1231 unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass);
1232 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTSDr),
1233 ResultReg).addReg(Op);
1234 UpdateValueMap(I, ResultReg);
1238 // FPToUI and FPToSI
1239 bool AArch64FastISel::SelectFPToInt(const Instruction *I, bool Signed) {
1241 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
1244 unsigned SrcReg = getRegForValue(I->getOperand(0));
1248 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
1249 if (SrcVT == MVT::f128)
1253 if (SrcVT == MVT::f64) {
1255 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
1257 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
1260 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
1262 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
1264 unsigned ResultReg = createResultReg(
1265 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);
1266 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1268 UpdateValueMap(I, ResultReg);
1272 bool AArch64FastISel::SelectIntToFP(const Instruction *I, bool Signed) {
1274 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
1276 assert ((DestVT == MVT::f32 || DestVT == MVT::f64) &&
1277 "Unexpected value type.");
1279 unsigned SrcReg = getRegForValue(I->getOperand(0));
1283 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
1285 // Handle sign-extension.
1286 if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) {
1288 EmitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);
1293 MRI.constrainRegClass(SrcReg, SrcVT == MVT::i64 ? &AArch64::GPR64RegClass
1294 : &AArch64::GPR32RegClass);
1297 if (SrcVT == MVT::i64) {
1299 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;
1301 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;
1304 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;
1306 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;
1309 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
1310 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1312 UpdateValueMap(I, ResultReg);
1316 bool AArch64FastISel::ProcessCallArgs(CallLoweringInfo &CLI,
1317 SmallVectorImpl<MVT> &OutVTs,
1318 unsigned &NumBytes) {
1319 CallingConv::ID CC = CLI.CallConv;
1320 SmallVector<CCValAssign, 16> ArgLocs;
1321 CCState CCInfo(CC, false, *FuncInfo.MF, TM, ArgLocs, *Context);
1322 CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1324 // Get a count of how many bytes are to be pushed on the stack.
1325 NumBytes = CCInfo.getNextStackOffset();
1327 // Issue CALLSEQ_START
1328 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1329 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
1332 // Process the args.
1333 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1334 CCValAssign &VA = ArgLocs[i];
1335 const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1336 MVT ArgVT = OutVTs[VA.getValNo()];
1338 unsigned ArgReg = getRegForValue(ArgVal);
1342 // Handle arg promotion: SExt, ZExt, AExt.
1343 switch (VA.getLocInfo()) {
1344 case CCValAssign::Full:
1346 case CCValAssign::SExt: {
1347 MVT DestVT = VA.getLocVT();
1349 ArgReg = EmitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1354 case CCValAssign::AExt:
1355 // Intentional fall-through.
1356 case CCValAssign::ZExt: {
1357 MVT DestVT = VA.getLocVT();
1359 ArgReg = EmitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1365 llvm_unreachable("Unknown arg promotion!");
1368 // Now copy/store arg to correct locations.
1369 if (VA.isRegLoc() && !VA.needsCustom()) {
1370 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1371 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1372 CLI.OutRegs.push_back(VA.getLocReg());
1373 } else if (VA.needsCustom()) {
1374 // FIXME: Handle custom args.
1377 assert(VA.isMemLoc() && "Assuming store on stack.");
1379 // Don't emit stores for undef values.
1380 if (isa<UndefValue>(ArgVal))
1383 // Need to store on the stack.
1384 unsigned ArgSize = (ArgVT.getSizeInBits() + 7) / 8;
1386 unsigned BEAlign = 0;
1387 if (ArgSize < 8 && !Subtarget->isLittleEndian())
1388 BEAlign = 8 - ArgSize;
1391 Addr.setKind(Address::RegBase);
1392 Addr.setReg(AArch64::SP);
1393 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1395 if (!EmitStore(ArgVT, ArgReg, Addr))
1402 bool AArch64FastISel::FinishCall(CallLoweringInfo &CLI, MVT RetVT,
1403 unsigned NumBytes) {
1404 CallingConv::ID CC = CLI.CallConv;
1406 // Issue CALLSEQ_END
1407 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
1408 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
1409 .addImm(NumBytes).addImm(0);
1411 // Now the return value.
1412 if (RetVT != MVT::isVoid) {
1413 SmallVector<CCValAssign, 16> RVLocs;
1414 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
1415 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC));
1417 // Only handle a single return value.
1418 if (RVLocs.size() != 1)
1421 // Copy all of the result registers out of their specified physreg.
1422 MVT CopyVT = RVLocs[0].getValVT();
1423 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1424 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1425 TII.get(TargetOpcode::COPY), ResultReg)
1426 .addReg(RVLocs[0].getLocReg());
1427 CLI.InRegs.push_back(RVLocs[0].getLocReg());
1429 CLI.ResultReg = ResultReg;
1430 CLI.NumResultRegs = 1;
1436 bool AArch64FastISel::FastLowerCall(CallLoweringInfo &CLI) {
1437 CallingConv::ID CC = CLI.CallConv;
1438 bool IsVarArg = CLI.IsVarArg;
1439 const Value *Callee = CLI.Callee;
1440 const char *SymName = CLI.SymName;
1442 CodeModel::Model CM = TM.getCodeModel();
1443 // Only support the small and large code model.
1444 if (CM != CodeModel::Small && CM != CodeModel::Large)
1447 // FIXME: Add large code model support for ELF.
1448 if (CM == CodeModel::Large && !Subtarget->isTargetMachO())
1451 // Let SDISel handle vararg functions.
1455 // FIXME: Only handle *simple* calls for now.
1457 if (CLI.RetTy->isVoidTy())
1458 RetVT = MVT::isVoid;
1459 else if (!isTypeLegal(CLI.RetTy, RetVT))
1462 for (auto Flag : CLI.OutFlags)
1463 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1466 // Set up the argument vectors.
1467 SmallVector<MVT, 16> OutVTs;
1468 OutVTs.reserve(CLI.OutVals.size());
1470 for (auto *Val : CLI.OutVals) {
1472 if (!isTypeLegal(Val->getType(), VT) &&
1473 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1476 // We don't handle vector parameters yet.
1477 if (VT.isVector() || VT.getSizeInBits() > 64)
1480 OutVTs.push_back(VT);
1484 if (!ComputeCallAddress(Callee, Addr))
1487 // Handle the arguments now that we've gotten them.
1489 if (!ProcessCallArgs(CLI, OutVTs, NumBytes))
1493 MachineInstrBuilder MIB;
1494 if (CM == CodeModel::Small) {
1495 unsigned CallOpc = Addr.getReg() ? AArch64::BLR : AArch64::BL;
1496 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CallOpc));
1498 MIB.addExternalSymbol(SymName, 0);
1499 else if (Addr.getGlobalValue())
1500 MIB.addGlobalAddress(Addr.getGlobalValue(), 0, 0);
1501 else if (Addr.getReg())
1502 MIB.addReg(Addr.getReg());
1506 unsigned CallReg = 0;
1508 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
1509 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
1511 .addExternalSymbol(SymName, AArch64II::MO_GOT | AArch64II::MO_PAGE);
1513 CallReg = createResultReg(&AArch64::GPR64RegClass);
1514 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui),
1517 .addExternalSymbol(SymName, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF |
1519 } else if (Addr.getGlobalValue()) {
1520 CallReg = AArch64MaterializeGV(Addr.getGlobalValue());
1521 } else if (Addr.getReg())
1522 CallReg = Addr.getReg();
1527 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1528 TII.get(AArch64::BLR)).addReg(CallReg);
1531 // Add implicit physical register uses to the call.
1532 for (auto Reg : CLI.OutRegs)
1533 MIB.addReg(Reg, RegState::Implicit);
1535 // Add a register mask with the call-preserved registers.
1536 // Proper defs for return values will be added by setPhysRegsDeadExcept().
1537 MIB.addRegMask(TRI.getCallPreservedMask(CC));
1541 // Finish off the call including any return values.
1542 return FinishCall(CLI, RetVT, NumBytes);
1545 bool AArch64FastISel::IsMemCpySmall(uint64_t Len, unsigned Alignment) {
1547 return Len / Alignment <= 4;
1552 bool AArch64FastISel::TryEmitSmallMemCpy(Address Dest, Address Src,
1553 uint64_t Len, unsigned Alignment) {
1554 // Make sure we don't bloat code by inlining very large memcpy's.
1555 if (!IsMemCpySmall(Len, Alignment))
1558 int64_t UnscaledOffset = 0;
1559 Address OrigDest = Dest;
1560 Address OrigSrc = Src;
1564 if (!Alignment || Alignment >= 8) {
1575 // Bound based on alignment.
1576 if (Len >= 4 && Alignment == 4)
1578 else if (Len >= 2 && Alignment == 2)
1587 RV = EmitLoad(VT, ResultReg, Src);
1591 RV = EmitStore(VT, ResultReg, Dest);
1595 int64_t Size = VT.getSizeInBits() / 8;
1597 UnscaledOffset += Size;
1599 // We need to recompute the unscaled offset for each iteration.
1600 Dest.setOffset(OrigDest.getOffset() + UnscaledOffset);
1601 Src.setOffset(OrigSrc.getOffset() + UnscaledOffset);
1607 /// \brief Check if it is possible to fold the condition from the XALU intrinsic
1608 /// into the user. The condition code will only be updated on success.
1609 bool AArch64FastISel::foldXALUIntrinsic(AArch64CC::CondCode &CC,
1610 const Instruction *I,
1611 const Value *Cond) {
1612 if (!isa<ExtractValueInst>(Cond))
1615 const auto *EV = cast<ExtractValueInst>(Cond);
1616 if (!isa<IntrinsicInst>(EV->getAggregateOperand()))
1619 const auto *II = cast<IntrinsicInst>(EV->getAggregateOperand());
1621 const Function *Callee = II->getCalledFunction();
1623 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(0U);
1624 if (!isTypeLegal(RetTy, RetVT))
1627 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1630 AArch64CC::CondCode TmpCC;
1631 switch (II->getIntrinsicID()) {
1632 default: return false;
1633 case Intrinsic::sadd_with_overflow:
1634 case Intrinsic::ssub_with_overflow: TmpCC = AArch64CC::VS; break;
1635 case Intrinsic::uadd_with_overflow: TmpCC = AArch64CC::HS; break;
1636 case Intrinsic::usub_with_overflow: TmpCC = AArch64CC::LO; break;
1637 case Intrinsic::smul_with_overflow:
1638 case Intrinsic::umul_with_overflow: TmpCC = AArch64CC::NE; break;
1641 // Check if both instructions are in the same basic block.
1642 if (II->getParent() != I->getParent())
1645 // Make sure nothing is in the way
1646 BasicBlock::const_iterator Start = I;
1647 BasicBlock::const_iterator End = II;
1648 for (auto Itr = std::prev(Start); Itr != End; --Itr) {
1649 // We only expect extractvalue instructions between the intrinsic and the
1650 // instruction to be selected.
1651 if (!isa<ExtractValueInst>(Itr))
1654 // Check that the extractvalue operand comes from the intrinsic.
1655 const auto *EVI = cast<ExtractValueInst>(Itr);
1656 if (EVI->getAggregateOperand() != II)
1664 bool AArch64FastISel::FastLowerIntrinsicCall(const IntrinsicInst *II) {
1665 // FIXME: Handle more intrinsics.
1666 switch (II->getIntrinsicID()) {
1667 default: return false;
1668 case Intrinsic::frameaddress: {
1669 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
1670 MFI->setFrameAddressIsTaken(true);
1672 const AArch64RegisterInfo *RegInfo =
1673 static_cast<const AArch64RegisterInfo *>(
1674 TM.getSubtargetImpl()->getRegisterInfo());
1675 unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
1676 unsigned SrcReg = FramePtr;
1678 // Recursively load frame address
1684 unsigned Depth = cast<ConstantInt>(II->getOperand(0))->getZExtValue();
1686 DestReg = createResultReg(&AArch64::GPR64RegClass);
1687 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1688 TII.get(AArch64::LDRXui), DestReg)
1689 .addReg(SrcReg).addImm(0);
1693 UpdateValueMap(II, SrcReg);
1696 case Intrinsic::memcpy:
1697 case Intrinsic::memmove: {
1698 const auto *MTI = cast<MemTransferInst>(II);
1699 // Don't handle volatile.
1700 if (MTI->isVolatile())
1703 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
1704 // we would emit dead code because we don't currently handle memmoves.
1705 bool IsMemCpy = (II->getIntrinsicID() == Intrinsic::memcpy);
1706 if (isa<ConstantInt>(MTI->getLength()) && IsMemCpy) {
1707 // Small memcpy's are common enough that we want to do them without a call
1709 uint64_t Len = cast<ConstantInt>(MTI->getLength())->getZExtValue();
1710 unsigned Alignment = MTI->getAlignment();
1711 if (IsMemCpySmall(Len, Alignment)) {
1713 if (!ComputeAddress(MTI->getRawDest(), Dest) ||
1714 !ComputeAddress(MTI->getRawSource(), Src))
1716 if (TryEmitSmallMemCpy(Dest, Src, Len, Alignment))
1721 if (!MTI->getLength()->getType()->isIntegerTy(64))
1724 if (MTI->getSourceAddressSpace() > 255 || MTI->getDestAddressSpace() > 255)
1725 // Fast instruction selection doesn't support the special
1729 const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
1730 return LowerCallTo(II, IntrMemName, II->getNumArgOperands() - 2);
1732 case Intrinsic::memset: {
1733 const MemSetInst *MSI = cast<MemSetInst>(II);
1734 // Don't handle volatile.
1735 if (MSI->isVolatile())
1738 if (!MSI->getLength()->getType()->isIntegerTy(64))
1741 if (MSI->getDestAddressSpace() > 255)
1742 // Fast instruction selection doesn't support the special
1746 return LowerCallTo(II, "memset", II->getNumArgOperands() - 2);
1748 case Intrinsic::trap: {
1749 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BRK))
1753 case Intrinsic::sqrt: {
1754 Type *RetTy = II->getCalledFunction()->getReturnType();
1757 if (!isTypeLegal(RetTy, VT))
1760 unsigned Op0Reg = getRegForValue(II->getOperand(0));
1763 bool Op0IsKill = hasTrivialKill(II->getOperand(0));
1765 unsigned ResultReg = FastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill);
1769 UpdateValueMap(II, ResultReg);
1772 case Intrinsic::sadd_with_overflow:
1773 case Intrinsic::uadd_with_overflow:
1774 case Intrinsic::ssub_with_overflow:
1775 case Intrinsic::usub_with_overflow:
1776 case Intrinsic::smul_with_overflow:
1777 case Intrinsic::umul_with_overflow: {
1778 // This implements the basic lowering of the xalu with overflow intrinsics.
1779 const Function *Callee = II->getCalledFunction();
1780 auto *Ty = cast<StructType>(Callee->getReturnType());
1781 Type *RetTy = Ty->getTypeAtIndex(0U);
1782 Type *CondTy = Ty->getTypeAtIndex(1);
1785 if (!isTypeLegal(RetTy, VT))
1788 if (VT != MVT::i32 && VT != MVT::i64)
1791 const Value *LHS = II->getArgOperand(0);
1792 const Value *RHS = II->getArgOperand(1);
1793 // Canonicalize immediate to the RHS.
1794 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS) &&
1795 isCommutativeIntrinsic(II))
1796 std::swap(LHS, RHS);
1798 unsigned LHSReg = getRegForValue(LHS);
1801 bool LHSIsKill = hasTrivialKill(LHS);
1803 // Check if the immediate can be encoded in the instruction and if we should
1804 // invert the instruction (adds -> subs) to handle negative immediates.
1805 bool UseImm = false;
1806 bool UseInverse = false;
1808 if (const auto *C = dyn_cast<ConstantInt>(RHS)) {
1809 if (C->isNegative()) {
1811 Imm = -(C->getSExtValue());
1813 Imm = C->getZExtValue();
1815 if (isUInt<12>(Imm))
1818 UseInverse = UseImm && UseInverse;
1821 static const unsigned OpcTable[2][2][2] = {
1822 { {AArch64::ADDSWrr, AArch64::ADDSXrr},
1823 {AArch64::ADDSWri, AArch64::ADDSXri} },
1824 { {AArch64::SUBSWrr, AArch64::SUBSXrr},
1825 {AArch64::SUBSWri, AArch64::SUBSXri} }
1828 unsigned MulReg = 0;
1829 unsigned RHSReg = 0;
1830 bool RHSIsKill = false;
1831 AArch64CC::CondCode CC = AArch64CC::Invalid;
1832 bool Is64Bit = VT == MVT::i64;
1833 switch (II->getIntrinsicID()) {
1834 default: llvm_unreachable("Unexpected intrinsic!");
1835 case Intrinsic::sadd_with_overflow:
1836 Opc = OpcTable[UseInverse][UseImm][Is64Bit]; CC = AArch64CC::VS; break;
1837 case Intrinsic::uadd_with_overflow:
1838 Opc = OpcTable[UseInverse][UseImm][Is64Bit]; CC = AArch64CC::HS; break;
1839 case Intrinsic::ssub_with_overflow:
1840 Opc = OpcTable[!UseInverse][UseImm][Is64Bit]; CC = AArch64CC::VS; break;
1841 case Intrinsic::usub_with_overflow:
1842 Opc = OpcTable[!UseInverse][UseImm][Is64Bit]; CC = AArch64CC::LO; break;
1843 case Intrinsic::smul_with_overflow: {
1845 RHSReg = getRegForValue(RHS);
1848 RHSIsKill = hasTrivialKill(RHS);
1850 if (VT == MVT::i32) {
1851 MulReg = Emit_SMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
1852 unsigned ShiftReg = Emit_LSR_ri(MVT::i64, MulReg, false, 32);
1853 MulReg = FastEmitInst_extractsubreg(VT, MulReg, /*IsKill=*/true,
1855 ShiftReg = FastEmitInst_extractsubreg(VT, ShiftReg, /*IsKill=*/true,
1857 unsigned CmpReg = createResultReg(TLI.getRegClassFor(VT));
1858 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1859 TII.get(AArch64::SUBSWrs), CmpReg)
1860 .addReg(ShiftReg, getKillRegState(true))
1861 .addReg(MulReg, getKillRegState(false))
1862 .addImm(159); // 159 <-> asr #31
1864 assert(VT == MVT::i64 && "Unexpected value type.");
1865 MulReg = Emit_MUL_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
1866 unsigned SMULHReg = FastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill,
1868 unsigned CmpReg = createResultReg(TLI.getRegClassFor(VT));
1869 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1870 TII.get(AArch64::SUBSXrs), CmpReg)
1871 .addReg(SMULHReg, getKillRegState(true))
1872 .addReg(MulReg, getKillRegState(false))
1873 .addImm(191); // 191 <-> asr #63
1877 case Intrinsic::umul_with_overflow: {
1879 RHSReg = getRegForValue(RHS);
1882 RHSIsKill = hasTrivialKill(RHS);
1884 if (VT == MVT::i32) {
1885 MulReg = Emit_UMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
1886 unsigned CmpReg = createResultReg(TLI.getRegClassFor(MVT::i64));
1887 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1888 TII.get(AArch64::SUBSXrs), CmpReg)
1889 .addReg(AArch64::XZR, getKillRegState(true))
1890 .addReg(MulReg, getKillRegState(false))
1891 .addImm(96); // 96 <-> lsr #32
1892 MulReg = FastEmitInst_extractsubreg(VT, MulReg, /*IsKill=*/true,
1895 assert(VT == MVT::i64 && "Unexpected value type.");
1896 MulReg = Emit_MUL_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
1897 unsigned UMULHReg = FastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill,
1899 unsigned CmpReg = createResultReg(TLI.getRegClassFor(VT));
1900 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1901 TII.get(AArch64::SUBSXrr), CmpReg)
1902 .addReg(AArch64::XZR, getKillRegState(true))
1903 .addReg(UMULHReg, getKillRegState(false));
1910 RHSReg = getRegForValue(RHS);
1913 RHSIsKill = hasTrivialKill(RHS);
1916 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1918 MachineInstrBuilder MIB;
1919 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1921 .addReg(LHSReg, getKillRegState(LHSIsKill));
1926 MIB.addReg(RHSReg, getKillRegState(RHSIsKill));
1929 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1930 TII.get(TargetOpcode::COPY), ResultReg)
1933 unsigned ResultReg2 = FuncInfo.CreateRegs(CondTy);
1934 assert((ResultReg+1) == ResultReg2 && "Nonconsecutive result registers.");
1935 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
1937 .addReg(AArch64::WZR, getKillRegState(true))
1938 .addReg(AArch64::WZR, getKillRegState(true))
1939 .addImm(getInvertedCondCode(CC));
1941 UpdateValueMap(II, ResultReg, 2);
1948 bool AArch64FastISel::SelectRet(const Instruction *I) {
1949 const ReturnInst *Ret = cast<ReturnInst>(I);
1950 const Function &F = *I->getParent()->getParent();
1952 if (!FuncInfo.CanLowerReturn)
1958 // Build a list of return value registers.
1959 SmallVector<unsigned, 4> RetRegs;
1961 if (Ret->getNumOperands() > 0) {
1962 CallingConv::ID CC = F.getCallingConv();
1963 SmallVector<ISD::OutputArg, 4> Outs;
1964 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
1966 // Analyze operands of the call, assigning locations to each operand.
1967 SmallVector<CCValAssign, 16> ValLocs;
1968 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,
1970 CCAssignFn *RetCC = CC == CallingConv::WebKit_JS ? RetCC_AArch64_WebKit_JS
1971 : RetCC_AArch64_AAPCS;
1972 CCInfo.AnalyzeReturn(Outs, RetCC);
1974 // Only handle a single return value for now.
1975 if (ValLocs.size() != 1)
1978 CCValAssign &VA = ValLocs[0];
1979 const Value *RV = Ret->getOperand(0);
1981 // Don't bother handling odd stuff for now.
1982 if (VA.getLocInfo() != CCValAssign::Full)
1984 // Only handle register returns for now.
1987 unsigned Reg = getRegForValue(RV);
1991 unsigned SrcReg = Reg + VA.getValNo();
1992 unsigned DestReg = VA.getLocReg();
1993 // Avoid a cross-class copy. This is very unlikely.
1994 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1997 EVT RVEVT = TLI.getValueType(RV->getType());
1998 if (!RVEVT.isSimple())
2001 // Vectors (of > 1 lane) in big endian need tricky handling.
2002 if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1)
2005 MVT RVVT = RVEVT.getSimpleVT();
2006 if (RVVT == MVT::f128)
2008 MVT DestVT = VA.getValVT();
2009 // Special handling for extended integers.
2010 if (RVVT != DestVT) {
2011 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2014 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
2017 bool isZExt = Outs[0].Flags.isZExt();
2018 SrcReg = EmitIntExt(RVVT, SrcReg, DestVT, isZExt);
2024 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2025 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
2027 // Add register to return instruction.
2028 RetRegs.push_back(VA.getLocReg());
2031 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2032 TII.get(AArch64::RET_ReallyLR));
2033 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
2034 MIB.addReg(RetRegs[i], RegState::Implicit);
2038 bool AArch64FastISel::SelectTrunc(const Instruction *I) {
2039 Type *DestTy = I->getType();
2040 Value *Op = I->getOperand(0);
2041 Type *SrcTy = Op->getType();
2043 EVT SrcEVT = TLI.getValueType(SrcTy, true);
2044 EVT DestEVT = TLI.getValueType(DestTy, true);
2045 if (!SrcEVT.isSimple())
2047 if (!DestEVT.isSimple())
2050 MVT SrcVT = SrcEVT.getSimpleVT();
2051 MVT DestVT = DestEVT.getSimpleVT();
2053 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
2056 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&
2060 unsigned SrcReg = getRegForValue(Op);
2064 // If we're truncating from i64 to a smaller non-legal type then generate an
2065 // AND. Otherwise, we know the high bits are undefined and a truncate doesn't
2066 // generate any code.
2067 if (SrcVT == MVT::i64) {
2069 switch (DestVT.SimpleTy) {
2071 // Trunc i64 to i32 is handled by the target-independent fast-isel.
2083 // Issue an extract_subreg to get the lower 32-bits.
2084 unsigned Reg32 = FastEmitInst_extractsubreg(MVT::i32, SrcReg, /*Kill=*/true,
2086 MRI.constrainRegClass(Reg32, &AArch64::GPR32RegClass);
2087 // Create the AND instruction which performs the actual truncation.
2088 unsigned ANDReg = createResultReg(&AArch64::GPR32spRegClass);
2089 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
2092 .addImm(AArch64_AM::encodeLogicalImmediate(Mask, 32));
2096 UpdateValueMap(I, SrcReg);
2100 unsigned AArch64FastISel::Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt) {
2101 assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
2102 DestVT == MVT::i64) &&
2103 "Unexpected value type.");
2104 // Handle i8 and i16 as i32.
2105 if (DestVT == MVT::i8 || DestVT == MVT::i16)
2109 MRI.constrainRegClass(SrcReg, &AArch64::GPR32RegClass);
2110 unsigned ResultReg = createResultReg(&AArch64::GPR32spRegClass);
2111 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDWri),
2114 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
2116 if (DestVT == MVT::i64) {
2117 // We're ZExt i1 to i64. The ANDWri Wd, Ws, #1 implicitly clears the
2118 // upper 32 bits. Emit a SUBREG_TO_REG to extend from Wd to Xd.
2119 unsigned Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
2120 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2121 TII.get(AArch64::SUBREG_TO_REG), Reg64)
2124 .addImm(AArch64::sub_32);
2129 if (DestVT == MVT::i64) {
2130 // FIXME: We're SExt i1 to i64.
2133 unsigned ResultReg = createResultReg(&AArch64::GPR32RegClass);
2134 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SBFMWri),
2143 unsigned AArch64FastISel::Emit_MUL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
2144 unsigned Op1, bool Op1IsKill) {
2146 switch (RetVT.SimpleTy) {
2152 Opc = AArch64::MADDWrrr; ZReg = AArch64::WZR; break;
2154 Opc = AArch64::MADDXrrr; ZReg = AArch64::XZR; break;
2157 // Create the base instruction, then add the operands.
2158 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
2159 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
2160 .addReg(Op0, getKillRegState(Op0IsKill))
2161 .addReg(Op1, getKillRegState(Op1IsKill))
2162 .addReg(ZReg, getKillRegState(true));
2167 unsigned AArch64FastISel::Emit_SMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
2168 unsigned Op1, bool Op1IsKill) {
2169 if (RetVT != MVT::i64)
2172 // Create the base instruction, then add the operands.
2173 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
2174 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::SMADDLrrr),
2176 .addReg(Op0, getKillRegState(Op0IsKill))
2177 .addReg(Op1, getKillRegState(Op1IsKill))
2178 .addReg(AArch64::XZR, getKillRegState(true));
2183 unsigned AArch64FastISel::Emit_UMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
2184 unsigned Op1, bool Op1IsKill) {
2185 if (RetVT != MVT::i64)
2188 // Create the base instruction, then add the operands.
2189 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
2190 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::UMADDLrrr),
2192 .addReg(Op0, getKillRegState(Op0IsKill))
2193 .addReg(Op1, getKillRegState(Op1IsKill))
2194 .addReg(AArch64::XZR, getKillRegState(true));
2199 unsigned AArch64FastISel::Emit_LSL_ri(MVT RetVT, unsigned Op0, bool Op0IsKill,
2201 unsigned Opc, ImmR, ImmS;
2202 switch (RetVT.SimpleTy) {
2208 Opc = AArch64::UBFMWri; ImmR = -Shift % 32; ImmS = 31 - Shift; break;
2210 Opc = AArch64::UBFMXri; ImmR = -Shift % 64; ImmS = 63 - Shift; break;
2213 return FastEmitInst_rii(Opc, TLI.getRegClassFor(RetVT), Op0, Op0IsKill, ImmR,
2217 unsigned AArch64FastISel::Emit_LSR_ri(MVT RetVT, unsigned Op0, bool Op0IsKill,
2220 switch (RetVT.SimpleTy) {
2226 Opc = AArch64::UBFMWri; ImmS = 31; break;
2228 Opc = AArch64::UBFMXri; ImmS = 63; break;
2231 return FastEmitInst_rii(Opc, TLI.getRegClassFor(RetVT), Op0, Op0IsKill, Shift,
2235 unsigned AArch64FastISel::Emit_ASR_ri(MVT RetVT, unsigned Op0, bool Op0IsKill,
2238 switch (RetVT.SimpleTy) {
2244 Opc = AArch64::SBFMWri; ImmS = 31; break;
2246 Opc = AArch64::SBFMXri; ImmS = 63; break;
2249 return FastEmitInst_rii(Opc, TLI.getRegClassFor(RetVT), Op0, Op0IsKill, Shift,
2253 unsigned AArch64FastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
2255 assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");
2257 // FastISel does not have plumbing to deal with extensions where the SrcVT or
2258 // DestVT are odd things, so test to make sure that they are both types we can
2259 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
2260 // bail out to SelectionDAG.
2261 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) &&
2262 (DestVT != MVT::i32) && (DestVT != MVT::i64)) ||
2263 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) &&
2264 (SrcVT != MVT::i16) && (SrcVT != MVT::i32)))
2270 switch (SrcVT.SimpleTy) {
2274 return Emiti1Ext(SrcReg, DestVT, isZExt);
2276 if (DestVT == MVT::i64)
2277 Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
2279 Opc = isZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
2283 if (DestVT == MVT::i64)
2284 Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
2286 Opc = isZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
2290 assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");
2291 Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
2296 // Handle i8 and i16 as i32.
2297 if (DestVT == MVT::i8 || DestVT == MVT::i16)
2299 else if (DestVT == MVT::i64) {
2300 unsigned Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
2301 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2302 TII.get(AArch64::SUBREG_TO_REG), Src64)
2305 .addImm(AArch64::sub_32);
2309 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
2310 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
2318 bool AArch64FastISel::SelectIntExt(const Instruction *I) {
2319 // On ARM, in general, integer casts don't involve legal types; this code
2320 // handles promotable integers. The high bits for a type smaller than
2321 // the register size are assumed to be undefined.
2322 Type *DestTy = I->getType();
2323 Value *Src = I->getOperand(0);
2324 Type *SrcTy = Src->getType();
2326 bool isZExt = isa<ZExtInst>(I);
2327 unsigned SrcReg = getRegForValue(Src);
2331 EVT SrcEVT = TLI.getValueType(SrcTy, true);
2332 EVT DestEVT = TLI.getValueType(DestTy, true);
2333 if (!SrcEVT.isSimple())
2335 if (!DestEVT.isSimple())
2338 MVT SrcVT = SrcEVT.getSimpleVT();
2339 MVT DestVT = DestEVT.getSimpleVT();
2340 unsigned ResultReg = EmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2343 UpdateValueMap(I, ResultReg);
2347 bool AArch64FastISel::SelectRem(const Instruction *I, unsigned ISDOpcode) {
2348 EVT DestEVT = TLI.getValueType(I->getType(), true);
2349 if (!DestEVT.isSimple())
2352 MVT DestVT = DestEVT.getSimpleVT();
2353 if (DestVT != MVT::i64 && DestVT != MVT::i32)
2357 bool is64bit = (DestVT == MVT::i64);
2358 switch (ISDOpcode) {
2362 DivOpc = is64bit ? AArch64::SDIVXr : AArch64::SDIVWr;
2365 DivOpc = is64bit ? AArch64::UDIVXr : AArch64::UDIVWr;
2368 unsigned MSubOpc = is64bit ? AArch64::MSUBXrrr : AArch64::MSUBWrrr;
2369 unsigned Src0Reg = getRegForValue(I->getOperand(0));
2373 unsigned Src1Reg = getRegForValue(I->getOperand(1));
2377 unsigned QuotReg = createResultReg(TLI.getRegClassFor(DestVT));
2378 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(DivOpc), QuotReg)
2381 // The remainder is computed as numerator - (quotient * denominator) using the
2382 // MSUB instruction.
2383 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
2384 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MSubOpc), ResultReg)
2388 UpdateValueMap(I, ResultReg);
2392 bool AArch64FastISel::SelectMul(const Instruction *I) {
2393 EVT SrcEVT = TLI.getValueType(I->getOperand(0)->getType(), true);
2394 if (!SrcEVT.isSimple())
2396 MVT SrcVT = SrcEVT.getSimpleVT();
2398 // Must be simple value type. Don't handle vectors.
2399 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
2403 unsigned Src0Reg = getRegForValue(I->getOperand(0));
2406 bool Src0IsKill = hasTrivialKill(I->getOperand(0));
2408 unsigned Src1Reg = getRegForValue(I->getOperand(1));
2411 bool Src1IsKill = hasTrivialKill(I->getOperand(1));
2413 unsigned ResultReg =
2414 Emit_MUL_rr(SrcVT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill);
2419 UpdateValueMap(I, ResultReg);
2423 bool AArch64FastISel::SelectShift(const Instruction *I, bool IsLeftShift,
2424 bool IsArithmetic) {
2425 EVT RetEVT = TLI.getValueType(I->getType(), true);
2426 if (!RetEVT.isSimple())
2428 MVT RetVT = RetEVT.getSimpleVT();
2430 if (!isa<ConstantInt>(I->getOperand(1)))
2433 unsigned Op0Reg = getRegForValue(I->getOperand(0));
2436 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
2438 uint64_t ShiftVal = cast<ConstantInt>(I->getOperand(1))->getZExtValue();
2442 ResultReg = Emit_LSL_ri(RetVT, Op0Reg, Op0IsKill, ShiftVal);
2445 ResultReg = Emit_ASR_ri(RetVT, Op0Reg, Op0IsKill, ShiftVal);
2447 ResultReg = Emit_LSR_ri(RetVT, Op0Reg, Op0IsKill, ShiftVal);
2453 UpdateValueMap(I, ResultReg);
2457 bool AArch64FastISel::SelectBitCast(const Instruction *I) {
2460 if (!isTypeLegal(I->getOperand(0)->getType(), SrcVT))
2462 if (!isTypeLegal(I->getType(), RetVT))
2466 if (RetVT == MVT::f32 && SrcVT == MVT::i32)
2467 Opc = AArch64::FMOVWSr;
2468 else if (RetVT == MVT::f64 && SrcVT == MVT::i64)
2469 Opc = AArch64::FMOVXDr;
2470 else if (RetVT == MVT::i32 && SrcVT == MVT::f32)
2471 Opc = AArch64::FMOVSWr;
2472 else if (RetVT == MVT::i64 && SrcVT == MVT::f64)
2473 Opc = AArch64::FMOVDXr;
2477 unsigned Op0Reg = getRegForValue(I->getOperand(0));
2480 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
2481 unsigned ResultReg = FastEmitInst_r(Opc, TLI.getRegClassFor(RetVT),
2487 UpdateValueMap(I, ResultReg);
2491 bool AArch64FastISel::TargetSelectInstruction(const Instruction *I) {
2492 switch (I->getOpcode()) {
2495 case Instruction::Load:
2496 return SelectLoad(I);
2497 case Instruction::Store:
2498 return SelectStore(I);
2499 case Instruction::Br:
2500 return SelectBranch(I);
2501 case Instruction::IndirectBr:
2502 return SelectIndirectBr(I);
2503 case Instruction::FCmp:
2504 case Instruction::ICmp:
2505 return SelectCmp(I);
2506 case Instruction::Select:
2507 return SelectSelect(I);
2508 case Instruction::FPExt:
2509 return SelectFPExt(I);
2510 case Instruction::FPTrunc:
2511 return SelectFPTrunc(I);
2512 case Instruction::FPToSI:
2513 return SelectFPToInt(I, /*Signed=*/true);
2514 case Instruction::FPToUI:
2515 return SelectFPToInt(I, /*Signed=*/false);
2516 case Instruction::SIToFP:
2517 return SelectIntToFP(I, /*Signed=*/true);
2518 case Instruction::UIToFP:
2519 return SelectIntToFP(I, /*Signed=*/false);
2520 case Instruction::SRem:
2521 return SelectRem(I, ISD::SREM);
2522 case Instruction::URem:
2523 return SelectRem(I, ISD::UREM);
2524 case Instruction::Ret:
2525 return SelectRet(I);
2526 case Instruction::Trunc:
2527 return SelectTrunc(I);
2528 case Instruction::ZExt:
2529 case Instruction::SExt:
2530 return SelectIntExt(I);
2532 // FIXME: All of these should really be handled by the target-independent
2533 // selector -> improve FastISel tblgen.
2534 case Instruction::Mul:
2535 return SelectMul(I);
2536 case Instruction::Shl:
2537 return SelectShift(I, /*IsLeftShift=*/true, /*IsArithmetic=*/false);
2538 case Instruction::LShr:
2539 return SelectShift(I, /*IsLeftShift=*/false, /*IsArithmetic=*/false);
2540 case Instruction::AShr:
2541 return SelectShift(I, /*IsLeftShift=*/false, /*IsArithmetic=*/true);
2542 case Instruction::BitCast:
2543 return SelectBitCast(I);
2546 // Silence warnings.
2547 (void)&CC_AArch64_DarwinPCS_VarArg;
2551 llvm::FastISel *AArch64::createFastISel(FunctionLoweringInfo &funcInfo,
2552 const TargetLibraryInfo *libInfo) {
2553 return new AArch64FastISel(funcInfo, libInfo);