1 //===-- AArch6464FastISel.cpp - AArch64 FastISel implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the AArch64-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // AArch64GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "AArch64Subtarget.h"
18 #include "AArch64TargetMachine.h"
19 #include "MCTargetDesc/AArch64AddressingModes.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/FastISel.h"
23 #include "llvm/CodeGen/FunctionLoweringInfo.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/GetElementPtrTypeIterator.h"
33 #include "llvm/IR/GlobalAlias.h"
34 #include "llvm/IR/GlobalVariable.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/IR/IntrinsicInst.h"
37 #include "llvm/IR/Operator.h"
38 #include "llvm/Support/CommandLine.h"
43 class AArch64FastISel : public FastISel {
53 AArch64_AM::ShiftExtendType ExtType;
61 const GlobalValue *GV;
64 Address() : Kind(RegBase), ExtType(AArch64_AM::InvalidShiftExtend),
65 OffsetReg(0), Shift(0), Offset(0), GV(nullptr) { Base.Reg = 0; }
66 void setKind(BaseKind K) { Kind = K; }
67 BaseKind getKind() const { return Kind; }
68 void setExtendType(AArch64_AM::ShiftExtendType E) { ExtType = E; }
69 AArch64_AM::ShiftExtendType getExtendType() const { return ExtType; }
70 bool isRegBase() const { return Kind == RegBase; }
71 bool isFIBase() const { return Kind == FrameIndexBase; }
72 void setReg(unsigned Reg) {
73 assert(isRegBase() && "Invalid base register access!");
76 unsigned getReg() const {
77 assert(isRegBase() && "Invalid base register access!");
80 void setOffsetReg(unsigned Reg) {
81 assert(isRegBase() && "Invalid offset register access!");
84 unsigned getOffsetReg() const {
85 assert(isRegBase() && "Invalid offset register access!");
88 void setFI(unsigned FI) {
89 assert(isFIBase() && "Invalid base frame index access!");
92 unsigned getFI() const {
93 assert(isFIBase() && "Invalid base frame index access!");
96 void setOffset(int64_t O) { Offset = O; }
97 int64_t getOffset() { return Offset; }
98 void setShift(unsigned S) { Shift = S; }
99 unsigned getShift() { return Shift; }
101 void setGlobalValue(const GlobalValue *G) { GV = G; }
102 const GlobalValue *getGlobalValue() { return GV; }
105 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
106 /// make the right decision when generating code for different targets.
107 const AArch64Subtarget *Subtarget;
108 LLVMContext *Context;
110 bool FastLowerArguments() override;
111 bool FastLowerCall(CallLoweringInfo &CLI) override;
112 bool FastLowerIntrinsicCall(const IntrinsicInst *II) override;
115 // Selection routines.
116 bool SelectLoad(const Instruction *I);
117 bool SelectStore(const Instruction *I);
118 bool SelectBranch(const Instruction *I);
119 bool SelectIndirectBr(const Instruction *I);
120 bool SelectCmp(const Instruction *I);
121 bool SelectSelect(const Instruction *I);
122 bool SelectFPExt(const Instruction *I);
123 bool SelectFPTrunc(const Instruction *I);
124 bool SelectFPToInt(const Instruction *I, bool Signed);
125 bool SelectIntToFP(const Instruction *I, bool Signed);
126 bool SelectRem(const Instruction *I, unsigned ISDOpcode);
127 bool SelectRet(const Instruction *I);
128 bool SelectTrunc(const Instruction *I);
129 bool SelectIntExt(const Instruction *I);
130 bool SelectMul(const Instruction *I);
131 bool SelectShift(const Instruction *I);
132 bool SelectBitCast(const Instruction *I);
134 // Utility helper routines.
135 bool isTypeLegal(Type *Ty, MVT &VT);
136 bool isLoadStoreTypeLegal(Type *Ty, MVT &VT);
137 bool isValueAvailable(const Value *V) const;
138 bool ComputeAddress(const Value *Obj, Address &Addr, Type *Ty = nullptr);
139 bool ComputeCallAddress(const Value *V, Address &Addr);
140 bool SimplifyAddress(Address &Addr, MVT VT);
141 void AddLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
142 unsigned Flags, unsigned ScaleFactor,
143 MachineMemOperand *MMO);
144 bool IsMemCpySmall(uint64_t Len, unsigned Alignment);
145 bool TryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
147 bool foldXALUIntrinsic(AArch64CC::CondCode &CC, const Instruction *I,
150 // Emit helper routines.
151 unsigned emitAddsSubs(bool UseAdds, MVT RetVT, const Value *LHS,
152 const Value *RHS, bool IsZExt = false,
153 bool WantResult = true);
154 unsigned emitAddsSubs_rr(bool UseAdds, MVT RetVT, unsigned LHSReg,
155 bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
156 bool WantResult = true);
157 unsigned emitAddsSubs_ri(bool UseAdds, MVT RetVT, unsigned LHSReg,
158 bool LHSIsKill, uint64_t Imm,
159 bool WantResult = true);
160 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
161 bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
162 AArch64_AM::ShiftExtendType ShiftType,
163 uint64_t ShiftImm, bool WantResult = true);
164 unsigned emitAddsSubs_rs(bool UseAdds, MVT RetVT, unsigned LHSReg,
165 bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
166 AArch64_AM::ShiftExtendType ShiftType,
167 uint64_t ShiftImm, bool WantResult = true);
168 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
169 bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
170 AArch64_AM::ShiftExtendType ExtType,
171 uint64_t ShiftImm, bool WantResult = true);
173 unsigned emitAddsSubs_rx(bool UseAdds, MVT RetVT, unsigned LHSReg,
174 bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
175 AArch64_AM::ShiftExtendType ExtType,
176 uint64_t ShiftImm, bool WantResult = true);
179 bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
180 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
181 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
182 bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
183 bool EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
184 MachineMemOperand *MMO = nullptr);
185 bool EmitStore(MVT VT, unsigned SrcReg, Address Addr,
186 MachineMemOperand *MMO = nullptr);
187 unsigned EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
188 unsigned Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
189 unsigned emitAdds(MVT RetVT, const Value *LHS, const Value *RHS,
190 bool IsZExt = false, bool WantResult = true);
191 unsigned emitSubs(MVT RetVT, const Value *LHS, const Value *RHS,
192 bool IsZExt = false, bool WantResult = true);
193 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
194 unsigned RHSReg, bool RHSIsKill, bool WantResult = true);
195 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
196 unsigned RHSReg, bool RHSIsKill,
197 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
198 bool WantResult = true);
199 unsigned emitAND_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
200 unsigned Emit_MUL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
201 unsigned Op1, bool Op1IsKill);
202 unsigned Emit_SMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
203 unsigned Op1, bool Op1IsKill);
204 unsigned Emit_UMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
205 unsigned Op1, bool Op1IsKill);
206 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
207 unsigned Op1Reg, bool Op1IsKill);
208 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
209 uint64_t Imm, bool IsZExt = true);
210 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
211 unsigned Op1Reg, bool Op1IsKill);
212 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
213 uint64_t Imm, bool IsZExt = true);
214 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
215 unsigned Op1Reg, bool Op1IsKill);
216 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
217 uint64_t Imm, bool IsZExt = false);
219 unsigned AArch64MaterializeInt(const ConstantInt *CI, MVT VT);
220 unsigned AArch64MaterializeFP(const ConstantFP *CFP, MVT VT);
221 unsigned AArch64MaterializeGV(const GlobalValue *GV);
223 // Call handling routines.
225 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
226 bool ProcessCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
228 bool FinishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
231 // Backend specific FastISel code.
232 unsigned TargetMaterializeAlloca(const AllocaInst *AI) override;
233 unsigned TargetMaterializeConstant(const Constant *C) override;
234 unsigned TargetMaterializeFloatZero(const ConstantFP* CF) override;
236 explicit AArch64FastISel(FunctionLoweringInfo &funcInfo,
237 const TargetLibraryInfo *libInfo)
238 : FastISel(funcInfo, libInfo) {
239 Subtarget = &TM.getSubtarget<AArch64Subtarget>();
240 Context = &funcInfo.Fn->getContext();
243 bool TargetSelectInstruction(const Instruction *I) override;
245 #include "AArch64GenFastISel.inc"
248 } // end anonymous namespace
250 #include "AArch64GenCallingConv.inc"
252 CCAssignFn *AArch64FastISel::CCAssignFnForCall(CallingConv::ID CC) const {
253 if (CC == CallingConv::WebKit_JS)
254 return CC_AArch64_WebKit_JS;
255 return Subtarget->isTargetDarwin() ? CC_AArch64_DarwinPCS : CC_AArch64_AAPCS;
258 unsigned AArch64FastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
259 assert(TLI.getValueType(AI->getType(), true) == MVT::i64 &&
260 "Alloca should always return a pointer.");
262 // Don't handle dynamic allocas.
263 if (!FuncInfo.StaticAllocaMap.count(AI))
266 DenseMap<const AllocaInst *, int>::iterator SI =
267 FuncInfo.StaticAllocaMap.find(AI);
269 if (SI != FuncInfo.StaticAllocaMap.end()) {
270 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
271 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
273 .addFrameIndex(SI->second)
282 unsigned AArch64FastISel::AArch64MaterializeInt(const ConstantInt *CI, MVT VT) {
287 return FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
289 // Create a copy from the zero register to materialize a "0" value.
290 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass
291 : &AArch64::GPR32RegClass;
292 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
293 unsigned ResultReg = createResultReg(RC);
294 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
295 ResultReg).addReg(ZeroReg, getKillRegState(true));
299 unsigned AArch64FastISel::AArch64MaterializeFP(const ConstantFP *CFP, MVT VT) {
300 // Positive zero (+0.0) has to be materialized with a fmov from the zero
301 // register, because the immediate version of fmov cannot encode zero.
302 if (CFP->isNullValue())
303 return TargetMaterializeFloatZero(CFP);
305 if (VT != MVT::f32 && VT != MVT::f64)
308 const APFloat Val = CFP->getValueAPF();
309 bool Is64Bit = (VT == MVT::f64);
310 // This checks to see if we can use FMOV instructions to materialize
311 // a constant, otherwise we have to materialize via the constant pool.
312 if (TLI.isFPImmLegal(Val, VT)) {
314 Is64Bit ? AArch64_AM::getFP64Imm(Val) : AArch64_AM::getFP32Imm(Val);
315 assert((Imm != -1) && "Cannot encode floating-point constant.");
316 unsigned Opc = Is64Bit ? AArch64::FMOVDi : AArch64::FMOVSi;
317 return FastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm);
320 // Materialize via constant pool. MachineConstantPool wants an explicit
322 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
324 Align = DL.getTypeAllocSize(CFP->getType());
326 unsigned CPI = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
327 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
328 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
329 ADRPReg).addConstantPoolIndex(CPI, 0, AArch64II::MO_PAGE);
331 unsigned Opc = Is64Bit ? AArch64::LDRDui : AArch64::LDRSui;
332 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
333 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
335 .addConstantPoolIndex(CPI, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
339 unsigned AArch64FastISel::AArch64MaterializeGV(const GlobalValue *GV) {
340 // We can't handle thread-local variables quickly yet.
341 if (GV->isThreadLocal())
344 // MachO still uses GOT for large code-model accesses, but ELF requires
345 // movz/movk sequences, which FastISel doesn't handle yet.
346 if (TM.getCodeModel() != CodeModel::Small && !Subtarget->isTargetMachO())
349 unsigned char OpFlags = Subtarget->ClassifyGlobalReference(GV, TM);
351 EVT DestEVT = TLI.getValueType(GV->getType(), true);
352 if (!DestEVT.isSimple())
355 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
358 if (OpFlags & AArch64II::MO_GOT) {
360 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
362 .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGE);
364 ResultReg = createResultReg(&AArch64::GPR64RegClass);
365 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui),
368 .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF |
372 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
374 .addGlobalAddress(GV, 0, AArch64II::MO_PAGE);
376 ResultReg = createResultReg(&AArch64::GPR64spRegClass);
377 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
380 .addGlobalAddress(GV, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC)
386 unsigned AArch64FastISel::TargetMaterializeConstant(const Constant *C) {
387 EVT CEVT = TLI.getValueType(C->getType(), true);
389 // Only handle simple types.
390 if (!CEVT.isSimple())
392 MVT VT = CEVT.getSimpleVT();
394 if (const auto *CI = dyn_cast<ConstantInt>(C))
395 return AArch64MaterializeInt(CI, VT);
396 else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
397 return AArch64MaterializeFP(CFP, VT);
398 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
399 return AArch64MaterializeGV(GV);
404 unsigned AArch64FastISel::TargetMaterializeFloatZero(const ConstantFP* CFP) {
405 assert(CFP->isNullValue() &&
406 "Floating-point constant is not a positive zero.");
408 if (!isTypeLegal(CFP->getType(), VT))
411 if (VT != MVT::f32 && VT != MVT::f64)
414 bool Is64Bit = (VT == MVT::f64);
415 unsigned ZReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
416 unsigned Opc = Is64Bit ? AArch64::FMOVXDr : AArch64::FMOVWSr;
417 return FastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true);
420 // Computes the address to get to an object.
421 bool AArch64FastISel::ComputeAddress(const Value *Obj, Address &Addr, Type *Ty)
423 const User *U = nullptr;
424 unsigned Opcode = Instruction::UserOp1;
425 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
426 // Don't walk into other basic blocks unless the object is an alloca from
427 // another block, otherwise it may not have a virtual register assigned.
428 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
429 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
430 Opcode = I->getOpcode();
433 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
434 Opcode = C->getOpcode();
438 if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
439 if (Ty->getAddressSpace() > 255)
440 // Fast instruction selection doesn't support the special
447 case Instruction::BitCast: {
448 // Look through bitcasts.
449 return ComputeAddress(U->getOperand(0), Addr, Ty);
451 case Instruction::IntToPtr: {
452 // Look past no-op inttoptrs.
453 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
454 return ComputeAddress(U->getOperand(0), Addr, Ty);
457 case Instruction::PtrToInt: {
458 // Look past no-op ptrtoints.
459 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
460 return ComputeAddress(U->getOperand(0), Addr, Ty);
463 case Instruction::GetElementPtr: {
464 Address SavedAddr = Addr;
465 uint64_t TmpOffset = Addr.getOffset();
467 // Iterate through the GEP folding the constants into offsets where
469 gep_type_iterator GTI = gep_type_begin(U);
470 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
472 const Value *Op = *i;
473 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
474 const StructLayout *SL = DL.getStructLayout(STy);
475 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
476 TmpOffset += SL->getElementOffset(Idx);
478 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
480 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
481 // Constant-offset addressing.
482 TmpOffset += CI->getSExtValue() * S;
485 if (canFoldAddIntoGEP(U, Op)) {
486 // A compatible add with a constant operand. Fold the constant.
488 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
489 TmpOffset += CI->getSExtValue() * S;
490 // Iterate on the other operand.
491 Op = cast<AddOperator>(Op)->getOperand(0);
495 goto unsupported_gep;
500 // Try to grab the base operand now.
501 Addr.setOffset(TmpOffset);
502 if (ComputeAddress(U->getOperand(0), Addr, Ty))
505 // We failed, restore everything and try the other options.
511 case Instruction::Alloca: {
512 const AllocaInst *AI = cast<AllocaInst>(Obj);
513 DenseMap<const AllocaInst *, int>::iterator SI =
514 FuncInfo.StaticAllocaMap.find(AI);
515 if (SI != FuncInfo.StaticAllocaMap.end()) {
516 Addr.setKind(Address::FrameIndexBase);
517 Addr.setFI(SI->second);
522 case Instruction::Add: {
523 // Adds of constants are common and easy enough.
524 const Value *LHS = U->getOperand(0);
525 const Value *RHS = U->getOperand(1);
527 if (isa<ConstantInt>(LHS))
530 if (const ConstantInt *CI = dyn_cast<ConstantInt>(RHS)) {
531 Addr.setOffset(Addr.getOffset() + (uint64_t)CI->getSExtValue());
532 return ComputeAddress(LHS, Addr, Ty);
535 Address Backup = Addr;
536 if (ComputeAddress(LHS, Addr, Ty) && ComputeAddress(RHS, Addr, Ty))
542 case Instruction::Shl:
543 if (Addr.getOffsetReg())
546 if (const auto *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
547 unsigned Val = CI->getZExtValue();
548 if (Val < 1 || Val > 3)
551 uint64_t NumBytes = 0;
552 if (Ty && Ty->isSized()) {
553 uint64_t NumBits = DL.getTypeSizeInBits(Ty);
554 NumBytes = NumBits / 8;
555 if (!isPowerOf2_64(NumBits))
559 if (NumBytes != (1ULL << Val))
563 Addr.setExtendType(AArch64_AM::LSL);
565 if (const auto *I = dyn_cast<Instruction>(U->getOperand(0)))
566 if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
569 if (const auto *ZE = dyn_cast<ZExtInst>(U))
570 if (ZE->getOperand(0)->getType()->isIntegerTy(32))
571 Addr.setExtendType(AArch64_AM::UXTW);
573 if (const auto *SE = dyn_cast<SExtInst>(U))
574 if (SE->getOperand(0)->getType()->isIntegerTy(32))
575 Addr.setExtendType(AArch64_AM::SXTW);
577 unsigned Reg = getRegForValue(U->getOperand(0));
580 Addr.setOffsetReg(Reg);
587 if (!Addr.getOffsetReg()) {
588 unsigned Reg = getRegForValue(Obj);
591 Addr.setOffsetReg(Reg);
597 unsigned Reg = getRegForValue(Obj);
604 bool AArch64FastISel::ComputeCallAddress(const Value *V, Address &Addr) {
605 const User *U = nullptr;
606 unsigned Opcode = Instruction::UserOp1;
609 if (const auto *I = dyn_cast<Instruction>(V)) {
610 Opcode = I->getOpcode();
612 InMBB = I->getParent() == FuncInfo.MBB->getBasicBlock();
613 } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
614 Opcode = C->getOpcode();
620 case Instruction::BitCast:
621 // Look past bitcasts if its operand is in the same BB.
623 return ComputeCallAddress(U->getOperand(0), Addr);
625 case Instruction::IntToPtr:
626 // Look past no-op inttoptrs if its operand is in the same BB.
628 TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
629 return ComputeCallAddress(U->getOperand(0), Addr);
631 case Instruction::PtrToInt:
632 // Look past no-op ptrtoints if its operand is in the same BB.
634 TLI.getValueType(U->getType()) == TLI.getPointerTy())
635 return ComputeCallAddress(U->getOperand(0), Addr);
639 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
640 Addr.setGlobalValue(GV);
644 // If all else fails, try to materialize the value in a register.
645 if (!Addr.getGlobalValue()) {
646 Addr.setReg(getRegForValue(V));
647 return Addr.getReg() != 0;
654 bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) {
655 EVT evt = TLI.getValueType(Ty, true);
657 // Only handle simple types.
658 if (evt == MVT::Other || !evt.isSimple())
660 VT = evt.getSimpleVT();
662 // This is a legal type, but it's not something we handle in fast-isel.
666 // Handle all other legal types, i.e. a register that will directly hold this
668 return TLI.isTypeLegal(VT);
671 bool AArch64FastISel::isLoadStoreTypeLegal(Type *Ty, MVT &VT) {
672 if (isTypeLegal(Ty, VT))
675 // If this is a type than can be sign or zero-extended to a basic operation
676 // go ahead and accept it now. For stores, this reflects truncation.
677 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
683 bool AArch64FastISel::isValueAvailable(const Value *V) const {
684 if (!isa<Instruction>(V))
687 const auto *I = cast<Instruction>(V);
688 if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
694 bool AArch64FastISel::SimplifyAddress(Address &Addr, MVT VT) {
695 unsigned ScaleFactor;
696 switch (VT.SimpleTy) {
697 default: return false;
698 case MVT::i1: // fall-through
699 case MVT::i8: ScaleFactor = 1; break;
700 case MVT::i16: ScaleFactor = 2; break;
701 case MVT::i32: // fall-through
702 case MVT::f32: ScaleFactor = 4; break;
703 case MVT::i64: // fall-through
704 case MVT::f64: ScaleFactor = 8; break;
707 bool ImmediateOffsetNeedsLowering = false;
708 bool RegisterOffsetNeedsLowering = false;
709 int64_t Offset = Addr.getOffset();
710 if (((Offset < 0) || (Offset & (ScaleFactor - 1))) && !isInt<9>(Offset))
711 ImmediateOffsetNeedsLowering = true;
712 else if (Offset > 0 && !(Offset & (ScaleFactor - 1)) &&
713 !isUInt<12>(Offset / ScaleFactor))
714 ImmediateOffsetNeedsLowering = true;
716 // Cannot encode an offset register and an immediate offset in the same
717 // instruction. Fold the immediate offset into the load/store instruction and
718 // emit an additonal add to take care of the offset register.
719 if (!ImmediateOffsetNeedsLowering && Addr.getOffset() && Addr.isRegBase() &&
721 RegisterOffsetNeedsLowering = true;
723 // Cannot encode zero register as base.
724 if (Addr.isRegBase() && Addr.getOffsetReg() && !Addr.getReg())
725 RegisterOffsetNeedsLowering = true;
727 // If this is a stack pointer and the offset needs to be simplified then put
728 // the alloca address into a register, set the base type back to register and
729 // continue. This should almost never happen.
730 if (ImmediateOffsetNeedsLowering && Addr.isFIBase()) {
731 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
732 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
734 .addFrameIndex(Addr.getFI())
737 Addr.setKind(Address::RegBase);
738 Addr.setReg(ResultReg);
741 if (RegisterOffsetNeedsLowering) {
742 unsigned ResultReg = 0;
744 if (Addr.getExtendType() == AArch64_AM::SXTW ||
745 Addr.getExtendType() == AArch64_AM::UXTW )
746 ResultReg = emitAddSub_rx(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
747 /*TODO:IsKill=*/false, Addr.getOffsetReg(),
748 /*TODO:IsKill=*/false, Addr.getExtendType(),
751 ResultReg = emitAddSub_rs(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
752 /*TODO:IsKill=*/false, Addr.getOffsetReg(),
753 /*TODO:IsKill=*/false, AArch64_AM::LSL,
756 if (Addr.getExtendType() == AArch64_AM::UXTW)
757 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
758 /*Op0IsKill=*/false, Addr.getShift(),
760 else if (Addr.getExtendType() == AArch64_AM::SXTW)
761 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
762 /*Op0IsKill=*/false, Addr.getShift(),
765 ResultReg = emitLSL_ri(MVT::i64, MVT::i64, Addr.getOffsetReg(),
766 /*Op0IsKill=*/false, Addr.getShift());
771 Addr.setReg(ResultReg);
772 Addr.setOffsetReg(0);
774 Addr.setExtendType(AArch64_AM::InvalidShiftExtend);
777 // Since the offset is too large for the load/store instruction get the
778 // reg+offset into a register.
779 if (ImmediateOffsetNeedsLowering) {
780 unsigned ResultReg = 0;
782 ResultReg = FastEmit_ri_(MVT::i64, ISD::ADD, Addr.getReg(),
783 /*IsKill=*/false, Offset, MVT::i64);
785 ResultReg = FastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset);
789 Addr.setReg(ResultReg);
795 void AArch64FastISel::AddLoadStoreOperands(Address &Addr,
796 const MachineInstrBuilder &MIB,
798 unsigned ScaleFactor,
799 MachineMemOperand *MMO) {
800 int64_t Offset = Addr.getOffset() / ScaleFactor;
801 // Frame base works a bit differently. Handle it separately.
802 if (Addr.isFIBase()) {
803 int FI = Addr.getFI();
804 // FIXME: We shouldn't be using getObjectSize/getObjectAlignment. The size
805 // and alignment should be based on the VT.
806 MMO = FuncInfo.MF->getMachineMemOperand(
807 MachinePointerInfo::getFixedStack(FI, Offset), Flags,
808 MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
809 // Now add the rest of the operands.
810 MIB.addFrameIndex(FI).addImm(Offset);
812 assert(Addr.isRegBase() && "Unexpected address kind.");
813 const MCInstrDesc &II = MIB->getDesc();
814 unsigned Idx = (Flags & MachineMemOperand::MOStore) ? 1 : 0;
816 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx));
818 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1));
819 if (Addr.getOffsetReg()) {
820 assert(Addr.getOffset() == 0 && "Unexpected offset");
821 bool IsSigned = Addr.getExtendType() == AArch64_AM::SXTW ||
822 Addr.getExtendType() == AArch64_AM::SXTX;
823 MIB.addReg(Addr.getReg());
824 MIB.addReg(Addr.getOffsetReg());
825 MIB.addImm(IsSigned);
826 MIB.addImm(Addr.getShift() != 0);
828 MIB.addReg(Addr.getReg());
834 MIB.addMemOperand(MMO);
837 unsigned AArch64FastISel::emitAddsSubs(bool UseAdds, MVT RetVT,
838 const Value *LHS, const Value *RHS,
839 bool IsZExt, bool WantResult) {
840 AArch64_AM::ShiftExtendType ExtendType = AArch64_AM::InvalidShiftExtend;
841 bool NeedExtend = false;
842 switch (RetVT.SimpleTy) {
850 ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB;
854 ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH;
856 case MVT::i32: // fall-through
861 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32);
863 // Canonicalize immediates to the RHS first.
864 if (UseAdds && isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
867 // Canonicalize shift immediate to the RHS.
868 if (UseAdds && isValueAvailable(LHS))
869 if (const auto *SI = dyn_cast<BinaryOperator>(LHS))
870 if (isa<ConstantInt>(SI->getOperand(1)))
871 if (SI->getOpcode() == Instruction::Shl ||
872 SI->getOpcode() == Instruction::LShr ||
873 SI->getOpcode() == Instruction::AShr )
876 unsigned LHSReg = getRegForValue(LHS);
879 bool LHSIsKill = hasTrivialKill(LHS);
882 LHSReg = EmitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
884 unsigned ResultReg = 0;
885 if (const auto *C = dyn_cast<ConstantInt>(RHS)) {
886 uint64_t Imm = IsZExt ? C->getZExtValue() : C->getSExtValue();
889 emitAddsSubs_ri(!UseAdds, RetVT, LHSReg, LHSIsKill, -Imm, WantResult);
892 emitAddsSubs_ri(UseAdds, RetVT, LHSReg, LHSIsKill, Imm, WantResult);
897 // Only extend the RHS within the instruction if there is a valid extend type.
898 if (ExtendType != AArch64_AM::InvalidShiftExtend && isValueAvailable(RHS)) {
899 if (const auto *SI = dyn_cast<BinaryOperator>(RHS))
900 if (const auto *C = dyn_cast<ConstantInt>(SI->getOperand(1)))
901 if ((SI->getOpcode() == Instruction::Shl) && (C->getZExtValue() < 4)) {
902 unsigned RHSReg = getRegForValue(SI->getOperand(0));
905 bool RHSIsKill = hasTrivialKill(SI->getOperand(0));
906 return emitAddsSubs_rx(UseAdds, RetVT, LHSReg, LHSIsKill, RHSReg,
907 RHSIsKill, ExtendType, C->getZExtValue(),
910 unsigned RHSReg = getRegForValue(RHS);
913 bool RHSIsKill = hasTrivialKill(RHS);
914 return emitAddsSubs_rx(UseAdds, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
915 ExtendType, 0, WantResult);
918 // Check if the shift can be folded into the instruction.
919 if (isValueAvailable(RHS))
920 if (const auto *SI = dyn_cast<BinaryOperator>(RHS)) {
921 if (const auto *C = dyn_cast<ConstantInt>(SI->getOperand(1))) {
922 AArch64_AM::ShiftExtendType ShiftType = AArch64_AM::InvalidShiftExtend;
923 switch (SI->getOpcode()) {
925 case Instruction::Shl: ShiftType = AArch64_AM::LSL; break;
926 case Instruction::LShr: ShiftType = AArch64_AM::LSR; break;
927 case Instruction::AShr: ShiftType = AArch64_AM::ASR; break;
929 uint64_t ShiftVal = C->getZExtValue();
930 if (ShiftType != AArch64_AM::InvalidShiftExtend) {
931 unsigned RHSReg = getRegForValue(SI->getOperand(0));
934 bool RHSIsKill = hasTrivialKill(SI->getOperand(0));
935 return emitAddsSubs_rs(UseAdds, RetVT, LHSReg, LHSIsKill, RHSReg,
936 RHSIsKill, ShiftType, ShiftVal, WantResult);
941 unsigned RHSReg = getRegForValue(RHS);
944 bool RHSIsKill = hasTrivialKill(RHS);
947 RHSReg = EmitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
949 return emitAddsSubs_rr(UseAdds, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
953 unsigned AArch64FastISel::emitAddsSubs_rr(bool UseAdds, MVT RetVT,
954 unsigned LHSReg, bool LHSIsKill,
955 unsigned RHSReg, bool RHSIsKill,
957 assert(LHSReg && RHSReg && "Invalid register number.");
959 if (RetVT != MVT::i32 && RetVT != MVT::i64)
962 static const unsigned OpcTable[2][2] = {
963 { AArch64::ADDSWrr, AArch64::ADDSXrr },
964 { AArch64::SUBSWrr, AArch64::SUBSXrr }
966 unsigned Opc = OpcTable[!UseAdds][(RetVT == MVT::i64)];
969 const TargetRegisterClass *RC =
970 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
971 ResultReg = createResultReg(RC);
973 ResultReg = (RetVT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
975 const MCInstrDesc &II = TII.get(Opc);
976 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
977 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
978 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
979 .addReg(LHSReg, getKillRegState(LHSIsKill))
980 .addReg(RHSReg, getKillRegState(RHSIsKill));
985 unsigned AArch64FastISel::emitAddsSubs_ri(bool UseAdds, MVT RetVT,
986 unsigned LHSReg, bool LHSIsKill,
987 uint64_t Imm, bool WantResult) {
988 assert(LHSReg && "Invalid register number.");
990 if (RetVT != MVT::i32 && RetVT != MVT::i64)
996 else if ((Imm & 0xfff000) == Imm) {
1002 static const unsigned OpcTable[2][2] = {
1003 { AArch64::ADDSWri, AArch64::ADDSXri },
1004 { AArch64::SUBSWri, AArch64::SUBSXri }
1006 unsigned Opc = OpcTable[!UseAdds][(RetVT == MVT::i64)];
1009 const TargetRegisterClass *RC =
1010 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1011 ResultReg = createResultReg(RC);
1013 ResultReg = (RetVT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
1015 const MCInstrDesc &II = TII.get(Opc);
1016 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1017 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1018 .addReg(LHSReg, getKillRegState(LHSIsKill))
1020 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm));
1025 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT,
1026 unsigned LHSReg, bool LHSIsKill,
1027 unsigned RHSReg, bool RHSIsKill,
1028 AArch64_AM::ShiftExtendType ShiftType,
1029 uint64_t ShiftImm, bool WantResult) {
1030 assert(LHSReg && RHSReg && "Invalid register number.");
1032 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1035 static const unsigned OpcTable[2][2] = {
1036 { AArch64::ADDWrs, AArch64::ADDXrs },
1037 { AArch64::SUBWrs, AArch64::SUBXrs }
1039 unsigned Opc = OpcTable[!UseAdd][(RetVT == MVT::i64)];
1042 const TargetRegisterClass *RC =
1043 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1044 ResultReg = createResultReg(RC);
1046 ResultReg = (RetVT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
1048 const MCInstrDesc &II = TII.get(Opc);
1049 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1050 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
1051 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1052 .addReg(LHSReg, getKillRegState(LHSIsKill))
1053 .addReg(RHSReg, getKillRegState(RHSIsKill))
1054 .addImm(getShifterImm(ShiftType, ShiftImm));
1059 unsigned AArch64FastISel::emitAddsSubs_rs(bool UseAdds, MVT RetVT,
1060 unsigned LHSReg, bool LHSIsKill,
1061 unsigned RHSReg, bool RHSIsKill,
1062 AArch64_AM::ShiftExtendType ShiftType,
1063 uint64_t ShiftImm, bool WantResult) {
1064 assert(LHSReg && RHSReg && "Invalid register number.");
1066 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1069 static const unsigned OpcTable[2][2] = {
1070 { AArch64::ADDSWrs, AArch64::ADDSXrs },
1071 { AArch64::SUBSWrs, AArch64::SUBSXrs }
1073 unsigned Opc = OpcTable[!UseAdds][(RetVT == MVT::i64)];
1076 const TargetRegisterClass *RC =
1077 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1078 ResultReg = createResultReg(RC);
1080 ResultReg = (RetVT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
1082 const MCInstrDesc &II = TII.get(Opc);
1083 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1084 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
1085 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1086 .addReg(LHSReg, getKillRegState(LHSIsKill))
1087 .addReg(RHSReg, getKillRegState(RHSIsKill))
1088 .addImm(getShifterImm(ShiftType, ShiftImm));
1093 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT,
1094 unsigned LHSReg, bool LHSIsKill,
1095 unsigned RHSReg, bool RHSIsKill,
1096 AArch64_AM::ShiftExtendType ExtType,
1097 uint64_t ShiftImm, bool WantResult) {
1098 assert(LHSReg && RHSReg && "Invalid register number.");
1100 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1103 static const unsigned OpcTable[2][2] = {
1104 { AArch64::ADDWrx, AArch64::ADDXrx },
1105 { AArch64::SUBWrx, AArch64::SUBXrx }
1107 unsigned Opc = OpcTable[!UseAdd][(RetVT == MVT::i64)];
1110 const TargetRegisterClass *RC =
1111 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1112 ResultReg = createResultReg(RC);
1114 ResultReg = (RetVT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
1116 const MCInstrDesc &II = TII.get(Opc);
1117 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1118 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
1119 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1120 .addReg(LHSReg, getKillRegState(LHSIsKill))
1121 .addReg(RHSReg, getKillRegState(RHSIsKill))
1122 .addImm(getArithExtendImm(ExtType, ShiftImm));
1127 unsigned AArch64FastISel::emitAddsSubs_rx(bool UseAdds, MVT RetVT,
1128 unsigned LHSReg, bool LHSIsKill,
1129 unsigned RHSReg, bool RHSIsKill,
1130 AArch64_AM::ShiftExtendType ExtType,
1131 uint64_t ShiftImm, bool WantResult) {
1132 assert(LHSReg && RHSReg && "Invalid register number.");
1134 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1137 static const unsigned OpcTable[2][2] = {
1138 { AArch64::ADDSWrx, AArch64::ADDSXrx },
1139 { AArch64::SUBSWrx, AArch64::SUBSXrx }
1141 unsigned Opc = OpcTable[!UseAdds][(RetVT == MVT::i64)];
1144 const TargetRegisterClass *RC =
1145 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1146 ResultReg = createResultReg(RC);
1148 ResultReg = (RetVT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
1150 const MCInstrDesc &II = TII.get(Opc);
1151 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1152 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
1153 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1154 .addReg(LHSReg, getKillRegState(LHSIsKill))
1155 .addReg(RHSReg, getKillRegState(RHSIsKill))
1156 .addImm(getArithExtendImm(ExtType, ShiftImm));
1161 bool AArch64FastISel::emitCmp(const Value *LHS, const Value *RHS, bool IsZExt) {
1162 Type *Ty = LHS->getType();
1163 EVT EVT = TLI.getValueType(Ty, true);
1164 if (!EVT.isSimple())
1166 MVT VT = EVT.getSimpleVT();
1168 switch (VT.SimpleTy) {
1176 return emitICmp(VT, LHS, RHS, IsZExt);
1179 return emitFCmp(VT, LHS, RHS);
1183 bool AArch64FastISel::emitICmp(MVT RetVT, const Value *LHS, const Value *RHS,
1185 return emitSubs(RetVT, LHS, RHS, IsZExt, /*WantResult=*/false) != 0;
1188 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
1190 return emitAddsSubs_ri(false, RetVT, LHSReg, LHSIsKill, Imm,
1191 /*WantResult=*/false) != 0;
1194 bool AArch64FastISel::emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS) {
1195 if (RetVT != MVT::f32 && RetVT != MVT::f64)
1198 // Check to see if the 2nd operand is a constant that we can encode directly
1200 bool UseImm = false;
1201 if (const auto *CFP = dyn_cast<ConstantFP>(RHS))
1202 if (CFP->isZero() && !CFP->isNegative())
1205 unsigned LHSReg = getRegForValue(LHS);
1208 bool LHSIsKill = hasTrivialKill(LHS);
1211 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDri : AArch64::FCMPSri;
1212 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
1213 .addReg(LHSReg, getKillRegState(LHSIsKill));
1217 unsigned RHSReg = getRegForValue(RHS);
1220 bool RHSIsKill = hasTrivialKill(RHS);
1222 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDrr : AArch64::FCMPSrr;
1223 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
1224 .addReg(LHSReg, getKillRegState(LHSIsKill))
1225 .addReg(RHSReg, getKillRegState(RHSIsKill));
1229 unsigned AArch64FastISel::emitAdds(MVT RetVT, const Value *LHS,
1230 const Value *RHS, bool IsZExt,
1232 return emitAddsSubs(true, RetVT, LHS, RHS, IsZExt, WantResult);
1235 unsigned AArch64FastISel::emitSubs(MVT RetVT, const Value *LHS,
1236 const Value *RHS, bool IsZExt,
1238 return emitAddsSubs(false, RetVT, LHS, RHS, IsZExt, WantResult);
1241 unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg,
1242 bool LHSIsKill, unsigned RHSReg,
1243 bool RHSIsKill, bool WantResult) {
1244 return emitAddsSubs_rr(false, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
1248 unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg,
1249 bool LHSIsKill, unsigned RHSReg,
1251 AArch64_AM::ShiftExtendType ShiftType,
1252 uint64_t ShiftImm, bool WantResult) {
1253 return emitAddsSubs_rs(false, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
1254 ShiftType, ShiftImm, WantResult);
1257 // FIXME: This should be eventually generated automatically by tblgen.
1258 unsigned AArch64FastISel::emitAND_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
1260 const TargetRegisterClass *RC = nullptr;
1262 unsigned RegSize = 0;
1263 switch (RetVT.SimpleTy) {
1267 Opc = AArch64::ANDWri;
1268 RC = &AArch64::GPR32spRegClass;
1272 Opc = AArch64::ANDXri;
1273 RC = &AArch64::GPR64spRegClass;
1278 if (!AArch64_AM::isLogicalImmediate(Imm, RegSize))
1281 return FastEmitInst_ri(Opc, RC, LHSReg, LHSIsKill,
1282 AArch64_AM::encodeLogicalImmediate(Imm, RegSize));
1285 bool AArch64FastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
1286 MachineMemOperand *MMO) {
1287 // Simplify this down to something we can handle.
1288 if (!SimplifyAddress(Addr, VT))
1291 unsigned ScaleFactor;
1292 switch (VT.SimpleTy) {
1293 default: llvm_unreachable("Unexpected value type.");
1294 case MVT::i1: // fall-through
1295 case MVT::i8: ScaleFactor = 1; break;
1296 case MVT::i16: ScaleFactor = 2; break;
1297 case MVT::i32: // fall-through
1298 case MVT::f32: ScaleFactor = 4; break;
1299 case MVT::i64: // fall-through
1300 case MVT::f64: ScaleFactor = 8; break;
1303 // Negative offsets require unscaled, 9-bit, signed immediate offsets.
1304 // Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
1305 bool UseScaled = true;
1306 if ((Addr.getOffset() < 0) || (Addr.getOffset() & (ScaleFactor - 1))) {
1311 static const unsigned OpcTable[4][6] = {
1312 { AArch64::LDURBBi, AArch64::LDURHHi, AArch64::LDURWi, AArch64::LDURXi,
1313 AArch64::LDURSi, AArch64::LDURDi },
1314 { AArch64::LDRBBui, AArch64::LDRHHui, AArch64::LDRWui, AArch64::LDRXui,
1315 AArch64::LDRSui, AArch64::LDRDui },
1316 { AArch64::LDRBBroX, AArch64::LDRHHroX, AArch64::LDRWroX, AArch64::LDRXroX,
1317 AArch64::LDRSroX, AArch64::LDRDroX },
1318 { AArch64::LDRBBroW, AArch64::LDRHHroW, AArch64::LDRWroW, AArch64::LDRXroW,
1319 AArch64::LDRSroW, AArch64::LDRDroW }
1323 const TargetRegisterClass *RC;
1324 bool VTIsi1 = false;
1325 bool UseRegOffset = Addr.isRegBase() && !Addr.getOffset() && Addr.getReg() &&
1326 Addr.getOffsetReg();
1327 unsigned Idx = UseRegOffset ? 2 : UseScaled ? 1 : 0;
1328 if (Addr.getExtendType() == AArch64_AM::UXTW ||
1329 Addr.getExtendType() == AArch64_AM::SXTW)
1332 switch (VT.SimpleTy) {
1333 default: llvm_unreachable("Unexpected value type.");
1334 case MVT::i1: VTIsi1 = true; // Intentional fall-through.
1335 case MVT::i8: Opc = OpcTable[Idx][0]; RC = &AArch64::GPR32RegClass; break;
1336 case MVT::i16: Opc = OpcTable[Idx][1]; RC = &AArch64::GPR32RegClass; break;
1337 case MVT::i32: Opc = OpcTable[Idx][2]; RC = &AArch64::GPR32RegClass; break;
1338 case MVT::i64: Opc = OpcTable[Idx][3]; RC = &AArch64::GPR64RegClass; break;
1339 case MVT::f32: Opc = OpcTable[Idx][4]; RC = &AArch64::FPR32RegClass; break;
1340 case MVT::f64: Opc = OpcTable[Idx][5]; RC = &AArch64::FPR64RegClass; break;
1343 // Create the base instruction, then add the operands.
1344 ResultReg = createResultReg(RC);
1345 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1346 TII.get(Opc), ResultReg);
1347 AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOLoad, ScaleFactor, MMO);
1349 // Loading an i1 requires special handling.
1351 unsigned ANDReg = emitAND_ri(MVT::i32, ResultReg, /*IsKill=*/true, 1);
1352 assert(ANDReg && "Unexpected AND instruction emission failure.");
1358 bool AArch64FastISel::SelectLoad(const Instruction *I) {
1360 // Verify we have a legal type before going any further. Currently, we handle
1361 // simple types that will directly fit in a register (i32/f32/i64/f64) or
1362 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
1363 if (!isLoadStoreTypeLegal(I->getType(), VT) || cast<LoadInst>(I)->isAtomic())
1366 // See if we can handle this address.
1368 if (!ComputeAddress(I->getOperand(0), Addr, I->getType()))
1372 if (!EmitLoad(VT, ResultReg, Addr, createMachineMemOperandFor(I)))
1375 UpdateValueMap(I, ResultReg);
1379 bool AArch64FastISel::EmitStore(MVT VT, unsigned SrcReg, Address Addr,
1380 MachineMemOperand *MMO) {
1381 // Simplify this down to something we can handle.
1382 if (!SimplifyAddress(Addr, VT))
1385 unsigned ScaleFactor;
1386 switch (VT.SimpleTy) {
1387 default: llvm_unreachable("Unexpected value type.");
1388 case MVT::i1: // fall-through
1389 case MVT::i8: ScaleFactor = 1; break;
1390 case MVT::i16: ScaleFactor = 2; break;
1391 case MVT::i32: // fall-through
1392 case MVT::f32: ScaleFactor = 4; break;
1393 case MVT::i64: // fall-through
1394 case MVT::f64: ScaleFactor = 8; break;
1397 // Negative offsets require unscaled, 9-bit, signed immediate offsets.
1398 // Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
1399 bool UseScaled = true;
1400 if ((Addr.getOffset() < 0) || (Addr.getOffset() & (ScaleFactor - 1))) {
1406 static const unsigned OpcTable[4][6] = {
1407 { AArch64::STURBBi, AArch64::STURHHi, AArch64::STURWi, AArch64::STURXi,
1408 AArch64::STURSi, AArch64::STURDi },
1409 { AArch64::STRBBui, AArch64::STRHHui, AArch64::STRWui, AArch64::STRXui,
1410 AArch64::STRSui, AArch64::STRDui },
1411 { AArch64::STRBBroX, AArch64::STRHHroX, AArch64::STRWroX, AArch64::STRXroX,
1412 AArch64::STRSroX, AArch64::STRDroX },
1413 { AArch64::STRBBroW, AArch64::STRHHroW, AArch64::STRWroW, AArch64::STRXroW,
1414 AArch64::STRSroW, AArch64::STRDroW }
1419 bool VTIsi1 = false;
1420 bool UseRegOffset = Addr.isRegBase() && !Addr.getOffset() && Addr.getReg() &&
1421 Addr.getOffsetReg();
1422 unsigned Idx = UseRegOffset ? 2 : UseScaled ? 1 : 0;
1423 if (Addr.getExtendType() == AArch64_AM::UXTW ||
1424 Addr.getExtendType() == AArch64_AM::SXTW)
1427 switch (VT.SimpleTy) {
1428 default: llvm_unreachable("Unexpected value type.");
1429 case MVT::i1: VTIsi1 = true;
1430 case MVT::i8: Opc = OpcTable[Idx][0]; break;
1431 case MVT::i16: Opc = OpcTable[Idx][1]; break;
1432 case MVT::i32: Opc = OpcTable[Idx][2]; break;
1433 case MVT::i64: Opc = OpcTable[Idx][3]; break;
1434 case MVT::f32: Opc = OpcTable[Idx][4]; break;
1435 case MVT::f64: Opc = OpcTable[Idx][5]; break;
1438 // Storing an i1 requires special handling.
1439 if (VTIsi1 && SrcReg != AArch64::WZR) {
1440 unsigned ANDReg = emitAND_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1);
1441 assert(ANDReg && "Unexpected AND instruction emission failure.");
1444 // Create the base instruction, then add the operands.
1445 const MCInstrDesc &II = TII.get(Opc);
1446 SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs());
1447 MachineInstrBuilder MIB =
1448 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(SrcReg);
1449 AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOStore, ScaleFactor, MMO);
1454 bool AArch64FastISel::SelectStore(const Instruction *I) {
1456 const Value *Op0 = I->getOperand(0);
1457 // Verify we have a legal type before going any further. Currently, we handle
1458 // simple types that will directly fit in a register (i32/f32/i64/f64) or
1459 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
1460 if (!isLoadStoreTypeLegal(Op0->getType(), VT) ||
1461 cast<StoreInst>(I)->isAtomic())
1464 // Get the value to be stored into a register. Use the zero register directly
1465 // when possible to avoid an unnecessary copy and a wasted register.
1466 unsigned SrcReg = 0;
1467 if (const auto *CI = dyn_cast<ConstantInt>(Op0)) {
1469 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
1470 } else if (const auto *CF = dyn_cast<ConstantFP>(Op0)) {
1471 if (CF->isZero() && !CF->isNegative()) {
1472 VT = MVT::getIntegerVT(VT.getSizeInBits());
1473 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
1478 SrcReg = getRegForValue(Op0);
1483 // See if we can handle this address.
1485 if (!ComputeAddress(I->getOperand(1), Addr, I->getOperand(0)->getType()))
1488 if (!EmitStore(VT, SrcReg, Addr, createMachineMemOperandFor(I)))
1493 static AArch64CC::CondCode getCompareCC(CmpInst::Predicate Pred) {
1495 case CmpInst::FCMP_ONE:
1496 case CmpInst::FCMP_UEQ:
1498 // AL is our "false" for now. The other two need more compares.
1499 return AArch64CC::AL;
1500 case CmpInst::ICMP_EQ:
1501 case CmpInst::FCMP_OEQ:
1502 return AArch64CC::EQ;
1503 case CmpInst::ICMP_SGT:
1504 case CmpInst::FCMP_OGT:
1505 return AArch64CC::GT;
1506 case CmpInst::ICMP_SGE:
1507 case CmpInst::FCMP_OGE:
1508 return AArch64CC::GE;
1509 case CmpInst::ICMP_UGT:
1510 case CmpInst::FCMP_UGT:
1511 return AArch64CC::HI;
1512 case CmpInst::FCMP_OLT:
1513 return AArch64CC::MI;
1514 case CmpInst::ICMP_ULE:
1515 case CmpInst::FCMP_OLE:
1516 return AArch64CC::LS;
1517 case CmpInst::FCMP_ORD:
1518 return AArch64CC::VC;
1519 case CmpInst::FCMP_UNO:
1520 return AArch64CC::VS;
1521 case CmpInst::FCMP_UGE:
1522 return AArch64CC::PL;
1523 case CmpInst::ICMP_SLT:
1524 case CmpInst::FCMP_ULT:
1525 return AArch64CC::LT;
1526 case CmpInst::ICMP_SLE:
1527 case CmpInst::FCMP_ULE:
1528 return AArch64CC::LE;
1529 case CmpInst::FCMP_UNE:
1530 case CmpInst::ICMP_NE:
1531 return AArch64CC::NE;
1532 case CmpInst::ICMP_UGE:
1533 return AArch64CC::HS;
1534 case CmpInst::ICMP_ULT:
1535 return AArch64CC::LO;
1539 bool AArch64FastISel::SelectBranch(const Instruction *I) {
1540 const BranchInst *BI = cast<BranchInst>(I);
1541 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1542 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1544 AArch64CC::CondCode CC = AArch64CC::NE;
1545 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1546 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1547 // We may not handle every CC for now.
1548 CC = getCompareCC(CI->getPredicate());
1549 if (CC == AArch64CC::AL)
1553 if (!emitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1557 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
1561 // Obtain the branch weight and add the TrueBB to the successor list.
1562 uint32_t BranchWeight = 0;
1564 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
1565 TBB->getBasicBlock());
1566 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
1568 FastEmitBranch(FBB, DbgLoc);
1571 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1573 if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1574 (isLoadStoreTypeLegal(TI->getOperand(0)->getType(), SrcVT))) {
1575 unsigned CondReg = getRegForValue(TI->getOperand(0));
1578 bool CondIsKill = hasTrivialKill(TI->getOperand(0));
1580 // Issue an extract_subreg to get the lower 32-bits.
1581 if (SrcVT == MVT::i64) {
1582 CondReg = FastEmitInst_extractsubreg(MVT::i32, CondReg, CondIsKill,
1587 unsigned ANDReg = emitAND_ri(MVT::i32, CondReg, CondIsKill, 1);
1588 assert(ANDReg && "Unexpected AND instruction emission failure.");
1589 emitICmp_ri(MVT::i32, ANDReg, /*IsKill=*/true, 0);
1591 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1592 std::swap(TBB, FBB);
1595 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
1599 // Obtain the branch weight and add the TrueBB to the successor list.
1600 uint32_t BranchWeight = 0;
1602 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
1603 TBB->getBasicBlock());
1604 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
1606 FastEmitBranch(FBB, DbgLoc);
1609 } else if (const ConstantInt *CI =
1610 dyn_cast<ConstantInt>(BI->getCondition())) {
1611 uint64_t Imm = CI->getZExtValue();
1612 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1613 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::B))
1616 // Obtain the branch weight and add the target to the successor list.
1617 uint32_t BranchWeight = 0;
1619 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
1620 Target->getBasicBlock());
1621 FuncInfo.MBB->addSuccessor(Target, BranchWeight);
1623 } else if (foldXALUIntrinsic(CC, I, BI->getCondition())) {
1624 // Fake request the condition, otherwise the intrinsic might be completely
1626 unsigned CondReg = getRegForValue(BI->getCondition());
1631 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
1635 // Obtain the branch weight and add the TrueBB to the successor list.
1636 uint32_t BranchWeight = 0;
1638 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
1639 TBB->getBasicBlock());
1640 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
1642 FastEmitBranch(FBB, DbgLoc);
1646 unsigned CondReg = getRegForValue(BI->getCondition());
1649 bool CondRegIsKill = hasTrivialKill(BI->getCondition());
1651 // We've been divorced from our compare! Our block was split, and
1652 // now our compare lives in a predecessor block. We musn't
1653 // re-compare here, as the children of the compare aren't guaranteed
1654 // live across the block boundary (we *could* check for this).
1655 // Regardless, the compare has been done in the predecessor block,
1656 // and it left a value for us in a virtual register. Ergo, we test
1657 // the one-bit value left in the virtual register.
1658 emitICmp_ri(MVT::i32, CondReg, CondRegIsKill, 0);
1660 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1661 std::swap(TBB, FBB);
1665 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
1669 // Obtain the branch weight and add the TrueBB to the successor list.
1670 uint32_t BranchWeight = 0;
1672 BranchWeight = FuncInfo.BPI->getEdgeWeight(BI->getParent(),
1673 TBB->getBasicBlock());
1674 FuncInfo.MBB->addSuccessor(TBB, BranchWeight);
1676 FastEmitBranch(FBB, DbgLoc);
1680 bool AArch64FastISel::SelectIndirectBr(const Instruction *I) {
1681 const IndirectBrInst *BI = cast<IndirectBrInst>(I);
1682 unsigned AddrReg = getRegForValue(BI->getOperand(0));
1686 // Emit the indirect branch.
1687 const MCInstrDesc &II = TII.get(AArch64::BR);
1688 AddrReg = constrainOperandRegClass(II, AddrReg, II.getNumDefs());
1689 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(AddrReg);
1691 // Make sure the CFG is up-to-date.
1692 for (unsigned i = 0, e = BI->getNumSuccessors(); i != e; ++i)
1693 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[BI->getSuccessor(i)]);
1698 bool AArch64FastISel::SelectCmp(const Instruction *I) {
1699 const CmpInst *CI = cast<CmpInst>(I);
1701 // We may not handle every CC for now.
1702 AArch64CC::CondCode CC = getCompareCC(CI->getPredicate());
1703 if (CC == AArch64CC::AL)
1707 if (!emitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1710 // Now set a register based on the comparison.
1711 AArch64CC::CondCode invertedCC = getInvertedCondCode(CC);
1712 unsigned ResultReg = createResultReg(&AArch64::GPR32RegClass);
1713 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
1715 .addReg(AArch64::WZR)
1716 .addReg(AArch64::WZR)
1717 .addImm(invertedCC);
1719 UpdateValueMap(I, ResultReg);
1723 bool AArch64FastISel::SelectSelect(const Instruction *I) {
1724 const SelectInst *SI = cast<SelectInst>(I);
1726 EVT DestEVT = TLI.getValueType(SI->getType(), true);
1727 if (!DestEVT.isSimple())
1730 MVT DestVT = DestEVT.getSimpleVT();
1731 if (DestVT != MVT::i32 && DestVT != MVT::i64 && DestVT != MVT::f32 &&
1736 const TargetRegisterClass *RC = nullptr;
1737 switch (DestVT.SimpleTy) {
1738 default: return false;
1740 SelectOpc = AArch64::CSELWr; RC = &AArch64::GPR32RegClass; break;
1742 SelectOpc = AArch64::CSELXr; RC = &AArch64::GPR64RegClass; break;
1744 SelectOpc = AArch64::FCSELSrrr; RC = &AArch64::FPR32RegClass; break;
1746 SelectOpc = AArch64::FCSELDrrr; RC = &AArch64::FPR64RegClass; break;
1749 const Value *Cond = SI->getCondition();
1750 bool NeedTest = true;
1751 AArch64CC::CondCode CC = AArch64CC::NE;
1752 if (foldXALUIntrinsic(CC, I, Cond))
1755 unsigned CondReg = getRegForValue(Cond);
1758 bool CondIsKill = hasTrivialKill(Cond);
1761 unsigned ANDReg = emitAND_ri(MVT::i32, CondReg, CondIsKill, 1);
1762 assert(ANDReg && "Unexpected AND instruction emission failure.");
1763 emitICmp_ri(MVT::i32, ANDReg, /*IsKill=*/true, 0);
1766 unsigned TrueReg = getRegForValue(SI->getTrueValue());
1767 bool TrueIsKill = hasTrivialKill(SI->getTrueValue());
1769 unsigned FalseReg = getRegForValue(SI->getFalseValue());
1770 bool FalseIsKill = hasTrivialKill(SI->getFalseValue());
1772 if (!TrueReg || !FalseReg)
1775 unsigned ResultReg = FastEmitInst_rri(SelectOpc, RC, TrueReg, TrueIsKill,
1776 FalseReg, FalseIsKill, CC);
1777 UpdateValueMap(I, ResultReg);
1781 bool AArch64FastISel::SelectFPExt(const Instruction *I) {
1782 Value *V = I->getOperand(0);
1783 if (!I->getType()->isDoubleTy() || !V->getType()->isFloatTy())
1786 unsigned Op = getRegForValue(V);
1790 unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass);
1791 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTDSr),
1792 ResultReg).addReg(Op);
1793 UpdateValueMap(I, ResultReg);
1797 bool AArch64FastISel::SelectFPTrunc(const Instruction *I) {
1798 Value *V = I->getOperand(0);
1799 if (!I->getType()->isFloatTy() || !V->getType()->isDoubleTy())
1802 unsigned Op = getRegForValue(V);
1806 unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass);
1807 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTSDr),
1808 ResultReg).addReg(Op);
1809 UpdateValueMap(I, ResultReg);
1813 // FPToUI and FPToSI
1814 bool AArch64FastISel::SelectFPToInt(const Instruction *I, bool Signed) {
1816 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
1819 unsigned SrcReg = getRegForValue(I->getOperand(0));
1823 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
1824 if (SrcVT == MVT::f128)
1828 if (SrcVT == MVT::f64) {
1830 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
1832 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
1835 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
1837 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
1839 unsigned ResultReg = createResultReg(
1840 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);
1841 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1843 UpdateValueMap(I, ResultReg);
1847 bool AArch64FastISel::SelectIntToFP(const Instruction *I, bool Signed) {
1849 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
1851 assert ((DestVT == MVT::f32 || DestVT == MVT::f64) &&
1852 "Unexpected value type.");
1854 unsigned SrcReg = getRegForValue(I->getOperand(0));
1857 bool SrcIsKill = hasTrivialKill(I->getOperand(0));
1859 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType(), true);
1861 // Handle sign-extension.
1862 if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) {
1864 EmitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);
1871 if (SrcVT == MVT::i64) {
1873 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;
1875 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;
1878 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;
1880 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;
1883 unsigned ResultReg = FastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg,
1885 UpdateValueMap(I, ResultReg);
1889 bool AArch64FastISel::FastLowerArguments() {
1890 if (!FuncInfo.CanLowerReturn)
1893 const Function *F = FuncInfo.Fn;
1897 CallingConv::ID CC = F->getCallingConv();
1898 if (CC != CallingConv::C)
1901 // Only handle simple cases like i1/i8/i16/i32/i64/f32/f64 of up to 8 GPR and
1903 unsigned GPRCnt = 0;
1904 unsigned FPRCnt = 0;
1906 for (auto const &Arg : F->args()) {
1907 // The first argument is at index 1.
1909 if (F->getAttributes().hasAttribute(Idx, Attribute::ByVal) ||
1910 F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
1911 F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
1912 F->getAttributes().hasAttribute(Idx, Attribute::Nest))
1915 Type *ArgTy = Arg.getType();
1916 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
1919 EVT ArgVT = TLI.getValueType(ArgTy);
1920 if (!ArgVT.isSimple()) return false;
1921 switch (ArgVT.getSimpleVT().SimpleTy) {
1922 default: return false;
1937 if (GPRCnt > 8 || FPRCnt > 8)
1941 static const MCPhysReg Registers[5][8] = {
1942 { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
1943 AArch64::W5, AArch64::W6, AArch64::W7 },
1944 { AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
1945 AArch64::X5, AArch64::X6, AArch64::X7 },
1946 { AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4,
1947 AArch64::H5, AArch64::H6, AArch64::H7 },
1948 { AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
1949 AArch64::S5, AArch64::S6, AArch64::S7 },
1950 { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
1951 AArch64::D5, AArch64::D6, AArch64::D7 }
1954 unsigned GPRIdx = 0;
1955 unsigned FPRIdx = 0;
1956 for (auto const &Arg : F->args()) {
1957 MVT VT = TLI.getSimpleValueType(Arg.getType());
1959 const TargetRegisterClass *RC = nullptr;
1960 switch (VT.SimpleTy) {
1961 default: llvm_unreachable("Unexpected value type.");
1964 case MVT::i16: VT = MVT::i32; // fall-through
1966 SrcReg = Registers[0][GPRIdx++]; RC = &AArch64::GPR32RegClass; break;
1968 SrcReg = Registers[1][GPRIdx++]; RC = &AArch64::GPR64RegClass; break;
1970 SrcReg = Registers[2][FPRIdx++]; RC = &AArch64::FPR16RegClass; break;
1972 SrcReg = Registers[3][FPRIdx++]; RC = &AArch64::FPR32RegClass; break;
1974 SrcReg = Registers[4][FPRIdx++]; RC = &AArch64::FPR64RegClass; break;
1977 // Skip unused arguments.
1978 if (Arg.use_empty()) {
1979 UpdateValueMap(&Arg, 0);
1983 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
1984 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
1985 // Without this, EmitLiveInCopies may eliminate the livein if its only
1986 // use is a bitcast (which isn't turned into an instruction).
1987 unsigned ResultReg = createResultReg(RC);
1988 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1989 TII.get(TargetOpcode::COPY), ResultReg)
1990 .addReg(DstReg, getKillRegState(true));
1991 UpdateValueMap(&Arg, ResultReg);
1996 bool AArch64FastISel::ProcessCallArgs(CallLoweringInfo &CLI,
1997 SmallVectorImpl<MVT> &OutVTs,
1998 unsigned &NumBytes) {
1999 CallingConv::ID CC = CLI.CallConv;
2000 SmallVector<CCValAssign, 16> ArgLocs;
2001 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
2002 CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
2004 // Get a count of how many bytes are to be pushed on the stack.
2005 NumBytes = CCInfo.getNextStackOffset();
2007 // Issue CALLSEQ_START
2008 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
2009 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
2012 // Process the args.
2013 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2014 CCValAssign &VA = ArgLocs[i];
2015 const Value *ArgVal = CLI.OutVals[VA.getValNo()];
2016 MVT ArgVT = OutVTs[VA.getValNo()];
2018 unsigned ArgReg = getRegForValue(ArgVal);
2022 // Handle arg promotion: SExt, ZExt, AExt.
2023 switch (VA.getLocInfo()) {
2024 case CCValAssign::Full:
2026 case CCValAssign::SExt: {
2027 MVT DestVT = VA.getLocVT();
2029 ArgReg = EmitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
2034 case CCValAssign::AExt:
2035 // Intentional fall-through.
2036 case CCValAssign::ZExt: {
2037 MVT DestVT = VA.getLocVT();
2039 ArgReg = EmitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
2045 llvm_unreachable("Unknown arg promotion!");
2048 // Now copy/store arg to correct locations.
2049 if (VA.isRegLoc() && !VA.needsCustom()) {
2050 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2051 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
2052 CLI.OutRegs.push_back(VA.getLocReg());
2053 } else if (VA.needsCustom()) {
2054 // FIXME: Handle custom args.
2057 assert(VA.isMemLoc() && "Assuming store on stack.");
2059 // Don't emit stores for undef values.
2060 if (isa<UndefValue>(ArgVal))
2063 // Need to store on the stack.
2064 unsigned ArgSize = (ArgVT.getSizeInBits() + 7) / 8;
2066 unsigned BEAlign = 0;
2067 if (ArgSize < 8 && !Subtarget->isLittleEndian())
2068 BEAlign = 8 - ArgSize;
2071 Addr.setKind(Address::RegBase);
2072 Addr.setReg(AArch64::SP);
2073 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
2075 unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
2076 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
2077 MachinePointerInfo::getStack(Addr.getOffset()),
2078 MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
2080 if (!EmitStore(ArgVT, ArgReg, Addr, MMO))
2087 bool AArch64FastISel::FinishCall(CallLoweringInfo &CLI, MVT RetVT,
2088 unsigned NumBytes) {
2089 CallingConv::ID CC = CLI.CallConv;
2091 // Issue CALLSEQ_END
2092 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2093 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
2094 .addImm(NumBytes).addImm(0);
2096 // Now the return value.
2097 if (RetVT != MVT::isVoid) {
2098 SmallVector<CCValAssign, 16> RVLocs;
2099 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
2100 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC));
2102 // Only handle a single return value.
2103 if (RVLocs.size() != 1)
2106 // Copy all of the result registers out of their specified physreg.
2107 MVT CopyVT = RVLocs[0].getValVT();
2108 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
2109 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2110 TII.get(TargetOpcode::COPY), ResultReg)
2111 .addReg(RVLocs[0].getLocReg());
2112 CLI.InRegs.push_back(RVLocs[0].getLocReg());
2114 CLI.ResultReg = ResultReg;
2115 CLI.NumResultRegs = 1;
2121 bool AArch64FastISel::FastLowerCall(CallLoweringInfo &CLI) {
2122 CallingConv::ID CC = CLI.CallConv;
2123 bool IsTailCall = CLI.IsTailCall;
2124 bool IsVarArg = CLI.IsVarArg;
2125 const Value *Callee = CLI.Callee;
2126 const char *SymName = CLI.SymName;
2128 // Allow SelectionDAG isel to handle tail calls.
2132 CodeModel::Model CM = TM.getCodeModel();
2133 // Only support the small and large code model.
2134 if (CM != CodeModel::Small && CM != CodeModel::Large)
2137 // FIXME: Add large code model support for ELF.
2138 if (CM == CodeModel::Large && !Subtarget->isTargetMachO())
2141 // Let SDISel handle vararg functions.
2145 // FIXME: Only handle *simple* calls for now.
2147 if (CLI.RetTy->isVoidTy())
2148 RetVT = MVT::isVoid;
2149 else if (!isTypeLegal(CLI.RetTy, RetVT))
2152 for (auto Flag : CLI.OutFlags)
2153 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
2156 // Set up the argument vectors.
2157 SmallVector<MVT, 16> OutVTs;
2158 OutVTs.reserve(CLI.OutVals.size());
2160 for (auto *Val : CLI.OutVals) {
2162 if (!isTypeLegal(Val->getType(), VT) &&
2163 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
2166 // We don't handle vector parameters yet.
2167 if (VT.isVector() || VT.getSizeInBits() > 64)
2170 OutVTs.push_back(VT);
2174 if (!ComputeCallAddress(Callee, Addr))
2177 // Handle the arguments now that we've gotten them.
2179 if (!ProcessCallArgs(CLI, OutVTs, NumBytes))
2183 MachineInstrBuilder MIB;
2184 if (CM == CodeModel::Small) {
2185 unsigned CallOpc = Addr.getReg() ? AArch64::BLR : AArch64::BL;
2186 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CallOpc));
2188 MIB.addExternalSymbol(SymName, 0);
2189 else if (Addr.getGlobalValue())
2190 MIB.addGlobalAddress(Addr.getGlobalValue(), 0, 0);
2191 else if (Addr.getReg())
2192 MIB.addReg(Addr.getReg());
2196 unsigned CallReg = 0;
2198 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
2199 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
2201 .addExternalSymbol(SymName, AArch64II::MO_GOT | AArch64II::MO_PAGE);
2203 CallReg = createResultReg(&AArch64::GPR64RegClass);
2204 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui),
2207 .addExternalSymbol(SymName, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF |
2209 } else if (Addr.getGlobalValue()) {
2210 CallReg = AArch64MaterializeGV(Addr.getGlobalValue());
2211 } else if (Addr.getReg())
2212 CallReg = Addr.getReg();
2217 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2218 TII.get(AArch64::BLR)).addReg(CallReg);
2221 // Add implicit physical register uses to the call.
2222 for (auto Reg : CLI.OutRegs)
2223 MIB.addReg(Reg, RegState::Implicit);
2225 // Add a register mask with the call-preserved registers.
2226 // Proper defs for return values will be added by setPhysRegsDeadExcept().
2227 MIB.addRegMask(TRI.getCallPreservedMask(CC));
2231 // Finish off the call including any return values.
2232 return FinishCall(CLI, RetVT, NumBytes);
2235 bool AArch64FastISel::IsMemCpySmall(uint64_t Len, unsigned Alignment) {
2237 return Len / Alignment <= 4;
2242 bool AArch64FastISel::TryEmitSmallMemCpy(Address Dest, Address Src,
2243 uint64_t Len, unsigned Alignment) {
2244 // Make sure we don't bloat code by inlining very large memcpy's.
2245 if (!IsMemCpySmall(Len, Alignment))
2248 int64_t UnscaledOffset = 0;
2249 Address OrigDest = Dest;
2250 Address OrigSrc = Src;
2254 if (!Alignment || Alignment >= 8) {
2265 // Bound based on alignment.
2266 if (Len >= 4 && Alignment == 4)
2268 else if (Len >= 2 && Alignment == 2)
2277 RV = EmitLoad(VT, ResultReg, Src);
2281 RV = EmitStore(VT, ResultReg, Dest);
2285 int64_t Size = VT.getSizeInBits() / 8;
2287 UnscaledOffset += Size;
2289 // We need to recompute the unscaled offset for each iteration.
2290 Dest.setOffset(OrigDest.getOffset() + UnscaledOffset);
2291 Src.setOffset(OrigSrc.getOffset() + UnscaledOffset);
2297 /// \brief Check if it is possible to fold the condition from the XALU intrinsic
2298 /// into the user. The condition code will only be updated on success.
2299 bool AArch64FastISel::foldXALUIntrinsic(AArch64CC::CondCode &CC,
2300 const Instruction *I,
2301 const Value *Cond) {
2302 if (!isa<ExtractValueInst>(Cond))
2305 const auto *EV = cast<ExtractValueInst>(Cond);
2306 if (!isa<IntrinsicInst>(EV->getAggregateOperand()))
2309 const auto *II = cast<IntrinsicInst>(EV->getAggregateOperand());
2311 const Function *Callee = II->getCalledFunction();
2313 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(0U);
2314 if (!isTypeLegal(RetTy, RetVT))
2317 if (RetVT != MVT::i32 && RetVT != MVT::i64)
2320 AArch64CC::CondCode TmpCC;
2321 switch (II->getIntrinsicID()) {
2322 default: return false;
2323 case Intrinsic::sadd_with_overflow:
2324 case Intrinsic::ssub_with_overflow: TmpCC = AArch64CC::VS; break;
2325 case Intrinsic::uadd_with_overflow: TmpCC = AArch64CC::HS; break;
2326 case Intrinsic::usub_with_overflow: TmpCC = AArch64CC::LO; break;
2327 case Intrinsic::smul_with_overflow:
2328 case Intrinsic::umul_with_overflow: TmpCC = AArch64CC::NE; break;
2331 // Check if both instructions are in the same basic block.
2332 if (II->getParent() != I->getParent())
2335 // Make sure nothing is in the way
2336 BasicBlock::const_iterator Start = I;
2337 BasicBlock::const_iterator End = II;
2338 for (auto Itr = std::prev(Start); Itr != End; --Itr) {
2339 // We only expect extractvalue instructions between the intrinsic and the
2340 // instruction to be selected.
2341 if (!isa<ExtractValueInst>(Itr))
2344 // Check that the extractvalue operand comes from the intrinsic.
2345 const auto *EVI = cast<ExtractValueInst>(Itr);
2346 if (EVI->getAggregateOperand() != II)
2354 bool AArch64FastISel::FastLowerIntrinsicCall(const IntrinsicInst *II) {
2355 // FIXME: Handle more intrinsics.
2356 switch (II->getIntrinsicID()) {
2357 default: return false;
2358 case Intrinsic::frameaddress: {
2359 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
2360 MFI->setFrameAddressIsTaken(true);
2362 const AArch64RegisterInfo *RegInfo =
2363 static_cast<const AArch64RegisterInfo *>(
2364 TM.getSubtargetImpl()->getRegisterInfo());
2365 unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2366 unsigned SrcReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
2367 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2368 TII.get(TargetOpcode::COPY), SrcReg).addReg(FramePtr);
2369 // Recursively load frame address
2375 unsigned Depth = cast<ConstantInt>(II->getOperand(0))->getZExtValue();
2377 DestReg = FastEmitInst_ri(AArch64::LDRXui, &AArch64::GPR64RegClass,
2378 SrcReg, /*IsKill=*/true, 0);
2379 assert(DestReg && "Unexpected LDR instruction emission failure.");
2383 UpdateValueMap(II, SrcReg);
2386 case Intrinsic::memcpy:
2387 case Intrinsic::memmove: {
2388 const auto *MTI = cast<MemTransferInst>(II);
2389 // Don't handle volatile.
2390 if (MTI->isVolatile())
2393 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
2394 // we would emit dead code because we don't currently handle memmoves.
2395 bool IsMemCpy = (II->getIntrinsicID() == Intrinsic::memcpy);
2396 if (isa<ConstantInt>(MTI->getLength()) && IsMemCpy) {
2397 // Small memcpy's are common enough that we want to do them without a call
2399 uint64_t Len = cast<ConstantInt>(MTI->getLength())->getZExtValue();
2400 unsigned Alignment = MTI->getAlignment();
2401 if (IsMemCpySmall(Len, Alignment)) {
2403 if (!ComputeAddress(MTI->getRawDest(), Dest) ||
2404 !ComputeAddress(MTI->getRawSource(), Src))
2406 if (TryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2411 if (!MTI->getLength()->getType()->isIntegerTy(64))
2414 if (MTI->getSourceAddressSpace() > 255 || MTI->getDestAddressSpace() > 255)
2415 // Fast instruction selection doesn't support the special
2419 const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
2420 return LowerCallTo(II, IntrMemName, II->getNumArgOperands() - 2);
2422 case Intrinsic::memset: {
2423 const MemSetInst *MSI = cast<MemSetInst>(II);
2424 // Don't handle volatile.
2425 if (MSI->isVolatile())
2428 if (!MSI->getLength()->getType()->isIntegerTy(64))
2431 if (MSI->getDestAddressSpace() > 255)
2432 // Fast instruction selection doesn't support the special
2436 return LowerCallTo(II, "memset", II->getNumArgOperands() - 2);
2438 case Intrinsic::trap: {
2439 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BRK))
2443 case Intrinsic::sqrt: {
2444 Type *RetTy = II->getCalledFunction()->getReturnType();
2447 if (!isTypeLegal(RetTy, VT))
2450 unsigned Op0Reg = getRegForValue(II->getOperand(0));
2453 bool Op0IsKill = hasTrivialKill(II->getOperand(0));
2455 unsigned ResultReg = FastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill);
2459 UpdateValueMap(II, ResultReg);
2462 case Intrinsic::sadd_with_overflow:
2463 case Intrinsic::uadd_with_overflow:
2464 case Intrinsic::ssub_with_overflow:
2465 case Intrinsic::usub_with_overflow:
2466 case Intrinsic::smul_with_overflow:
2467 case Intrinsic::umul_with_overflow: {
2468 // This implements the basic lowering of the xalu with overflow intrinsics.
2469 const Function *Callee = II->getCalledFunction();
2470 auto *Ty = cast<StructType>(Callee->getReturnType());
2471 Type *RetTy = Ty->getTypeAtIndex(0U);
2474 if (!isTypeLegal(RetTy, VT))
2477 if (VT != MVT::i32 && VT != MVT::i64)
2480 const Value *LHS = II->getArgOperand(0);
2481 const Value *RHS = II->getArgOperand(1);
2482 // Canonicalize immediate to the RHS.
2483 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS) &&
2484 isCommutativeIntrinsic(II))
2485 std::swap(LHS, RHS);
2487 unsigned ResultReg1 = 0, ResultReg2 = 0, MulReg = 0;
2488 AArch64CC::CondCode CC = AArch64CC::Invalid;
2489 switch (II->getIntrinsicID()) {
2490 default: llvm_unreachable("Unexpected intrinsic!");
2491 case Intrinsic::sadd_with_overflow:
2492 ResultReg1 = emitAdds(VT, LHS, RHS); CC = AArch64CC::VS; break;
2493 case Intrinsic::uadd_with_overflow:
2494 ResultReg1 = emitAdds(VT, LHS, RHS); CC = AArch64CC::HS; break;
2495 case Intrinsic::ssub_with_overflow:
2496 ResultReg1 = emitSubs(VT, LHS, RHS); CC = AArch64CC::VS; break;
2497 case Intrinsic::usub_with_overflow:
2498 ResultReg1 = emitSubs(VT, LHS, RHS); CC = AArch64CC::LO; break;
2499 case Intrinsic::smul_with_overflow: {
2501 unsigned LHSReg = getRegForValue(LHS);
2504 bool LHSIsKill = hasTrivialKill(LHS);
2506 unsigned RHSReg = getRegForValue(RHS);
2509 bool RHSIsKill = hasTrivialKill(RHS);
2511 if (VT == MVT::i32) {
2512 MulReg = Emit_SMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
2513 unsigned ShiftReg = emitLSR_ri(MVT::i64, MVT::i64, MulReg,
2514 /*IsKill=*/false, 32);
2515 MulReg = FastEmitInst_extractsubreg(VT, MulReg, /*IsKill=*/true,
2517 ShiftReg = FastEmitInst_extractsubreg(VT, ShiftReg, /*IsKill=*/true,
2519 emitSubs_rs(VT, ShiftReg, /*IsKill=*/true, MulReg, /*IsKill=*/false,
2520 AArch64_AM::ASR, 31, /*WantResult=*/false);
2522 assert(VT == MVT::i64 && "Unexpected value type.");
2523 MulReg = Emit_MUL_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
2524 unsigned SMULHReg = FastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill,
2526 emitSubs_rs(VT, SMULHReg, /*IsKill=*/true, MulReg, /*IsKill=*/false,
2527 AArch64_AM::ASR, 63, /*WantResult=*/false);
2531 case Intrinsic::umul_with_overflow: {
2533 unsigned LHSReg = getRegForValue(LHS);
2536 bool LHSIsKill = hasTrivialKill(LHS);
2538 unsigned RHSReg = getRegForValue(RHS);
2541 bool RHSIsKill = hasTrivialKill(RHS);
2543 if (VT == MVT::i32) {
2544 MulReg = Emit_UMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
2545 emitSubs_rs(MVT::i64, AArch64::XZR, /*IsKill=*/true, MulReg,
2546 /*IsKill=*/false, AArch64_AM::LSR, 32,
2547 /*WantResult=*/false);
2548 MulReg = FastEmitInst_extractsubreg(VT, MulReg, /*IsKill=*/true,
2551 assert(VT == MVT::i64 && "Unexpected value type.");
2552 MulReg = Emit_MUL_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
2553 unsigned UMULHReg = FastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill,
2555 emitSubs_rr(VT, AArch64::XZR, /*IsKill=*/true, UMULHReg,
2556 /*IsKill=*/false, /*WantResult=*/false);
2563 ResultReg1 = createResultReg(TLI.getRegClassFor(VT));
2564 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2565 TII.get(TargetOpcode::COPY), ResultReg1).addReg(MulReg);
2568 ResultReg2 = FastEmitInst_rri(AArch64::CSINCWr, &AArch64::GPR32RegClass,
2569 AArch64::WZR, /*IsKill=*/true, AArch64::WZR,
2570 /*IsKill=*/true, getInvertedCondCode(CC));
2571 assert((ResultReg1 + 1) == ResultReg2 &&
2572 "Nonconsecutive result registers.");
2573 UpdateValueMap(II, ResultReg1, 2);
2580 bool AArch64FastISel::SelectRet(const Instruction *I) {
2581 const ReturnInst *Ret = cast<ReturnInst>(I);
2582 const Function &F = *I->getParent()->getParent();
2584 if (!FuncInfo.CanLowerReturn)
2590 // Build a list of return value registers.
2591 SmallVector<unsigned, 4> RetRegs;
2593 if (Ret->getNumOperands() > 0) {
2594 CallingConv::ID CC = F.getCallingConv();
2595 SmallVector<ISD::OutputArg, 4> Outs;
2596 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
2598 // Analyze operands of the call, assigning locations to each operand.
2599 SmallVector<CCValAssign, 16> ValLocs;
2600 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext());
2601 CCAssignFn *RetCC = CC == CallingConv::WebKit_JS ? RetCC_AArch64_WebKit_JS
2602 : RetCC_AArch64_AAPCS;
2603 CCInfo.AnalyzeReturn(Outs, RetCC);
2605 // Only handle a single return value for now.
2606 if (ValLocs.size() != 1)
2609 CCValAssign &VA = ValLocs[0];
2610 const Value *RV = Ret->getOperand(0);
2612 // Don't bother handling odd stuff for now.
2613 if (VA.getLocInfo() != CCValAssign::Full)
2615 // Only handle register returns for now.
2618 unsigned Reg = getRegForValue(RV);
2622 unsigned SrcReg = Reg + VA.getValNo();
2623 unsigned DestReg = VA.getLocReg();
2624 // Avoid a cross-class copy. This is very unlikely.
2625 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
2628 EVT RVEVT = TLI.getValueType(RV->getType());
2629 if (!RVEVT.isSimple())
2632 // Vectors (of > 1 lane) in big endian need tricky handling.
2633 if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1)
2636 MVT RVVT = RVEVT.getSimpleVT();
2637 if (RVVT == MVT::f128)
2639 MVT DestVT = VA.getValVT();
2640 // Special handling for extended integers.
2641 if (RVVT != DestVT) {
2642 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2645 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
2648 bool isZExt = Outs[0].Flags.isZExt();
2649 SrcReg = EmitIntExt(RVVT, SrcReg, DestVT, isZExt);
2655 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2656 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
2658 // Add register to return instruction.
2659 RetRegs.push_back(VA.getLocReg());
2662 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2663 TII.get(AArch64::RET_ReallyLR));
2664 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
2665 MIB.addReg(RetRegs[i], RegState::Implicit);
2669 bool AArch64FastISel::SelectTrunc(const Instruction *I) {
2670 Type *DestTy = I->getType();
2671 Value *Op = I->getOperand(0);
2672 Type *SrcTy = Op->getType();
2674 EVT SrcEVT = TLI.getValueType(SrcTy, true);
2675 EVT DestEVT = TLI.getValueType(DestTy, true);
2676 if (!SrcEVT.isSimple())
2678 if (!DestEVT.isSimple())
2681 MVT SrcVT = SrcEVT.getSimpleVT();
2682 MVT DestVT = DestEVT.getSimpleVT();
2684 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
2687 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&
2691 unsigned SrcReg = getRegForValue(Op);
2694 bool SrcIsKill = hasTrivialKill(Op);
2696 // If we're truncating from i64 to a smaller non-legal type then generate an
2697 // AND. Otherwise, we know the high bits are undefined and a truncate only
2698 // generate a COPY. We cannot mark the source register also as result
2699 // register, because this can incorrectly transfer the kill flag onto the
2702 if (SrcVT == MVT::i64) {
2704 switch (DestVT.SimpleTy) {
2706 // Trunc i64 to i32 is handled by the target-independent fast-isel.
2718 // Issue an extract_subreg to get the lower 32-bits.
2719 unsigned Reg32 = FastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill,
2721 // Create the AND instruction which performs the actual truncation.
2722 ResultReg = emitAND_ri(MVT::i32, Reg32, /*IsKill=*/true, Mask);
2723 assert(ResultReg && "Unexpected AND instruction emission failure.");
2725 ResultReg = createResultReg(&AArch64::GPR32RegClass);
2726 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2727 TII.get(TargetOpcode::COPY), ResultReg)
2728 .addReg(SrcReg, getKillRegState(SrcIsKill));
2731 UpdateValueMap(I, ResultReg);
2735 unsigned AArch64FastISel::Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt) {
2736 assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
2737 DestVT == MVT::i64) &&
2738 "Unexpected value type.");
2739 // Handle i8 and i16 as i32.
2740 if (DestVT == MVT::i8 || DestVT == MVT::i16)
2744 unsigned ResultReg = emitAND_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1);
2745 assert(ResultReg && "Unexpected AND instruction emission failure.");
2746 if (DestVT == MVT::i64) {
2747 // We're ZExt i1 to i64. The ANDWri Wd, Ws, #1 implicitly clears the
2748 // upper 32 bits. Emit a SUBREG_TO_REG to extend from Wd to Xd.
2749 unsigned Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
2750 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2751 TII.get(AArch64::SUBREG_TO_REG), Reg64)
2754 .addImm(AArch64::sub_32);
2759 if (DestVT == MVT::i64) {
2760 // FIXME: We're SExt i1 to i64.
2763 return FastEmitInst_rii(AArch64::SBFMWri, &AArch64::GPR32RegClass, SrcReg,
2764 /*TODO:IsKill=*/false, 0, 0);
2768 unsigned AArch64FastISel::Emit_MUL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
2769 unsigned Op1, bool Op1IsKill) {
2771 switch (RetVT.SimpleTy) {
2777 Opc = AArch64::MADDWrrr; ZReg = AArch64::WZR; break;
2779 Opc = AArch64::MADDXrrr; ZReg = AArch64::XZR; break;
2782 const TargetRegisterClass *RC =
2783 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
2784 return FastEmitInst_rrr(Opc, RC, Op0, Op0IsKill, Op1, Op1IsKill,
2785 /*IsKill=*/ZReg, true);
2788 unsigned AArch64FastISel::Emit_SMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
2789 unsigned Op1, bool Op1IsKill) {
2790 if (RetVT != MVT::i64)
2793 return FastEmitInst_rrr(AArch64::SMADDLrrr, &AArch64::GPR64RegClass,
2794 Op0, Op0IsKill, Op1, Op1IsKill,
2795 AArch64::XZR, /*IsKill=*/true);
2798 unsigned AArch64FastISel::Emit_UMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
2799 unsigned Op1, bool Op1IsKill) {
2800 if (RetVT != MVT::i64)
2803 return FastEmitInst_rrr(AArch64::UMADDLrrr, &AArch64::GPR64RegClass,
2804 Op0, Op0IsKill, Op1, Op1IsKill,
2805 AArch64::XZR, /*IsKill=*/true);
2808 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
2809 unsigned Op1Reg, bool Op1IsKill) {
2811 bool NeedTrunc = false;
2813 switch (RetVT.SimpleTy) {
2815 case MVT::i8: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xff; break;
2816 case MVT::i16: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xffff; break;
2817 case MVT::i32: Opc = AArch64::LSLVWr; break;
2818 case MVT::i64: Opc = AArch64::LSLVXr; break;
2821 const TargetRegisterClass *RC =
2822 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
2824 Op1Reg = emitAND_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
2827 unsigned ResultReg = FastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
2830 ResultReg = emitAND_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
2834 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
2835 bool Op0IsKill, uint64_t Shift,
2837 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
2838 "Unexpected source/return type pair.");
2839 assert((SrcVT == MVT::i8 || SrcVT == MVT::i16 || SrcVT == MVT::i32 ||
2840 SrcVT == MVT::i64) && "Unexpected source value type.");
2841 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
2842 RetVT == MVT::i64) && "Unexpected return value type.");
2844 bool Is64Bit = (RetVT == MVT::i64);
2845 unsigned RegSize = Is64Bit ? 64 : 32;
2846 unsigned DstBits = RetVT.getSizeInBits();
2847 unsigned SrcBits = SrcVT.getSizeInBits();
2849 // Don't deal with undefined shifts.
2850 if (Shift >= DstBits)
2853 // For immediate shifts we can fold the zero-/sign-extension into the shift.
2854 // {S|U}BFM Wd, Wn, #r, #s
2855 // Wd<32+s-r,32-r> = Wn<s:0> when r > s
2857 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
2858 // %2 = shl i16 %1, 4
2859 // Wd<32+7-28,32-28> = Wn<7:0> <- clamp s to 7
2860 // 0b1111_1111_1111_1111__1111_1010_1010_0000 sext
2861 // 0b0000_0000_0000_0000__0000_0101_0101_0000 sext | zext
2862 // 0b0000_0000_0000_0000__0000_1010_1010_0000 zext
2864 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
2865 // %2 = shl i16 %1, 8
2866 // Wd<32+7-24,32-24> = Wn<7:0>
2867 // 0b1111_1111_1111_1111__1010_1010_0000_0000 sext
2868 // 0b0000_0000_0000_0000__0101_0101_0000_0000 sext | zext
2869 // 0b0000_0000_0000_0000__1010_1010_0000_0000 zext
2871 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
2872 // %2 = shl i16 %1, 12
2873 // Wd<32+3-20,32-20> = Wn<3:0>
2874 // 0b1111_1111_1111_1111__1010_0000_0000_0000 sext
2875 // 0b0000_0000_0000_0000__0101_0000_0000_0000 sext | zext
2876 // 0b0000_0000_0000_0000__1010_0000_0000_0000 zext
2878 unsigned ImmR = RegSize - Shift;
2879 // Limit the width to the length of the source type.
2880 unsigned ImmS = std::min<unsigned>(SrcBits - 1, DstBits - 1 - Shift);
2881 static const unsigned OpcTable[2][2] = {
2882 {AArch64::SBFMWri, AArch64::SBFMXri},
2883 {AArch64::UBFMWri, AArch64::UBFMXri}
2885 unsigned Opc = OpcTable[IsZext][Is64Bit];
2886 const TargetRegisterClass *RC =
2887 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
2888 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
2889 unsigned TmpReg = MRI.createVirtualRegister(RC);
2890 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2891 TII.get(AArch64::SUBREG_TO_REG), TmpReg)
2893 .addReg(Op0, getKillRegState(Op0IsKill))
2894 .addImm(AArch64::sub_32);
2898 return FastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
2901 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
2902 unsigned Op1Reg, bool Op1IsKill) {
2904 bool NeedTrunc = false;
2906 switch (RetVT.SimpleTy) {
2908 case MVT::i8: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xff; break;
2909 case MVT::i16: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xffff; break;
2910 case MVT::i32: Opc = AArch64::LSRVWr; break;
2911 case MVT::i64: Opc = AArch64::LSRVXr; break;
2914 const TargetRegisterClass *RC =
2915 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
2917 Op0Reg = emitAND_ri(MVT::i32, Op0Reg, Op0IsKill, Mask);
2918 Op1Reg = emitAND_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
2919 Op0IsKill = Op1IsKill = true;
2921 unsigned ResultReg = FastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
2924 ResultReg = emitAND_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
2928 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
2929 bool Op0IsKill, uint64_t Shift,
2931 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
2932 "Unexpected source/return type pair.");
2933 assert((SrcVT == MVT::i8 || SrcVT == MVT::i16 || SrcVT == MVT::i32 ||
2934 SrcVT == MVT::i64) && "Unexpected source value type.");
2935 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
2936 RetVT == MVT::i64) && "Unexpected return value type.");
2938 bool Is64Bit = (RetVT == MVT::i64);
2939 unsigned RegSize = Is64Bit ? 64 : 32;
2940 unsigned DstBits = RetVT.getSizeInBits();
2941 unsigned SrcBits = SrcVT.getSizeInBits();
2943 // Don't deal with undefined shifts.
2944 if (Shift >= DstBits)
2947 // For immediate shifts we can fold the zero-/sign-extension into the shift.
2948 // {S|U}BFM Wd, Wn, #r, #s
2949 // Wd<s-r:0> = Wn<s:r> when r <= s
2951 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
2952 // %2 = lshr i16 %1, 4
2953 // Wd<7-4:0> = Wn<7:4>
2954 // 0b0000_0000_0000_0000__0000_1111_1111_1010 sext
2955 // 0b0000_0000_0000_0000__0000_0000_0000_0101 sext | zext
2956 // 0b0000_0000_0000_0000__0000_0000_0000_1010 zext
2958 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
2959 // %2 = lshr i16 %1, 8
2960 // Wd<7-7,0> = Wn<7:7>
2961 // 0b0000_0000_0000_0000__0000_0000_1111_1111 sext
2962 // 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
2963 // 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
2965 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
2966 // %2 = lshr i16 %1, 12
2967 // Wd<7-7,0> = Wn<7:7> <- clamp r to 7
2968 // 0b0000_0000_0000_0000__0000_0000_0000_1111 sext
2969 // 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
2970 // 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
2972 if (Shift >= SrcBits && IsZExt)
2973 return AArch64MaterializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)),
2976 // It is not possible to fold a sign-extend into the LShr instruction. In this
2977 // case emit a sign-extend.
2979 Op0 = EmitIntExt(SrcVT, Op0, RetVT, IsZExt);
2984 SrcBits = SrcVT.getSizeInBits();
2988 unsigned ImmR = std::min<unsigned>(SrcBits - 1, Shift);
2989 unsigned ImmS = SrcBits - 1;
2990 static const unsigned OpcTable[2][2] = {
2991 {AArch64::SBFMWri, AArch64::SBFMXri},
2992 {AArch64::UBFMWri, AArch64::UBFMXri}
2994 unsigned Opc = OpcTable[IsZExt][Is64Bit];
2995 const TargetRegisterClass *RC =
2996 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
2997 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
2998 unsigned TmpReg = MRI.createVirtualRegister(RC);
2999 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3000 TII.get(AArch64::SUBREG_TO_REG), TmpReg)
3002 .addReg(Op0, getKillRegState(Op0IsKill))
3003 .addImm(AArch64::sub_32);
3007 return FastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
3010 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
3011 unsigned Op1Reg, bool Op1IsKill) {
3013 bool NeedTrunc = false;
3015 switch (RetVT.SimpleTy) {
3017 case MVT::i8: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xff; break;
3018 case MVT::i16: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xffff; break;
3019 case MVT::i32: Opc = AArch64::ASRVWr; break;
3020 case MVT::i64: Opc = AArch64::ASRVXr; break;
3023 const TargetRegisterClass *RC =
3024 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3026 Op0Reg = EmitIntExt(RetVT, Op0Reg, MVT::i32, /*IsZExt=*/false);
3027 Op1Reg = emitAND_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
3028 Op0IsKill = Op1IsKill = true;
3030 unsigned ResultReg = FastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
3033 ResultReg = emitAND_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
3037 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
3038 bool Op0IsKill, uint64_t Shift,
3040 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
3041 "Unexpected source/return type pair.");
3042 assert((SrcVT == MVT::i8 || SrcVT == MVT::i16 || SrcVT == MVT::i32 ||
3043 SrcVT == MVT::i64) && "Unexpected source value type.");
3044 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
3045 RetVT == MVT::i64) && "Unexpected return value type.");
3047 bool Is64Bit = (RetVT == MVT::i64);
3048 unsigned RegSize = Is64Bit ? 64 : 32;
3049 unsigned DstBits = RetVT.getSizeInBits();
3050 unsigned SrcBits = SrcVT.getSizeInBits();
3052 // Don't deal with undefined shifts.
3053 if (Shift >= DstBits)
3056 // For immediate shifts we can fold the zero-/sign-extension into the shift.
3057 // {S|U}BFM Wd, Wn, #r, #s
3058 // Wd<s-r:0> = Wn<s:r> when r <= s
3060 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3061 // %2 = ashr i16 %1, 4
3062 // Wd<7-4:0> = Wn<7:4>
3063 // 0b1111_1111_1111_1111__1111_1111_1111_1010 sext
3064 // 0b0000_0000_0000_0000__0000_0000_0000_0101 sext | zext
3065 // 0b0000_0000_0000_0000__0000_0000_0000_1010 zext
3067 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3068 // %2 = ashr i16 %1, 8
3069 // Wd<7-7,0> = Wn<7:7>
3070 // 0b1111_1111_1111_1111__1111_1111_1111_1111 sext
3071 // 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
3072 // 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
3074 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3075 // %2 = ashr i16 %1, 12
3076 // Wd<7-7,0> = Wn<7:7> <- clamp r to 7
3077 // 0b1111_1111_1111_1111__1111_1111_1111_1111 sext
3078 // 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
3079 // 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
3081 if (Shift >= SrcBits && IsZExt)
3082 return AArch64MaterializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)),
3085 unsigned ImmR = std::min<unsigned>(SrcBits - 1, Shift);
3086 unsigned ImmS = SrcBits - 1;
3087 static const unsigned OpcTable[2][2] = {
3088 {AArch64::SBFMWri, AArch64::SBFMXri},
3089 {AArch64::UBFMWri, AArch64::UBFMXri}
3091 unsigned Opc = OpcTable[IsZExt][Is64Bit];
3092 const TargetRegisterClass *RC =
3093 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3094 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
3095 unsigned TmpReg = MRI.createVirtualRegister(RC);
3096 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3097 TII.get(AArch64::SUBREG_TO_REG), TmpReg)
3099 .addReg(Op0, getKillRegState(Op0IsKill))
3100 .addImm(AArch64::sub_32);
3104 return FastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
3107 unsigned AArch64FastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
3109 assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");
3111 // FastISel does not have plumbing to deal with extensions where the SrcVT or
3112 // DestVT are odd things, so test to make sure that they are both types we can
3113 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
3114 // bail out to SelectionDAG.
3115 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) &&
3116 (DestVT != MVT::i32) && (DestVT != MVT::i64)) ||
3117 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) &&
3118 (SrcVT != MVT::i16) && (SrcVT != MVT::i32)))
3124 switch (SrcVT.SimpleTy) {
3128 return Emiti1Ext(SrcReg, DestVT, isZExt);
3130 if (DestVT == MVT::i64)
3131 Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
3133 Opc = isZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
3137 if (DestVT == MVT::i64)
3138 Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
3140 Opc = isZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
3144 assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");
3145 Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
3150 // Handle i8 and i16 as i32.
3151 if (DestVT == MVT::i8 || DestVT == MVT::i16)
3153 else if (DestVT == MVT::i64) {
3154 unsigned Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
3155 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3156 TII.get(AArch64::SUBREG_TO_REG), Src64)
3159 .addImm(AArch64::sub_32);
3163 const TargetRegisterClass *RC =
3164 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3165 return FastEmitInst_rii(Opc, RC, SrcReg, /*TODO:IsKill=*/false, 0, Imm);
3168 bool AArch64FastISel::SelectIntExt(const Instruction *I) {
3169 // On ARM, in general, integer casts don't involve legal types; this code
3170 // handles promotable integers. The high bits for a type smaller than
3171 // the register size are assumed to be undefined.
3172 Type *DestTy = I->getType();
3173 Value *Src = I->getOperand(0);
3174 Type *SrcTy = Src->getType();
3176 bool isZExt = isa<ZExtInst>(I);
3177 unsigned SrcReg = getRegForValue(Src);
3181 EVT SrcEVT = TLI.getValueType(SrcTy, true);
3182 EVT DestEVT = TLI.getValueType(DestTy, true);
3183 if (!SrcEVT.isSimple())
3185 if (!DestEVT.isSimple())
3188 MVT SrcVT = SrcEVT.getSimpleVT();
3189 MVT DestVT = DestEVT.getSimpleVT();
3190 unsigned ResultReg = 0;
3192 // Check if it is an argument and if it is already zero/sign-extended.
3193 if (const auto *Arg = dyn_cast<Argument>(Src)) {
3194 if ((isZExt && Arg->hasZExtAttr()) || (!isZExt && Arg->hasSExtAttr())) {
3195 if (DestVT == MVT::i64) {
3196 ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
3197 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3198 TII.get(AArch64::SUBREG_TO_REG), ResultReg)
3201 .addImm(AArch64::sub_32);
3208 ResultReg = EmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
3213 UpdateValueMap(I, ResultReg);
3217 bool AArch64FastISel::SelectRem(const Instruction *I, unsigned ISDOpcode) {
3218 EVT DestEVT = TLI.getValueType(I->getType(), true);
3219 if (!DestEVT.isSimple())
3222 MVT DestVT = DestEVT.getSimpleVT();
3223 if (DestVT != MVT::i64 && DestVT != MVT::i32)
3227 bool is64bit = (DestVT == MVT::i64);
3228 switch (ISDOpcode) {
3232 DivOpc = is64bit ? AArch64::SDIVXr : AArch64::SDIVWr;
3235 DivOpc = is64bit ? AArch64::UDIVXr : AArch64::UDIVWr;
3238 unsigned MSubOpc = is64bit ? AArch64::MSUBXrrr : AArch64::MSUBWrrr;
3239 unsigned Src0Reg = getRegForValue(I->getOperand(0));
3242 bool Src0IsKill = hasTrivialKill(I->getOperand(0));
3244 unsigned Src1Reg = getRegForValue(I->getOperand(1));
3247 bool Src1IsKill = hasTrivialKill(I->getOperand(1));
3249 const TargetRegisterClass *RC =
3250 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3251 unsigned QuotReg = FastEmitInst_rr(DivOpc, RC, Src0Reg, /*IsKill=*/false,
3252 Src1Reg, /*IsKill=*/false);
3253 assert(QuotReg && "Unexpected DIV instruction emission failure.");
3254 // The remainder is computed as numerator - (quotient * denominator) using the
3255 // MSUB instruction.
3256 unsigned ResultReg = FastEmitInst_rrr(MSubOpc, RC, QuotReg, /*IsKill=*/true,
3257 Src1Reg, Src1IsKill, Src0Reg,
3259 UpdateValueMap(I, ResultReg);
3263 bool AArch64FastISel::SelectMul(const Instruction *I) {
3264 EVT SrcEVT = TLI.getValueType(I->getOperand(0)->getType(), true);
3265 if (!SrcEVT.isSimple())
3267 MVT SrcVT = SrcEVT.getSimpleVT();
3269 // Must be simple value type. Don't handle vectors.
3270 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
3274 unsigned Src0Reg = getRegForValue(I->getOperand(0));
3277 bool Src0IsKill = hasTrivialKill(I->getOperand(0));
3279 unsigned Src1Reg = getRegForValue(I->getOperand(1));
3282 bool Src1IsKill = hasTrivialKill(I->getOperand(1));
3284 unsigned ResultReg =
3285 Emit_MUL_rr(SrcVT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill);
3290 UpdateValueMap(I, ResultReg);
3294 bool AArch64FastISel::SelectShift(const Instruction *I) {
3296 if (!isLoadStoreTypeLegal(I->getType(), RetVT))
3299 if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
3300 unsigned ResultReg = 0;
3301 uint64_t ShiftVal = C->getZExtValue();
3303 bool IsZExt = (I->getOpcode() == Instruction::AShr) ? false : true;
3304 const Value *Op0 = I->getOperand(0);
3305 if (const auto *ZExt = dyn_cast<ZExtInst>(Op0)) {
3307 if (isValueAvailable(ZExt) &&
3308 isLoadStoreTypeLegal(ZExt->getSrcTy(), TmpVT)) {
3311 Op0 = ZExt->getOperand(0);
3313 } else if (const auto *SExt = dyn_cast<SExtInst>(Op0)) {
3315 if (isValueAvailable(SExt) &&
3316 isLoadStoreTypeLegal(SExt->getSrcTy(), TmpVT)) {
3319 Op0 = SExt->getOperand(0);
3323 unsigned Op0Reg = getRegForValue(Op0);
3326 bool Op0IsKill = hasTrivialKill(Op0);
3328 switch (I->getOpcode()) {
3329 default: llvm_unreachable("Unexpected instruction.");
3330 case Instruction::Shl:
3331 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
3333 case Instruction::AShr:
3334 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
3336 case Instruction::LShr:
3337 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
3343 UpdateValueMap(I, ResultReg);
3347 unsigned Op0Reg = getRegForValue(I->getOperand(0));
3350 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
3352 unsigned Op1Reg = getRegForValue(I->getOperand(1));
3355 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
3357 unsigned ResultReg = 0;
3358 switch (I->getOpcode()) {
3359 default: llvm_unreachable("Unexpected instruction.");
3360 case Instruction::Shl:
3361 ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
3363 case Instruction::AShr:
3364 ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
3366 case Instruction::LShr:
3367 ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
3374 UpdateValueMap(I, ResultReg);
3378 bool AArch64FastISel::SelectBitCast(const Instruction *I) {
3381 if (!isTypeLegal(I->getOperand(0)->getType(), SrcVT))
3383 if (!isTypeLegal(I->getType(), RetVT))
3387 if (RetVT == MVT::f32 && SrcVT == MVT::i32)
3388 Opc = AArch64::FMOVWSr;
3389 else if (RetVT == MVT::f64 && SrcVT == MVT::i64)
3390 Opc = AArch64::FMOVXDr;
3391 else if (RetVT == MVT::i32 && SrcVT == MVT::f32)
3392 Opc = AArch64::FMOVSWr;
3393 else if (RetVT == MVT::i64 && SrcVT == MVT::f64)
3394 Opc = AArch64::FMOVDXr;
3398 const TargetRegisterClass *RC = nullptr;
3399 switch (RetVT.SimpleTy) {
3400 default: llvm_unreachable("Unexpected value type.");
3401 case MVT::i32: RC = &AArch64::GPR32RegClass; break;
3402 case MVT::i64: RC = &AArch64::GPR64RegClass; break;
3403 case MVT::f32: RC = &AArch64::FPR32RegClass; break;
3404 case MVT::f64: RC = &AArch64::FPR64RegClass; break;
3406 unsigned Op0Reg = getRegForValue(I->getOperand(0));
3409 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
3410 unsigned ResultReg = FastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill);
3415 UpdateValueMap(I, ResultReg);
3419 bool AArch64FastISel::TargetSelectInstruction(const Instruction *I) {
3420 switch (I->getOpcode()) {
3423 case Instruction::Load:
3424 return SelectLoad(I);
3425 case Instruction::Store:
3426 return SelectStore(I);
3427 case Instruction::Br:
3428 return SelectBranch(I);
3429 case Instruction::IndirectBr:
3430 return SelectIndirectBr(I);
3431 case Instruction::FCmp:
3432 case Instruction::ICmp:
3433 return SelectCmp(I);
3434 case Instruction::Select:
3435 return SelectSelect(I);
3436 case Instruction::FPExt:
3437 return SelectFPExt(I);
3438 case Instruction::FPTrunc:
3439 return SelectFPTrunc(I);
3440 case Instruction::FPToSI:
3441 return SelectFPToInt(I, /*Signed=*/true);
3442 case Instruction::FPToUI:
3443 return SelectFPToInt(I, /*Signed=*/false);
3444 case Instruction::SIToFP:
3445 return SelectIntToFP(I, /*Signed=*/true);
3446 case Instruction::UIToFP:
3447 return SelectIntToFP(I, /*Signed=*/false);
3448 case Instruction::SRem:
3449 return SelectRem(I, ISD::SREM);
3450 case Instruction::URem:
3451 return SelectRem(I, ISD::UREM);
3452 case Instruction::Ret:
3453 return SelectRet(I);
3454 case Instruction::Trunc:
3455 return SelectTrunc(I);
3456 case Instruction::ZExt:
3457 case Instruction::SExt:
3458 return SelectIntExt(I);
3460 // FIXME: All of these should really be handled by the target-independent
3461 // selector -> improve FastISel tblgen.
3462 case Instruction::Mul:
3463 return SelectMul(I);
3464 case Instruction::Shl: // fall-through
3465 case Instruction::LShr: // fall-through
3466 case Instruction::AShr:
3467 return SelectShift(I);
3468 case Instruction::BitCast:
3469 return SelectBitCast(I);
3472 // Silence warnings.
3473 (void)&CC_AArch64_DarwinPCS_VarArg;
3477 llvm::FastISel *AArch64::createFastISel(FunctionLoweringInfo &funcInfo,
3478 const TargetLibraryInfo *libInfo) {
3479 return new AArch64FastISel(funcInfo, libInfo);