1 //===-- AArch6464FastISel.cpp - AArch64 FastISel implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the AArch64-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // AArch64GenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "AArch64CallingConvention.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64TargetMachine.h"
20 #include "MCTargetDesc/AArch64AddressingModes.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/FunctionLoweringInfo.h"
25 #include "llvm/CodeGen/MachineConstantPool.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/IR/CallingConv.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/GetElementPtrTypeIterator.h"
34 #include "llvm/IR/GlobalAlias.h"
35 #include "llvm/IR/GlobalVariable.h"
36 #include "llvm/IR/Instructions.h"
37 #include "llvm/IR/IntrinsicInst.h"
38 #include "llvm/IR/Operator.h"
39 #include "llvm/MC/MCSymbol.h"
40 #include "llvm/Support/CommandLine.h"
45 class AArch64FastISel final : public FastISel {
55 AArch64_AM::ShiftExtendType ExtType;
63 const GlobalValue *GV;
66 Address() : Kind(RegBase), ExtType(AArch64_AM::InvalidShiftExtend),
67 OffsetReg(0), Shift(0), Offset(0), GV(nullptr) { Base.Reg = 0; }
68 void setKind(BaseKind K) { Kind = K; }
69 BaseKind getKind() const { return Kind; }
70 void setExtendType(AArch64_AM::ShiftExtendType E) { ExtType = E; }
71 AArch64_AM::ShiftExtendType getExtendType() const { return ExtType; }
72 bool isRegBase() const { return Kind == RegBase; }
73 bool isFIBase() const { return Kind == FrameIndexBase; }
74 void setReg(unsigned Reg) {
75 assert(isRegBase() && "Invalid base register access!");
78 unsigned getReg() const {
79 assert(isRegBase() && "Invalid base register access!");
82 void setOffsetReg(unsigned Reg) {
85 unsigned getOffsetReg() const {
88 void setFI(unsigned FI) {
89 assert(isFIBase() && "Invalid base frame index access!");
92 unsigned getFI() const {
93 assert(isFIBase() && "Invalid base frame index access!");
96 void setOffset(int64_t O) { Offset = O; }
97 int64_t getOffset() { return Offset; }
98 void setShift(unsigned S) { Shift = S; }
99 unsigned getShift() { return Shift; }
101 void setGlobalValue(const GlobalValue *G) { GV = G; }
102 const GlobalValue *getGlobalValue() { return GV; }
105 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
106 /// make the right decision when generating code for different targets.
107 const AArch64Subtarget *Subtarget;
108 LLVMContext *Context;
110 bool fastLowerArguments() override;
111 bool fastLowerCall(CallLoweringInfo &CLI) override;
112 bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
115 // Selection routines.
116 bool selectAddSub(const Instruction *I);
117 bool selectLogicalOp(const Instruction *I);
118 bool selectLoad(const Instruction *I);
119 bool selectStore(const Instruction *I);
120 bool selectBranch(const Instruction *I);
121 bool selectIndirectBr(const Instruction *I);
122 bool selectCmp(const Instruction *I);
123 bool selectSelect(const Instruction *I);
124 bool selectFPExt(const Instruction *I);
125 bool selectFPTrunc(const Instruction *I);
126 bool selectFPToInt(const Instruction *I, bool Signed);
127 bool selectIntToFP(const Instruction *I, bool Signed);
128 bool selectRem(const Instruction *I, unsigned ISDOpcode);
129 bool selectRet(const Instruction *I);
130 bool selectTrunc(const Instruction *I);
131 bool selectIntExt(const Instruction *I);
132 bool selectMul(const Instruction *I);
133 bool selectShift(const Instruction *I);
134 bool selectBitCast(const Instruction *I);
135 bool selectFRem(const Instruction *I);
136 bool selectSDiv(const Instruction *I);
137 bool selectGetElementPtr(const Instruction *I);
139 // Utility helper routines.
140 bool isTypeLegal(Type *Ty, MVT &VT);
141 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
142 bool isValueAvailable(const Value *V) const;
143 bool computeAddress(const Value *Obj, Address &Addr, Type *Ty = nullptr);
144 bool computeCallAddress(const Value *V, Address &Addr);
145 bool simplifyAddress(Address &Addr, MVT VT);
146 void addLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
147 unsigned Flags, unsigned ScaleFactor,
148 MachineMemOperand *MMO);
149 bool isMemCpySmall(uint64_t Len, unsigned Alignment);
150 bool tryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
152 bool foldXALUIntrinsic(AArch64CC::CondCode &CC, const Instruction *I,
154 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
155 bool optimizeSelect(const SelectInst *SI);
156 std::pair<unsigned, bool> getRegForGEPIndex(const Value *Idx);
158 // Emit helper routines.
159 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
160 const Value *RHS, bool SetFlags = false,
161 bool WantResult = true, bool IsZExt = false);
162 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
163 bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
164 bool SetFlags = false, bool WantResult = true);
165 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
166 bool LHSIsKill, uint64_t Imm, bool SetFlags = false,
167 bool WantResult = true);
168 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
169 bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
170 AArch64_AM::ShiftExtendType ShiftType,
171 uint64_t ShiftImm, bool SetFlags = false,
172 bool WantResult = true);
173 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
174 bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
175 AArch64_AM::ShiftExtendType ExtType,
176 uint64_t ShiftImm, bool SetFlags = false,
177 bool WantResult = true);
180 bool emitCompareAndBranch(const BranchInst *BI);
181 bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
182 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
183 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
184 bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
185 unsigned emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,
186 MachineMemOperand *MMO = nullptr);
187 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
188 MachineMemOperand *MMO = nullptr);
189 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
190 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
191 unsigned emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
192 bool SetFlags = false, bool WantResult = true,
193 bool IsZExt = false);
194 unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm);
195 unsigned emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
196 bool SetFlags = false, bool WantResult = true,
197 bool IsZExt = false);
198 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
199 unsigned RHSReg, bool RHSIsKill, bool WantResult = true);
200 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
201 unsigned RHSReg, bool RHSIsKill,
202 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
203 bool WantResult = true);
204 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
206 unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
207 bool LHSIsKill, uint64_t Imm);
208 unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
209 bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
211 unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
212 unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
213 unsigned Op1, bool Op1IsKill);
214 unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
215 unsigned Op1, bool Op1IsKill);
216 unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
217 unsigned Op1, bool Op1IsKill);
218 unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
219 unsigned Op1Reg, bool Op1IsKill);
220 unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
221 uint64_t Imm, bool IsZExt = true);
222 unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
223 unsigned Op1Reg, bool Op1IsKill);
224 unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
225 uint64_t Imm, bool IsZExt = true);
226 unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
227 unsigned Op1Reg, bool Op1IsKill);
228 unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
229 uint64_t Imm, bool IsZExt = false);
231 unsigned materializeInt(const ConstantInt *CI, MVT VT);
232 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
233 unsigned materializeGV(const GlobalValue *GV);
235 // Call handling routines.
237 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
238 bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
240 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
243 // Backend specific FastISel code.
244 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
245 unsigned fastMaterializeConstant(const Constant *C) override;
246 unsigned fastMaterializeFloatZero(const ConstantFP* CF) override;
248 explicit AArch64FastISel(FunctionLoweringInfo &FuncInfo,
249 const TargetLibraryInfo *LibInfo)
250 : FastISel(FuncInfo, LibInfo, /*SkipTargetIndependentISel=*/true) {
252 &static_cast<const AArch64Subtarget &>(FuncInfo.MF->getSubtarget());
253 Context = &FuncInfo.Fn->getContext();
256 bool fastSelectInstruction(const Instruction *I) override;
258 #include "AArch64GenFastISel.inc"
261 } // end anonymous namespace
263 #include "AArch64GenCallingConv.inc"
265 /// \brief Check if the sign-/zero-extend will be a noop.
266 static bool isIntExtFree(const Instruction *I) {
267 assert((isa<ZExtInst>(I) || isa<SExtInst>(I)) &&
268 "Unexpected integer extend instruction.");
269 assert(!I->getType()->isVectorTy() && I->getType()->isIntegerTy() &&
270 "Unexpected value type.");
271 bool IsZExt = isa<ZExtInst>(I);
273 if (const auto *LI = dyn_cast<LoadInst>(I->getOperand(0)))
277 if (const auto *Arg = dyn_cast<Argument>(I->getOperand(0)))
278 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr()))
284 /// \brief Determine the implicit scale factor that is applied by a memory
285 /// operation for a given value type.
286 static unsigned getImplicitScaleFactor(MVT VT) {
287 switch (VT.SimpleTy) {
290 case MVT::i1: // fall-through
295 case MVT::i32: // fall-through
298 case MVT::i64: // fall-through
304 CCAssignFn *AArch64FastISel::CCAssignFnForCall(CallingConv::ID CC) const {
305 if (CC == CallingConv::WebKit_JS)
306 return CC_AArch64_WebKit_JS;
307 if (CC == CallingConv::GHC)
308 return CC_AArch64_GHC;
309 return Subtarget->isTargetDarwin() ? CC_AArch64_DarwinPCS : CC_AArch64_AAPCS;
312 unsigned AArch64FastISel::fastMaterializeAlloca(const AllocaInst *AI) {
313 assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i64 &&
314 "Alloca should always return a pointer.");
316 // Don't handle dynamic allocas.
317 if (!FuncInfo.StaticAllocaMap.count(AI))
320 DenseMap<const AllocaInst *, int>::iterator SI =
321 FuncInfo.StaticAllocaMap.find(AI);
323 if (SI != FuncInfo.StaticAllocaMap.end()) {
324 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
325 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
327 .addFrameIndex(SI->second)
336 unsigned AArch64FastISel::materializeInt(const ConstantInt *CI, MVT VT) {
341 return fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
343 // Create a copy from the zero register to materialize a "0" value.
344 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass
345 : &AArch64::GPR32RegClass;
346 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
347 unsigned ResultReg = createResultReg(RC);
348 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
349 ResultReg).addReg(ZeroReg, getKillRegState(true));
353 unsigned AArch64FastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
354 // Positive zero (+0.0) has to be materialized with a fmov from the zero
355 // register, because the immediate version of fmov cannot encode zero.
356 if (CFP->isNullValue())
357 return fastMaterializeFloatZero(CFP);
359 if (VT != MVT::f32 && VT != MVT::f64)
362 const APFloat Val = CFP->getValueAPF();
363 bool Is64Bit = (VT == MVT::f64);
364 // This checks to see if we can use FMOV instructions to materialize
365 // a constant, otherwise we have to materialize via the constant pool.
366 if (TLI.isFPImmLegal(Val, VT)) {
368 Is64Bit ? AArch64_AM::getFP64Imm(Val) : AArch64_AM::getFP32Imm(Val);
369 assert((Imm != -1) && "Cannot encode floating-point constant.");
370 unsigned Opc = Is64Bit ? AArch64::FMOVDi : AArch64::FMOVSi;
371 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm);
374 // For the MachO large code model materialize the FP constant in code.
375 if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) {
376 unsigned Opc1 = Is64Bit ? AArch64::MOVi64imm : AArch64::MOVi32imm;
377 const TargetRegisterClass *RC = Is64Bit ?
378 &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
380 unsigned TmpReg = createResultReg(RC);
381 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc1), TmpReg)
382 .addImm(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
384 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
385 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
386 TII.get(TargetOpcode::COPY), ResultReg)
387 .addReg(TmpReg, getKillRegState(true));
392 // Materialize via constant pool. MachineConstantPool wants an explicit
394 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
396 Align = DL.getTypeAllocSize(CFP->getType());
398 unsigned CPI = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
399 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
400 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
401 ADRPReg).addConstantPoolIndex(CPI, 0, AArch64II::MO_PAGE);
403 unsigned Opc = Is64Bit ? AArch64::LDRDui : AArch64::LDRSui;
404 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
405 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
407 .addConstantPoolIndex(CPI, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
411 unsigned AArch64FastISel::materializeGV(const GlobalValue *GV) {
412 // We can't handle thread-local variables quickly yet.
413 if (GV->isThreadLocal())
416 // MachO still uses GOT for large code-model accesses, but ELF requires
417 // movz/movk sequences, which FastISel doesn't handle yet.
418 if (TM.getCodeModel() != CodeModel::Small && !Subtarget->isTargetMachO())
421 unsigned char OpFlags = Subtarget->ClassifyGlobalReference(GV, TM);
423 EVT DestEVT = TLI.getValueType(DL, GV->getType(), true);
424 if (!DestEVT.isSimple())
427 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
430 if (OpFlags & AArch64II::MO_GOT) {
432 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
434 .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGE);
436 ResultReg = createResultReg(&AArch64::GPR64RegClass);
437 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::LDRXui),
440 .addGlobalAddress(GV, 0, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF |
442 } else if (OpFlags & AArch64II::MO_CONSTPOOL) {
443 // We can't handle addresses loaded from a constant pool quickly yet.
447 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
449 .addGlobalAddress(GV, 0, AArch64II::MO_PAGE);
451 ResultReg = createResultReg(&AArch64::GPR64spRegClass);
452 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
455 .addGlobalAddress(GV, 0, AArch64II::MO_PAGEOFF | AArch64II::MO_NC)
461 unsigned AArch64FastISel::fastMaterializeConstant(const Constant *C) {
462 EVT CEVT = TLI.getValueType(DL, C->getType(), true);
464 // Only handle simple types.
465 if (!CEVT.isSimple())
467 MVT VT = CEVT.getSimpleVT();
469 if (const auto *CI = dyn_cast<ConstantInt>(C))
470 return materializeInt(CI, VT);
471 else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
472 return materializeFP(CFP, VT);
473 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
474 return materializeGV(GV);
479 unsigned AArch64FastISel::fastMaterializeFloatZero(const ConstantFP* CFP) {
480 assert(CFP->isNullValue() &&
481 "Floating-point constant is not a positive zero.");
483 if (!isTypeLegal(CFP->getType(), VT))
486 if (VT != MVT::f32 && VT != MVT::f64)
489 bool Is64Bit = (VT == MVT::f64);
490 unsigned ZReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
491 unsigned Opc = Is64Bit ? AArch64::FMOVXDr : AArch64::FMOVWSr;
492 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true);
495 /// \brief Check if the multiply is by a power-of-2 constant.
496 static bool isMulPowOf2(const Value *I) {
497 if (const auto *MI = dyn_cast<MulOperator>(I)) {
498 if (const auto *C = dyn_cast<ConstantInt>(MI->getOperand(0)))
499 if (C->getValue().isPowerOf2())
501 if (const auto *C = dyn_cast<ConstantInt>(MI->getOperand(1)))
502 if (C->getValue().isPowerOf2())
508 // Computes the address to get to an object.
509 bool AArch64FastISel::computeAddress(const Value *Obj, Address &Addr, Type *Ty)
511 const User *U = nullptr;
512 unsigned Opcode = Instruction::UserOp1;
513 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
514 // Don't walk into other basic blocks unless the object is an alloca from
515 // another block, otherwise it may not have a virtual register assigned.
516 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
517 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
518 Opcode = I->getOpcode();
521 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
522 Opcode = C->getOpcode();
526 if (auto *Ty = dyn_cast<PointerType>(Obj->getType()))
527 if (Ty->getAddressSpace() > 255)
528 // Fast instruction selection doesn't support the special
535 case Instruction::BitCast: {
536 // Look through bitcasts.
537 return computeAddress(U->getOperand(0), Addr, Ty);
539 case Instruction::IntToPtr: {
540 // Look past no-op inttoptrs.
541 if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
542 TLI.getPointerTy(DL))
543 return computeAddress(U->getOperand(0), Addr, Ty);
546 case Instruction::PtrToInt: {
547 // Look past no-op ptrtoints.
548 if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
549 return computeAddress(U->getOperand(0), Addr, Ty);
552 case Instruction::GetElementPtr: {
553 Address SavedAddr = Addr;
554 uint64_t TmpOffset = Addr.getOffset();
556 // Iterate through the GEP folding the constants into offsets where
558 gep_type_iterator GTI = gep_type_begin(U);
559 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
561 const Value *Op = *i;
562 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
563 const StructLayout *SL = DL.getStructLayout(STy);
564 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
565 TmpOffset += SL->getElementOffset(Idx);
567 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
569 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
570 // Constant-offset addressing.
571 TmpOffset += CI->getSExtValue() * S;
574 if (canFoldAddIntoGEP(U, Op)) {
575 // A compatible add with a constant operand. Fold the constant.
577 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
578 TmpOffset += CI->getSExtValue() * S;
579 // Iterate on the other operand.
580 Op = cast<AddOperator>(Op)->getOperand(0);
584 goto unsupported_gep;
589 // Try to grab the base operand now.
590 Addr.setOffset(TmpOffset);
591 if (computeAddress(U->getOperand(0), Addr, Ty))
594 // We failed, restore everything and try the other options.
600 case Instruction::Alloca: {
601 const AllocaInst *AI = cast<AllocaInst>(Obj);
602 DenseMap<const AllocaInst *, int>::iterator SI =
603 FuncInfo.StaticAllocaMap.find(AI);
604 if (SI != FuncInfo.StaticAllocaMap.end()) {
605 Addr.setKind(Address::FrameIndexBase);
606 Addr.setFI(SI->second);
611 case Instruction::Add: {
612 // Adds of constants are common and easy enough.
613 const Value *LHS = U->getOperand(0);
614 const Value *RHS = U->getOperand(1);
616 if (isa<ConstantInt>(LHS))
619 if (const ConstantInt *CI = dyn_cast<ConstantInt>(RHS)) {
620 Addr.setOffset(Addr.getOffset() + CI->getSExtValue());
621 return computeAddress(LHS, Addr, Ty);
624 Address Backup = Addr;
625 if (computeAddress(LHS, Addr, Ty) && computeAddress(RHS, Addr, Ty))
631 case Instruction::Sub: {
632 // Subs of constants are common and easy enough.
633 const Value *LHS = U->getOperand(0);
634 const Value *RHS = U->getOperand(1);
636 if (const ConstantInt *CI = dyn_cast<ConstantInt>(RHS)) {
637 Addr.setOffset(Addr.getOffset() - CI->getSExtValue());
638 return computeAddress(LHS, Addr, Ty);
642 case Instruction::Shl: {
643 if (Addr.getOffsetReg())
646 const auto *CI = dyn_cast<ConstantInt>(U->getOperand(1));
650 unsigned Val = CI->getZExtValue();
651 if (Val < 1 || Val > 3)
654 uint64_t NumBytes = 0;
655 if (Ty && Ty->isSized()) {
656 uint64_t NumBits = DL.getTypeSizeInBits(Ty);
657 NumBytes = NumBits / 8;
658 if (!isPowerOf2_64(NumBits))
662 if (NumBytes != (1ULL << Val))
666 Addr.setExtendType(AArch64_AM::LSL);
668 const Value *Src = U->getOperand(0);
669 if (const auto *I = dyn_cast<Instruction>(Src)) {
670 if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
671 // Fold the zext or sext when it won't become a noop.
672 if (const auto *ZE = dyn_cast<ZExtInst>(I)) {
673 if (!isIntExtFree(ZE) &&
674 ZE->getOperand(0)->getType()->isIntegerTy(32)) {
675 Addr.setExtendType(AArch64_AM::UXTW);
676 Src = ZE->getOperand(0);
678 } else if (const auto *SE = dyn_cast<SExtInst>(I)) {
679 if (!isIntExtFree(SE) &&
680 SE->getOperand(0)->getType()->isIntegerTy(32)) {
681 Addr.setExtendType(AArch64_AM::SXTW);
682 Src = SE->getOperand(0);
688 if (const auto *AI = dyn_cast<BinaryOperator>(Src))
689 if (AI->getOpcode() == Instruction::And) {
690 const Value *LHS = AI->getOperand(0);
691 const Value *RHS = AI->getOperand(1);
693 if (const auto *C = dyn_cast<ConstantInt>(LHS))
694 if (C->getValue() == 0xffffffff)
697 if (const auto *C = dyn_cast<ConstantInt>(RHS))
698 if (C->getValue() == 0xffffffff) {
699 Addr.setExtendType(AArch64_AM::UXTW);
700 unsigned Reg = getRegForValue(LHS);
703 bool RegIsKill = hasTrivialKill(LHS);
704 Reg = fastEmitInst_extractsubreg(MVT::i32, Reg, RegIsKill,
706 Addr.setOffsetReg(Reg);
711 unsigned Reg = getRegForValue(Src);
714 Addr.setOffsetReg(Reg);
717 case Instruction::Mul: {
718 if (Addr.getOffsetReg())
724 const Value *LHS = U->getOperand(0);
725 const Value *RHS = U->getOperand(1);
727 // Canonicalize power-of-2 value to the RHS.
728 if (const auto *C = dyn_cast<ConstantInt>(LHS))
729 if (C->getValue().isPowerOf2())
732 assert(isa<ConstantInt>(RHS) && "Expected an ConstantInt.");
733 const auto *C = cast<ConstantInt>(RHS);
734 unsigned Val = C->getValue().logBase2();
735 if (Val < 1 || Val > 3)
738 uint64_t NumBytes = 0;
739 if (Ty && Ty->isSized()) {
740 uint64_t NumBits = DL.getTypeSizeInBits(Ty);
741 NumBytes = NumBits / 8;
742 if (!isPowerOf2_64(NumBits))
746 if (NumBytes != (1ULL << Val))
750 Addr.setExtendType(AArch64_AM::LSL);
752 const Value *Src = LHS;
753 if (const auto *I = dyn_cast<Instruction>(Src)) {
754 if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
755 // Fold the zext or sext when it won't become a noop.
756 if (const auto *ZE = dyn_cast<ZExtInst>(I)) {
757 if (!isIntExtFree(ZE) &&
758 ZE->getOperand(0)->getType()->isIntegerTy(32)) {
759 Addr.setExtendType(AArch64_AM::UXTW);
760 Src = ZE->getOperand(0);
762 } else if (const auto *SE = dyn_cast<SExtInst>(I)) {
763 if (!isIntExtFree(SE) &&
764 SE->getOperand(0)->getType()->isIntegerTy(32)) {
765 Addr.setExtendType(AArch64_AM::SXTW);
766 Src = SE->getOperand(0);
772 unsigned Reg = getRegForValue(Src);
775 Addr.setOffsetReg(Reg);
778 case Instruction::And: {
779 if (Addr.getOffsetReg())
782 if (!Ty || DL.getTypeSizeInBits(Ty) != 8)
785 const Value *LHS = U->getOperand(0);
786 const Value *RHS = U->getOperand(1);
788 if (const auto *C = dyn_cast<ConstantInt>(LHS))
789 if (C->getValue() == 0xffffffff)
792 if (const auto *C = dyn_cast<ConstantInt>(RHS))
793 if (C->getValue() == 0xffffffff) {
795 Addr.setExtendType(AArch64_AM::LSL);
796 Addr.setExtendType(AArch64_AM::UXTW);
798 unsigned Reg = getRegForValue(LHS);
801 bool RegIsKill = hasTrivialKill(LHS);
802 Reg = fastEmitInst_extractsubreg(MVT::i32, Reg, RegIsKill,
804 Addr.setOffsetReg(Reg);
809 case Instruction::SExt:
810 case Instruction::ZExt: {
811 if (!Addr.getReg() || Addr.getOffsetReg())
814 const Value *Src = nullptr;
815 // Fold the zext or sext when it won't become a noop.
816 if (const auto *ZE = dyn_cast<ZExtInst>(U)) {
817 if (!isIntExtFree(ZE) && ZE->getOperand(0)->getType()->isIntegerTy(32)) {
818 Addr.setExtendType(AArch64_AM::UXTW);
819 Src = ZE->getOperand(0);
821 } else if (const auto *SE = dyn_cast<SExtInst>(U)) {
822 if (!isIntExtFree(SE) && SE->getOperand(0)->getType()->isIntegerTy(32)) {
823 Addr.setExtendType(AArch64_AM::SXTW);
824 Src = SE->getOperand(0);
832 unsigned Reg = getRegForValue(Src);
835 Addr.setOffsetReg(Reg);
840 if (Addr.isRegBase() && !Addr.getReg()) {
841 unsigned Reg = getRegForValue(Obj);
848 if (!Addr.getOffsetReg()) {
849 unsigned Reg = getRegForValue(Obj);
852 Addr.setOffsetReg(Reg);
859 bool AArch64FastISel::computeCallAddress(const Value *V, Address &Addr) {
860 const User *U = nullptr;
861 unsigned Opcode = Instruction::UserOp1;
864 if (const auto *I = dyn_cast<Instruction>(V)) {
865 Opcode = I->getOpcode();
867 InMBB = I->getParent() == FuncInfo.MBB->getBasicBlock();
868 } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
869 Opcode = C->getOpcode();
875 case Instruction::BitCast:
876 // Look past bitcasts if its operand is in the same BB.
878 return computeCallAddress(U->getOperand(0), Addr);
880 case Instruction::IntToPtr:
881 // Look past no-op inttoptrs if its operand is in the same BB.
883 TLI.getValueType(DL, U->getOperand(0)->getType()) ==
884 TLI.getPointerTy(DL))
885 return computeCallAddress(U->getOperand(0), Addr);
887 case Instruction::PtrToInt:
888 // Look past no-op ptrtoints if its operand is in the same BB.
889 if (InMBB && TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
890 return computeCallAddress(U->getOperand(0), Addr);
894 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
895 Addr.setGlobalValue(GV);
899 // If all else fails, try to materialize the value in a register.
900 if (!Addr.getGlobalValue()) {
901 Addr.setReg(getRegForValue(V));
902 return Addr.getReg() != 0;
909 bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) {
910 EVT evt = TLI.getValueType(DL, Ty, true);
912 // Only handle simple types.
913 if (evt == MVT::Other || !evt.isSimple())
915 VT = evt.getSimpleVT();
917 // This is a legal type, but it's not something we handle in fast-isel.
921 // Handle all other legal types, i.e. a register that will directly hold this
923 return TLI.isTypeLegal(VT);
926 /// \brief Determine if the value type is supported by FastISel.
928 /// FastISel for AArch64 can handle more value types than are legal. This adds
929 /// simple value type such as i1, i8, and i16.
930 bool AArch64FastISel::isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed) {
931 if (Ty->isVectorTy() && !IsVectorAllowed)
934 if (isTypeLegal(Ty, VT))
937 // If this is a type than can be sign or zero-extended to a basic operation
938 // go ahead and accept it now.
939 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
945 bool AArch64FastISel::isValueAvailable(const Value *V) const {
946 if (!isa<Instruction>(V))
949 const auto *I = cast<Instruction>(V);
950 if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
956 bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) {
957 unsigned ScaleFactor = getImplicitScaleFactor(VT);
961 bool ImmediateOffsetNeedsLowering = false;
962 bool RegisterOffsetNeedsLowering = false;
963 int64_t Offset = Addr.getOffset();
964 if (((Offset < 0) || (Offset & (ScaleFactor - 1))) && !isInt<9>(Offset))
965 ImmediateOffsetNeedsLowering = true;
966 else if (Offset > 0 && !(Offset & (ScaleFactor - 1)) &&
967 !isUInt<12>(Offset / ScaleFactor))
968 ImmediateOffsetNeedsLowering = true;
970 // Cannot encode an offset register and an immediate offset in the same
971 // instruction. Fold the immediate offset into the load/store instruction and
972 // emit an additional add to take care of the offset register.
973 if (!ImmediateOffsetNeedsLowering && Addr.getOffset() && Addr.getOffsetReg())
974 RegisterOffsetNeedsLowering = true;
976 // Cannot encode zero register as base.
977 if (Addr.isRegBase() && Addr.getOffsetReg() && !Addr.getReg())
978 RegisterOffsetNeedsLowering = true;
980 // If this is a stack pointer and the offset needs to be simplified then put
981 // the alloca address into a register, set the base type back to register and
982 // continue. This should almost never happen.
983 if ((ImmediateOffsetNeedsLowering || Addr.getOffsetReg()) && Addr.isFIBase())
985 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
986 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
988 .addFrameIndex(Addr.getFI())
991 Addr.setKind(Address::RegBase);
992 Addr.setReg(ResultReg);
995 if (RegisterOffsetNeedsLowering) {
996 unsigned ResultReg = 0;
998 if (Addr.getExtendType() == AArch64_AM::SXTW ||
999 Addr.getExtendType() == AArch64_AM::UXTW )
1000 ResultReg = emitAddSub_rx(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
1001 /*TODO:IsKill=*/false, Addr.getOffsetReg(),
1002 /*TODO:IsKill=*/false, Addr.getExtendType(),
1005 ResultReg = emitAddSub_rs(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
1006 /*TODO:IsKill=*/false, Addr.getOffsetReg(),
1007 /*TODO:IsKill=*/false, AArch64_AM::LSL,
1010 if (Addr.getExtendType() == AArch64_AM::UXTW)
1011 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
1012 /*Op0IsKill=*/false, Addr.getShift(),
1014 else if (Addr.getExtendType() == AArch64_AM::SXTW)
1015 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
1016 /*Op0IsKill=*/false, Addr.getShift(),
1019 ResultReg = emitLSL_ri(MVT::i64, MVT::i64, Addr.getOffsetReg(),
1020 /*Op0IsKill=*/false, Addr.getShift());
1025 Addr.setReg(ResultReg);
1026 Addr.setOffsetReg(0);
1028 Addr.setExtendType(AArch64_AM::InvalidShiftExtend);
1031 // Since the offset is too large for the load/store instruction get the
1032 // reg+offset into a register.
1033 if (ImmediateOffsetNeedsLowering) {
1036 // Try to fold the immediate into the add instruction.
1037 ResultReg = emitAdd_ri_(MVT::i64, Addr.getReg(), /*IsKill=*/false, Offset);
1039 ResultReg = fastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset);
1043 Addr.setReg(ResultReg);
1049 void AArch64FastISel::addLoadStoreOperands(Address &Addr,
1050 const MachineInstrBuilder &MIB,
1052 unsigned ScaleFactor,
1053 MachineMemOperand *MMO) {
1054 int64_t Offset = Addr.getOffset() / ScaleFactor;
1055 // Frame base works a bit differently. Handle it separately.
1056 if (Addr.isFIBase()) {
1057 int FI = Addr.getFI();
1058 // FIXME: We shouldn't be using getObjectSize/getObjectAlignment. The size
1059 // and alignment should be based on the VT.
1060 MMO = FuncInfo.MF->getMachineMemOperand(
1061 MachinePointerInfo::getFixedStack(*FuncInfo.MF, FI, Offset), Flags,
1062 MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
1063 // Now add the rest of the operands.
1064 MIB.addFrameIndex(FI).addImm(Offset);
1066 assert(Addr.isRegBase() && "Unexpected address kind.");
1067 const MCInstrDesc &II = MIB->getDesc();
1068 unsigned Idx = (Flags & MachineMemOperand::MOStore) ? 1 : 0;
1070 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx));
1072 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1));
1073 if (Addr.getOffsetReg()) {
1074 assert(Addr.getOffset() == 0 && "Unexpected offset");
1075 bool IsSigned = Addr.getExtendType() == AArch64_AM::SXTW ||
1076 Addr.getExtendType() == AArch64_AM::SXTX;
1077 MIB.addReg(Addr.getReg());
1078 MIB.addReg(Addr.getOffsetReg());
1079 MIB.addImm(IsSigned);
1080 MIB.addImm(Addr.getShift() != 0);
1082 MIB.addReg(Addr.getReg()).addImm(Offset);
1086 MIB.addMemOperand(MMO);
1089 unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
1090 const Value *RHS, bool SetFlags,
1091 bool WantResult, bool IsZExt) {
1092 AArch64_AM::ShiftExtendType ExtendType = AArch64_AM::InvalidShiftExtend;
1093 bool NeedExtend = false;
1094 switch (RetVT.SimpleTy) {
1102 ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB;
1106 ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH;
1108 case MVT::i32: // fall-through
1113 RetVT.SimpleTy = std::max(RetVT.SimpleTy, MVT::i32);
1115 // Canonicalize immediates to the RHS first.
1116 if (UseAdd && isa<Constant>(LHS) && !isa<Constant>(RHS))
1117 std::swap(LHS, RHS);
1119 // Canonicalize mul by power of 2 to the RHS.
1120 if (UseAdd && LHS->hasOneUse() && isValueAvailable(LHS))
1121 if (isMulPowOf2(LHS))
1122 std::swap(LHS, RHS);
1124 // Canonicalize shift immediate to the RHS.
1125 if (UseAdd && LHS->hasOneUse() && isValueAvailable(LHS))
1126 if (const auto *SI = dyn_cast<BinaryOperator>(LHS))
1127 if (isa<ConstantInt>(SI->getOperand(1)))
1128 if (SI->getOpcode() == Instruction::Shl ||
1129 SI->getOpcode() == Instruction::LShr ||
1130 SI->getOpcode() == Instruction::AShr )
1131 std::swap(LHS, RHS);
1133 unsigned LHSReg = getRegForValue(LHS);
1136 bool LHSIsKill = hasTrivialKill(LHS);
1139 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
1141 unsigned ResultReg = 0;
1142 if (const auto *C = dyn_cast<ConstantInt>(RHS)) {
1143 uint64_t Imm = IsZExt ? C->getZExtValue() : C->getSExtValue();
1144 if (C->isNegative())
1145 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, LHSIsKill, -Imm,
1146 SetFlags, WantResult);
1148 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, Imm, SetFlags,
1150 } else if (const auto *C = dyn_cast<Constant>(RHS))
1151 if (C->isNullValue())
1152 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, 0, SetFlags,
1158 // Only extend the RHS within the instruction if there is a valid extend type.
1159 if (ExtendType != AArch64_AM::InvalidShiftExtend && RHS->hasOneUse() &&
1160 isValueAvailable(RHS)) {
1161 if (const auto *SI = dyn_cast<BinaryOperator>(RHS))
1162 if (const auto *C = dyn_cast<ConstantInt>(SI->getOperand(1)))
1163 if ((SI->getOpcode() == Instruction::Shl) && (C->getZExtValue() < 4)) {
1164 unsigned RHSReg = getRegForValue(SI->getOperand(0));
1167 bool RHSIsKill = hasTrivialKill(SI->getOperand(0));
1168 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,
1169 RHSIsKill, ExtendType, C->getZExtValue(),
1170 SetFlags, WantResult);
1172 unsigned RHSReg = getRegForValue(RHS);
1175 bool RHSIsKill = hasTrivialKill(RHS);
1176 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
1177 ExtendType, 0, SetFlags, WantResult);
1180 // Check if the mul can be folded into the instruction.
1181 if (RHS->hasOneUse() && isValueAvailable(RHS)) {
1182 if (isMulPowOf2(RHS)) {
1183 const Value *MulLHS = cast<MulOperator>(RHS)->getOperand(0);
1184 const Value *MulRHS = cast<MulOperator>(RHS)->getOperand(1);
1186 if (const auto *C = dyn_cast<ConstantInt>(MulLHS))
1187 if (C->getValue().isPowerOf2())
1188 std::swap(MulLHS, MulRHS);
1190 assert(isa<ConstantInt>(MulRHS) && "Expected a ConstantInt.");
1191 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2();
1192 unsigned RHSReg = getRegForValue(MulLHS);
1195 bool RHSIsKill = hasTrivialKill(MulLHS);
1196 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,
1197 RHSIsKill, AArch64_AM::LSL, ShiftVal, SetFlags,
1204 // Check if the shift can be folded into the instruction.
1205 if (RHS->hasOneUse() && isValueAvailable(RHS)) {
1206 if (const auto *SI = dyn_cast<BinaryOperator>(RHS)) {
1207 if (const auto *C = dyn_cast<ConstantInt>(SI->getOperand(1))) {
1208 AArch64_AM::ShiftExtendType ShiftType = AArch64_AM::InvalidShiftExtend;
1209 switch (SI->getOpcode()) {
1211 case Instruction::Shl: ShiftType = AArch64_AM::LSL; break;
1212 case Instruction::LShr: ShiftType = AArch64_AM::LSR; break;
1213 case Instruction::AShr: ShiftType = AArch64_AM::ASR; break;
1215 uint64_t ShiftVal = C->getZExtValue();
1216 if (ShiftType != AArch64_AM::InvalidShiftExtend) {
1217 unsigned RHSReg = getRegForValue(SI->getOperand(0));
1220 bool RHSIsKill = hasTrivialKill(SI->getOperand(0));
1221 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,
1222 RHSIsKill, ShiftType, ShiftVal, SetFlags,
1231 unsigned RHSReg = getRegForValue(RHS);
1234 bool RHSIsKill = hasTrivialKill(RHS);
1237 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
1239 return emitAddSub_rr(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
1240 SetFlags, WantResult);
1243 unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
1244 bool LHSIsKill, unsigned RHSReg,
1245 bool RHSIsKill, bool SetFlags,
1247 assert(LHSReg && RHSReg && "Invalid register number.");
1249 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1252 static const unsigned OpcTable[2][2][2] = {
1253 { { AArch64::SUBWrr, AArch64::SUBXrr },
1254 { AArch64::ADDWrr, AArch64::ADDXrr } },
1255 { { AArch64::SUBSWrr, AArch64::SUBSXrr },
1256 { AArch64::ADDSWrr, AArch64::ADDSXrr } }
1258 bool Is64Bit = RetVT == MVT::i64;
1259 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1260 const TargetRegisterClass *RC =
1261 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1264 ResultReg = createResultReg(RC);
1266 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1268 const MCInstrDesc &II = TII.get(Opc);
1269 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1270 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
1271 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1272 .addReg(LHSReg, getKillRegState(LHSIsKill))
1273 .addReg(RHSReg, getKillRegState(RHSIsKill));
1277 unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
1278 bool LHSIsKill, uint64_t Imm,
1279 bool SetFlags, bool WantResult) {
1280 assert(LHSReg && "Invalid register number.");
1282 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1286 if (isUInt<12>(Imm))
1288 else if ((Imm & 0xfff000) == Imm) {
1294 static const unsigned OpcTable[2][2][2] = {
1295 { { AArch64::SUBWri, AArch64::SUBXri },
1296 { AArch64::ADDWri, AArch64::ADDXri } },
1297 { { AArch64::SUBSWri, AArch64::SUBSXri },
1298 { AArch64::ADDSWri, AArch64::ADDSXri } }
1300 bool Is64Bit = RetVT == MVT::i64;
1301 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1302 const TargetRegisterClass *RC;
1304 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1306 RC = Is64Bit ? &AArch64::GPR64spRegClass : &AArch64::GPR32spRegClass;
1309 ResultReg = createResultReg(RC);
1311 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1313 const MCInstrDesc &II = TII.get(Opc);
1314 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1315 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1316 .addReg(LHSReg, getKillRegState(LHSIsKill))
1318 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm));
1322 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
1323 bool LHSIsKill, unsigned RHSReg,
1325 AArch64_AM::ShiftExtendType ShiftType,
1326 uint64_t ShiftImm, bool SetFlags,
1328 assert(LHSReg && RHSReg && "Invalid register number.");
1330 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1333 // Don't deal with undefined shifts.
1334 if (ShiftImm >= RetVT.getSizeInBits())
1337 static const unsigned OpcTable[2][2][2] = {
1338 { { AArch64::SUBWrs, AArch64::SUBXrs },
1339 { AArch64::ADDWrs, AArch64::ADDXrs } },
1340 { { AArch64::SUBSWrs, AArch64::SUBSXrs },
1341 { AArch64::ADDSWrs, AArch64::ADDSXrs } }
1343 bool Is64Bit = RetVT == MVT::i64;
1344 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1345 const TargetRegisterClass *RC =
1346 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1349 ResultReg = createResultReg(RC);
1351 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1353 const MCInstrDesc &II = TII.get(Opc);
1354 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1355 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
1356 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1357 .addReg(LHSReg, getKillRegState(LHSIsKill))
1358 .addReg(RHSReg, getKillRegState(RHSIsKill))
1359 .addImm(getShifterImm(ShiftType, ShiftImm));
1363 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
1364 bool LHSIsKill, unsigned RHSReg,
1366 AArch64_AM::ShiftExtendType ExtType,
1367 uint64_t ShiftImm, bool SetFlags,
1369 assert(LHSReg && RHSReg && "Invalid register number.");
1371 if (RetVT != MVT::i32 && RetVT != MVT::i64)
1377 static const unsigned OpcTable[2][2][2] = {
1378 { { AArch64::SUBWrx, AArch64::SUBXrx },
1379 { AArch64::ADDWrx, AArch64::ADDXrx } },
1380 { { AArch64::SUBSWrx, AArch64::SUBSXrx },
1381 { AArch64::ADDSWrx, AArch64::ADDSXrx } }
1383 bool Is64Bit = RetVT == MVT::i64;
1384 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit];
1385 const TargetRegisterClass *RC = nullptr;
1387 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1389 RC = Is64Bit ? &AArch64::GPR64spRegClass : &AArch64::GPR32spRegClass;
1392 ResultReg = createResultReg(RC);
1394 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1396 const MCInstrDesc &II = TII.get(Opc);
1397 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());
1398 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);
1399 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1400 .addReg(LHSReg, getKillRegState(LHSIsKill))
1401 .addReg(RHSReg, getKillRegState(RHSIsKill))
1402 .addImm(getArithExtendImm(ExtType, ShiftImm));
1406 bool AArch64FastISel::emitCmp(const Value *LHS, const Value *RHS, bool IsZExt) {
1407 Type *Ty = LHS->getType();
1408 EVT EVT = TLI.getValueType(DL, Ty, true);
1409 if (!EVT.isSimple())
1411 MVT VT = EVT.getSimpleVT();
1413 switch (VT.SimpleTy) {
1421 return emitICmp(VT, LHS, RHS, IsZExt);
1424 return emitFCmp(VT, LHS, RHS);
1428 bool AArch64FastISel::emitICmp(MVT RetVT, const Value *LHS, const Value *RHS,
1430 return emitSub(RetVT, LHS, RHS, /*SetFlags=*/true, /*WantResult=*/false,
1434 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
1436 return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, Imm,
1437 /*SetFlags=*/true, /*WantResult=*/false) != 0;
1440 bool AArch64FastISel::emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS) {
1441 if (RetVT != MVT::f32 && RetVT != MVT::f64)
1444 // Check to see if the 2nd operand is a constant that we can encode directly
1446 bool UseImm = false;
1447 if (const auto *CFP = dyn_cast<ConstantFP>(RHS))
1448 if (CFP->isZero() && !CFP->isNegative())
1451 unsigned LHSReg = getRegForValue(LHS);
1454 bool LHSIsKill = hasTrivialKill(LHS);
1457 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDri : AArch64::FCMPSri;
1458 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
1459 .addReg(LHSReg, getKillRegState(LHSIsKill));
1463 unsigned RHSReg = getRegForValue(RHS);
1466 bool RHSIsKill = hasTrivialKill(RHS);
1468 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDrr : AArch64::FCMPSrr;
1469 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
1470 .addReg(LHSReg, getKillRegState(LHSIsKill))
1471 .addReg(RHSReg, getKillRegState(RHSIsKill));
1475 unsigned AArch64FastISel::emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
1476 bool SetFlags, bool WantResult, bool IsZExt) {
1477 return emitAddSub(/*UseAdd=*/true, RetVT, LHS, RHS, SetFlags, WantResult,
1481 /// \brief This method is a wrapper to simplify add emission.
1483 /// First try to emit an add with an immediate operand using emitAddSub_ri. If
1484 /// that fails, then try to materialize the immediate into a register and use
1485 /// emitAddSub_rr instead.
1486 unsigned AArch64FastISel::emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill,
1490 ResultReg = emitAddSub_ri(false, VT, Op0, Op0IsKill, -Imm);
1492 ResultReg = emitAddSub_ri(true, VT, Op0, Op0IsKill, Imm);
1497 unsigned CReg = fastEmit_i(VT, VT, ISD::Constant, Imm);
1501 ResultReg = emitAddSub_rr(true, VT, Op0, Op0IsKill, CReg, true);
1505 unsigned AArch64FastISel::emitSub(MVT RetVT, const Value *LHS, const Value *RHS,
1506 bool SetFlags, bool WantResult, bool IsZExt) {
1507 return emitAddSub(/*UseAdd=*/false, RetVT, LHS, RHS, SetFlags, WantResult,
1511 unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg,
1512 bool LHSIsKill, unsigned RHSReg,
1513 bool RHSIsKill, bool WantResult) {
1514 return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg,
1515 RHSIsKill, /*SetFlags=*/true, WantResult);
1518 unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg,
1519 bool LHSIsKill, unsigned RHSReg,
1521 AArch64_AM::ShiftExtendType ShiftType,
1522 uint64_t ShiftImm, bool WantResult) {
1523 return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg,
1524 RHSIsKill, ShiftType, ShiftImm, /*SetFlags=*/true,
1528 unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
1529 const Value *LHS, const Value *RHS) {
1530 // Canonicalize immediates to the RHS first.
1531 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
1532 std::swap(LHS, RHS);
1534 // Canonicalize mul by power-of-2 to the RHS.
1535 if (LHS->hasOneUse() && isValueAvailable(LHS))
1536 if (isMulPowOf2(LHS))
1537 std::swap(LHS, RHS);
1539 // Canonicalize shift immediate to the RHS.
1540 if (LHS->hasOneUse() && isValueAvailable(LHS))
1541 if (const auto *SI = dyn_cast<ShlOperator>(LHS))
1542 if (isa<ConstantInt>(SI->getOperand(1)))
1543 std::swap(LHS, RHS);
1545 unsigned LHSReg = getRegForValue(LHS);
1548 bool LHSIsKill = hasTrivialKill(LHS);
1550 unsigned ResultReg = 0;
1551 if (const auto *C = dyn_cast<ConstantInt>(RHS)) {
1552 uint64_t Imm = C->getZExtValue();
1553 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm);
1558 // Check if the mul can be folded into the instruction.
1559 if (RHS->hasOneUse() && isValueAvailable(RHS)) {
1560 if (isMulPowOf2(RHS)) {
1561 const Value *MulLHS = cast<MulOperator>(RHS)->getOperand(0);
1562 const Value *MulRHS = cast<MulOperator>(RHS)->getOperand(1);
1564 if (const auto *C = dyn_cast<ConstantInt>(MulLHS))
1565 if (C->getValue().isPowerOf2())
1566 std::swap(MulLHS, MulRHS);
1568 assert(isa<ConstantInt>(MulRHS) && "Expected a ConstantInt.");
1569 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2();
1571 unsigned RHSReg = getRegForValue(MulLHS);
1574 bool RHSIsKill = hasTrivialKill(MulLHS);
1575 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,
1576 RHSIsKill, ShiftVal);
1582 // Check if the shift can be folded into the instruction.
1583 if (RHS->hasOneUse() && isValueAvailable(RHS)) {
1584 if (const auto *SI = dyn_cast<ShlOperator>(RHS))
1585 if (const auto *C = dyn_cast<ConstantInt>(SI->getOperand(1))) {
1586 uint64_t ShiftVal = C->getZExtValue();
1587 unsigned RHSReg = getRegForValue(SI->getOperand(0));
1590 bool RHSIsKill = hasTrivialKill(SI->getOperand(0));
1591 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,
1592 RHSIsKill, ShiftVal);
1598 unsigned RHSReg = getRegForValue(RHS);
1601 bool RHSIsKill = hasTrivialKill(RHS);
1603 MVT VT = std::max(MVT::i32, RetVT.SimpleTy);
1604 ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
1605 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) {
1606 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1607 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
1612 unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,
1613 unsigned LHSReg, bool LHSIsKill,
1615 assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR) &&
1616 "ISD nodes are not consecutive!");
1617 static const unsigned OpcTable[3][2] = {
1618 { AArch64::ANDWri, AArch64::ANDXri },
1619 { AArch64::ORRWri, AArch64::ORRXri },
1620 { AArch64::EORWri, AArch64::EORXri }
1622 const TargetRegisterClass *RC;
1625 switch (RetVT.SimpleTy) {
1632 unsigned Idx = ISDOpc - ISD::AND;
1633 Opc = OpcTable[Idx][0];
1634 RC = &AArch64::GPR32spRegClass;
1639 Opc = OpcTable[ISDOpc - ISD::AND][1];
1640 RC = &AArch64::GPR64spRegClass;
1645 if (!AArch64_AM::isLogicalImmediate(Imm, RegSize))
1648 unsigned ResultReg =
1649 fastEmitInst_ri(Opc, RC, LHSReg, LHSIsKill,
1650 AArch64_AM::encodeLogicalImmediate(Imm, RegSize));
1651 if (RetVT >= MVT::i8 && RetVT <= MVT::i16 && ISDOpc != ISD::AND) {
1652 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1653 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
1658 unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT,
1659 unsigned LHSReg, bool LHSIsKill,
1660 unsigned RHSReg, bool RHSIsKill,
1661 uint64_t ShiftImm) {
1662 assert((ISD::AND + 1 == ISD::OR) && (ISD::AND + 2 == ISD::XOR) &&
1663 "ISD nodes are not consecutive!");
1664 static const unsigned OpcTable[3][2] = {
1665 { AArch64::ANDWrs, AArch64::ANDXrs },
1666 { AArch64::ORRWrs, AArch64::ORRXrs },
1667 { AArch64::EORWrs, AArch64::EORXrs }
1670 // Don't deal with undefined shifts.
1671 if (ShiftImm >= RetVT.getSizeInBits())
1674 const TargetRegisterClass *RC;
1676 switch (RetVT.SimpleTy) {
1683 Opc = OpcTable[ISDOpc - ISD::AND][0];
1684 RC = &AArch64::GPR32RegClass;
1687 Opc = OpcTable[ISDOpc - ISD::AND][1];
1688 RC = &AArch64::GPR64RegClass;
1691 unsigned ResultReg =
1692 fastEmitInst_rri(Opc, RC, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
1693 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftImm));
1694 if (RetVT >= MVT::i8 && RetVT <= MVT::i16) {
1695 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1696 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
1701 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
1703 return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, LHSIsKill, Imm);
1706 unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr,
1707 bool WantZExt, MachineMemOperand *MMO) {
1708 if (!TLI.allowsMisalignedMemoryAccesses(VT))
1711 // Simplify this down to something we can handle.
1712 if (!simplifyAddress(Addr, VT))
1715 unsigned ScaleFactor = getImplicitScaleFactor(VT);
1717 llvm_unreachable("Unexpected value type.");
1719 // Negative offsets require unscaled, 9-bit, signed immediate offsets.
1720 // Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
1721 bool UseScaled = true;
1722 if ((Addr.getOffset() < 0) || (Addr.getOffset() & (ScaleFactor - 1))) {
1727 static const unsigned GPOpcTable[2][8][4] = {
1729 { { AArch64::LDURSBWi, AArch64::LDURSHWi, AArch64::LDURWi,
1731 { AArch64::LDURSBXi, AArch64::LDURSHXi, AArch64::LDURSWi,
1733 { AArch64::LDRSBWui, AArch64::LDRSHWui, AArch64::LDRWui,
1735 { AArch64::LDRSBXui, AArch64::LDRSHXui, AArch64::LDRSWui,
1737 { AArch64::LDRSBWroX, AArch64::LDRSHWroX, AArch64::LDRWroX,
1739 { AArch64::LDRSBXroX, AArch64::LDRSHXroX, AArch64::LDRSWroX,
1741 { AArch64::LDRSBWroW, AArch64::LDRSHWroW, AArch64::LDRWroW,
1743 { AArch64::LDRSBXroW, AArch64::LDRSHXroW, AArch64::LDRSWroW,
1747 { { AArch64::LDURBBi, AArch64::LDURHHi, AArch64::LDURWi,
1749 { AArch64::LDURBBi, AArch64::LDURHHi, AArch64::LDURWi,
1751 { AArch64::LDRBBui, AArch64::LDRHHui, AArch64::LDRWui,
1753 { AArch64::LDRBBui, AArch64::LDRHHui, AArch64::LDRWui,
1755 { AArch64::LDRBBroX, AArch64::LDRHHroX, AArch64::LDRWroX,
1757 { AArch64::LDRBBroX, AArch64::LDRHHroX, AArch64::LDRWroX,
1759 { AArch64::LDRBBroW, AArch64::LDRHHroW, AArch64::LDRWroW,
1761 { AArch64::LDRBBroW, AArch64::LDRHHroW, AArch64::LDRWroW,
1766 static const unsigned FPOpcTable[4][2] = {
1767 { AArch64::LDURSi, AArch64::LDURDi },
1768 { AArch64::LDRSui, AArch64::LDRDui },
1769 { AArch64::LDRSroX, AArch64::LDRDroX },
1770 { AArch64::LDRSroW, AArch64::LDRDroW }
1774 const TargetRegisterClass *RC;
1775 bool UseRegOffset = Addr.isRegBase() && !Addr.getOffset() && Addr.getReg() &&
1776 Addr.getOffsetReg();
1777 unsigned Idx = UseRegOffset ? 2 : UseScaled ? 1 : 0;
1778 if (Addr.getExtendType() == AArch64_AM::UXTW ||
1779 Addr.getExtendType() == AArch64_AM::SXTW)
1782 bool IsRet64Bit = RetVT == MVT::i64;
1783 switch (VT.SimpleTy) {
1785 llvm_unreachable("Unexpected value type.");
1786 case MVT::i1: // Intentional fall-through.
1788 Opc = GPOpcTable[WantZExt][2 * Idx + IsRet64Bit][0];
1789 RC = (IsRet64Bit && !WantZExt) ?
1790 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;
1793 Opc = GPOpcTable[WantZExt][2 * Idx + IsRet64Bit][1];
1794 RC = (IsRet64Bit && !WantZExt) ?
1795 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;
1798 Opc = GPOpcTable[WantZExt][2 * Idx + IsRet64Bit][2];
1799 RC = (IsRet64Bit && !WantZExt) ?
1800 &AArch64::GPR64RegClass: &AArch64::GPR32RegClass;
1803 Opc = GPOpcTable[WantZExt][2 * Idx + IsRet64Bit][3];
1804 RC = &AArch64::GPR64RegClass;
1807 Opc = FPOpcTable[Idx][0];
1808 RC = &AArch64::FPR32RegClass;
1811 Opc = FPOpcTable[Idx][1];
1812 RC = &AArch64::FPR64RegClass;
1816 // Create the base instruction, then add the operands.
1817 unsigned ResultReg = createResultReg(RC);
1818 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1819 TII.get(Opc), ResultReg);
1820 addLoadStoreOperands(Addr, MIB, MachineMemOperand::MOLoad, ScaleFactor, MMO);
1822 // Loading an i1 requires special handling.
1823 if (VT == MVT::i1) {
1824 unsigned ANDReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, 1);
1825 assert(ANDReg && "Unexpected AND instruction emission failure.");
1829 // For zero-extending loads to 64bit we emit a 32bit load and then convert
1830 // the 32bit reg to a 64bit reg.
1831 if (WantZExt && RetVT == MVT::i64 && VT <= MVT::i32) {
1832 unsigned Reg64 = createResultReg(&AArch64::GPR64RegClass);
1833 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1834 TII.get(AArch64::SUBREG_TO_REG), Reg64)
1836 .addReg(ResultReg, getKillRegState(true))
1837 .addImm(AArch64::sub_32);
1843 bool AArch64FastISel::selectAddSub(const Instruction *I) {
1845 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true))
1849 return selectOperator(I, I->getOpcode());
1852 switch (I->getOpcode()) {
1854 llvm_unreachable("Unexpected instruction.");
1855 case Instruction::Add:
1856 ResultReg = emitAdd(VT, I->getOperand(0), I->getOperand(1));
1858 case Instruction::Sub:
1859 ResultReg = emitSub(VT, I->getOperand(0), I->getOperand(1));
1865 updateValueMap(I, ResultReg);
1869 bool AArch64FastISel::selectLogicalOp(const Instruction *I) {
1871 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true))
1875 return selectOperator(I, I->getOpcode());
1878 switch (I->getOpcode()) {
1880 llvm_unreachable("Unexpected instruction.");
1881 case Instruction::And:
1882 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
1884 case Instruction::Or:
1885 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
1887 case Instruction::Xor:
1888 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
1894 updateValueMap(I, ResultReg);
1898 bool AArch64FastISel::selectLoad(const Instruction *I) {
1900 // Verify we have a legal type before going any further. Currently, we handle
1901 // simple types that will directly fit in a register (i32/f32/i64/f64) or
1902 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
1903 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true) ||
1904 cast<LoadInst>(I)->isAtomic())
1907 // See if we can handle this address.
1909 if (!computeAddress(I->getOperand(0), Addr, I->getType()))
1912 // Fold the following sign-/zero-extend into the load instruction.
1913 bool WantZExt = true;
1915 const Value *IntExtVal = nullptr;
1916 if (I->hasOneUse()) {
1917 if (const auto *ZE = dyn_cast<ZExtInst>(I->use_begin()->getUser())) {
1918 if (isTypeSupported(ZE->getType(), RetVT))
1922 } else if (const auto *SE = dyn_cast<SExtInst>(I->use_begin()->getUser())) {
1923 if (isTypeSupported(SE->getType(), RetVT))
1931 unsigned ResultReg =
1932 emitLoad(VT, RetVT, Addr, WantZExt, createMachineMemOperandFor(I));
1936 // There are a few different cases we have to handle, because the load or the
1937 // sign-/zero-extend might not be selected by FastISel if we fall-back to
1938 // SelectionDAG. There is also an ordering issue when both instructions are in
1939 // different basic blocks.
1940 // 1.) The load instruction is selected by FastISel, but the integer extend
1941 // not. This usually happens when the integer extend is in a different
1942 // basic block and SelectionDAG took over for that basic block.
1943 // 2.) The load instruction is selected before the integer extend. This only
1944 // happens when the integer extend is in a different basic block.
1945 // 3.) The load instruction is selected by SelectionDAG and the integer extend
1946 // by FastISel. This happens if there are instructions between the load
1947 // and the integer extend that couldn't be selected by FastISel.
1949 // The integer extend hasn't been emitted yet. FastISel or SelectionDAG
1950 // could select it. Emit a copy to subreg if necessary. FastISel will remove
1951 // it when it selects the integer extend.
1952 unsigned Reg = lookUpRegForValue(IntExtVal);
1953 auto *MI = MRI.getUniqueVRegDef(Reg);
1955 if (RetVT == MVT::i64 && VT <= MVT::i32) {
1957 // Delete the last emitted instruction from emitLoad (SUBREG_TO_REG).
1958 std::prev(FuncInfo.InsertPt)->eraseFromParent();
1959 ResultReg = std::prev(FuncInfo.InsertPt)->getOperand(0).getReg();
1961 ResultReg = fastEmitInst_extractsubreg(MVT::i32, ResultReg,
1965 updateValueMap(I, ResultReg);
1969 // The integer extend has already been emitted - delete all the instructions
1970 // that have been emitted by the integer extend lowering code and use the
1971 // result from the load instruction directly.
1974 for (auto &Opnd : MI->uses()) {
1976 Reg = Opnd.getReg();
1980 MI->eraseFromParent();
1983 MI = MRI.getUniqueVRegDef(Reg);
1985 updateValueMap(IntExtVal, ResultReg);
1989 updateValueMap(I, ResultReg);
1993 bool AArch64FastISel::emitStore(MVT VT, unsigned SrcReg, Address Addr,
1994 MachineMemOperand *MMO) {
1995 if (!TLI.allowsMisalignedMemoryAccesses(VT))
1998 // Simplify this down to something we can handle.
1999 if (!simplifyAddress(Addr, VT))
2002 unsigned ScaleFactor = getImplicitScaleFactor(VT);
2004 llvm_unreachable("Unexpected value type.");
2006 // Negative offsets require unscaled, 9-bit, signed immediate offsets.
2007 // Otherwise, we try using scaled, 12-bit, unsigned immediate offsets.
2008 bool UseScaled = true;
2009 if ((Addr.getOffset() < 0) || (Addr.getOffset() & (ScaleFactor - 1))) {
2014 static const unsigned OpcTable[4][6] = {
2015 { AArch64::STURBBi, AArch64::STURHHi, AArch64::STURWi, AArch64::STURXi,
2016 AArch64::STURSi, AArch64::STURDi },
2017 { AArch64::STRBBui, AArch64::STRHHui, AArch64::STRWui, AArch64::STRXui,
2018 AArch64::STRSui, AArch64::STRDui },
2019 { AArch64::STRBBroX, AArch64::STRHHroX, AArch64::STRWroX, AArch64::STRXroX,
2020 AArch64::STRSroX, AArch64::STRDroX },
2021 { AArch64::STRBBroW, AArch64::STRHHroW, AArch64::STRWroW, AArch64::STRXroW,
2022 AArch64::STRSroW, AArch64::STRDroW }
2026 bool VTIsi1 = false;
2027 bool UseRegOffset = Addr.isRegBase() && !Addr.getOffset() && Addr.getReg() &&
2028 Addr.getOffsetReg();
2029 unsigned Idx = UseRegOffset ? 2 : UseScaled ? 1 : 0;
2030 if (Addr.getExtendType() == AArch64_AM::UXTW ||
2031 Addr.getExtendType() == AArch64_AM::SXTW)
2034 switch (VT.SimpleTy) {
2035 default: llvm_unreachable("Unexpected value type.");
2036 case MVT::i1: VTIsi1 = true;
2037 case MVT::i8: Opc = OpcTable[Idx][0]; break;
2038 case MVT::i16: Opc = OpcTable[Idx][1]; break;
2039 case MVT::i32: Opc = OpcTable[Idx][2]; break;
2040 case MVT::i64: Opc = OpcTable[Idx][3]; break;
2041 case MVT::f32: Opc = OpcTable[Idx][4]; break;
2042 case MVT::f64: Opc = OpcTable[Idx][5]; break;
2045 // Storing an i1 requires special handling.
2046 if (VTIsi1 && SrcReg != AArch64::WZR) {
2047 unsigned ANDReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1);
2048 assert(ANDReg && "Unexpected AND instruction emission failure.");
2051 // Create the base instruction, then add the operands.
2052 const MCInstrDesc &II = TII.get(Opc);
2053 SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs());
2054 MachineInstrBuilder MIB =
2055 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(SrcReg);
2056 addLoadStoreOperands(Addr, MIB, MachineMemOperand::MOStore, ScaleFactor, MMO);
2061 bool AArch64FastISel::selectStore(const Instruction *I) {
2063 const Value *Op0 = I->getOperand(0);
2064 // Verify we have a legal type before going any further. Currently, we handle
2065 // simple types that will directly fit in a register (i32/f32/i64/f64) or
2066 // those that can be sign or zero-extended to a basic operation (i1/i8/i16).
2067 if (!isTypeSupported(Op0->getType(), VT, /*IsVectorAllowed=*/true) ||
2068 cast<StoreInst>(I)->isAtomic())
2071 // Get the value to be stored into a register. Use the zero register directly
2072 // when possible to avoid an unnecessary copy and a wasted register.
2073 unsigned SrcReg = 0;
2074 if (const auto *CI = dyn_cast<ConstantInt>(Op0)) {
2076 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
2077 } else if (const auto *CF = dyn_cast<ConstantFP>(Op0)) {
2078 if (CF->isZero() && !CF->isNegative()) {
2079 VT = MVT::getIntegerVT(VT.getSizeInBits());
2080 SrcReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
2085 SrcReg = getRegForValue(Op0);
2090 // See if we can handle this address.
2092 if (!computeAddress(I->getOperand(1), Addr, I->getOperand(0)->getType()))
2095 if (!emitStore(VT, SrcReg, Addr, createMachineMemOperandFor(I)))
2100 static AArch64CC::CondCode getCompareCC(CmpInst::Predicate Pred) {
2102 case CmpInst::FCMP_ONE:
2103 case CmpInst::FCMP_UEQ:
2105 // AL is our "false" for now. The other two need more compares.
2106 return AArch64CC::AL;
2107 case CmpInst::ICMP_EQ:
2108 case CmpInst::FCMP_OEQ:
2109 return AArch64CC::EQ;
2110 case CmpInst::ICMP_SGT:
2111 case CmpInst::FCMP_OGT:
2112 return AArch64CC::GT;
2113 case CmpInst::ICMP_SGE:
2114 case CmpInst::FCMP_OGE:
2115 return AArch64CC::GE;
2116 case CmpInst::ICMP_UGT:
2117 case CmpInst::FCMP_UGT:
2118 return AArch64CC::HI;
2119 case CmpInst::FCMP_OLT:
2120 return AArch64CC::MI;
2121 case CmpInst::ICMP_ULE:
2122 case CmpInst::FCMP_OLE:
2123 return AArch64CC::LS;
2124 case CmpInst::FCMP_ORD:
2125 return AArch64CC::VC;
2126 case CmpInst::FCMP_UNO:
2127 return AArch64CC::VS;
2128 case CmpInst::FCMP_UGE:
2129 return AArch64CC::PL;
2130 case CmpInst::ICMP_SLT:
2131 case CmpInst::FCMP_ULT:
2132 return AArch64CC::LT;
2133 case CmpInst::ICMP_SLE:
2134 case CmpInst::FCMP_ULE:
2135 return AArch64CC::LE;
2136 case CmpInst::FCMP_UNE:
2137 case CmpInst::ICMP_NE:
2138 return AArch64CC::NE;
2139 case CmpInst::ICMP_UGE:
2140 return AArch64CC::HS;
2141 case CmpInst::ICMP_ULT:
2142 return AArch64CC::LO;
2146 /// \brief Try to emit a combined compare-and-branch instruction.
2147 bool AArch64FastISel::emitCompareAndBranch(const BranchInst *BI) {
2148 assert(isa<CmpInst>(BI->getCondition()) && "Expected cmp instruction");
2149 const CmpInst *CI = cast<CmpInst>(BI->getCondition());
2150 CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
2152 const Value *LHS = CI->getOperand(0);
2153 const Value *RHS = CI->getOperand(1);
2156 if (!isTypeSupported(LHS->getType(), VT))
2159 unsigned BW = VT.getSizeInBits();
2163 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
2164 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
2166 // Try to take advantage of fallthrough opportunities.
2167 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
2168 std::swap(TBB, FBB);
2169 Predicate = CmpInst::getInversePredicate(Predicate);
2174 switch (Predicate) {
2177 case CmpInst::ICMP_EQ:
2178 case CmpInst::ICMP_NE:
2179 if (isa<Constant>(LHS) && cast<Constant>(LHS)->isNullValue())
2180 std::swap(LHS, RHS);
2182 if (!isa<Constant>(RHS) || !cast<Constant>(RHS)->isNullValue())
2185 if (const auto *AI = dyn_cast<BinaryOperator>(LHS))
2186 if (AI->getOpcode() == Instruction::And && isValueAvailable(AI)) {
2187 const Value *AndLHS = AI->getOperand(0);
2188 const Value *AndRHS = AI->getOperand(1);
2190 if (const auto *C = dyn_cast<ConstantInt>(AndLHS))
2191 if (C->getValue().isPowerOf2())
2192 std::swap(AndLHS, AndRHS);
2194 if (const auto *C = dyn_cast<ConstantInt>(AndRHS))
2195 if (C->getValue().isPowerOf2()) {
2196 TestBit = C->getValue().logBase2();
2204 IsCmpNE = Predicate == CmpInst::ICMP_NE;
2206 case CmpInst::ICMP_SLT:
2207 case CmpInst::ICMP_SGE:
2208 if (!isa<Constant>(RHS) || !cast<Constant>(RHS)->isNullValue())
2212 IsCmpNE = Predicate == CmpInst::ICMP_SLT;
2214 case CmpInst::ICMP_SGT:
2215 case CmpInst::ICMP_SLE:
2216 if (!isa<ConstantInt>(RHS))
2219 if (cast<ConstantInt>(RHS)->getValue() != APInt(BW, -1, true))
2223 IsCmpNE = Predicate == CmpInst::ICMP_SLE;
2227 static const unsigned OpcTable[2][2][2] = {
2228 { {AArch64::CBZW, AArch64::CBZX },
2229 {AArch64::CBNZW, AArch64::CBNZX} },
2230 { {AArch64::TBZW, AArch64::TBZX },
2231 {AArch64::TBNZW, AArch64::TBNZX} }
2234 bool IsBitTest = TestBit != -1;
2235 bool Is64Bit = BW == 64;
2236 if (TestBit < 32 && TestBit >= 0)
2239 unsigned Opc = OpcTable[IsBitTest][IsCmpNE][Is64Bit];
2240 const MCInstrDesc &II = TII.get(Opc);
2242 unsigned SrcReg = getRegForValue(LHS);
2245 bool SrcIsKill = hasTrivialKill(LHS);
2247 if (BW == 64 && !Is64Bit)
2248 SrcReg = fastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill,
2251 if ((BW < 32) && !IsBitTest)
2252 SrcReg = emitIntExt(VT, SrcReg, MVT::i32, /*IsZExt=*/true);
2254 // Emit the combined compare and branch instruction.
2255 SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs());
2256 MachineInstrBuilder MIB =
2257 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
2258 .addReg(SrcReg, getKillRegState(SrcIsKill));
2260 MIB.addImm(TestBit);
2263 finishCondBranch(BI->getParent(), TBB, FBB);
2267 bool AArch64FastISel::selectBranch(const Instruction *I) {
2268 const BranchInst *BI = cast<BranchInst>(I);
2269 if (BI->isUnconditional()) {
2270 MachineBasicBlock *MSucc = FuncInfo.MBBMap[BI->getSuccessor(0)];
2271 fastEmitBranch(MSucc, BI->getDebugLoc());
2275 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
2276 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
2278 AArch64CC::CondCode CC = AArch64CC::NE;
2279 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
2280 if (CI->hasOneUse() && isValueAvailable(CI)) {
2281 // Try to optimize or fold the cmp.
2282 CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
2283 switch (Predicate) {
2286 case CmpInst::FCMP_FALSE:
2287 fastEmitBranch(FBB, DbgLoc);
2289 case CmpInst::FCMP_TRUE:
2290 fastEmitBranch(TBB, DbgLoc);
2294 // Try to emit a combined compare-and-branch first.
2295 if (emitCompareAndBranch(BI))
2298 // Try to take advantage of fallthrough opportunities.
2299 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
2300 std::swap(TBB, FBB);
2301 Predicate = CmpInst::getInversePredicate(Predicate);
2305 if (!emitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
2308 // FCMP_UEQ and FCMP_ONE cannot be checked with a single branch
2310 CC = getCompareCC(Predicate);
2311 AArch64CC::CondCode ExtraCC = AArch64CC::AL;
2312 switch (Predicate) {
2315 case CmpInst::FCMP_UEQ:
2316 ExtraCC = AArch64CC::EQ;
2319 case CmpInst::FCMP_ONE:
2320 ExtraCC = AArch64CC::MI;
2324 assert((CC != AArch64CC::AL) && "Unexpected condition code.");
2326 // Emit the extra branch for FCMP_UEQ and FCMP_ONE.
2327 if (ExtraCC != AArch64CC::AL) {
2328 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2334 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2338 finishCondBranch(BI->getParent(), TBB, FBB);
2341 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
2343 if (TI->hasOneUse() && isValueAvailable(TI) &&
2344 isTypeSupported(TI->getOperand(0)->getType(), SrcVT)) {
2345 unsigned CondReg = getRegForValue(TI->getOperand(0));
2348 bool CondIsKill = hasTrivialKill(TI->getOperand(0));
2350 // Issue an extract_subreg to get the lower 32-bits.
2351 if (SrcVT == MVT::i64) {
2352 CondReg = fastEmitInst_extractsubreg(MVT::i32, CondReg, CondIsKill,
2357 unsigned ANDReg = emitAnd_ri(MVT::i32, CondReg, CondIsKill, 1);
2358 assert(ANDReg && "Unexpected AND instruction emission failure.");
2359 emitICmp_ri(MVT::i32, ANDReg, /*IsKill=*/true, 0);
2361 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
2362 std::swap(TBB, FBB);
2365 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2369 finishCondBranch(BI->getParent(), TBB, FBB);
2372 } else if (const auto *CI = dyn_cast<ConstantInt>(BI->getCondition())) {
2373 uint64_t Imm = CI->getZExtValue();
2374 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
2375 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::B))
2378 // Obtain the branch weight and add the target to the successor list.
2380 uint32_t BranchWeight =
2381 FuncInfo.BPI->getEdgeWeight(BI->getParent(), Target->getBasicBlock());
2382 FuncInfo.MBB->addSuccessor(Target, BranchWeight);
2384 FuncInfo.MBB->addSuccessorWithoutWeight(Target);
2386 } else if (foldXALUIntrinsic(CC, I, BI->getCondition())) {
2387 // Fake request the condition, otherwise the intrinsic might be completely
2389 unsigned CondReg = getRegForValue(BI->getCondition());
2394 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2398 finishCondBranch(BI->getParent(), TBB, FBB);
2402 unsigned CondReg = getRegForValue(BI->getCondition());
2405 bool CondRegIsKill = hasTrivialKill(BI->getCondition());
2407 // We've been divorced from our compare! Our block was split, and
2408 // now our compare lives in a predecessor block. We musn't
2409 // re-compare here, as the children of the compare aren't guaranteed
2410 // live across the block boundary (we *could* check for this).
2411 // Regardless, the compare has been done in the predecessor block,
2412 // and it left a value for us in a virtual register. Ergo, we test
2413 // the one-bit value left in the virtual register.
2415 // FIXME: Optimize this with TBZW/TBZNW.
2416 unsigned ANDReg = emitAnd_ri(MVT::i32, CondReg, CondRegIsKill, 1);
2417 assert(ANDReg && "Unexpected AND instruction emission failure.");
2418 emitICmp_ri(MVT::i32, ANDReg, /*IsKill=*/true, 0);
2420 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
2421 std::swap(TBB, FBB);
2425 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::Bcc))
2429 finishCondBranch(BI->getParent(), TBB, FBB);
2433 bool AArch64FastISel::selectIndirectBr(const Instruction *I) {
2434 const IndirectBrInst *BI = cast<IndirectBrInst>(I);
2435 unsigned AddrReg = getRegForValue(BI->getOperand(0));
2439 // Emit the indirect branch.
2440 const MCInstrDesc &II = TII.get(AArch64::BR);
2441 AddrReg = constrainOperandRegClass(II, AddrReg, II.getNumDefs());
2442 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(AddrReg);
2444 // Make sure the CFG is up-to-date.
2445 for (auto *Succ : BI->successors())
2446 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[Succ]);
2451 bool AArch64FastISel::selectCmp(const Instruction *I) {
2452 const CmpInst *CI = cast<CmpInst>(I);
2454 // Try to optimize or fold the cmp.
2455 CmpInst::Predicate Predicate = optimizeCmpPredicate(CI);
2456 unsigned ResultReg = 0;
2457 switch (Predicate) {
2460 case CmpInst::FCMP_FALSE:
2461 ResultReg = createResultReg(&AArch64::GPR32RegClass);
2462 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2463 TII.get(TargetOpcode::COPY), ResultReg)
2464 .addReg(AArch64::WZR, getKillRegState(true));
2466 case CmpInst::FCMP_TRUE:
2467 ResultReg = fastEmit_i(MVT::i32, MVT::i32, ISD::Constant, 1);
2472 updateValueMap(I, ResultReg);
2477 if (!emitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
2480 ResultReg = createResultReg(&AArch64::GPR32RegClass);
2482 // FCMP_UEQ and FCMP_ONE cannot be checked with a single instruction. These
2483 // condition codes are inverted, because they are used by CSINC.
2484 static unsigned CondCodeTable[2][2] = {
2485 { AArch64CC::NE, AArch64CC::VC },
2486 { AArch64CC::PL, AArch64CC::LE }
2488 unsigned *CondCodes = nullptr;
2489 switch (Predicate) {
2492 case CmpInst::FCMP_UEQ:
2493 CondCodes = &CondCodeTable[0][0];
2495 case CmpInst::FCMP_ONE:
2496 CondCodes = &CondCodeTable[1][0];
2501 unsigned TmpReg1 = createResultReg(&AArch64::GPR32RegClass);
2502 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
2504 .addReg(AArch64::WZR, getKillRegState(true))
2505 .addReg(AArch64::WZR, getKillRegState(true))
2506 .addImm(CondCodes[0]);
2507 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
2509 .addReg(TmpReg1, getKillRegState(true))
2510 .addReg(AArch64::WZR, getKillRegState(true))
2511 .addImm(CondCodes[1]);
2513 updateValueMap(I, ResultReg);
2517 // Now set a register based on the comparison.
2518 AArch64CC::CondCode CC = getCompareCC(Predicate);
2519 assert((CC != AArch64CC::AL) && "Unexpected condition code.");
2520 AArch64CC::CondCode invertedCC = getInvertedCondCode(CC);
2521 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
2523 .addReg(AArch64::WZR, getKillRegState(true))
2524 .addReg(AArch64::WZR, getKillRegState(true))
2525 .addImm(invertedCC);
2527 updateValueMap(I, ResultReg);
2531 /// \brief Optimize selects of i1 if one of the operands has a 'true' or 'false'
2533 bool AArch64FastISel::optimizeSelect(const SelectInst *SI) {
2534 if (!SI->getType()->isIntegerTy(1))
2537 const Value *Src1Val, *Src2Val;
2539 bool NeedExtraOp = false;
2540 if (auto *CI = dyn_cast<ConstantInt>(SI->getTrueValue())) {
2542 Src1Val = SI->getCondition();
2543 Src2Val = SI->getFalseValue();
2544 Opc = AArch64::ORRWrr;
2546 assert(CI->isZero());
2547 Src1Val = SI->getFalseValue();
2548 Src2Val = SI->getCondition();
2549 Opc = AArch64::BICWrr;
2551 } else if (auto *CI = dyn_cast<ConstantInt>(SI->getFalseValue())) {
2553 Src1Val = SI->getCondition();
2554 Src2Val = SI->getTrueValue();
2555 Opc = AArch64::ORRWrr;
2558 assert(CI->isZero());
2559 Src1Val = SI->getCondition();
2560 Src2Val = SI->getTrueValue();
2561 Opc = AArch64::ANDWrr;
2568 unsigned Src1Reg = getRegForValue(Src1Val);
2571 bool Src1IsKill = hasTrivialKill(Src1Val);
2573 unsigned Src2Reg = getRegForValue(Src2Val);
2576 bool Src2IsKill = hasTrivialKill(Src2Val);
2579 Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, Src1IsKill, 1);
2582 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg,
2583 Src1IsKill, Src2Reg, Src2IsKill);
2584 updateValueMap(SI, ResultReg);
2588 bool AArch64FastISel::selectSelect(const Instruction *I) {
2589 assert(isa<SelectInst>(I) && "Expected a select instruction.");
2591 if (!isTypeSupported(I->getType(), VT))
2595 const TargetRegisterClass *RC;
2596 switch (VT.SimpleTy) {
2603 Opc = AArch64::CSELWr;
2604 RC = &AArch64::GPR32RegClass;
2607 Opc = AArch64::CSELXr;
2608 RC = &AArch64::GPR64RegClass;
2611 Opc = AArch64::FCSELSrrr;
2612 RC = &AArch64::FPR32RegClass;
2615 Opc = AArch64::FCSELDrrr;
2616 RC = &AArch64::FPR64RegClass;
2620 const SelectInst *SI = cast<SelectInst>(I);
2621 const Value *Cond = SI->getCondition();
2622 AArch64CC::CondCode CC = AArch64CC::NE;
2623 AArch64CC::CondCode ExtraCC = AArch64CC::AL;
2625 if (optimizeSelect(SI))
2628 // Try to pickup the flags, so we don't have to emit another compare.
2629 if (foldXALUIntrinsic(CC, I, Cond)) {
2630 // Fake request the condition to force emission of the XALU intrinsic.
2631 unsigned CondReg = getRegForValue(Cond);
2634 } else if (isa<CmpInst>(Cond) && cast<CmpInst>(Cond)->hasOneUse() &&
2635 isValueAvailable(Cond)) {
2636 const auto *Cmp = cast<CmpInst>(Cond);
2637 // Try to optimize or fold the cmp.
2638 CmpInst::Predicate Predicate = optimizeCmpPredicate(Cmp);
2639 const Value *FoldSelect = nullptr;
2640 switch (Predicate) {
2643 case CmpInst::FCMP_FALSE:
2644 FoldSelect = SI->getFalseValue();
2646 case CmpInst::FCMP_TRUE:
2647 FoldSelect = SI->getTrueValue();
2652 unsigned SrcReg = getRegForValue(FoldSelect);
2655 unsigned UseReg = lookUpRegForValue(SI);
2657 MRI.clearKillFlags(UseReg);
2659 updateValueMap(I, SrcReg);
2664 if (!emitCmp(Cmp->getOperand(0), Cmp->getOperand(1), Cmp->isUnsigned()))
2667 // FCMP_UEQ and FCMP_ONE cannot be checked with a single select instruction.
2668 CC = getCompareCC(Predicate);
2669 switch (Predicate) {
2672 case CmpInst::FCMP_UEQ:
2673 ExtraCC = AArch64CC::EQ;
2676 case CmpInst::FCMP_ONE:
2677 ExtraCC = AArch64CC::MI;
2681 assert((CC != AArch64CC::AL) && "Unexpected condition code.");
2683 unsigned CondReg = getRegForValue(Cond);
2686 bool CondIsKill = hasTrivialKill(Cond);
2688 const MCInstrDesc &II = TII.get(AArch64::ANDSWri);
2689 CondReg = constrainOperandRegClass(II, CondReg, 1);
2691 // Emit a TST instruction (ANDS wzr, reg, #imm).
2692 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
2694 .addReg(CondReg, getKillRegState(CondIsKill))
2695 .addImm(AArch64_AM::encodeLogicalImmediate(1, 32));
2698 unsigned Src1Reg = getRegForValue(SI->getTrueValue());
2699 bool Src1IsKill = hasTrivialKill(SI->getTrueValue());
2701 unsigned Src2Reg = getRegForValue(SI->getFalseValue());
2702 bool Src2IsKill = hasTrivialKill(SI->getFalseValue());
2704 if (!Src1Reg || !Src2Reg)
2707 if (ExtraCC != AArch64CC::AL) {
2708 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg,
2709 Src2IsKill, ExtraCC);
2712 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg,
2714 updateValueMap(I, ResultReg);
2718 bool AArch64FastISel::selectFPExt(const Instruction *I) {
2719 Value *V = I->getOperand(0);
2720 if (!I->getType()->isDoubleTy() || !V->getType()->isFloatTy())
2723 unsigned Op = getRegForValue(V);
2727 unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass);
2728 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTDSr),
2729 ResultReg).addReg(Op);
2730 updateValueMap(I, ResultReg);
2734 bool AArch64FastISel::selectFPTrunc(const Instruction *I) {
2735 Value *V = I->getOperand(0);
2736 if (!I->getType()->isFloatTy() || !V->getType()->isDoubleTy())
2739 unsigned Op = getRegForValue(V);
2743 unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass);
2744 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTSDr),
2745 ResultReg).addReg(Op);
2746 updateValueMap(I, ResultReg);
2750 // FPToUI and FPToSI
2751 bool AArch64FastISel::selectFPToInt(const Instruction *I, bool Signed) {
2753 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
2756 unsigned SrcReg = getRegForValue(I->getOperand(0));
2760 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true);
2761 if (SrcVT == MVT::f128)
2765 if (SrcVT == MVT::f64) {
2767 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;
2769 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;
2772 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;
2774 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;
2776 unsigned ResultReg = createResultReg(
2777 DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);
2778 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
2780 updateValueMap(I, ResultReg);
2784 bool AArch64FastISel::selectIntToFP(const Instruction *I, bool Signed) {
2786 if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
2788 assert ((DestVT == MVT::f32 || DestVT == MVT::f64) &&
2789 "Unexpected value type.");
2791 unsigned SrcReg = getRegForValue(I->getOperand(0));
2794 bool SrcIsKill = hasTrivialKill(I->getOperand(0));
2796 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType(), true);
2798 // Handle sign-extension.
2799 if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) {
2801 emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);
2808 if (SrcVT == MVT::i64) {
2810 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;
2812 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;
2815 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;
2817 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;
2820 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg,
2822 updateValueMap(I, ResultReg);
2826 bool AArch64FastISel::fastLowerArguments() {
2827 if (!FuncInfo.CanLowerReturn)
2830 const Function *F = FuncInfo.Fn;
2834 CallingConv::ID CC = F->getCallingConv();
2835 if (CC != CallingConv::C)
2838 // Only handle simple cases of up to 8 GPR and FPR each.
2839 unsigned GPRCnt = 0;
2840 unsigned FPRCnt = 0;
2842 for (auto const &Arg : F->args()) {
2843 // The first argument is at index 1.
2845 if (F->getAttributes().hasAttribute(Idx, Attribute::ByVal) ||
2846 F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
2847 F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
2848 F->getAttributes().hasAttribute(Idx, Attribute::Nest))
2851 Type *ArgTy = Arg.getType();
2852 if (ArgTy->isStructTy() || ArgTy->isArrayTy())
2855 EVT ArgVT = TLI.getValueType(DL, ArgTy);
2856 if (!ArgVT.isSimple())
2859 MVT VT = ArgVT.getSimpleVT().SimpleTy;
2860 if (VT.isFloatingPoint() && !Subtarget->hasFPARMv8())
2863 if (VT.isVector() &&
2864 (!Subtarget->hasNEON() || !Subtarget->isLittleEndian()))
2867 if (VT >= MVT::i1 && VT <= MVT::i64)
2869 else if ((VT >= MVT::f16 && VT <= MVT::f64) || VT.is64BitVector() ||
2870 VT.is128BitVector())
2875 if (GPRCnt > 8 || FPRCnt > 8)
2879 static const MCPhysReg Registers[6][8] = {
2880 { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4,
2881 AArch64::W5, AArch64::W6, AArch64::W7 },
2882 { AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4,
2883 AArch64::X5, AArch64::X6, AArch64::X7 },
2884 { AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4,
2885 AArch64::H5, AArch64::H6, AArch64::H7 },
2886 { AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4,
2887 AArch64::S5, AArch64::S6, AArch64::S7 },
2888 { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
2889 AArch64::D5, AArch64::D6, AArch64::D7 },
2890 { AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4,
2891 AArch64::Q5, AArch64::Q6, AArch64::Q7 }
2894 unsigned GPRIdx = 0;
2895 unsigned FPRIdx = 0;
2896 for (auto const &Arg : F->args()) {
2897 MVT VT = TLI.getSimpleValueType(DL, Arg.getType());
2899 const TargetRegisterClass *RC;
2900 if (VT >= MVT::i1 && VT <= MVT::i32) {
2901 SrcReg = Registers[0][GPRIdx++];
2902 RC = &AArch64::GPR32RegClass;
2904 } else if (VT == MVT::i64) {
2905 SrcReg = Registers[1][GPRIdx++];
2906 RC = &AArch64::GPR64RegClass;
2907 } else if (VT == MVT::f16) {
2908 SrcReg = Registers[2][FPRIdx++];
2909 RC = &AArch64::FPR16RegClass;
2910 } else if (VT == MVT::f32) {
2911 SrcReg = Registers[3][FPRIdx++];
2912 RC = &AArch64::FPR32RegClass;
2913 } else if ((VT == MVT::f64) || VT.is64BitVector()) {
2914 SrcReg = Registers[4][FPRIdx++];
2915 RC = &AArch64::FPR64RegClass;
2916 } else if (VT.is128BitVector()) {
2917 SrcReg = Registers[5][FPRIdx++];
2918 RC = &AArch64::FPR128RegClass;
2920 llvm_unreachable("Unexpected value type.");
2922 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
2923 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
2924 // Without this, EmitLiveInCopies may eliminate the livein if its only
2925 // use is a bitcast (which isn't turned into an instruction).
2926 unsigned ResultReg = createResultReg(RC);
2927 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2928 TII.get(TargetOpcode::COPY), ResultReg)
2929 .addReg(DstReg, getKillRegState(true));
2930 updateValueMap(&Arg, ResultReg);
2935 bool AArch64FastISel::processCallArgs(CallLoweringInfo &CLI,
2936 SmallVectorImpl<MVT> &OutVTs,
2937 unsigned &NumBytes) {
2938 CallingConv::ID CC = CLI.CallConv;
2939 SmallVector<CCValAssign, 16> ArgLocs;
2940 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
2941 CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
2943 // Get a count of how many bytes are to be pushed on the stack.
2944 NumBytes = CCInfo.getNextStackOffset();
2946 // Issue CALLSEQ_START
2947 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
2948 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
2951 // Process the args.
2952 for (CCValAssign &VA : ArgLocs) {
2953 const Value *ArgVal = CLI.OutVals[VA.getValNo()];
2954 MVT ArgVT = OutVTs[VA.getValNo()];
2956 unsigned ArgReg = getRegForValue(ArgVal);
2960 // Handle arg promotion: SExt, ZExt, AExt.
2961 switch (VA.getLocInfo()) {
2962 case CCValAssign::Full:
2964 case CCValAssign::SExt: {
2965 MVT DestVT = VA.getLocVT();
2967 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
2972 case CCValAssign::AExt:
2973 // Intentional fall-through.
2974 case CCValAssign::ZExt: {
2975 MVT DestVT = VA.getLocVT();
2977 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
2983 llvm_unreachable("Unknown arg promotion!");
2986 // Now copy/store arg to correct locations.
2987 if (VA.isRegLoc() && !VA.needsCustom()) {
2988 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2989 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
2990 CLI.OutRegs.push_back(VA.getLocReg());
2991 } else if (VA.needsCustom()) {
2992 // FIXME: Handle custom args.
2995 assert(VA.isMemLoc() && "Assuming store on stack.");
2997 // Don't emit stores for undef values.
2998 if (isa<UndefValue>(ArgVal))
3001 // Need to store on the stack.
3002 unsigned ArgSize = (ArgVT.getSizeInBits() + 7) / 8;
3004 unsigned BEAlign = 0;
3005 if (ArgSize < 8 && !Subtarget->isLittleEndian())
3006 BEAlign = 8 - ArgSize;
3009 Addr.setKind(Address::RegBase);
3010 Addr.setReg(AArch64::SP);
3011 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
3013 unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
3014 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
3015 MachinePointerInfo::getStack(*FuncInfo.MF, Addr.getOffset()),
3016 MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
3018 if (!emitStore(ArgVT, ArgReg, Addr, MMO))
3025 bool AArch64FastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
3026 unsigned NumBytes) {
3027 CallingConv::ID CC = CLI.CallConv;
3029 // Issue CALLSEQ_END
3030 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
3031 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
3032 .addImm(NumBytes).addImm(0);
3034 // Now the return value.
3035 if (RetVT != MVT::isVoid) {
3036 SmallVector<CCValAssign, 16> RVLocs;
3037 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
3038 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC));
3040 // Only handle a single return value.
3041 if (RVLocs.size() != 1)
3044 // Copy all of the result registers out of their specified physreg.
3045 MVT CopyVT = RVLocs[0].getValVT();
3047 // TODO: Handle big-endian results
3048 if (CopyVT.isVector() && !Subtarget->isLittleEndian())
3051 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
3052 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3053 TII.get(TargetOpcode::COPY), ResultReg)
3054 .addReg(RVLocs[0].getLocReg());
3055 CLI.InRegs.push_back(RVLocs[0].getLocReg());
3057 CLI.ResultReg = ResultReg;
3058 CLI.NumResultRegs = 1;
3064 bool AArch64FastISel::fastLowerCall(CallLoweringInfo &CLI) {
3065 CallingConv::ID CC = CLI.CallConv;
3066 bool IsTailCall = CLI.IsTailCall;
3067 bool IsVarArg = CLI.IsVarArg;
3068 const Value *Callee = CLI.Callee;
3069 MCSymbol *Symbol = CLI.Symbol;
3071 if (!Callee && !Symbol)
3074 // Allow SelectionDAG isel to handle tail calls.
3078 CodeModel::Model CM = TM.getCodeModel();
3079 // Only support the small and large code model.
3080 if (CM != CodeModel::Small && CM != CodeModel::Large)
3083 // FIXME: Add large code model support for ELF.
3084 if (CM == CodeModel::Large && !Subtarget->isTargetMachO())
3087 // Let SDISel handle vararg functions.
3091 // FIXME: Only handle *simple* calls for now.
3093 if (CLI.RetTy->isVoidTy())
3094 RetVT = MVT::isVoid;
3095 else if (!isTypeLegal(CLI.RetTy, RetVT))
3098 for (auto Flag : CLI.OutFlags)
3099 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
3102 // Set up the argument vectors.
3103 SmallVector<MVT, 16> OutVTs;
3104 OutVTs.reserve(CLI.OutVals.size());
3106 for (auto *Val : CLI.OutVals) {
3108 if (!isTypeLegal(Val->getType(), VT) &&
3109 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
3112 // We don't handle vector parameters yet.
3113 if (VT.isVector() || VT.getSizeInBits() > 64)
3116 OutVTs.push_back(VT);
3120 if (Callee && !computeCallAddress(Callee, Addr))
3123 // Handle the arguments now that we've gotten them.
3125 if (!processCallArgs(CLI, OutVTs, NumBytes))
3129 MachineInstrBuilder MIB;
3130 if (CM == CodeModel::Small) {
3131 const MCInstrDesc &II = TII.get(Addr.getReg() ? AArch64::BLR : AArch64::BL);
3132 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II);
3134 MIB.addSym(Symbol, 0);
3135 else if (Addr.getGlobalValue())
3136 MIB.addGlobalAddress(Addr.getGlobalValue(), 0, 0);
3137 else if (Addr.getReg()) {
3138 unsigned Reg = constrainOperandRegClass(II, Addr.getReg(), 0);
3143 unsigned CallReg = 0;
3145 unsigned ADRPReg = createResultReg(&AArch64::GPR64commonRegClass);
3146 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
3148 .addSym(Symbol, AArch64II::MO_GOT | AArch64II::MO_PAGE);
3150 CallReg = createResultReg(&AArch64::GPR64RegClass);
3151 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3152 TII.get(AArch64::LDRXui), CallReg)
3155 AArch64II::MO_GOT | AArch64II::MO_PAGEOFF | AArch64II::MO_NC);
3156 } else if (Addr.getGlobalValue())
3157 CallReg = materializeGV(Addr.getGlobalValue());
3158 else if (Addr.getReg())
3159 CallReg = Addr.getReg();
3164 const MCInstrDesc &II = TII.get(AArch64::BLR);
3165 CallReg = constrainOperandRegClass(II, CallReg, 0);
3166 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(CallReg);
3169 // Add implicit physical register uses to the call.
3170 for (auto Reg : CLI.OutRegs)
3171 MIB.addReg(Reg, RegState::Implicit);
3173 // Add a register mask with the call-preserved registers.
3174 // Proper defs for return values will be added by setPhysRegsDeadExcept().
3175 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
3179 // Finish off the call including any return values.
3180 return finishCall(CLI, RetVT, NumBytes);
3183 bool AArch64FastISel::isMemCpySmall(uint64_t Len, unsigned Alignment) {
3185 return Len / Alignment <= 4;
3190 bool AArch64FastISel::tryEmitSmallMemCpy(Address Dest, Address Src,
3191 uint64_t Len, unsigned Alignment) {
3192 // Make sure we don't bloat code by inlining very large memcpy's.
3193 if (!isMemCpySmall(Len, Alignment))
3196 int64_t UnscaledOffset = 0;
3197 Address OrigDest = Dest;
3198 Address OrigSrc = Src;
3202 if (!Alignment || Alignment >= 8) {
3213 // Bound based on alignment.
3214 if (Len >= 4 && Alignment == 4)
3216 else if (Len >= 2 && Alignment == 2)
3223 unsigned ResultReg = emitLoad(VT, VT, Src);
3227 if (!emitStore(VT, ResultReg, Dest))
3230 int64_t Size = VT.getSizeInBits() / 8;
3232 UnscaledOffset += Size;
3234 // We need to recompute the unscaled offset for each iteration.
3235 Dest.setOffset(OrigDest.getOffset() + UnscaledOffset);
3236 Src.setOffset(OrigSrc.getOffset() + UnscaledOffset);
3242 /// \brief Check if it is possible to fold the condition from the XALU intrinsic
3243 /// into the user. The condition code will only be updated on success.
3244 bool AArch64FastISel::foldXALUIntrinsic(AArch64CC::CondCode &CC,
3245 const Instruction *I,
3246 const Value *Cond) {
3247 if (!isa<ExtractValueInst>(Cond))
3250 const auto *EV = cast<ExtractValueInst>(Cond);
3251 if (!isa<IntrinsicInst>(EV->getAggregateOperand()))
3254 const auto *II = cast<IntrinsicInst>(EV->getAggregateOperand());
3256 const Function *Callee = II->getCalledFunction();
3258 cast<StructType>(Callee->getReturnType())->getTypeAtIndex(0U);
3259 if (!isTypeLegal(RetTy, RetVT))
3262 if (RetVT != MVT::i32 && RetVT != MVT::i64)
3265 const Value *LHS = II->getArgOperand(0);
3266 const Value *RHS = II->getArgOperand(1);
3268 // Canonicalize immediate to the RHS.
3269 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS) &&
3270 isCommutativeIntrinsic(II))
3271 std::swap(LHS, RHS);
3273 // Simplify multiplies.
3274 Intrinsic::ID IID = II->getIntrinsicID();
3278 case Intrinsic::smul_with_overflow:
3279 if (const auto *C = dyn_cast<ConstantInt>(RHS))
3280 if (C->getValue() == 2)
3281 IID = Intrinsic::sadd_with_overflow;
3283 case Intrinsic::umul_with_overflow:
3284 if (const auto *C = dyn_cast<ConstantInt>(RHS))
3285 if (C->getValue() == 2)
3286 IID = Intrinsic::uadd_with_overflow;
3290 AArch64CC::CondCode TmpCC;
3294 case Intrinsic::sadd_with_overflow:
3295 case Intrinsic::ssub_with_overflow:
3296 TmpCC = AArch64CC::VS;
3298 case Intrinsic::uadd_with_overflow:
3299 TmpCC = AArch64CC::HS;
3301 case Intrinsic::usub_with_overflow:
3302 TmpCC = AArch64CC::LO;
3304 case Intrinsic::smul_with_overflow:
3305 case Intrinsic::umul_with_overflow:
3306 TmpCC = AArch64CC::NE;
3310 // Check if both instructions are in the same basic block.
3311 if (!isValueAvailable(II))
3314 // Make sure nothing is in the way
3315 BasicBlock::const_iterator Start(I);
3316 BasicBlock::const_iterator End(II);
3317 for (auto Itr = std::prev(Start); Itr != End; --Itr) {
3318 // We only expect extractvalue instructions between the intrinsic and the
3319 // instruction to be selected.
3320 if (!isa<ExtractValueInst>(Itr))
3323 // Check that the extractvalue operand comes from the intrinsic.
3324 const auto *EVI = cast<ExtractValueInst>(Itr);
3325 if (EVI->getAggregateOperand() != II)
3333 bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
3334 // FIXME: Handle more intrinsics.
3335 switch (II->getIntrinsicID()) {
3336 default: return false;
3337 case Intrinsic::frameaddress: {
3338 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
3339 MFI->setFrameAddressIsTaken(true);
3341 const AArch64RegisterInfo *RegInfo =
3342 static_cast<const AArch64RegisterInfo *>(Subtarget->getRegisterInfo());
3343 unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
3344 unsigned SrcReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
3345 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3346 TII.get(TargetOpcode::COPY), SrcReg).addReg(FramePtr);
3347 // Recursively load frame address
3353 unsigned Depth = cast<ConstantInt>(II->getOperand(0))->getZExtValue();
3355 DestReg = fastEmitInst_ri(AArch64::LDRXui, &AArch64::GPR64RegClass,
3356 SrcReg, /*IsKill=*/true, 0);
3357 assert(DestReg && "Unexpected LDR instruction emission failure.");
3361 updateValueMap(II, SrcReg);
3364 case Intrinsic::memcpy:
3365 case Intrinsic::memmove: {
3366 const auto *MTI = cast<MemTransferInst>(II);
3367 // Don't handle volatile.
3368 if (MTI->isVolatile())
3371 // Disable inlining for memmove before calls to ComputeAddress. Otherwise,
3372 // we would emit dead code because we don't currently handle memmoves.
3373 bool IsMemCpy = (II->getIntrinsicID() == Intrinsic::memcpy);
3374 if (isa<ConstantInt>(MTI->getLength()) && IsMemCpy) {
3375 // Small memcpy's are common enough that we want to do them without a call
3377 uint64_t Len = cast<ConstantInt>(MTI->getLength())->getZExtValue();
3378 unsigned Alignment = MTI->getAlignment();
3379 if (isMemCpySmall(Len, Alignment)) {
3381 if (!computeAddress(MTI->getRawDest(), Dest) ||
3382 !computeAddress(MTI->getRawSource(), Src))
3384 if (tryEmitSmallMemCpy(Dest, Src, Len, Alignment))
3389 if (!MTI->getLength()->getType()->isIntegerTy(64))
3392 if (MTI->getSourceAddressSpace() > 255 || MTI->getDestAddressSpace() > 255)
3393 // Fast instruction selection doesn't support the special
3397 const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
3398 return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 2);
3400 case Intrinsic::memset: {
3401 const MemSetInst *MSI = cast<MemSetInst>(II);
3402 // Don't handle volatile.
3403 if (MSI->isVolatile())
3406 if (!MSI->getLength()->getType()->isIntegerTy(64))
3409 if (MSI->getDestAddressSpace() > 255)
3410 // Fast instruction selection doesn't support the special
3414 return lowerCallTo(II, "memset", II->getNumArgOperands() - 2);
3416 case Intrinsic::sin:
3417 case Intrinsic::cos:
3418 case Intrinsic::pow: {
3420 if (!isTypeLegal(II->getType(), RetVT))
3423 if (RetVT != MVT::f32 && RetVT != MVT::f64)
3426 static const RTLIB::Libcall LibCallTable[3][2] = {
3427 { RTLIB::SIN_F32, RTLIB::SIN_F64 },
3428 { RTLIB::COS_F32, RTLIB::COS_F64 },
3429 { RTLIB::POW_F32, RTLIB::POW_F64 }
3432 bool Is64Bit = RetVT == MVT::f64;
3433 switch (II->getIntrinsicID()) {
3435 llvm_unreachable("Unexpected intrinsic.");
3436 case Intrinsic::sin:
3437 LC = LibCallTable[0][Is64Bit];
3439 case Intrinsic::cos:
3440 LC = LibCallTable[1][Is64Bit];
3442 case Intrinsic::pow:
3443 LC = LibCallTable[2][Is64Bit];
3448 Args.reserve(II->getNumArgOperands());
3450 // Populate the argument list.
3451 for (auto &Arg : II->arg_operands()) {
3454 Entry.Ty = Arg->getType();
3455 Args.push_back(Entry);
3458 CallLoweringInfo CLI;
3459 MCContext &Ctx = MF->getContext();
3460 CLI.setCallee(DL, Ctx, TLI.getLibcallCallingConv(LC), II->getType(),
3461 TLI.getLibcallName(LC), std::move(Args));
3462 if (!lowerCallTo(CLI))
3464 updateValueMap(II, CLI.ResultReg);
3467 case Intrinsic::fabs: {
3469 if (!isTypeLegal(II->getType(), VT))
3473 switch (VT.SimpleTy) {
3477 Opc = AArch64::FABSSr;
3480 Opc = AArch64::FABSDr;
3483 unsigned SrcReg = getRegForValue(II->getOperand(0));
3486 bool SrcRegIsKill = hasTrivialKill(II->getOperand(0));
3487 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
3488 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
3489 .addReg(SrcReg, getKillRegState(SrcRegIsKill));
3490 updateValueMap(II, ResultReg);
3493 case Intrinsic::trap: {
3494 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::BRK))
3498 case Intrinsic::sqrt: {
3499 Type *RetTy = II->getCalledFunction()->getReturnType();
3502 if (!isTypeLegal(RetTy, VT))
3505 unsigned Op0Reg = getRegForValue(II->getOperand(0));
3508 bool Op0IsKill = hasTrivialKill(II->getOperand(0));
3510 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill);
3514 updateValueMap(II, ResultReg);
3517 case Intrinsic::sadd_with_overflow:
3518 case Intrinsic::uadd_with_overflow:
3519 case Intrinsic::ssub_with_overflow:
3520 case Intrinsic::usub_with_overflow:
3521 case Intrinsic::smul_with_overflow:
3522 case Intrinsic::umul_with_overflow: {
3523 // This implements the basic lowering of the xalu with overflow intrinsics.
3524 const Function *Callee = II->getCalledFunction();
3525 auto *Ty = cast<StructType>(Callee->getReturnType());
3526 Type *RetTy = Ty->getTypeAtIndex(0U);
3529 if (!isTypeLegal(RetTy, VT))
3532 if (VT != MVT::i32 && VT != MVT::i64)
3535 const Value *LHS = II->getArgOperand(0);
3536 const Value *RHS = II->getArgOperand(1);
3537 // Canonicalize immediate to the RHS.
3538 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS) &&
3539 isCommutativeIntrinsic(II))
3540 std::swap(LHS, RHS);
3542 // Simplify multiplies.
3543 Intrinsic::ID IID = II->getIntrinsicID();
3547 case Intrinsic::smul_with_overflow:
3548 if (const auto *C = dyn_cast<ConstantInt>(RHS))
3549 if (C->getValue() == 2) {
3550 IID = Intrinsic::sadd_with_overflow;
3554 case Intrinsic::umul_with_overflow:
3555 if (const auto *C = dyn_cast<ConstantInt>(RHS))
3556 if (C->getValue() == 2) {
3557 IID = Intrinsic::uadd_with_overflow;
3563 unsigned ResultReg1 = 0, ResultReg2 = 0, MulReg = 0;
3564 AArch64CC::CondCode CC = AArch64CC::Invalid;
3566 default: llvm_unreachable("Unexpected intrinsic!");
3567 case Intrinsic::sadd_with_overflow:
3568 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true);
3571 case Intrinsic::uadd_with_overflow:
3572 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true);
3575 case Intrinsic::ssub_with_overflow:
3576 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true);
3579 case Intrinsic::usub_with_overflow:
3580 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true);
3583 case Intrinsic::smul_with_overflow: {
3585 unsigned LHSReg = getRegForValue(LHS);
3588 bool LHSIsKill = hasTrivialKill(LHS);
3590 unsigned RHSReg = getRegForValue(RHS);
3593 bool RHSIsKill = hasTrivialKill(RHS);
3595 if (VT == MVT::i32) {
3596 MulReg = emitSMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
3597 unsigned ShiftReg = emitLSR_ri(MVT::i64, MVT::i64, MulReg,
3598 /*IsKill=*/false, 32);
3599 MulReg = fastEmitInst_extractsubreg(VT, MulReg, /*IsKill=*/true,
3601 ShiftReg = fastEmitInst_extractsubreg(VT, ShiftReg, /*IsKill=*/true,
3603 emitSubs_rs(VT, ShiftReg, /*IsKill=*/true, MulReg, /*IsKill=*/false,
3604 AArch64_AM::ASR, 31, /*WantResult=*/false);
3606 assert(VT == MVT::i64 && "Unexpected value type.");
3607 // LHSReg and RHSReg cannot be killed by this Mul, since they are
3608 // reused in the next instruction.
3609 MulReg = emitMul_rr(VT, LHSReg, /*IsKill=*/false, RHSReg,
3611 unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill,
3613 emitSubs_rs(VT, SMULHReg, /*IsKill=*/true, MulReg, /*IsKill=*/false,
3614 AArch64_AM::ASR, 63, /*WantResult=*/false);
3618 case Intrinsic::umul_with_overflow: {
3620 unsigned LHSReg = getRegForValue(LHS);
3623 bool LHSIsKill = hasTrivialKill(LHS);
3625 unsigned RHSReg = getRegForValue(RHS);
3628 bool RHSIsKill = hasTrivialKill(RHS);
3630 if (VT == MVT::i32) {
3631 MulReg = emitUMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
3632 emitSubs_rs(MVT::i64, AArch64::XZR, /*IsKill=*/true, MulReg,
3633 /*IsKill=*/false, AArch64_AM::LSR, 32,
3634 /*WantResult=*/false);
3635 MulReg = fastEmitInst_extractsubreg(VT, MulReg, /*IsKill=*/true,
3638 assert(VT == MVT::i64 && "Unexpected value type.");
3639 // LHSReg and RHSReg cannot be killed by this Mul, since they are
3640 // reused in the next instruction.
3641 MulReg = emitMul_rr(VT, LHSReg, /*IsKill=*/false, RHSReg,
3643 unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill,
3645 emitSubs_rr(VT, AArch64::XZR, /*IsKill=*/true, UMULHReg,
3646 /*IsKill=*/false, /*WantResult=*/false);
3653 ResultReg1 = createResultReg(TLI.getRegClassFor(VT));
3654 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3655 TII.get(TargetOpcode::COPY), ResultReg1).addReg(MulReg);
3658 ResultReg2 = fastEmitInst_rri(AArch64::CSINCWr, &AArch64::GPR32RegClass,
3659 AArch64::WZR, /*IsKill=*/true, AArch64::WZR,
3660 /*IsKill=*/true, getInvertedCondCode(CC));
3662 assert((ResultReg1 + 1) == ResultReg2 &&
3663 "Nonconsecutive result registers.");
3664 updateValueMap(II, ResultReg1, 2);
3671 bool AArch64FastISel::selectRet(const Instruction *I) {
3672 const ReturnInst *Ret = cast<ReturnInst>(I);
3673 const Function &F = *I->getParent()->getParent();
3675 if (!FuncInfo.CanLowerReturn)
3681 // Build a list of return value registers.
3682 SmallVector<unsigned, 4> RetRegs;
3684 if (Ret->getNumOperands() > 0) {
3685 CallingConv::ID CC = F.getCallingConv();
3686 SmallVector<ISD::OutputArg, 4> Outs;
3687 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
3689 // Analyze operands of the call, assigning locations to each operand.
3690 SmallVector<CCValAssign, 16> ValLocs;
3691 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext());
3692 CCAssignFn *RetCC = CC == CallingConv::WebKit_JS ? RetCC_AArch64_WebKit_JS
3693 : RetCC_AArch64_AAPCS;
3694 CCInfo.AnalyzeReturn(Outs, RetCC);
3696 // Only handle a single return value for now.
3697 if (ValLocs.size() != 1)
3700 CCValAssign &VA = ValLocs[0];
3701 const Value *RV = Ret->getOperand(0);
3703 // Don't bother handling odd stuff for now.
3704 if ((VA.getLocInfo() != CCValAssign::Full) &&
3705 (VA.getLocInfo() != CCValAssign::BCvt))
3708 // Only handle register returns for now.
3712 unsigned Reg = getRegForValue(RV);
3716 unsigned SrcReg = Reg + VA.getValNo();
3717 unsigned DestReg = VA.getLocReg();
3718 // Avoid a cross-class copy. This is very unlikely.
3719 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
3722 EVT RVEVT = TLI.getValueType(DL, RV->getType());
3723 if (!RVEVT.isSimple())
3726 // Vectors (of > 1 lane) in big endian need tricky handling.
3727 if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1 &&
3728 !Subtarget->isLittleEndian())
3731 MVT RVVT = RVEVT.getSimpleVT();
3732 if (RVVT == MVT::f128)
3735 MVT DestVT = VA.getValVT();
3736 // Special handling for extended integers.
3737 if (RVVT != DestVT) {
3738 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
3741 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
3744 bool IsZExt = Outs[0].Flags.isZExt();
3745 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
3751 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3752 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
3754 // Add register to return instruction.
3755 RetRegs.push_back(VA.getLocReg());
3758 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3759 TII.get(AArch64::RET_ReallyLR));
3760 for (unsigned RetReg : RetRegs)
3761 MIB.addReg(RetReg, RegState::Implicit);
3765 bool AArch64FastISel::selectTrunc(const Instruction *I) {
3766 Type *DestTy = I->getType();
3767 Value *Op = I->getOperand(0);
3768 Type *SrcTy = Op->getType();
3770 EVT SrcEVT = TLI.getValueType(DL, SrcTy, true);
3771 EVT DestEVT = TLI.getValueType(DL, DestTy, true);
3772 if (!SrcEVT.isSimple())
3774 if (!DestEVT.isSimple())
3777 MVT SrcVT = SrcEVT.getSimpleVT();
3778 MVT DestVT = DestEVT.getSimpleVT();
3780 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16 &&
3783 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&
3787 unsigned SrcReg = getRegForValue(Op);
3790 bool SrcIsKill = hasTrivialKill(Op);
3792 // If we're truncating from i64 to a smaller non-legal type then generate an
3793 // AND. Otherwise, we know the high bits are undefined and a truncate only
3794 // generate a COPY. We cannot mark the source register also as result
3795 // register, because this can incorrectly transfer the kill flag onto the
3798 if (SrcVT == MVT::i64) {
3800 switch (DestVT.SimpleTy) {
3802 // Trunc i64 to i32 is handled by the target-independent fast-isel.
3814 // Issue an extract_subreg to get the lower 32-bits.
3815 unsigned Reg32 = fastEmitInst_extractsubreg(MVT::i32, SrcReg, SrcIsKill,
3817 // Create the AND instruction which performs the actual truncation.
3818 ResultReg = emitAnd_ri(MVT::i32, Reg32, /*IsKill=*/true, Mask);
3819 assert(ResultReg && "Unexpected AND instruction emission failure.");
3821 ResultReg = createResultReg(&AArch64::GPR32RegClass);
3822 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3823 TII.get(TargetOpcode::COPY), ResultReg)
3824 .addReg(SrcReg, getKillRegState(SrcIsKill));
3827 updateValueMap(I, ResultReg);
3831 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) {
3832 assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
3833 DestVT == MVT::i64) &&
3834 "Unexpected value type.");
3835 // Handle i8 and i16 as i32.
3836 if (DestVT == MVT::i8 || DestVT == MVT::i16)
3840 unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1);
3841 assert(ResultReg && "Unexpected AND instruction emission failure.");
3842 if (DestVT == MVT::i64) {
3843 // We're ZExt i1 to i64. The ANDWri Wd, Ws, #1 implicitly clears the
3844 // upper 32 bits. Emit a SUBREG_TO_REG to extend from Wd to Xd.
3845 unsigned Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
3846 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3847 TII.get(AArch64::SUBREG_TO_REG), Reg64)
3850 .addImm(AArch64::sub_32);
3855 if (DestVT == MVT::i64) {
3856 // FIXME: We're SExt i1 to i64.
3859 return fastEmitInst_rii(AArch64::SBFMWri, &AArch64::GPR32RegClass, SrcReg,
3860 /*TODO:IsKill=*/false, 0, 0);
3864 unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
3865 unsigned Op1, bool Op1IsKill) {
3867 switch (RetVT.SimpleTy) {
3873 Opc = AArch64::MADDWrrr; ZReg = AArch64::WZR; break;
3875 Opc = AArch64::MADDXrrr; ZReg = AArch64::XZR; break;
3878 const TargetRegisterClass *RC =
3879 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3880 return fastEmitInst_rrr(Opc, RC, Op0, Op0IsKill, Op1, Op1IsKill,
3881 /*IsKill=*/ZReg, true);
3884 unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
3885 unsigned Op1, bool Op1IsKill) {
3886 if (RetVT != MVT::i64)
3889 return fastEmitInst_rrr(AArch64::SMADDLrrr, &AArch64::GPR64RegClass,
3890 Op0, Op0IsKill, Op1, Op1IsKill,
3891 AArch64::XZR, /*IsKill=*/true);
3894 unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
3895 unsigned Op1, bool Op1IsKill) {
3896 if (RetVT != MVT::i64)
3899 return fastEmitInst_rrr(AArch64::UMADDLrrr, &AArch64::GPR64RegClass,
3900 Op0, Op0IsKill, Op1, Op1IsKill,
3901 AArch64::XZR, /*IsKill=*/true);
3904 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
3905 unsigned Op1Reg, bool Op1IsKill) {
3907 bool NeedTrunc = false;
3909 switch (RetVT.SimpleTy) {
3911 case MVT::i8: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xff; break;
3912 case MVT::i16: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xffff; break;
3913 case MVT::i32: Opc = AArch64::LSLVWr; break;
3914 case MVT::i64: Opc = AArch64::LSLVXr; break;
3917 const TargetRegisterClass *RC =
3918 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3920 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
3923 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
3926 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
3930 unsigned AArch64FastISel::emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
3931 bool Op0IsKill, uint64_t Shift,
3933 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
3934 "Unexpected source/return type pair.");
3935 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
3936 SrcVT == MVT::i32 || SrcVT == MVT::i64) &&
3937 "Unexpected source value type.");
3938 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
3939 RetVT == MVT::i64) && "Unexpected return value type.");
3941 bool Is64Bit = (RetVT == MVT::i64);
3942 unsigned RegSize = Is64Bit ? 64 : 32;
3943 unsigned DstBits = RetVT.getSizeInBits();
3944 unsigned SrcBits = SrcVT.getSizeInBits();
3945 const TargetRegisterClass *RC =
3946 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
3948 // Just emit a copy for "zero" shifts.
3950 if (RetVT == SrcVT) {
3951 unsigned ResultReg = createResultReg(RC);
3952 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3953 TII.get(TargetOpcode::COPY), ResultReg)
3954 .addReg(Op0, getKillRegState(Op0IsKill));
3957 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
3960 // Don't deal with undefined shifts.
3961 if (Shift >= DstBits)
3964 // For immediate shifts we can fold the zero-/sign-extension into the shift.
3965 // {S|U}BFM Wd, Wn, #r, #s
3966 // Wd<32+s-r,32-r> = Wn<s:0> when r > s
3968 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3969 // %2 = shl i16 %1, 4
3970 // Wd<32+7-28,32-28> = Wn<7:0> <- clamp s to 7
3971 // 0b1111_1111_1111_1111__1111_1010_1010_0000 sext
3972 // 0b0000_0000_0000_0000__0000_0101_0101_0000 sext | zext
3973 // 0b0000_0000_0000_0000__0000_1010_1010_0000 zext
3975 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3976 // %2 = shl i16 %1, 8
3977 // Wd<32+7-24,32-24> = Wn<7:0>
3978 // 0b1111_1111_1111_1111__1010_1010_0000_0000 sext
3979 // 0b0000_0000_0000_0000__0101_0101_0000_0000 sext | zext
3980 // 0b0000_0000_0000_0000__1010_1010_0000_0000 zext
3982 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
3983 // %2 = shl i16 %1, 12
3984 // Wd<32+3-20,32-20> = Wn<3:0>
3985 // 0b1111_1111_1111_1111__1010_0000_0000_0000 sext
3986 // 0b0000_0000_0000_0000__0101_0000_0000_0000 sext | zext
3987 // 0b0000_0000_0000_0000__1010_0000_0000_0000 zext
3989 unsigned ImmR = RegSize - Shift;
3990 // Limit the width to the length of the source type.
3991 unsigned ImmS = std::min<unsigned>(SrcBits - 1, DstBits - 1 - Shift);
3992 static const unsigned OpcTable[2][2] = {
3993 {AArch64::SBFMWri, AArch64::SBFMXri},
3994 {AArch64::UBFMWri, AArch64::UBFMXri}
3996 unsigned Opc = OpcTable[IsZExt][Is64Bit];
3997 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
3998 unsigned TmpReg = MRI.createVirtualRegister(RC);
3999 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
4000 TII.get(AArch64::SUBREG_TO_REG), TmpReg)
4002 .addReg(Op0, getKillRegState(Op0IsKill))
4003 .addImm(AArch64::sub_32);
4007 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
4010 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
4011 unsigned Op1Reg, bool Op1IsKill) {
4013 bool NeedTrunc = false;
4015 switch (RetVT.SimpleTy) {
4017 case MVT::i8: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xff; break;
4018 case MVT::i16: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xffff; break;
4019 case MVT::i32: Opc = AArch64::LSRVWr; break;
4020 case MVT::i64: Opc = AArch64::LSRVXr; break;
4023 const TargetRegisterClass *RC =
4024 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4026 Op0Reg = emitAnd_ri(MVT::i32, Op0Reg, Op0IsKill, Mask);
4027 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
4028 Op0IsKill = Op1IsKill = true;
4030 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
4033 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
4037 unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
4038 bool Op0IsKill, uint64_t Shift,
4040 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
4041 "Unexpected source/return type pair.");
4042 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
4043 SrcVT == MVT::i32 || SrcVT == MVT::i64) &&
4044 "Unexpected source value type.");
4045 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4046 RetVT == MVT::i64) && "Unexpected return value type.");
4048 bool Is64Bit = (RetVT == MVT::i64);
4049 unsigned RegSize = Is64Bit ? 64 : 32;
4050 unsigned DstBits = RetVT.getSizeInBits();
4051 unsigned SrcBits = SrcVT.getSizeInBits();
4052 const TargetRegisterClass *RC =
4053 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4055 // Just emit a copy for "zero" shifts.
4057 if (RetVT == SrcVT) {
4058 unsigned ResultReg = createResultReg(RC);
4059 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
4060 TII.get(TargetOpcode::COPY), ResultReg)
4061 .addReg(Op0, getKillRegState(Op0IsKill));
4064 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4067 // Don't deal with undefined shifts.
4068 if (Shift >= DstBits)
4071 // For immediate shifts we can fold the zero-/sign-extension into the shift.
4072 // {S|U}BFM Wd, Wn, #r, #s
4073 // Wd<s-r:0> = Wn<s:r> when r <= s
4075 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
4076 // %2 = lshr i16 %1, 4
4077 // Wd<7-4:0> = Wn<7:4>
4078 // 0b0000_0000_0000_0000__0000_1111_1111_1010 sext
4079 // 0b0000_0000_0000_0000__0000_0000_0000_0101 sext | zext
4080 // 0b0000_0000_0000_0000__0000_0000_0000_1010 zext
4082 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
4083 // %2 = lshr i16 %1, 8
4084 // Wd<7-7,0> = Wn<7:7>
4085 // 0b0000_0000_0000_0000__0000_0000_1111_1111 sext
4086 // 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
4087 // 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
4089 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
4090 // %2 = lshr i16 %1, 12
4091 // Wd<7-7,0> = Wn<7:7> <- clamp r to 7
4092 // 0b0000_0000_0000_0000__0000_0000_0000_1111 sext
4093 // 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
4094 // 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
4096 if (Shift >= SrcBits && IsZExt)
4097 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT);
4099 // It is not possible to fold a sign-extend into the LShr instruction. In this
4100 // case emit a sign-extend.
4102 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4107 SrcBits = SrcVT.getSizeInBits();
4111 unsigned ImmR = std::min<unsigned>(SrcBits - 1, Shift);
4112 unsigned ImmS = SrcBits - 1;
4113 static const unsigned OpcTable[2][2] = {
4114 {AArch64::SBFMWri, AArch64::SBFMXri},
4115 {AArch64::UBFMWri, AArch64::UBFMXri}
4117 unsigned Opc = OpcTable[IsZExt][Is64Bit];
4118 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4119 unsigned TmpReg = MRI.createVirtualRegister(RC);
4120 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
4121 TII.get(AArch64::SUBREG_TO_REG), TmpReg)
4123 .addReg(Op0, getKillRegState(Op0IsKill))
4124 .addImm(AArch64::sub_32);
4128 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
4131 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
4132 unsigned Op1Reg, bool Op1IsKill) {
4134 bool NeedTrunc = false;
4136 switch (RetVT.SimpleTy) {
4138 case MVT::i8: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xff; break;
4139 case MVT::i16: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xffff; break;
4140 case MVT::i32: Opc = AArch64::ASRVWr; break;
4141 case MVT::i64: Opc = AArch64::ASRVXr; break;
4144 const TargetRegisterClass *RC =
4145 (RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4147 Op0Reg = emitIntExt(RetVT, Op0Reg, MVT::i32, /*IsZExt=*/false);
4148 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
4149 Op0IsKill = Op1IsKill = true;
4151 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,
4154 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
4158 unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
4159 bool Op0IsKill, uint64_t Shift,
4161 assert(RetVT.SimpleTy >= SrcVT.SimpleTy &&
4162 "Unexpected source/return type pair.");
4163 assert((SrcVT == MVT::i1 || SrcVT == MVT::i8 || SrcVT == MVT::i16 ||
4164 SrcVT == MVT::i32 || SrcVT == MVT::i64) &&
4165 "Unexpected source value type.");
4166 assert((RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32 ||
4167 RetVT == MVT::i64) && "Unexpected return value type.");
4169 bool Is64Bit = (RetVT == MVT::i64);
4170 unsigned RegSize = Is64Bit ? 64 : 32;
4171 unsigned DstBits = RetVT.getSizeInBits();
4172 unsigned SrcBits = SrcVT.getSizeInBits();
4173 const TargetRegisterClass *RC =
4174 Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4176 // Just emit a copy for "zero" shifts.
4178 if (RetVT == SrcVT) {
4179 unsigned ResultReg = createResultReg(RC);
4180 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
4181 TII.get(TargetOpcode::COPY), ResultReg)
4182 .addReg(Op0, getKillRegState(Op0IsKill));
4185 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4188 // Don't deal with undefined shifts.
4189 if (Shift >= DstBits)
4192 // For immediate shifts we can fold the zero-/sign-extension into the shift.
4193 // {S|U}BFM Wd, Wn, #r, #s
4194 // Wd<s-r:0> = Wn<s:r> when r <= s
4196 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
4197 // %2 = ashr i16 %1, 4
4198 // Wd<7-4:0> = Wn<7:4>
4199 // 0b1111_1111_1111_1111__1111_1111_1111_1010 sext
4200 // 0b0000_0000_0000_0000__0000_0000_0000_0101 sext | zext
4201 // 0b0000_0000_0000_0000__0000_0000_0000_1010 zext
4203 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
4204 // %2 = ashr i16 %1, 8
4205 // Wd<7-7,0> = Wn<7:7>
4206 // 0b1111_1111_1111_1111__1111_1111_1111_1111 sext
4207 // 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
4208 // 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
4210 // %1 = {s|z}ext i8 {0b1010_1010|0b0101_0101} to i16
4211 // %2 = ashr i16 %1, 12
4212 // Wd<7-7,0> = Wn<7:7> <- clamp r to 7
4213 // 0b1111_1111_1111_1111__1111_1111_1111_1111 sext
4214 // 0b0000_0000_0000_0000__0000_0000_0000_0000 sext
4215 // 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
4217 if (Shift >= SrcBits && IsZExt)
4218 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT);
4220 unsigned ImmR = std::min<unsigned>(SrcBits - 1, Shift);
4221 unsigned ImmS = SrcBits - 1;
4222 static const unsigned OpcTable[2][2] = {
4223 {AArch64::SBFMWri, AArch64::SBFMXri},
4224 {AArch64::UBFMWri, AArch64::UBFMXri}
4226 unsigned Opc = OpcTable[IsZExt][Is64Bit];
4227 if (SrcVT.SimpleTy <= MVT::i32 && RetVT == MVT::i64) {
4228 unsigned TmpReg = MRI.createVirtualRegister(RC);
4229 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
4230 TII.get(AArch64::SUBREG_TO_REG), TmpReg)
4232 .addReg(Op0, getKillRegState(Op0IsKill))
4233 .addImm(AArch64::sub_32);
4237 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
4240 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
4242 assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");
4244 // FastISel does not have plumbing to deal with extensions where the SrcVT or
4245 // DestVT are odd things, so test to make sure that they are both types we can
4246 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
4247 // bail out to SelectionDAG.
4248 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) &&
4249 (DestVT != MVT::i32) && (DestVT != MVT::i64)) ||
4250 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) &&
4251 (SrcVT != MVT::i16) && (SrcVT != MVT::i32)))
4257 switch (SrcVT.SimpleTy) {
4261 return emiti1Ext(SrcReg, DestVT, IsZExt);
4263 if (DestVT == MVT::i64)
4264 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
4266 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
4270 if (DestVT == MVT::i64)
4271 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
4273 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
4277 assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");
4278 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
4283 // Handle i8 and i16 as i32.
4284 if (DestVT == MVT::i8 || DestVT == MVT::i16)
4286 else if (DestVT == MVT::i64) {
4287 unsigned Src64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
4288 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
4289 TII.get(AArch64::SUBREG_TO_REG), Src64)
4292 .addImm(AArch64::sub_32);
4296 const TargetRegisterClass *RC =
4297 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4298 return fastEmitInst_rii(Opc, RC, SrcReg, /*TODO:IsKill=*/false, 0, Imm);
4301 static bool isZExtLoad(const MachineInstr *LI) {
4302 switch (LI->getOpcode()) {
4305 case AArch64::LDURBBi:
4306 case AArch64::LDURHHi:
4307 case AArch64::LDURWi:
4308 case AArch64::LDRBBui:
4309 case AArch64::LDRHHui:
4310 case AArch64::LDRWui:
4311 case AArch64::LDRBBroX:
4312 case AArch64::LDRHHroX:
4313 case AArch64::LDRWroX:
4314 case AArch64::LDRBBroW:
4315 case AArch64::LDRHHroW:
4316 case AArch64::LDRWroW:
4321 static bool isSExtLoad(const MachineInstr *LI) {
4322 switch (LI->getOpcode()) {
4325 case AArch64::LDURSBWi:
4326 case AArch64::LDURSHWi:
4327 case AArch64::LDURSBXi:
4328 case AArch64::LDURSHXi:
4329 case AArch64::LDURSWi:
4330 case AArch64::LDRSBWui:
4331 case AArch64::LDRSHWui:
4332 case AArch64::LDRSBXui:
4333 case AArch64::LDRSHXui:
4334 case AArch64::LDRSWui:
4335 case AArch64::LDRSBWroX:
4336 case AArch64::LDRSHWroX:
4337 case AArch64::LDRSBXroX:
4338 case AArch64::LDRSHXroX:
4339 case AArch64::LDRSWroX:
4340 case AArch64::LDRSBWroW:
4341 case AArch64::LDRSHWroW:
4342 case AArch64::LDRSBXroW:
4343 case AArch64::LDRSHXroW:
4344 case AArch64::LDRSWroW:
4349 bool AArch64FastISel::optimizeIntExtLoad(const Instruction *I, MVT RetVT,
4351 const auto *LI = dyn_cast<LoadInst>(I->getOperand(0));
4352 if (!LI || !LI->hasOneUse())
4355 // Check if the load instruction has already been selected.
4356 unsigned Reg = lookUpRegForValue(LI);
4360 MachineInstr *MI = MRI.getUniqueVRegDef(Reg);
4364 // Check if the correct load instruction has been emitted - SelectionDAG might
4365 // have emitted a zero-extending load, but we need a sign-extending load.
4366 bool IsZExt = isa<ZExtInst>(I);
4367 const auto *LoadMI = MI;
4368 if (LoadMI->getOpcode() == TargetOpcode::COPY &&
4369 LoadMI->getOperand(1).getSubReg() == AArch64::sub_32) {
4370 unsigned LoadReg = MI->getOperand(1).getReg();
4371 LoadMI = MRI.getUniqueVRegDef(LoadReg);
4372 assert(LoadMI && "Expected valid instruction");
4374 if (!(IsZExt && isZExtLoad(LoadMI)) && !(!IsZExt && isSExtLoad(LoadMI)))
4377 // Nothing to be done.
4378 if (RetVT != MVT::i64 || SrcVT > MVT::i32) {
4379 updateValueMap(I, Reg);
4384 unsigned Reg64 = createResultReg(&AArch64::GPR64RegClass);
4385 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
4386 TII.get(AArch64::SUBREG_TO_REG), Reg64)
4388 .addReg(Reg, getKillRegState(true))
4389 .addImm(AArch64::sub_32);
4392 assert((MI->getOpcode() == TargetOpcode::COPY &&
4393 MI->getOperand(1).getSubReg() == AArch64::sub_32) &&
4394 "Expected copy instruction");
4395 Reg = MI->getOperand(1).getReg();
4396 MI->eraseFromParent();
4398 updateValueMap(I, Reg);
4402 bool AArch64FastISel::selectIntExt(const Instruction *I) {
4403 assert((isa<ZExtInst>(I) || isa<SExtInst>(I)) &&
4404 "Unexpected integer extend instruction.");
4407 if (!isTypeSupported(I->getType(), RetVT))
4410 if (!isTypeSupported(I->getOperand(0)->getType(), SrcVT))
4413 // Try to optimize already sign-/zero-extended values from load instructions.
4414 if (optimizeIntExtLoad(I, RetVT, SrcVT))
4417 unsigned SrcReg = getRegForValue(I->getOperand(0));
4420 bool SrcIsKill = hasTrivialKill(I->getOperand(0));
4422 // Try to optimize already sign-/zero-extended values from function arguments.
4423 bool IsZExt = isa<ZExtInst>(I);
4424 if (const auto *Arg = dyn_cast<Argument>(I->getOperand(0))) {
4425 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) {
4426 if (RetVT == MVT::i64 && SrcVT != MVT::i64) {
4427 unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);
4428 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
4429 TII.get(AArch64::SUBREG_TO_REG), ResultReg)
4431 .addReg(SrcReg, getKillRegState(SrcIsKill))
4432 .addImm(AArch64::sub_32);
4435 // Conservatively clear all kill flags from all uses, because we are
4436 // replacing a sign-/zero-extend instruction at IR level with a nop at MI
4437 // level. The result of the instruction at IR level might have been
4438 // trivially dead, which is now not longer true.
4439 unsigned UseReg = lookUpRegForValue(I);
4441 MRI.clearKillFlags(UseReg);
4443 updateValueMap(I, SrcReg);
4448 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);
4452 updateValueMap(I, ResultReg);
4456 bool AArch64FastISel::selectRem(const Instruction *I, unsigned ISDOpcode) {
4457 EVT DestEVT = TLI.getValueType(DL, I->getType(), true);
4458 if (!DestEVT.isSimple())
4461 MVT DestVT = DestEVT.getSimpleVT();
4462 if (DestVT != MVT::i64 && DestVT != MVT::i32)
4466 bool Is64bit = (DestVT == MVT::i64);
4467 switch (ISDOpcode) {
4471 DivOpc = Is64bit ? AArch64::SDIVXr : AArch64::SDIVWr;
4474 DivOpc = Is64bit ? AArch64::UDIVXr : AArch64::UDIVWr;
4477 unsigned MSubOpc = Is64bit ? AArch64::MSUBXrrr : AArch64::MSUBWrrr;
4478 unsigned Src0Reg = getRegForValue(I->getOperand(0));
4481 bool Src0IsKill = hasTrivialKill(I->getOperand(0));
4483 unsigned Src1Reg = getRegForValue(I->getOperand(1));
4486 bool Src1IsKill = hasTrivialKill(I->getOperand(1));
4488 const TargetRegisterClass *RC =
4489 (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
4490 unsigned QuotReg = fastEmitInst_rr(DivOpc, RC, Src0Reg, /*IsKill=*/false,
4491 Src1Reg, /*IsKill=*/false);
4492 assert(QuotReg && "Unexpected DIV instruction emission failure.");
4493 // The remainder is computed as numerator - (quotient * denominator) using the
4494 // MSUB instruction.
4495 unsigned ResultReg = fastEmitInst_rrr(MSubOpc, RC, QuotReg, /*IsKill=*/true,
4496 Src1Reg, Src1IsKill, Src0Reg,
4498 updateValueMap(I, ResultReg);
4502 bool AArch64FastISel::selectMul(const Instruction *I) {
4504 if (!isTypeSupported(I->getType(), VT, /*IsVectorAllowed=*/true))
4508 return selectBinaryOp(I, ISD::MUL);
4510 const Value *Src0 = I->getOperand(0);
4511 const Value *Src1 = I->getOperand(1);
4512 if (const auto *C = dyn_cast<ConstantInt>(Src0))
4513 if (C->getValue().isPowerOf2())
4514 std::swap(Src0, Src1);
4516 // Try to simplify to a shift instruction.
4517 if (const auto *C = dyn_cast<ConstantInt>(Src1))
4518 if (C->getValue().isPowerOf2()) {
4519 uint64_t ShiftVal = C->getValue().logBase2();
4522 if (const auto *ZExt = dyn_cast<ZExtInst>(Src0)) {
4523 if (!isIntExtFree(ZExt)) {
4525 if (isValueAvailable(ZExt) && isTypeSupported(ZExt->getSrcTy(), VT)) {
4528 Src0 = ZExt->getOperand(0);
4531 } else if (const auto *SExt = dyn_cast<SExtInst>(Src0)) {
4532 if (!isIntExtFree(SExt)) {
4534 if (isValueAvailable(SExt) && isTypeSupported(SExt->getSrcTy(), VT)) {
4537 Src0 = SExt->getOperand(0);
4542 unsigned Src0Reg = getRegForValue(Src0);
4545 bool Src0IsKill = hasTrivialKill(Src0);
4547 unsigned ResultReg =
4548 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt);
4551 updateValueMap(I, ResultReg);
4556 unsigned Src0Reg = getRegForValue(I->getOperand(0));
4559 bool Src0IsKill = hasTrivialKill(I->getOperand(0));
4561 unsigned Src1Reg = getRegForValue(I->getOperand(1));
4564 bool Src1IsKill = hasTrivialKill(I->getOperand(1));
4566 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill);
4571 updateValueMap(I, ResultReg);
4575 bool AArch64FastISel::selectShift(const Instruction *I) {
4577 if (!isTypeSupported(I->getType(), RetVT, /*IsVectorAllowed=*/true))
4580 if (RetVT.isVector())
4581 return selectOperator(I, I->getOpcode());
4583 if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
4584 unsigned ResultReg = 0;
4585 uint64_t ShiftVal = C->getZExtValue();
4587 bool IsZExt = I->getOpcode() != Instruction::AShr;
4588 const Value *Op0 = I->getOperand(0);
4589 if (const auto *ZExt = dyn_cast<ZExtInst>(Op0)) {
4590 if (!isIntExtFree(ZExt)) {
4592 if (isValueAvailable(ZExt) && isTypeSupported(ZExt->getSrcTy(), TmpVT)) {
4595 Op0 = ZExt->getOperand(0);
4598 } else if (const auto *SExt = dyn_cast<SExtInst>(Op0)) {
4599 if (!isIntExtFree(SExt)) {
4601 if (isValueAvailable(SExt) && isTypeSupported(SExt->getSrcTy(), TmpVT)) {
4604 Op0 = SExt->getOperand(0);
4609 unsigned Op0Reg = getRegForValue(Op0);
4612 bool Op0IsKill = hasTrivialKill(Op0);
4614 switch (I->getOpcode()) {
4615 default: llvm_unreachable("Unexpected instruction.");
4616 case Instruction::Shl:
4617 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4619 case Instruction::AShr:
4620 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4622 case Instruction::LShr:
4623 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4629 updateValueMap(I, ResultReg);
4633 unsigned Op0Reg = getRegForValue(I->getOperand(0));
4636 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
4638 unsigned Op1Reg = getRegForValue(I->getOperand(1));
4641 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
4643 unsigned ResultReg = 0;
4644 switch (I->getOpcode()) {
4645 default: llvm_unreachable("Unexpected instruction.");
4646 case Instruction::Shl:
4647 ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4649 case Instruction::AShr:
4650 ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4652 case Instruction::LShr:
4653 ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);
4660 updateValueMap(I, ResultReg);
4664 bool AArch64FastISel::selectBitCast(const Instruction *I) {
4667 if (!isTypeLegal(I->getOperand(0)->getType(), SrcVT))
4669 if (!isTypeLegal(I->getType(), RetVT))
4673 if (RetVT == MVT::f32 && SrcVT == MVT::i32)
4674 Opc = AArch64::FMOVWSr;
4675 else if (RetVT == MVT::f64 && SrcVT == MVT::i64)
4676 Opc = AArch64::FMOVXDr;
4677 else if (RetVT == MVT::i32 && SrcVT == MVT::f32)
4678 Opc = AArch64::FMOVSWr;
4679 else if (RetVT == MVT::i64 && SrcVT == MVT::f64)
4680 Opc = AArch64::FMOVDXr;
4684 const TargetRegisterClass *RC = nullptr;
4685 switch (RetVT.SimpleTy) {
4686 default: llvm_unreachable("Unexpected value type.");
4687 case MVT::i32: RC = &AArch64::GPR32RegClass; break;
4688 case MVT::i64: RC = &AArch64::GPR64RegClass; break;
4689 case MVT::f32: RC = &AArch64::FPR32RegClass; break;
4690 case MVT::f64: RC = &AArch64::FPR64RegClass; break;
4692 unsigned Op0Reg = getRegForValue(I->getOperand(0));
4695 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
4696 unsigned ResultReg = fastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill);
4701 updateValueMap(I, ResultReg);
4705 bool AArch64FastISel::selectFRem(const Instruction *I) {
4707 if (!isTypeLegal(I->getType(), RetVT))
4711 switch (RetVT.SimpleTy) {
4715 LC = RTLIB::REM_F32;
4718 LC = RTLIB::REM_F64;
4723 Args.reserve(I->getNumOperands());
4725 // Populate the argument list.
4726 for (auto &Arg : I->operands()) {
4729 Entry.Ty = Arg->getType();
4730 Args.push_back(Entry);
4733 CallLoweringInfo CLI;
4734 MCContext &Ctx = MF->getContext();
4735 CLI.setCallee(DL, Ctx, TLI.getLibcallCallingConv(LC), I->getType(),
4736 TLI.getLibcallName(LC), std::move(Args));
4737 if (!lowerCallTo(CLI))
4739 updateValueMap(I, CLI.ResultReg);
4743 bool AArch64FastISel::selectSDiv(const Instruction *I) {
4745 if (!isTypeLegal(I->getType(), VT))
4748 if (!isa<ConstantInt>(I->getOperand(1)))
4749 return selectBinaryOp(I, ISD::SDIV);
4751 const APInt &C = cast<ConstantInt>(I->getOperand(1))->getValue();
4752 if ((VT != MVT::i32 && VT != MVT::i64) || !C ||
4753 !(C.isPowerOf2() || (-C).isPowerOf2()))
4754 return selectBinaryOp(I, ISD::SDIV);
4756 unsigned Lg2 = C.countTrailingZeros();
4757 unsigned Src0Reg = getRegForValue(I->getOperand(0));
4760 bool Src0IsKill = hasTrivialKill(I->getOperand(0));
4762 if (cast<BinaryOperator>(I)->isExact()) {
4763 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2);
4766 updateValueMap(I, ResultReg);
4770 int64_t Pow2MinusOne = (1ULL << Lg2) - 1;
4771 unsigned AddReg = emitAdd_ri_(VT, Src0Reg, /*IsKill=*/false, Pow2MinusOne);
4775 // (Src0 < 0) ? Pow2 - 1 : 0;
4776 if (!emitICmp_ri(VT, Src0Reg, /*IsKill=*/false, 0))
4780 const TargetRegisterClass *RC;
4781 if (VT == MVT::i64) {
4782 SelectOpc = AArch64::CSELXr;
4783 RC = &AArch64::GPR64RegClass;
4785 SelectOpc = AArch64::CSELWr;
4786 RC = &AArch64::GPR32RegClass;
4788 unsigned SelectReg =
4789 fastEmitInst_rri(SelectOpc, RC, AddReg, /*IsKill=*/true, Src0Reg,
4790 Src0IsKill, AArch64CC::LT);
4794 // Divide by Pow2 --> ashr. If we're dividing by a negative value we must also
4795 // negate the result.
4796 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
4799 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, /*IsKill=*/true,
4800 SelectReg, /*IsKill=*/true, AArch64_AM::ASR, Lg2);
4802 ResultReg = emitASR_ri(VT, VT, SelectReg, /*IsKill=*/true, Lg2);
4807 updateValueMap(I, ResultReg);
4811 /// This is mostly a copy of the existing FastISel getRegForGEPIndex code. We
4812 /// have to duplicate it for AArch64, because otherwise we would fail during the
4813 /// sign-extend emission.
4814 std::pair<unsigned, bool> AArch64FastISel::getRegForGEPIndex(const Value *Idx) {
4815 unsigned IdxN = getRegForValue(Idx);
4817 // Unhandled operand. Halt "fast" selection and bail.
4818 return std::pair<unsigned, bool>(0, false);
4820 bool IdxNIsKill = hasTrivialKill(Idx);
4822 // If the index is smaller or larger than intptr_t, truncate or extend it.
4823 MVT PtrVT = TLI.getPointerTy(DL);
4824 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
4825 if (IdxVT.bitsLT(PtrVT)) {
4826 IdxN = emitIntExt(IdxVT.getSimpleVT(), IdxN, PtrVT, /*IsZExt=*/false);
4828 } else if (IdxVT.bitsGT(PtrVT))
4829 llvm_unreachable("AArch64 FastISel doesn't support types larger than i64");
4830 return std::pair<unsigned, bool>(IdxN, IdxNIsKill);
4833 /// This is mostly a copy of the existing FastISel GEP code, but we have to
4834 /// duplicate it for AArch64, because otherwise we would bail out even for
4835 /// simple cases. This is because the standard fastEmit functions don't cover
4836 /// MUL at all and ADD is lowered very inefficientily.
4837 bool AArch64FastISel::selectGetElementPtr(const Instruction *I) {
4838 unsigned N = getRegForValue(I->getOperand(0));
4841 bool NIsKill = hasTrivialKill(I->getOperand(0));
4843 // Keep a running tab of the total offset to coalesce multiple N = N + Offset
4844 // into a single N = N + TotalOffset.
4845 uint64_t TotalOffs = 0;
4846 Type *Ty = I->getOperand(0)->getType();
4847 MVT VT = TLI.getPointerTy(DL);
4848 for (auto OI = std::next(I->op_begin()), E = I->op_end(); OI != E; ++OI) {
4849 const Value *Idx = *OI;
4850 if (auto *StTy = dyn_cast<StructType>(Ty)) {
4851 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
4854 TotalOffs += DL.getStructLayout(StTy)->getElementOffset(Field);
4855 Ty = StTy->getElementType(Field);
4857 Ty = cast<SequentialType>(Ty)->getElementType();
4858 // If this is a constant subscript, handle it quickly.
4859 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
4864 DL.getTypeAllocSize(Ty) * cast<ConstantInt>(CI)->getSExtValue();
4868 N = emitAdd_ri_(VT, N, NIsKill, TotalOffs);
4875 // N = N + Idx * ElementSize;
4876 uint64_t ElementSize = DL.getTypeAllocSize(Ty);
4877 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx);
4878 unsigned IdxN = Pair.first;
4879 bool IdxNIsKill = Pair.second;
4883 if (ElementSize != 1) {
4884 unsigned C = fastEmit_i(VT, VT, ISD::Constant, ElementSize);
4887 IdxN = emitMul_rr(VT, IdxN, IdxNIsKill, C, true);
4892 N = fastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill);
4898 N = emitAdd_ri_(VT, N, NIsKill, TotalOffs);
4902 updateValueMap(I, N);
4906 bool AArch64FastISel::fastSelectInstruction(const Instruction *I) {
4907 switch (I->getOpcode()) {
4910 case Instruction::Add:
4911 case Instruction::Sub:
4912 return selectAddSub(I);
4913 case Instruction::Mul:
4914 return selectMul(I);
4915 case Instruction::SDiv:
4916 return selectSDiv(I);
4917 case Instruction::SRem:
4918 if (!selectBinaryOp(I, ISD::SREM))
4919 return selectRem(I, ISD::SREM);
4921 case Instruction::URem:
4922 if (!selectBinaryOp(I, ISD::UREM))
4923 return selectRem(I, ISD::UREM);
4925 case Instruction::Shl:
4926 case Instruction::LShr:
4927 case Instruction::AShr:
4928 return selectShift(I);
4929 case Instruction::And:
4930 case Instruction::Or:
4931 case Instruction::Xor:
4932 return selectLogicalOp(I);
4933 case Instruction::Br:
4934 return selectBranch(I);
4935 case Instruction::IndirectBr:
4936 return selectIndirectBr(I);
4937 case Instruction::BitCast:
4938 if (!FastISel::selectBitCast(I))
4939 return selectBitCast(I);
4941 case Instruction::FPToSI:
4942 if (!selectCast(I, ISD::FP_TO_SINT))
4943 return selectFPToInt(I, /*Signed=*/true);
4945 case Instruction::FPToUI:
4946 return selectFPToInt(I, /*Signed=*/false);
4947 case Instruction::ZExt:
4948 case Instruction::SExt:
4949 return selectIntExt(I);
4950 case Instruction::Trunc:
4951 if (!selectCast(I, ISD::TRUNCATE))
4952 return selectTrunc(I);
4954 case Instruction::FPExt:
4955 return selectFPExt(I);
4956 case Instruction::FPTrunc:
4957 return selectFPTrunc(I);
4958 case Instruction::SIToFP:
4959 if (!selectCast(I, ISD::SINT_TO_FP))
4960 return selectIntToFP(I, /*Signed=*/true);
4962 case Instruction::UIToFP:
4963 return selectIntToFP(I, /*Signed=*/false);
4964 case Instruction::Load:
4965 return selectLoad(I);
4966 case Instruction::Store:
4967 return selectStore(I);
4968 case Instruction::FCmp:
4969 case Instruction::ICmp:
4970 return selectCmp(I);
4971 case Instruction::Select:
4972 return selectSelect(I);
4973 case Instruction::Ret:
4974 return selectRet(I);
4975 case Instruction::FRem:
4976 return selectFRem(I);
4977 case Instruction::GetElementPtr:
4978 return selectGetElementPtr(I);
4981 // fall-back to target-independent instruction selection.
4982 return selectOperator(I, I->getOpcode());
4983 // Silence warnings.
4984 (void)&CC_AArch64_DarwinPCS_VarArg;
4988 llvm::FastISel *AArch64::createFastISel(FunctionLoweringInfo &FuncInfo,
4989 const TargetLibraryInfo *LibInfo) {
4990 return new AArch64FastISel(FuncInfo, LibInfo);