1 //===-- AArch64AsmPrinter.cpp - Print machine code to an AArch64 .s file --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format AArch64 assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "AArch64AsmPrinter.h"
17 #include "InstPrinter/AArch64InstPrinter.h"
18 #include "llvm/DebugInfo.h"
19 #include "llvm/ADT/SmallString.h"
20 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
21 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
22 #include "llvm/MC/MCAsmInfo.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Target/Mangler.h"
30 /// Try to print a floating-point register as if it belonged to a specified
31 /// register-class. For example the inline asm operand modifier "b" requires its
32 /// argument to be printed as "bN".
33 static bool printModifiedFPRAsmOperand(const MachineOperand &MO,
34 const TargetRegisterInfo *TRI,
35 char RegType, raw_ostream &O) {
39 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) {
40 if (AArch64::FPR8RegClass.contains(*AR)) {
41 O << RegType << TRI->getEncodingValue(MO.getReg());
46 // The register doesn't correspond to anything floating-point like.
50 /// Implements the 'w' and 'x' inline asm operand modifiers, which print a GPR
51 /// with the obvious type and an immediate 0 as either wzr or xzr.
52 static bool printModifiedGPRAsmOperand(const MachineOperand &MO,
53 const TargetRegisterInfo *TRI,
54 const TargetRegisterClass &RegClass,
56 char Prefix = &RegClass == &AArch64::GPR32RegClass ? 'w' : 'x';
58 if (MO.isImm() && MO.getImm() == 0) {
61 } else if (MO.isReg()) {
62 if (MO.getReg() == AArch64::XSP || MO.getReg() == AArch64::WSP) {
63 O << (Prefix == 'x' ? "sp" : "wsp");
67 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) {
68 if (RegClass.contains(*AR)) {
69 O << AArch64InstPrinter::getRegisterName(*AR);
78 bool AArch64AsmPrinter::printSymbolicAddress(const MachineOperand &MO,
79 bool PrintImmediatePrefix,
80 StringRef Suffix, raw_ostream &O) {
83 switch (MO.getType()) {
85 llvm_unreachable("Unexpected operand for symbolic address constraint");
86 case MachineOperand::MO_GlobalAddress:
87 Name = getSymbol(MO.getGlobal())->getName();
89 // Global variables may be accessed either via a GOT or in various fun and
90 // interesting TLS-model specific ways. Set the prefix modifier as
92 if (const GlobalVariable *GV = dyn_cast<GlobalVariable>(MO.getGlobal())) {
93 Reloc::Model RelocM = TM.getRelocationModel();
94 if (GV->isThreadLocal()) {
95 switch (TM.getTLSModel(GV)) {
96 case TLSModel::GeneralDynamic:
99 case TLSModel::LocalDynamic:
102 case TLSModel::InitialExec:
103 Modifier = "gottprel";
105 case TLSModel::LocalExec:
109 } else if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) {
114 case MachineOperand::MO_BlockAddress:
115 Name = GetBlockAddressSymbol(MO.getBlockAddress())->getName();
117 case MachineOperand::MO_ExternalSymbol:
118 Name = MO.getSymbolName();
120 case MachineOperand::MO_ConstantPoolIndex:
121 Name = GetCPISymbol(MO.getIndex())->getName();
125 // Some instructions (notably ADRP) don't take the # prefix for
126 // immediates. Only print it if asked to.
127 if (PrintImmediatePrefix)
130 // Only need the joining "_" if both the prefix and the suffix are
131 // non-null. This little block simply takes care of the four possibly
132 // combinations involved there.
133 if (Modifier == "" && Suffix == "")
135 else if (Modifier == "" && Suffix != "")
136 O << ":" << Suffix << ':' << Name;
137 else if (Modifier != "" && Suffix == "")
138 O << ":" << Modifier << ':' << Name;
140 O << ":" << Modifier << '_' << Suffix << ':' << Name;
145 bool AArch64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
147 const char *ExtraCode, raw_ostream &O) {
148 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
149 if (!ExtraCode || !ExtraCode[0]) {
150 // There's actually no operand modifier, which leads to a slightly eclectic
151 // set of behaviour which we have to handle here.
152 const MachineOperand &MO = MI->getOperand(OpNum);
153 switch (MO.getType()) {
155 llvm_unreachable("Unexpected operand for inline assembly");
156 case MachineOperand::MO_Register:
157 // GCC prints the unmodified operand of a 'w' constraint as the vector
158 // register. Technically, we could allocate the argument as a VPR128, but
159 // that leads to extremely dodgy copies being generated to get the data
161 if (printModifiedFPRAsmOperand(MO, TRI, 'v', O))
162 O << AArch64InstPrinter::getRegisterName(MO.getReg());
164 case MachineOperand::MO_Immediate:
165 O << '#' << MO.getImm();
167 case MachineOperand::MO_FPImmediate:
168 assert(MO.getFPImm()->isExactlyValue(0.0) && "Only FP 0.0 expected");
171 case MachineOperand::MO_BlockAddress:
172 case MachineOperand::MO_ConstantPoolIndex:
173 case MachineOperand::MO_GlobalAddress:
174 case MachineOperand::MO_ExternalSymbol:
175 return printSymbolicAddress(MO, false, "", O);
180 // We have a real modifier to handle.
181 switch(ExtraCode[0]) {
183 // See if this is a generic operand
184 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
185 case 'c': // Don't print "#" before an immediate operand.
186 if (!MI->getOperand(OpNum).isImm())
188 O << MI->getOperand(OpNum).getImm();
191 // Output 32-bit general register operand, constant zero as wzr, or stack
192 // pointer as wsp. Ignored when used with other operand types.
193 return printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI,
194 AArch64::GPR32RegClass, O);
196 // Output 64-bit general register operand, constant zero as xzr, or stack
197 // pointer as sp. Ignored when used with other operand types.
198 return printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI,
199 AArch64::GPR64RegClass, O);
201 // Output higher numbered of a 64-bit general register pair
203 // Output least significant register of a 64-bit general register pair
205 // Output most significant register of a 64-bit general register pair
207 // FIXME note: these three operand modifiers will require, to some extent,
208 // adding a paired GPR64 register class. Initial investigation suggests that
209 // assertions are hit unless it has a type and is made legal for that type
210 // in ISelLowering. After that step is made, the number of modifications
211 // needed explodes (operation legality, calling conventions, stores, reg
213 llvm_unreachable("FIXME: Unimplemented register pairs");
219 return printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI,
222 // Output symbolic address with appropriate relocation modifier (also
223 // suitable for ADRP).
224 return printSymbolicAddress(MI->getOperand(OpNum), false, "", O);
226 // Output bits 11:0 of symbolic address with appropriate :lo12: relocation
228 return printSymbolicAddress(MI->getOperand(OpNum), true, "lo12", O);
230 // Output bits 23:12 of symbolic address with appropriate :hi12: relocation
231 // modifier (currently only for TLS local exec).
232 return printSymbolicAddress(MI->getOperand(OpNum), true, "hi12", O);
234 return PrintAsmMemoryOperand(MI, OpNum, AsmVariant, ExtraCode, O);
240 bool AArch64AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
243 const char *ExtraCode,
245 // Currently both the memory constraints (m and Q) behave the same and amount
246 // to the address as a single register. In future, we may allow "m" to provide
247 // both a base and an offset.
248 const MachineOperand &MO = MI->getOperand(OpNum);
249 assert(MO.isReg() && "unexpected inline assembly memory operand");
250 O << '[' << AArch64InstPrinter::getRegisterName(MO.getReg()) << ']';
254 #include "AArch64GenMCPseudoLowering.inc"
256 void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
257 // Do any auto-generated pseudo lowerings.
258 if (emitPseudoExpansionLowering(OutStreamer, MI))
262 LowerAArch64MachineInstrToMCInst(MI, TmpInst, *this);
263 OutStreamer.EmitInstruction(TmpInst);
266 void AArch64AsmPrinter::EmitEndOfAsmFile(Module &M) {
267 if (Subtarget->isTargetELF()) {
268 const TargetLoweringObjectFileELF &TLOFELF =
269 static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
271 MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
273 // Output stubs for external and common global variables.
274 MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
275 if (!Stubs.empty()) {
276 OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
277 const DataLayout *TD = TM.getDataLayout();
279 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
280 OutStreamer.EmitLabel(Stubs[i].first);
281 OutStreamer.EmitSymbolValue(Stubs[i].second.getPointer(),
282 TD->getPointerSize(0));
289 bool AArch64AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
290 return AsmPrinter::runOnMachineFunction(MF);
293 // Force static initialization.
294 extern "C" void LLVMInitializeAArch64AsmPrinter() {
295 RegisterAsmPrinter<AArch64AsmPrinter> X(TheAArch64Target);