lib/Target/AArch64/AArch64.td

   1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // AArch64 Subtarget features.
  21 //
  22
  23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
  24                                        "Enable ARMv8 FP">;
  25
  26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  27   "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
  28
  29 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
  30   "Enable cryptographic instructions">;
  31
  32 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
  33   "Enable ARMv8 CRC-32 checksum instructions">;
  34
  35 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  36   "Enable ARMv8 PMUv3 Performance Monitors extension">;
  37
  38 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
  39   "Full FP16", [FeatureFPARMv8]>;
  40
  41 /// Cyclone has register move instructions which are "free".
  42 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
  43                                         "Has zero-cycle register moves">;
  44
  45 /// Cyclone has instructions which zero registers for "free".
  46 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
  47                                         "Has zero-cycle zeroing instructions">;
  48
  49 def FeatureStrictAlign : SubtargetFeature<"strict-align",
  50                                           "StrictAlign", "true",
  51                                           "Disallow all unaligned memory "
  52                                           "access">;
  53
  54 def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
  55                                          "Reserve X18, making it unavailable "
  56                                          "as a GPR">;
  57
  58 //===----------------------------------------------------------------------===//
  59 // Architectures.
  60 //
  61
  62 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
  63   "Support ARM v8.1a instructions", [FeatureCRC]>;
  64
  65 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
  66   "Support ARM v8.2a instructions", [HasV8_1aOps]>;
  67
  68 //===----------------------------------------------------------------------===//
  69 // Register File Description
  70 //===----------------------------------------------------------------------===//
  71
  72 include "AArch64RegisterInfo.td"
  73 include "AArch64CallingConvention.td"
  74
  75 //===----------------------------------------------------------------------===//
  76 // Instruction Descriptions
  77 //===----------------------------------------------------------------------===//
  78
  79 include "AArch64Schedule.td"
  80 include "AArch64InstrInfo.td"
  81
  82 def AArch64InstrInfo : InstrInfo;
  83
  84 //===----------------------------------------------------------------------===//
  85 // AArch64 Processors supported.
  86 //
  87 include "AArch64SchedA53.td"
  88 include "AArch64SchedA57.td"
  89 include "AArch64SchedCyclone.td"
  90
  91 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
  92                                    "Cortex-A53 ARM processors",
  93                                    [FeatureFPARMv8,
  94                                    FeatureNEON,
  95                                    FeatureCrypto,
  96                                    FeatureCRC,
  97                                    FeaturePerfMon]>;
  98
  99 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 100                                    "Cortex-A57 ARM processors",
 101                                    [FeatureFPARMv8,
 102                                    FeatureNEON,
 103                                    FeatureCrypto,
 104                                    FeatureCRC,
 105                                    FeaturePerfMon]>;
 106
 107 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
 108                                    "Cyclone",
 109                                    [FeatureFPARMv8,
 110                                    FeatureNEON,
 111                                    FeatureCrypto,
 112                                    FeatureCRC,
 113                                    FeaturePerfMon,
 114                                    FeatureZCRegMove, FeatureZCZeroing]>;
 115
 116 def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8,
 117                                               FeatureNEON,
 118                                               FeatureCRC,
 119                                               FeaturePerfMon]>;
 120
 121 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
 122 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
 123 // FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
 124 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA57]>;
 125 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
 126
 127 //===----------------------------------------------------------------------===//
 128 // Assembly parser
 129 //===----------------------------------------------------------------------===//
 130
 131 def GenericAsmParserVariant : AsmParserVariant {
 132   int Variant = 0;
 133   string Name = "generic";
 134   string BreakCharacters = ".";
 135 }
 136
 137 def AppleAsmParserVariant : AsmParserVariant {
 138   int Variant = 1;
 139   string Name = "apple-neon";
 140   string BreakCharacters = ".";
 141 }
 142
 143 //===----------------------------------------------------------------------===//
 144 // Assembly printer
 145 //===----------------------------------------------------------------------===//
 146 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
 147 // AsmWriter bits get associated with the correct class.
 148 def GenericAsmWriter : AsmWriter {
 149   string AsmWriterClassName  = "InstPrinter";
 150   int PassSubtarget = 1;
 151   int Variant = 0;
 152   bit isMCAsmWriter = 1;
 153 }
 154
 155 def AppleAsmWriter : AsmWriter {
 156   let AsmWriterClassName = "AppleInstPrinter";
 157   int PassSubtarget = 1;
 158   int Variant = 1;
 159   int isMCAsmWriter = 1;
 160 }
 161
 162 //===----------------------------------------------------------------------===//
 163 // Target Declaration
 164 //===----------------------------------------------------------------------===//
 165
 166 def AArch64 : Target {
 167   let InstructionSet = AArch64InstrInfo;
 168   let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
 169   let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
 170 }