1 //===-- TargetParser - Parser for target features ---------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a target parser to recognise hardware features such as
11 // FPU/CPU/ARCH names as well as specific support such as HDIV, etc.
13 //===----------------------------------------------------------------------===//
15 #include "llvm/Support/ARMBuildAttributes.h"
16 #include "llvm/Support/TargetParser.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/ADT/StringSwitch.h"
24 // List of canonical FPU names (use getFPUSynonym)
25 // FIXME: TableGen this.
30 { "invalid", ARM::FK_INVALID },
31 { "vfp", ARM::FK_VFP },
32 { "vfpv2", ARM::FK_VFPV2 },
33 { "vfpv3", ARM::FK_VFPV3 },
34 { "vfpv3-d16", ARM::FK_VFPV3_D16 },
35 { "vfpv4", ARM::FK_VFPV4 },
36 { "vfpv4-d16", ARM::FK_VFPV4_D16 },
37 { "fpv5-d16", ARM::FK_FPV5_D16 },
38 { "fp-armv8", ARM::FK_FP_ARMV8 },
39 { "neon", ARM::FK_NEON },
40 { "neon-vfpv4", ARM::FK_NEON_VFPV4 },
41 { "neon-fp-armv8", ARM::FK_NEON_FP_ARMV8 },
42 { "crypto-neon-fp-armv8", ARM::FK_CRYPTO_NEON_FP_ARMV8 },
43 { "softvfp", ARM::FK_SOFTVFP }
45 // List of canonical arch names (use getArchSynonym)
46 // FIXME: TableGen this.
50 const char *DefaultCPU;
51 ARMBuildAttrs::CPUArch DefaultArch;
53 { "invalid", ARM::AK_INVALID, nullptr, ARMBuildAttrs::CPUArch::Pre_v4 },
54 { "armv2", ARM::AK_ARMV2, "2", ARMBuildAttrs::CPUArch::v4 },
55 { "armv2a", ARM::AK_ARMV2A, "2A", ARMBuildAttrs::CPUArch::v4 },
56 { "armv3", ARM::AK_ARMV3, "3", ARMBuildAttrs::CPUArch::v4 },
57 { "armv3m", ARM::AK_ARMV3M, "3M", ARMBuildAttrs::CPUArch::v4 },
58 { "armv4", ARM::AK_ARMV4, "4", ARMBuildAttrs::CPUArch::v4 },
59 { "armv4t", ARM::AK_ARMV4T, "4T", ARMBuildAttrs::CPUArch::v4T },
60 { "armv5", ARM::AK_ARMV5, "5", ARMBuildAttrs::CPUArch::v5T },
61 { "armv5t", ARM::AK_ARMV5T, "5T", ARMBuildAttrs::CPUArch::v5T },
62 { "armv5te", ARM::AK_ARMV5TE, "5TE", ARMBuildAttrs::CPUArch::v5TE },
63 { "armv6", ARM::AK_ARMV6, "6", ARMBuildAttrs::CPUArch::v6 },
64 { "armv6j", ARM::AK_ARMV6J, "6J", ARMBuildAttrs::CPUArch::v6 },
65 { "armv6k", ARM::AK_ARMV6K, "6K", ARMBuildAttrs::CPUArch::v6K },
66 { "armv6t2", ARM::AK_ARMV6T2, "6T2", ARMBuildAttrs::CPUArch::v6T2 },
67 { "armv6z", ARM::AK_ARMV6Z, "6Z", ARMBuildAttrs::CPUArch::v6KZ },
68 { "armv6zk", ARM::AK_ARMV6ZK, "6ZK", ARMBuildAttrs::CPUArch::v6KZ },
69 { "armv6-m", ARM::AK_ARMV6M, "6-M", ARMBuildAttrs::CPUArch::v6_M },
70 { "armv7", ARM::AK_ARMV7, "7", ARMBuildAttrs::CPUArch::v7 },
71 { "armv7-a", ARM::AK_ARMV7A, "7-A", ARMBuildAttrs::CPUArch::v7 },
72 { "armv7-r", ARM::AK_ARMV7R, "7-R", ARMBuildAttrs::CPUArch::v7 },
73 { "armv7-m", ARM::AK_ARMV7M, "7-M", ARMBuildAttrs::CPUArch::v7 },
74 { "armv8-a", ARM::AK_ARMV8A, "8-A", ARMBuildAttrs::CPUArch::v8 },
75 { "armv8.1-a", ARM::AK_ARMV8_1A, "8.1-A", ARMBuildAttrs::CPUArch::v8 },
76 // Non-standard Arch names.
77 { "iwmmxt", ARM::AK_IWMMXT, "iwmmxt", ARMBuildAttrs::CPUArch::v5TE },
78 { "iwmmxt2", ARM::AK_IWMMXT2, "iwmmxt2", ARMBuildAttrs::CPUArch::v5TE },
79 { "xscale", ARM::AK_XSCALE, "xscale", ARMBuildAttrs::CPUArch::v5TE },
80 { "armv5e", ARM::AK_ARMV5E, "5E", ARMBuildAttrs::CPUArch::v5TE },
81 { "armv5tej", ARM::AK_ARMV5TEJ, "5TE", ARMBuildAttrs::CPUArch::v5TE },
82 { "armv6sm", ARM::AK_ARMV6SM, "6-M", ARMBuildAttrs::CPUArch::v6_M },
83 { "armv6hl", ARM::AK_ARMV6HL, "6-M", ARMBuildAttrs::CPUArch::v6_M },
84 { "armv7e-m", ARM::AK_ARMV7EM, "7E-M", ARMBuildAttrs::CPUArch::v7E_M },
85 { "armv7l", ARM::AK_ARMV7L, "7-L", ARMBuildAttrs::CPUArch::v7 },
86 { "armv7hl", ARM::AK_ARMV7HL, "7H-L", ARMBuildAttrs::CPUArch::v7 },
87 { "armv7s", ARM::AK_ARMV7S, "7-S", ARMBuildAttrs::CPUArch::v7 }
89 // List of canonical ARCH names (use getARCHSynonym)
90 // FIXME: TableGen this.
95 { "invalid", ARM::AEK_INVALID },
96 { "crc", ARM::AEK_CRC },
97 { "crypto", ARM::AEK_CRYPTO },
98 { "fp", ARM::AEK_FP },
99 { "idiv", ARM::AEK_HWDIV },
100 { "mp", ARM::AEK_MP },
101 { "sec", ARM::AEK_SEC },
102 { "virt", ARM::AEK_VIRT }
104 // List of CPU names and their arches.
105 // The same CPU can have multiple arches and can be default on multiple arches.
106 // When finding the Arch for a CPU, first-found prevails. Sort them accordingly.
107 // FIXME: TableGen this.
110 ARM::ArchKind ArchID;
113 { "arm2", ARM::AK_ARMV2, true },
114 { "arm6", ARM::AK_ARMV3, true },
115 { "arm7m", ARM::AK_ARMV3M, true },
116 { "strongarm", ARM::AK_ARMV4, true },
117 { "arm7tdmi", ARM::AK_ARMV4T, true },
118 { "arm7tdmi-s", ARM::AK_ARMV4T, false },
119 { "arm710t", ARM::AK_ARMV4T, false },
120 { "arm720t", ARM::AK_ARMV4T, false },
121 { "arm9", ARM::AK_ARMV4T, false },
122 { "arm9tdmi", ARM::AK_ARMV4T, false },
123 { "arm920", ARM::AK_ARMV4T, false },
124 { "arm920t", ARM::AK_ARMV4T, false },
125 { "arm922t", ARM::AK_ARMV4T, false },
126 { "arm9312", ARM::AK_ARMV4T, false },
127 { "arm940t", ARM::AK_ARMV4T, false },
128 { "ep9312", ARM::AK_ARMV4T, false },
129 { "arm10tdmi", ARM::AK_ARMV5, true },
130 { "arm10tdmi", ARM::AK_ARMV5T, true },
131 { "arm1020t", ARM::AK_ARMV5T, false },
132 { "xscale", ARM::AK_XSCALE, true },
133 { "xscale", ARM::AK_ARMV5TE, false },
134 { "arm9e", ARM::AK_ARMV5TE, false },
135 { "arm926ej-s", ARM::AK_ARMV5TE, false },
136 { "arm946ej-s", ARM::AK_ARMV5TE, false },
137 { "arm966e-s", ARM::AK_ARMV5TE, false },
138 { "arm968e-s", ARM::AK_ARMV5TE, false },
139 { "arm1020e", ARM::AK_ARMV5TE, false },
140 { "arm1022e", ARM::AK_ARMV5TE, true },
141 { "iwmmxt", ARM::AK_ARMV5TE, false },
142 { "iwmmxt", ARM::AK_IWMMXT, true },
143 { "arm1136jf-s", ARM::AK_ARMV6, true },
144 { "arm1136j-s", ARM::AK_ARMV6J, true },
145 { "arm1136jz-s", ARM::AK_ARMV6J, false },
146 { "arm1176j-s", ARM::AK_ARMV6K, false },
147 { "mpcore", ARM::AK_ARMV6K, false },
148 { "mpcorenovfp", ARM::AK_ARMV6K, false },
149 { "arm1176jzf-s", ARM::AK_ARMV6K, true },
150 { "arm1176jzf-s", ARM::AK_ARMV6Z, true },
151 { "arm1176jzf-s", ARM::AK_ARMV6ZK, true },
152 { "arm1156t2-s", ARM::AK_ARMV6T2, true },
153 { "arm1156t2f-s", ARM::AK_ARMV6T2, false },
154 { "cortex-m0", ARM::AK_ARMV6M, true },
155 { "cortex-m0plus", ARM::AK_ARMV6M, false },
156 { "cortex-m1", ARM::AK_ARMV6M, false },
157 { "sc000", ARM::AK_ARMV6M, false },
158 { "cortex-a8", ARM::AK_ARMV7, true },
159 { "cortex-a5", ARM::AK_ARMV7A, false },
160 { "cortex-a7", ARM::AK_ARMV7A, false },
161 { "cortex-a8", ARM::AK_ARMV7A, true },
162 { "cortex-a9", ARM::AK_ARMV7A, false },
163 { "cortex-a12", ARM::AK_ARMV7A, false },
164 { "cortex-a15", ARM::AK_ARMV7A, false },
165 { "cortex-a17", ARM::AK_ARMV7A, false },
166 { "krait", ARM::AK_ARMV7A, false },
167 { "cortex-r4", ARM::AK_ARMV7R, true },
168 { "cortex-r4f", ARM::AK_ARMV7R, false },
169 { "cortex-r5", ARM::AK_ARMV7R, false },
170 { "cortex-r7", ARM::AK_ARMV7R, false },
171 { "sc300", ARM::AK_ARMV7M, false },
172 { "cortex-m3", ARM::AK_ARMV7M, true },
173 { "cortex-m4", ARM::AK_ARMV7M, false },
174 { "cortex-m7", ARM::AK_ARMV7M, false },
175 { "cortex-a53", ARM::AK_ARMV8A, true },
176 { "cortex-a57", ARM::AK_ARMV8A, false },
177 { "cortex-a72", ARM::AK_ARMV8A, false },
178 { "cyclone", ARM::AK_ARMV8A, false },
179 { "generic", ARM::AK_ARMV8_1A, true },
180 // Non-standard Arch names.
181 { "arm1022e", ARM::AK_ARMV5E, true },
182 { "arm926ej-s", ARM::AK_ARMV5TEJ, true },
183 { "cortex-m0", ARM::AK_ARMV6SM, true },
184 { "arm1176jzf-s", ARM::AK_ARMV6HL, true },
185 { "cortex-a8", ARM::AK_ARMV7L, true },
186 { "cortex-a8", ARM::AK_ARMV7HL, true },
187 { "cortex-m4", ARM::AK_ARMV7EM, true },
188 { "swift", ARM::AK_ARMV7S, true },
190 { "invalid", ARM::AK_INVALID, true }
197 // ======================================================= //
199 // ======================================================= //
201 const char *ARMTargetParser::getFPUName(unsigned FPUKind) {
202 if (FPUKind >= ARM::FK_LAST)
204 return FPUNames[FPUKind].Name;
207 const char *ARMTargetParser::getArchName(unsigned ArchKind) {
208 if (ArchKind >= ARM::AK_LAST)
210 return ARCHNames[ArchKind].Name;
213 const char *ARMTargetParser::getArchDefaultCPUName(unsigned ArchKind) {
214 if (ArchKind >= ARM::AK_LAST)
216 return ARCHNames[ArchKind].DefaultCPU;
219 unsigned ARMTargetParser::getArchDefaultCPUArch(unsigned ArchKind) {
220 if (ArchKind >= ARM::AK_LAST)
221 return ARMBuildAttrs::CPUArch::Pre_v4;
222 return ARCHNames[ArchKind].DefaultArch;
225 const char *ARMTargetParser::getArchExtName(unsigned ArchExtKind) {
226 if (ArchExtKind >= ARM::AEK_LAST)
228 return ARCHExtNames[ArchExtKind].Name;
231 const char *ARMTargetParser::getDefaultCPU(StringRef Arch) {
232 unsigned AK = parseArch(Arch);
233 if (AK == ARM::AK_INVALID)
236 // Look for multiple AKs to find the default for pair AK+Name.
237 for (const auto CPU : CPUNames) {
238 if (CPU.ArchID == AK && CPU.Default)
244 // ======================================================= //
246 // ======================================================= //
248 StringRef ARMTargetParser::getFPUSynonym(StringRef FPU) {
249 return StringSwitch<StringRef>(FPU)
250 .Cases("fpa", "fpe2", "fpe3", "maverick", "invalid") // Unsupported
251 .Case("vfp2", "vfpv2")
252 .Case("vfp3", "vfpv3")
253 .Case("vfp4", "vfpv4")
254 .Case("vfp3-d16", "vfpv3-d16")
255 .Case("vfp4-d16", "vfpv4-d16")
256 // FIXME: sp-16 is NOT the same as d16
257 .Cases("fp4-sp-d16", "fpv4-sp-d16", "vfpv4-d16")
258 .Cases("fp4-dp-d16", "fpv4-dp-d16", "vfpv4-d16")
259 .Cases("fp5-sp-d16", "fpv5-sp-d16", "fpv5-d16")
260 .Cases("fp5-dp-d16", "fpv5-dp-d16", "fpv5-d16")
261 // FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3.
262 .Case("neon-vfpv3", "neon")
266 StringRef ARMTargetParser::getArchSynonym(StringRef Arch) {
267 return StringSwitch<StringRef>(Arch)
268 .Cases("armv6m", "v6m", "armv6-m")
269 .Cases("armv7a", "v7a", "armv7-a")
270 .Cases("armv7r", "v7r", "armv7-r")
271 .Cases("armv7m", "v7m", "armv7-m")
272 .Cases("armv7em", "v7em", "armv7e-m")
273 .Cases("armv8", "v8", "armv8-a")
274 .Cases("armv8a", "v8a", "armv8-a")
275 .Cases("armv8.1a", "v8.1a", "armv8.1-a")
276 .Cases("aarch64", "arm64", "armv8-a")
280 // MArch is expected to be of the form (arm|thumb)?(eb)?(v.+)?(eb)?, but
281 // (iwmmxt|xscale)(eb)? is also permitted. If the former, return
282 // "v.+", if the latter, return unmodified string. If invalid, return "".
283 StringRef ARMTargetParser::getCanonicalArchName(StringRef Arch) {
284 size_t offset = StringRef::npos;
286 StringRef Error = "";
288 // Begins with "arm" / "thumb", move past it.
289 if (A.startswith("arm"))
291 else if (A.startswith("thumb"))
293 else if (A.startswith("aarch64")) {
295 // AArch64 uses "_be", not "eb" suffix.
296 if (A.find("eb") != StringRef::npos)
298 if (A.substr(offset,3) == "_be")
302 // Ex. "armebv7", move past the "eb".
303 if (offset != StringRef::npos && A.substr(offset, 2) == "eb")
305 // Or, if it ends with eb ("armv7eb"), chop it off.
306 else if (A.endswith("eb"))
307 A = A.substr(0, A.size() - 2);
308 // Reached the end or a 'v', canonicalise.
309 if (offset != StringRef::npos && (offset == A.size() || A[offset] == 'v'))
310 A = A.substr(offset);
312 // Empty string mans offset reached the end. Although valid, this arch
313 // will not have a match in the table. Return the original string.
317 // If can't find the arch, return an empty StringRef.
318 if (parseArch(A) == ARM::AK_INVALID)
321 // Arch will either be a 'v' name (v7a) or a marketing name (xscale)
322 // or empty, if invalid.
326 unsigned ARMTargetParser::parseFPU(StringRef FPU) {
327 StringRef Syn = getFPUSynonym(FPU);
328 for (const auto F : FPUNames) {
332 return ARM::FK_INVALID;
335 // Allows partial match, ex. "v7a" matches "armv7a".
336 unsigned ARMTargetParser::parseArch(StringRef Arch) {
337 StringRef Syn = getArchSynonym(Arch);
338 for (const auto A : ARCHNames) {
339 if (StringRef(A.Name).endswith(Syn))
342 return ARM::AK_INVALID;
345 unsigned ARMTargetParser::parseArchExt(StringRef ArchExt) {
346 for (const auto A : ARCHExtNames) {
347 if (ArchExt == A.Name)
350 return ARM::AEK_INVALID;
353 unsigned ARMTargetParser::parseCPUArch(StringRef CPU) {
354 for (const auto C : CPUNames) {
358 return ARM::AK_INVALID;
361 // ARM, Thumb, AArch64
362 unsigned ARMTargetParser::parseArchISA(StringRef Arch) {
363 return StringSwitch<unsigned>(Arch)
364 .StartsWith("aarch64", ARM::IK_AARCH64)
365 .StartsWith("arm64", ARM::IK_AARCH64)
366 .StartsWith("thumb", ARM::IK_THUMB)
367 .StartsWith("arm", ARM::IK_ARM)
368 .Default(ARM::EK_INVALID);
372 unsigned ARMTargetParser::parseArchEndian(StringRef Arch) {
373 if (Arch.startswith("armeb") ||
374 Arch.startswith("thumbeb") ||
375 Arch.startswith("aarch64_be"))
378 if (Arch.startswith("arm") || Arch.startswith("thumb")) {
379 if (Arch.endswith("eb"))
382 return ARM::EK_LITTLE;
385 if (Arch.startswith("aarch64"))
386 return ARM::EK_LITTLE;
388 return ARM::EK_INVALID;
392 unsigned ARMTargetParser::parseArchProfile(StringRef Arch) {
393 // FIXME: We're running parseArch twice.
394 Arch = getCanonicalArchName(Arch);
395 switch(parseArch(Arch)) {
398 case ARM::AK_ARMV6SM:
399 case ARM::AK_ARMV7EM:
406 case ARM::AK_ARMV8_1A:
409 return ARM::PK_INVALID;
412 // Version number 4 ~ 8 (ex. v7 = 7).
413 unsigned ARMTargetParser::parseArchVersion(StringRef Arch) {
414 // FIXME: We're running parseArch twice.
415 Arch = getCanonicalArchName(Arch);
416 switch(parseArch(Arch)) {
428 case ARM::AK_ARMV5TE:
430 case ARM::AK_IWMMXT2:
433 case ARM::AK_ARMV5TEJ:
438 case ARM::AK_ARMV6T2:
440 case ARM::AK_ARMV6ZK:
442 case ARM::AK_ARMV6SM:
443 case ARM::AK_ARMV6HL:
450 case ARM::AK_ARMV7HL:
452 case ARM::AK_ARMV7EM:
455 case ARM::AK_ARMV8_1A: