1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This header file implements the operating system Host concept.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Support/Host.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/Config/config.h"
20 #include "llvm/Support/DataStream.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
25 // Include the platform-specific parts of this class.
27 #include "Unix/Host.inc"
30 #include "Windows/Host.inc"
35 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
36 #include <mach/mach.h>
37 #include <mach/mach_host.h>
38 #include <mach/host_info.h>
39 #include <mach/machine.h>
42 #define DEBUG_TYPE "host-detection"
44 //===----------------------------------------------------------------------===//
46 // Implementations of the CPU detection routines
48 //===----------------------------------------------------------------------===//
52 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
53 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
55 /// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
56 /// specified arguments. If we can't run cpuid on the host, return true.
57 static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
58 unsigned *rECX, unsigned *rEDX) {
59 #if defined(__GNUC__) || defined(__clang__)
60 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
61 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
62 asm ("movq\t%%rbx, %%rsi\n\t"
64 "xchgq\t%%rbx, %%rsi\n\t"
71 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
72 asm ("movl\t%%ebx, %%esi\n\t"
74 "xchgl\t%%ebx, %%esi\n\t"
81 // pedantic #else returns to appease -Wunreachable-code (so we don't generate
82 // postprocessed code that looks like "return true; return false;")
86 #elif defined(_MSC_VER)
87 // The MSVC intrinsic is portable across x86 and x64.
89 __cpuid(registers, value);
100 /// GetX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the
101 /// 4 values in the specified arguments. If we can't run cpuid on the host,
103 static bool GetX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
104 unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
106 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
107 #if defined(__GNUC__)
108 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
109 asm ("movq\t%%rbx, %%rsi\n\t"
111 "xchgq\t%%rbx, %%rsi\n\t"
119 #elif defined(_MSC_VER)
120 // __cpuidex was added in MSVC++ 9.0 SP1
121 #if (_MSC_VER > 1500) || (_MSC_VER == 1500 && _MSC_FULL_VER >= 150030729)
123 __cpuidex(registers, value, subleaf);
124 *rEAX = registers[0];
125 *rEBX = registers[1];
126 *rECX = registers[2];
127 *rEDX = registers[3];
135 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
136 #if defined(__GNUC__)
137 asm ("movl\t%%ebx, %%esi\n\t"
139 "xchgl\t%%ebx, %%esi\n\t"
147 #elif defined(_MSC_VER)
153 mov dword ptr [esi],eax
155 mov dword ptr [esi],ebx
157 mov dword ptr [esi],ecx
159 mov dword ptr [esi],edx
170 static bool OSHasAVXSupport() {
171 #if defined(__GNUC__)
172 // Check xgetbv; this uses a .byte sequence instead of the instruction
173 // directly because older assemblers do not include support for xgetbv and
174 // there is no easy way to conditionally compile based on the assembler used.
176 __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
177 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
178 unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
180 int rEAX = 0; // Ensures we return false
182 return (rEAX & 6) == 6;
185 static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
187 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
188 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
189 if (Family == 6 || Family == 0xf) {
191 // Examine extended family ID if family ID is F.
192 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
193 // Examine extended model ID if family ID is 6 or F.
194 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
198 StringRef sys::getHostCPUName() {
199 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
200 if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
204 DetectX86FamilyModel(EAX, Family, Model);
211 GetX86CpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
213 unsigned MaxLeaf = EAX;
214 bool HasSSE3 = (ECX & 0x1);
215 bool HasSSE41 = (ECX & 0x80000);
216 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
217 // indicates that the AVX registers will be saved and restored on context
218 // switch, then we have full AVX support.
219 const unsigned AVXBits = (1 << 27) | (1 << 28);
220 bool HasAVX = ((ECX & AVXBits) == AVXBits) && OSHasAVXSupport();
221 bool HasAVX2 = HasAVX && MaxLeaf >= 0x7 &&
222 !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX) &&
224 GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
225 bool Em64T = (EDX >> 29) & 0x1;
227 if (memcmp(text.c, "GenuineIntel", 12) == 0) {
233 case 0: // Intel486 DX processors
234 case 1: // Intel486 DX processors
235 case 2: // Intel486 SX processors
236 case 3: // Intel487 processors, IntelDX2 OverDrive processors,
237 // IntelDX2 processors
238 case 4: // Intel486 SL processor
239 case 5: // IntelSX2 processors
240 case 7: // Write-Back Enhanced IntelDX2 processors
241 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
242 default: return "i486";
246 case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
247 // Pentium processors (60, 66)
248 case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
249 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
251 case 3: // Pentium OverDrive processors for Intel486 processor-based
255 case 4: // Pentium OverDrive processor with MMX technology for Pentium
256 // processor (75, 90, 100, 120, 133), Pentium processor with
257 // MMX technology (166, 200)
258 return "pentium-mmx";
260 default: return "pentium";
264 case 1: // Pentium Pro processor
267 case 3: // Intel Pentium II OverDrive processor, Pentium II processor,
269 case 5: // Pentium II processor, model 05, Pentium II Xeon processor,
270 // model 05, and Intel Celeron processor, model 05
271 case 6: // Celeron processor, model 06
274 case 7: // Pentium III processor, model 07, and Pentium III Xeon
275 // processor, model 07
276 case 8: // Pentium III processor, model 08, Pentium III Xeon processor,
277 // model 08, and Celeron processor, model 08
278 case 10: // Pentium III Xeon processor, model 0Ah
279 case 11: // Pentium III processor, model 0Bh
282 case 9: // Intel Pentium M processor, Intel Celeron M processor model 09.
283 case 13: // Intel Pentium M processor, Intel Celeron M processor, model
284 // 0Dh. All processors are manufactured using the 90 nm process.
287 case 14: // Intel Core Duo processor, Intel Core Solo processor, model
288 // 0Eh. All processors are manufactured using the 65 nm process.
291 case 15: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
292 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
293 // mobile processor, Intel Core 2 Extreme processor, Intel
294 // Pentium Dual-Core processor, Intel Xeon processor, model
295 // 0Fh. All processors are manufactured using the 65 nm process.
296 case 22: // Intel Celeron processor model 16h. All processors are
297 // manufactured using the 65 nm process
300 case 21: // Intel EP80579 Integrated Processor and Intel EP80579
301 // Integrated Processor with Intel QuickAssist Technology
302 return "i686"; // FIXME: ???
304 case 23: // Intel Core 2 Extreme processor, Intel Xeon processor, model
305 // 17h. All processors are manufactured using the 45 nm process.
307 // 45nm: Penryn , Wolfdale, Yorkfield (XE)
308 // Not all Penryn processors support SSE 4.1 (such as the Pentium brand)
309 return HasSSE41 ? "penryn" : "core2";
311 case 26: // Intel Core i7 processor and Intel Xeon processor. All
312 // processors are manufactured using the 45 nm process.
313 case 29: // Intel Xeon processor MP. All processors are manufactured using
314 // the 45 nm process.
315 case 30: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
316 // As found in a Summer 2010 model iMac.
317 case 37: // Intel Core i7, laptop version.
318 case 44: // Intel Core i7 processor and Intel Xeon processor. All
319 // processors are manufactured using the 32 nm process.
320 case 46: // Nehalem EX
321 case 47: // Westmere EX
325 case 42: // Intel Core i7 processor. All processors are manufactured
326 // using the 32 nm process.
328 // Not all Sandy Bridge processors support AVX (such as the Pentium
329 // versions instead of the i7 versions).
330 return HasAVX ? "corei7-avx" : "corei7";
334 case 62: // Ivy Bridge EP
335 // Not all Ivy Bridge processors support AVX (such as the Pentium
336 // versions instead of the i7 versions).
337 return HasAVX ? "core-avx-i" : "corei7";
344 // Not all Haswell processors support AVX too (such as the Pentium
345 // versions instead of the i7 versions).
346 return HasAVX2 ? "core-avx2" : "corei7";
348 case 28: // Most 45 nm Intel Atom processors
349 case 38: // 45 nm Atom Lincroft
350 case 39: // 32 nm Atom Medfield
351 case 53: // 32 nm Atom Midview
352 case 54: // 32 nm Atom Midview
355 // Atom Silvermont codes from the Intel software optimization guide.
361 default: return (Em64T) ? "x86-64" : "i686";
365 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
366 // model 00h and manufactured using the 0.18 micron process.
367 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
368 // processor MP, and Intel Celeron processor. All processors are
369 // model 01h and manufactured using the 0.18 micron process.
370 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
371 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
372 // processor, and Mobile Intel Celeron processor. All processors
373 // are model 02h and manufactured using the 0.13 micron process.
374 return (Em64T) ? "x86-64" : "pentium4";
376 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
377 // processor. All processors are model 03h and manufactured using
378 // the 90 nm process.
379 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
380 // Pentium D processor, Intel Xeon processor, Intel Xeon
381 // processor MP, Intel Celeron D processor. All processors are
382 // model 04h and manufactured using the 90 nm process.
383 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
384 // Extreme Edition, Intel Xeon processor, Intel Xeon processor
385 // MP, Intel Celeron D processor. All processors are model 06h
386 // and manufactured using the 65 nm process.
387 return (Em64T) ? "nocona" : "prescott";
390 return (Em64T) ? "x86-64" : "pentium4";
397 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
398 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
399 // appears to be no way to generate the wide variety of AMD-specific targets
400 // from the information returned from CPUID.
408 case 8: return "k6-2";
410 case 13: return "k6-3";
411 case 10: return "geode";
412 default: return "pentium";
416 case 4: return "athlon-tbird";
419 case 8: return "athlon-mp";
420 case 10: return "athlon-xp";
421 default: return "athlon";
427 case 1: return "opteron";
428 case 5: return "athlon-fx"; // also opteron
429 default: return "athlon64";
436 if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
439 return "bdver4"; // 50h-6Fh: Excavator
441 return "bdver3"; // 30h-3Fh: Steamroller
443 return "bdver2"; // 10h-1Fh: Piledriver
444 return "bdver1"; // 00h-0Fh: Bulldozer
446 if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
455 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
456 StringRef sys::getHostCPUName() {
457 host_basic_info_data_t hostInfo;
458 mach_msg_type_number_t infoCount;
460 infoCount = HOST_BASIC_INFO_COUNT;
461 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
464 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) return "generic";
466 switch(hostInfo.cpu_subtype) {
467 case CPU_SUBTYPE_POWERPC_601: return "601";
468 case CPU_SUBTYPE_POWERPC_602: return "602";
469 case CPU_SUBTYPE_POWERPC_603: return "603";
470 case CPU_SUBTYPE_POWERPC_603e: return "603e";
471 case CPU_SUBTYPE_POWERPC_603ev: return "603ev";
472 case CPU_SUBTYPE_POWERPC_604: return "604";
473 case CPU_SUBTYPE_POWERPC_604e: return "604e";
474 case CPU_SUBTYPE_POWERPC_620: return "620";
475 case CPU_SUBTYPE_POWERPC_750: return "750";
476 case CPU_SUBTYPE_POWERPC_7400: return "7400";
477 case CPU_SUBTYPE_POWERPC_7450: return "7450";
478 case CPU_SUBTYPE_POWERPC_970: return "970";
484 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
485 StringRef sys::getHostCPUName() {
486 // Access to the Processor Version Register (PVR) on PowerPC is privileged,
487 // and so we must use an operating-system interface to determine the current
488 // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
489 const char *generic = "generic";
491 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
492 // memory buffer because the 'file' has 0 size (it can be read from only
496 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
498 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
502 // The cpu line is second (after the 'processor: 0' line), so if this
503 // buffer is too small then something has changed (or is wrong).
505 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
508 const char *CPUInfoStart = buffer;
509 const char *CPUInfoEnd = buffer + CPUInfoSize;
511 const char *CIP = CPUInfoStart;
513 const char *CPUStart = 0;
516 // We need to find the first line which starts with cpu, spaces, and a colon.
517 // After the colon, there may be some additional spaces and then the cpu type.
518 while (CIP < CPUInfoEnd && CPUStart == 0) {
519 if (CIP < CPUInfoEnd && *CIP == '\n')
522 if (CIP < CPUInfoEnd && *CIP == 'c') {
524 if (CIP < CPUInfoEnd && *CIP == 'p') {
526 if (CIP < CPUInfoEnd && *CIP == 'u') {
528 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
531 if (CIP < CPUInfoEnd && *CIP == ':') {
533 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
536 if (CIP < CPUInfoEnd) {
538 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
539 *CIP != ',' && *CIP != '\n'))
541 CPULen = CIP - CPUStart;
549 while (CIP < CPUInfoEnd && *CIP != '\n')
556 return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
557 .Case("604e", "604e")
559 .Case("7400", "7400")
560 .Case("7410", "7400")
561 .Case("7447", "7400")
562 .Case("7455", "7450")
564 .Case("POWER4", "970")
565 .Case("PPC970FX", "970")
566 .Case("PPC970MP", "970")
568 .Case("POWER5", "g5")
570 .Case("POWER6", "pwr6")
571 .Case("POWER7", "pwr7")
574 #elif defined(__linux__) && defined(__arm__)
575 StringRef sys::getHostCPUName() {
576 // The cpuid register on arm is not accessible from user space. On Linux,
577 // it is exposed through the /proc/cpuinfo file.
578 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
579 // memory buffer because the 'file' has 0 size (it can be read from only
583 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
585 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
589 // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line
592 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
595 StringRef Str(buffer, CPUInfoSize);
597 SmallVector<StringRef, 32> Lines;
598 Str.split(Lines, "\n");
600 // Look for the CPU implementer line.
601 StringRef Implementer;
602 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
603 if (Lines[I].startswith("CPU implementer"))
604 Implementer = Lines[I].substr(15).ltrim("\t :");
606 if (Implementer == "0x41") // ARM Ltd.
607 // Look for the CPU part line.
608 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
609 if (Lines[I].startswith("CPU part"))
610 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
611 // values correspond to the "Part number" in the CP15/c0 register. The
612 // contents are specified in the various processor manuals.
613 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
614 .Case("0x926", "arm926ej-s")
615 .Case("0xb02", "mpcore")
616 .Case("0xb36", "arm1136j-s")
617 .Case("0xb56", "arm1156t2-s")
618 .Case("0xb76", "arm1176jz-s")
619 .Case("0xc08", "cortex-a8")
620 .Case("0xc09", "cortex-a9")
621 .Case("0xc0f", "cortex-a15")
622 .Case("0xc20", "cortex-m0")
623 .Case("0xc23", "cortex-m3")
624 .Case("0xc24", "cortex-m4")
627 if (Implementer == "0x51") // Qualcomm Technologies, Inc.
628 // Look for the CPU part line.
629 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
630 if (Lines[I].startswith("CPU part"))
631 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
632 // values correspond to the "Part number" in the CP15/c0 register. The
633 // contents are specified in the various processor manuals.
634 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
635 .Case("0x06f", "krait") // APQ8064
640 #elif defined(__linux__) && defined(__s390x__)
641 StringRef sys::getHostCPUName() {
642 // STIDP is a privileged operation, so use /proc/cpuinfo instead.
643 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
644 // memory buffer because the 'file' has 0 size (it can be read from only
648 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
650 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
654 // The "processor 0:" line comes after a fair amount of other information,
655 // including a cache breakdown, but this should be plenty.
657 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
660 StringRef Str(buffer, CPUInfoSize);
661 SmallVector<StringRef, 32> Lines;
662 Str.split(Lines, "\n");
663 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
664 if (Lines[I].startswith("processor ")) {
665 size_t Pos = Lines[I].find("machine = ");
666 if (Pos != StringRef::npos) {
667 Pos += sizeof("machine = ") - 1;
669 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
683 StringRef sys::getHostCPUName() {
688 #if defined(__linux__) && defined(__arm__)
689 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
691 DataStreamer *DS = getDataFileStreamer("/proc/cpuinfo", &Err);
693 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << Err << "\n");
697 // Read 1024 bytes from /proc/cpuinfo, which should contain the Features line
700 size_t CPUInfoSize = DS->GetBytes((unsigned char*) buffer, sizeof(buffer));
703 StringRef Str(buffer, CPUInfoSize);
705 SmallVector<StringRef, 32> Lines;
706 Str.split(Lines, "\n");
708 SmallVector<StringRef, 32> CPUFeatures;
710 // Look for the CPU features.
711 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
712 if (Lines[I].startswith("Features")) {
713 Lines[I].split(CPUFeatures, " ");
717 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
718 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
719 .Case("half", "fp16")
720 .Case("neon", "neon")
721 .Case("vfpv3", "vfp3")
722 .Case("vfpv3d16", "d16")
723 .Case("vfpv4", "vfp4")
724 .Case("idiva", "hwdiv-arm")
725 .Case("idivt", "hwdiv")
728 if (LLVMFeatureStr != "")
729 Features.GetOrCreateValue(LLVMFeatureStr).setValue(true);
735 bool sys::getHostCPUFeatures(StringMap<bool> &Features){
740 std::string sys::getProcessTriple() {
741 Triple PT(Triple::normalize(LLVM_HOST_TRIPLE));
743 if (sizeof(void *) == 8 && PT.isArch32Bit())
744 PT = PT.get64BitArchVariant();
745 if (sizeof(void *) == 4 && PT.isArch64Bit())
746 PT = PT.get32BitArchVariant();