1 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the operating system Host concept.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Support/Host.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/Config/config.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/FileSystem.h"
22 #include "llvm/Support/raw_ostream.h"
25 // Include the platform-specific parts of this class.
27 #include "Unix/Host.inc"
30 #include "Windows/Host.inc"
35 #if defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
36 #include <mach/mach.h>
37 #include <mach/mach_host.h>
38 #include <mach/host_info.h>
39 #include <mach/machine.h>
42 #define DEBUG_TYPE "host-detection"
44 //===----------------------------------------------------------------------===//
46 // Implementations of the CPU detection routines
48 //===----------------------------------------------------------------------===//
52 #if defined(__linux__)
53 static ssize_t LLVM_ATTRIBUTE_UNUSED readCpuInfo(void *Buf, size_t Size) {
54 // Note: We cannot mmap /proc/cpuinfo here and then process the resulting
55 // memory buffer because the 'file' has 0 size (it can be read from only
59 std::error_code EC = sys::fs::openFileForRead("/proc/cpuinfo", FD);
61 DEBUG(dbgs() << "Unable to open /proc/cpuinfo: " << EC.message() << "\n");
64 int Ret = read(FD, Buf, Size);
65 int CloseStatus = close(FD);
72 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
73 || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
75 /// GetX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in the
76 /// specified arguments. If we can't run cpuid on the host, return true.
77 static bool GetX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
78 unsigned *rECX, unsigned *rEDX) {
79 #if defined(__GNUC__) || defined(__clang__)
80 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
81 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
82 asm ("movq\t%%rbx, %%rsi\n\t"
84 "xchgq\t%%rbx, %%rsi\n\t"
91 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
92 asm ("movl\t%%ebx, %%esi\n\t"
94 "xchgl\t%%ebx, %%esi\n\t"
101 // pedantic #else returns to appease -Wunreachable-code (so we don't generate
102 // postprocessed code that looks like "return true; return false;")
106 #elif defined(_MSC_VER)
107 // The MSVC intrinsic is portable across x86 and x64.
109 __cpuid(registers, value);
110 *rEAX = registers[0];
111 *rEBX = registers[1];
112 *rECX = registers[2];
113 *rEDX = registers[3];
120 /// GetX86CpuIDAndInfoEx - Execute the specified cpuid with subleaf and return the
121 /// 4 values in the specified arguments. If we can't run cpuid on the host,
123 static bool GetX86CpuIDAndInfoEx(unsigned value, unsigned subleaf,
124 unsigned *rEAX, unsigned *rEBX, unsigned *rECX,
126 #if defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
127 #if defined(__GNUC__)
128 // gcc doesn't know cpuid would clobber ebx/rbx. Preseve it manually.
129 asm ("movq\t%%rbx, %%rsi\n\t"
131 "xchgq\t%%rbx, %%rsi\n\t"
139 #elif defined(_MSC_VER)
141 __cpuidex(registers, value, subleaf);
142 *rEAX = registers[0];
143 *rEBX = registers[1];
144 *rECX = registers[2];
145 *rEDX = registers[3];
150 #elif defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)
151 #if defined(__GNUC__)
152 asm ("movl\t%%ebx, %%esi\n\t"
154 "xchgl\t%%ebx, %%esi\n\t"
162 #elif defined(_MSC_VER)
168 mov dword ptr [esi],eax
170 mov dword ptr [esi],ebx
172 mov dword ptr [esi],ecx
174 mov dword ptr [esi],edx
185 static bool OSHasAVXSupport() {
186 #if defined(__GNUC__)
187 // Check xgetbv; this uses a .byte sequence instead of the instruction
188 // directly because older assemblers do not include support for xgetbv and
189 // there is no easy way to conditionally compile based on the assembler used.
191 __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
192 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
193 unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
195 int rEAX = 0; // Ensures we return false
197 return (rEAX & 6) == 6;
200 static void DetectX86FamilyModel(unsigned EAX, unsigned &Family,
202 Family = (EAX >> 8) & 0xf; // Bits 8 - 11
203 Model = (EAX >> 4) & 0xf; // Bits 4 - 7
204 if (Family == 6 || Family == 0xf) {
206 // Examine extended family ID if family ID is F.
207 Family += (EAX >> 20) & 0xff; // Bits 20 - 27
208 // Examine extended model ID if family ID is 6 or F.
209 Model += ((EAX >> 16) & 0xf) << 4; // Bits 16 - 19
213 StringRef sys::getHostCPUName() {
214 unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
215 if (GetX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
219 DetectX86FamilyModel(EAX, Family, Model);
226 GetX86CpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
228 unsigned MaxLeaf = EAX;
229 bool HasSSE3 = (ECX & 0x1);
230 bool HasSSE41 = (ECX & 0x80000);
231 // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
232 // indicates that the AVX registers will be saved and restored on context
233 // switch, then we have full AVX support.
234 const unsigned AVXBits = (1 << 27) | (1 << 28);
235 bool HasAVX = ((ECX & AVXBits) == AVXBits) && OSHasAVXSupport();
236 bool HasAVX2 = HasAVX && MaxLeaf >= 0x7 &&
237 !GetX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX) &&
239 GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
240 bool Em64T = (EDX >> 29) & 0x1;
241 bool HasTBM = (ECX >> 21) & 0x1;
243 if (memcmp(text.c, "GenuineIntel", 12) == 0) {
249 case 0: // Intel486 DX processors
250 case 1: // Intel486 DX processors
251 case 2: // Intel486 SX processors
252 case 3: // Intel487 processors, IntelDX2 OverDrive processors,
253 // IntelDX2 processors
254 case 4: // Intel486 SL processor
255 case 5: // IntelSX2 processors
256 case 7: // Write-Back Enhanced IntelDX2 processors
257 case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
258 default: return "i486";
262 case 1: // Pentium OverDrive processor for Pentium processor (60, 66),
263 // Pentium processors (60, 66)
264 case 2: // Pentium OverDrive processor for Pentium processor (75, 90,
265 // 100, 120, 133), Pentium processors (75, 90, 100, 120, 133,
267 case 3: // Pentium OverDrive processors for Intel486 processor-based
271 case 4: // Pentium OverDrive processor with MMX technology for Pentium
272 // processor (75, 90, 100, 120, 133), Pentium processor with
273 // MMX technology (166, 200)
274 return "pentium-mmx";
276 default: return "pentium";
280 case 1: // Pentium Pro processor
283 case 3: // Intel Pentium II OverDrive processor, Pentium II processor,
285 case 5: // Pentium II processor, model 05, Pentium II Xeon processor,
286 // model 05, and Intel Celeron processor, model 05
287 case 6: // Celeron processor, model 06
290 case 7: // Pentium III processor, model 07, and Pentium III Xeon
291 // processor, model 07
292 case 8: // Pentium III processor, model 08, Pentium III Xeon processor,
293 // model 08, and Celeron processor, model 08
294 case 10: // Pentium III Xeon processor, model 0Ah
295 case 11: // Pentium III processor, model 0Bh
298 case 9: // Intel Pentium M processor, Intel Celeron M processor model 09.
299 case 13: // Intel Pentium M processor, Intel Celeron M processor, model
300 // 0Dh. All processors are manufactured using the 90 nm process.
303 case 14: // Intel Core Duo processor, Intel Core Solo processor, model
304 // 0Eh. All processors are manufactured using the 65 nm process.
307 case 15: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
308 // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
309 // mobile processor, Intel Core 2 Extreme processor, Intel
310 // Pentium Dual-Core processor, Intel Xeon processor, model
311 // 0Fh. All processors are manufactured using the 65 nm process.
312 case 22: // Intel Celeron processor model 16h. All processors are
313 // manufactured using the 65 nm process
316 case 21: // Intel EP80579 Integrated Processor and Intel EP80579
317 // Integrated Processor with Intel QuickAssist Technology
318 return "i686"; // FIXME: ???
320 case 23: // Intel Core 2 Extreme processor, Intel Xeon processor, model
321 // 17h. All processors are manufactured using the 45 nm process.
323 // 45nm: Penryn , Wolfdale, Yorkfield (XE)
324 // Not all Penryn processors support SSE 4.1 (such as the Pentium brand)
325 return HasSSE41 ? "penryn" : "core2";
327 case 26: // Intel Core i7 processor and Intel Xeon processor. All
328 // processors are manufactured using the 45 nm process.
329 case 29: // Intel Xeon processor MP. All processors are manufactured using
330 // the 45 nm process.
331 case 30: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
332 // As found in a Summer 2010 model iMac.
333 case 37: // Intel Core i7, laptop version.
334 case 44: // Intel Core i7 processor and Intel Xeon processor. All
335 // processors are manufactured using the 32 nm process.
336 case 46: // Nehalem EX
337 case 47: // Westmere EX
341 case 42: // Intel Core i7 processor. All processors are manufactured
342 // using the 32 nm process.
344 // Not all Sandy Bridge processors support AVX (such as the Pentium
345 // versions instead of the i7 versions).
346 return HasAVX ? "corei7-avx" : "corei7";
350 case 62: // Ivy Bridge EP
351 // Not all Ivy Bridge processors support AVX (such as the Pentium
352 // versions instead of the i7 versions).
353 return HasAVX ? "core-avx-i" : "corei7";
360 // Not all Haswell processors support AVX too (such as the Pentium
361 // versions instead of the i7 versions).
362 return HasAVX2 ? "core-avx2" : "corei7";
366 // Not all Broadwell processors support AVX too (such as the Pentium
367 // versions instead of the i7 versions).
368 return HasAVX2 ? "broadwell" : "corei7";
370 case 28: // Most 45 nm Intel Atom processors
371 case 38: // 45 nm Atom Lincroft
372 case 39: // 32 nm Atom Medfield
373 case 53: // 32 nm Atom Midview
374 case 54: // 32 nm Atom Midview
377 // Atom Silvermont codes from the Intel software optimization guide.
383 default: return (Em64T) ? "x86-64" : "i686";
387 case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
388 // model 00h and manufactured using the 0.18 micron process.
389 case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
390 // processor MP, and Intel Celeron processor. All processors are
391 // model 01h and manufactured using the 0.18 micron process.
392 case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
393 // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
394 // processor, and Mobile Intel Celeron processor. All processors
395 // are model 02h and manufactured using the 0.13 micron process.
396 return (Em64T) ? "x86-64" : "pentium4";
398 case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
399 // processor. All processors are model 03h and manufactured using
400 // the 90 nm process.
401 case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
402 // Pentium D processor, Intel Xeon processor, Intel Xeon
403 // processor MP, Intel Celeron D processor. All processors are
404 // model 04h and manufactured using the 90 nm process.
405 case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
406 // Extreme Edition, Intel Xeon processor, Intel Xeon processor
407 // MP, Intel Celeron D processor. All processors are model 06h
408 // and manufactured using the 65 nm process.
409 return (Em64T) ? "nocona" : "prescott";
412 return (Em64T) ? "x86-64" : "pentium4";
419 } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
420 // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
421 // appears to be no way to generate the wide variety of AMD-specific targets
422 // from the information returned from CPUID.
430 case 8: return "k6-2";
432 case 13: return "k6-3";
433 case 10: return "geode";
434 default: return "pentium";
438 case 4: return "athlon-tbird";
441 case 8: return "athlon-mp";
442 case 10: return "athlon-xp";
443 default: return "athlon";
449 case 1: return "opteron";
450 case 5: return "athlon-fx"; // also opteron
451 default: return "athlon64";
458 if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
461 return "bdver4"; // 50h-6Fh: Excavator
463 return "bdver3"; // 30h-3Fh: Steamroller
464 if (Model >= 0x10 || HasTBM)
465 return "bdver2"; // 10h-1Fh: Piledriver
466 return "bdver1"; // 00h-0Fh: Bulldozer
468 if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
477 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
478 StringRef sys::getHostCPUName() {
479 host_basic_info_data_t hostInfo;
480 mach_msg_type_number_t infoCount;
482 infoCount = HOST_BASIC_INFO_COUNT;
483 host_info(mach_host_self(), HOST_BASIC_INFO, (host_info_t)&hostInfo,
486 if (hostInfo.cpu_type != CPU_TYPE_POWERPC) return "generic";
488 switch(hostInfo.cpu_subtype) {
489 case CPU_SUBTYPE_POWERPC_601: return "601";
490 case CPU_SUBTYPE_POWERPC_602: return "602";
491 case CPU_SUBTYPE_POWERPC_603: return "603";
492 case CPU_SUBTYPE_POWERPC_603e: return "603e";
493 case CPU_SUBTYPE_POWERPC_603ev: return "603ev";
494 case CPU_SUBTYPE_POWERPC_604: return "604";
495 case CPU_SUBTYPE_POWERPC_604e: return "604e";
496 case CPU_SUBTYPE_POWERPC_620: return "620";
497 case CPU_SUBTYPE_POWERPC_750: return "750";
498 case CPU_SUBTYPE_POWERPC_7400: return "7400";
499 case CPU_SUBTYPE_POWERPC_7450: return "7450";
500 case CPU_SUBTYPE_POWERPC_970: return "970";
506 #elif defined(__linux__) && (defined(__ppc__) || defined(__powerpc__))
507 StringRef sys::getHostCPUName() {
508 // Access to the Processor Version Register (PVR) on PowerPC is privileged,
509 // and so we must use an operating-system interface to determine the current
510 // processor type. On Linux, this is exposed through the /proc/cpuinfo file.
511 const char *generic = "generic";
513 // The cpu line is second (after the 'processor: 0' line), so if this
514 // buffer is too small then something has changed (or is wrong).
516 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
517 if (CPUInfoSize == -1)
520 const char *CPUInfoStart = buffer;
521 const char *CPUInfoEnd = buffer + CPUInfoSize;
523 const char *CIP = CPUInfoStart;
525 const char *CPUStart = 0;
528 // We need to find the first line which starts with cpu, spaces, and a colon.
529 // After the colon, there may be some additional spaces and then the cpu type.
530 while (CIP < CPUInfoEnd && CPUStart == 0) {
531 if (CIP < CPUInfoEnd && *CIP == '\n')
534 if (CIP < CPUInfoEnd && *CIP == 'c') {
536 if (CIP < CPUInfoEnd && *CIP == 'p') {
538 if (CIP < CPUInfoEnd && *CIP == 'u') {
540 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
543 if (CIP < CPUInfoEnd && *CIP == ':') {
545 while (CIP < CPUInfoEnd && (*CIP == ' ' || *CIP == '\t'))
548 if (CIP < CPUInfoEnd) {
550 while (CIP < CPUInfoEnd && (*CIP != ' ' && *CIP != '\t' &&
551 *CIP != ',' && *CIP != '\n'))
553 CPULen = CIP - CPUStart;
561 while (CIP < CPUInfoEnd && *CIP != '\n')
568 return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
569 .Case("604e", "604e")
571 .Case("7400", "7400")
572 .Case("7410", "7400")
573 .Case("7447", "7400")
574 .Case("7455", "7450")
576 .Case("POWER4", "970")
577 .Case("PPC970FX", "970")
578 .Case("PPC970MP", "970")
580 .Case("POWER5", "g5")
582 .Case("POWER6", "pwr6")
583 .Case("POWER7", "pwr7")
584 .Case("POWER8", "pwr8")
585 .Case("POWER8E", "pwr8")
588 #elif defined(__linux__) && defined(__arm__)
589 StringRef sys::getHostCPUName() {
590 // The cpuid register on arm is not accessible from user space. On Linux,
591 // it is exposed through the /proc/cpuinfo file.
593 // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line
596 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
597 if (CPUInfoSize == -1)
600 StringRef Str(buffer, CPUInfoSize);
602 SmallVector<StringRef, 32> Lines;
603 Str.split(Lines, "\n");
605 // Look for the CPU implementer line.
606 StringRef Implementer;
607 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
608 if (Lines[I].startswith("CPU implementer"))
609 Implementer = Lines[I].substr(15).ltrim("\t :");
611 if (Implementer == "0x41") // ARM Ltd.
612 // Look for the CPU part line.
613 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
614 if (Lines[I].startswith("CPU part"))
615 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
616 // values correspond to the "Part number" in the CP15/c0 register. The
617 // contents are specified in the various processor manuals.
618 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
619 .Case("0x926", "arm926ej-s")
620 .Case("0xb02", "mpcore")
621 .Case("0xb36", "arm1136j-s")
622 .Case("0xb56", "arm1156t2-s")
623 .Case("0xb76", "arm1176jz-s")
624 .Case("0xc08", "cortex-a8")
625 .Case("0xc09", "cortex-a9")
626 .Case("0xc0f", "cortex-a15")
627 .Case("0xc20", "cortex-m0")
628 .Case("0xc23", "cortex-m3")
629 .Case("0xc24", "cortex-m4")
632 if (Implementer == "0x51") // Qualcomm Technologies, Inc.
633 // Look for the CPU part line.
634 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
635 if (Lines[I].startswith("CPU part"))
636 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
637 // values correspond to the "Part number" in the CP15/c0 register. The
638 // contents are specified in the various processor manuals.
639 return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
640 .Case("0x06f", "krait") // APQ8064
645 #elif defined(__linux__) && defined(__s390x__)
646 StringRef sys::getHostCPUName() {
647 // STIDP is a privileged operation, so use /proc/cpuinfo instead.
649 // The "processor 0:" line comes after a fair amount of other information,
650 // including a cache breakdown, but this should be plenty.
652 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
653 if (CPUInfoSize == -1)
656 StringRef Str(buffer, CPUInfoSize);
657 SmallVector<StringRef, 32> Lines;
658 Str.split(Lines, "\n");
659 for (unsigned I = 0, E = Lines.size(); I != E; ++I) {
660 if (Lines[I].startswith("processor ")) {
661 size_t Pos = Lines[I].find("machine = ");
662 if (Pos != StringRef::npos) {
663 Pos += sizeof("machine = ") - 1;
665 if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) {
679 StringRef sys::getHostCPUName() {
684 #if defined(__linux__) && (defined(__arm__) || defined(__aarch64__))
685 bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
686 // Read 1024 bytes from /proc/cpuinfo, which should contain the Features line
689 ssize_t CPUInfoSize = readCpuInfo(buffer, sizeof(buffer));
690 if (CPUInfoSize == -1)
693 StringRef Str(buffer, CPUInfoSize);
695 SmallVector<StringRef, 32> Lines;
696 Str.split(Lines, "\n");
698 SmallVector<StringRef, 32> CPUFeatures;
700 // Look for the CPU features.
701 for (unsigned I = 0, E = Lines.size(); I != E; ++I)
702 if (Lines[I].startswith("Features")) {
703 Lines[I].split(CPUFeatures, " ");
707 #if defined(__aarch64__)
708 // Keep track of which crypto features we have seen
718 for (unsigned I = 0, E = CPUFeatures.size(); I != E; ++I) {
719 StringRef LLVMFeatureStr = StringSwitch<StringRef>(CPUFeatures[I])
720 #if defined(__aarch64__)
721 .Case("asimd", "neon")
722 .Case("fp", "fp-armv8")
723 .Case("crc32", "crc")
725 .Case("half", "fp16")
726 .Case("neon", "neon")
727 .Case("vfpv3", "vfp3")
728 .Case("vfpv3d16", "d16")
729 .Case("vfpv4", "vfp4")
730 .Case("idiva", "hwdiv-arm")
731 .Case("idivt", "hwdiv")
735 #if defined(__aarch64__)
736 // We need to check crypto separately since we need all of the crypto
737 // extensions to enable the subtarget feature
738 if (CPUFeatures[I] == "aes")
740 else if (CPUFeatures[I] == "pmull")
742 else if (CPUFeatures[I] == "sha1")
744 else if (CPUFeatures[I] == "sha2")
748 if (LLVMFeatureStr != "")
749 Features[LLVMFeatureStr] = true;
752 #if defined(__aarch64__)
753 // If we have all crypto bits we can add the feature
754 if (crypto == (CAP_AES | CAP_PMULL | CAP_SHA1 | CAP_SHA2))
755 Features["crypto"] = true;
761 bool sys::getHostCPUFeatures(StringMap<bool> &Features){
766 std::string sys::getProcessTriple() {
767 Triple PT(Triple::normalize(LLVM_HOST_TRIPLE));
769 if (sizeof(void *) == 8 && PT.isArch32Bit())
770 PT = PT.get64BitArchVariant();
771 if (sizeof(void *) == 4 && PT.isArch64Bit())
772 PT = PT.get32BitArchVariant();