1 //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the VirtRegMap class.
12 // It also contains implementations of the Spiller interface, which, given a
13 // virtual register map and a machine function, eliminates all virtual
14 // references by replacing them with physical register references - adding spill
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "virtregmap"
20 #include "VirtRegMap.h"
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SlotIndexes.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetInstrInfo.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/ADT/BitVector.h"
36 #include "llvm/ADT/DenseMap.h"
37 #include "llvm/ADT/DepthFirstIterator.h"
38 #include "llvm/ADT/Statistic.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/ADT/SmallSet.h"
44 STATISTIC(NumSpillSlots, "Number of spill slots allocated");
45 STATISTIC(NumIdCopies, "Number of identity moves eliminated after rewriting");
47 //===----------------------------------------------------------------------===//
48 // VirtRegMap implementation
49 //===----------------------------------------------------------------------===//
51 char VirtRegMap::ID = 0;
53 INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
55 bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
56 MRI = &mf.getRegInfo();
57 TII = mf.getTarget().getInstrInfo();
58 TRI = mf.getTarget().getRegisterInfo();
62 Virt2StackSlotMap.clear();
63 Virt2SplitMap.clear();
65 allocatableRCRegs.clear();
66 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
67 E = TRI->regclass_end(); I != E; ++I)
68 allocatableRCRegs.insert(std::make_pair(*I,
69 TRI->getAllocatableSet(mf, *I)));
76 void VirtRegMap::grow() {
77 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
78 Virt2PhysMap.resize(NumRegs);
79 Virt2StackSlotMap.resize(NumRegs);
80 Virt2SplitMap.resize(NumRegs);
83 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
84 int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
90 unsigned VirtRegMap::getRegAllocPref(unsigned virtReg) {
91 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(virtReg);
92 unsigned physReg = Hint.second;
93 if (TargetRegisterInfo::isVirtualRegister(physReg) && hasPhys(physReg))
94 physReg = getPhys(physReg);
96 return (TargetRegisterInfo::isPhysicalRegister(physReg))
98 return TRI->ResolveRegAllocHint(Hint.first, physReg, *MF);
101 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
102 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
103 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
104 "attempt to assign stack slot to already spilled register");
105 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
106 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
109 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
110 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
111 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
112 "attempt to assign stack slot to already spilled register");
114 (SS >= MF->getFrameInfo()->getObjectIndexBegin())) &&
115 "illegal fixed frame index");
116 Virt2StackSlotMap[virtReg] = SS;
119 void VirtRegMap::rewrite(SlotIndexes *Indexes) {
120 DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
121 << "********** Function: "
122 << MF->getFunction()->getName() << '\n');
124 SmallVector<unsigned, 8> SuperDeads;
125 SmallVector<unsigned, 8> SuperDefs;
126 SmallVector<unsigned, 8> SuperKills;
128 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
129 MBBI != MBBE; ++MBBI) {
130 DEBUG(MBBI->print(dbgs(), Indexes));
131 for (MachineBasicBlock::iterator MII = MBBI->begin(), MIE = MBBI->end();
133 MachineInstr *MI = MII;
136 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
137 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
138 MachineOperand &MO = *MOI;
139 if (!MO.isReg() || !TargetRegisterInfo::isVirtualRegister(MO.getReg()))
141 unsigned VirtReg = MO.getReg();
142 unsigned PhysReg = getPhys(VirtReg);
143 assert(PhysReg != NO_PHYS_REG && "Instruction uses unmapped VirtReg");
145 // Preserve semantics of sub-register operands.
146 if (MO.getSubReg()) {
147 // A virtual register kill refers to the whole register, so we may
148 // have to add <imp-use,kill> operands for the super-register. A
149 // partial redef always kills and redefines the super-register.
150 if (MO.readsReg() && (MO.isDef() || MO.isKill()))
151 SuperKills.push_back(PhysReg);
154 // The <def,undef> flag only makes sense for sub-register defs, and
155 // we are substituting a full physreg. An <imp-use,kill> operand
156 // from the SuperKills list will represent the partial read of the
158 MO.setIsUndef(false);
160 // Also add implicit defs for the super-register.
162 SuperDeads.push_back(PhysReg);
164 SuperDefs.push_back(PhysReg);
167 // PhysReg operands cannot have subregister indexes.
168 PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg());
169 assert(PhysReg && "Invalid SubReg for physical register");
172 // Rewrite. Note we could have used MachineOperand::substPhysReg(), but
173 // we need the inlining here.
177 // Add any missing super-register kills after rewriting the whole
179 while (!SuperKills.empty())
180 MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
182 while (!SuperDeads.empty())
183 MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
185 while (!SuperDefs.empty())
186 MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
188 DEBUG(dbgs() << "> " << *MI);
190 // Finally, remove any identity copies.
191 if (MI->isIdentityCopy()) {
193 if (MI->getNumOperands() == 2) {
194 DEBUG(dbgs() << "Deleting identity copy.\n");
196 Indexes->removeMachineInstrFromMaps(MI);
197 // It's safe to erase MI because MII has already been incremented.
198 MI->eraseFromParent();
200 // Transform identity copy to a KILL to deal with subregisters.
201 MI->setDesc(TII->get(TargetOpcode::KILL));
202 DEBUG(dbgs() << "Identity copy: " << *MI);
208 // Tell MRI about physical registers in use.
209 for (unsigned Reg = 1, RegE = TRI->getNumRegs(); Reg != RegE; ++Reg)
210 if (!MRI->reg_nodbg_empty(Reg))
211 MRI->setPhysRegUsed(Reg);
214 void VirtRegMap::print(raw_ostream &OS, const Module* M) const {
215 const TargetRegisterInfo* TRI = MF->getTarget().getRegisterInfo();
216 const MachineRegisterInfo &MRI = MF->getRegInfo();
218 OS << "********** REGISTER MAP **********\n";
219 for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
220 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
221 if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
222 OS << '[' << PrintReg(Reg, TRI) << " -> "
223 << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
224 << MRI.getRegClass(Reg)->getName() << "\n";
228 for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
229 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
230 if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
231 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
232 << "] " << MRI.getRegClass(Reg)->getName() << "\n";
238 void VirtRegMap::dump() const {