1 //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the VirtRegMap class.
12 // It also contains implementations of the Spiller interface, which, given a
13 // virtual register map and a machine function, eliminates all virtual
14 // references by replacing them with physical register references - adding spill
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "virtregmap"
20 #include "VirtRegMap.h"
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/BitVector.h"
35 #include "llvm/ADT/DenseMap.h"
36 #include "llvm/ADT/DepthFirstIterator.h"
37 #include "llvm/ADT/Statistic.h"
38 #include "llvm/ADT/STLExtras.h"
39 #include "llvm/ADT/SmallSet.h"
43 STATISTIC(NumSpills , "Number of register spills");
45 //===----------------------------------------------------------------------===//
46 // VirtRegMap implementation
47 //===----------------------------------------------------------------------===//
49 char VirtRegMap::ID = 0;
51 INITIALIZE_PASS(VirtRegMap, "virtregmap", "Virtual Register Map", false, false)
53 bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
54 MRI = &mf.getRegInfo();
55 TII = mf.getTarget().getInstrInfo();
56 TRI = mf.getTarget().getRegisterInfo();
59 ReMatId = MAX_STACK_SLOT+1;
60 LowSpillSlot = HighSpillSlot = NO_STACK_SLOT;
63 Virt2StackSlotMap.clear();
64 Virt2ReMatIdMap.clear();
65 Virt2SplitMap.clear();
66 Virt2SplitKillMap.clear();
68 ImplicitDefed.clear();
69 SpillSlotToUsesMap.clear();
71 SpillPt2VirtMap.clear();
72 RestorePt2VirtMap.clear();
73 EmergencySpillMap.clear();
74 EmergencySpillSlots.clear();
76 SpillSlotToUsesMap.resize(8);
77 ImplicitDefed.resize(MF->getRegInfo().getNumVirtRegs());
79 allocatableRCRegs.clear();
80 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
81 E = TRI->regclass_end(); I != E; ++I)
82 allocatableRCRegs.insert(std::make_pair(*I,
83 TRI->getAllocatableSet(mf, *I)));
90 void VirtRegMap::grow() {
91 unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg();
92 Virt2PhysMap.grow(LastVirtReg);
93 Virt2StackSlotMap.grow(LastVirtReg);
94 Virt2ReMatIdMap.grow(LastVirtReg);
95 Virt2SplitMap.grow(LastVirtReg);
96 Virt2SplitKillMap.grow(LastVirtReg);
97 ReMatMap.grow(LastVirtReg);
98 ImplicitDefed.resize(MF->getRegInfo().getNumVirtRegs());
101 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
102 int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
104 if (LowSpillSlot == NO_STACK_SLOT)
106 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
108 assert(SS >= LowSpillSlot && "Unexpected low spill slot");
109 unsigned Idx = SS-LowSpillSlot;
110 while (Idx >= SpillSlotToUsesMap.size())
111 SpillSlotToUsesMap.resize(SpillSlotToUsesMap.size()*2);
115 unsigned VirtRegMap::getRegAllocPref(unsigned virtReg) {
116 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(virtReg);
117 unsigned physReg = Hint.second;
119 TargetRegisterInfo::isVirtualRegister(physReg) && hasPhys(physReg))
120 physReg = getPhys(physReg);
122 return (physReg && TargetRegisterInfo::isPhysicalRegister(physReg))
124 return TRI->ResolveRegAllocHint(Hint.first, physReg, *MF);
127 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
128 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
129 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
130 "attempt to assign stack slot to already spilled register");
131 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
133 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
136 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
137 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
138 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
139 "attempt to assign stack slot to already spilled register");
141 (SS >= MF->getFrameInfo()->getObjectIndexBegin())) &&
142 "illegal fixed frame index");
143 Virt2StackSlotMap[virtReg] = SS;
146 int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
147 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
148 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
149 "attempt to assign re-mat id to already spilled register");
150 Virt2ReMatIdMap[virtReg] = ReMatId;
154 void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) {
155 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
156 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
157 "attempt to assign re-mat id to already spilled register");
158 Virt2ReMatIdMap[virtReg] = id;
161 int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) {
162 std::map<const TargetRegisterClass*, int>::iterator I =
163 EmergencySpillSlots.find(RC);
164 if (I != EmergencySpillSlots.end())
166 return EmergencySpillSlots[RC] = createSpillSlot(RC);
169 void VirtRegMap::addSpillSlotUse(int FI, MachineInstr *MI) {
170 if (!MF->getFrameInfo()->isFixedObjectIndex(FI)) {
171 // If FI < LowSpillSlot, this stack reference was produced by
172 // instruction selection and is not a spill
173 if (FI >= LowSpillSlot) {
174 assert(FI >= 0 && "Spill slot index should not be negative!");
175 assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
176 && "Invalid spill slot");
177 SpillSlotToUsesMap[FI-LowSpillSlot].insert(MI);
182 void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
183 MachineInstr *NewMI, ModRef MRInfo) {
184 // Move previous memory references folded to new instruction.
185 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
186 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
187 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
188 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
189 MI2VirtMap.erase(I++);
192 // add new memory reference
193 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
196 void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) {
197 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(MI);
198 MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo)));
201 void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) {
202 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
203 MachineOperand &MO = MI->getOperand(i);
206 int FI = MO.getIndex();
207 if (MF->getFrameInfo()->isFixedObjectIndex(FI))
209 // This stack reference was produced by instruction selection and
211 if (FI < LowSpillSlot)
213 assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
214 && "Invalid spill slot");
215 SpillSlotToUsesMap[FI-LowSpillSlot].erase(MI);
217 MI2VirtMap.erase(MI);
218 SpillPt2VirtMap.erase(MI);
219 RestorePt2VirtMap.erase(MI);
220 EmergencySpillMap.erase(MI);
223 /// FindUnusedRegisters - Gather a list of allocatable registers that
224 /// have not been allocated to any virtual register.
225 bool VirtRegMap::FindUnusedRegisters(LiveIntervals* LIs) {
226 unsigned NumRegs = TRI->getNumRegs();
228 UnusedRegs.resize(NumRegs);
230 BitVector Used(NumRegs);
231 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
232 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
233 if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG)
234 Used.set(Virt2PhysMap[Reg]);
237 BitVector Allocatable = TRI->getAllocatableSet(*MF);
238 bool AnyUnused = false;
239 for (unsigned Reg = 1; Reg < NumRegs; ++Reg) {
240 if (Allocatable[Reg] && !Used[Reg] && !LIs->hasInterval(Reg)) {
241 bool ReallyUnused = true;
242 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
243 if (Used[*AS] || LIs->hasInterval(*AS)) {
244 ReallyUnused = false;
258 void VirtRegMap::print(raw_ostream &OS, const Module* M) const {
259 const TargetRegisterInfo* TRI = MF->getTarget().getRegisterInfo();
260 const MachineRegisterInfo &MRI = MF->getRegInfo();
262 OS << "********** REGISTER MAP **********\n";
263 for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
264 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
265 if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
266 OS << '[' << PrintReg(Reg, TRI) << " -> "
267 << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
268 << MRI.getRegClass(Reg)->getName() << "\n";
272 for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
273 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
274 if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
275 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
276 << "] " << MRI.getRegClass(Reg)->getName() << "\n";
282 void VirtRegMap::dump() const {