1 //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the VirtRegMap class.
12 // It also contains implementations of the the Spiller interface, which, given a
13 // virtual register map and a machine function, eliminates all virtual
14 // references by replacing them with physical register references - adding spill
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "spiller"
20 #include "VirtRegMap.h"
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/ADT/BitVector.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/DepthFirstIterator.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/STLExtras.h"
36 #include "llvm/ADT/SmallSet.h"
40 STATISTIC(NumSpills , "Number of register spills");
41 STATISTIC(NumPSpills , "Number of physical register spills");
42 STATISTIC(NumReMats , "Number of re-materialization");
43 STATISTIC(NumDRM , "Number of re-materializable defs elided");
44 STATISTIC(NumStores , "Number of stores added");
45 STATISTIC(NumLoads , "Number of loads added");
46 STATISTIC(NumReused , "Number of values reused");
47 STATISTIC(NumDSE , "Number of dead stores elided");
48 STATISTIC(NumDCE , "Number of copies elided");
49 STATISTIC(NumDSS , "Number of dead spill slots removed");
50 STATISTIC(NumCommutes, "Number of instructions commuted");
51 STATISTIC(NumOmitted , "Number of reloads omited");
52 STATISTIC(NumCopified, "Number of available reloads turned into copies");
55 enum SpillerName { simple, local };
58 static cl::opt<SpillerName>
60 cl::desc("Spiller to use: (default: local)"),
62 cl::values(clEnumVal(simple, "simple spiller"),
63 clEnumVal(local, "local spiller"),
67 //===----------------------------------------------------------------------===//
68 // VirtRegMap implementation
69 //===----------------------------------------------------------------------===//
71 VirtRegMap::VirtRegMap(MachineFunction &mf)
72 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
73 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT),
74 Virt2ReMatIdMap(NO_STACK_SLOT), Virt2SplitMap(0),
75 Virt2SplitKillMap(0), ReMatMap(NULL), ReMatId(MAX_STACK_SLOT+1),
76 LowSpillSlot(NO_STACK_SLOT), HighSpillSlot(NO_STACK_SLOT) {
77 SpillSlotToUsesMap.resize(8);
78 ImplicitDefed.resize(MF.getRegInfo().getLastVirtReg()+1-
79 TargetRegisterInfo::FirstVirtualRegister);
83 void VirtRegMap::grow() {
84 unsigned LastVirtReg = MF.getRegInfo().getLastVirtReg();
85 Virt2PhysMap.grow(LastVirtReg);
86 Virt2StackSlotMap.grow(LastVirtReg);
87 Virt2ReMatIdMap.grow(LastVirtReg);
88 Virt2SplitMap.grow(LastVirtReg);
89 Virt2SplitKillMap.grow(LastVirtReg);
90 ReMatMap.grow(LastVirtReg);
91 ImplicitDefed.resize(LastVirtReg-TargetRegisterInfo::FirstVirtualRegister+1);
94 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
95 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
96 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
97 "attempt to assign stack slot to already spilled register");
98 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(virtReg);
99 int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
101 if (LowSpillSlot == NO_STACK_SLOT)
103 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
105 unsigned Idx = SS-LowSpillSlot;
106 while (Idx >= SpillSlotToUsesMap.size())
107 SpillSlotToUsesMap.resize(SpillSlotToUsesMap.size()*2);
108 Virt2StackSlotMap[virtReg] = SS;
113 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
114 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
115 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
116 "attempt to assign stack slot to already spilled register");
118 (SS >= MF.getFrameInfo()->getObjectIndexBegin())) &&
119 "illegal fixed frame index");
120 Virt2StackSlotMap[virtReg] = SS;
123 int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
124 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
125 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
126 "attempt to assign re-mat id to already spilled register");
127 Virt2ReMatIdMap[virtReg] = ReMatId;
131 void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) {
132 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
133 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
134 "attempt to assign re-mat id to already spilled register");
135 Virt2ReMatIdMap[virtReg] = id;
138 int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) {
139 std::map<const TargetRegisterClass*, int>::iterator I =
140 EmergencySpillSlots.find(RC);
141 if (I != EmergencySpillSlots.end())
143 int SS = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
145 if (LowSpillSlot == NO_STACK_SLOT)
147 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
149 EmergencySpillSlots[RC] = SS;
153 void VirtRegMap::addSpillSlotUse(int FI, MachineInstr *MI) {
154 if (!MF.getFrameInfo()->isFixedObjectIndex(FI)) {
155 // If FI < LowSpillSlot, this stack reference was produced by
156 // instruction selection and is not a spill
157 if (FI >= LowSpillSlot) {
158 assert(FI >= 0 && "Spill slot index should not be negative!");
159 assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
160 && "Invalid spill slot");
161 SpillSlotToUsesMap[FI-LowSpillSlot].insert(MI);
166 void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
167 MachineInstr *NewMI, ModRef MRInfo) {
168 // Move previous memory references folded to new instruction.
169 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
170 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
171 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
172 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
173 MI2VirtMap.erase(I++);
176 // add new memory reference
177 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
180 void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) {
181 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(MI);
182 MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo)));
185 void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) {
186 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
187 MachineOperand &MO = MI->getOperand(i);
190 int FI = MO.getIndex();
191 if (MF.getFrameInfo()->isFixedObjectIndex(FI))
193 // This stack reference was produced by instruction selection and
195 if (FI < LowSpillSlot)
197 assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
198 && "Invalid spill slot");
199 SpillSlotToUsesMap[FI-LowSpillSlot].erase(MI);
201 MI2VirtMap.erase(MI);
202 SpillPt2VirtMap.erase(MI);
203 RestorePt2VirtMap.erase(MI);
204 EmergencySpillMap.erase(MI);
207 void VirtRegMap::print(std::ostream &OS) const {
208 const TargetRegisterInfo* TRI = MF.getTarget().getRegisterInfo();
210 OS << "********** REGISTER MAP **********\n";
211 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
212 e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) {
213 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
214 OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i])
218 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
219 e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i)
220 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
221 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
225 void VirtRegMap::dump() const {
230 //===----------------------------------------------------------------------===//
231 // Simple Spiller Implementation
232 //===----------------------------------------------------------------------===//
234 Spiller::~Spiller() {}
237 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
238 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
242 bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
243 DOUT << "********** REWRITE MACHINE CODE **********\n";
244 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
245 const TargetMachine &TM = MF.getTarget();
246 const TargetInstrInfo &TII = *TM.getInstrInfo();
247 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
250 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
251 // each vreg once (in the case where a spilled vreg is used by multiple
252 // operands). This is always smaller than the number of operands to the
253 // current machine instr, so it should be small.
254 std::vector<unsigned> LoadedRegs;
256 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
258 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
259 MachineBasicBlock &MBB = *MBBI;
260 for (MachineBasicBlock::iterator MII = MBB.begin(),
261 E = MBB.end(); MII != E; ++MII) {
262 MachineInstr &MI = *MII;
263 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
264 MachineOperand &MO = MI.getOperand(i);
265 if (MO.isReg() && MO.getReg()) {
266 if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
267 unsigned VirtReg = MO.getReg();
268 unsigned SubIdx = MO.getSubReg();
269 unsigned PhysReg = VRM.getPhys(VirtReg);
270 unsigned RReg = SubIdx ? TRI.getSubReg(PhysReg, SubIdx) : PhysReg;
271 if (!VRM.isAssignedReg(VirtReg)) {
272 int StackSlot = VRM.getStackSlot(VirtReg);
273 const TargetRegisterClass* RC =
274 MF.getRegInfo().getRegClass(VirtReg);
277 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
278 == LoadedRegs.end()) {
279 TII.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
280 MachineInstr *LoadMI = prior(MII);
281 VRM.addSpillSlotUse(StackSlot, LoadMI);
282 LoadedRegs.push_back(VirtReg);
284 DOUT << '\t' << *LoadMI;
288 TII.storeRegToStackSlot(MBB, next(MII), PhysReg, true,
290 MachineInstr *StoreMI = next(MII);
291 VRM.addSpillSlotUse(StackSlot, StoreMI);
295 MF.getRegInfo().setPhysRegUsed(RReg);
296 MI.getOperand(i).setReg(RReg);
298 MF.getRegInfo().setPhysRegUsed(MO.getReg());
310 //===----------------------------------------------------------------------===//
311 // Local Spiller Implementation
312 //===----------------------------------------------------------------------===//
314 /// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
315 /// top down, keep track of which spills slots or remat are available in each
318 /// Note that not all physregs are created equal here. In particular, some
319 /// physregs are reloads that we are allowed to clobber or ignore at any time.
320 /// Other physregs are values that the register allocated program is using that
321 /// we cannot CHANGE, but we can read if we like. We keep track of this on a
322 /// per-stack-slot / remat id basis as the low bit in the value of the
323 /// SpillSlotsAvailable entries. The predicate 'canClobberPhysReg()' checks
324 /// this bit and addAvailable sets it if.
326 class VISIBILITY_HIDDEN AvailableSpills {
327 const TargetRegisterInfo *TRI;
328 const TargetInstrInfo *TII;
330 // SpillSlotsOrReMatsAvailable - This map keeps track of all of the spilled
331 // or remat'ed virtual register values that are still available, due to being
332 // loaded or stored to, but not invalidated yet.
333 std::map<int, unsigned> SpillSlotsOrReMatsAvailable;
335 // PhysRegsAvailable - This is the inverse of SpillSlotsOrReMatsAvailable,
336 // indicating which stack slot values are currently held by a physreg. This
337 // is used to invalidate entries in SpillSlotsOrReMatsAvailable when a
338 // physreg is modified.
339 std::multimap<unsigned, int> PhysRegsAvailable;
341 void disallowClobberPhysRegOnly(unsigned PhysReg);
343 void ClobberPhysRegOnly(unsigned PhysReg);
345 AvailableSpills(const TargetRegisterInfo *tri, const TargetInstrInfo *tii)
346 : TRI(tri), TII(tii) {
349 /// clear - Reset the state.
351 SpillSlotsOrReMatsAvailable.clear();
352 PhysRegsAvailable.clear();
355 const TargetRegisterInfo *getRegInfo() const { return TRI; }
357 /// getSpillSlotOrReMatPhysReg - If the specified stack slot or remat is
358 /// available in a physical register, return that PhysReg, otherwise
360 unsigned getSpillSlotOrReMatPhysReg(int Slot) const {
361 std::map<int, unsigned>::const_iterator I =
362 SpillSlotsOrReMatsAvailable.find(Slot);
363 if (I != SpillSlotsOrReMatsAvailable.end()) {
364 return I->second >> 1; // Remove the CanClobber bit.
369 /// addAvailable - Mark that the specified stack slot / remat is available in
370 /// the specified physreg. If CanClobber is true, the physreg can be modified
371 /// at any time without changing the semantics of the program.
372 void addAvailable(int SlotOrReMat, unsigned Reg, bool CanClobber = true) {
373 // If this stack slot is thought to be available in some other physreg,
374 // remove its record.
375 ModifyStackSlotOrReMat(SlotOrReMat);
377 PhysRegsAvailable.insert(std::make_pair(Reg, SlotOrReMat));
378 SpillSlotsOrReMatsAvailable[SlotOrReMat]= (Reg << 1) | (unsigned)CanClobber;
380 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
381 DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1;
383 DOUT << "Remembering SS#" << SlotOrReMat;
384 DOUT << " in physreg " << TRI->getName(Reg) << "\n";
387 /// canClobberPhysReg - Return true if the spiller is allowed to change the
388 /// value of the specified stackslot register if it desires. The specified
389 /// stack slot must be available in a physreg for this query to make sense.
390 bool canClobberPhysReg(int SlotOrReMat) const {
391 assert(SpillSlotsOrReMatsAvailable.count(SlotOrReMat) &&
392 "Value not available!");
393 return SpillSlotsOrReMatsAvailable.find(SlotOrReMat)->second & 1;
396 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
397 /// stackslot register. The register is still available but is no longer
398 /// allowed to be modifed.
399 void disallowClobberPhysReg(unsigned PhysReg);
401 /// ClobberPhysReg - This is called when the specified physreg changes
402 /// value. We use this to invalidate any info about stuff that lives in
403 /// it and any of its aliases.
404 void ClobberPhysReg(unsigned PhysReg);
406 /// ModifyStackSlotOrReMat - This method is called when the value in a stack
407 /// slot changes. This removes information about which register the previous
408 /// value for this slot lives in (as the previous value is dead now).
409 void ModifyStackSlotOrReMat(int SlotOrReMat);
413 /// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
414 /// stackslot register. The register is still available but is no longer
415 /// allowed to be modifed.
416 void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
417 std::multimap<unsigned, int>::iterator I =
418 PhysRegsAvailable.lower_bound(PhysReg);
419 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
420 int SlotOrReMat = I->second;
422 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
423 "Bidirectional map mismatch!");
424 SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
425 DOUT << "PhysReg " << TRI->getName(PhysReg)
426 << " copied, it is available for use but can no longer be modified\n";
430 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
431 /// stackslot register and its aliases. The register and its aliases may
432 /// still available but is no longer allowed to be modifed.
433 void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
434 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS)
435 disallowClobberPhysRegOnly(*AS);
436 disallowClobberPhysRegOnly(PhysReg);
439 /// ClobberPhysRegOnly - This is called when the specified physreg changes
440 /// value. We use this to invalidate any info about stuff we thing lives in it.
441 void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
442 std::multimap<unsigned, int>::iterator I =
443 PhysRegsAvailable.lower_bound(PhysReg);
444 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
445 int SlotOrReMat = I->second;
446 PhysRegsAvailable.erase(I++);
447 assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
448 "Bidirectional map mismatch!");
449 SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
450 DOUT << "PhysReg " << TRI->getName(PhysReg)
451 << " clobbered, invalidating ";
452 if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
453 DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
455 DOUT << "SS#" << SlotOrReMat << "\n";
459 /// ClobberPhysReg - This is called when the specified physreg changes
460 /// value. We use this to invalidate any info about stuff we thing lives in
461 /// it and any of its aliases.
462 void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
463 for (const unsigned *AS = TRI->getAliasSet(PhysReg); *AS; ++AS)
464 ClobberPhysRegOnly(*AS);
465 ClobberPhysRegOnly(PhysReg);
468 /// ModifyStackSlotOrReMat - This method is called when the value in a stack
469 /// slot changes. This removes information about which register the previous
470 /// value for this slot lives in (as the previous value is dead now).
471 void AvailableSpills::ModifyStackSlotOrReMat(int SlotOrReMat) {
472 std::map<int, unsigned>::iterator It =
473 SpillSlotsOrReMatsAvailable.find(SlotOrReMat);
474 if (It == SpillSlotsOrReMatsAvailable.end()) return;
475 unsigned Reg = It->second >> 1;
476 SpillSlotsOrReMatsAvailable.erase(It);
478 // This register may hold the value of multiple stack slots, only remove this
479 // stack slot from the set of values the register contains.
480 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
482 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
483 "Map inverse broken!");
484 if (I->second == SlotOrReMat) break;
486 PhysRegsAvailable.erase(I);
489 static void findSinglePredSuccessor(MachineBasicBlock *MBB,
490 SmallVectorImpl<MachineBasicBlock *> &Succs) {
491 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
492 SE = MBB->succ_end(); SI != SE; ++SI) {
493 MachineBasicBlock *SuccMBB = *SI;
494 if (SuccMBB->pred_size() == 1)
495 Succs.push_back(SuccMBB);
500 class AvailableSpills;
502 /// LocalSpiller - This spiller does a simple pass over the machine basic
503 /// block to attempt to keep spills in registers as much as possible for
504 /// blocks that have low register pressure (the vreg may be spilled due to
505 /// register pressure in other blocks).
506 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
507 MachineRegisterInfo *RegInfo;
508 const TargetRegisterInfo *TRI;
509 const TargetInstrInfo *TII;
510 DenseMap<MachineInstr*, unsigned> DistanceMap;
512 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
513 RegInfo = &MF.getRegInfo();
514 TRI = MF.getTarget().getRegisterInfo();
515 TII = MF.getTarget().getInstrInfo();
516 DOUT << "\n**** Local spiller rewriting function '"
517 << MF.getFunction()->getName() << "':\n";
518 DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!)"
522 // Spills - Keep track of which spilled values are available in physregs
523 // so that we can choose to reuse the physregs instead of emitting
524 // reloads. This is usually refreshed per basic block.
525 AvailableSpills Spills(TRI, TII);
527 // SingleEntrySuccs - Successor blocks which have a single predecessor.
528 SmallVector<MachineBasicBlock*, 4> SinglePredSuccs;
529 SmallPtrSet<MachineBasicBlock*,16> EarlyVisited;
531 // Traverse the basic blocks depth first.
532 MachineBasicBlock *Entry = MF.begin();
533 SmallPtrSet<MachineBasicBlock*,16> Visited;
534 for (df_ext_iterator<MachineBasicBlock*,
535 SmallPtrSet<MachineBasicBlock*,16> >
536 DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited);
538 MachineBasicBlock *MBB = *DFI;
539 if (!EarlyVisited.count(MBB))
540 RewriteMBB(*MBB, VRM, Spills);
542 // If this MBB is the only predecessor of a successor. Keep the
543 // availability information and visit it next.
545 // Keep visiting single predecessor successor as long as possible.
546 SinglePredSuccs.clear();
547 findSinglePredSuccessor(MBB, SinglePredSuccs);
548 if (SinglePredSuccs.empty())
551 // FIXME: More than one successors, each of which has MBB has
552 // the only predecessor.
553 MBB = SinglePredSuccs[0];
554 if (!Visited.count(MBB) && EarlyVisited.insert(MBB))
555 RewriteMBB(*MBB, VRM, Spills);
559 // Clear the availability info.
563 DOUT << "**** Post Machine Instrs ****\n";
566 // Mark unused spill slots.
567 MachineFrameInfo *MFI = MF.getFrameInfo();
568 int SS = VRM.getLowSpillSlot();
569 if (SS != VirtRegMap::NO_STACK_SLOT)
570 for (int e = VRM.getHighSpillSlot(); SS <= e; ++SS)
571 if (!VRM.isSpillSlotUsed(SS)) {
572 MFI->RemoveStackObject(SS);
579 void TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist,
580 unsigned Reg, BitVector &RegKills,
581 std::vector<MachineOperand*> &KillOps);
582 bool PrepForUnfoldOpti(MachineBasicBlock &MBB,
583 MachineBasicBlock::iterator &MII,
584 std::vector<MachineInstr*> &MaybeDeadStores,
585 AvailableSpills &Spills, BitVector &RegKills,
586 std::vector<MachineOperand*> &KillOps,
588 bool CommuteToFoldReload(MachineBasicBlock &MBB,
589 MachineBasicBlock::iterator &MII,
590 unsigned VirtReg, unsigned SrcReg, int SS,
592 std::vector<MachineOperand*> &KillOps,
593 const TargetRegisterInfo *TRI,
595 void SpillRegToStackSlot(MachineBasicBlock &MBB,
596 MachineBasicBlock::iterator &MII,
597 int Idx, unsigned PhysReg, int StackSlot,
598 const TargetRegisterClass *RC,
599 bool isAvailable, MachineInstr *&LastStore,
600 AvailableSpills &Spills,
601 SmallSet<MachineInstr*, 4> &ReMatDefs,
603 std::vector<MachineOperand*> &KillOps,
605 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
606 AvailableSpills &Spills);
610 /// InvalidateKills - MI is going to be deleted. If any of its operands are
611 /// marked kill, then invalidate the information.
612 static void InvalidateKills(MachineInstr &MI, BitVector &RegKills,
613 std::vector<MachineOperand*> &KillOps,
614 SmallVector<unsigned, 2> *KillRegs = NULL) {
615 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
616 MachineOperand &MO = MI.getOperand(i);
617 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
619 unsigned Reg = MO.getReg();
620 if (TargetRegisterInfo::isVirtualRegister(Reg))
623 KillRegs->push_back(Reg);
624 assert(Reg < KillOps.size());
625 if (KillOps[Reg] == &MO) {
632 /// InvalidateKill - A MI that defines the specified register is being deleted,
633 /// invalidate the register kill information.
634 static void InvalidateKill(unsigned Reg, BitVector &RegKills,
635 std::vector<MachineOperand*> &KillOps) {
637 KillOps[Reg]->setIsKill(false);
643 /// InvalidateRegDef - If the def operand of the specified def MI is now dead
644 /// (since it's spill instruction is removed), mark it isDead. Also checks if
645 /// the def MI has other definition operands that are not dead. Returns it by
647 static bool InvalidateRegDef(MachineBasicBlock::iterator I,
648 MachineInstr &NewDef, unsigned Reg,
650 // Due to remat, it's possible this reg isn't being reused. That is,
651 // the def of this reg (by prev MI) is now dead.
652 MachineInstr *DefMI = I;
653 MachineOperand *DefOp = NULL;
654 for (unsigned i = 0, e = DefMI->getNumOperands(); i != e; ++i) {
655 MachineOperand &MO = DefMI->getOperand(i);
656 if (MO.isReg() && MO.isDef()) {
657 if (MO.getReg() == Reg)
659 else if (!MO.isDead())
666 bool FoundUse = false, Done = false;
667 MachineBasicBlock::iterator E = &NewDef;
669 for (; !Done && I != E; ++I) {
670 MachineInstr *NMI = I;
671 for (unsigned j = 0, ee = NMI->getNumOperands(); j != ee; ++j) {
672 MachineOperand &MO = NMI->getOperand(j);
673 if (!MO.isReg() || MO.getReg() != Reg)
677 Done = true; // Stop after scanning all the operands of this MI.
688 /// UpdateKills - Track and update kill info. If a MI reads a register that is
689 /// marked kill, then it must be due to register reuse. Transfer the kill info
691 static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
692 std::vector<MachineOperand*> &KillOps,
693 const TargetRegisterInfo* TRI) {
694 const TargetInstrDesc &TID = MI.getDesc();
695 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
696 MachineOperand &MO = MI.getOperand(i);
697 if (!MO.isReg() || !MO.isUse())
699 unsigned Reg = MO.getReg();
703 if (RegKills[Reg] && KillOps[Reg]->getParent() != &MI) {
704 // That can't be right. Register is killed but not re-defined and it's
705 // being reused. Let's fix that.
706 KillOps[Reg]->setIsKill(false);
709 if (i < TID.getNumOperands() &&
710 TID.getOperandConstraint(i, TOI::TIED_TO) == -1)
711 // Unless it's a two-address operand, this is the new kill.
720 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
721 const MachineOperand &MO = MI.getOperand(i);
722 if (!MO.isReg() || !MO.isDef())
724 unsigned Reg = MO.getReg();
727 // It also defines (or partially define) aliases.
728 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
735 /// ReMaterialize - Re-materialize definition for Reg targetting DestReg.
737 static void ReMaterialize(MachineBasicBlock &MBB,
738 MachineBasicBlock::iterator &MII,
739 unsigned DestReg, unsigned Reg,
740 const TargetInstrInfo *TII,
741 const TargetRegisterInfo *TRI,
743 TII->reMaterialize(MBB, MII, DestReg, VRM.getReMaterializedMI(Reg));
744 MachineInstr *NewMI = prior(MII);
745 for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
746 MachineOperand &MO = NewMI->getOperand(i);
747 if (!MO.isReg() || MO.getReg() == 0)
749 unsigned VirtReg = MO.getReg();
750 if (TargetRegisterInfo::isPhysicalRegister(VirtReg))
753 unsigned SubIdx = MO.getSubReg();
754 unsigned Phys = VRM.getPhys(VirtReg);
756 unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys;
763 // ReusedOp - For each reused operand, we keep track of a bit of information, in
764 // case we need to rollback upon processing a new operand. See comments below.
767 // The MachineInstr operand that reused an available value.
770 // StackSlotOrReMat - The spill slot or remat id of the value being reused.
771 unsigned StackSlotOrReMat;
773 // PhysRegReused - The physical register the value was available in.
774 unsigned PhysRegReused;
776 // AssignedPhysReg - The physreg that was assigned for use by the reload.
777 unsigned AssignedPhysReg;
779 // VirtReg - The virtual register itself.
782 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
784 : Operand(o), StackSlotOrReMat(ss), PhysRegReused(prr),
785 AssignedPhysReg(apr), VirtReg(vreg) {}
788 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
789 /// is reused instead of reloaded.
790 class VISIBILITY_HIDDEN ReuseInfo {
792 std::vector<ReusedOp> Reuses;
793 BitVector PhysRegsClobbered;
795 ReuseInfo(MachineInstr &mi, const TargetRegisterInfo *tri) : MI(mi) {
796 PhysRegsClobbered.resize(tri->getNumRegs());
799 bool hasReuses() const {
800 return !Reuses.empty();
803 /// addReuse - If we choose to reuse a virtual register that is already
804 /// available instead of reloading it, remember that we did so.
805 void addReuse(unsigned OpNo, unsigned StackSlotOrReMat,
806 unsigned PhysRegReused, unsigned AssignedPhysReg,
808 // If the reload is to the assigned register anyway, no undo will be
810 if (PhysRegReused == AssignedPhysReg) return;
812 // Otherwise, remember this.
813 Reuses.push_back(ReusedOp(OpNo, StackSlotOrReMat, PhysRegReused,
814 AssignedPhysReg, VirtReg));
817 void markClobbered(unsigned PhysReg) {
818 PhysRegsClobbered.set(PhysReg);
821 bool isClobbered(unsigned PhysReg) const {
822 return PhysRegsClobbered.test(PhysReg);
825 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
826 /// is some other operand that is using the specified register, either pick
827 /// a new register to use, or evict the previous reload and use this reg.
828 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
829 AvailableSpills &Spills,
830 std::vector<MachineInstr*> &MaybeDeadStores,
831 SmallSet<unsigned, 8> &Rejected,
833 std::vector<MachineOperand*> &KillOps,
835 const TargetInstrInfo* TII = MI->getParent()->getParent()->getTarget()
838 if (Reuses.empty()) return PhysReg; // This is most often empty.
840 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
841 ReusedOp &Op = Reuses[ro];
842 // If we find some other reuse that was supposed to use this register
843 // exactly for its reload, we can change this reload to use ITS reload
844 // register. That is, unless its reload register has already been
845 // considered and subsequently rejected because it has also been reused
846 // by another operand.
847 if (Op.PhysRegReused == PhysReg &&
848 Rejected.count(Op.AssignedPhysReg) == 0) {
849 // Yup, use the reload register that we didn't use before.
850 unsigned NewReg = Op.AssignedPhysReg;
851 Rejected.insert(PhysReg);
852 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores, Rejected,
853 RegKills, KillOps, VRM);
855 // Otherwise, we might also have a problem if a previously reused
856 // value aliases the new register. If so, codegen the previous reload
858 unsigned PRRU = Op.PhysRegReused;
859 const TargetRegisterInfo *TRI = Spills.getRegInfo();
860 if (TRI->areAliases(PRRU, PhysReg)) {
861 // Okay, we found out that an alias of a reused register
862 // was used. This isn't good because it means we have
863 // to undo a previous reuse.
864 MachineBasicBlock *MBB = MI->getParent();
865 const TargetRegisterClass *AliasRC =
866 MBB->getParent()->getRegInfo().getRegClass(Op.VirtReg);
868 // Copy Op out of the vector and remove it, we're going to insert an
869 // explicit load for it.
871 Reuses.erase(Reuses.begin()+ro);
873 // Ok, we're going to try to reload the assigned physreg into the
874 // slot that we were supposed to in the first place. However, that
875 // register could hold a reuse. Check to see if it conflicts or
876 // would prefer us to use a different register.
877 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
878 MI, Spills, MaybeDeadStores,
879 Rejected, RegKills, KillOps, VRM);
881 MachineBasicBlock::iterator MII = MI;
882 if (NewOp.StackSlotOrReMat > VirtRegMap::MAX_STACK_SLOT) {
883 ReMaterialize(*MBB, MII, NewPhysReg, NewOp.VirtReg, TII, TRI,VRM);
885 TII->loadRegFromStackSlot(*MBB, MII, NewPhysReg,
886 NewOp.StackSlotOrReMat, AliasRC);
887 MachineInstr *LoadMI = prior(MII);
888 VRM.addSpillSlotUse(NewOp.StackSlotOrReMat, LoadMI);
889 // Any stores to this stack slot are not dead anymore.
890 MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL;
893 Spills.ClobberPhysReg(NewPhysReg);
894 Spills.ClobberPhysReg(NewOp.PhysRegReused);
896 unsigned SubIdx = MI->getOperand(NewOp.Operand).getSubReg();
897 unsigned RReg = SubIdx ? TRI->getSubReg(NewPhysReg, SubIdx) : NewPhysReg;
898 MI->getOperand(NewOp.Operand).setReg(RReg);
900 Spills.addAvailable(NewOp.StackSlotOrReMat, NewPhysReg);
902 UpdateKills(*MII, RegKills, KillOps, TRI);
903 DOUT << '\t' << *MII;
905 DOUT << "Reuse undone!\n";
908 // Finally, PhysReg is now available, go ahead and use it.
916 /// GetRegForReload - Helper for the above GetRegForReload(). Add a
917 /// 'Rejected' set to remember which registers have been considered and
918 /// rejected for the reload. This avoids infinite looping in case like
921 /// t2 <- assigned r0 for use by the reload but ended up reuse r1
922 /// t3 <- assigned r1 for use by the reload but ended up reuse r0
924 /// sees r1 is taken by t2, tries t2's reload register r0
925 /// sees r0 is taken by t3, tries t3's reload register r1
926 /// sees r1 is taken by t2, tries t2's reload register r0 ...
927 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
928 AvailableSpills &Spills,
929 std::vector<MachineInstr*> &MaybeDeadStores,
931 std::vector<MachineOperand*> &KillOps,
933 SmallSet<unsigned, 8> Rejected;
934 return GetRegForReload(PhysReg, MI, Spills, MaybeDeadStores, Rejected,
935 RegKills, KillOps, VRM);
940 /// PrepForUnfoldOpti - Turn a store folding instruction into a load folding
941 /// instruction. e.g.
943 /// movl %eax, -32(%ebp)
944 /// movl -36(%ebp), %eax
945 /// orl %eax, -32(%ebp)
948 /// orl -36(%ebp), %eax
949 /// mov %eax, -32(%ebp)
950 /// This enables unfolding optimization for a subsequent instruction which will
951 /// also eliminate the newly introduced store instruction.
952 bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB,
953 MachineBasicBlock::iterator &MII,
954 std::vector<MachineInstr*> &MaybeDeadStores,
955 AvailableSpills &Spills,
957 std::vector<MachineOperand*> &KillOps,
959 MachineFunction &MF = *MBB.getParent();
960 MachineInstr &MI = *MII;
961 unsigned UnfoldedOpc = 0;
962 unsigned UnfoldPR = 0;
963 unsigned UnfoldVR = 0;
964 int FoldedSS = VirtRegMap::NO_STACK_SLOT;
965 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
966 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) {
967 // Only transform a MI that folds a single register.
970 UnfoldVR = I->second.first;
971 VirtRegMap::ModRef MR = I->second.second;
972 // MI2VirtMap be can updated which invalidate the iterator.
973 // Increment the iterator first.
975 if (VRM.isAssignedReg(UnfoldVR))
977 // If this reference is not a use, any previous store is now dead.
978 // Otherwise, the store to this stack slot is not dead anymore.
979 FoldedSS = VRM.getStackSlot(UnfoldVR);
980 MachineInstr* DeadStore = MaybeDeadStores[FoldedSS];
981 if (DeadStore && (MR & VirtRegMap::isModRef)) {
982 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(FoldedSS);
983 if (!PhysReg || !DeadStore->readsRegister(PhysReg))
986 UnfoldedOpc = TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
994 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
995 MachineOperand &MO = MI.getOperand(i);
996 if (!MO.isReg() || MO.getReg() == 0 || !MO.isUse())
998 unsigned VirtReg = MO.getReg();
999 if (TargetRegisterInfo::isPhysicalRegister(VirtReg) || MO.getSubReg())
1001 if (VRM.isAssignedReg(VirtReg)) {
1002 unsigned PhysReg = VRM.getPhys(VirtReg);
1003 if (PhysReg && TRI->regsOverlap(PhysReg, UnfoldPR))
1005 } else if (VRM.isReMaterialized(VirtReg))
1007 int SS = VRM.getStackSlot(VirtReg);
1008 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
1010 if (TRI->regsOverlap(PhysReg, UnfoldPR))
1014 if (VRM.hasPhys(VirtReg)) {
1015 PhysReg = VRM.getPhys(VirtReg);
1016 if (!TRI->regsOverlap(PhysReg, UnfoldPR))
1020 // Ok, we'll need to reload the value into a register which makes
1021 // it impossible to perform the store unfolding optimization later.
1022 // Let's see if it is possible to fold the load if the store is
1023 // unfolded. This allows us to perform the store unfolding
1025 SmallVector<MachineInstr*, 4> NewMIs;
1026 if (TII->unfoldMemoryOperand(MF, &MI, UnfoldVR, false, false, NewMIs)) {
1027 assert(NewMIs.size() == 1);
1028 MachineInstr *NewMI = NewMIs.back();
1030 int Idx = NewMI->findRegisterUseOperandIdx(VirtReg, false);
1032 SmallVector<unsigned, 2> Ops;
1034 MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, NewMI, Ops, SS);
1036 VRM.addSpillSlotUse(SS, FoldedMI);
1037 if (!VRM.hasPhys(UnfoldVR))
1038 VRM.assignVirt2Phys(UnfoldVR, UnfoldPR);
1039 VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
1040 MII = MBB.insert(MII, FoldedMI);
1041 InvalidateKills(MI, RegKills, KillOps);
1042 VRM.RemoveMachineInstrFromMaps(&MI);
1044 MF.DeleteMachineInstr(NewMI);
1047 MF.DeleteMachineInstr(NewMI);
1053 /// CommuteToFoldReload -
1056 /// r1 = op r1, r2<kill>
1059 /// If op is commutable and r2 is killed, then we can xform these to
1060 /// r2 = op r2, fi#1
1062 bool LocalSpiller::CommuteToFoldReload(MachineBasicBlock &MBB,
1063 MachineBasicBlock::iterator &MII,
1064 unsigned VirtReg, unsigned SrcReg, int SS,
1065 BitVector &RegKills,
1066 std::vector<MachineOperand*> &KillOps,
1067 const TargetRegisterInfo *TRI,
1069 if (MII == MBB.begin() || !MII->killsRegister(SrcReg))
1072 MachineFunction &MF = *MBB.getParent();
1073 MachineInstr &MI = *MII;
1074 MachineBasicBlock::iterator DefMII = prior(MII);
1075 MachineInstr *DefMI = DefMII;
1076 const TargetInstrDesc &TID = DefMI->getDesc();
1078 if (DefMII != MBB.begin() &&
1079 TID.isCommutable() &&
1080 TII->CommuteChangesDestination(DefMI, NewDstIdx)) {
1081 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
1082 unsigned NewReg = NewDstMO.getReg();
1083 if (!NewDstMO.isKill() || TRI->regsOverlap(NewReg, SrcReg))
1085 MachineInstr *ReloadMI = prior(DefMII);
1087 unsigned DestReg = TII->isLoadFromStackSlot(ReloadMI, FrameIdx);
1088 if (DestReg != SrcReg || FrameIdx != SS)
1090 int UseIdx = DefMI->findRegisterUseOperandIdx(DestReg, false);
1093 int DefIdx = TID.getOperandConstraint(UseIdx, TOI::TIED_TO);
1096 assert(DefMI->getOperand(DefIdx).isReg() &&
1097 DefMI->getOperand(DefIdx).getReg() == SrcReg);
1099 // Now commute def instruction.
1100 MachineInstr *CommutedMI = TII->commuteInstruction(DefMI, true);
1103 SmallVector<unsigned, 2> Ops;
1104 Ops.push_back(NewDstIdx);
1105 MachineInstr *FoldedMI = TII->foldMemoryOperand(MF, CommutedMI, Ops, SS);
1106 // Not needed since foldMemoryOperand returns new MI.
1107 MF.DeleteMachineInstr(CommutedMI);
1111 VRM.addSpillSlotUse(SS, FoldedMI);
1112 VRM.virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef);
1113 // Insert new def MI and spill MI.
1114 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(VirtReg);
1115 TII->storeRegToStackSlot(MBB, &MI, NewReg, true, SS, RC);
1117 MachineInstr *StoreMI = MII;
1118 VRM.addSpillSlotUse(SS, StoreMI);
1119 VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
1120 MII = MBB.insert(MII, FoldedMI); // Update MII to backtrack.
1122 // Delete all 3 old instructions.
1123 InvalidateKills(*ReloadMI, RegKills, KillOps);
1124 VRM.RemoveMachineInstrFromMaps(ReloadMI);
1125 MBB.erase(ReloadMI);
1126 InvalidateKills(*DefMI, RegKills, KillOps);
1127 VRM.RemoveMachineInstrFromMaps(DefMI);
1129 InvalidateKills(MI, RegKills, KillOps);
1130 VRM.RemoveMachineInstrFromMaps(&MI);
1140 /// findSuperReg - Find the SubReg's super-register of given register class
1141 /// where its SubIdx sub-register is SubReg.
1142 static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg,
1143 unsigned SubIdx, const TargetRegisterInfo *TRI) {
1144 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
1147 if (TRI->getSubReg(Reg, SubIdx) == SubReg)
1153 /// SpillRegToStackSlot - Spill a register to a specified stack slot. Check if
1154 /// the last store to the same slot is now dead. If so, remove the last store.
1155 void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB,
1156 MachineBasicBlock::iterator &MII,
1157 int Idx, unsigned PhysReg, int StackSlot,
1158 const TargetRegisterClass *RC,
1159 bool isAvailable, MachineInstr *&LastStore,
1160 AvailableSpills &Spills,
1161 SmallSet<MachineInstr*, 4> &ReMatDefs,
1162 BitVector &RegKills,
1163 std::vector<MachineOperand*> &KillOps,
1165 TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC);
1166 MachineInstr *StoreMI = next(MII);
1167 VRM.addSpillSlotUse(StackSlot, StoreMI);
1168 DOUT << "Store:\t" << *StoreMI;
1170 // If there is a dead store to this stack slot, nuke it now.
1172 DOUT << "Removed dead store:\t" << *LastStore;
1174 SmallVector<unsigned, 2> KillRegs;
1175 InvalidateKills(*LastStore, RegKills, KillOps, &KillRegs);
1176 MachineBasicBlock::iterator PrevMII = LastStore;
1177 bool CheckDef = PrevMII != MBB.begin();
1180 VRM.RemoveMachineInstrFromMaps(LastStore);
1181 MBB.erase(LastStore);
1183 // Look at defs of killed registers on the store. Mark the defs
1184 // as dead since the store has been deleted and they aren't
1186 for (unsigned j = 0, ee = KillRegs.size(); j != ee; ++j) {
1187 bool HasOtherDef = false;
1188 if (InvalidateRegDef(PrevMII, *MII, KillRegs[j], HasOtherDef)) {
1189 MachineInstr *DeadDef = PrevMII;
1190 if (ReMatDefs.count(DeadDef) && !HasOtherDef) {
1191 // FIXME: This assumes a remat def does not have side
1193 VRM.RemoveMachineInstrFromMaps(DeadDef);
1202 LastStore = next(MII);
1204 // If the stack slot value was previously available in some other
1205 // register, change it now. Otherwise, make the register available,
1207 Spills.ModifyStackSlotOrReMat(StackSlot);
1208 Spills.ClobberPhysReg(PhysReg);
1209 Spills.addAvailable(StackSlot, PhysReg, isAvailable);
1213 /// TransferDeadness - A identity copy definition is dead and it's being
1214 /// removed. Find the last def or use and mark it as dead / kill.
1215 void LocalSpiller::TransferDeadness(MachineBasicBlock *MBB, unsigned CurDist,
1216 unsigned Reg, BitVector &RegKills,
1217 std::vector<MachineOperand*> &KillOps) {
1218 int LastUDDist = -1;
1219 MachineInstr *LastUDMI = NULL;
1220 for (MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(Reg),
1221 RE = RegInfo->reg_end(); RI != RE; ++RI) {
1222 MachineInstr *UDMI = &*RI;
1223 if (UDMI->getParent() != MBB)
1225 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UDMI);
1226 if (DI == DistanceMap.end() || DI->second > CurDist)
1228 if ((int)DI->second < LastUDDist)
1230 LastUDDist = DI->second;
1235 const TargetInstrDesc &TID = LastUDMI->getDesc();
1236 MachineOperand *LastUD = NULL;
1237 for (unsigned i = 0, e = LastUDMI->getNumOperands(); i != e; ++i) {
1238 MachineOperand &MO = LastUDMI->getOperand(i);
1239 if (!MO.isReg() || MO.getReg() != Reg)
1241 if (!LastUD || (LastUD->isUse() && MO.isDef()))
1243 if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1)
1246 if (LastUD->isDef())
1247 LastUD->setIsDead();
1249 LastUD->setIsKill();
1251 KillOps[Reg] = LastUD;
1256 /// rewriteMBB - Keep track of which spills are available even after the
1257 /// register allocator is done with them. If possible, avid reloading vregs.
1258 void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM,
1259 AvailableSpills &Spills) {
1260 DOUT << "\n**** Local spiller rewriting MBB '"
1261 << MBB.getBasicBlock()->getName() << ":\n";
1263 MachineFunction &MF = *MBB.getParent();
1265 // MaybeDeadStores - When we need to write a value back into a stack slot,
1266 // keep track of the inserted store. If the stack slot value is never read
1267 // (because the value was used from some available register, for example), and
1268 // subsequently stored to, the original store is dead. This map keeps track
1269 // of inserted stores that are not used. If we see a subsequent store to the
1270 // same stack slot, the original store is deleted.
1271 std::vector<MachineInstr*> MaybeDeadStores;
1272 MaybeDeadStores.resize(MF.getFrameInfo()->getObjectIndexEnd(), NULL);
1274 // ReMatDefs - These are rematerializable def MIs which are not deleted.
1275 SmallSet<MachineInstr*, 4> ReMatDefs;
1277 // Keep track of kill information.
1278 BitVector RegKills(TRI->getNumRegs());
1279 std::vector<MachineOperand*> KillOps;
1280 KillOps.resize(TRI->getNumRegs(), NULL);
1283 DistanceMap.clear();
1284 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
1286 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
1288 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
1289 bool Erased = false;
1290 bool BackTracked = false;
1291 if (PrepForUnfoldOpti(MBB, MII,
1292 MaybeDeadStores, Spills, RegKills, KillOps, VRM))
1293 NextMII = next(MII);
1295 MachineInstr &MI = *MII;
1296 const TargetInstrDesc &TID = MI.getDesc();
1298 if (VRM.hasEmergencySpills(&MI)) {
1299 // Spill physical register(s) in the rare case the allocator has run out
1300 // of registers to allocate.
1301 SmallSet<int, 4> UsedSS;
1302 std::vector<unsigned> &EmSpills = VRM.getEmergencySpills(&MI);
1303 for (unsigned i = 0, e = EmSpills.size(); i != e; ++i) {
1304 unsigned PhysReg = EmSpills[i];
1305 const TargetRegisterClass *RC =
1306 TRI->getPhysicalRegisterRegClass(PhysReg);
1307 assert(RC && "Unable to determine register class!");
1308 int SS = VRM.getEmergencySpillSlot(RC);
1309 if (UsedSS.count(SS))
1310 assert(0 && "Need to spill more than one physical registers!");
1312 TII->storeRegToStackSlot(MBB, MII, PhysReg, true, SS, RC);
1313 MachineInstr *StoreMI = prior(MII);
1314 VRM.addSpillSlotUse(SS, StoreMI);
1315 TII->loadRegFromStackSlot(MBB, next(MII), PhysReg, SS, RC);
1316 MachineInstr *LoadMI = next(MII);
1317 VRM.addSpillSlotUse(SS, LoadMI);
1320 NextMII = next(MII);
1323 // Insert restores here if asked to.
1324 if (VRM.isRestorePt(&MI)) {
1325 std::vector<unsigned> &RestoreRegs = VRM.getRestorePtRestores(&MI);
1326 for (unsigned i = 0, e = RestoreRegs.size(); i != e; ++i) {
1327 unsigned VirtReg = RestoreRegs[e-i-1]; // Reverse order.
1328 if (!VRM.getPreSplitReg(VirtReg))
1329 continue; // Split interval spilled again.
1330 unsigned Phys = VRM.getPhys(VirtReg);
1331 RegInfo->setPhysRegUsed(Phys);
1333 // Check if the value being restored if available. If so, it must be
1334 // from a predecessor BB that fallthrough into this BB. We do not
1340 // ... # r1 not clobbered
1343 bool DoReMat = VRM.isReMaterialized(VirtReg);
1344 int SSorRMId = DoReMat
1345 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg);
1346 unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
1347 if (InReg == Phys) {
1348 // If the value is already available in the expected register, save
1349 // a reload / remat.
1351 DOUT << "Reusing RM#" << SSorRMId-VirtRegMap::MAX_STACK_SLOT-1;
1353 DOUT << "Reusing SS#" << SSorRMId;
1354 DOUT << " from physreg "
1355 << TRI->getName(InReg) << " for vreg"
1356 << VirtReg <<" instead of reloading into physreg "
1357 << TRI->getName(Phys) << "\n";
1360 } else if (InReg && InReg != Phys) {
1362 DOUT << "Reusing RM#" << SSorRMId-VirtRegMap::MAX_STACK_SLOT-1;
1364 DOUT << "Reusing SS#" << SSorRMId;
1365 DOUT << " from physreg "
1366 << TRI->getName(InReg) << " for vreg"
1367 << VirtReg <<" by copying it into physreg "
1368 << TRI->getName(Phys) << "\n";
1370 // If the reloaded / remat value is available in another register,
1371 // copy it to the desired register.
1372 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1373 TII->copyRegToReg(MBB, &MI, Phys, InReg, RC, RC);
1375 // This invalidates Phys.
1376 Spills.ClobberPhysReg(Phys);
1377 // Remember it's available.
1378 Spills.addAvailable(SSorRMId, Phys);
1381 MachineInstr *CopyMI = prior(MII);
1382 MachineOperand *KillOpnd = CopyMI->findRegisterUseOperand(InReg);
1383 KillOpnd->setIsKill();
1384 UpdateKills(*CopyMI, RegKills, KillOps, TRI);
1386 DOUT << '\t' << *CopyMI;
1391 if (VRM.isReMaterialized(VirtReg)) {
1392 ReMaterialize(MBB, MII, Phys, VirtReg, TII, TRI, VRM);
1394 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1395 TII->loadRegFromStackSlot(MBB, &MI, Phys, SSorRMId, RC);
1396 MachineInstr *LoadMI = prior(MII);
1397 VRM.addSpillSlotUse(SSorRMId, LoadMI);
1401 // This invalidates Phys.
1402 Spills.ClobberPhysReg(Phys);
1403 // Remember it's available.
1404 Spills.addAvailable(SSorRMId, Phys);
1406 UpdateKills(*prior(MII), RegKills, KillOps, TRI);
1407 DOUT << '\t' << *prior(MII);
1411 // Insert spills here if asked to.
1412 if (VRM.isSpillPt(&MI)) {
1413 std::vector<std::pair<unsigned,bool> > &SpillRegs =
1414 VRM.getSpillPtSpills(&MI);
1415 for (unsigned i = 0, e = SpillRegs.size(); i != e; ++i) {
1416 unsigned VirtReg = SpillRegs[i].first;
1417 bool isKill = SpillRegs[i].second;
1418 if (!VRM.getPreSplitReg(VirtReg))
1419 continue; // Split interval spilled again.
1420 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
1421 unsigned Phys = VRM.getPhys(VirtReg);
1422 int StackSlot = VRM.getStackSlot(VirtReg);
1423 TII->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC);
1424 MachineInstr *StoreMI = next(MII);
1425 VRM.addSpillSlotUse(StackSlot, StoreMI);
1426 DOUT << "Store:\t" << *StoreMI;
1427 VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
1429 NextMII = next(MII);
1432 /// ReusedOperands - Keep track of operand reuse in case we need to undo
1434 ReuseInfo ReusedOperands(MI, TRI);
1435 SmallVector<unsigned, 4> VirtUseOps;
1436 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1437 MachineOperand &MO = MI.getOperand(i);
1438 if (!MO.isReg() || MO.getReg() == 0)
1439 continue; // Ignore non-register operands.
1441 unsigned VirtReg = MO.getReg();
1442 if (TargetRegisterInfo::isPhysicalRegister(VirtReg)) {
1443 // Ignore physregs for spilling, but remember that it is used by this
1445 RegInfo->setPhysRegUsed(VirtReg);
1449 // We want to process implicit virtual register uses first.
1450 if (MO.isImplicit())
1451 // If the virtual register is implicitly defined, emit a implicit_def
1452 // before so scavenger knows it's "defined".
1453 VirtUseOps.insert(VirtUseOps.begin(), i);
1455 VirtUseOps.push_back(i);
1458 // Process all of the spilled uses and all non spilled reg references.
1459 SmallVector<int, 2> PotentialDeadStoreSlots;
1460 for (unsigned j = 0, e = VirtUseOps.size(); j != e; ++j) {
1461 unsigned i = VirtUseOps[j];
1462 MachineOperand &MO = MI.getOperand(i);
1463 unsigned VirtReg = MO.getReg();
1464 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) &&
1465 "Not a virtual register?");
1467 unsigned SubIdx = MO.getSubReg();
1468 if (VRM.isAssignedReg(VirtReg)) {
1469 // This virtual register was assigned a physreg!
1470 unsigned Phys = VRM.getPhys(VirtReg);
1471 RegInfo->setPhysRegUsed(Phys);
1473 ReusedOperands.markClobbered(Phys);
1474 unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys;
1475 MI.getOperand(i).setReg(RReg);
1476 if (VRM.isImplicitlyDefined(VirtReg))
1477 BuildMI(MBB, &MI, MI.getDebugLoc(),
1478 TII->get(TargetInstrInfo::IMPLICIT_DEF), RReg);
1482 // This virtual register is now known to be a spilled value.
1484 continue; // Handle defs in the loop below (handle use&def here though)
1486 bool DoReMat = VRM.isReMaterialized(VirtReg);
1487 int SSorRMId = DoReMat
1488 ? VRM.getReMatId(VirtReg) : VRM.getStackSlot(VirtReg);
1489 int ReuseSlot = SSorRMId;
1491 // Check to see if this stack slot is available.
1492 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SSorRMId);
1494 // If this is a sub-register use, make sure the reuse register is in the
1495 // right register class. For example, for x86 not all of the 32-bit
1496 // registers have accessible sub-registers.
1497 // Similarly so for EXTRACT_SUBREG. Consider this:
1499 // MOV32_mr fi#1, EDI
1501 // = EXTRACT_SUBREG fi#1
1502 // fi#1 is available in EDI, but it cannot be reused because it's not in
1503 // the right register file.
1505 (SubIdx || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) {
1506 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1507 if (!RC->contains(PhysReg))
1512 // This spilled operand might be part of a two-address operand. If this
1513 // is the case, then changing it will necessarily require changing the
1514 // def part of the instruction as well. However, in some cases, we
1515 // aren't allowed to modify the reused register. If none of these cases
1517 bool CanReuse = true;
1518 int ti = TID.getOperandConstraint(i, TOI::TIED_TO);
1520 MI.getOperand(ti).isReg() &&
1521 MI.getOperand(ti).getReg() == VirtReg) {
1522 // Okay, we have a two address operand. We can reuse this physreg as
1523 // long as we are allowed to clobber the value and there isn't an
1524 // earlier def that has already clobbered the physreg.
1525 CanReuse = Spills.canClobberPhysReg(ReuseSlot) &&
1526 !ReusedOperands.isClobbered(PhysReg);
1530 // If this stack slot value is already available, reuse it!
1531 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
1532 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
1534 DOUT << "Reusing SS#" << ReuseSlot;
1535 DOUT << " from physreg "
1536 << TRI->getName(PhysReg) << " for vreg"
1537 << VirtReg <<" instead of reloading into physreg "
1538 << TRI->getName(VRM.getPhys(VirtReg)) << "\n";
1539 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
1540 MI.getOperand(i).setReg(RReg);
1542 // The only technical detail we have is that we don't know that
1543 // PhysReg won't be clobbered by a reloaded stack slot that occurs
1544 // later in the instruction. In particular, consider 'op V1, V2'.
1545 // If V1 is available in physreg R0, we would choose to reuse it
1546 // here, instead of reloading it into the register the allocator
1547 // indicated (say R1). However, V2 might have to be reloaded
1548 // later, and it might indicate that it needs to live in R0. When
1549 // this occurs, we need to have information available that
1550 // indicates it is safe to use R1 for the reload instead of R0.
1552 // To further complicate matters, we might conflict with an alias,
1553 // or R0 and R1 might not be compatible with each other. In this
1554 // case, we actually insert a reload for V1 in R1, ensuring that
1555 // we can get at R0 or its alias.
1556 ReusedOperands.addReuse(i, ReuseSlot, PhysReg,
1557 VRM.getPhys(VirtReg), VirtReg);
1559 // Only mark it clobbered if this is a use&def operand.
1560 ReusedOperands.markClobbered(PhysReg);
1563 if (MI.getOperand(i).isKill() &&
1564 ReuseSlot <= VirtRegMap::MAX_STACK_SLOT) {
1566 // The store of this spilled value is potentially dead, but we
1567 // won't know for certain until we've confirmed that the re-use
1568 // above is valid, which means waiting until the other operands
1569 // are processed. For now we just track the spill slot, we'll
1570 // remove it after the other operands are processed if valid.
1572 PotentialDeadStoreSlots.push_back(ReuseSlot);
1577 // Otherwise we have a situation where we have a two-address instruction
1578 // whose mod/ref operand needs to be reloaded. This reload is already
1579 // available in some register "PhysReg", but if we used PhysReg as the
1580 // operand to our 2-addr instruction, the instruction would modify
1581 // PhysReg. This isn't cool if something later uses PhysReg and expects
1582 // to get its initial value.
1584 // To avoid this problem, and to avoid doing a load right after a store,
1585 // we emit a copy from PhysReg into the designated register for this
1587 unsigned DesignatedReg = VRM.getPhys(VirtReg);
1588 assert(DesignatedReg && "Must map virtreg to physreg!");
1590 // Note that, if we reused a register for a previous operand, the
1591 // register we want to reload into might not actually be
1592 // available. If this occurs, use the register indicated by the
1594 if (ReusedOperands.hasReuses())
1595 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
1596 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
1598 // If the mapped designated register is actually the physreg we have
1599 // incoming, we don't need to inserted a dead copy.
1600 if (DesignatedReg == PhysReg) {
1601 // If this stack slot value is already available, reuse it!
1602 if (ReuseSlot > VirtRegMap::MAX_STACK_SLOT)
1603 DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
1605 DOUT << "Reusing SS#" << ReuseSlot;
1606 DOUT << " from physreg " << TRI->getName(PhysReg)
1607 << " for vreg" << VirtReg
1608 << " instead of reloading into same physreg.\n";
1609 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
1610 MI.getOperand(i).setReg(RReg);
1611 ReusedOperands.markClobbered(RReg);
1616 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1617 RegInfo->setPhysRegUsed(DesignatedReg);
1618 ReusedOperands.markClobbered(DesignatedReg);
1619 TII->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC);
1621 MachineInstr *CopyMI = prior(MII);
1622 UpdateKills(*CopyMI, RegKills, KillOps, TRI);
1624 // This invalidates DesignatedReg.
1625 Spills.ClobberPhysReg(DesignatedReg);
1627 Spills.addAvailable(ReuseSlot, DesignatedReg);
1629 SubIdx ? TRI->getSubReg(DesignatedReg, SubIdx) : DesignatedReg;
1630 MI.getOperand(i).setReg(RReg);
1631 DOUT << '\t' << *prior(MII);
1636 // Otherwise, reload it and remember that we have it.
1637 PhysReg = VRM.getPhys(VirtReg);
1638 assert(PhysReg && "Must map virtreg to physreg!");
1640 // Note that, if we reused a register for a previous operand, the
1641 // register we want to reload into might not actually be
1642 // available. If this occurs, use the register indicated by the
1644 if (ReusedOperands.hasReuses())
1645 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
1646 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
1648 RegInfo->setPhysRegUsed(PhysReg);
1649 ReusedOperands.markClobbered(PhysReg);
1651 ReMaterialize(MBB, MII, PhysReg, VirtReg, TII, TRI, VRM);
1653 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1654 TII->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
1655 MachineInstr *LoadMI = prior(MII);
1656 VRM.addSpillSlotUse(SSorRMId, LoadMI);
1659 // This invalidates PhysReg.
1660 Spills.ClobberPhysReg(PhysReg);
1662 // Any stores to this stack slot are not dead anymore.
1664 MaybeDeadStores[SSorRMId] = NULL;
1665 Spills.addAvailable(SSorRMId, PhysReg);
1666 // Assumes this is the last use. IsKill will be unset if reg is reused
1667 // unless it's a two-address operand.
1668 if (TID.getOperandConstraint(i, TOI::TIED_TO) == -1)
1669 MI.getOperand(i).setIsKill();
1670 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
1671 MI.getOperand(i).setReg(RReg);
1672 UpdateKills(*prior(MII), RegKills, KillOps, TRI);
1673 DOUT << '\t' << *prior(MII);
1676 // Ok - now we can remove stores that have been confirmed dead.
1677 for (unsigned j = 0, e = PotentialDeadStoreSlots.size(); j != e; ++j) {
1678 // This was the last use and the spilled value is still available
1679 // for reuse. That means the spill was unnecessary!
1680 int PDSSlot = PotentialDeadStoreSlots[j];
1681 MachineInstr* DeadStore = MaybeDeadStores[PDSSlot];
1683 DOUT << "Removed dead store:\t" << *DeadStore;
1684 InvalidateKills(*DeadStore, RegKills, KillOps);
1685 VRM.RemoveMachineInstrFromMaps(DeadStore);
1686 MBB.erase(DeadStore);
1687 MaybeDeadStores[PDSSlot] = NULL;
1696 // If we have folded references to memory operands, make sure we clear all
1697 // physical registers that may contain the value of the spilled virtual
1699 SmallSet<int, 2> FoldedSS;
1700 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ) {
1701 unsigned VirtReg = I->second.first;
1702 VirtRegMap::ModRef MR = I->second.second;
1703 DOUT << "Folded vreg: " << VirtReg << " MR: " << MR;
1705 // MI2VirtMap be can updated which invalidate the iterator.
1706 // Increment the iterator first.
1708 int SS = VRM.getStackSlot(VirtReg);
1709 if (SS == VirtRegMap::NO_STACK_SLOT)
1711 FoldedSS.insert(SS);
1712 DOUT << " - StackSlot: " << SS << "\n";
1714 // If this folded instruction is just a use, check to see if it's a
1715 // straight load from the virt reg slot.
1716 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
1718 unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx);
1719 if (DestReg && FrameIdx == SS) {
1720 // If this spill slot is available, turn it into a copy (or nothing)
1721 // instead of leaving it as a load!
1722 if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) {
1723 DOUT << "Promoted Load To Copy: " << MI;
1724 if (DestReg != InReg) {
1725 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
1726 TII->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC);
1727 MachineOperand *DefMO = MI.findRegisterDefOperand(DestReg);
1728 unsigned SubIdx = DefMO->getSubReg();
1729 // Revisit the copy so we make sure to notice the effects of the
1730 // operation on the destreg (either needing to RA it if it's
1731 // virtual or needing to clobber any values if it's physical).
1733 --NextMII; // backtrack to the copy.
1734 // Propagate the sub-register index over.
1736 DefMO = NextMII->findRegisterDefOperand(DestReg);
1737 DefMO->setSubReg(SubIdx);
1741 DOUT << "Removing now-noop copy: " << MI;
1742 // Unset last kill since it's being reused.
1743 InvalidateKill(InReg, RegKills, KillOps);
1746 InvalidateKills(MI, RegKills, KillOps);
1747 VRM.RemoveMachineInstrFromMaps(&MI);
1750 goto ProcessNextInst;
1753 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
1754 SmallVector<MachineInstr*, 4> NewMIs;
1756 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)) {
1757 MBB.insert(MII, NewMIs[0]);
1758 InvalidateKills(MI, RegKills, KillOps);
1759 VRM.RemoveMachineInstrFromMaps(&MI);
1762 --NextMII; // backtrack to the unfolded instruction.
1764 goto ProcessNextInst;
1769 // If this reference is not a use, any previous store is now dead.
1770 // Otherwise, the store to this stack slot is not dead anymore.
1771 MachineInstr* DeadStore = MaybeDeadStores[SS];
1773 bool isDead = !(MR & VirtRegMap::isRef);
1774 MachineInstr *NewStore = NULL;
1775 if (MR & VirtRegMap::isModRef) {
1776 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
1777 SmallVector<MachineInstr*, 4> NewMIs;
1778 // We can reuse this physreg as long as we are allowed to clobber
1779 // the value and there isn't an earlier def that has already clobbered
1782 !TII->isStoreToStackSlot(&MI, SS)) { // Not profitable!
1783 MachineOperand *KillOpnd =
1784 DeadStore->findRegisterUseOperand(PhysReg, true);
1785 // Note, if the store is storing a sub-register, it's possible the
1786 // super-register is needed below.
1787 if (KillOpnd && !KillOpnd->getSubReg() &&
1788 TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, true,NewMIs)){
1789 MBB.insert(MII, NewMIs[0]);
1790 NewStore = NewMIs[1];
1791 MBB.insert(MII, NewStore);
1792 VRM.addSpillSlotUse(SS, NewStore);
1793 InvalidateKills(MI, RegKills, KillOps);
1794 VRM.RemoveMachineInstrFromMaps(&MI);
1798 --NextMII; // backtrack to the unfolded instruction.
1805 if (isDead) { // Previous store is dead.
1806 // If we get here, the store is dead, nuke it now.
1807 DOUT << "Removed dead store:\t" << *DeadStore;
1808 InvalidateKills(*DeadStore, RegKills, KillOps);
1809 VRM.RemoveMachineInstrFromMaps(DeadStore);
1810 MBB.erase(DeadStore);
1815 MaybeDeadStores[SS] = NULL;
1817 // Treat this store as a spill merged into a copy. That makes the
1818 // stack slot value available.
1819 VRM.virtFolded(VirtReg, NewStore, VirtRegMap::isMod);
1820 goto ProcessNextInst;
1824 // If the spill slot value is available, and this is a new definition of
1825 // the value, the value is not available anymore.
1826 if (MR & VirtRegMap::isMod) {
1827 // Notice that the value in this stack slot has been modified.
1828 Spills.ModifyStackSlotOrReMat(SS);
1830 // If this is *just* a mod of the value, check to see if this is just a
1831 // store to the spill slot (i.e. the spill got merged into the copy). If
1832 // so, realize that the vreg is available now, and add the store to the
1833 // MaybeDeadStore info.
1835 if (!(MR & VirtRegMap::isRef)) {
1836 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
1837 assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
1838 "Src hasn't been allocated yet?");
1840 if (CommuteToFoldReload(MBB, MII, VirtReg, SrcReg, StackSlot,
1841 RegKills, KillOps, TRI, VRM)) {
1842 NextMII = next(MII);
1844 goto ProcessNextInst;
1847 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
1848 // this as a potentially dead store in case there is a subsequent
1849 // store into the stack slot without a read from it.
1850 MaybeDeadStores[StackSlot] = &MI;
1852 // If the stack slot value was previously available in some other
1853 // register, change it now. Otherwise, make the register
1854 // available in PhysReg.
1855 Spills.addAvailable(StackSlot, SrcReg, false/*!clobber*/);
1861 // Process all of the spilled defs.
1862 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1863 MachineOperand &MO = MI.getOperand(i);
1864 if (!(MO.isReg() && MO.getReg() && MO.isDef()))
1867 unsigned VirtReg = MO.getReg();
1868 if (!TargetRegisterInfo::isVirtualRegister(VirtReg)) {
1869 // Check to see if this is a noop copy. If so, eliminate the
1870 // instruction before considering the dest reg to be changed.
1871 unsigned Src, Dst, SrcSR, DstSR;
1872 if (TII->isMoveInstr(MI, Src, Dst, SrcSR, DstSR) && Src == Dst) {
1874 DOUT << "Removing now-noop copy: " << MI;
1875 SmallVector<unsigned, 2> KillRegs;
1876 InvalidateKills(MI, RegKills, KillOps, &KillRegs);
1877 if (MO.isDead() && !KillRegs.empty()) {
1878 // Source register or an implicit super/sub-register use is killed.
1879 assert(KillRegs[0] == Dst ||
1880 TRI->isSubRegister(KillRegs[0], Dst) ||
1881 TRI->isSuperRegister(KillRegs[0], Dst));
1882 // Last def is now dead.
1883 TransferDeadness(&MBB, Dist, Src, RegKills, KillOps);
1885 VRM.RemoveMachineInstrFromMaps(&MI);
1888 Spills.disallowClobberPhysReg(VirtReg);
1889 goto ProcessNextInst;
1892 // If it's not a no-op copy, it clobbers the value in the destreg.
1893 Spills.ClobberPhysReg(VirtReg);
1894 ReusedOperands.markClobbered(VirtReg);
1896 // Check to see if this instruction is a load from a stack slot into
1897 // a register. If so, this provides the stack slot value in the reg.
1899 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
1900 assert(DestReg == VirtReg && "Unknown load situation!");
1902 // If it is a folded reference, then it's not safe to clobber.
1903 bool Folded = FoldedSS.count(FrameIdx);
1904 // Otherwise, if it wasn't available, remember that it is now!
1905 Spills.addAvailable(FrameIdx, DestReg, !Folded);
1906 goto ProcessNextInst;
1912 unsigned SubIdx = MO.getSubReg();
1913 bool DoReMat = VRM.isReMaterialized(VirtReg);
1915 ReMatDefs.insert(&MI);
1917 // The only vregs left are stack slot definitions.
1918 int StackSlot = VRM.getStackSlot(VirtReg);
1919 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
1921 // If this def is part of a two-address operand, make sure to execute
1922 // the store from the correct physical register.
1924 int TiedOp = MI.getDesc().findTiedToSrcOperand(i);
1926 PhysReg = MI.getOperand(TiedOp).getReg();
1928 unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, TRI);
1929 assert(SuperReg && TRI->getSubReg(SuperReg, SubIdx) == PhysReg &&
1930 "Can't find corresponding super-register!");
1934 PhysReg = VRM.getPhys(VirtReg);
1935 if (ReusedOperands.isClobbered(PhysReg)) {
1936 // Another def has taken the assigned physreg. It must have been a
1937 // use&def which got it due to reuse. Undo the reuse!
1938 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
1939 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
1943 assert(PhysReg && "VR not assigned a physical register?");
1944 RegInfo->setPhysRegUsed(PhysReg);
1945 unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
1946 ReusedOperands.markClobbered(RReg);
1947 MI.getOperand(i).setReg(RReg);
1950 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
1951 SpillRegToStackSlot(MBB, MII, -1, PhysReg, StackSlot, RC, true,
1952 LastStore, Spills, ReMatDefs, RegKills, KillOps, VRM);
1953 NextMII = next(MII);
1955 // Check to see if this is a noop copy. If so, eliminate the
1956 // instruction before considering the dest reg to be changed.
1958 unsigned Src, Dst, SrcSR, DstSR;
1959 if (TII->isMoveInstr(MI, Src, Dst, SrcSR, DstSR) && Src == Dst) {
1961 DOUT << "Removing now-noop copy: " << MI;
1962 InvalidateKills(MI, RegKills, KillOps);
1963 VRM.RemoveMachineInstrFromMaps(&MI);
1966 UpdateKills(*LastStore, RegKills, KillOps, TRI);
1967 goto ProcessNextInst;
1973 DistanceMap.insert(std::make_pair(&MI, Dist++));
1974 if (!Erased && !BackTracked) {
1975 for (MachineBasicBlock::iterator II = &MI; II != NextMII; ++II)
1976 UpdateKills(*II, RegKills, KillOps, TRI);
1983 llvm::Spiller* llvm::createSpiller() {
1984 switch (SpillerOpt) {
1985 default: assert(0 && "Unreachable!");
1987 return new LocalSpiller();
1989 return new SimpleSpiller();