1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
28 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "twoaddrinstr"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/Function.h"
33 #include "llvm/CodeGen/LiveVariables.h"
34 #include "llvm/CodeGen/MachineFunctionPass.h"
35 #include "llvm/CodeGen/MachineInstr.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/Analysis/AliasAnalysis.h"
39 #include "llvm/MC/MCInstrItineraries.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetInstrInfo.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/ADT/BitVector.h"
47 #include "llvm/ADT/DenseMap.h"
48 #include "llvm/ADT/SmallSet.h"
49 #include "llvm/ADT/Statistic.h"
50 #include "llvm/ADT/STLExtras.h"
53 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
54 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
55 STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
56 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
57 STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
58 STATISTIC(NumReMats, "Number of instructions re-materialized");
59 STATISTIC(NumDeletes, "Number of dead instructions deleted");
60 STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");
61 STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");
64 class TwoAddressInstructionPass : public MachineFunctionPass {
65 const TargetInstrInfo *TII;
66 const TargetRegisterInfo *TRI;
67 const InstrItineraryData *InstrItins;
68 MachineRegisterInfo *MRI;
72 // DistanceMap - Keep track the distance of a MI from the start of the
73 // current basic block.
74 DenseMap<MachineInstr*, unsigned> DistanceMap;
76 // SrcRegMap - A map from virtual registers to physical registers which
77 // are likely targets to be coalesced to due to copies from physical
78 // registers to virtual registers. e.g. v1024 = move r0.
79 DenseMap<unsigned, unsigned> SrcRegMap;
81 // DstRegMap - A map from virtual registers to physical registers which
82 // are likely targets to be coalesced to due to copies to physical
83 // registers from virtual registers. e.g. r1 = move v1024.
84 DenseMap<unsigned, unsigned> DstRegMap;
86 /// RegSequences - Keep track the list of REG_SEQUENCE instructions seen
87 /// during the initial walk of the machine function.
88 SmallVector<MachineInstr*, 16> RegSequences;
90 bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI,
92 MachineBasicBlock::iterator OldPos);
94 bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC,
95 MachineInstr *MI, MachineInstr *DefMI,
96 MachineBasicBlock *MBB, unsigned Loc);
98 bool NoUseAfterLastDef(unsigned Reg, MachineBasicBlock *MBB, unsigned Dist,
101 MachineInstr *FindLastUseInMBB(unsigned Reg, MachineBasicBlock *MBB,
104 bool isProfitableToCommute(unsigned regB, unsigned regC,
105 MachineInstr *MI, MachineBasicBlock *MBB,
108 bool CommuteInstruction(MachineBasicBlock::iterator &mi,
109 MachineFunction::iterator &mbbi,
110 unsigned RegB, unsigned RegC, unsigned Dist);
112 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
114 bool ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
115 MachineBasicBlock::iterator &nmi,
116 MachineFunction::iterator &mbbi,
117 unsigned RegA, unsigned RegB, unsigned Dist);
119 typedef std::pair<std::pair<unsigned, bool>, MachineInstr*> NewKill;
120 bool canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills,
121 SmallVector<NewKill, 4> &NewKills,
122 MachineBasicBlock *MBB, unsigned Dist);
123 bool DeleteUnusedInstr(MachineBasicBlock::iterator &mi,
124 MachineBasicBlock::iterator &nmi,
125 MachineFunction::iterator &mbbi, unsigned Dist);
127 bool isDefTooClose(unsigned Reg, unsigned Dist,
128 MachineInstr *MI, MachineBasicBlock *MBB);
130 bool RescheduleMIBelowKill(MachineBasicBlock *MBB,
131 MachineBasicBlock::iterator &mi,
132 MachineBasicBlock::iterator &nmi,
134 bool RescheduleKillAboveMI(MachineBasicBlock *MBB,
135 MachineBasicBlock::iterator &mi,
136 MachineBasicBlock::iterator &nmi,
139 bool TryInstructionTransform(MachineBasicBlock::iterator &mi,
140 MachineBasicBlock::iterator &nmi,
141 MachineFunction::iterator &mbbi,
142 unsigned SrcIdx, unsigned DstIdx,
144 SmallPtrSet<MachineInstr*, 8> &Processed);
146 void ScanUses(unsigned DstReg, MachineBasicBlock *MBB,
147 SmallPtrSet<MachineInstr*, 8> &Processed);
149 void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB,
150 SmallPtrSet<MachineInstr*, 8> &Processed);
152 void CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, unsigned DstReg);
154 /// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
155 /// of the de-ssa process. This replaces sources of REG_SEQUENCE as
156 /// sub-register references of the register defined by REG_SEQUENCE.
157 bool EliminateRegSequences();
160 static char ID; // Pass identification, replacement for typeid
161 TwoAddressInstructionPass() : MachineFunctionPass(ID) {
162 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
165 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
166 AU.setPreservesCFG();
167 AU.addRequired<AliasAnalysis>();
168 AU.addPreserved<LiveVariables>();
169 AU.addPreservedID(MachineLoopInfoID);
170 AU.addPreservedID(MachineDominatorsID);
171 AU.addPreservedID(PHIEliminationID);
172 MachineFunctionPass::getAnalysisUsage(AU);
175 /// runOnMachineFunction - Pass entry point.
176 bool runOnMachineFunction(MachineFunction&);
180 char TwoAddressInstructionPass::ID = 0;
181 INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction",
182 "Two-Address instruction pass", false, false)
183 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
184 INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction",
185 "Two-Address instruction pass", false, false)
187 char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
189 /// Sink3AddrInstruction - A two-address instruction has been converted to a
190 /// three-address instruction to avoid clobbering a register. Try to sink it
191 /// past the instruction that would kill the above mentioned register to reduce
192 /// register pressure.
193 bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
194 MachineInstr *MI, unsigned SavedReg,
195 MachineBasicBlock::iterator OldPos) {
196 // FIXME: Shouldn't we be trying to do this before we three-addressify the
197 // instruction? After this transformation is done, we no longer need
198 // the instruction to be in three-address form.
200 // Check if it's safe to move this instruction.
201 bool SeenStore = true; // Be conservative.
202 if (!MI->isSafeToMove(TII, AA, SeenStore))
206 SmallSet<unsigned, 4> UseRegs;
208 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
209 const MachineOperand &MO = MI->getOperand(i);
212 unsigned MOReg = MO.getReg();
215 if (MO.isUse() && MOReg != SavedReg)
216 UseRegs.insert(MO.getReg());
220 // Don't try to move it if it implicitly defines a register.
223 // For now, don't move any instructions that define multiple registers.
225 DefReg = MO.getReg();
228 // Find the instruction that kills SavedReg.
229 MachineInstr *KillMI = NULL;
230 for (MachineRegisterInfo::use_nodbg_iterator
231 UI = MRI->use_nodbg_begin(SavedReg),
232 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
233 MachineOperand &UseMO = UI.getOperand();
236 KillMI = UseMO.getParent();
240 // If we find the instruction that kills SavedReg, and it is in an
241 // appropriate location, we can try to sink the current instruction
243 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI ||
244 KillMI->getDesc().isTerminator())
247 // If any of the definitions are used by another instruction between the
248 // position and the kill use, then it's not safe to sink it.
250 // FIXME: This can be sped up if there is an easy way to query whether an
251 // instruction is before or after another instruction. Then we can use
252 // MachineRegisterInfo def / use instead.
253 MachineOperand *KillMO = NULL;
254 MachineBasicBlock::iterator KillPos = KillMI;
257 unsigned NumVisited = 0;
258 for (MachineBasicBlock::iterator I = llvm::next(OldPos); I != KillPos; ++I) {
259 MachineInstr *OtherMI = I;
260 // DBG_VALUE cannot be counted against the limit.
261 if (OtherMI->isDebugValue())
263 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
266 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
267 MachineOperand &MO = OtherMI->getOperand(i);
270 unsigned MOReg = MO.getReg();
277 if (OtherMI == KillMI && MOReg == SavedReg)
278 // Save the operand that kills the register. We want to unset the kill
279 // marker if we can sink MI past it.
281 else if (UseRegs.count(MOReg))
282 // One of the uses is killed before the destination.
288 // Update kill and LV information.
289 KillMO->setIsKill(false);
290 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
291 KillMO->setIsKill(true);
294 LV->replaceKillInstruction(SavedReg, KillMI, MI);
296 // Move instruction to its destination.
298 MBB->insert(KillPos, MI);
304 /// isTwoAddrUse - Return true if the specified MI is using the specified
305 /// register as a two-address operand.
306 static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) {
307 const MCInstrDesc &MCID = UseMI->getDesc();
308 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
309 MachineOperand &MO = UseMI->getOperand(i);
310 if (MO.isReg() && MO.getReg() == Reg &&
311 (MO.isDef() || UseMI->isRegTiedToDefOperand(i)))
312 // Earlier use is a two-address one.
318 /// isProfitableToReMat - Return true if the heuristics determines it is likely
319 /// to be profitable to re-materialize the definition of Reg rather than copy
322 TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg,
323 const TargetRegisterClass *RC,
324 MachineInstr *MI, MachineInstr *DefMI,
325 MachineBasicBlock *MBB, unsigned Loc) {
326 bool OtherUse = false;
327 for (MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(Reg),
328 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
329 MachineOperand &UseMO = UI.getOperand();
330 MachineInstr *UseMI = UseMO.getParent();
331 MachineBasicBlock *UseMBB = UseMI->getParent();
333 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
334 if (DI != DistanceMap.end() && DI->second == Loc)
335 continue; // Current use.
337 // There is at least one other use in the MBB that will clobber the
339 if (isTwoAddrUse(UseMI, Reg))
344 // If other uses in MBB are not two-address uses, then don't remat.
348 // No other uses in the same block, remat if it's defined in the same
349 // block so it does not unnecessarily extend the live range.
350 return MBB == DefMI->getParent();
353 /// NoUseAfterLastDef - Return true if there are no intervening uses between the
354 /// last instruction in the MBB that defines the specified register and the
355 /// two-address instruction which is being processed. It also returns the last
356 /// def location by reference
357 bool TwoAddressInstructionPass::NoUseAfterLastDef(unsigned Reg,
358 MachineBasicBlock *MBB, unsigned Dist,
361 unsigned LastUse = Dist;
362 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
363 E = MRI->reg_end(); I != E; ++I) {
364 MachineOperand &MO = I.getOperand();
365 MachineInstr *MI = MO.getParent();
366 if (MI->getParent() != MBB || MI->isDebugValue())
368 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
369 if (DI == DistanceMap.end())
371 if (MO.isUse() && DI->second < LastUse)
372 LastUse = DI->second;
373 if (MO.isDef() && DI->second > LastDef)
374 LastDef = DI->second;
377 return !(LastUse > LastDef && LastUse < Dist);
380 MachineInstr *TwoAddressInstructionPass::FindLastUseInMBB(unsigned Reg,
381 MachineBasicBlock *MBB,
383 unsigned LastUseDist = 0;
384 MachineInstr *LastUse = 0;
385 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
386 E = MRI->reg_end(); I != E; ++I) {
387 MachineOperand &MO = I.getOperand();
388 MachineInstr *MI = MO.getParent();
389 if (MI->getParent() != MBB || MI->isDebugValue())
391 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
392 if (DI == DistanceMap.end())
394 if (DI->second >= Dist)
397 if (MO.isUse() && DI->second > LastUseDist) {
399 LastUseDist = DI->second;
405 /// isCopyToReg - Return true if the specified MI is a copy instruction or
406 /// a extract_subreg instruction. It also returns the source and destination
407 /// registers and whether they are physical registers by reference.
408 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
409 unsigned &SrcReg, unsigned &DstReg,
410 bool &IsSrcPhys, bool &IsDstPhys) {
414 DstReg = MI.getOperand(0).getReg();
415 SrcReg = MI.getOperand(1).getReg();
416 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
417 DstReg = MI.getOperand(0).getReg();
418 SrcReg = MI.getOperand(2).getReg();
422 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
423 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
427 /// isKilled - Test if the given register value, which is used by the given
428 /// instruction, is killed by the given instruction. This looks through
429 /// coalescable copies to see if the original value is potentially not killed.
431 /// For example, in this code:
433 /// %reg1034 = copy %reg1024
434 /// %reg1035 = copy %reg1025<kill>
435 /// %reg1036 = add %reg1034<kill>, %reg1035<kill>
437 /// %reg1034 is not considered to be killed, since it is copied from a
438 /// register which is not killed. Treating it as not killed lets the
439 /// normal heuristics commute the (two-address) add, which lets
440 /// coalescing eliminate the extra copy.
442 static bool isKilled(MachineInstr &MI, unsigned Reg,
443 const MachineRegisterInfo *MRI,
444 const TargetInstrInfo *TII) {
445 MachineInstr *DefMI = &MI;
447 if (!DefMI->killsRegister(Reg))
449 if (TargetRegisterInfo::isPhysicalRegister(Reg))
451 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
452 // If there are multiple defs, we can't do a simple analysis, so just
453 // go with what the kill flag says.
454 if (llvm::next(Begin) != MRI->def_end())
457 bool IsSrcPhys, IsDstPhys;
458 unsigned SrcReg, DstReg;
459 // If the def is something other than a copy, then it isn't going to
460 // be coalesced, so follow the kill flag.
461 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
467 /// isTwoAddrUse - Return true if the specified MI uses the specified register
468 /// as a two-address use. If so, return the destination register by reference.
469 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
470 const MCInstrDesc &MCID = MI.getDesc();
471 unsigned NumOps = MI.isInlineAsm()
472 ? MI.getNumOperands() : MCID.getNumOperands();
473 for (unsigned i = 0; i != NumOps; ++i) {
474 const MachineOperand &MO = MI.getOperand(i);
475 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
478 if (MI.isRegTiedToDefOperand(i, &ti)) {
479 DstReg = MI.getOperand(ti).getReg();
486 /// findLocalKill - Look for an instruction below MI in the MBB that kills the
487 /// specified register. Returns null if there are any other Reg use between the
490 MachineInstr *findLocalKill(unsigned Reg, MachineBasicBlock *MBB,
491 MachineInstr *MI, MachineRegisterInfo *MRI,
492 DenseMap<MachineInstr*, unsigned> &DistanceMap) {
493 MachineInstr *KillMI = 0;
494 for (MachineRegisterInfo::use_nodbg_iterator
495 UI = MRI->use_nodbg_begin(Reg),
496 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
497 MachineInstr *UseMI = &*UI;
498 if (UseMI == MI || UseMI->getParent() != MBB)
500 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
501 if (DI != DistanceMap.end())
503 if (!UI.getOperand().isKill())
506 return 0; // -O0 kill markers cannot be trusted?
513 /// findOnlyInterestingUse - Given a register, if has a single in-basic block
514 /// use, return the use instruction if it's a copy or a two-address use.
516 MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
517 MachineRegisterInfo *MRI,
518 const TargetInstrInfo *TII,
520 unsigned &DstReg, bool &IsDstPhys) {
521 if (!MRI->hasOneNonDBGUse(Reg))
522 // None or more than one use.
524 MachineInstr &UseMI = *MRI->use_nodbg_begin(Reg);
525 if (UseMI.getParent() != MBB)
529 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
534 if (isTwoAddrUse(UseMI, Reg, DstReg)) {
535 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
541 /// getMappedReg - Return the physical register the specified virtual register
542 /// might be mapped to.
544 getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
545 while (TargetRegisterInfo::isVirtualRegister(Reg)) {
546 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
547 if (SI == RegMap.end())
551 if (TargetRegisterInfo::isPhysicalRegister(Reg))
556 /// regsAreCompatible - Return true if the two registers are equal or aliased.
559 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
564 return TRI->regsOverlap(RegA, RegB);
568 /// isProfitableToReMat - Return true if it's potentially profitable to commute
569 /// the two-address instruction that's being processed.
571 TwoAddressInstructionPass::isProfitableToCommute(unsigned regB, unsigned regC,
572 MachineInstr *MI, MachineBasicBlock *MBB,
574 // Determine if it's profitable to commute this two address instruction. In
575 // general, we want no uses between this instruction and the definition of
576 // the two-address register.
578 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
579 // %reg1029<def> = MOV8rr %reg1028
580 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
581 // insert => %reg1030<def> = MOV8rr %reg1028
582 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
583 // In this case, it might not be possible to coalesce the second MOV8rr
584 // instruction if the first one is coalesced. So it would be profitable to
586 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
587 // %reg1029<def> = MOV8rr %reg1028
588 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
589 // insert => %reg1030<def> = MOV8rr %reg1029
590 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
592 if (!MI->killsRegister(regC))
595 // Ok, we have something like:
596 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
597 // let's see if it's worth commuting it.
599 // Look for situations like this:
600 // %reg1024<def> = MOV r1
601 // %reg1025<def> = MOV r0
602 // %reg1026<def> = ADD %reg1024, %reg1025
604 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
605 unsigned FromRegB = getMappedReg(regB, SrcRegMap);
606 unsigned FromRegC = getMappedReg(regC, SrcRegMap);
607 unsigned ToRegB = getMappedReg(regB, DstRegMap);
608 unsigned ToRegC = getMappedReg(regC, DstRegMap);
609 if ((FromRegB && ToRegB && !regsAreCompatible(FromRegB, ToRegB, TRI)) &&
610 ((!FromRegC && !ToRegC) ||
611 regsAreCompatible(FromRegB, ToRegC, TRI) ||
612 regsAreCompatible(FromRegC, ToRegB, TRI)))
615 // If there is a use of regC between its last def (could be livein) and this
616 // instruction, then bail.
617 unsigned LastDefC = 0;
618 if (!NoUseAfterLastDef(regC, MBB, Dist, LastDefC))
621 // If there is a use of regB between its last def (could be livein) and this
622 // instruction, then go ahead and make this transformation.
623 unsigned LastDefB = 0;
624 if (!NoUseAfterLastDef(regB, MBB, Dist, LastDefB))
627 // Since there are no intervening uses for both registers, then commute
628 // if the def of regC is closer. Its live interval is shorter.
629 return LastDefB && LastDefC && LastDefC > LastDefB;
632 /// CommuteInstruction - Commute a two-address instruction and update the basic
633 /// block, distance map, and live variables if needed. Return true if it is
636 TwoAddressInstructionPass::CommuteInstruction(MachineBasicBlock::iterator &mi,
637 MachineFunction::iterator &mbbi,
638 unsigned RegB, unsigned RegC, unsigned Dist) {
639 MachineInstr *MI = mi;
640 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
641 MachineInstr *NewMI = TII->commuteInstruction(MI);
644 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
648 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
649 // If the instruction changed to commute it, update livevar.
652 // Update live variables
653 LV->replaceKillInstruction(RegC, MI, NewMI);
655 mbbi->insert(mi, NewMI); // Insert the new inst
656 mbbi->erase(mi); // Nuke the old inst.
658 DistanceMap.insert(std::make_pair(NewMI, Dist));
661 // Update source register map.
662 unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
664 unsigned RegA = MI->getOperand(0).getReg();
665 SrcRegMap[RegA] = FromRegC;
671 /// isProfitableToConv3Addr - Return true if it is profitable to convert the
672 /// given 2-address instruction to a 3-address one.
674 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
675 // Look for situations like this:
676 // %reg1024<def> = MOV r1
677 // %reg1025<def> = MOV r0
678 // %reg1026<def> = ADD %reg1024, %reg1025
680 // Turn ADD into a 3-address instruction to avoid a copy.
681 unsigned FromRegB = getMappedReg(RegB, SrcRegMap);
684 unsigned ToRegA = getMappedReg(RegA, DstRegMap);
685 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI));
688 /// ConvertInstTo3Addr - Convert the specified two-address instruction into a
689 /// three address one. Return true if this transformation was successful.
691 TwoAddressInstructionPass::ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
692 MachineBasicBlock::iterator &nmi,
693 MachineFunction::iterator &mbbi,
694 unsigned RegA, unsigned RegB,
696 MachineInstr *NewMI = TII->convertToThreeAddress(mbbi, mi, LV);
698 DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
699 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
702 if (NewMI->findRegisterUseOperand(RegB, false, TRI))
703 // FIXME: Temporary workaround. If the new instruction doesn't
704 // uses RegB, convertToThreeAddress must have created more
705 // then one instruction.
706 Sunk = Sink3AddrInstruction(mbbi, NewMI, RegB, mi);
708 mbbi->erase(mi); // Nuke the old inst.
711 DistanceMap.insert(std::make_pair(NewMI, Dist));
713 nmi = llvm::next(mi);
716 // Update source and destination register maps.
717 SrcRegMap.erase(RegA);
718 DstRegMap.erase(RegB);
725 /// ScanUses - Scan forward recursively for only uses, update maps if the use
726 /// is a copy or a two-address instruction.
728 TwoAddressInstructionPass::ScanUses(unsigned DstReg, MachineBasicBlock *MBB,
729 SmallPtrSet<MachineInstr*, 8> &Processed) {
730 SmallVector<unsigned, 4> VirtRegPairs;
734 unsigned Reg = DstReg;
735 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy,
736 NewReg, IsDstPhys)) {
737 if (IsCopy && !Processed.insert(UseMI))
740 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
741 if (DI != DistanceMap.end())
742 // Earlier in the same MBB.Reached via a back edge.
746 VirtRegPairs.push_back(NewReg);
749 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
751 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
752 VirtRegPairs.push_back(NewReg);
756 if (!VirtRegPairs.empty()) {
757 unsigned ToReg = VirtRegPairs.back();
758 VirtRegPairs.pop_back();
759 while (!VirtRegPairs.empty()) {
760 unsigned FromReg = VirtRegPairs.back();
761 VirtRegPairs.pop_back();
762 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
764 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");
767 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;
769 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
773 /// ProcessCopy - If the specified instruction is not yet processed, process it
774 /// if it's a copy. For a copy instruction, we find the physical registers the
775 /// source and destination registers might be mapped to. These are kept in
776 /// point-to maps used to determine future optimizations. e.g.
779 /// v1026 = add v1024, v1025
781 /// If 'add' is a two-address instruction, v1024, v1026 are both potentially
782 /// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
783 /// potentially joined with r1 on the output side. It's worthwhile to commute
784 /// 'add' to eliminate a copy.
785 void TwoAddressInstructionPass::ProcessCopy(MachineInstr *MI,
786 MachineBasicBlock *MBB,
787 SmallPtrSet<MachineInstr*, 8> &Processed) {
788 if (Processed.count(MI))
791 bool IsSrcPhys, IsDstPhys;
792 unsigned SrcReg, DstReg;
793 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
796 if (IsDstPhys && !IsSrcPhys)
797 DstRegMap.insert(std::make_pair(SrcReg, DstReg));
798 else if (!IsDstPhys && IsSrcPhys) {
799 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
801 assert(SrcRegMap[DstReg] == SrcReg &&
802 "Can't map to two src physical registers!");
804 ScanUses(DstReg, MBB, Processed);
807 Processed.insert(MI);
811 /// isSafeToDelete - If the specified instruction does not produce any side
812 /// effects and all of its defs are dead, then it's safe to delete.
813 static bool isSafeToDelete(MachineInstr *MI,
814 const TargetInstrInfo *TII,
815 SmallVector<unsigned, 4> &Kills) {
816 const MCInstrDesc &MCID = MI->getDesc();
817 if (MCID.mayStore() || MCID.isCall())
819 if (MCID.isTerminator() || MI->hasUnmodeledSideEffects())
822 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
823 MachineOperand &MO = MI->getOperand(i);
826 if (MO.isDef() && !MO.isDead())
828 if (MO.isUse() && MO.isKill())
829 Kills.push_back(MO.getReg());
834 /// canUpdateDeletedKills - Check if all the registers listed in Kills are
835 /// killed by instructions in MBB preceding the current instruction at
836 /// position Dist. If so, return true and record information about the
837 /// preceding kills in NewKills.
838 bool TwoAddressInstructionPass::
839 canUpdateDeletedKills(SmallVector<unsigned, 4> &Kills,
840 SmallVector<NewKill, 4> &NewKills,
841 MachineBasicBlock *MBB, unsigned Dist) {
842 while (!Kills.empty()) {
843 unsigned Kill = Kills.back();
845 if (TargetRegisterInfo::isPhysicalRegister(Kill))
848 MachineInstr *LastKill = FindLastUseInMBB(Kill, MBB, Dist);
852 bool isModRef = LastKill->definesRegister(Kill);
853 NewKills.push_back(std::make_pair(std::make_pair(Kill, isModRef),
859 /// DeleteUnusedInstr - If an instruction with a tied register operand can
860 /// be safely deleted, just delete it.
862 TwoAddressInstructionPass::DeleteUnusedInstr(MachineBasicBlock::iterator &mi,
863 MachineBasicBlock::iterator &nmi,
864 MachineFunction::iterator &mbbi,
866 // Check if the instruction has no side effects and if all its defs are dead.
867 SmallVector<unsigned, 4> Kills;
868 if (!isSafeToDelete(mi, TII, Kills))
871 // If this instruction kills some virtual registers, we need to
872 // update the kill information. If it's not possible to do so,
874 SmallVector<NewKill, 4> NewKills;
875 if (!canUpdateDeletedKills(Kills, NewKills, &*mbbi, Dist))
879 while (!NewKills.empty()) {
880 MachineInstr *NewKill = NewKills.back().second;
881 unsigned Kill = NewKills.back().first.first;
882 bool isDead = NewKills.back().first.second;
884 if (LV->removeVirtualRegisterKilled(Kill, mi)) {
886 LV->addVirtualRegisterDead(Kill, NewKill);
888 LV->addVirtualRegisterKilled(Kill, NewKill);
893 mbbi->erase(mi); // Nuke the old inst.
898 /// RescheduleMIBelowKill - If there is one more local instruction that reads
899 /// 'Reg' and it kills 'Reg, consider moving the instruction below the kill
900 /// instruction in order to eliminate the need for the copy.
902 TwoAddressInstructionPass::RescheduleMIBelowKill(MachineBasicBlock *MBB,
903 MachineBasicBlock::iterator &mi,
904 MachineBasicBlock::iterator &nmi,
906 MachineInstr *MI = &*mi;
907 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
908 if (DI == DistanceMap.end())
909 // Must be created from unfolded load. Don't waste time trying this.
912 MachineInstr *KillMI = findLocalKill(Reg, MBB, mi, MRI, DistanceMap);
913 if (!KillMI || KillMI->isCopy() || KillMI->isCopyLike())
914 // Don't mess with copies, they may be coalesced later.
917 const MCInstrDesc &MCID = KillMI->getDesc();
918 if (MCID.hasUnmodeledSideEffects() || MCID.isCall() || MCID.isBranch() ||
920 // Don't move pass calls, etc.
924 if (isTwoAddrUse(*KillMI, Reg, DstReg))
927 bool SeenStore = true;
928 if (!MI->isSafeToMove(TII, AA, SeenStore))
931 if (TII->getInstrLatency(InstrItins, MI) > 1)
932 // FIXME: Needs more sophisticated heuristics.
935 SmallSet<unsigned, 2> Uses;
936 SmallSet<unsigned, 2> Kills;
937 SmallSet<unsigned, 2> Defs;
938 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
939 const MachineOperand &MO = MI->getOperand(i);
942 unsigned MOReg = MO.getReg();
949 if (MO.isKill() && MOReg != Reg)
954 // Move the copies connected to MI down as well.
955 MachineBasicBlock::iterator From = MI;
956 MachineBasicBlock::iterator To = llvm::next(From);
957 while (To->isCopy() && Defs.count(To->getOperand(1).getReg())) {
958 Defs.insert(To->getOperand(0).getReg());
962 // Check if the reschedule will not break depedencies.
963 unsigned NumVisited = 0;
964 MachineBasicBlock::iterator KillPos = KillMI;
966 for (MachineBasicBlock::iterator I = To; I != KillPos; ++I) {
967 MachineInstr *OtherMI = I;
968 // DBG_VALUE cannot be counted against the limit.
969 if (OtherMI->isDebugValue())
971 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
974 const MCInstrDesc &OMCID = OtherMI->getDesc();
975 if (OMCID.hasUnmodeledSideEffects() || OMCID.isCall() || OMCID.isBranch() ||
976 OMCID.isTerminator())
977 // Don't move pass calls, etc.
979 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
980 const MachineOperand &MO = OtherMI->getOperand(i);
983 unsigned MOReg = MO.getReg();
987 if (Uses.count(MOReg))
988 // Physical register use would be clobbered.
990 if (!MO.isDead() && Defs.count(MOReg))
991 // May clobber a physical register def.
992 // FIXME: This may be too conservative. It's ok if the instruction
993 // is sunken completely below the use.
996 if (Defs.count(MOReg))
999 ((MO.isKill() && Uses.count(MOReg)) || Kills.count(MOReg)))
1000 // Don't want to extend other live ranges and update kills.
1006 // Move debug info as well.
1007 while (From != MBB->begin() && llvm::prior(From)->isDebugValue())
1010 // Copies following MI may have been moved as well.
1012 MBB->splice(KillPos, MBB, From, To);
1013 DistanceMap.erase(DI);
1016 // Update live variables
1017 LV->removeVirtualRegisterKilled(Reg, KillMI);
1018 LV->addVirtualRegisterKilled(Reg, MI);
1020 for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) {
1021 MachineOperand &MO = KillMI->getOperand(i);
1022 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
1024 MO.setIsKill(false);
1026 MI->addRegisterKilled(Reg, 0);
1032 /// isDefTooClose - Return true if the re-scheduling will put the given
1033 /// instruction too close to the defs of its register dependencies.
1034 bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
1036 MachineBasicBlock *MBB) {
1037 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(Reg),
1038 DE = MRI->def_end(); DI != DE; ++DI) {
1039 MachineInstr *DefMI = &*DI;
1040 if (DefMI->getParent() != MBB || DefMI->isCopy() || DefMI->isCopyLike())
1043 return true; // MI is defining something KillMI uses
1044 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(DefMI);
1045 if (DDI == DistanceMap.end())
1046 return true; // Below MI
1047 unsigned DefDist = DDI->second;
1048 assert(Dist > DefDist && "Visited def already?");
1049 if (TII->getInstrLatency(InstrItins, DefMI) > (int)(Dist - DefDist))
1055 /// RescheduleKillAboveMI - If there is one more local instruction that reads
1056 /// 'Reg' and it kills 'Reg, consider moving the kill instruction above the
1057 /// current two-address instruction in order to eliminate the need for the
1060 TwoAddressInstructionPass::RescheduleKillAboveMI(MachineBasicBlock *MBB,
1061 MachineBasicBlock::iterator &mi,
1062 MachineBasicBlock::iterator &nmi,
1064 MachineInstr *MI = &*mi;
1065 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
1066 if (DI == DistanceMap.end())
1067 // Must be created from unfolded load. Don't waste time trying this.
1070 MachineInstr *KillMI = findLocalKill(Reg, MBB, mi, MRI, DistanceMap);
1071 if (!KillMI || KillMI->isCopy() || KillMI->isCopyLike())
1072 // Don't mess with copies, they may be coalesced later.
1076 if (isTwoAddrUse(*KillMI, Reg, DstReg))
1079 bool SeenStore = true;
1080 if (!KillMI->isSafeToMove(TII, AA, SeenStore))
1083 SmallSet<unsigned, 2> Uses;
1084 SmallSet<unsigned, 2> Kills;
1085 SmallSet<unsigned, 2> Defs;
1086 SmallSet<unsigned, 2> LiveDefs;
1087 for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) {
1088 const MachineOperand &MO = KillMI->getOperand(i);
1091 unsigned MOReg = MO.getReg();
1095 if (isDefTooClose(MOReg, DI->second, MI, MBB))
1098 if (MO.isKill() && MOReg != Reg)
1099 Kills.insert(MOReg);
1100 } else if (TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1103 LiveDefs.insert(MOReg);
1107 // Check if the reschedule will not break depedencies.
1108 unsigned NumVisited = 0;
1109 MachineBasicBlock::iterator KillPos = KillMI;
1110 for (MachineBasicBlock::iterator I = mi; I != KillPos; ++I) {
1111 MachineInstr *OtherMI = I;
1112 // DBG_VALUE cannot be counted against the limit.
1113 if (OtherMI->isDebugValue())
1115 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
1118 const MCInstrDesc &MCID = OtherMI->getDesc();
1119 if (MCID.hasUnmodeledSideEffects() || MCID.isCall() || MCID.isBranch() ||
1120 MCID.isTerminator())
1121 // Don't move pass calls, etc.
1123 SmallVector<unsigned, 2> OtherDefs;
1124 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
1125 const MachineOperand &MO = OtherMI->getOperand(i);
1128 unsigned MOReg = MO.getReg();
1132 if (Defs.count(MOReg))
1133 // Moving KillMI can clobber the physical register if the def has
1136 if (Kills.count(MOReg))
1137 // Don't want to extend other live ranges and update kills.
1140 OtherDefs.push_back(MOReg);
1144 for (unsigned i = 0, e = OtherDefs.size(); i != e; ++i) {
1145 unsigned MOReg = OtherDefs[i];
1146 if (Uses.count(MOReg))
1148 if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1149 LiveDefs.count(MOReg))
1151 // Physical register def is seen.
1156 // Move the old kill above MI, don't forget to move debug info as well.
1157 MachineBasicBlock::iterator InsertPos = mi;
1158 while (InsertPos != MBB->begin() && llvm::prior(InsertPos)->isDebugValue())
1160 MachineBasicBlock::iterator From = KillMI;
1161 MachineBasicBlock::iterator To = llvm::next(From);
1162 while (llvm::prior(From)->isDebugValue())
1164 MBB->splice(InsertPos, MBB, From, To);
1166 nmi = llvm::prior(InsertPos); // Backtrack so we process the moved instr.
1167 DistanceMap.erase(DI);
1170 // Update live variables
1171 LV->removeVirtualRegisterKilled(Reg, KillMI);
1172 LV->addVirtualRegisterKilled(Reg, MI);
1174 for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) {
1175 MachineOperand &MO = KillMI->getOperand(i);
1176 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
1178 MO.setIsKill(false);
1180 MI->addRegisterKilled(Reg, 0);
1185 /// TryInstructionTransform - For the case where an instruction has a single
1186 /// pair of tied register operands, attempt some transformations that may
1187 /// either eliminate the tied operands or improve the opportunities for
1188 /// coalescing away the register copy. Returns true if the tied operands
1189 /// are eliminated altogether.
1190 bool TwoAddressInstructionPass::
1191 TryInstructionTransform(MachineBasicBlock::iterator &mi,
1192 MachineBasicBlock::iterator &nmi,
1193 MachineFunction::iterator &mbbi,
1194 unsigned SrcIdx, unsigned DstIdx, unsigned Dist,
1195 SmallPtrSet<MachineInstr*, 8> &Processed) {
1196 MachineInstr &MI = *mi;
1197 const MCInstrDesc &MCID = MI.getDesc();
1198 unsigned regA = MI.getOperand(DstIdx).getReg();
1199 unsigned regB = MI.getOperand(SrcIdx).getReg();
1201 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
1202 "cannot make instruction into two-address form");
1204 // If regA is dead and the instruction can be deleted, just delete
1205 // it so it doesn't clobber regB.
1206 bool regBKilled = isKilled(MI, regB, MRI, TII);
1207 if (!regBKilled && MI.getOperand(DstIdx).isDead() &&
1208 DeleteUnusedInstr(mi, nmi, mbbi, Dist)) {
1210 return true; // Done with this instruction.
1213 // Check if it is profitable to commute the operands.
1214 unsigned SrcOp1, SrcOp2;
1216 unsigned regCIdx = ~0U;
1217 bool TryCommute = false;
1218 bool AggressiveCommute = false;
1219 if (MCID.isCommutable() && MI.getNumOperands() >= 3 &&
1220 TII->findCommutedOpIndices(&MI, SrcOp1, SrcOp2)) {
1221 if (SrcIdx == SrcOp1)
1223 else if (SrcIdx == SrcOp2)
1226 if (regCIdx != ~0U) {
1227 regC = MI.getOperand(regCIdx).getReg();
1228 if (!regBKilled && isKilled(MI, regC, MRI, TII))
1229 // If C dies but B does not, swap the B and C operands.
1230 // This makes the live ranges of A and C joinable.
1232 else if (isProfitableToCommute(regB, regC, &MI, mbbi, Dist)) {
1234 AggressiveCommute = true;
1239 // If it's profitable to commute, try to do so.
1240 if (TryCommute && CommuteInstruction(mi, mbbi, regB, regC, Dist)) {
1242 if (AggressiveCommute)
1247 // If there is one more use of regB later in the same MBB, consider
1248 // re-schedule this MI below it.
1249 if (RescheduleMIBelowKill(mbbi, mi, nmi, regB)) {
1254 if (TargetRegisterInfo::isVirtualRegister(regA))
1255 ScanUses(regA, &*mbbi, Processed);
1257 if (MCID.isConvertibleTo3Addr()) {
1258 // This instruction is potentially convertible to a true
1259 // three-address instruction. Check if it is profitable.
1260 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1261 // Try to convert it.
1262 if (ConvertInstTo3Addr(mi, nmi, mbbi, regA, regB, Dist)) {
1263 ++NumConvertedTo3Addr;
1264 return true; // Done with this instruction.
1269 // If there is one more use of regB later in the same MBB, consider
1270 // re-schedule it before this MI if it's legal.
1271 if (RescheduleKillAboveMI(mbbi, mi, nmi, regB)) {
1276 // If this is an instruction with a load folded into it, try unfolding
1277 // the load, e.g. avoid this:
1279 // addq (%rax), %rcx
1280 // in favor of this:
1281 // movq (%rax), %rcx
1283 // because it's preferable to schedule a load than a register copy.
1284 if (MCID.mayLoad() && !regBKilled) {
1285 // Determine if a load can be unfolded.
1286 unsigned LoadRegIndex;
1288 TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
1289 /*UnfoldLoad=*/true,
1290 /*UnfoldStore=*/false,
1293 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
1294 if (UnfoldMCID.getNumDefs() == 1) {
1295 MachineFunction &MF = *mbbi->getParent();
1298 DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
1299 const TargetRegisterClass *RC =
1300 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI);
1301 unsigned Reg = MRI->createVirtualRegister(RC);
1302 SmallVector<MachineInstr *, 2> NewMIs;
1303 if (!TII->unfoldMemoryOperand(MF, &MI, Reg,
1304 /*UnfoldLoad=*/true,/*UnfoldStore=*/false,
1306 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1309 assert(NewMIs.size() == 2 &&
1310 "Unfolded a load into multiple instructions!");
1311 // The load was previously folded, so this is the only use.
1312 NewMIs[1]->addRegisterKilled(Reg, TRI);
1314 // Tentatively insert the instructions into the block so that they
1315 // look "normal" to the transformation logic.
1316 mbbi->insert(mi, NewMIs[0]);
1317 mbbi->insert(mi, NewMIs[1]);
1319 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1320 << "2addr: NEW INST: " << *NewMIs[1]);
1322 // Transform the instruction, now that it no longer has a load.
1323 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1324 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1325 MachineBasicBlock::iterator NewMI = NewMIs[1];
1326 bool TransformSuccess =
1327 TryInstructionTransform(NewMI, mi, mbbi,
1328 NewSrcIdx, NewDstIdx, Dist, Processed);
1329 if (TransformSuccess ||
1330 NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1331 // Success, or at least we made an improvement. Keep the unfolded
1332 // instructions and discard the original.
1334 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1335 MachineOperand &MO = MI.getOperand(i);
1337 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
1340 if (NewMIs[0]->killsRegister(MO.getReg()))
1341 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]);
1343 assert(NewMIs[1]->killsRegister(MO.getReg()) &&
1344 "Kill missing after load unfold!");
1345 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]);
1348 } else if (LV->removeVirtualRegisterDead(MO.getReg(), &MI)) {
1349 if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1350 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);
1352 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
1353 "Dead flag missing after load unfold!");
1354 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]);
1359 LV->addVirtualRegisterKilled(Reg, NewMIs[1]);
1361 MI.eraseFromParent();
1363 if (TransformSuccess)
1366 // Transforming didn't eliminate the tie and didn't lead to an
1367 // improvement. Clean up the unfolded instructions and keep the
1369 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1370 NewMIs[0]->eraseFromParent();
1371 NewMIs[1]->eraseFromParent();
1380 /// runOnMachineFunction - Reduce two-address instructions to two operands.
1382 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
1383 DEBUG(dbgs() << "Machine Function\n");
1384 const TargetMachine &TM = MF.getTarget();
1385 MRI = &MF.getRegInfo();
1386 TII = TM.getInstrInfo();
1387 TRI = TM.getRegisterInfo();
1388 InstrItins = TM.getInstrItineraryData();
1389 LV = getAnalysisIfAvailable<LiveVariables>();
1390 AA = &getAnalysis<AliasAnalysis>();
1392 bool MadeChange = false;
1394 DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
1395 DEBUG(dbgs() << "********** Function: "
1396 << MF.getFunction()->getName() << '\n');
1398 // This pass takes the function out of SSA form.
1401 // ReMatRegs - Keep track of the registers whose def's are remat'ed.
1402 BitVector ReMatRegs(MRI->getNumVirtRegs());
1404 typedef DenseMap<unsigned, SmallVector<std::pair<unsigned, unsigned>, 4> >
1406 TiedOperandMap TiedOperands(4);
1408 SmallPtrSet<MachineInstr*, 8> Processed;
1409 for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
1410 mbbi != mbbe; ++mbbi) {
1412 DistanceMap.clear();
1416 for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
1418 MachineBasicBlock::iterator nmi = llvm::next(mi);
1419 if (mi->isDebugValue()) {
1424 // Remember REG_SEQUENCE instructions, we'll deal with them later.
1425 if (mi->isRegSequence())
1426 RegSequences.push_back(&*mi);
1428 const MCInstrDesc &MCID = mi->getDesc();
1429 bool FirstTied = true;
1431 DistanceMap.insert(std::make_pair(mi, ++Dist));
1433 ProcessCopy(&*mi, &*mbbi, Processed);
1435 // First scan through all the tied register uses in this instruction
1436 // and record a list of pairs of tied operands for each register.
1437 unsigned NumOps = mi->isInlineAsm()
1438 ? mi->getNumOperands() : MCID.getNumOperands();
1439 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1440 unsigned DstIdx = 0;
1441 if (!mi->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1446 ++NumTwoAddressInstrs;
1447 DEBUG(dbgs() << '\t' << *mi);
1450 assert(mi->getOperand(SrcIdx).isReg() &&
1451 mi->getOperand(SrcIdx).getReg() &&
1452 mi->getOperand(SrcIdx).isUse() &&
1453 "two address instruction invalid");
1455 unsigned regB = mi->getOperand(SrcIdx).getReg();
1456 TiedOperands[regB].push_back(std::make_pair(SrcIdx, DstIdx));
1459 // Now iterate over the information collected above.
1460 for (TiedOperandMap::iterator OI = TiedOperands.begin(),
1461 OE = TiedOperands.end(); OI != OE; ++OI) {
1462 SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs = OI->second;
1464 // If the instruction has a single pair of tied operands, try some
1465 // transformations that may either eliminate the tied operands or
1466 // improve the opportunities for coalescing away the register copy.
1467 if (TiedOperands.size() == 1 && TiedPairs.size() == 1) {
1468 unsigned SrcIdx = TiedPairs[0].first;
1469 unsigned DstIdx = TiedPairs[0].second;
1471 // If the registers are already equal, nothing needs to be done.
1472 if (mi->getOperand(SrcIdx).getReg() ==
1473 mi->getOperand(DstIdx).getReg())
1474 break; // Done with this instruction.
1476 if (TryInstructionTransform(mi, nmi, mbbi, SrcIdx, DstIdx, Dist,
1478 break; // The tied operands have been eliminated.
1481 bool IsEarlyClobber = false;
1482 bool RemovedKillFlag = false;
1483 bool AllUsesCopied = true;
1484 unsigned LastCopiedReg = 0;
1485 unsigned regB = OI->first;
1486 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1487 unsigned SrcIdx = TiedPairs[tpi].first;
1488 unsigned DstIdx = TiedPairs[tpi].second;
1490 const MachineOperand &DstMO = mi->getOperand(DstIdx);
1491 unsigned regA = DstMO.getReg();
1492 IsEarlyClobber |= DstMO.isEarlyClobber();
1494 // Grab regB from the instruction because it may have changed if the
1495 // instruction was commuted.
1496 regB = mi->getOperand(SrcIdx).getReg();
1499 // The register is tied to multiple destinations (or else we would
1500 // not have continued this far), but this use of the register
1501 // already matches the tied destination. Leave it.
1502 AllUsesCopied = false;
1505 LastCopiedReg = regA;
1507 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
1508 "cannot make instruction into two-address form");
1511 // First, verify that we don't have a use of "a" in the instruction
1512 // (a = b + a for example) because our transformation will not
1513 // work. This should never occur because we are in SSA form.
1514 for (unsigned i = 0; i != mi->getNumOperands(); ++i)
1515 assert(i == DstIdx ||
1516 !mi->getOperand(i).isReg() ||
1517 mi->getOperand(i).getReg() != regA);
1520 // Emit a copy or rematerialize the definition.
1521 const TargetRegisterClass *rc = MRI->getRegClass(regB);
1522 MachineInstr *DefMI = MRI->getVRegDef(regB);
1523 // If it's safe and profitable, remat the definition instead of
1526 DefMI->getDesc().isAsCheapAsAMove() &&
1527 DefMI->isSafeToReMat(TII, AA, regB) &&
1528 isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){
1529 DEBUG(dbgs() << "2addr: REMATTING : " << *DefMI << "\n");
1530 unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg();
1531 TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, *TRI);
1532 ReMatRegs.set(TargetRegisterInfo::virtReg2Index(regB));
1535 BuildMI(*mbbi, mi, mi->getDebugLoc(), TII->get(TargetOpcode::COPY),
1539 MachineBasicBlock::iterator prevMI = prior(mi);
1540 // Update DistanceMap.
1541 DistanceMap.insert(std::make_pair(prevMI, Dist));
1542 DistanceMap[mi] = ++Dist;
1544 DEBUG(dbgs() << "\t\tprepend:\t" << *prevMI);
1546 MachineOperand &MO = mi->getOperand(SrcIdx);
1547 assert(MO.isReg() && MO.getReg() == regB && MO.isUse() &&
1548 "inconsistent operand info for 2-reg pass");
1550 MO.setIsKill(false);
1551 RemovedKillFlag = true;
1556 if (AllUsesCopied) {
1557 if (!IsEarlyClobber) {
1558 // Replace other (un-tied) uses of regB with LastCopiedReg.
1559 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
1560 MachineOperand &MO = mi->getOperand(i);
1561 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
1563 MO.setIsKill(false);
1564 RemovedKillFlag = true;
1566 MO.setReg(LastCopiedReg);
1571 // Update live variables for regB.
1572 if (RemovedKillFlag && LV && LV->getVarInfo(regB).removeKill(mi))
1573 LV->addVirtualRegisterKilled(regB, prior(mi));
1575 } else if (RemovedKillFlag) {
1576 // Some tied uses of regB matched their destination registers, so
1577 // regB is still used in this instruction, but a kill flag was
1578 // removed from a different tied use of regB, so now we need to add
1579 // a kill flag to one of the remaining uses of regB.
1580 for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
1581 MachineOperand &MO = mi->getOperand(i);
1582 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) {
1589 // Schedule the source copy / remat inserted to form two-address
1590 // instruction. FIXME: Does it matter the distance map may not be
1591 // accurate after it's scheduled?
1592 TII->scheduleTwoAddrSource(prior(mi), mi, *TRI);
1596 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1599 // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
1600 if (mi->isInsertSubreg()) {
1601 // From %reg = INSERT_SUBREG %reg, %subreg, subidx
1602 // To %reg:subidx = COPY %subreg
1603 unsigned SubIdx = mi->getOperand(3).getImm();
1604 mi->RemoveOperand(3);
1605 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1606 mi->getOperand(0).setSubReg(SubIdx);
1607 mi->RemoveOperand(1);
1608 mi->setDesc(TII->get(TargetOpcode::COPY));
1609 DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
1612 // Clear TiedOperands here instead of at the top of the loop
1613 // since most instructions do not have tied operands.
1614 TiedOperands.clear();
1619 // Some remat'ed instructions are dead.
1620 for (int i = ReMatRegs.find_first(); i != -1; i = ReMatRegs.find_next(i)) {
1621 unsigned VReg = TargetRegisterInfo::index2VirtReg(i);
1622 if (MRI->use_nodbg_empty(VReg)) {
1623 MachineInstr *DefMI = MRI->getVRegDef(VReg);
1624 DefMI->eraseFromParent();
1628 // Eliminate REG_SEQUENCE instructions. Their whole purpose was to preseve
1629 // SSA form. It's now safe to de-SSA.
1630 MadeChange |= EliminateRegSequences();
1635 static void UpdateRegSequenceSrcs(unsigned SrcReg,
1636 unsigned DstReg, unsigned SubIdx,
1637 MachineRegisterInfo *MRI,
1638 const TargetRegisterInfo &TRI) {
1639 for (MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(SrcReg),
1640 RE = MRI->reg_end(); RI != RE; ) {
1641 MachineOperand &MO = RI.getOperand();
1643 MO.substVirtReg(DstReg, SubIdx, TRI);
1647 /// CoalesceExtSubRegs - If a number of sources of the REG_SEQUENCE are
1648 /// EXTRACT_SUBREG from the same register and to the same virtual register
1649 /// with different sub-register indices, attempt to combine the
1650 /// EXTRACT_SUBREGs and pre-coalesce them. e.g.
1651 /// %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
1652 /// %reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
1653 /// %reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5
1654 /// Since D subregs 5, 6 can combine to a Q register, we can coalesce
1655 /// reg1026 to reg1029.
1657 TwoAddressInstructionPass::CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs,
1659 SmallSet<unsigned, 4> Seen;
1660 for (unsigned i = 0, e = Srcs.size(); i != e; ++i) {
1661 unsigned SrcReg = Srcs[i];
1662 if (!Seen.insert(SrcReg))
1665 // Check that the instructions are all in the same basic block.
1666 MachineInstr *SrcDefMI = MRI->getVRegDef(SrcReg);
1667 MachineInstr *DstDefMI = MRI->getVRegDef(DstReg);
1668 if (SrcDefMI->getParent() != DstDefMI->getParent())
1671 // If there are no other uses than copies which feed into
1672 // the reg_sequence, then we might be able to coalesce them.
1673 bool CanCoalesce = true;
1674 SmallVector<unsigned, 4> SrcSubIndices, DstSubIndices;
1675 for (MachineRegisterInfo::use_nodbg_iterator
1676 UI = MRI->use_nodbg_begin(SrcReg),
1677 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
1678 MachineInstr *UseMI = &*UI;
1679 if (!UseMI->isCopy() || UseMI->getOperand(0).getReg() != DstReg) {
1680 CanCoalesce = false;
1683 SrcSubIndices.push_back(UseMI->getOperand(1).getSubReg());
1684 DstSubIndices.push_back(UseMI->getOperand(0).getSubReg());
1687 if (!CanCoalesce || SrcSubIndices.size() < 2)
1690 // Check that the source subregisters can be combined.
1691 std::sort(SrcSubIndices.begin(), SrcSubIndices.end());
1692 unsigned NewSrcSubIdx = 0;
1693 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(SrcReg), SrcSubIndices,
1697 // Check that the destination subregisters can also be combined.
1698 std::sort(DstSubIndices.begin(), DstSubIndices.end());
1699 unsigned NewDstSubIdx = 0;
1700 if (!TRI->canCombineSubRegIndices(MRI->getRegClass(DstReg), DstSubIndices,
1704 // If neither source nor destination can be combined to the full register,
1705 // just give up. This could be improved if it ever matters.
1706 if (NewSrcSubIdx != 0 && NewDstSubIdx != 0)
1709 // Now that we know that all the uses are extract_subregs and that those
1710 // subregs can somehow be combined, scan all the extract_subregs again to
1711 // make sure the subregs are in the right order and can be composed.
1712 MachineInstr *SomeMI = 0;
1714 for (MachineRegisterInfo::use_nodbg_iterator
1715 UI = MRI->use_nodbg_begin(SrcReg),
1716 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
1717 MachineInstr *UseMI = &*UI;
1718 assert(UseMI->isCopy());
1719 unsigned DstSubIdx = UseMI->getOperand(0).getSubReg();
1720 unsigned SrcSubIdx = UseMI->getOperand(1).getSubReg();
1721 assert(DstSubIdx != 0 && "missing subreg from RegSequence elimination");
1722 if ((NewDstSubIdx == 0 &&
1723 TRI->composeSubRegIndices(NewSrcSubIdx, DstSubIdx) != SrcSubIdx) ||
1724 (NewSrcSubIdx == 0 &&
1725 TRI->composeSubRegIndices(NewDstSubIdx, SrcSubIdx) != DstSubIdx)) {
1726 CanCoalesce = false;
1729 // Keep track of one of the uses.
1735 // Insert a copy to replace the original.
1736 MachineInstr *CopyMI = BuildMI(*SomeMI->getParent(), SomeMI,
1737 SomeMI->getDebugLoc(),
1738 TII->get(TargetOpcode::COPY))
1739 .addReg(DstReg, RegState::Define, NewDstSubIdx)
1740 .addReg(SrcReg, 0, NewSrcSubIdx);
1742 // Remove all the old extract instructions.
1743 for (MachineRegisterInfo::use_nodbg_iterator
1744 UI = MRI->use_nodbg_begin(SrcReg),
1745 UE = MRI->use_nodbg_end(); UI != UE; ) {
1746 MachineInstr *UseMI = &*UI;
1748 if (UseMI == CopyMI)
1750 assert(UseMI->isCopy());
1751 // Move any kills to the new copy or extract instruction.
1752 if (UseMI->getOperand(1).isKill()) {
1753 CopyMI->getOperand(1).setIsKill();
1755 // Update live variables
1756 LV->replaceKillInstruction(SrcReg, UseMI, &*CopyMI);
1758 UseMI->eraseFromParent();
1763 static bool HasOtherRegSequenceUses(unsigned Reg, MachineInstr *RegSeq,
1764 MachineRegisterInfo *MRI) {
1765 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(Reg),
1766 UE = MRI->use_end(); UI != UE; ++UI) {
1767 MachineInstr *UseMI = &*UI;
1768 if (UseMI != RegSeq && UseMI->isRegSequence())
1774 /// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
1775 /// of the de-ssa process. This replaces sources of REG_SEQUENCE as
1776 /// sub-register references of the register defined by REG_SEQUENCE. e.g.
1778 /// %reg1029<def>, %reg1030<def> = VLD1q16 %reg1024<kill>, ...
1779 /// %reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6
1781 /// %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
1782 bool TwoAddressInstructionPass::EliminateRegSequences() {
1783 if (RegSequences.empty())
1786 for (unsigned i = 0, e = RegSequences.size(); i != e; ++i) {
1787 MachineInstr *MI = RegSequences[i];
1788 unsigned DstReg = MI->getOperand(0).getReg();
1789 if (MI->getOperand(0).getSubReg() ||
1790 TargetRegisterInfo::isPhysicalRegister(DstReg) ||
1791 !(MI->getNumOperands() & 1)) {
1792 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
1793 llvm_unreachable(0);
1796 bool IsImpDef = true;
1797 SmallVector<unsigned, 4> RealSrcs;
1798 SmallSet<unsigned, 4> Seen;
1799 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
1800 unsigned SrcReg = MI->getOperand(i).getReg();
1801 unsigned SubIdx = MI->getOperand(i+1).getImm();
1802 if (MI->getOperand(i).getSubReg() ||
1803 TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
1804 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
1805 llvm_unreachable(0);
1808 MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
1809 if (DefMI->isImplicitDef()) {
1810 DefMI->eraseFromParent();
1815 // Remember COPY sources. These might be candidate for coalescing.
1816 if (DefMI->isCopy() && DefMI->getOperand(1).getSubReg())
1817 RealSrcs.push_back(DefMI->getOperand(1).getReg());
1819 bool isKill = MI->getOperand(i).isKill();
1820 if (!Seen.insert(SrcReg) || MI->getParent() != DefMI->getParent() ||
1821 !isKill || HasOtherRegSequenceUses(SrcReg, MI, MRI) ||
1822 !TRI->getMatchingSuperRegClass(MRI->getRegClass(DstReg),
1823 MRI->getRegClass(SrcReg), SubIdx)) {
1824 // REG_SEQUENCE cannot have duplicated operands, add a copy.
1825 // Also add an copy if the source is live-in the block. We don't want
1826 // to end up with a partial-redef of a livein, e.g.
1828 // reg1051:10<def> =
1834 // LiveIntervalAnalysis won't like it.
1836 // If the REG_SEQUENCE doesn't kill its source, keeping live variables
1837 // correctly up to date becomes very difficult. Insert a copy.
1839 // Defer any kill flag to the last operand using SrcReg. Otherwise, we
1840 // might insert a COPY that uses SrcReg after is was killed.
1842 for (unsigned j = i + 2; j < e; j += 2)
1843 if (MI->getOperand(j).getReg() == SrcReg) {
1844 MI->getOperand(j).setIsKill();
1849 MachineBasicBlock::iterator InsertLoc = MI;
1850 MachineInstr *CopyMI = BuildMI(*MI->getParent(), InsertLoc,
1851 MI->getDebugLoc(), TII->get(TargetOpcode::COPY))
1852 .addReg(DstReg, RegState::Define, SubIdx)
1853 .addReg(SrcReg, getKillRegState(isKill));
1854 MI->getOperand(i).setReg(0);
1856 LV->replaceKillInstruction(SrcReg, MI, CopyMI);
1857 DEBUG(dbgs() << "Inserted: " << *CopyMI);
1861 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
1862 unsigned SrcReg = MI->getOperand(i).getReg();
1863 if (!SrcReg) continue;
1864 unsigned SubIdx = MI->getOperand(i+1).getImm();
1865 UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI);
1869 DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF");
1870 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
1871 for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
1872 MI->RemoveOperand(j);
1874 DEBUG(dbgs() << "Eliminated: " << *MI);
1875 MI->eraseFromParent();
1878 // Try coalescing some EXTRACT_SUBREG instructions. This can create
1879 // INSERT_SUBREG instructions that must have <undef> flags added by
1880 // LiveIntervalAnalysis, so only run it when LiveVariables is available.
1882 CoalesceExtSubRegs(RealSrcs, DstReg);
1885 RegSequences.clear();