1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TwoAddress instruction pass which is used
11 // by most register allocators. Two-Address instructions are rewritten
21 // Note that if a register allocator chooses to use this pass, that it
22 // has to be capable of handling the non-SSA nature of these rewritten
25 // It is also worth noting that the duplicate operand of the two
26 // address instruction is removed.
28 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "twoaddrinstr"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/ADT/BitVector.h"
33 #include "llvm/ADT/DenseMap.h"
34 #include "llvm/ADT/STLExtras.h"
35 #include "llvm/ADT/SmallSet.h"
36 #include "llvm/ADT/Statistic.h"
37 #include "llvm/Analysis/AliasAnalysis.h"
38 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
39 #include "llvm/CodeGen/LiveVariables.h"
40 #include "llvm/CodeGen/MachineFunctionPass.h"
41 #include "llvm/CodeGen/MachineInstr.h"
42 #include "llvm/CodeGen/MachineInstrBuilder.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/MC/MCInstrItineraries.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetMachine.h"
51 #include "llvm/Target/TargetRegisterInfo.h"
54 STATISTIC(NumTwoAddressInstrs, "Number of two-address instructions");
55 STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
56 STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
57 STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
58 STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
59 STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");
60 STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");
62 // Temporary flag to disable rescheduling.
64 EnableRescheduling("twoaddr-reschedule",
65 cl::desc("Coalesce copies by rescheduling (default=true)"), cl::init(true), cl::Hidden);
68 class TwoAddressInstructionPass : public MachineFunctionPass {
70 const TargetInstrInfo *TII;
71 const TargetRegisterInfo *TRI;
72 const InstrItineraryData *InstrItins;
73 MachineRegisterInfo *MRI;
77 CodeGenOpt::Level OptLevel;
79 // The current basic block being processed.
80 MachineBasicBlock *MBB;
82 // DistanceMap - Keep track the distance of a MI from the start of the
83 // current basic block.
84 DenseMap<MachineInstr*, unsigned> DistanceMap;
86 // Set of already processed instructions in the current block.
87 SmallPtrSet<MachineInstr*, 8> Processed;
89 // SrcRegMap - A map from virtual registers to physical registers which are
90 // likely targets to be coalesced to due to copies from physical registers to
91 // virtual registers. e.g. v1024 = move r0.
92 DenseMap<unsigned, unsigned> SrcRegMap;
94 // DstRegMap - A map from virtual registers to physical registers which are
95 // likely targets to be coalesced to due to copies to physical registers from
96 // virtual registers. e.g. r1 = move v1024.
97 DenseMap<unsigned, unsigned> DstRegMap;
99 bool sink3AddrInstruction(MachineInstr *MI, unsigned Reg,
100 MachineBasicBlock::iterator OldPos);
102 bool noUseAfterLastDef(unsigned Reg, unsigned Dist, unsigned &LastDef);
104 bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
105 MachineInstr *MI, unsigned Dist);
107 bool commuteInstruction(MachineBasicBlock::iterator &mi,
108 unsigned RegB, unsigned RegC, unsigned Dist);
110 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
112 bool convertInstTo3Addr(MachineBasicBlock::iterator &mi,
113 MachineBasicBlock::iterator &nmi,
114 unsigned RegA, unsigned RegB, unsigned Dist);
116 bool isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI);
118 bool rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
119 MachineBasicBlock::iterator &nmi,
121 bool rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
122 MachineBasicBlock::iterator &nmi,
125 bool tryInstructionTransform(MachineBasicBlock::iterator &mi,
126 MachineBasicBlock::iterator &nmi,
127 unsigned SrcIdx, unsigned DstIdx,
128 unsigned Dist, bool shouldOnlyCommute);
130 void scanUses(unsigned DstReg);
132 void processCopy(MachineInstr *MI);
134 typedef SmallVector<std::pair<unsigned, unsigned>, 4> TiedPairList;
135 typedef SmallDenseMap<unsigned, TiedPairList> TiedOperandMap;
136 bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
137 void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
138 void eliminateRegSequence(MachineBasicBlock::iterator&);
141 static char ID; // Pass identification, replacement for typeid
142 TwoAddressInstructionPass() : MachineFunctionPass(ID) {
143 initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
146 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
147 AU.setPreservesCFG();
148 AU.addRequired<AliasAnalysis>();
149 AU.addPreserved<LiveVariables>();
150 AU.addPreserved<SlotIndexes>();
151 AU.addPreserved<LiveIntervals>();
152 AU.addPreservedID(MachineLoopInfoID);
153 AU.addPreservedID(MachineDominatorsID);
154 MachineFunctionPass::getAnalysisUsage(AU);
157 /// runOnMachineFunction - Pass entry point.
158 bool runOnMachineFunction(MachineFunction&);
160 } // end anonymous namespace
162 char TwoAddressInstructionPass::ID = 0;
163 INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction",
164 "Two-Address instruction pass", false, false)
165 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
166 INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction",
167 "Two-Address instruction pass", false, false)
169 char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
171 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS);
173 /// sink3AddrInstruction - A two-address instruction has been converted to a
174 /// three-address instruction to avoid clobbering a register. Try to sink it
175 /// past the instruction that would kill the above mentioned register to reduce
176 /// register pressure.
177 bool TwoAddressInstructionPass::
178 sink3AddrInstruction(MachineInstr *MI, unsigned SavedReg,
179 MachineBasicBlock::iterator OldPos) {
180 // FIXME: Shouldn't we be trying to do this before we three-addressify the
181 // instruction? After this transformation is done, we no longer need
182 // the instruction to be in three-address form.
184 // Check if it's safe to move this instruction.
185 bool SeenStore = true; // Be conservative.
186 if (!MI->isSafeToMove(TII, AA, SeenStore))
190 SmallSet<unsigned, 4> UseRegs;
192 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
193 const MachineOperand &MO = MI->getOperand(i);
196 unsigned MOReg = MO.getReg();
199 if (MO.isUse() && MOReg != SavedReg)
200 UseRegs.insert(MO.getReg());
204 // Don't try to move it if it implicitly defines a register.
207 // For now, don't move any instructions that define multiple registers.
209 DefReg = MO.getReg();
212 // Find the instruction that kills SavedReg.
213 MachineInstr *KillMI = NULL;
215 LiveInterval &LI = LIS->getInterval(SavedReg);
216 assert(LI.end() != LI.begin() &&
217 "Reg should not have empty live interval.");
219 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
220 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
221 if (I != LI.end() && I->start < MBBEndIdx)
225 KillMI = LIS->getInstructionFromIndex(I->end);
228 for (MachineRegisterInfo::use_nodbg_iterator
229 UI = MRI->use_nodbg_begin(SavedReg),
230 UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
231 MachineOperand &UseMO = UI.getOperand();
234 KillMI = UseMO.getParent();
239 // If we find the instruction that kills SavedReg, and it is in an
240 // appropriate location, we can try to sink the current instruction
242 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI ||
243 KillMI == OldPos || KillMI->isTerminator())
246 // If any of the definitions are used by another instruction between the
247 // position and the kill use, then it's not safe to sink it.
249 // FIXME: This can be sped up if there is an easy way to query whether an
250 // instruction is before or after another instruction. Then we can use
251 // MachineRegisterInfo def / use instead.
252 MachineOperand *KillMO = NULL;
253 MachineBasicBlock::iterator KillPos = KillMI;
256 unsigned NumVisited = 0;
257 for (MachineBasicBlock::iterator I = llvm::next(OldPos); I != KillPos; ++I) {
258 MachineInstr *OtherMI = I;
259 // DBG_VALUE cannot be counted against the limit.
260 if (OtherMI->isDebugValue())
262 if (NumVisited > 30) // FIXME: Arbitrary limit to reduce compile time cost.
265 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
266 MachineOperand &MO = OtherMI->getOperand(i);
269 unsigned MOReg = MO.getReg();
275 if (MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS))) {
276 if (OtherMI == KillMI && MOReg == SavedReg)
277 // Save the operand that kills the register. We want to unset the kill
278 // marker if we can sink MI past it.
280 else if (UseRegs.count(MOReg))
281 // One of the uses is killed before the destination.
286 assert(KillMO && "Didn't find kill");
289 // Update kill and LV information.
290 KillMO->setIsKill(false);
291 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI);
292 KillMO->setIsKill(true);
295 LV->replaceKillInstruction(SavedReg, KillMI, MI);
298 // Move instruction to its destination.
300 MBB->insert(KillPos, MI);
309 /// noUseAfterLastDef - Return true if there are no intervening uses between the
310 /// last instruction in the MBB that defines the specified register and the
311 /// two-address instruction which is being processed. It also returns the last
312 /// def location by reference
313 bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg, unsigned Dist,
316 unsigned LastUse = Dist;
317 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
318 E = MRI->reg_end(); I != E; ++I) {
319 MachineOperand &MO = I.getOperand();
320 MachineInstr *MI = MO.getParent();
321 if (MI->getParent() != MBB || MI->isDebugValue())
323 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
324 if (DI == DistanceMap.end())
326 if (MO.isUse() && DI->second < LastUse)
327 LastUse = DI->second;
328 if (MO.isDef() && DI->second > LastDef)
329 LastDef = DI->second;
332 return !(LastUse > LastDef && LastUse < Dist);
335 /// isCopyToReg - Return true if the specified MI is a copy instruction or
336 /// a extract_subreg instruction. It also returns the source and destination
337 /// registers and whether they are physical registers by reference.
338 static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
339 unsigned &SrcReg, unsigned &DstReg,
340 bool &IsSrcPhys, bool &IsDstPhys) {
344 DstReg = MI.getOperand(0).getReg();
345 SrcReg = MI.getOperand(1).getReg();
346 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
347 DstReg = MI.getOperand(0).getReg();
348 SrcReg = MI.getOperand(2).getReg();
352 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
353 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
357 /// isPLainlyKilled - Test if the given register value, which is used by the
358 // given instruction, is killed by the given instruction.
359 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg,
360 LiveIntervals *LIS) {
361 if (LIS && TargetRegisterInfo::isVirtualRegister(Reg) &&
362 !LIS->isNotInMIMap(MI)) {
363 // FIXME: Sometimes tryInstructionTransform() will add instructions and
364 // test whether they can be folded before keeping them. In this case it
365 // sets a kill before recursively calling tryInstructionTransform() again.
366 // If there is no interval available, we assume that this instruction is
367 // one of those. A kill flag is manually inserted on the operand so the
368 // check below will handle it.
369 LiveInterval &LI = LIS->getInterval(Reg);
370 // This is to match the kill flag version where undefs don't have kill
372 if (!LI.hasAtLeastOneValue())
375 SlotIndex useIdx = LIS->getInstructionIndex(MI);
376 LiveInterval::const_iterator I = LI.find(useIdx);
377 assert(I != LI.end() && "Reg must be live-in to use.");
378 return !I->end.isBlock() && SlotIndex::isSameInstr(I->end, useIdx);
381 return MI->killsRegister(Reg);
384 /// isKilled - Test if the given register value, which is used by the given
385 /// instruction, is killed by the given instruction. This looks through
386 /// coalescable copies to see if the original value is potentially not killed.
388 /// For example, in this code:
390 /// %reg1034 = copy %reg1024
391 /// %reg1035 = copy %reg1025<kill>
392 /// %reg1036 = add %reg1034<kill>, %reg1035<kill>
394 /// %reg1034 is not considered to be killed, since it is copied from a
395 /// register which is not killed. Treating it as not killed lets the
396 /// normal heuristics commute the (two-address) add, which lets
397 /// coalescing eliminate the extra copy.
399 /// If allowFalsePositives is true then likely kills are treated as kills even
400 /// if it can't be proven that they are kills.
401 static bool isKilled(MachineInstr &MI, unsigned Reg,
402 const MachineRegisterInfo *MRI,
403 const TargetInstrInfo *TII,
405 bool allowFalsePositives) {
406 MachineInstr *DefMI = &MI;
408 // All uses of physical registers are likely to be kills.
409 if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
410 (allowFalsePositives || MRI->hasOneUse(Reg)))
412 if (!isPlainlyKilled(DefMI, Reg, LIS))
414 if (TargetRegisterInfo::isPhysicalRegister(Reg))
416 MachineRegisterInfo::def_iterator Begin = MRI->def_begin(Reg);
417 // If there are multiple defs, we can't do a simple analysis, so just
418 // go with what the kill flag says.
419 if (llvm::next(Begin) != MRI->def_end())
422 bool IsSrcPhys, IsDstPhys;
423 unsigned SrcReg, DstReg;
424 // If the def is something other than a copy, then it isn't going to
425 // be coalesced, so follow the kill flag.
426 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
432 /// isTwoAddrUse - Return true if the specified MI uses the specified register
433 /// as a two-address use. If so, return the destination register by reference.
434 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) {
435 const MCInstrDesc &MCID = MI.getDesc();
436 unsigned NumOps = MI.isInlineAsm()
437 ? MI.getNumOperands() : MCID.getNumOperands();
438 for (unsigned i = 0; i != NumOps; ++i) {
439 const MachineOperand &MO = MI.getOperand(i);
440 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
443 if (MI.isRegTiedToDefOperand(i, &ti)) {
444 DstReg = MI.getOperand(ti).getReg();
451 /// findOnlyInterestingUse - Given a register, if has a single in-basic block
452 /// use, return the use instruction if it's a copy or a two-address use.
454 MachineInstr *findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB,
455 MachineRegisterInfo *MRI,
456 const TargetInstrInfo *TII,
458 unsigned &DstReg, bool &IsDstPhys) {
459 if (!MRI->hasOneNonDBGUse(Reg))
460 // None or more than one use.
462 MachineInstr &UseMI = *MRI->use_nodbg_begin(Reg);
463 if (UseMI.getParent() != MBB)
467 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) {
472 if (isTwoAddrUse(UseMI, Reg, DstReg)) {
473 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
479 /// getMappedReg - Return the physical register the specified virtual register
480 /// might be mapped to.
482 getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) {
483 while (TargetRegisterInfo::isVirtualRegister(Reg)) {
484 DenseMap<unsigned, unsigned>::iterator SI = RegMap.find(Reg);
485 if (SI == RegMap.end())
489 if (TargetRegisterInfo::isPhysicalRegister(Reg))
494 /// regsAreCompatible - Return true if the two registers are equal or aliased.
497 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
502 return TRI->regsOverlap(RegA, RegB);
506 /// isProfitableToCommute - Return true if it's potentially profitable to commute
507 /// the two-address instruction that's being processed.
509 TwoAddressInstructionPass::
510 isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
511 MachineInstr *MI, unsigned Dist) {
512 if (OptLevel == CodeGenOpt::None)
515 // Determine if it's profitable to commute this two address instruction. In
516 // general, we want no uses between this instruction and the definition of
517 // the two-address register.
519 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
520 // %reg1029<def> = MOV8rr %reg1028
521 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
522 // insert => %reg1030<def> = MOV8rr %reg1028
523 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
524 // In this case, it might not be possible to coalesce the second MOV8rr
525 // instruction if the first one is coalesced. So it would be profitable to
527 // %reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1
528 // %reg1029<def> = MOV8rr %reg1028
529 // %reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>
530 // insert => %reg1030<def> = MOV8rr %reg1029
531 // %reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>
533 if (!isPlainlyKilled(MI, regC, LIS))
536 // Ok, we have something like:
537 // %reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>
538 // let's see if it's worth commuting it.
540 // Look for situations like this:
541 // %reg1024<def> = MOV r1
542 // %reg1025<def> = MOV r0
543 // %reg1026<def> = ADD %reg1024, %reg1025
545 // Commute the ADD to hopefully eliminate an otherwise unavoidable copy.
546 unsigned ToRegA = getMappedReg(regA, DstRegMap);
548 unsigned FromRegB = getMappedReg(regB, SrcRegMap);
549 unsigned FromRegC = getMappedReg(regC, SrcRegMap);
550 bool BComp = !FromRegB || regsAreCompatible(FromRegB, ToRegA, TRI);
551 bool CComp = !FromRegC || regsAreCompatible(FromRegC, ToRegA, TRI);
553 return !BComp && CComp;
556 // If there is a use of regC between its last def (could be livein) and this
557 // instruction, then bail.
558 unsigned LastDefC = 0;
559 if (!noUseAfterLastDef(regC, Dist, LastDefC))
562 // If there is a use of regB between its last def (could be livein) and this
563 // instruction, then go ahead and make this transformation.
564 unsigned LastDefB = 0;
565 if (!noUseAfterLastDef(regB, Dist, LastDefB))
568 // Since there are no intervening uses for both registers, then commute
569 // if the def of regC is closer. Its live interval is shorter.
570 return LastDefB && LastDefC && LastDefC > LastDefB;
573 /// commuteInstruction - Commute a two-address instruction and update the basic
574 /// block, distance map, and live variables if needed. Return true if it is
576 bool TwoAddressInstructionPass::
577 commuteInstruction(MachineBasicBlock::iterator &mi,
578 unsigned RegB, unsigned RegC, unsigned Dist) {
579 MachineInstr *MI = mi;
580 DEBUG(dbgs() << "2addr: COMMUTING : " << *MI);
581 MachineInstr *NewMI = TII->commuteInstruction(MI);
584 DEBUG(dbgs() << "2addr: COMMUTING FAILED!\n");
588 DEBUG(dbgs() << "2addr: COMMUTED TO: " << *NewMI);
589 assert(NewMI == MI &&
590 "TargetInstrInfo::commuteInstruction() should not return a new "
591 "instruction unless it was requested.");
593 // Update source register map.
594 unsigned FromRegC = getMappedReg(RegC, SrcRegMap);
596 unsigned RegA = MI->getOperand(0).getReg();
597 SrcRegMap[RegA] = FromRegC;
603 /// isProfitableToConv3Addr - Return true if it is profitable to convert the
604 /// given 2-address instruction to a 3-address one.
606 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
607 // Look for situations like this:
608 // %reg1024<def> = MOV r1
609 // %reg1025<def> = MOV r0
610 // %reg1026<def> = ADD %reg1024, %reg1025
612 // Turn ADD into a 3-address instruction to avoid a copy.
613 unsigned FromRegB = getMappedReg(RegB, SrcRegMap);
616 unsigned ToRegA = getMappedReg(RegA, DstRegMap);
617 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI));
620 /// convertInstTo3Addr - Convert the specified two-address instruction into a
621 /// three address one. Return true if this transformation was successful.
623 TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi,
624 MachineBasicBlock::iterator &nmi,
625 unsigned RegA, unsigned RegB,
627 // FIXME: Why does convertToThreeAddress() need an iterator reference?
628 MachineFunction::iterator MFI = MBB;
629 MachineInstr *NewMI = TII->convertToThreeAddress(MFI, mi, LV);
630 assert(MBB == MFI && "convertToThreeAddress changed iterator reference");
634 DEBUG(dbgs() << "2addr: CONVERTING 2-ADDR: " << *mi);
635 DEBUG(dbgs() << "2addr: TO 3-ADDR: " << *NewMI);
639 LIS->ReplaceMachineInstrInMaps(mi, NewMI);
641 if (NewMI->findRegisterUseOperand(RegB, false, TRI))
642 // FIXME: Temporary workaround. If the new instruction doesn't
643 // uses RegB, convertToThreeAddress must have created more
644 // then one instruction.
645 Sunk = sink3AddrInstruction(NewMI, RegB, mi);
647 MBB->erase(mi); // Nuke the old inst.
650 DistanceMap.insert(std::make_pair(NewMI, Dist));
652 nmi = llvm::next(mi);
655 // Update source and destination register maps.
656 SrcRegMap.erase(RegA);
657 DstRegMap.erase(RegB);
661 /// scanUses - Scan forward recursively for only uses, update maps if the use
662 /// is a copy or a two-address instruction.
664 TwoAddressInstructionPass::scanUses(unsigned DstReg) {
665 SmallVector<unsigned, 4> VirtRegPairs;
669 unsigned Reg = DstReg;
670 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy,
671 NewReg, IsDstPhys)) {
672 if (IsCopy && !Processed.insert(UseMI))
675 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
676 if (DI != DistanceMap.end())
677 // Earlier in the same MBB.Reached via a back edge.
681 VirtRegPairs.push_back(NewReg);
684 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
686 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
687 VirtRegPairs.push_back(NewReg);
691 if (!VirtRegPairs.empty()) {
692 unsigned ToReg = VirtRegPairs.back();
693 VirtRegPairs.pop_back();
694 while (!VirtRegPairs.empty()) {
695 unsigned FromReg = VirtRegPairs.back();
696 VirtRegPairs.pop_back();
697 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
699 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");
702 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;
704 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
708 /// processCopy - If the specified instruction is not yet processed, process it
709 /// if it's a copy. For a copy instruction, we find the physical registers the
710 /// source and destination registers might be mapped to. These are kept in
711 /// point-to maps used to determine future optimizations. e.g.
714 /// v1026 = add v1024, v1025
716 /// If 'add' is a two-address instruction, v1024, v1026 are both potentially
717 /// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
718 /// potentially joined with r1 on the output side. It's worthwhile to commute
719 /// 'add' to eliminate a copy.
720 void TwoAddressInstructionPass::processCopy(MachineInstr *MI) {
721 if (Processed.count(MI))
724 bool IsSrcPhys, IsDstPhys;
725 unsigned SrcReg, DstReg;
726 if (!isCopyToReg(*MI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys))
729 if (IsDstPhys && !IsSrcPhys)
730 DstRegMap.insert(std::make_pair(SrcReg, DstReg));
731 else if (!IsDstPhys && IsSrcPhys) {
732 bool isNew = SrcRegMap.insert(std::make_pair(DstReg, SrcReg)).second;
734 assert(SrcRegMap[DstReg] == SrcReg &&
735 "Can't map to two src physical registers!");
740 Processed.insert(MI);
744 /// rescheduleMIBelowKill - If there is one more local instruction that reads
745 /// 'Reg' and it kills 'Reg, consider moving the instruction below the kill
746 /// instruction in order to eliminate the need for the copy.
747 bool TwoAddressInstructionPass::
748 rescheduleMIBelowKill(MachineBasicBlock::iterator &mi,
749 MachineBasicBlock::iterator &nmi,
751 // Bail immediately if we don't have LV or LIS available. We use them to find
752 // kills efficiently.
756 MachineInstr *MI = &*mi;
757 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
758 if (DI == DistanceMap.end())
759 // Must be created from unfolded load. Don't waste time trying this.
762 MachineInstr *KillMI = 0;
764 LiveInterval &LI = LIS->getInterval(Reg);
765 assert(LI.end() != LI.begin() &&
766 "Reg should not have empty live interval.");
768 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
769 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
770 if (I != LI.end() && I->start < MBBEndIdx)
774 KillMI = LIS->getInstructionFromIndex(I->end);
776 KillMI = LV->getVarInfo(Reg).findKill(MBB);
778 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
779 // Don't mess with copies, they may be coalesced later.
782 if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() ||
783 KillMI->isBranch() || KillMI->isTerminator())
784 // Don't move pass calls, etc.
788 if (isTwoAddrUse(*KillMI, Reg, DstReg))
791 bool SeenStore = true;
792 if (!MI->isSafeToMove(TII, AA, SeenStore))
795 if (TII->getInstrLatency(InstrItins, MI) > 1)
796 // FIXME: Needs more sophisticated heuristics.
799 SmallSet<unsigned, 2> Uses;
800 SmallSet<unsigned, 2> Kills;
801 SmallSet<unsigned, 2> Defs;
802 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
803 const MachineOperand &MO = MI->getOperand(i);
806 unsigned MOReg = MO.getReg();
813 if (MOReg != Reg && (MO.isKill() ||
814 (LIS && isPlainlyKilled(MI, MOReg, LIS))))
819 // Move the copies connected to MI down as well.
820 MachineBasicBlock::iterator Begin = MI;
821 MachineBasicBlock::iterator AfterMI = llvm::next(Begin);
823 MachineBasicBlock::iterator End = AfterMI;
824 while (End->isCopy() && Defs.count(End->getOperand(1).getReg())) {
825 Defs.insert(End->getOperand(0).getReg());
829 // Check if the reschedule will not break depedencies.
830 unsigned NumVisited = 0;
831 MachineBasicBlock::iterator KillPos = KillMI;
833 for (MachineBasicBlock::iterator I = End; I != KillPos; ++I) {
834 MachineInstr *OtherMI = I;
835 // DBG_VALUE cannot be counted against the limit.
836 if (OtherMI->isDebugValue())
838 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
841 if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
842 OtherMI->isBranch() || OtherMI->isTerminator())
843 // Don't move pass calls, etc.
845 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
846 const MachineOperand &MO = OtherMI->getOperand(i);
849 unsigned MOReg = MO.getReg();
853 if (Uses.count(MOReg))
854 // Physical register use would be clobbered.
856 if (!MO.isDead() && Defs.count(MOReg))
857 // May clobber a physical register def.
858 // FIXME: This may be too conservative. It's ok if the instruction
859 // is sunken completely below the use.
862 if (Defs.count(MOReg))
864 bool isKill = MO.isKill() ||
865 (LIS && isPlainlyKilled(OtherMI, MOReg, LIS));
867 ((isKill && Uses.count(MOReg)) || Kills.count(MOReg)))
868 // Don't want to extend other live ranges and update kills.
870 if (MOReg == Reg && !isKill)
871 // We can't schedule across a use of the register in question.
873 // Ensure that if this is register in question, its the kill we expect.
874 assert((MOReg != Reg || OtherMI == KillMI) &&
875 "Found multiple kills of a register in a basic block");
880 // Move debug info as well.
881 while (Begin != MBB->begin() && llvm::prior(Begin)->isDebugValue())
885 MachineBasicBlock::iterator InsertPos = KillPos;
887 // We have to move the copies first so that the MBB is still well-formed
888 // when calling handleMove().
889 for (MachineBasicBlock::iterator MBBI = AfterMI; MBBI != End;) {
890 MachineInstr *CopyMI = MBBI;
892 MBB->splice(InsertPos, MBB, CopyMI);
893 LIS->handleMove(CopyMI);
896 End = llvm::next(MachineBasicBlock::iterator(MI));
899 // Copies following MI may have been moved as well.
900 MBB->splice(InsertPos, MBB, Begin, End);
901 DistanceMap.erase(DI);
903 // Update live variables
907 LV->removeVirtualRegisterKilled(Reg, KillMI);
908 LV->addVirtualRegisterKilled(Reg, MI);
911 DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI);
915 /// isDefTooClose - Return true if the re-scheduling will put the given
916 /// instruction too close to the defs of its register dependencies.
917 bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
919 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(Reg),
920 DE = MRI->def_end(); DI != DE; ++DI) {
921 MachineInstr *DefMI = &*DI;
922 if (DefMI->getParent() != MBB || DefMI->isCopy() || DefMI->isCopyLike())
925 return true; // MI is defining something KillMI uses
926 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(DefMI);
927 if (DDI == DistanceMap.end())
928 return true; // Below MI
929 unsigned DefDist = DDI->second;
930 assert(Dist > DefDist && "Visited def already?");
931 if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist))
937 /// rescheduleKillAboveMI - If there is one more local instruction that reads
938 /// 'Reg' and it kills 'Reg, consider moving the kill instruction above the
939 /// current two-address instruction in order to eliminate the need for the
941 bool TwoAddressInstructionPass::
942 rescheduleKillAboveMI(MachineBasicBlock::iterator &mi,
943 MachineBasicBlock::iterator &nmi,
945 // Bail immediately if we don't have LV or LIS available. We use them to find
946 // kills efficiently.
950 MachineInstr *MI = &*mi;
951 DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(MI);
952 if (DI == DistanceMap.end())
953 // Must be created from unfolded load. Don't waste time trying this.
956 MachineInstr *KillMI = 0;
958 LiveInterval &LI = LIS->getInterval(Reg);
959 assert(LI.end() != LI.begin() &&
960 "Reg should not have empty live interval.");
962 SlotIndex MBBEndIdx = LIS->getMBBEndIdx(MBB).getPrevSlot();
963 LiveInterval::const_iterator I = LI.find(MBBEndIdx);
964 if (I != LI.end() && I->start < MBBEndIdx)
968 KillMI = LIS->getInstructionFromIndex(I->end);
970 KillMI = LV->getVarInfo(Reg).findKill(MBB);
972 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike())
973 // Don't mess with copies, they may be coalesced later.
977 if (isTwoAddrUse(*KillMI, Reg, DstReg))
980 bool SeenStore = true;
981 if (!KillMI->isSafeToMove(TII, AA, SeenStore))
984 SmallSet<unsigned, 2> Uses;
985 SmallSet<unsigned, 2> Kills;
986 SmallSet<unsigned, 2> Defs;
987 SmallSet<unsigned, 2> LiveDefs;
988 for (unsigned i = 0, e = KillMI->getNumOperands(); i != e; ++i) {
989 const MachineOperand &MO = KillMI->getOperand(i);
992 unsigned MOReg = MO.getReg();
996 if (isDefTooClose(MOReg, DI->second, MI))
998 bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS));
999 if (MOReg == Reg && !isKill)
1002 if (isKill && MOReg != Reg)
1003 Kills.insert(MOReg);
1004 } else if (TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1007 LiveDefs.insert(MOReg);
1011 // Check if the reschedule will not break depedencies.
1012 unsigned NumVisited = 0;
1013 MachineBasicBlock::iterator KillPos = KillMI;
1014 for (MachineBasicBlock::iterator I = mi; I != KillPos; ++I) {
1015 MachineInstr *OtherMI = I;
1016 // DBG_VALUE cannot be counted against the limit.
1017 if (OtherMI->isDebugValue())
1019 if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
1022 if (OtherMI->hasUnmodeledSideEffects() || OtherMI->isCall() ||
1023 OtherMI->isBranch() || OtherMI->isTerminator())
1024 // Don't move pass calls, etc.
1026 SmallVector<unsigned, 2> OtherDefs;
1027 for (unsigned i = 0, e = OtherMI->getNumOperands(); i != e; ++i) {
1028 const MachineOperand &MO = OtherMI->getOperand(i);
1031 unsigned MOReg = MO.getReg();
1035 if (Defs.count(MOReg))
1036 // Moving KillMI can clobber the physical register if the def has
1039 if (Kills.count(MOReg))
1040 // Don't want to extend other live ranges and update kills.
1042 if (OtherMI != MI && MOReg == Reg &&
1043 !(MO.isKill() || (LIS && isPlainlyKilled(OtherMI, MOReg, LIS))))
1044 // We can't schedule across a use of the register in question.
1047 OtherDefs.push_back(MOReg);
1051 for (unsigned i = 0, e = OtherDefs.size(); i != e; ++i) {
1052 unsigned MOReg = OtherDefs[i];
1053 if (Uses.count(MOReg))
1055 if (TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1056 LiveDefs.count(MOReg))
1058 // Physical register def is seen.
1063 // Move the old kill above MI, don't forget to move debug info as well.
1064 MachineBasicBlock::iterator InsertPos = mi;
1065 while (InsertPos != MBB->begin() && llvm::prior(InsertPos)->isDebugValue())
1067 MachineBasicBlock::iterator From = KillMI;
1068 MachineBasicBlock::iterator To = llvm::next(From);
1069 while (llvm::prior(From)->isDebugValue())
1071 MBB->splice(InsertPos, MBB, From, To);
1073 nmi = llvm::prior(InsertPos); // Backtrack so we process the moved instr.
1074 DistanceMap.erase(DI);
1076 // Update live variables
1078 LIS->handleMove(KillMI);
1080 LV->removeVirtualRegisterKilled(Reg, KillMI);
1081 LV->addVirtualRegisterKilled(Reg, MI);
1084 DEBUG(dbgs() << "\trescheduled kill: " << *KillMI);
1088 /// tryInstructionTransform - For the case where an instruction has a single
1089 /// pair of tied register operands, attempt some transformations that may
1090 /// either eliminate the tied operands or improve the opportunities for
1091 /// coalescing away the register copy. Returns true if no copy needs to be
1092 /// inserted to untie mi's operands (either because they were untied, or
1093 /// because mi was rescheduled, and will be visited again later). If the
1094 /// shouldOnlyCommute flag is true, only instruction commutation is attempted.
1095 bool TwoAddressInstructionPass::
1096 tryInstructionTransform(MachineBasicBlock::iterator &mi,
1097 MachineBasicBlock::iterator &nmi,
1098 unsigned SrcIdx, unsigned DstIdx,
1099 unsigned Dist, bool shouldOnlyCommute) {
1100 if (OptLevel == CodeGenOpt::None)
1103 MachineInstr &MI = *mi;
1104 unsigned regA = MI.getOperand(DstIdx).getReg();
1105 unsigned regB = MI.getOperand(SrcIdx).getReg();
1107 assert(TargetRegisterInfo::isVirtualRegister(regB) &&
1108 "cannot make instruction into two-address form");
1109 bool regBKilled = isKilled(MI, regB, MRI, TII, LIS, true);
1111 if (TargetRegisterInfo::isVirtualRegister(regA))
1114 // Check if it is profitable to commute the operands.
1115 unsigned SrcOp1, SrcOp2;
1117 unsigned regCIdx = ~0U;
1118 bool TryCommute = false;
1119 bool AggressiveCommute = false;
1120 if (MI.isCommutable() && MI.getNumOperands() >= 3 &&
1121 TII->findCommutedOpIndices(&MI, SrcOp1, SrcOp2)) {
1122 if (SrcIdx == SrcOp1)
1124 else if (SrcIdx == SrcOp2)
1127 if (regCIdx != ~0U) {
1128 regC = MI.getOperand(regCIdx).getReg();
1129 if (!regBKilled && isKilled(MI, regC, MRI, TII, LIS, false))
1130 // If C dies but B does not, swap the B and C operands.
1131 // This makes the live ranges of A and C joinable.
1133 else if (isProfitableToCommute(regA, regB, regC, &MI, Dist)) {
1135 AggressiveCommute = true;
1140 // If it's profitable to commute, try to do so.
1141 if (TryCommute && commuteInstruction(mi, regB, regC, Dist)) {
1143 if (AggressiveCommute)
1148 if (shouldOnlyCommute)
1151 // If there is one more use of regB later in the same MBB, consider
1152 // re-schedule this MI below it.
1153 if (EnableRescheduling && rescheduleMIBelowKill(mi, nmi, regB)) {
1158 if (MI.isConvertibleTo3Addr()) {
1159 // This instruction is potentially convertible to a true
1160 // three-address instruction. Check if it is profitable.
1161 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
1162 // Try to convert it.
1163 if (convertInstTo3Addr(mi, nmi, regA, regB, Dist)) {
1164 ++NumConvertedTo3Addr;
1165 return true; // Done with this instruction.
1170 // If there is one more use of regB later in the same MBB, consider
1171 // re-schedule it before this MI if it's legal.
1172 if (EnableRescheduling && rescheduleKillAboveMI(mi, nmi, regB)) {
1177 // If this is an instruction with a load folded into it, try unfolding
1178 // the load, e.g. avoid this:
1180 // addq (%rax), %rcx
1181 // in favor of this:
1182 // movq (%rax), %rcx
1184 // because it's preferable to schedule a load than a register copy.
1185 if (MI.mayLoad() && !regBKilled) {
1186 // Determine if a load can be unfolded.
1187 unsigned LoadRegIndex;
1189 TII->getOpcodeAfterMemoryUnfold(MI.getOpcode(),
1190 /*UnfoldLoad=*/true,
1191 /*UnfoldStore=*/false,
1194 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
1195 if (UnfoldMCID.getNumDefs() == 1) {
1197 DEBUG(dbgs() << "2addr: UNFOLDING: " << MI);
1198 const TargetRegisterClass *RC =
1199 TRI->getAllocatableClass(
1200 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI, *MF));
1201 unsigned Reg = MRI->createVirtualRegister(RC);
1202 SmallVector<MachineInstr *, 2> NewMIs;
1203 if (!TII->unfoldMemoryOperand(*MF, &MI, Reg,
1204 /*UnfoldLoad=*/true,/*UnfoldStore=*/false,
1206 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1209 assert(NewMIs.size() == 2 &&
1210 "Unfolded a load into multiple instructions!");
1211 // The load was previously folded, so this is the only use.
1212 NewMIs[1]->addRegisterKilled(Reg, TRI);
1214 // Tentatively insert the instructions into the block so that they
1215 // look "normal" to the transformation logic.
1216 MBB->insert(mi, NewMIs[0]);
1217 MBB->insert(mi, NewMIs[1]);
1219 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1220 << "2addr: NEW INST: " << *NewMIs[1]);
1222 // Transform the instruction, now that it no longer has a load.
1223 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1224 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
1225 MachineBasicBlock::iterator NewMI = NewMIs[1];
1226 bool TransformResult =
1227 tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist, true);
1228 (void)TransformResult;
1229 assert(!TransformResult &&
1230 "tryInstructionTransform() should return false.");
1231 if (NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
1232 // Success, or at least we made an improvement. Keep the unfolded
1233 // instructions and discard the original.
1235 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1236 MachineOperand &MO = MI.getOperand(i);
1238 TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
1241 if (NewMIs[0]->killsRegister(MO.getReg()))
1242 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[0]);
1244 assert(NewMIs[1]->killsRegister(MO.getReg()) &&
1245 "Kill missing after load unfold!");
1246 LV->replaceKillInstruction(MO.getReg(), &MI, NewMIs[1]);
1249 } else if (LV->removeVirtualRegisterDead(MO.getReg(), &MI)) {
1250 if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1251 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[1]);
1253 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
1254 "Dead flag missing after load unfold!");
1255 LV->addVirtualRegisterDead(MO.getReg(), NewMIs[0]);
1260 LV->addVirtualRegisterKilled(Reg, NewMIs[1]);
1263 SmallVector<unsigned, 4> OrigRegs;
1265 for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(),
1266 MOE = MI.operands_end(); MOI != MOE; ++MOI) {
1268 OrigRegs.push_back(MOI->getReg());
1272 MI.eraseFromParent();
1274 // Update LiveIntervals.
1276 MachineBasicBlock::iterator Begin(NewMIs[0]);
1277 MachineBasicBlock::iterator End(NewMIs[1]);
1278 LIS->repairIntervalsInRange(MBB, Begin, End, OrigRegs);
1283 // Transforming didn't eliminate the tie and didn't lead to an
1284 // improvement. Clean up the unfolded instructions and keep the
1286 DEBUG(dbgs() << "2addr: ABANDONING UNFOLD\n");
1287 NewMIs[0]->eraseFromParent();
1288 NewMIs[1]->eraseFromParent();
1297 // Collect tied operands of MI that need to be handled.
1298 // Rewrite trivial cases immediately.
1299 // Return true if any tied operands where found, including the trivial ones.
1300 bool TwoAddressInstructionPass::
1301 collectTiedOperands(MachineInstr *MI, TiedOperandMap &TiedOperands) {
1302 const MCInstrDesc &MCID = MI->getDesc();
1303 bool AnyOps = false;
1304 unsigned NumOps = MI->getNumOperands();
1306 for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) {
1307 unsigned DstIdx = 0;
1308 if (!MI->isRegTiedToDefOperand(SrcIdx, &DstIdx))
1311 MachineOperand &SrcMO = MI->getOperand(SrcIdx);
1312 MachineOperand &DstMO = MI->getOperand(DstIdx);
1313 unsigned SrcReg = SrcMO.getReg();
1314 unsigned DstReg = DstMO.getReg();
1315 // Tied constraint already satisfied?
1316 if (SrcReg == DstReg)
1319 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");
1321 // Deal with <undef> uses immediately - simply rewrite the src operand.
1322 if (SrcMO.isUndef()) {
1323 // Constrain the DstReg register class if required.
1324 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1325 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
1327 MRI->constrainRegClass(DstReg, RC);
1328 SrcMO.setReg(DstReg);
1329 DEBUG(dbgs() << "\t\trewrite undef:\t" << *MI);
1332 TiedOperands[SrcReg].push_back(std::make_pair(SrcIdx, DstIdx));
1337 // Process a list of tied MI operands that all use the same source register.
1338 // The tied pairs are of the form (SrcIdx, DstIdx).
1340 TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
1341 TiedPairList &TiedPairs,
1343 bool IsEarlyClobber = false;
1344 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1345 const MachineOperand &DstMO = MI->getOperand(TiedPairs[tpi].second);
1346 IsEarlyClobber |= DstMO.isEarlyClobber();
1349 bool RemovedKillFlag = false;
1350 bool AllUsesCopied = true;
1351 unsigned LastCopiedReg = 0;
1352 SlotIndex LastCopyIdx;
1354 for (unsigned tpi = 0, tpe = TiedPairs.size(); tpi != tpe; ++tpi) {
1355 unsigned SrcIdx = TiedPairs[tpi].first;
1356 unsigned DstIdx = TiedPairs[tpi].second;
1358 const MachineOperand &DstMO = MI->getOperand(DstIdx);
1359 unsigned RegA = DstMO.getReg();
1361 // Grab RegB from the instruction because it may have changed if the
1362 // instruction was commuted.
1363 RegB = MI->getOperand(SrcIdx).getReg();
1366 // The register is tied to multiple destinations (or else we would
1367 // not have continued this far), but this use of the register
1368 // already matches the tied destination. Leave it.
1369 AllUsesCopied = false;
1372 LastCopiedReg = RegA;
1374 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
1375 "cannot make instruction into two-address form");
1378 // First, verify that we don't have a use of "a" in the instruction
1379 // (a = b + a for example) because our transformation will not
1380 // work. This should never occur because we are in SSA form.
1381 for (unsigned i = 0; i != MI->getNumOperands(); ++i)
1382 assert(i == DstIdx ||
1383 !MI->getOperand(i).isReg() ||
1384 MI->getOperand(i).getReg() != RegA);
1388 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1389 TII->get(TargetOpcode::COPY), RegA).addReg(RegB);
1391 // Update DistanceMap.
1392 MachineBasicBlock::iterator PrevMI = MI;
1394 DistanceMap.insert(std::make_pair(PrevMI, Dist));
1395 DistanceMap[MI] = ++Dist;
1398 LastCopyIdx = LIS->InsertMachineInstrInMaps(PrevMI).getRegSlot();
1400 if (TargetRegisterInfo::isVirtualRegister(RegA)) {
1401 LiveInterval &LI = LIS->getInterval(RegA);
1402 VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
1404 LIS->getInstructionIndex(MI).getRegSlot(IsEarlyClobber);
1405 LI.addRange(LiveRange(LastCopyIdx, endIdx, VNI));
1409 DEBUG(dbgs() << "\t\tprepend:\t" << *PrevMI);
1411 MachineOperand &MO = MI->getOperand(SrcIdx);
1412 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1413 "inconsistent operand info for 2-reg pass");
1415 MO.setIsKill(false);
1416 RemovedKillFlag = true;
1419 // Make sure regA is a legal regclass for the SrcIdx operand.
1420 if (TargetRegisterInfo::isVirtualRegister(RegA) &&
1421 TargetRegisterInfo::isVirtualRegister(RegB))
1422 MRI->constrainRegClass(RegA, MRI->getRegClass(RegB));
1426 // Propagate SrcRegMap.
1427 SrcRegMap[RegA] = RegB;
1431 if (AllUsesCopied) {
1432 if (!IsEarlyClobber) {
1433 // Replace other (un-tied) uses of regB with LastCopiedReg.
1434 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1435 MachineOperand &MO = MI->getOperand(i);
1436 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1438 MO.setIsKill(false);
1439 RemovedKillFlag = true;
1441 MO.setReg(LastCopiedReg);
1446 // Update live variables for regB.
1447 if (RemovedKillFlag && LV && LV->getVarInfo(RegB).removeKill(MI)) {
1448 MachineBasicBlock::iterator PrevMI = MI;
1450 LV->addVirtualRegisterKilled(RegB, PrevMI);
1453 // Update LiveIntervals.
1455 LiveInterval &LI = LIS->getInterval(RegB);
1456 SlotIndex MIIdx = LIS->getInstructionIndex(MI);
1457 LiveInterval::const_iterator I = LI.find(MIIdx);
1458 assert(I != LI.end() && "RegB must be live-in to use.");
1460 SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber);
1461 if (I->end == UseIdx)
1462 LI.removeRange(LastCopyIdx, UseIdx);
1465 } else if (RemovedKillFlag) {
1466 // Some tied uses of regB matched their destination registers, so
1467 // regB is still used in this instruction, but a kill flag was
1468 // removed from a different tied use of regB, so now we need to add
1469 // a kill flag to one of the remaining uses of regB.
1470 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1471 MachineOperand &MO = MI->getOperand(i);
1472 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1480 /// runOnMachineFunction - Reduce two-address instructions to two operands.
1482 bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
1484 const TargetMachine &TM = MF->getTarget();
1485 MRI = &MF->getRegInfo();
1486 TII = TM.getInstrInfo();
1487 TRI = TM.getRegisterInfo();
1488 InstrItins = TM.getInstrItineraryData();
1489 LV = getAnalysisIfAvailable<LiveVariables>();
1490 LIS = getAnalysisIfAvailable<LiveIntervals>();
1491 AA = &getAnalysis<AliasAnalysis>();
1492 OptLevel = TM.getOptLevel();
1494 bool MadeChange = false;
1496 DEBUG(dbgs() << "********** REWRITING TWO-ADDR INSTRS **********\n");
1497 DEBUG(dbgs() << "********** Function: "
1498 << MF->getName() << '\n');
1500 // This pass takes the function out of SSA form.
1503 TiedOperandMap TiedOperands;
1504 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
1505 MBBI != MBBE; ++MBBI) {
1508 DistanceMap.clear();
1512 for (MachineBasicBlock::iterator mi = MBB->begin(), me = MBB->end();
1514 MachineBasicBlock::iterator nmi = llvm::next(mi);
1515 if (mi->isDebugValue()) {
1520 // Expand REG_SEQUENCE instructions. This will position mi at the first
1521 // expanded instruction.
1522 if (mi->isRegSequence())
1523 eliminateRegSequence(mi);
1525 DistanceMap.insert(std::make_pair(mi, ++Dist));
1529 // First scan through all the tied register uses in this instruction
1530 // and record a list of pairs of tied operands for each register.
1531 if (!collectTiedOperands(mi, TiedOperands)) {
1536 ++NumTwoAddressInstrs;
1538 DEBUG(dbgs() << '\t' << *mi);
1540 // If the instruction has a single pair of tied operands, try some
1541 // transformations that may either eliminate the tied operands or
1542 // improve the opportunities for coalescing away the register copy.
1543 if (TiedOperands.size() == 1) {
1544 SmallVector<std::pair<unsigned, unsigned>, 4> &TiedPairs
1545 = TiedOperands.begin()->second;
1546 if (TiedPairs.size() == 1) {
1547 unsigned SrcIdx = TiedPairs[0].first;
1548 unsigned DstIdx = TiedPairs[0].second;
1549 unsigned SrcReg = mi->getOperand(SrcIdx).getReg();
1550 unsigned DstReg = mi->getOperand(DstIdx).getReg();
1551 if (SrcReg != DstReg &&
1552 tryInstructionTransform(mi, nmi, SrcIdx, DstIdx, Dist, false)) {
1553 // The tied operands have been eliminated or shifted further down the
1554 // block to ease elimination. Continue processing with 'nmi'.
1555 TiedOperands.clear();
1562 // Now iterate over the information collected above.
1563 for (TiedOperandMap::iterator OI = TiedOperands.begin(),
1564 OE = TiedOperands.end(); OI != OE; ++OI) {
1565 processTiedPairs(mi, OI->second, Dist);
1566 DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
1569 // Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
1570 if (mi->isInsertSubreg()) {
1571 // From %reg = INSERT_SUBREG %reg, %subreg, subidx
1572 // To %reg:subidx = COPY %subreg
1573 unsigned SubIdx = mi->getOperand(3).getImm();
1574 mi->RemoveOperand(3);
1575 assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
1576 mi->getOperand(0).setSubReg(SubIdx);
1577 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1578 mi->RemoveOperand(1);
1579 mi->setDesc(TII->get(TargetOpcode::COPY));
1580 DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
1583 // Clear TiedOperands here instead of at the top of the loop
1584 // since most instructions do not have tied operands.
1585 TiedOperands.clear();
1591 MF->verify(this, "After two-address instruction pass");
1596 /// Eliminate a REG_SEQUENCE instruction as part of the de-ssa process.
1598 /// The instruction is turned into a sequence of sub-register copies:
1600 /// %dst = REG_SEQUENCE %v1, ssub0, %v2, ssub1
1604 /// %dst:ssub0<def,undef> = COPY %v1
1605 /// %dst:ssub1<def> = COPY %v2
1607 void TwoAddressInstructionPass::
1608 eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
1609 MachineInstr *MI = MBBI;
1610 unsigned DstReg = MI->getOperand(0).getReg();
1611 if (MI->getOperand(0).getSubReg() ||
1612 TargetRegisterInfo::isPhysicalRegister(DstReg) ||
1613 !(MI->getNumOperands() & 1)) {
1614 DEBUG(dbgs() << "Illegal REG_SEQUENCE instruction:" << *MI);
1615 llvm_unreachable(0);
1618 SmallVector<unsigned, 4> OrigRegs;
1620 OrigRegs.push_back(MI->getOperand(0).getReg());
1621 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2)
1622 OrigRegs.push_back(MI->getOperand(i).getReg());
1625 bool DefEmitted = false;
1626 for (unsigned i = 1, e = MI->getNumOperands(); i < e; i += 2) {
1627 MachineOperand &UseMO = MI->getOperand(i);
1628 unsigned SrcReg = UseMO.getReg();
1629 unsigned SubIdx = MI->getOperand(i+1).getImm();
1630 // Nothing needs to be inserted for <undef> operands.
1631 if (UseMO.isUndef())
1634 // Defer any kill flag to the last operand using SrcReg. Otherwise, we
1635 // might insert a COPY that uses SrcReg after is was killed.
1636 bool isKill = UseMO.isKill();
1638 for (unsigned j = i + 2; j < e; j += 2)
1639 if (MI->getOperand(j).getReg() == SrcReg) {
1640 MI->getOperand(j).setIsKill();
1641 UseMO.setIsKill(false);
1646 // Insert the sub-register copy.
1647 MachineInstr *CopyMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1648 TII->get(TargetOpcode::COPY))
1649 .addReg(DstReg, RegState::Define, SubIdx)
1652 // The first def needs an <undef> flag because there is no live register
1655 CopyMI->getOperand(0).setIsUndef(true);
1656 // Return an iterator pointing to the first inserted instr.
1661 // Update LiveVariables' kill info.
1662 if (LV && isKill && !TargetRegisterInfo::isPhysicalRegister(SrcReg))
1663 LV->replaceKillInstruction(SrcReg, MI, CopyMI);
1665 DEBUG(dbgs() << "Inserted: " << *CopyMI);
1668 MachineBasicBlock::iterator EndMBBI =
1669 llvm::next(MachineBasicBlock::iterator(MI));
1672 DEBUG(dbgs() << "Turned: " << *MI << " into an IMPLICIT_DEF");
1673 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
1674 for (int j = MI->getNumOperands() - 1, ee = 0; j > ee; --j)
1675 MI->RemoveOperand(j);
1677 DEBUG(dbgs() << "Eliminated: " << *MI);
1678 MI->eraseFromParent();
1681 // Udpate LiveIntervals.
1683 LIS->repairIntervalsInRange(MBB, MBBI, EndMBBI, OrigRegs);