1 //===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SplitAnalysis class as well as mutator functions for
11 // live range splitting.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regalloc"
17 #include "LiveRangeEdit.h"
18 #include "VirtRegMap.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/MachineDominators.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
31 STATISTIC(NumFinished, "Number of splits finished");
32 STATISTIC(NumSimple, "Number of splits that were simple");
33 STATISTIC(NumCopies, "Number of copies inserted for splitting");
34 STATISTIC(NumRemats, "Number of rematerialized defs for splitting");
35 STATISTIC(NumRepairs, "Number of invalid live ranges repaired");
37 //===----------------------------------------------------------------------===//
39 //===----------------------------------------------------------------------===//
41 SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm,
42 const LiveIntervals &lis,
43 const MachineLoopInfo &mli)
44 : MF(vrm.getMachineFunction()),
48 TII(*MF.getTarget().getInstrInfo()),
50 LastSplitPoint(MF.getNumBlockIDs()) {}
52 void SplitAnalysis::clear() {
55 ThroughBlocks.clear();
57 DidRepairRange = false;
60 SlotIndex SplitAnalysis::computeLastSplitPoint(unsigned Num) {
61 const MachineBasicBlock *MBB = MF.getBlockNumbered(Num);
62 const MachineBasicBlock *LPad = MBB->getLandingPadSuccessor();
63 std::pair<SlotIndex, SlotIndex> &LSP = LastSplitPoint[Num];
65 // Compute split points on the first call. The pair is independent of the
66 // current live interval.
67 if (!LSP.first.isValid()) {
68 MachineBasicBlock::const_iterator FirstTerm = MBB->getFirstTerminator();
69 if (FirstTerm == MBB->end())
70 LSP.first = LIS.getMBBEndIdx(MBB);
72 LSP.first = LIS.getInstructionIndex(FirstTerm);
74 // If there is a landing pad successor, also find the call instruction.
77 // There may not be a call instruction (?) in which case we ignore LPad.
78 LSP.second = LSP.first;
79 for (MachineBasicBlock::const_iterator I = MBB->end(), E = MBB->begin();
82 if (I->getDesc().isCall()) {
83 LSP.second = LIS.getInstructionIndex(I);
89 // If CurLI is live into a landing pad successor, move the last split point
90 // back to the call that may throw.
91 if (LPad && LSP.second.isValid() && LIS.isLiveInToMBB(*CurLI, LPad))
97 /// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
98 void SplitAnalysis::analyzeUses() {
99 assert(UseSlots.empty() && "Call clear first");
101 // First get all the defs from the interval values. This provides the correct
102 // slots for early clobbers.
103 for (LiveInterval::const_vni_iterator I = CurLI->vni_begin(),
104 E = CurLI->vni_end(); I != E; ++I)
105 if (!(*I)->isPHIDef() && !(*I)->isUnused())
106 UseSlots.push_back((*I)->def);
108 // Get use slots form the use-def chain.
109 const MachineRegisterInfo &MRI = MF.getRegInfo();
110 for (MachineRegisterInfo::use_nodbg_iterator
111 I = MRI.use_nodbg_begin(CurLI->reg), E = MRI.use_nodbg_end(); I != E;
113 if (!I.getOperand().isUndef())
114 UseSlots.push_back(LIS.getInstructionIndex(&*I).getDefIndex());
116 array_pod_sort(UseSlots.begin(), UseSlots.end());
118 // Remove duplicates, keeping the smaller slot for each instruction.
119 // That is what we want for early clobbers.
120 UseSlots.erase(std::unique(UseSlots.begin(), UseSlots.end(),
121 SlotIndex::isSameInstr),
124 // Compute per-live block info.
125 if (!calcLiveBlockInfo()) {
126 // FIXME: calcLiveBlockInfo found inconsistencies in the live range.
127 // I am looking at you, RegisterCoalescer!
128 DidRepairRange = true;
130 DEBUG(dbgs() << "*** Fixing inconsistent live interval! ***\n");
131 const_cast<LiveIntervals&>(LIS)
132 .shrinkToUses(const_cast<LiveInterval*>(CurLI));
134 ThroughBlocks.clear();
135 bool fixed = calcLiveBlockInfo();
137 assert(fixed && "Couldn't fix broken live interval");
140 DEBUG(dbgs() << "Analyze counted "
141 << UseSlots.size() << " instrs in "
142 << UseBlocks.size() << " blocks, through "
143 << NumThroughBlocks << " blocks.\n");
146 /// calcLiveBlockInfo - Fill the LiveBlocks array with information about blocks
147 /// where CurLI is live.
148 bool SplitAnalysis::calcLiveBlockInfo() {
149 ThroughBlocks.resize(MF.getNumBlockIDs());
150 NumThroughBlocks = NumGapBlocks = 0;
154 LiveInterval::const_iterator LVI = CurLI->begin();
155 LiveInterval::const_iterator LVE = CurLI->end();
157 SmallVectorImpl<SlotIndex>::const_iterator UseI, UseE;
158 UseI = UseSlots.begin();
159 UseE = UseSlots.end();
161 // Loop over basic blocks where CurLI is live.
162 MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start);
166 SlotIndex Start, Stop;
167 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
169 // If the block contains no uses, the range must be live through. At one
170 // point, RegisterCoalescer could create dangling ranges that ended
172 if (UseI == UseE || *UseI >= Stop) {
174 ThroughBlocks.set(BI.MBB->getNumber());
175 // The range shouldn't end mid-block if there are no uses. This shouldn't
180 // This block has uses. Find the first and last uses in the block.
181 BI.FirstInstr = *UseI;
182 assert(BI.FirstInstr >= Start);
184 while (UseI != UseE && *UseI < Stop);
185 BI.LastInstr = UseI[-1];
186 assert(BI.LastInstr < Stop);
188 // LVI is the first live segment overlapping MBB.
189 BI.LiveIn = LVI->start <= Start;
191 // When not live in, the first use should be a def.
193 assert(LVI->start == LVI->valno->def && "Dangling LiveRange start");
194 assert(LVI->start == BI.FirstInstr && "First instr should be a def");
195 BI.FirstDef = BI.FirstInstr;
198 // Look for gaps in the live range.
200 while (LVI->end < Stop) {
201 SlotIndex LastStop = LVI->end;
202 if (++LVI == LVE || LVI->start >= Stop) {
204 BI.LastInstr = LastStop;
208 if (LastStop < LVI->start) {
209 // There is a gap in the live range. Create duplicate entries for the
210 // live-in snippet and the live-out snippet.
213 // Push the Live-in part.
215 UseBlocks.push_back(BI);
216 UseBlocks.back().LastInstr = LastStop;
218 // Set up BI for the live-out part.
221 BI.FirstInstr = BI.FirstDef = LVI->start;
224 // A LiveRange that starts in the middle of the block must be a def.
225 assert(LVI->start == LVI->valno->def && "Dangling LiveRange start");
227 BI.FirstDef = LVI->start;
230 UseBlocks.push_back(BI);
232 // LVI is now at LVE or LVI->end >= Stop.
237 // Live segment ends exactly at Stop. Move to the next segment.
238 if (LVI->end == Stop && ++LVI == LVE)
241 // Pick the next basic block.
242 if (LVI->start < Stop)
245 MFI = LIS.getMBBFromIndex(LVI->start);
248 assert(getNumLiveBlocks() == countLiveBlocks(CurLI) && "Bad block count");
252 unsigned SplitAnalysis::countLiveBlocks(const LiveInterval *cli) const {
255 LiveInterval *li = const_cast<LiveInterval*>(cli);
256 LiveInterval::iterator LVI = li->begin();
257 LiveInterval::iterator LVE = li->end();
260 // Loop over basic blocks where li is live.
261 MachineFunction::const_iterator MFI = LIS.getMBBFromIndex(LVI->start);
262 SlotIndex Stop = LIS.getMBBEndIdx(MFI);
265 LVI = li->advanceTo(LVI, Stop);
270 Stop = LIS.getMBBEndIdx(MFI);
271 } while (Stop <= LVI->start);
275 bool SplitAnalysis::isOriginalEndpoint(SlotIndex Idx) const {
276 unsigned OrigReg = VRM.getOriginal(CurLI->reg);
277 const LiveInterval &Orig = LIS.getInterval(OrigReg);
278 assert(!Orig.empty() && "Splitting empty interval?");
279 LiveInterval::const_iterator I = Orig.find(Idx);
281 // Range containing Idx should begin at Idx.
282 if (I != Orig.end() && I->start <= Idx)
283 return I->start == Idx;
285 // Range does not contain Idx, previous must end at Idx.
286 return I != Orig.begin() && (--I)->end == Idx;
289 void SplitAnalysis::analyze(const LiveInterval *li) {
296 //===----------------------------------------------------------------------===//
298 //===----------------------------------------------------------------------===//
300 /// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
301 SplitEditor::SplitEditor(SplitAnalysis &sa,
304 MachineDominatorTree &mdt)
305 : SA(sa), LIS(lis), VRM(vrm),
306 MRI(vrm.getMachineFunction().getRegInfo()),
308 TII(*vrm.getMachineFunction().getTarget().getInstrInfo()),
309 TRI(*vrm.getMachineFunction().getTarget().getRegisterInfo()),
312 SpillMode(SM_Partition),
316 void SplitEditor::reset(LiveRangeEdit &LRE, ComplementSpillMode SM) {
322 LRCalc.reset(&VRM.getMachineFunction());
324 // We don't need an AliasAnalysis since we will only be performing
325 // cheap-as-a-copy remats anyway.
326 Edit->anyRematerializable(LIS, TII, 0);
329 void SplitEditor::dump() const {
330 if (RegAssign.empty()) {
331 dbgs() << " empty\n";
335 for (RegAssignMap::const_iterator I = RegAssign.begin(); I.valid(); ++I)
336 dbgs() << " [" << I.start() << ';' << I.stop() << "):" << I.value();
340 VNInfo *SplitEditor::defValue(unsigned RegIdx,
341 const VNInfo *ParentVNI,
343 assert(ParentVNI && "Mapping NULL value");
344 assert(Idx.isValid() && "Invalid SlotIndex");
345 assert(Edit->getParent().getVNInfoAt(Idx) == ParentVNI && "Bad Parent VNI");
346 LiveInterval *LI = Edit->get(RegIdx);
348 // Create a new value.
349 VNInfo *VNI = LI->getNextValue(Idx, 0, LIS.getVNInfoAllocator());
351 // Use insert for lookup, so we can add missing values with a second lookup.
352 std::pair<ValueMap::iterator, bool> InsP =
353 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), VNI));
355 // This was the first time (RegIdx, ParentVNI) was mapped.
356 // Keep it as a simple def without any liveness.
360 // If the previous value was a simple mapping, add liveness for it now.
361 if (VNInfo *OldVNI = InsP.first->second) {
362 SlotIndex Def = OldVNI->def;
363 LI->addRange(LiveRange(Def, Def.getNextSlot(), OldVNI));
364 // No longer a simple mapping.
365 InsP.first->second = 0;
368 // This is a complex mapping, add liveness for VNI
369 SlotIndex Def = VNI->def;
370 LI->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
375 void SplitEditor::markComplexMapped(unsigned RegIdx, const VNInfo *ParentVNI) {
376 assert(ParentVNI && "Mapping NULL value");
377 VNInfo *&VNI = Values[std::make_pair(RegIdx, ParentVNI->id)];
379 // ParentVNI was either unmapped or already complex mapped. Either way.
383 // This was previously a single mapping. Make sure the old def is represented
384 // by a trivial live range.
385 SlotIndex Def = VNI->def;
386 Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
390 // extendRange - Extend the live range to reach Idx.
391 // Potentially create phi-def values.
392 void SplitEditor::extendRange(unsigned RegIdx, SlotIndex Idx) {
393 LRCalc.extend(Edit->get(RegIdx), Idx.getNextSlot(),
394 LIS.getSlotIndexes(), &MDT, &LIS.getVNInfoAllocator());
397 VNInfo *SplitEditor::defFromParent(unsigned RegIdx,
400 MachineBasicBlock &MBB,
401 MachineBasicBlock::iterator I) {
402 MachineInstr *CopyMI = 0;
404 LiveInterval *LI = Edit->get(RegIdx);
406 // We may be trying to avoid interference that ends at a deleted instruction,
407 // so always begin RegIdx 0 early and all others late.
408 bool Late = RegIdx != 0;
410 // Attempt cheap-as-a-copy rematerialization.
411 LiveRangeEdit::Remat RM(ParentVNI);
412 if (Edit->canRematerializeAt(RM, UseIdx, true, LIS)) {
413 Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI, Late);
416 // Can't remat, just insert a copy from parent.
417 CopyMI = BuildMI(MBB, I, DebugLoc(), TII.get(TargetOpcode::COPY), LI->reg)
418 .addReg(Edit->getReg());
419 Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late)
424 // Define the value in Reg.
425 VNInfo *VNI = defValue(RegIdx, ParentVNI, Def);
426 VNI->setCopy(CopyMI);
430 /// Create a new virtual register and live interval.
431 unsigned SplitEditor::openIntv() {
432 // Create the complement as index 0.
434 Edit->create(LIS, VRM);
436 // Create the open interval.
437 OpenIdx = Edit->size();
438 Edit->create(LIS, VRM);
442 void SplitEditor::selectIntv(unsigned Idx) {
443 assert(Idx != 0 && "Cannot select the complement interval");
444 assert(Idx < Edit->size() && "Can only select previously opened interval");
445 DEBUG(dbgs() << " selectIntv " << OpenIdx << " -> " << Idx << '\n');
449 SlotIndex SplitEditor::enterIntvBefore(SlotIndex Idx) {
450 assert(OpenIdx && "openIntv not called before enterIntvBefore");
451 DEBUG(dbgs() << " enterIntvBefore " << Idx);
452 Idx = Idx.getBaseIndex();
453 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
455 DEBUG(dbgs() << ": not live\n");
458 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
459 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
460 assert(MI && "enterIntvBefore called with invalid index");
462 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), MI);
466 SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) {
467 assert(OpenIdx && "openIntv not called before enterIntvAfter");
468 DEBUG(dbgs() << " enterIntvAfter " << Idx);
469 Idx = Idx.getBoundaryIndex();
470 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
472 DEBUG(dbgs() << ": not live\n");
475 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
476 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
477 assert(MI && "enterIntvAfter called with invalid index");
479 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(),
480 llvm::next(MachineBasicBlock::iterator(MI)));
484 SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) {
485 assert(OpenIdx && "openIntv not called before enterIntvAtEnd");
486 SlotIndex End = LIS.getMBBEndIdx(&MBB);
487 SlotIndex Last = End.getPrevSlot();
488 DEBUG(dbgs() << " enterIntvAtEnd BB#" << MBB.getNumber() << ", " << Last);
489 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Last);
491 DEBUG(dbgs() << ": not live\n");
494 DEBUG(dbgs() << ": valno " << ParentVNI->id);
495 VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Last, MBB,
496 LIS.getLastSplitPoint(Edit->getParent(), &MBB));
497 RegAssign.insert(VNI->def, End, OpenIdx);
502 /// useIntv - indicate that all instructions in MBB should use OpenLI.
503 void SplitEditor::useIntv(const MachineBasicBlock &MBB) {
504 useIntv(LIS.getMBBStartIdx(&MBB), LIS.getMBBEndIdx(&MBB));
507 void SplitEditor::useIntv(SlotIndex Start, SlotIndex End) {
508 assert(OpenIdx && "openIntv not called before useIntv");
509 DEBUG(dbgs() << " useIntv [" << Start << ';' << End << "):");
510 RegAssign.insert(Start, End, OpenIdx);
514 SlotIndex SplitEditor::leaveIntvAfter(SlotIndex Idx) {
515 assert(OpenIdx && "openIntv not called before leaveIntvAfter");
516 DEBUG(dbgs() << " leaveIntvAfter " << Idx);
518 // The interval must be live beyond the instruction at Idx.
519 Idx = Idx.getBoundaryIndex();
520 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
522 DEBUG(dbgs() << ": not live\n");
523 return Idx.getNextSlot();
525 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
527 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
528 assert(MI && "No instruction at index");
529 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(),
530 llvm::next(MachineBasicBlock::iterator(MI)));
534 SlotIndex SplitEditor::leaveIntvBefore(SlotIndex Idx) {
535 assert(OpenIdx && "openIntv not called before leaveIntvBefore");
536 DEBUG(dbgs() << " leaveIntvBefore " << Idx);
538 // The interval must be live into the instruction at Idx.
539 Idx = Idx.getBaseIndex();
540 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx);
542 DEBUG(dbgs() << ": not live\n");
543 return Idx.getNextSlot();
545 DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n');
547 MachineInstr *MI = LIS.getInstructionFromIndex(Idx);
548 assert(MI && "No instruction at index");
549 VNInfo *VNI = defFromParent(0, ParentVNI, Idx, *MI->getParent(), MI);
553 SlotIndex SplitEditor::leaveIntvAtTop(MachineBasicBlock &MBB) {
554 assert(OpenIdx && "openIntv not called before leaveIntvAtTop");
555 SlotIndex Start = LIS.getMBBStartIdx(&MBB);
556 DEBUG(dbgs() << " leaveIntvAtTop BB#" << MBB.getNumber() << ", " << Start);
558 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
560 DEBUG(dbgs() << ": not live\n");
564 VNInfo *VNI = defFromParent(0, ParentVNI, Start, MBB,
565 MBB.SkipPHIsAndLabels(MBB.begin()));
566 RegAssign.insert(Start, VNI->def, OpenIdx);
571 void SplitEditor::overlapIntv(SlotIndex Start, SlotIndex End) {
572 assert(OpenIdx && "openIntv not called before overlapIntv");
573 const VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Start);
574 assert(ParentVNI == Edit->getParent().getVNInfoAt(End.getPrevSlot()) &&
575 "Parent changes value in extended range");
576 assert(LIS.getMBBFromIndex(Start) == LIS.getMBBFromIndex(End) &&
577 "Range cannot span basic blocks");
579 // The complement interval will be extended as needed by extendRange().
581 markComplexMapped(0, ParentVNI);
582 DEBUG(dbgs() << " overlapIntv [" << Start << ';' << End << "):");
583 RegAssign.insert(Start, End, OpenIdx);
587 /// transferValues - Transfer all possible values to the new live ranges.
588 /// Values that were rematerialized are left alone, they need extendRange().
589 bool SplitEditor::transferValues() {
590 bool Skipped = false;
591 RegAssignMap::const_iterator AssignI = RegAssign.begin();
592 for (LiveInterval::const_iterator ParentI = Edit->getParent().begin(),
593 ParentE = Edit->getParent().end(); ParentI != ParentE; ++ParentI) {
594 DEBUG(dbgs() << " blit " << *ParentI << ':');
595 VNInfo *ParentVNI = ParentI->valno;
596 // RegAssign has holes where RegIdx 0 should be used.
597 SlotIndex Start = ParentI->start;
598 AssignI.advanceTo(Start);
601 SlotIndex End = ParentI->end;
602 if (!AssignI.valid()) {
604 } else if (AssignI.start() <= Start) {
605 RegIdx = AssignI.value();
606 if (AssignI.stop() < End) {
607 End = AssignI.stop();
612 End = std::min(End, AssignI.start());
615 // The interval [Start;End) is continuously mapped to RegIdx, ParentVNI.
616 DEBUG(dbgs() << " [" << Start << ';' << End << ")=" << RegIdx);
617 LiveInterval *LI = Edit->get(RegIdx);
619 // Check for a simply defined value that can be blitted directly.
620 if (VNInfo *VNI = Values.lookup(std::make_pair(RegIdx, ParentVNI->id))) {
621 DEBUG(dbgs() << ':' << VNI->id);
622 LI->addRange(LiveRange(Start, End, VNI));
627 // Skip rematerialized values, we need to use extendRange() and
628 // extendPHIKillRanges() to completely recompute the live ranges.
629 if (Edit->didRematerialize(ParentVNI)) {
630 DEBUG(dbgs() << "(remat)");
636 // This value has multiple defs in RegIdx, but it wasn't rematerialized,
637 // so the live range is accurate. Add live-in blocks in [Start;End) to the
639 MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start);
640 SlotIndex BlockStart, BlockEnd;
641 tie(BlockStart, BlockEnd) = LIS.getSlotIndexes()->getMBBRange(MBB);
643 // The first block may be live-in, or it may have its own def.
644 if (Start != BlockStart) {
645 VNInfo *VNI = LI->extendInBlock(BlockStart,
646 std::min(BlockEnd, End).getPrevSlot());
647 assert(VNI && "Missing def for complex mapped value");
648 DEBUG(dbgs() << ':' << VNI->id << "*BB#" << MBB->getNumber());
649 // MBB has its own def. Is it also live-out?
651 LRCalc.setLiveOutValue(MBB, VNI);
653 // Skip to the next block for live-in.
655 BlockStart = BlockEnd;
658 // Handle the live-in blocks covered by [Start;End).
659 assert(Start <= BlockStart && "Expected live-in block");
660 while (BlockStart < End) {
661 DEBUG(dbgs() << ">BB#" << MBB->getNumber());
662 BlockEnd = LIS.getMBBEndIdx(MBB);
663 if (BlockStart == ParentVNI->def) {
664 // This block has the def of a parent PHI, so it isn't live-in.
665 assert(ParentVNI->isPHIDef() && "Non-phi defined at block start?");
666 VNInfo *VNI = LI->extendInBlock(BlockStart,
667 std::min(BlockEnd, End).getPrevSlot());
668 assert(VNI && "Missing def for complex mapped parent PHI");
670 LRCalc.setLiveOutValue(MBB, VNI); // Live-out as well.
672 // This block needs a live-in value. The last block covered may not
675 LRCalc.addLiveInBlock(LI, MDT[MBB], End);
677 // Live-through, and we don't know the value.
678 LRCalc.addLiveInBlock(LI, MDT[MBB]);
679 LRCalc.setLiveOutValue(MBB, 0);
682 BlockStart = BlockEnd;
686 } while (Start != ParentI->end);
687 DEBUG(dbgs() << '\n');
690 LRCalc.calculateValues(LIS.getSlotIndexes(), &MDT, &LIS.getVNInfoAllocator());
695 void SplitEditor::extendPHIKillRanges() {
696 // Extend live ranges to be live-out for successor PHI values.
697 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
698 E = Edit->getParent().vni_end(); I != E; ++I) {
699 const VNInfo *PHIVNI = *I;
700 if (PHIVNI->isUnused() || !PHIVNI->isPHIDef())
702 unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
703 MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
704 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
705 PE = MBB->pred_end(); PI != PE; ++PI) {
706 SlotIndex End = LIS.getMBBEndIdx(*PI).getPrevSlot();
707 // The predecessor may not have a live-out value. That is OK, like an
708 // undef PHI operand.
709 if (Edit->getParent().liveAt(End)) {
710 assert(RegAssign.lookup(End) == RegIdx &&
711 "Different register assignment in phi predecessor");
712 extendRange(RegIdx, End);
718 /// rewriteAssigned - Rewrite all uses of Edit->getReg().
719 void SplitEditor::rewriteAssigned(bool ExtendRanges) {
720 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
721 RE = MRI.reg_end(); RI != RE;) {
722 MachineOperand &MO = RI.getOperand();
723 MachineInstr *MI = MO.getParent();
725 // LiveDebugVariables should have handled all DBG_VALUE instructions.
726 if (MI->isDebugValue()) {
727 DEBUG(dbgs() << "Zapping " << *MI);
732 // <undef> operands don't really read the register, so it doesn't matter
733 // which register we choose. When the use operand is tied to a def, we must
734 // use the same register as the def, so just do that always.
735 SlotIndex Idx = LIS.getInstructionIndex(MI);
736 if (MO.isDef() || MO.isUndef())
737 Idx = MO.isEarlyClobber() ? Idx.getUseIndex() : Idx.getDefIndex();
739 // Rewrite to the mapped register at Idx.
740 unsigned RegIdx = RegAssign.lookup(Idx);
741 MO.setReg(Edit->get(RegIdx)->reg);
742 DEBUG(dbgs() << " rewr BB#" << MI->getParent()->getNumber() << '\t'
743 << Idx << ':' << RegIdx << '\t' << *MI);
745 // Extend liveness to Idx if the instruction reads reg.
746 if (!ExtendRanges || MO.isUndef())
749 // Skip instructions that don't read Reg.
751 if (!MO.getSubReg() && !MO.isEarlyClobber())
753 // We may wan't to extend a live range for a partial redef, or for a use
754 // tied to an early clobber.
755 Idx = Idx.getPrevSlot();
756 if (!Edit->getParent().liveAt(Idx))
759 Idx = Idx.getUseIndex();
761 extendRange(RegIdx, Idx);
765 void SplitEditor::deleteRematVictims() {
766 SmallVector<MachineInstr*, 8> Dead;
767 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I){
768 LiveInterval *LI = *I;
769 for (LiveInterval::const_iterator LII = LI->begin(), LIE = LI->end();
771 // Dead defs end at the store slot.
772 if (LII->end != LII->valno->def.getNextSlot())
774 MachineInstr *MI = LIS.getInstructionFromIndex(LII->valno->def);
775 assert(MI && "Missing instruction for dead def");
776 MI->addRegisterDead(LI->reg, &TRI);
778 if (!MI->allDefsAreDead())
781 DEBUG(dbgs() << "All defs dead: " << *MI);
789 Edit->eliminateDeadDefs(Dead, LIS, VRM, TII);
792 void SplitEditor::finish(SmallVectorImpl<unsigned> *LRMap) {
795 // At this point, the live intervals in Edit contain VNInfos corresponding to
796 // the inserted copies.
798 // Add the original defs from the parent interval.
799 for (LiveInterval::const_vni_iterator I = Edit->getParent().vni_begin(),
800 E = Edit->getParent().vni_end(); I != E; ++I) {
801 const VNInfo *ParentVNI = *I;
802 if (ParentVNI->isUnused())
804 unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
805 VNInfo *VNI = defValue(RegIdx, ParentVNI, ParentVNI->def);
806 VNI->setIsPHIDef(ParentVNI->isPHIDef());
807 VNI->setCopy(ParentVNI->getCopy());
809 // Mark rematted values as complex everywhere to force liveness computation.
810 // The new live ranges may be truncated.
811 if (Edit->didRematerialize(ParentVNI))
812 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
813 markComplexMapped(i, ParentVNI);
816 // Transfer the simply mapped values, check if any are skipped.
817 bool Skipped = transferValues();
819 extendPHIKillRanges();
823 // Rewrite virtual registers, possibly extending ranges.
824 rewriteAssigned(Skipped);
826 // Delete defs that were rematted everywhere.
828 deleteRematVictims();
830 // Get rid of unused values and set phi-kill flags.
831 for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I)
832 (*I)->RenumberValues(LIS);
834 // Provide a reverse mapping from original indices to Edit ranges.
837 for (unsigned i = 0, e = Edit->size(); i != e; ++i)
841 // Now check if any registers were separated into multiple components.
842 ConnectedVNInfoEqClasses ConEQ(LIS);
843 for (unsigned i = 0, e = Edit->size(); i != e; ++i) {
844 // Don't use iterators, they are invalidated by create() below.
845 LiveInterval *li = Edit->get(i);
846 unsigned NumComp = ConEQ.Classify(li);
849 DEBUG(dbgs() << " " << NumComp << " components: " << *li << '\n');
850 SmallVector<LiveInterval*, 8> dups;
852 for (unsigned j = 1; j != NumComp; ++j)
853 dups.push_back(&Edit->create(LIS, VRM));
854 ConEQ.Distribute(&dups[0], MRI);
855 // The new intervals all map back to i.
857 LRMap->resize(Edit->size(), i);
860 // Calculate spill weight and allocation hints for new intervals.
861 Edit->calculateRegClassAndHint(VRM.getMachineFunction(), LIS, SA.Loops);
863 assert(!LRMap || LRMap->size() == Edit->size());
867 //===----------------------------------------------------------------------===//
868 // Single Block Splitting
869 //===----------------------------------------------------------------------===//
871 bool SplitAnalysis::shouldSplitSingleBlock(const BlockInfo &BI,
872 bool SingleInstrs) const {
873 // Always split for multiple instructions.
874 if (!BI.isOneInstr())
876 // Don't split for single instructions unless explicitly requested.
879 // Splitting a live-through range always makes progress.
880 if (BI.LiveIn && BI.LiveOut)
882 // No point in isolating a copy. It has no register class constraints.
883 if (LIS.getInstructionFromIndex(BI.FirstInstr)->isCopyLike())
885 // Finally, don't isolate an end point that was created by earlier splits.
886 return isOriginalEndpoint(BI.FirstInstr);
889 void SplitEditor::splitSingleBlock(const SplitAnalysis::BlockInfo &BI) {
891 SlotIndex LastSplitPoint = SA.getLastSplitPoint(BI.MBB->getNumber());
892 SlotIndex SegStart = enterIntvBefore(std::min(BI.FirstInstr,
894 if (!BI.LiveOut || BI.LastInstr < LastSplitPoint) {
895 useIntv(SegStart, leaveIntvAfter(BI.LastInstr));
897 // The last use is after the last valid split point.
898 SlotIndex SegStop = leaveIntvBefore(LastSplitPoint);
899 useIntv(SegStart, SegStop);
900 overlapIntv(SegStop, BI.LastInstr);
905 //===----------------------------------------------------------------------===//
906 // Global Live Range Splitting Support
907 //===----------------------------------------------------------------------===//
909 // These methods support a method of global live range splitting that uses a
910 // global algorithm to decide intervals for CFG edges. They will insert split
911 // points and color intervals in basic blocks while avoiding interference.
913 // Note that splitSingleBlock is also useful for blocks where both CFG edges
916 void SplitEditor::splitLiveThroughBlock(unsigned MBBNum,
917 unsigned IntvIn, SlotIndex LeaveBefore,
918 unsigned IntvOut, SlotIndex EnterAfter){
919 SlotIndex Start, Stop;
920 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(MBBNum);
922 DEBUG(dbgs() << "BB#" << MBBNum << " [" << Start << ';' << Stop
923 << ") intf " << LeaveBefore << '-' << EnterAfter
924 << ", live-through " << IntvIn << " -> " << IntvOut);
926 assert((IntvIn || IntvOut) && "Use splitSingleBlock for isolated blocks");
928 assert((!LeaveBefore || LeaveBefore < Stop) && "Interference after block");
929 assert((!IntvIn || !LeaveBefore || LeaveBefore > Start) && "Impossible intf");
930 assert((!EnterAfter || EnterAfter >= Start) && "Interference before block");
932 MachineBasicBlock *MBB = VRM.getMachineFunction().getBlockNumbered(MBBNum);
935 DEBUG(dbgs() << ", spill on entry.\n");
937 // <<<<<<<<< Possible LeaveBefore interference.
938 // |-----------| Live through.
939 // -____________ Spill on entry.
942 SlotIndex Idx = leaveIntvAtTop(*MBB);
943 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
949 DEBUG(dbgs() << ", reload on exit.\n");
951 // >>>>>>> Possible EnterAfter interference.
952 // |-----------| Live through.
953 // ___________-- Reload on exit.
956 SlotIndex Idx = enterIntvAtEnd(*MBB);
957 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
962 if (IntvIn == IntvOut && !LeaveBefore && !EnterAfter) {
963 DEBUG(dbgs() << ", straight through.\n");
965 // |-----------| Live through.
966 // ------------- Straight through, same intv, no interference.
969 useIntv(Start, Stop);
973 // We cannot legally insert splits after LSP.
974 SlotIndex LSP = SA.getLastSplitPoint(MBBNum);
975 assert((!IntvOut || !EnterAfter || EnterAfter < LSP) && "Impossible intf");
977 if (IntvIn != IntvOut && (!LeaveBefore || !EnterAfter ||
978 LeaveBefore.getBaseIndex() > EnterAfter.getBoundaryIndex())) {
979 DEBUG(dbgs() << ", switch avoiding interference.\n");
981 // >>>> <<<< Non-overlapping EnterAfter/LeaveBefore interference.
982 // |-----------| Live through.
983 // ------======= Switch intervals between interference.
987 if (LeaveBefore && LeaveBefore < LSP) {
988 Idx = enterIntvBefore(LeaveBefore);
991 Idx = enterIntvAtEnd(*MBB);
995 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
996 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1000 DEBUG(dbgs() << ", create local intv for interference.\n");
1002 // >>><><><><<<< Overlapping EnterAfter/LeaveBefore interference.
1003 // |-----------| Live through.
1004 // ==---------== Switch intervals before/after interference.
1006 assert(LeaveBefore <= EnterAfter && "Missed case");
1008 selectIntv(IntvOut);
1009 SlotIndex Idx = enterIntvAfter(EnterAfter);
1011 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1014 Idx = leaveIntvBefore(LeaveBefore);
1015 useIntv(Start, Idx);
1016 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1020 void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
1021 unsigned IntvIn, SlotIndex LeaveBefore) {
1022 SlotIndex Start, Stop;
1023 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1025 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1026 << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1027 << ", reg-in " << IntvIn << ", leave before " << LeaveBefore
1028 << (BI.LiveOut ? ", stack-out" : ", killed in block"));
1030 assert(IntvIn && "Must have register in");
1031 assert(BI.LiveIn && "Must be live-in");
1032 assert((!LeaveBefore || LeaveBefore > Start) && "Bad interference");
1034 if (!BI.LiveOut && (!LeaveBefore || LeaveBefore >= BI.LastInstr)) {
1035 DEBUG(dbgs() << " before interference.\n");
1037 // <<< Interference after kill.
1038 // |---o---x | Killed in block.
1039 // ========= Use IntvIn everywhere.
1042 useIntv(Start, BI.LastInstr);
1046 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1048 if (!LeaveBefore || LeaveBefore > BI.LastInstr.getBoundaryIndex()) {
1050 // <<< Possible interference after last use.
1051 // |---o---o---| Live-out on stack.
1052 // =========____ Leave IntvIn after last use.
1054 // < Interference after last use.
1055 // |---o---o--o| Live-out on stack, late last use.
1056 // ============ Copy to stack after LSP, overlap IntvIn.
1057 // \_____ Stack interval is live-out.
1059 if (BI.LastInstr < LSP) {
1060 DEBUG(dbgs() << ", spill after last use before interference.\n");
1062 SlotIndex Idx = leaveIntvAfter(BI.LastInstr);
1063 useIntv(Start, Idx);
1064 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1066 DEBUG(dbgs() << ", spill before last split point.\n");
1068 SlotIndex Idx = leaveIntvBefore(LSP);
1069 overlapIntv(Idx, BI.LastInstr);
1070 useIntv(Start, Idx);
1071 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
1076 // The interference is overlapping somewhere we wanted to use IntvIn. That
1077 // means we need to create a local interval that can be allocated a
1078 // different register.
1079 unsigned LocalIntv = openIntv();
1081 DEBUG(dbgs() << ", creating local interval " << LocalIntv << ".\n");
1083 if (!BI.LiveOut || BI.LastInstr < LSP) {
1085 // <<<<<<< Interference overlapping uses.
1086 // |---o---o---| Live-out on stack.
1087 // =====----____ Leave IntvIn before interference, then spill.
1089 SlotIndex To = leaveIntvAfter(BI.LastInstr);
1090 SlotIndex From = enterIntvBefore(LeaveBefore);
1093 useIntv(Start, From);
1094 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1098 // <<<<<<< Interference overlapping uses.
1099 // |---o---o--o| Live-out on stack, late last use.
1100 // =====------- Copy to stack before LSP, overlap LocalIntv.
1101 // \_____ Stack interval is live-out.
1103 SlotIndex To = leaveIntvBefore(LSP);
1104 overlapIntv(To, BI.LastInstr);
1105 SlotIndex From = enterIntvBefore(std::min(To, LeaveBefore));
1108 useIntv(Start, From);
1109 assert((!LeaveBefore || From <= LeaveBefore) && "Interference");
1112 void SplitEditor::splitRegOutBlock(const SplitAnalysis::BlockInfo &BI,
1113 unsigned IntvOut, SlotIndex EnterAfter) {
1114 SlotIndex Start, Stop;
1115 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
1117 DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " [" << Start << ';' << Stop
1118 << "), uses " << BI.FirstInstr << '-' << BI.LastInstr
1119 << ", reg-out " << IntvOut << ", enter after " << EnterAfter
1120 << (BI.LiveIn ? ", stack-in" : ", defined in block"));
1122 SlotIndex LSP = SA.getLastSplitPoint(BI.MBB->getNumber());
1124 assert(IntvOut && "Must have register out");
1125 assert(BI.LiveOut && "Must be live-out");
1126 assert((!EnterAfter || EnterAfter < LSP) && "Bad interference");
1128 if (!BI.LiveIn && (!EnterAfter || EnterAfter <= BI.FirstInstr)) {
1129 DEBUG(dbgs() << " after interference.\n");
1131 // >>>> Interference before def.
1132 // | o---o---| Defined in block.
1133 // ========= Use IntvOut everywhere.
1135 selectIntv(IntvOut);
1136 useIntv(BI.FirstInstr, Stop);
1140 if (!EnterAfter || EnterAfter < BI.FirstInstr.getBaseIndex()) {
1141 DEBUG(dbgs() << ", reload after interference.\n");
1143 // >>>> Interference before def.
1144 // |---o---o---| Live-through, stack-in.
1145 // ____========= Enter IntvOut before first use.
1147 selectIntv(IntvOut);
1148 SlotIndex Idx = enterIntvBefore(std::min(LSP, BI.FirstInstr));
1150 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1154 // The interference is overlapping somewhere we wanted to use IntvOut. That
1155 // means we need to create a local interval that can be allocated a
1156 // different register.
1157 DEBUG(dbgs() << ", interference overlaps uses.\n");
1159 // >>>>>>> Interference overlapping uses.
1160 // |---o---o---| Live-through, stack-in.
1161 // ____---====== Create local interval for interference range.
1163 selectIntv(IntvOut);
1164 SlotIndex Idx = enterIntvAfter(EnterAfter);
1166 assert((!EnterAfter || Idx >= EnterAfter) && "Interference");
1169 SlotIndex From = enterIntvBefore(std::min(Idx, BI.FirstInstr));