1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/Analysis/LoopInfo.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/CodeGen/RegisterCoalescer.h"
27 #include "llvm/Target/MRegisterInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/ADT/SmallSet.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
39 STATISTIC(numJoins , "Number of interval joins performed");
40 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
41 STATISTIC(numAborts , "Number of times interval joining aborted");
43 char SimpleRegisterCoalescing::ID = 0;
46 EnableJoining("join-liveintervals",
47 cl::desc("Coalesce copies (default=true)"),
51 NewHeuristic("new-coalescer-heuristic",
52 cl::desc("Use new coalescer heuristic"),
55 RegisterPass<SimpleRegisterCoalescing>
56 X("simple-register-coalescing", "Simple Register Coalescing");
58 // Declare that we implement the RegisterCoalescer interface
59 RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
62 const PassInfo *llvm::SimpleRegisterCoalescingID = X.getPassInfo();
64 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
65 AU.addPreserved<LiveIntervals>();
66 AU.addPreservedID(PHIEliminationID);
67 AU.addPreservedID(TwoAddressInstructionPassID);
68 AU.addRequired<LiveVariables>();
69 AU.addRequired<LiveIntervals>();
70 AU.addRequired<LoopInfo>();
71 MachineFunctionPass::getAnalysisUsage(AU);
74 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
75 /// being the source and IntB being the dest, thus this defines a value number
76 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
77 /// see if we can merge these two pieces of B into a single value number,
78 /// eliminating a copy. For example:
82 /// B1 = A3 <- this copy
84 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
85 /// value number to be replaced with B0 (which simplifies the B liveinterval).
87 /// This returns true if an interval was modified.
89 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
90 MachineInstr *CopyMI) {
91 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
93 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
95 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
96 VNInfo *BValNo = BLR->valno;
98 // Get the location that B is defined at. Two options: either this value has
99 // an unknown definition point or it is defined at CopyIdx. If unknown, we
101 if (!BValNo->reg) return false;
102 assert(BValNo->def == CopyIdx &&
103 "Copy doesn't define the value?");
105 // AValNo is the value number in A that defines the copy, A0 in the example.
106 LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1);
107 VNInfo *AValNo = AValLR->valno;
109 // If AValNo is defined as a copy from IntB, we can potentially process this.
111 // Get the instruction that defines this value number.
112 unsigned SrcReg = AValNo->reg;
113 if (!SrcReg) return false; // Not defined by a copy.
115 // If the value number is not defined by a copy instruction, ignore it.
117 // If the source register comes from an interval other than IntB, we can't
119 if (rep(SrcReg) != IntB.reg) return false;
121 // Get the LiveRange in IntB that this value number starts with.
122 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
124 // Make sure that the end of the live range is inside the same block as
126 MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
128 ValLREndInst->getParent() != CopyMI->getParent()) return false;
130 // Okay, we now know that ValLR ends in the same block that the CopyMI
131 // live-range starts. If there are no intervening live ranges between them in
132 // IntB, we can merge them.
133 if (ValLR+1 != BLR) return false;
135 // If a live interval is a physical register, conservatively check if any
136 // of its sub-registers is overlapping the live interval of the virtual
137 // register. If so, do not coalesce.
138 if (MRegisterInfo::isPhysicalRegister(IntB.reg) &&
139 *mri_->getSubRegisters(IntB.reg)) {
140 for (const unsigned* SR = mri_->getSubRegisters(IntB.reg); *SR; ++SR)
141 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
142 DOUT << "Interfere with sub-register ";
143 DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
148 DOUT << "\nExtending: "; IntB.print(DOUT, mri_);
150 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
151 // We are about to delete CopyMI, so need to remove it as the 'instruction
152 // that defines this value #'. Update the the valnum with the new defining
154 BValNo->def = FillerStart;
157 // Okay, we can merge them. We need to insert a new liverange:
158 // [ValLR.end, BLR.begin) of either value number, then we merge the
159 // two value numbers.
160 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
162 // If the IntB live range is assigned to a physical register, and if that
163 // physreg has aliases,
164 if (MRegisterInfo::isPhysicalRegister(IntB.reg)) {
165 // Update the liveintervals of sub-registers.
166 for (const unsigned *AS = mri_->getSubRegisters(IntB.reg); *AS; ++AS) {
167 LiveInterval &AliasLI = li_->getInterval(*AS);
168 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
169 AliasLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator())));
173 // Okay, merge "B1" into the same value number as "B0".
174 if (BValNo != ValLR->valno)
175 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
176 DOUT << " result = "; IntB.print(DOUT, mri_);
179 // If the source instruction was killing the source register before the
180 // merge, unset the isKill marker given the live range has been extended.
181 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
183 ValLREndInst->getOperand(UIdx).unsetIsKill();
189 /// AddSubRegIdxPairs - Recursively mark all the registers represented by the
190 /// specified register as sub-registers. The recursion level is expected to be
192 void SimpleRegisterCoalescing::AddSubRegIdxPairs(unsigned Reg, unsigned SubIdx) {
193 std::vector<unsigned> &JoinedRegs = r2rRevMap_[Reg];
194 for (unsigned i = 0, e = JoinedRegs.size(); i != e; ++i) {
195 SubRegIdxes.push_back(std::make_pair(JoinedRegs[i], SubIdx));
196 AddSubRegIdxPairs(JoinedRegs[i], SubIdx);
200 /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
202 bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
204 MachineBasicBlock *MBB = CopyMI->getParent();
205 const BasicBlock *BB = MBB->getBasicBlock();
206 const Loop *L = loopInfo->getLoopFor(BB);
209 if (BB != L->getLoopLatch())
212 DstReg = rep(DstReg);
213 LiveInterval &LI = li_->getInterval(DstReg);
214 unsigned DefIdx = li_->getInstructionIndex(CopyMI);
215 LiveInterval::const_iterator DstLR =
216 LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx));
217 if (DstLR == LI.end())
219 unsigned KillIdx = li_->getInstructionIndex(&MBB->back()) + InstrSlots::NUM-1;
220 if (DstLR->valno->kills.size() == 1 && DstLR->valno->kills[0] == KillIdx)
225 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
226 /// which are the src/dst of the copy instruction CopyMI. This returns true
227 /// if the copy was successfully coalesced away. If it is not currently
228 /// possible to coalesce this interval, but it may be possible if other
229 /// things get coalesced, then it returns true by reference in 'Again'.
230 bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) {
231 MachineInstr *CopyMI = TheCopy.MI;
234 if (JoinedCopies.count(CopyMI))
235 return false; // Already done.
237 DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
239 // Get representative registers.
240 unsigned SrcReg = TheCopy.SrcReg;
241 unsigned DstReg = TheCopy.DstReg;
242 unsigned repSrcReg = rep(SrcReg);
243 unsigned repDstReg = rep(DstReg);
245 // If they are already joined we continue.
246 if (repSrcReg == repDstReg) {
247 DOUT << "\tCopy already coalesced.\n";
248 return false; // Not coalescable.
251 bool SrcIsPhys = MRegisterInfo::isPhysicalRegister(repSrcReg);
252 bool DstIsPhys = MRegisterInfo::isPhysicalRegister(repDstReg);
254 // If they are both physical registers, we cannot join them.
255 if (SrcIsPhys && DstIsPhys) {
256 DOUT << "\tCan not coalesce physregs.\n";
257 return false; // Not coalescable.
260 // We only join virtual registers with allocatable physical registers.
261 if (SrcIsPhys && !allocatableRegs_[repSrcReg]) {
262 DOUT << "\tSrc reg is unallocatable physreg.\n";
263 return false; // Not coalescable.
265 if (DstIsPhys && !allocatableRegs_[repDstReg]) {
266 DOUT << "\tDst reg is unallocatable physreg.\n";
267 return false; // Not coalescable.
270 bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
271 unsigned RealDstReg = 0;
273 unsigned SubIdx = CopyMI->getOperand(2).getImm();
275 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
276 // coalesced with AX.
277 repSrcReg = mri_->getSubReg(repSrcReg, SubIdx);
278 else if (DstIsPhys) {
279 // If this is a extract_subreg where dst is a physical register, e.g.
280 // cl = EXTRACT_SUBREG reg1024, 1
281 // then create and update the actual physical register allocated to RHS.
282 const TargetRegisterClass *RC=mf_->getSSARegMap()->getRegClass(repSrcReg);
283 for (const unsigned *SRs = mri_->getSuperRegisters(repDstReg);
284 unsigned SR = *SRs; ++SRs) {
285 if (repDstReg == mri_->getSubReg(SR, SubIdx) &&
291 assert(RealDstReg && "Invalid extra_subreg instruction!");
293 // For this type of EXTRACT_SUBREG, conservatively
294 // check if the live interval of the source register interfere with the
295 // actual super physical register we are trying to coalesce with.
296 LiveInterval &RHS = li_->getInterval(repSrcReg);
297 if (li_->hasInterval(RealDstReg) &&
298 RHS.overlaps(li_->getInterval(RealDstReg))) {
299 DOUT << "Interfere with register ";
300 DEBUG(li_->getInterval(RealDstReg).print(DOUT, mri_));
301 return false; // Not coalescable
303 for (const unsigned* SR = mri_->getSubRegisters(RealDstReg); *SR; ++SR)
304 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
305 DOUT << "Interfere with sub-register ";
306 DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
307 return false; // Not coalescable
310 unsigned SrcSize= li_->getInterval(repSrcReg).getSize() / InstrSlots::NUM;
311 unsigned DstSize= li_->getInterval(repDstReg).getSize() / InstrSlots::NUM;
312 const TargetRegisterClass *RC=mf_->getSSARegMap()->getRegClass(repDstReg);
313 unsigned Threshold = allocatableRCRegs_[RC].count();
314 // Be conservative. If both sides are virtual registers, do not coalesce
315 // if this will cause a high use density interval to target a smaller set
317 if (DstSize > Threshold || SrcSize > Threshold) {
318 LiveVariables::VarInfo &svi = lv_->getVarInfo(repSrcReg);
319 LiveVariables::VarInfo &dvi = lv_->getVarInfo(repDstReg);
320 if ((float)dvi.NumUses / DstSize < (float)svi.NumUses / SrcSize) {
321 Again = true; // May be possible to coalesce later.
326 } else if (differingRegisterClasses(repSrcReg, repDstReg)) {
327 // If they are not of the same register class, we cannot join them.
328 DOUT << "\tSrc/Dest are different register classes.\n";
329 // Allow the coalescer to try again in case either side gets coalesced to
330 // a physical register that's compatible with the other side. e.g.
331 // r1024 = MOV32to32_ r1025
332 // but later r1024 is assigned EAX then r1025 may be coalesced with EAX.
333 Again = true; // May be possible to coalesce later.
337 LiveInterval &SrcInt = li_->getInterval(repSrcReg);
338 LiveInterval &DstInt = li_->getInterval(repDstReg);
339 assert(SrcInt.reg == repSrcReg && DstInt.reg == repDstReg &&
340 "Register mapping is horribly broken!");
342 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_);
343 DOUT << " and "; DstInt.print(DOUT, mri_);
346 // Check if it is necessary to propagate "isDead" property before intervals
348 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg);
349 bool isDead = mopd->isDead();
350 bool isShorten = false;
351 unsigned SrcStart = 0, RemoveStart = 0;
352 unsigned SrcEnd = 0, RemoveEnd = 0;
354 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
355 LiveInterval::iterator SrcLR =
356 SrcInt.FindLiveRangeContaining(li_->getUseIndex(CopyIdx));
357 RemoveStart = SrcStart = SrcLR->start;
358 RemoveEnd = SrcEnd = SrcLR->end;
359 // The instruction which defines the src is only truly dead if there are
360 // no intermediate uses and there isn't a use beyond the copy.
361 // FIXME: find the last use, mark is kill and shorten the live range.
362 if (SrcEnd > li_->getDefIndex(CopyIdx)) {
366 MachineInstr *LastUse= lastRegisterUse(SrcStart, CopyIdx, repSrcReg, MOU);
368 // Shorten the liveinterval to the end of last use.
372 RemoveStart = li_->getDefIndex(li_->getInstructionIndex(LastUse));
375 MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart);
377 MachineOperand *mops = findDefOperand(SrcMI, repSrcReg);
379 // A dead def should have a single cycle interval.
386 // We need to be careful about coalescing a source physical register with a
387 // virtual register. Once the coalescing is done, it cannot be broken and
388 // these are not spillable! If the destination interval uses are far away,
389 // think twice about coalescing them!
390 if (!mopd->isDead() && (SrcIsPhys || DstIsPhys) && !isExtSubReg) {
391 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
392 unsigned JoinVReg = SrcIsPhys ? repDstReg : repSrcReg;
393 unsigned JoinPReg = SrcIsPhys ? repSrcReg : repDstReg;
394 const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(JoinVReg);
395 unsigned Threshold = allocatableRCRegs_[RC].count();
396 if (TheCopy.isBackEdge)
397 Threshold *= 2; // Favors back edge copies.
399 // If the virtual register live interval is long but it has low use desity,
400 // do not join them, instead mark the physical register as its allocation
402 unsigned Length = JoinVInt.getSize() / InstrSlots::NUM;
403 LiveVariables::VarInfo &vi = lv_->getVarInfo(JoinVReg);
404 if (Length > Threshold &&
405 (((float)vi.NumUses / Length) < (1.0 / Threshold))) {
406 JoinVInt.preference = JoinPReg;
408 DOUT << "\tMay tie down a physical register, abort!\n";
409 Again = true; // May be possible to coalesce later.
414 // Okay, attempt to join these two intervals. On failure, this returns false.
415 // Otherwise, if one of the intervals being joined is a physreg, this method
416 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
417 // been modified, so we can use this information below to update aliases.
418 bool Swapped = false;
419 if (JoinIntervals(DstInt, SrcInt, Swapped)) {
421 // Result of the copy is dead. Propagate this property.
423 assert(MRegisterInfo::isPhysicalRegister(repSrcReg) &&
424 "Live-in must be a physical register!");
425 // Live-in to the function but dead. Remove it from entry live-in set.
426 // JoinIntervals may end up swapping the two intervals.
427 mf_->begin()->removeLiveIn(repSrcReg);
429 MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart);
431 MachineOperand *mops = findDefOperand(SrcMI, repSrcReg);
438 if (isShorten || isDead) {
439 // Shorten the destination live interval.
441 SrcInt.removeRange(RemoveStart, RemoveEnd);
444 // Coalescing failed.
446 // If we can eliminate the copy without merging the live ranges, do so now.
447 if (!isExtSubReg && AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI)) {
448 JoinedCopies.insert(CopyMI);
452 // Otherwise, we are unable to join the intervals.
453 DOUT << "Interference!\n";
454 Again = true; // May be possible to coalesce later.
458 LiveInterval *ResSrcInt = &SrcInt;
459 LiveInterval *ResDstInt = &DstInt;
461 std::swap(repSrcReg, repDstReg);
462 std::swap(ResSrcInt, ResDstInt);
464 assert(MRegisterInfo::isVirtualRegister(repSrcReg) &&
465 "LiveInterval::join didn't work right!");
467 // If we're about to merge live ranges into a physical register live range,
468 // we have to update any aliased register's live ranges to indicate that they
469 // have clobbered values for this range.
470 if (MRegisterInfo::isPhysicalRegister(repDstReg)) {
471 // Unset unnecessary kills.
472 if (!ResDstInt->containsOneValue()) {
473 for (LiveInterval::Ranges::const_iterator I = ResSrcInt->begin(),
474 E = ResSrcInt->end(); I != E; ++I)
475 unsetRegisterKills(I->start, I->end, repDstReg);
478 // If this is a extract_subreg where dst is a physical register, e.g.
479 // cl = EXTRACT_SUBREG reg1024, 1
480 // then create and update the actual physical register allocated to RHS.
482 LiveInterval &RealDstInt = li_->getOrCreateInterval(RealDstReg);
483 SmallSet<const VNInfo*, 4> CopiedValNos;
484 for (LiveInterval::Ranges::const_iterator I = ResSrcInt->ranges.begin(),
485 E = ResSrcInt->ranges.end(); I != E; ++I) {
486 LiveInterval::const_iterator DstLR =
487 ResDstInt->FindLiveRangeContaining(I->start);
488 assert(DstLR != ResDstInt->end() && "Invalid joined interval!");
489 const VNInfo *DstValNo = DstLR->valno;
490 if (CopiedValNos.insert(DstValNo)) {
491 VNInfo *ValNo = RealDstInt.getNextValue(DstValNo->def, DstValNo->reg,
492 li_->getVNInfoAllocator());
493 RealDstInt.addKills(ValNo, DstValNo->kills);
494 RealDstInt.MergeValueInAsValue(*ResDstInt, DstValNo, ValNo);
497 repDstReg = RealDstReg;
500 // Update the liveintervals of sub-registers.
501 for (const unsigned *AS = mri_->getSubRegisters(repDstReg); *AS; ++AS)
502 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt,
503 li_->getVNInfoAllocator());
505 // Merge use info if the destination is a virtual register.
506 LiveVariables::VarInfo& dVI = lv_->getVarInfo(repDstReg);
507 LiveVariables::VarInfo& sVI = lv_->getVarInfo(repSrcReg);
508 dVI.NumUses += sVI.NumUses;
511 // Remember these liveintervals have been joined.
512 JoinedLIs.set(repSrcReg - MRegisterInfo::FirstVirtualRegister);
513 if (MRegisterInfo::isVirtualRegister(repDstReg))
514 JoinedLIs.set(repDstReg - MRegisterInfo::FirstVirtualRegister);
516 if (isExtSubReg && !SrcIsPhys && !DstIsPhys) {
518 // Make sure we allocate the larger super-register.
519 ResSrcInt->Copy(*ResDstInt, li_->getVNInfoAllocator());
520 std::swap(repSrcReg, repDstReg);
521 std::swap(ResSrcInt, ResDstInt);
523 unsigned SubIdx = CopyMI->getOperand(2).getImm();
524 SubRegIdxes.push_back(std::make_pair(repSrcReg, SubIdx));
525 AddSubRegIdxPairs(repSrcReg, SubIdx);
529 for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(),
530 e = ResSrcInt->vni_end(); i != e; ++i) {
531 const VNInfo *vni = *i;
532 if (vni->def && vni->def != ~1U && vni->def != ~0U) {
533 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
534 unsigned SrcReg, DstReg;
535 if (CopyMI && tii_->isMoveInstr(*CopyMI, SrcReg, DstReg) &&
536 JoinedCopies.count(CopyMI) == 0) {
538 loopInfo->getLoopDepth(CopyMI->getParent()->getBasicBlock());
539 JoinQueue->push(CopyRec(CopyMI, SrcReg, DstReg, LoopDepth,
540 isBackEdgeCopy(CopyMI, DstReg)));
546 DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, mri_);
549 // repSrcReg is guarateed to be the register whose live interval that is
551 li_->removeInterval(repSrcReg);
552 r2rMap_[repSrcReg] = repDstReg;
553 r2rRevMap_[repDstReg].push_back(repSrcReg);
555 // Finally, delete the copy instruction.
556 JoinedCopies.insert(CopyMI);
562 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
563 /// compute what the resultant value numbers for each value in the input two
564 /// ranges will be. This is complicated by copies between the two which can
565 /// and will commonly cause multiple value numbers to be merged into one.
567 /// VN is the value number that we're trying to resolve. InstDefiningValue
568 /// keeps track of the new InstDefiningValue assignment for the result
569 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
570 /// whether a value in this or other is a copy from the opposite set.
571 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
572 /// already been assigned.
574 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
575 /// contains the value number the copy is from.
577 static unsigned ComputeUltimateVN(VNInfo *VNI,
578 SmallVector<VNInfo*, 16> &NewVNInfo,
579 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
580 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
581 SmallVector<int, 16> &ThisValNoAssignments,
582 SmallVector<int, 16> &OtherValNoAssignments) {
583 unsigned VN = VNI->id;
585 // If the VN has already been computed, just return it.
586 if (ThisValNoAssignments[VN] >= 0)
587 return ThisValNoAssignments[VN];
588 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
590 // If this val is not a copy from the other val, then it must be a new value
591 // number in the destination.
592 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
593 if (I == ThisFromOther.end()) {
594 NewVNInfo.push_back(VNI);
595 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
597 VNInfo *OtherValNo = I->second;
599 // Otherwise, this *is* a copy from the RHS. If the other side has already
600 // been computed, return it.
601 if (OtherValNoAssignments[OtherValNo->id] >= 0)
602 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
604 // Mark this value number as currently being computed, then ask what the
605 // ultimate value # of the other value is.
606 ThisValNoAssignments[VN] = -2;
607 unsigned UltimateVN =
608 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
609 OtherValNoAssignments, ThisValNoAssignments);
610 return ThisValNoAssignments[VN] = UltimateVN;
613 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
614 return std::find(V.begin(), V.end(), Val) != V.end();
617 /// SimpleJoin - Attempt to joint the specified interval into this one. The
618 /// caller of this method must guarantee that the RHS only contains a single
619 /// value number and that the RHS is not defined by a copy from this
620 /// interval. This returns false if the intervals are not joinable, or it
621 /// joins them and returns true.
622 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) {
623 assert(RHS.containsOneValue());
625 // Some number (potentially more than one) value numbers in the current
626 // interval may be defined as copies from the RHS. Scan the overlapping
627 // portions of the LHS and RHS, keeping track of this and looking for
628 // overlapping live ranges that are NOT defined as copies. If these exist, we
631 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
632 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
634 if (LHSIt->start < RHSIt->start) {
635 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
636 if (LHSIt != LHS.begin()) --LHSIt;
637 } else if (RHSIt->start < LHSIt->start) {
638 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
639 if (RHSIt != RHS.begin()) --RHSIt;
642 SmallVector<VNInfo*, 8> EliminatedLHSVals;
645 // Determine if these live intervals overlap.
646 bool Overlaps = false;
647 if (LHSIt->start <= RHSIt->start)
648 Overlaps = LHSIt->end > RHSIt->start;
650 Overlaps = RHSIt->end > LHSIt->start;
652 // If the live intervals overlap, there are two interesting cases: if the
653 // LHS interval is defined by a copy from the RHS, it's ok and we record
654 // that the LHS value # is the same as the RHS. If it's not, then we cannot
655 // coalesce these live ranges and we bail out.
657 // If we haven't already recorded that this value # is safe, check it.
658 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
659 // Copy from the RHS?
660 unsigned SrcReg = LHSIt->valno->reg;
661 if (rep(SrcReg) != RHS.reg)
662 return false; // Nope, bail out.
664 EliminatedLHSVals.push_back(LHSIt->valno);
667 // We know this entire LHS live range is okay, so skip it now.
668 if (++LHSIt == LHSEnd) break;
672 if (LHSIt->end < RHSIt->end) {
673 if (++LHSIt == LHSEnd) break;
675 // One interesting case to check here. It's possible that we have
676 // something like "X3 = Y" which defines a new value number in the LHS,
677 // and is the last use of this liverange of the RHS. In this case, we
678 // want to notice this copy (so that it gets coalesced away) even though
679 // the live ranges don't actually overlap.
680 if (LHSIt->start == RHSIt->end) {
681 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
682 // We already know that this value number is going to be merged in
683 // if coalescing succeeds. Just skip the liverange.
684 if (++LHSIt == LHSEnd) break;
686 // Otherwise, if this is a copy from the RHS, mark it as being merged
688 if (rep(LHSIt->valno->reg) == RHS.reg) {
689 EliminatedLHSVals.push_back(LHSIt->valno);
691 // We know this entire LHS live range is okay, so skip it now.
692 if (++LHSIt == LHSEnd) break;
697 if (++RHSIt == RHSEnd) break;
701 // If we got here, we know that the coalescing will be successful and that
702 // the value numbers in EliminatedLHSVals will all be merged together. Since
703 // the most common case is that EliminatedLHSVals has a single number, we
704 // optimize for it: if there is more than one value, we merge them all into
705 // the lowest numbered one, then handle the interval as if we were merging
706 // with one value number.
708 if (EliminatedLHSVals.size() > 1) {
709 // Loop through all the equal value numbers merging them into the smallest
711 VNInfo *Smallest = EliminatedLHSVals[0];
712 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
713 if (EliminatedLHSVals[i]->id < Smallest->id) {
714 // Merge the current notion of the smallest into the smaller one.
715 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
716 Smallest = EliminatedLHSVals[i];
718 // Merge into the smallest.
719 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
724 assert(!EliminatedLHSVals.empty() && "No copies from the RHS?");
725 LHSValNo = EliminatedLHSVals[0];
728 // Okay, now that there is a single LHS value number that we're merging the
729 // RHS into, update the value number info for the LHS to indicate that the
730 // value number is defined where the RHS value number was.
731 const VNInfo *VNI = RHS.getValNumInfo(0);
732 LHSValNo->def = VNI->def;
733 LHSValNo->reg = VNI->reg;
735 // Okay, the final step is to loop over the RHS live intervals, adding them to
737 LHS.addKills(LHSValNo, VNI->kills);
738 LHS.MergeRangesInAsValue(RHS, LHSValNo);
739 LHS.weight += RHS.weight;
740 if (RHS.preference && !LHS.preference)
741 LHS.preference = RHS.preference;
746 /// JoinIntervals - Attempt to join these two intervals. On failure, this
747 /// returns false. Otherwise, if one of the intervals being joined is a
748 /// physreg, this method always canonicalizes LHS to be it. The output
749 /// "RHS" will not have been modified, so we can use this information
750 /// below to update aliases.
751 bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS,
752 LiveInterval &RHS, bool &Swapped) {
753 // Compute the final value assignment, assuming that the live ranges can be
755 SmallVector<int, 16> LHSValNoAssignments;
756 SmallVector<int, 16> RHSValNoAssignments;
757 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
758 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
759 SmallVector<VNInfo*, 16> NewVNInfo;
761 // If a live interval is a physical register, conservatively check if any
762 // of its sub-registers is overlapping the live interval of the virtual
763 // register. If so, do not coalesce.
764 if (MRegisterInfo::isPhysicalRegister(LHS.reg) &&
765 *mri_->getSubRegisters(LHS.reg)) {
766 for (const unsigned* SR = mri_->getSubRegisters(LHS.reg); *SR; ++SR)
767 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
768 DOUT << "Interfere with sub-register ";
769 DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
772 } else if (MRegisterInfo::isPhysicalRegister(RHS.reg) &&
773 *mri_->getSubRegisters(RHS.reg)) {
774 for (const unsigned* SR = mri_->getSubRegisters(RHS.reg); *SR; ++SR)
775 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
776 DOUT << "Interfere with sub-register ";
777 DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
782 // Compute ultimate value numbers for the LHS and RHS values.
783 if (RHS.containsOneValue()) {
784 // Copies from a liveinterval with a single value are simple to handle and
785 // very common, handle the special case here. This is important, because
786 // often RHS is small and LHS is large (e.g. a physreg).
788 // Find out if the RHS is defined as a copy from some value in the LHS.
789 int RHSVal0DefinedFromLHS = -1;
791 VNInfo *RHSValNoInfo = NULL;
792 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
793 unsigned RHSSrcReg = RHSValNoInfo0->reg;
794 if ((RHSSrcReg == 0 || rep(RHSSrcReg) != LHS.reg)) {
795 // If RHS is not defined as a copy from the LHS, we can use simpler and
796 // faster checks to see if the live ranges are coalescable. This joiner
797 // can't swap the LHS/RHS intervals though.
798 if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) {
799 return SimpleJoin(LHS, RHS);
801 RHSValNoInfo = RHSValNoInfo0;
804 // It was defined as a copy from the LHS, find out what value # it is.
805 RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno;
806 RHSValID = RHSValNoInfo->id;
807 RHSVal0DefinedFromLHS = RHSValID;
810 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
811 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
812 NewVNInfo.resize(LHS.getNumValNums(), NULL);
814 // Okay, *all* of the values in LHS that are defined as a copy from RHS
815 // should now get updated.
816 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
819 unsigned VN = VNI->id;
820 if (unsigned LHSSrcReg = VNI->reg) {
821 if (rep(LHSSrcReg) != RHS.reg) {
822 // If this is not a copy from the RHS, its value number will be
823 // unmodified by the coalescing.
825 LHSValNoAssignments[VN] = VN;
826 } else if (RHSValID == -1) {
827 // Otherwise, it is a copy from the RHS, and we don't already have a
828 // value# for it. Keep the current value number, but remember it.
829 LHSValNoAssignments[VN] = RHSValID = VN;
830 NewVNInfo[VN] = RHSValNoInfo;
831 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
833 // Otherwise, use the specified value #.
834 LHSValNoAssignments[VN] = RHSValID;
835 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
836 NewVNInfo[VN] = RHSValNoInfo;
837 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
842 LHSValNoAssignments[VN] = VN;
846 assert(RHSValID != -1 && "Didn't find value #?");
847 RHSValNoAssignments[0] = RHSValID;
848 if (RHSVal0DefinedFromLHS != -1) {
849 // This path doesn't go through ComputeUltimateVN so just set
851 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
854 // Loop over the value numbers of the LHS, seeing if any are defined from
856 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
859 unsigned ValSrcReg = VNI->reg;
860 if (VNI->def == ~1U ||ValSrcReg == 0) // Src not defined by a copy?
863 // DstReg is known to be a register in the LHS interval. If the src is
864 // from the RHS interval, we can use its value #.
865 if (rep(ValSrcReg) != RHS.reg)
868 // Figure out the value # from the RHS.
869 LHSValsDefinedFromRHS[VNI] = RHS.getLiveRangeContaining(VNI->def-1)->valno;
872 // Loop over the value numbers of the RHS, seeing if any are defined from
874 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
877 unsigned ValSrcReg = VNI->reg;
878 if (VNI->def == ~1U || ValSrcReg == 0) // Src not defined by a copy?
881 // DstReg is known to be a register in the RHS interval. If the src is
882 // from the LHS interval, we can use its value #.
883 if (rep(ValSrcReg) != LHS.reg)
886 // Figure out the value # from the LHS.
887 RHSValsDefinedFromLHS[VNI]= LHS.getLiveRangeContaining(VNI->def-1)->valno;
890 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
891 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
892 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
894 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
897 unsigned VN = VNI->id;
898 if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
900 ComputeUltimateVN(VNI, NewVNInfo,
901 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
902 LHSValNoAssignments, RHSValNoAssignments);
904 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
907 unsigned VN = VNI->id;
908 if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
910 // If this value number isn't a copy from the LHS, it's a new number.
911 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
912 NewVNInfo.push_back(VNI);
913 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
917 ComputeUltimateVN(VNI, NewVNInfo,
918 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
919 RHSValNoAssignments, LHSValNoAssignments);
923 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
924 // interval lists to see if these intervals are coalescable.
925 LiveInterval::const_iterator I = LHS.begin();
926 LiveInterval::const_iterator IE = LHS.end();
927 LiveInterval::const_iterator J = RHS.begin();
928 LiveInterval::const_iterator JE = RHS.end();
930 // Skip ahead until the first place of potential sharing.
931 if (I->start < J->start) {
932 I = std::upper_bound(I, IE, J->start);
933 if (I != LHS.begin()) --I;
934 } else if (J->start < I->start) {
935 J = std::upper_bound(J, JE, I->start);
936 if (J != RHS.begin()) --J;
940 // Determine if these two live ranges overlap.
942 if (I->start < J->start) {
943 Overlaps = I->end > J->start;
945 Overlaps = J->end > I->start;
948 // If so, check value # info to determine if they are really different.
950 // If the live range overlap will map to the same value number in the
951 // result liverange, we can still coalesce them. If not, we can't.
952 if (LHSValNoAssignments[I->valno->id] !=
953 RHSValNoAssignments[J->valno->id])
957 if (I->end < J->end) {
966 // Update kill info. Some live ranges are extended due to copy coalescing.
967 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
968 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
969 VNInfo *VNI = I->first;
970 unsigned LHSValID = LHSValNoAssignments[VNI->id];
971 LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def);
972 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
975 // Update kill info. Some live ranges are extended due to copy coalescing.
976 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
977 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
978 VNInfo *VNI = I->first;
979 unsigned RHSValID = RHSValNoAssignments[VNI->id];
980 LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def);
981 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
984 // If we get here, we know that we can coalesce the live ranges. Ask the
985 // intervals to coalesce themselves now.
986 if ((RHS.ranges.size() > LHS.ranges.size() &&
987 MRegisterInfo::isVirtualRegister(LHS.reg)) ||
988 MRegisterInfo::isPhysicalRegister(RHS.reg)) {
989 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo);
992 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo);
999 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1000 // depth of the basic block (the unsigned), and then on the MBB number.
1001 struct DepthMBBCompare {
1002 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1003 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1004 if (LHS.first > RHS.first) return true; // Deeper loops first
1005 return LHS.first == RHS.first &&
1006 LHS.second->getNumber() < RHS.second->getNumber();
1011 /// getRepIntervalSize - Returns the size of the interval that represents the
1012 /// specified register.
1014 unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) {
1015 return Rc->getRepIntervalSize(Reg);
1018 /// CopyRecSort::operator - Join priority queue sorting function.
1020 bool CopyRecSort::operator()(CopyRec left, CopyRec right) const {
1021 // Inner loops first.
1022 if (left.LoopDepth > right.LoopDepth)
1024 else if (left.LoopDepth == right.LoopDepth) {
1025 if (left.isBackEdge && !right.isBackEdge)
1027 else if (left.isBackEdge == right.isBackEdge) {
1028 // Join virtuals to physical registers first.
1029 bool LDstIsPhys = MRegisterInfo::isPhysicalRegister(left.DstReg);
1030 bool LSrcIsPhys = MRegisterInfo::isPhysicalRegister(left.SrcReg);
1031 bool LIsPhys = LDstIsPhys || LSrcIsPhys;
1032 bool RDstIsPhys = MRegisterInfo::isPhysicalRegister(right.DstReg);
1033 bool RSrcIsPhys = MRegisterInfo::isPhysicalRegister(right.SrcReg);
1034 bool RIsPhys = RDstIsPhys || RSrcIsPhys;
1035 if (LIsPhys && !RIsPhys)
1037 else if (LIsPhys == RIsPhys) {
1038 // Join shorter intervals first.
1042 LSize = LDstIsPhys ? 0 : JPQ->getRepIntervalSize(left.DstReg);
1043 LSize += LSrcIsPhys ? 0 : JPQ->getRepIntervalSize(left.SrcReg);
1044 RSize = RDstIsPhys ? 0 : JPQ->getRepIntervalSize(right.DstReg);
1045 RSize += RSrcIsPhys ? 0 : JPQ->getRepIntervalSize(right.SrcReg);
1047 LSize = std::min(JPQ->getRepIntervalSize(left.DstReg),
1048 JPQ->getRepIntervalSize(left.SrcReg));
1049 RSize = std::min(JPQ->getRepIntervalSize(right.DstReg),
1050 JPQ->getRepIntervalSize(right.SrcReg));
1060 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
1061 std::vector<CopyRec> &TryAgain) {
1062 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
1064 std::vector<CopyRec> VirtCopies;
1065 std::vector<CopyRec> PhysCopies;
1066 unsigned LoopDepth = loopInfo->getLoopDepth(MBB->getBasicBlock());
1067 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1069 MachineInstr *Inst = MII++;
1071 // If this isn't a copy nor a extract_subreg, we can't join intervals.
1072 unsigned SrcReg, DstReg;
1073 if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
1074 DstReg = Inst->getOperand(0).getReg();
1075 SrcReg = Inst->getOperand(1).getReg();
1076 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg))
1079 unsigned repSrcReg = rep(SrcReg);
1080 unsigned repDstReg = rep(DstReg);
1081 bool SrcIsPhys = MRegisterInfo::isPhysicalRegister(repSrcReg);
1082 bool DstIsPhys = MRegisterInfo::isPhysicalRegister(repDstReg);
1084 JoinQueue->push(CopyRec(Inst, SrcReg, DstReg, LoopDepth,
1085 isBackEdgeCopy(Inst, DstReg)));
1087 if (SrcIsPhys || DstIsPhys)
1088 PhysCopies.push_back(CopyRec(Inst, SrcReg, DstReg, 0, false));
1090 VirtCopies.push_back(CopyRec(Inst, SrcReg, DstReg, 0, false));
1097 // Try coalescing physical register + virtual register first.
1098 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
1099 CopyRec &TheCopy = PhysCopies[i];
1101 if (!JoinCopy(TheCopy, Again))
1103 TryAgain.push_back(TheCopy);
1105 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
1106 CopyRec &TheCopy = VirtCopies[i];
1108 if (!JoinCopy(TheCopy, Again))
1110 TryAgain.push_back(TheCopy);
1114 void SimpleRegisterCoalescing::joinIntervals() {
1115 DOUT << "********** JOINING INTERVALS ***********\n";
1118 JoinQueue = new JoinPriorityQueue<CopyRecSort>(this);
1120 JoinedLIs.resize(li_->getNumIntervals());
1123 std::vector<CopyRec> TryAgainList;
1124 if (loopInfo->begin() == loopInfo->end()) {
1125 // If there are no loops in the function, join intervals in function order.
1126 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1128 CopyCoalesceInMBB(I, TryAgainList);
1130 // Otherwise, join intervals in inner loops before other intervals.
1131 // Unfortunately we can't just iterate over loop hierarchy here because
1132 // there may be more MBB's than BB's. Collect MBB's for sorting.
1134 // Join intervals in the function prolog first. We want to join physical
1135 // registers with virtual registers before the intervals got too long.
1136 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1137 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); I != E;++I)
1138 MBBs.push_back(std::make_pair(loopInfo->
1139 getLoopDepth(I->getBasicBlock()), I));
1141 // Sort by loop depth.
1142 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1144 // Finally, join intervals in loop nest order.
1145 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1146 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
1149 // Joining intervals can allow other intervals to be joined. Iteratively join
1150 // until we make no progress.
1152 SmallVector<CopyRec, 16> TryAgain;
1153 bool ProgressMade = true;
1154 while (ProgressMade) {
1155 ProgressMade = false;
1156 while (!JoinQueue->empty()) {
1157 CopyRec R = JoinQueue->pop();
1159 bool Success = JoinCopy(R, Again);
1161 ProgressMade = true;
1163 TryAgain.push_back(R);
1167 while (!TryAgain.empty()) {
1168 JoinQueue->push(TryAgain.back());
1169 TryAgain.pop_back();
1174 bool ProgressMade = true;
1175 while (ProgressMade) {
1176 ProgressMade = false;
1178 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1179 CopyRec &TheCopy = TryAgainList[i];
1182 bool Success = JoinCopy(TheCopy, Again);
1183 if (Success || !Again) {
1184 TheCopy.MI = 0; // Mark this one as done.
1185 ProgressMade = true;
1192 // Some live range has been lengthened due to colaescing, eliminate the
1193 // unnecessary kills.
1194 int RegNum = JoinedLIs.find_first();
1195 while (RegNum != -1) {
1196 unsigned Reg = RegNum + MRegisterInfo::FirstVirtualRegister;
1197 unsigned repReg = rep(Reg);
1198 LiveInterval &LI = li_->getInterval(repReg);
1199 LiveVariables::VarInfo& svi = lv_->getVarInfo(Reg);
1200 for (unsigned i = 0, e = svi.Kills.size(); i != e; ++i) {
1201 MachineInstr *Kill = svi.Kills[i];
1202 // Suppose vr1 = op vr2, x
1203 // and vr1 and vr2 are coalesced. vr2 should still be marked kill
1204 // unless it is a two-address operand.
1205 if (li_->isRemoved(Kill) || hasRegisterDef(Kill, repReg))
1207 if (LI.liveAt(li_->getInstructionIndex(Kill) + InstrSlots::NUM))
1208 unsetRegisterKill(Kill, repReg);
1210 RegNum = JoinedLIs.find_next(RegNum);
1216 DOUT << "*** Register mapping ***\n";
1217 for (unsigned i = 0, e = r2rMap_.size(); i != e; ++i)
1219 DOUT << " reg " << i << " -> ";
1220 DEBUG(printRegName(r2rMap_[i]));
1225 /// Return true if the two specified registers belong to different register
1226 /// classes. The registers may be either phys or virt regs.
1227 bool SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
1228 unsigned RegB) const {
1230 // Get the register classes for the first reg.
1231 if (MRegisterInfo::isPhysicalRegister(RegA)) {
1232 assert(MRegisterInfo::isVirtualRegister(RegB) &&
1233 "Shouldn't consider two physregs!");
1234 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
1237 // Compare against the regclass for the second reg.
1238 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA);
1239 if (MRegisterInfo::isVirtualRegister(RegB))
1240 return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
1242 return !RegClass->contains(RegB);
1245 /// lastRegisterUse - Returns the last use of the specific register between
1246 /// cycles Start and End. It also returns the use operand by reference. It
1247 /// returns NULL if there are no uses.
1249 SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End, unsigned Reg,
1250 MachineOperand *&MOU) {
1251 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
1254 // Skip deleted instructions
1255 MachineInstr *MI = li_->getInstructionFromIndex(e);
1256 while ((e - InstrSlots::NUM) >= s && !MI) {
1257 e -= InstrSlots::NUM;
1258 MI = li_->getInstructionFromIndex(e);
1260 if (e < s || MI == NULL)
1263 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
1264 MachineOperand &MO = MI->getOperand(i);
1265 if (MO.isRegister() && MO.isUse() && MO.getReg() &&
1266 mri_->regsOverlap(rep(MO.getReg()), Reg)) {
1272 e -= InstrSlots::NUM;
1279 /// findDefOperand - Returns the MachineOperand that is a def of the specific
1280 /// register. It returns NULL if the def is not found.
1281 MachineOperand *SimpleRegisterCoalescing::findDefOperand(MachineInstr *MI, unsigned Reg) {
1282 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1283 MachineOperand &MO = MI->getOperand(i);
1284 if (MO.isRegister() && MO.isDef() &&
1285 mri_->regsOverlap(rep(MO.getReg()), Reg))
1291 /// unsetRegisterKill - Unset IsKill property of all uses of specific register
1292 /// of the specific instruction.
1293 void SimpleRegisterCoalescing::unsetRegisterKill(MachineInstr *MI, unsigned Reg) {
1294 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1295 MachineOperand &MO = MI->getOperand(i);
1296 if (MO.isRegister() && MO.isKill() && MO.getReg() &&
1297 mri_->regsOverlap(rep(MO.getReg()), Reg))
1302 /// unsetRegisterKills - Unset IsKill property of all uses of specific register
1303 /// between cycles Start and End.
1304 void SimpleRegisterCoalescing::unsetRegisterKills(unsigned Start, unsigned End,
1306 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
1309 // Skip deleted instructions
1310 MachineInstr *MI = li_->getInstructionFromIndex(e);
1311 while ((e - InstrSlots::NUM) >= s && !MI) {
1312 e -= InstrSlots::NUM;
1313 MI = li_->getInstructionFromIndex(e);
1315 if (e < s || MI == NULL)
1318 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
1319 MachineOperand &MO = MI->getOperand(i);
1320 if (MO.isRegister() && MO.isKill() && MO.getReg() &&
1321 mri_->regsOverlap(rep(MO.getReg()), Reg)) {
1326 e -= InstrSlots::NUM;
1330 /// hasRegisterDef - True if the instruction defines the specific register.
1332 bool SimpleRegisterCoalescing::hasRegisterDef(MachineInstr *MI, unsigned Reg) {
1333 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1334 MachineOperand &MO = MI->getOperand(i);
1335 if (MO.isRegister() && MO.isDef() &&
1336 mri_->regsOverlap(rep(MO.getReg()), Reg))
1342 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
1343 if (MRegisterInfo::isPhysicalRegister(reg))
1344 cerr << mri_->getName(reg);
1346 cerr << "%reg" << reg;
1349 void SimpleRegisterCoalescing::releaseMemory() {
1350 for (unsigned i = 0, e = r2rMap_.size(); i != e; ++i)
1351 r2rRevMap_[i].clear();
1355 SubRegIdxes.clear();
1356 JoinedCopies.clear();
1359 static bool isZeroLengthInterval(LiveInterval *li) {
1360 for (LiveInterval::Ranges::const_iterator
1361 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
1362 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
1367 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
1369 tm_ = &fn.getTarget();
1370 mri_ = tm_->getRegisterInfo();
1371 tii_ = tm_->getInstrInfo();
1372 li_ = &getAnalysis<LiveIntervals>();
1373 lv_ = &getAnalysis<LiveVariables>();
1374 loopInfo = &getAnalysis<LoopInfo>();
1376 DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
1377 << "********** Function: "
1378 << ((Value*)mf_->getFunction())->getName() << '\n';
1380 allocatableRegs_ = mri_->getAllocatableSet(fn);
1381 for (MRegisterInfo::regclass_iterator I = mri_->regclass_begin(),
1382 E = mri_->regclass_end(); I != E; ++I)
1383 allocatableRCRegs_.insert(std::make_pair(*I,mri_->getAllocatableSet(fn, *I)));
1385 SSARegMap *RegMap = mf_->getSSARegMap();
1386 r2rMap_.grow(RegMap->getLastVirtReg());
1387 r2rRevMap_.grow(RegMap->getLastVirtReg());
1389 // Join (coalesce) intervals if requested.
1390 IndexedMap<unsigned, VirtReg2IndexFunctor> RegSubIdxMap;
1391 if (EnableJoining) {
1393 DOUT << "********** INTERVALS POST JOINING **********\n";
1394 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
1395 I->second.print(DOUT, mri_);
1399 // Delete all coalesced copies.
1400 for (SmallPtrSet<MachineInstr*,32>::iterator I = JoinedCopies.begin(),
1401 E = JoinedCopies.end(); I != E; ++I) {
1402 li_->RemoveMachineInstrFromMaps(*I);
1403 (*I)->eraseFromParent();
1406 // Transfer sub-registers info to SSARegMap now that coalescing information
1408 RegSubIdxMap.grow(mf_->getSSARegMap()->getLastVirtReg()+1);
1409 while (!SubRegIdxes.empty()) {
1410 std::pair<unsigned, unsigned> RI = SubRegIdxes.back();
1411 SubRegIdxes.pop_back();
1412 RegSubIdxMap[RI.first] = RI.second;
1416 // perform a final pass over the instructions and compute spill
1417 // weights, coalesce virtual registers and remove identity moves.
1418 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
1419 mbbi != mbbe; ++mbbi) {
1420 MachineBasicBlock* mbb = mbbi;
1421 unsigned loopDepth = loopInfo->getLoopDepth(mbb->getBasicBlock());
1423 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
1425 // if the move will be an identity move delete it
1426 unsigned srcReg, dstReg, RegRep;
1427 if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
1428 (RegRep = rep(srcReg)) == rep(dstReg)) {
1429 // remove from def list
1430 LiveInterval &RegInt = li_->getOrCreateInterval(RegRep);
1431 MachineOperand *MO = mii->findRegisterDefOperand(dstReg);
1432 // If def of this move instruction is dead, remove its live range from
1433 // the dstination register's live interval.
1435 unsigned MoveIdx = li_->getDefIndex(li_->getInstructionIndex(mii));
1436 LiveInterval::iterator MLR = RegInt.FindLiveRangeContaining(MoveIdx);
1437 RegInt.removeRange(MLR->start, MoveIdx+1);
1439 li_->removeInterval(RegRep);
1441 li_->RemoveMachineInstrFromMaps(mii);
1442 mii = mbbi->erase(mii);
1445 SmallSet<unsigned, 4> UniqueUses;
1446 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
1447 const MachineOperand &mop = mii->getOperand(i);
1448 if (mop.isRegister() && mop.getReg() &&
1449 MRegisterInfo::isVirtualRegister(mop.getReg())) {
1450 // replace register with representative register
1451 unsigned OrigReg = mop.getReg();
1452 unsigned reg = rep(OrigReg);
1453 unsigned SubIdx = RegSubIdxMap[OrigReg];
1454 if (SubIdx && MRegisterInfo::isPhysicalRegister(reg))
1455 mii->getOperand(i).setReg(mri_->getSubReg(reg, SubIdx));
1457 mii->getOperand(i).setReg(reg);
1458 mii->getOperand(i).setSubReg(SubIdx);
1461 // Multiple uses of reg by the same instruction. It should not
1462 // contribute to spill weight again.
1463 if (UniqueUses.count(reg) != 0)
1465 LiveInterval &RegInt = li_->getInterval(reg);
1466 RegInt.weight += li_->getSpillWeight(mop, loopDepth);
1467 UniqueUses.insert(reg);
1475 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
1476 LiveInterval &LI = I->second;
1477 if (MRegisterInfo::isVirtualRegister(LI.reg)) {
1478 // If the live interval length is essentially zero, i.e. in every live
1479 // range the use follows def immediately, it doesn't make sense to spill
1480 // it and hope it will be easier to allocate for this li.
1481 if (isZeroLengthInterval(&LI))
1482 LI.weight = HUGE_VALF;
1484 // Slightly prefer live interval that has been assigned a preferred reg.
1488 // Divide the weight of the interval by its size. This encourages
1489 // spilling of intervals that are large and have few uses, and
1490 // discourages spilling of small intervals with many uses.
1491 LI.weight /= LI.getSize();
1499 /// print - Implement the dump method.
1500 void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const {
1504 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
1505 return new SimpleRegisterCoalescing();
1508 // Make sure that anything that uses RegisterCoalescer pulls in this file...
1509 DEFINING_FILE_FOR(SimpleRegisterCoalescing)