1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegisterCoalescer.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/OwningPtr.h"
35 #include "llvm/ADT/SmallSet.h"
36 #include "llvm/ADT/Statistic.h"
37 #include "llvm/ADT/STLExtras.h"
42 STATISTIC(numJoins , "Number of interval joins performed");
43 STATISTIC(numCrossRCs , "Number of cross class joins performed");
44 STATISTIC(numCommutes , "Number of instruction commuting performed");
45 STATISTIC(numExtends , "Number of copies extended");
46 STATISTIC(NumReMats , "Number of instructions re-materialized");
47 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
48 STATISTIC(numAborts , "Number of times interval joining aborted");
49 STATISTIC(numDeadValNo, "Number of valno def marked dead");
51 char SimpleRegisterCoalescing::ID = 0;
53 EnableJoining("join-liveintervals",
54 cl::desc("Coalesce copies (default=true)"),
58 DisableCrossClassJoin("disable-cross-class-join",
59 cl::desc("Avoid coalescing cross register class copies"),
60 cl::init(false), cl::Hidden);
62 static RegisterPass<SimpleRegisterCoalescing>
63 X("simple-register-coalescing", "Simple Register Coalescing");
65 // Declare that we implement the RegisterCoalescer interface
66 static RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
68 const PassInfo *const llvm::SimpleRegisterCoalescingID = &X;
70 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
72 AU.addRequired<AliasAnalysis>();
73 AU.addRequired<LiveIntervals>();
74 AU.addPreserved<LiveIntervals>();
75 AU.addPreserved<SlotIndexes>();
76 AU.addRequired<MachineLoopInfo>();
77 AU.addPreserved<MachineLoopInfo>();
78 AU.addPreservedID(MachineDominatorsID);
80 AU.addPreservedID(StrongPHIEliminationID);
82 AU.addPreservedID(PHIEliminationID);
83 AU.addPreservedID(TwoAddressInstructionPassID);
84 MachineFunctionPass::getAnalysisUsage(AU);
87 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
88 /// being the source and IntB being the dest, thus this defines a value number
89 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
90 /// see if we can merge these two pieces of B into a single value number,
91 /// eliminating a copy. For example:
95 /// B1 = A3 <- this copy
97 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
98 /// value number to be replaced with B0 (which simplifies the B liveinterval).
100 /// This returns true if an interval was modified.
102 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
104 MachineInstr *CopyMI) {
105 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getDefIndex();
107 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
108 // the example above.
109 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
110 assert(BLR != IntB.end() && "Live range not found!");
111 VNInfo *BValNo = BLR->valno;
113 // Get the location that B is defined at. Two options: either this value has
114 // an unknown definition point or it is defined at CopyIdx. If unknown, we
116 if (!BValNo->getCopy()) return false;
117 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
119 // AValNo is the value number in A that defines the copy, A3 in the example.
120 SlotIndex CopyUseIdx = CopyIdx.getUseIndex();
121 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
122 assert(ALR != IntA.end() && "Live range not found!");
123 VNInfo *AValNo = ALR->valno;
124 // If it's re-defined by an early clobber somewhere in the live range, then
125 // it's not safe to eliminate the copy. FIXME: This is a temporary workaround.
127 // 172 %ECX<def> = MOV32rr %reg1039<kill>
128 // 180 INLINEASM <es:subl $5,$1
129 // sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9,
131 // 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0
132 // 188 %EAX<def> = MOV32rr %EAX<kill>
133 // 196 %ECX<def> = MOV32rr %ECX<kill>
134 // 204 %ECX<def> = MOV32rr %ECX<kill>
135 // 212 %EAX<def> = MOV32rr %EAX<kill>
136 // 220 %EAX<def> = MOV32rr %EAX
137 // 228 %reg1039<def> = MOV32rr %ECX<kill>
138 // The early clobber operand ties ECX input to the ECX def.
140 // The live interval of ECX is represented as this:
141 // %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47)
142 // The coalescer has no idea there was a def in the middle of [174,230].
143 if (AValNo->hasRedefByEC())
146 // If AValNo is defined as a copy from IntB, we can potentially process this.
147 // Get the instruction that defines this value number.
148 unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
149 if (!SrcReg) return false; // Not defined by a copy.
151 // If the value number is not defined by a copy instruction, ignore it.
153 // If the source register comes from an interval other than IntB, we can't
155 if (SrcReg != IntB.reg) return false;
157 // Get the LiveRange in IntB that this value number starts with.
158 LiveInterval::iterator ValLR =
159 IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot());
160 assert(ValLR != IntB.end() && "Live range not found!");
162 // Make sure that the end of the live range is inside the same block as
164 MachineInstr *ValLREndInst =
165 li_->getInstructionFromIndex(ValLR->end.getPrevSlot());
167 ValLREndInst->getParent() != CopyMI->getParent()) return false;
169 // Okay, we now know that ValLR ends in the same block that the CopyMI
170 // live-range starts. If there are no intervening live ranges between them in
171 // IntB, we can merge them.
172 if (ValLR+1 != BLR) return false;
174 // If a live interval is a physical register, conservatively check if any
175 // of its sub-registers is overlapping the live interval of the virtual
176 // register. If so, do not coalesce.
177 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
178 *tri_->getSubRegisters(IntB.reg)) {
179 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
180 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
182 dbgs() << "\t\tInterfere with sub-register ";
183 li_->getInterval(*SR).print(dbgs(), tri_);
190 dbgs() << "Extending: ";
191 IntB.print(dbgs(), tri_);
194 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
195 // We are about to delete CopyMI, so need to remove it as the 'instruction
196 // that defines this value #'. Update the valnum with the new defining
198 BValNo->def = FillerStart;
201 // Okay, we can merge them. We need to insert a new liverange:
202 // [ValLR.end, BLR.begin) of either value number, then we merge the
203 // two value numbers.
204 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
206 // If the IntB live range is assigned to a physical register, and if that
207 // physreg has sub-registers, update their live intervals as well.
208 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
209 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
210 LiveInterval &SRLI = li_->getInterval(*SR);
211 SRLI.addRange(LiveRange(FillerStart, FillerEnd,
212 SRLI.getNextValue(FillerStart, 0, true,
213 li_->getVNInfoAllocator())));
217 // Okay, merge "B1" into the same value number as "B0".
218 if (BValNo != ValLR->valno) {
219 IntB.addKills(ValLR->valno, BValNo->kills);
220 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
223 dbgs() << " result = ";
224 IntB.print(dbgs(), tri_);
228 // If the source instruction was killing the source register before the
229 // merge, unset the isKill marker given the live range has been extended.
230 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
232 ValLREndInst->getOperand(UIdx).setIsKill(false);
233 ValLR->valno->removeKill(FillerStart);
236 // If the copy instruction was killing the destination register before the
237 // merge, find the last use and trim the live range. That will also add the
239 if (ALR->valno->isKill(CopyIdx))
240 TrimLiveIntervalToLastUse(CopyUseIdx, CopyMI->getParent(), IntA, ALR);
246 /// HasOtherReachingDefs - Return true if there are definitions of IntB
247 /// other than BValNo val# that can reach uses of AValno val# of IntA.
248 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
252 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
254 if (AI->valno != AValNo) continue;
255 LiveInterval::Ranges::iterator BI =
256 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
257 if (BI != IntB.ranges.begin())
259 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
260 if (BI->valno == BValNo)
262 // When BValNo is null, we're looking for a dummy clobber-value for a subreg.
263 if (!BValNo && !BI->valno->isDefAccurate() && !BI->valno->getCopy())
265 if (BI->start <= AI->start && BI->end > AI->start)
267 if (BI->start > AI->start && BI->start < AI->end)
275 TransferImplicitOps(MachineInstr *MI, MachineInstr *NewMI) {
276 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
278 MachineOperand &MO = MI->getOperand(i);
279 if (MO.isReg() && MO.isImplicit())
280 NewMI->addOperand(MO);
284 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with
285 /// IntA being the source and IntB being the dest, thus this defines a value
286 /// number in IntB. If the source value number (in IntA) is defined by a
287 /// commutable instruction and its other operand is coalesced to the copy dest
288 /// register, see if we can transform the copy into a noop by commuting the
289 /// definition. For example,
291 /// A3 = op A2 B0<kill>
293 /// B1 = A3 <- this copy
295 /// = op A3 <- more uses
299 /// B2 = op B0 A2<kill>
301 /// B1 = B2 <- now an identify copy
303 /// = op B2 <- more uses
305 /// This returns true if an interval was modified.
307 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
309 MachineInstr *CopyMI) {
311 li_->getInstructionIndex(CopyMI).getDefIndex();
313 // FIXME: For now, only eliminate the copy by commuting its def when the
314 // source register is a virtual register. We want to guard against cases
315 // where the copy is a back edge copy and commuting the def lengthen the
316 // live interval of the source register to the entire loop.
317 if (TargetRegisterInfo::isPhysicalRegister(IntA.reg))
320 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
321 // the example above.
322 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
323 assert(BLR != IntB.end() && "Live range not found!");
324 VNInfo *BValNo = BLR->valno;
326 // Get the location that B is defined at. Two options: either this value has
327 // an unknown definition point or it is defined at CopyIdx. If unknown, we
329 if (!BValNo->getCopy()) return false;
330 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
332 // AValNo is the value number in A that defines the copy, A3 in the example.
333 LiveInterval::iterator ALR =
334 IntA.FindLiveRangeContaining(CopyIdx.getUseIndex()); //
336 assert(ALR != IntA.end() && "Live range not found!");
337 VNInfo *AValNo = ALR->valno;
338 // If other defs can reach uses of this def, then it's not safe to perform
339 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
341 if (AValNo->isPHIDef() || !AValNo->isDefAccurate() ||
342 AValNo->isUnused() || AValNo->hasPHIKill())
344 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
345 const TargetInstrDesc &TID = DefMI->getDesc();
346 if (!TID.isCommutable())
348 // If DefMI is a two-address instruction then commuting it will change the
349 // destination register.
350 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
351 assert(DefIdx != -1);
353 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
355 unsigned Op1, Op2, NewDstIdx;
356 if (!tii_->findCommutedOpIndices(DefMI, Op1, Op2))
360 else if (Op2 == UseOpIdx)
365 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
366 unsigned NewReg = NewDstMO.getReg();
367 if (NewReg != IntB.reg || !NewDstMO.isKill())
370 // Make sure there are no other definitions of IntB that would reach the
371 // uses which the new definition can reach.
372 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
375 bool BHasSubRegs = false;
376 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
377 BHasSubRegs = *tri_->getSubRegisters(IntB.reg);
379 // Abort if the subregisters of IntB.reg have values that are not simply the
380 // clobbers from the superreg.
382 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
383 if (HasOtherReachingDefs(IntA, li_->getInterval(*SR), AValNo, 0))
386 // If some of the uses of IntA.reg is already coalesced away, return false.
387 // It's not possible to determine whether it's safe to perform the coalescing.
388 for (MachineRegisterInfo::use_nodbg_iterator UI =
389 mri_->use_nodbg_begin(IntA.reg),
390 UE = mri_->use_nodbg_end(); UI != UE; ++UI) {
391 MachineInstr *UseMI = &*UI;
392 SlotIndex UseIdx = li_->getInstructionIndex(UseMI);
393 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
394 if (ULR == IntA.end())
396 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
400 // At this point we have decided that it is legal to do this
401 // transformation. Start by commuting the instruction.
402 MachineBasicBlock *MBB = DefMI->getParent();
403 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
406 if (NewMI != DefMI) {
407 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
408 MBB->insert(DefMI, NewMI);
411 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
412 NewMI->getOperand(OpIdx).setIsKill();
414 bool BHasPHIKill = BValNo->hasPHIKill();
415 SmallVector<VNInfo*, 4> BDeadValNos;
416 VNInfo::KillSet BKills;
417 std::map<SlotIndex, SlotIndex> BExtend;
419 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
428 // then do not add kills of A to the newly created B interval.
429 bool Extended = BLR->end > ALR->end && ALR->end != ALR->start;
431 BExtend[ALR->end] = BLR->end;
433 // Update uses of IntA of the specific Val# with IntB.
434 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
435 UE = mri_->use_end(); UI != UE;) {
436 MachineOperand &UseMO = UI.getOperand();
437 MachineInstr *UseMI = &*UI;
439 if (JoinedCopies.count(UseMI))
441 if (UseMI->isDebugValue()) {
442 // FIXME These don't have an instruction index. Not clear we have enough
443 // info to decide whether to do this replacement or not. For now do it.
444 UseMO.setReg(NewReg);
447 SlotIndex UseIdx = li_->getInstructionIndex(UseMI).getUseIndex();
448 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
449 if (ULR == IntA.end() || ULR->valno != AValNo)
451 UseMO.setReg(NewReg);
454 if (UseMO.isKill()) {
456 UseMO.setIsKill(false);
458 BKills.push_back(UseIdx.getDefIndex());
460 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
461 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
463 if (DstReg == IntB.reg && DstSubIdx == 0) {
464 // This copy will become a noop. If it's defining a new val#,
465 // remove that val# as well. However this live range is being
466 // extended to the end of the existing live range defined by the copy.
467 SlotIndex DefIdx = UseIdx.getDefIndex();
468 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
469 BHasPHIKill |= DLR->valno->hasPHIKill();
470 assert(DLR->valno->def == DefIdx);
471 BDeadValNos.push_back(DLR->valno);
472 BExtend[DLR->start] = DLR->end;
473 JoinedCopies.insert(UseMI);
474 // If this is a kill but it's going to be removed, the last use
475 // of the same val# is the new kill.
481 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
482 // simply extend BLR if CopyMI doesn't end the range.
484 dbgs() << "Extending: ";
485 IntB.print(dbgs(), tri_);
488 // Remove val#'s defined by copies that will be coalesced away.
489 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) {
490 VNInfo *DeadVNI = BDeadValNos[i];
492 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
493 LiveInterval &SRLI = li_->getInterval(*SR);
494 const LiveRange *SRLR = SRLI.getLiveRangeContaining(DeadVNI->def);
495 SRLI.removeValNo(SRLR->valno);
498 IntB.removeValNo(BDeadValNos[i]);
501 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
502 // is updated. Kills are also updated.
503 VNInfo *ValNo = BValNo;
504 ValNo->def = AValNo->def;
506 for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) {
507 if (ValNo->kills[j] != BLR->end)
508 BKills.push_back(ValNo->kills[j]);
510 ValNo->kills.clear();
511 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
513 if (AI->valno != AValNo) continue;
514 SlotIndex End = AI->end;
515 std::map<SlotIndex, SlotIndex>::iterator
516 EI = BExtend.find(End);
517 if (EI != BExtend.end())
519 IntB.addRange(LiveRange(AI->start, End, ValNo));
521 // If the IntB live range is assigned to a physical register, and if that
522 // physreg has sub-registers, update their live intervals as well.
524 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
525 LiveInterval &SRLI = li_->getInterval(*SR);
526 SRLI.MergeInClobberRange(*li_, AI->start, End,
527 li_->getVNInfoAllocator());
531 IntB.addKills(ValNo, BKills);
532 ValNo->setHasPHIKill(BHasPHIKill);
535 dbgs() << " result = ";
536 IntB.print(dbgs(), tri_);
537 dbgs() << "\nShortening: ";
538 IntA.print(dbgs(), tri_);
541 IntA.removeValNo(AValNo);
544 dbgs() << " result = ";
545 IntA.print(dbgs(), tri_);
553 /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply
554 /// fallthoughs to SuccMBB.
555 static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
556 MachineBasicBlock *SuccMBB,
557 const TargetInstrInfo *tii_) {
560 MachineBasicBlock *TBB = 0, *FBB = 0;
561 SmallVector<MachineOperand, 4> Cond;
562 return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
563 MBB->isSuccessor(SuccMBB);
566 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
567 /// from a physical register live interval as well as from the live intervals
568 /// of its sub-registers.
569 static void removeRange(LiveInterval &li,
570 SlotIndex Start, SlotIndex End,
571 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
572 li.removeRange(Start, End, true);
573 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
574 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
575 if (!li_->hasInterval(*SR))
577 LiveInterval &sli = li_->getInterval(*SR);
578 SlotIndex RemoveStart = Start;
579 SlotIndex RemoveEnd = Start;
581 while (RemoveEnd != End) {
582 LiveInterval::iterator LR = sli.FindLiveRangeContaining(RemoveStart);
585 RemoveEnd = (LR->end < End) ? LR->end : End;
586 sli.removeRange(RemoveStart, RemoveEnd, true);
587 RemoveStart = RemoveEnd;
593 /// TrimLiveIntervalToLastUse - If there is a last use in the same basic block
594 /// as the copy instruction, trim the live interval to the last use and return
597 SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(SlotIndex CopyIdx,
598 MachineBasicBlock *CopyMBB,
600 const LiveRange *LR) {
601 SlotIndex MBBStart = li_->getMBBStartIdx(CopyMBB);
602 SlotIndex LastUseIdx;
603 MachineOperand *LastUse =
604 lastRegisterUse(LR->start, CopyIdx.getPrevSlot(), li.reg, LastUseIdx);
606 MachineInstr *LastUseMI = LastUse->getParent();
607 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
614 // r1025<dead> = r1024<kill>
615 if (MBBStart < LR->end)
616 removeRange(li, MBBStart, LR->end, li_, tri_);
620 // There are uses before the copy, just shorten the live range to the end
622 LastUse->setIsKill();
623 removeRange(li, LastUseIdx.getDefIndex(), LR->end, li_, tri_);
624 LR->valno->addKill(LastUseIdx.getDefIndex());
625 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
626 if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
627 DstReg == li.reg && DstSubIdx == 0) {
628 // Last use is itself an identity code.
629 int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg,
631 LastUseMI->getOperand(DeadIdx).setIsDead();
637 if (LR->start <= MBBStart && LR->end > MBBStart) {
638 if (LR->start == li_->getZeroIndex()) {
639 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
640 // Live-in to the function but dead. Remove it from entry live-in set.
641 mf_->begin()->removeLiveIn(li.reg);
643 // FIXME: Shorten intervals in BBs that reaches this BB.
649 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
650 /// computation, replace the copy by rematerialize the definition.
651 bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
654 MachineInstr *CopyMI) {
655 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getUseIndex();
656 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
657 assert(SrcLR != SrcInt.end() && "Live range not found!");
658 VNInfo *ValNo = SrcLR->valno;
659 // If other defs can reach uses of this def, then it's not safe to perform
660 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
662 if (ValNo->isPHIDef() || !ValNo->isDefAccurate() ||
663 ValNo->isUnused() || ValNo->hasPHIKill())
665 MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
666 const TargetInstrDesc &TID = DefMI->getDesc();
667 if (!TID.isAsCheapAsAMove())
669 if (!tii_->isTriviallyReMaterializable(DefMI, AA))
671 bool SawStore = false;
672 if (!DefMI->isSafeToMove(tii_, AA, SawStore))
674 if (TID.getNumDefs() != 1)
676 if (!DefMI->isImplicitDef()) {
677 // Make sure the copy destination register class fits the instruction
678 // definition register class. The mismatch can happen as a result of earlier
679 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
680 const TargetRegisterClass *RC = TID.OpInfo[0].getRegClass(tri_);
681 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
682 if (mri_->getRegClass(DstReg) != RC)
684 } else if (!RC->contains(DstReg))
688 // If destination register has a sub-register index on it, make sure it mtches
689 // the instruction register class.
691 const TargetInstrDesc &TID = DefMI->getDesc();
692 if (TID.getNumDefs() != 1)
694 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
695 const TargetRegisterClass *DstSubRC =
696 DstRC->getSubRegisterRegClass(DstSubIdx);
697 const TargetRegisterClass *DefRC = TID.OpInfo[0].getRegClass(tri_);
700 else if (DefRC != DstSubRC)
704 SlotIndex DefIdx = CopyIdx.getDefIndex();
705 const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
706 DLR->valno->setCopy(0);
707 // Don't forget to update sub-register intervals.
708 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
709 for (const unsigned* SR = tri_->getSubRegisters(DstReg); *SR; ++SR) {
710 if (!li_->hasInterval(*SR))
712 const LiveRange *DLR =
713 li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
714 if (DLR && DLR->valno->getCopy() == CopyMI)
715 DLR->valno->setCopy(0);
719 // If copy kills the source register, find the last use and propagate
721 bool checkForDeadDef = false;
722 MachineBasicBlock *MBB = CopyMI->getParent();
723 if (SrcLR->valno->isKill(DefIdx))
724 if (!TrimLiveIntervalToLastUse(CopyIdx, MBB, SrcInt, SrcLR)) {
725 checkForDeadDef = true;
728 MachineBasicBlock::iterator MII =
729 llvm::next(MachineBasicBlock::iterator(CopyMI));
730 tii_->reMaterialize(*MBB, MII, DstReg, DstSubIdx, DefMI, tri_);
731 MachineInstr *NewMI = prior(MII);
733 if (checkForDeadDef) {
734 // PR4090 fix: Trim interval failed because there was no use of the
735 // source interval in this MBB. If the def is in this MBB too then we
736 // should mark it dead:
737 if (DefMI->getParent() == MBB) {
738 DefMI->addRegisterDead(SrcInt.reg, tri_);
739 SrcLR->end = SrcLR->start.getNextSlot();
743 // CopyMI may have implicit operands, transfer them over to the newly
744 // rematerialized instruction. And update implicit def interval valnos.
745 for (unsigned i = CopyMI->getDesc().getNumOperands(),
746 e = CopyMI->getNumOperands(); i != e; ++i) {
747 MachineOperand &MO = CopyMI->getOperand(i);
748 if (MO.isReg() && MO.isImplicit())
749 NewMI->addOperand(MO);
750 if (MO.isDef() && li_->hasInterval(MO.getReg())) {
751 unsigned Reg = MO.getReg();
752 const LiveRange *DLR =
753 li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
754 if (DLR && DLR->valno->getCopy() == CopyMI)
755 DLR->valno->setCopy(0);
756 // Handle subregs as well
757 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
758 for (const unsigned* SR = tri_->getSubRegisters(Reg); *SR; ++SR) {
759 if (!li_->hasInterval(*SR))
761 const LiveRange *DLR =
762 li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
763 if (DLR && DLR->valno->getCopy() == CopyMI)
764 DLR->valno->setCopy(0);
770 TransferImplicitOps(CopyMI, NewMI);
771 li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
772 CopyMI->eraseFromParent();
773 ReMatCopies.insert(CopyMI);
774 ReMatDefs.insert(DefMI);
775 DEBUG(dbgs() << "Remat: " << *NewMI);
780 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
781 /// update the subregister number if it is not zero. If DstReg is a
782 /// physical register and the existing subregister number of the def / use
783 /// being updated is not zero, make sure to set it to the correct physical
786 SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
788 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
789 if (DstIsPhys && SubIdx) {
790 // Figure out the real physical register we are updating with.
791 DstReg = tri_->getSubReg(DstReg, SubIdx);
795 // Copy the register use-list before traversing it. We may be adding operands
796 // and invalidating pointers.
797 SmallVector<std::pair<MachineInstr*, unsigned>, 32> reglist;
798 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
799 E = mri_->reg_end(); I != E; ++I)
800 reglist.push_back(std::make_pair(&*I, I.getOperandNo()));
802 for (unsigned N=0; N != reglist.size(); ++N) {
803 MachineInstr *UseMI = reglist[N].first;
804 MachineOperand &O = UseMI->getOperand(reglist[N].second);
805 unsigned OldSubIdx = O.getSubReg();
807 unsigned UseDstReg = DstReg;
809 UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
811 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
812 if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
813 CopySrcSubIdx, CopyDstSubIdx) &&
814 CopySrcSubIdx == 0 &&
815 CopyDstSubIdx == 0 &&
816 CopySrcReg != CopyDstReg &&
817 CopySrcReg == SrcReg && CopyDstReg != UseDstReg) {
818 // If the use is a copy and it won't be coalesced away, and its source
819 // is defined by a trivial computation, try to rematerialize it instead.
820 if (!JoinedCopies.count(UseMI) &&
821 ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg,
822 CopyDstSubIdx, UseMI))
829 // Def and kill of subregister of a virtual register actually defs and
830 // kills the whole register. Add imp-defs and imp-kills as needed.
833 UseMI->addRegisterDead(DstReg, tri_, true);
835 UseMI->addRegisterDefined(DstReg, tri_);
836 } else if (!O.isUndef() &&
838 UseMI->isRegTiedToDefOperand(&O-&UseMI->getOperand(0))))
839 UseMI->addRegisterKilled(DstReg, tri_, true);
843 dbgs() << "\t\tupdated: ";
844 if (!UseMI->isDebugValue())
845 dbgs() << li_->getInstructionIndex(UseMI) << "\t";
851 // Sub-register indexes goes from small to large. e.g.
852 // RAX: 1 -> AL, 2 -> AX, 3 -> EAX
853 // EAX: 1 -> AL, 2 -> AX
854 // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose
855 // sub-register 2 is also AX.
856 if (SubIdx && OldSubIdx && SubIdx != OldSubIdx)
857 assert(OldSubIdx < SubIdx && "Conflicting sub-register index!");
863 dbgs() << "\t\tupdated: ";
864 if (!UseMI->isDebugValue())
865 dbgs() << li_->getInstructionIndex(UseMI) << "\t";
869 // After updating the operand, check if the machine instruction has
870 // become a copy. If so, update its val# information.
871 if (JoinedCopies.count(UseMI))
874 const TargetInstrDesc &TID = UseMI->getDesc();
875 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
876 if (TID.getNumDefs() == 1 && TID.getNumOperands() > 2 &&
877 tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
878 CopySrcSubIdx, CopyDstSubIdx) &&
879 CopySrcReg != CopyDstReg &&
880 (TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
881 allocatableRegs_[CopyDstReg])) {
882 LiveInterval &LI = li_->getInterval(CopyDstReg);
884 li_->getInstructionIndex(UseMI).getDefIndex();
885 if (const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx)) {
886 if (DLR->valno->def == DefIdx)
887 DLR->valno->setCopy(UseMI);
893 /// removeIntervalIfEmpty - Check if the live interval of a physical register
894 /// is empty, if so remove it and also remove the empty intervals of its
895 /// sub-registers. Return true if live interval is removed.
896 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
897 const TargetRegisterInfo *tri_) {
899 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
900 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
901 if (!li_->hasInterval(*SR))
903 LiveInterval &sli = li_->getInterval(*SR);
905 li_->removeInterval(*SR);
907 li_->removeInterval(li.reg);
913 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
914 /// Return true if live interval is removed.
915 bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
916 MachineInstr *CopyMI) {
917 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI);
918 LiveInterval::iterator MLR =
919 li.FindLiveRangeContaining(CopyIdx.getDefIndex());
921 return false; // Already removed by ShortenDeadCopySrcLiveRange.
922 SlotIndex RemoveStart = MLR->start;
923 SlotIndex RemoveEnd = MLR->end;
924 SlotIndex DefIdx = CopyIdx.getDefIndex();
925 // Remove the liverange that's defined by this.
926 if (RemoveStart == DefIdx && RemoveEnd == DefIdx.getStoreIndex()) {
927 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
928 return removeIntervalIfEmpty(li, li_, tri_);
933 /// RemoveDeadDef - If a def of a live interval is now determined dead, remove
934 /// the val# it defines. If the live interval becomes empty, remove it as well.
935 bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li,
936 MachineInstr *DefMI) {
937 SlotIndex DefIdx = li_->getInstructionIndex(DefMI).getDefIndex();
938 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
939 if (DefIdx != MLR->valno->def)
941 li.removeValNo(MLR->valno);
942 return removeIntervalIfEmpty(li, li_, tri_);
945 /// PropagateDeadness - Propagate the dead marker to the instruction which
946 /// defines the val#.
947 static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
948 SlotIndex &LRStart, LiveIntervals *li_,
949 const TargetRegisterInfo* tri_) {
950 MachineInstr *DefMI =
951 li_->getInstructionFromIndex(LRStart.getDefIndex());
952 if (DefMI && DefMI != CopyMI) {
953 int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg);
955 DefMI->getOperand(DeadIdx).setIsDead();
957 DefMI->addOperand(MachineOperand::CreateReg(li.reg,
958 /*def*/true, /*implicit*/true, /*kill*/false, /*dead*/true));
959 LRStart = LRStart.getNextSlot();
963 /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially
964 /// extended by a dead copy. Mark the last use (if any) of the val# as kill as
965 /// ends the live range there. If there isn't another use, then this live range
966 /// is dead. Return true if live interval is removed.
968 SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
969 MachineInstr *CopyMI) {
970 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI);
971 if (CopyIdx == SlotIndex()) {
972 // FIXME: special case: function live in. It can be a general case if the
973 // first instruction index starts at > 0 value.
974 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
975 // Live-in to the function but dead. Remove it from entry live-in set.
976 if (mf_->begin()->isLiveIn(li.reg))
977 mf_->begin()->removeLiveIn(li.reg);
978 const LiveRange *LR = li.getLiveRangeContaining(CopyIdx);
979 removeRange(li, LR->start, LR->end, li_, tri_);
980 return removeIntervalIfEmpty(li, li_, tri_);
983 LiveInterval::iterator LR =
984 li.FindLiveRangeContaining(CopyIdx.getPrevIndex().getStoreIndex());
986 // Livein but defined by a phi.
989 SlotIndex RemoveStart = LR->start;
990 SlotIndex RemoveEnd = CopyIdx.getStoreIndex();
991 if (LR->end > RemoveEnd)
992 // More uses past this copy? Nothing to do.
995 // If there is a last use in the same bb, we can't remove the live range.
996 // Shorten the live interval and return.
997 MachineBasicBlock *CopyMBB = CopyMI->getParent();
998 if (TrimLiveIntervalToLastUse(CopyIdx, CopyMBB, li, LR))
1001 // There are other kills of the val#. Nothing to do.
1002 if (!li.isOnlyLROfValNo(LR))
1005 MachineBasicBlock *StartMBB = li_->getMBBFromIndex(RemoveStart);
1006 if (!isSameOrFallThroughBB(StartMBB, CopyMBB, tii_))
1007 // If the live range starts in another mbb and the copy mbb is not a fall
1008 // through mbb, then we can only cut the range from the beginning of the
1010 RemoveStart = li_->getMBBStartIdx(CopyMBB).getNextIndex().getBaseIndex();
1012 if (LR->valno->def == RemoveStart) {
1013 // If the def MI defines the val# and this copy is the only kill of the
1014 // val#, then propagate the dead marker.
1015 PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
1018 if (LR->valno->isKill(RemoveEnd))
1019 LR->valno->removeKill(RemoveEnd);
1022 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
1023 return removeIntervalIfEmpty(li, li_, tri_);
1026 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
1027 /// from an implicit def to another register can be coalesced away.
1028 bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI,
1030 LiveInterval &ImpLi) const{
1031 if (!CopyMI->killsRegister(ImpLi.reg))
1033 // Make sure this is the only use.
1034 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(ImpLi.reg),
1035 UE = mri_->use_end(); UI != UE;) {
1036 MachineInstr *UseMI = &*UI;
1038 if (CopyMI == UseMI || JoinedCopies.count(UseMI))
1046 /// isWinToJoinVRWithSrcPhysReg - Return true if it's worth while to join a
1047 /// a virtual destination register with physical source register.
1049 SimpleRegisterCoalescing::isWinToJoinVRWithSrcPhysReg(MachineInstr *CopyMI,
1050 MachineBasicBlock *CopyMBB,
1051 LiveInterval &DstInt,
1052 LiveInterval &SrcInt) {
1053 // If the virtual register live interval is long but it has low use desity,
1054 // do not join them, instead mark the physical register as its allocation
1056 const TargetRegisterClass *RC = mri_->getRegClass(DstInt.reg);
1057 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1058 unsigned Length = li_->getApproximateInstructionCount(DstInt);
1059 if (Length > Threshold &&
1060 std::distance(mri_->use_nodbg_begin(DstInt.reg),
1061 mri_->use_nodbg_end()) * Threshold < Length)
1064 // If the virtual register live interval extends into a loop, turn down
1067 li_->getInstructionIndex(CopyMI).getDefIndex();
1068 const MachineLoop *L = loopInfo->getLoopFor(CopyMBB);
1070 // Let's see if the virtual register live interval extends into the loop.
1071 LiveInterval::iterator DLR = DstInt.FindLiveRangeContaining(CopyIdx);
1072 assert(DLR != DstInt.end() && "Live range not found!");
1073 DLR = DstInt.FindLiveRangeContaining(DLR->end.getNextSlot());
1074 if (DLR != DstInt.end()) {
1075 CopyMBB = li_->getMBBFromIndex(DLR->start);
1076 L = loopInfo->getLoopFor(CopyMBB);
1080 if (!L || Length <= Threshold)
1083 SlotIndex UseIdx = CopyIdx.getUseIndex();
1084 LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
1085 MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
1086 if (loopInfo->getLoopFor(SMBB) != L) {
1087 if (!loopInfo->isLoopHeader(CopyMBB))
1089 // If vr's live interval extends pass the loop header, do not join.
1090 for (MachineBasicBlock::succ_iterator SI = CopyMBB->succ_begin(),
1091 SE = CopyMBB->succ_end(); SI != SE; ++SI) {
1092 MachineBasicBlock *SuccMBB = *SI;
1093 if (SuccMBB == CopyMBB)
1095 if (DstInt.overlaps(li_->getMBBStartIdx(SuccMBB),
1096 li_->getMBBEndIdx(SuccMBB)))
1103 /// isWinToJoinVRWithDstPhysReg - Return true if it's worth while to join a
1104 /// copy from a virtual source register to a physical destination register.
1106 SimpleRegisterCoalescing::isWinToJoinVRWithDstPhysReg(MachineInstr *CopyMI,
1107 MachineBasicBlock *CopyMBB,
1108 LiveInterval &DstInt,
1109 LiveInterval &SrcInt) {
1110 // If the virtual register live interval is long but it has low use density,
1111 // do not join them, instead mark the physical register as its allocation
1113 const TargetRegisterClass *RC = mri_->getRegClass(SrcInt.reg);
1114 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1115 unsigned Length = li_->getApproximateInstructionCount(SrcInt);
1116 if (Length > Threshold &&
1117 std::distance(mri_->use_nodbg_begin(SrcInt.reg),
1118 mri_->use_nodbg_end()) * Threshold < Length)
1122 // Must be implicit_def.
1125 // If the virtual register live interval is defined or cross a loop, turn
1126 // down aggressiveness.
1128 li_->getInstructionIndex(CopyMI).getDefIndex();
1129 SlotIndex UseIdx = CopyIdx.getUseIndex();
1130 LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
1131 assert(SLR != SrcInt.end() && "Live range not found!");
1132 SLR = SrcInt.FindLiveRangeContaining(SLR->start.getPrevSlot());
1133 if (SLR == SrcInt.end())
1135 MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
1136 const MachineLoop *L = loopInfo->getLoopFor(SMBB);
1138 if (!L || Length <= Threshold)
1141 if (loopInfo->getLoopFor(CopyMBB) != L) {
1142 if (SMBB != L->getLoopLatch())
1144 // If vr's live interval is extended from before the loop latch, do not
1146 for (MachineBasicBlock::pred_iterator PI = SMBB->pred_begin(),
1147 PE = SMBB->pred_end(); PI != PE; ++PI) {
1148 MachineBasicBlock *PredMBB = *PI;
1149 if (PredMBB == SMBB)
1151 if (SrcInt.overlaps(li_->getMBBStartIdx(PredMBB),
1152 li_->getMBBEndIdx(PredMBB)))
1159 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
1160 /// two virtual registers from different register classes.
1162 SimpleRegisterCoalescing::isWinToJoinCrossClass(unsigned SrcReg,
1164 const TargetRegisterClass *SrcRC,
1165 const TargetRegisterClass *DstRC,
1166 const TargetRegisterClass *NewRC) {
1167 unsigned NewRCCount = allocatableRCRegs_[NewRC].count();
1168 // This heuristics is good enough in practice, but it's obviously not *right*.
1169 // 4 is a magic number that works well enough for x86, ARM, etc. It filter
1170 // out all but the most restrictive register classes.
1171 if (NewRCCount > 4 ||
1172 // Early exit if the function is fairly small, coalesce aggressively if
1173 // that's the case. For really special register classes with 3 or
1174 // fewer registers, be a bit more careful.
1175 (li_->getFuncInstructionCount() / NewRCCount) < 8)
1177 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1178 LiveInterval &DstInt = li_->getInterval(DstReg);
1179 unsigned SrcSize = li_->getApproximateInstructionCount(SrcInt);
1180 unsigned DstSize = li_->getApproximateInstructionCount(DstInt);
1181 if (SrcSize <= NewRCCount && DstSize <= NewRCCount)
1183 // Estimate *register use density*. If it doubles or more, abort.
1184 unsigned SrcUses = std::distance(mri_->use_nodbg_begin(SrcReg),
1185 mri_->use_nodbg_end());
1186 unsigned DstUses = std::distance(mri_->use_nodbg_begin(DstReg),
1187 mri_->use_nodbg_end());
1188 unsigned NewUses = SrcUses + DstUses;
1189 unsigned NewSize = SrcSize + DstSize;
1190 if (SrcRC != NewRC && SrcSize > NewRCCount) {
1191 unsigned SrcRCCount = allocatableRCRegs_[SrcRC].count();
1192 if (NewUses*SrcSize*SrcRCCount > 2*SrcUses*NewSize*NewRCCount)
1195 if (DstRC != NewRC && DstSize > NewRCCount) {
1196 unsigned DstRCCount = allocatableRCRegs_[DstRC].count();
1197 if (NewUses*DstSize*DstRCCount > 2*DstUses*NewSize*NewRCCount)
1203 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
1204 /// register with a physical register, check if any of the virtual register
1205 /// operand is a sub-register use or def. If so, make sure it won't result
1206 /// in an illegal extract_subreg or insert_subreg instruction. e.g.
1207 /// vr1024 = extract_subreg vr1025, 1
1209 /// vr1024 = mov8rr AH
1210 /// If vr1024 is coalesced with AH, the extract_subreg is now illegal since
1211 /// AH does not have a super-reg whose sub-register 1 is AH.
1213 SimpleRegisterCoalescing::HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
1216 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(VirtReg),
1217 E = mri_->reg_end(); I != E; ++I) {
1218 MachineOperand &O = I.getOperand();
1221 MachineInstr *MI = &*I;
1222 if (MI == CopyMI || JoinedCopies.count(MI))
1224 unsigned SubIdx = O.getSubReg();
1225 if (SubIdx && !tri_->getSubReg(PhysReg, SubIdx))
1227 if (MI->isExtractSubreg()) {
1228 SubIdx = MI->getOperand(2).getImm();
1229 if (O.isUse() && !tri_->getSubReg(PhysReg, SubIdx))
1232 unsigned SrcReg = MI->getOperand(1).getReg();
1233 const TargetRegisterClass *RC =
1234 TargetRegisterInfo::isPhysicalRegister(SrcReg)
1235 ? tri_->getPhysicalRegisterRegClass(SrcReg)
1236 : mri_->getRegClass(SrcReg);
1237 if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
1241 if (MI->isInsertSubreg() || MI->isSubregToReg()) {
1242 SubIdx = MI->getOperand(3).getImm();
1243 if (VirtReg == MI->getOperand(0).getReg()) {
1244 if (!tri_->getSubReg(PhysReg, SubIdx))
1247 unsigned DstReg = MI->getOperand(0).getReg();
1248 const TargetRegisterClass *RC =
1249 TargetRegisterInfo::isPhysicalRegister(DstReg)
1250 ? tri_->getPhysicalRegisterRegClass(DstReg)
1251 : mri_->getRegClass(DstReg);
1252 if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
1261 /// CanJoinExtractSubRegToPhysReg - Return true if it's possible to coalesce
1262 /// an extract_subreg where dst is a physical register, e.g.
1263 /// cl = EXTRACT_SUBREG reg1024, 1
1265 SimpleRegisterCoalescing::CanJoinExtractSubRegToPhysReg(unsigned DstReg,
1266 unsigned SrcReg, unsigned SubIdx,
1267 unsigned &RealDstReg) {
1268 const TargetRegisterClass *RC = mri_->getRegClass(SrcReg);
1269 RealDstReg = tri_->getMatchingSuperReg(DstReg, SubIdx, RC);
1271 DEBUG(dbgs() << "\tIncompatible source regclass: "
1272 << "none of the super-registers of " << tri_->getName(DstReg)
1273 << " are in " << RC->getName() << ".\n");
1277 LiveInterval &RHS = li_->getInterval(SrcReg);
1278 // For this type of EXTRACT_SUBREG, conservatively
1279 // check if the live interval of the source register interfere with the
1280 // actual super physical register we are trying to coalesce with.
1281 if (li_->hasInterval(RealDstReg) &&
1282 RHS.overlaps(li_->getInterval(RealDstReg))) {
1284 dbgs() << "\t\tInterfere with register ";
1285 li_->getInterval(RealDstReg).print(dbgs(), tri_);
1287 return false; // Not coalescable
1289 for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR)
1290 // Do not check DstReg or its sub-register. JoinIntervals() will take care
1292 if (*SR != DstReg &&
1293 !tri_->isSubRegister(DstReg, *SR) &&
1294 li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1296 dbgs() << "\t\tInterfere with sub-register ";
1297 li_->getInterval(*SR).print(dbgs(), tri_);
1299 return false; // Not coalescable
1304 /// CanJoinInsertSubRegToPhysReg - Return true if it's possible to coalesce
1305 /// an insert_subreg where src is a physical register, e.g.
1306 /// reg1024 = INSERT_SUBREG reg1024, c1, 0
1308 SimpleRegisterCoalescing::CanJoinInsertSubRegToPhysReg(unsigned DstReg,
1309 unsigned SrcReg, unsigned SubIdx,
1310 unsigned &RealSrcReg) {
1311 const TargetRegisterClass *RC = mri_->getRegClass(DstReg);
1312 RealSrcReg = tri_->getMatchingSuperReg(SrcReg, SubIdx, RC);
1314 DEBUG(dbgs() << "\tIncompatible destination regclass: "
1315 << "none of the super-registers of " << tri_->getName(SrcReg)
1316 << " are in " << RC->getName() << ".\n");
1320 LiveInterval &LHS = li_->getInterval(DstReg);
1321 if (li_->hasInterval(RealSrcReg) &&
1322 LHS.overlaps(li_->getInterval(RealSrcReg))) {
1324 dbgs() << "\t\tInterfere with register ";
1325 li_->getInterval(RealSrcReg).print(dbgs(), tri_);
1327 return false; // Not coalescable
1329 for (const unsigned* SR = tri_->getSubRegisters(RealSrcReg); *SR; ++SR)
1330 // Do not check SrcReg or its sub-register. JoinIntervals() will take care
1332 if (*SR != SrcReg &&
1333 !tri_->isSubRegister(SrcReg, *SR) &&
1334 li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
1336 dbgs() << "\t\tInterfere with sub-register ";
1337 li_->getInterval(*SR).print(dbgs(), tri_);
1339 return false; // Not coalescable
1344 /// getRegAllocPreference - Return register allocation preference register.
1346 static unsigned getRegAllocPreference(unsigned Reg, MachineFunction &MF,
1347 MachineRegisterInfo *MRI,
1348 const TargetRegisterInfo *TRI) {
1349 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1351 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
1352 return TRI->ResolveRegAllocHint(Hint.first, Hint.second, MF);
1355 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1356 /// which are the src/dst of the copy instruction CopyMI. This returns true
1357 /// if the copy was successfully coalesced away. If it is not currently
1358 /// possible to coalesce this interval, but it may be possible if other
1359 /// things get coalesced, then it returns true by reference in 'Again'.
1360 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
1361 MachineInstr *CopyMI = TheCopy.MI;
1364 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1365 return false; // Already done.
1367 DEBUG(dbgs() << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
1369 unsigned SrcReg, DstReg, SrcSubIdx = 0, DstSubIdx = 0;
1370 bool isExtSubReg = CopyMI->isExtractSubreg();
1371 bool isInsSubReg = CopyMI->isInsertSubreg();
1372 bool isSubRegToReg = CopyMI->isSubregToReg();
1373 unsigned SubIdx = 0;
1375 DstReg = CopyMI->getOperand(0).getReg();
1376 DstSubIdx = CopyMI->getOperand(0).getSubReg();
1377 SrcReg = CopyMI->getOperand(1).getReg();
1378 SrcSubIdx = CopyMI->getOperand(2).getImm();
1379 } else if (isInsSubReg || isSubRegToReg) {
1380 DstReg = CopyMI->getOperand(0).getReg();
1381 DstSubIdx = CopyMI->getOperand(3).getImm();
1382 SrcReg = CopyMI->getOperand(2).getReg();
1383 SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1384 if (SrcSubIdx && SrcSubIdx != DstSubIdx) {
1385 // r1025 = INSERT_SUBREG r1025, r1024<2>, 2 Then r1024 has already been
1386 // coalesced to a larger register so the subreg indices cancel out.
1387 DEBUG(dbgs() << "\tSource of insert_subreg or subreg_to_reg is already "
1388 "coalesced to another register.\n");
1389 return false; // Not coalescable.
1391 } else if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
1392 if (SrcSubIdx && DstSubIdx && SrcSubIdx != DstSubIdx) {
1393 // e.g. %reg16404:1<def> = MOV8rr %reg16412:2<kill>
1395 return false; // Not coalescable.
1398 llvm_unreachable("Unrecognized copy instruction!");
1401 // If they are already joined we continue.
1402 if (SrcReg == DstReg) {
1403 DEBUG(dbgs() << "\tCopy already coalesced.\n");
1404 return false; // Not coalescable.
1407 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1408 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1410 // If they are both physical registers, we cannot join them.
1411 if (SrcIsPhys && DstIsPhys) {
1412 DEBUG(dbgs() << "\tCan not coalesce physregs.\n");
1413 return false; // Not coalescable.
1416 // We only join virtual registers with allocatable physical registers.
1417 if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
1418 DEBUG(dbgs() << "\tSrc reg is unallocatable physreg.\n");
1419 return false; // Not coalescable.
1421 if (DstIsPhys && !allocatableRegs_[DstReg]) {
1422 DEBUG(dbgs() << "\tDst reg is unallocatable physreg.\n");
1423 return false; // Not coalescable.
1426 // We cannot handle dual subreg indices and mismatched classes at the same
1428 if (SrcSubIdx && DstSubIdx && differingRegisterClasses(SrcReg, DstReg)) {
1429 DEBUG(dbgs() << "\tCannot handle subreg indices and mismatched classes.\n");
1433 // Check that a physical source register is compatible with dst regclass
1435 unsigned SrcSubReg = SrcSubIdx ?
1436 tri_->getSubReg(SrcReg, SrcSubIdx) : SrcReg;
1437 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
1438 const TargetRegisterClass *DstSubRC = DstRC;
1440 DstSubRC = DstRC->getSubRegisterRegClass(DstSubIdx);
1441 assert(DstSubRC && "Illegal subregister index");
1442 if (!DstSubRC->contains(SrcSubReg)) {
1443 DEBUG(dbgs() << "\tIncompatible destination regclass: "
1444 << "none of the super-registers of "
1445 << tri_->getName(SrcSubReg) << " are in "
1446 << DstSubRC->getName() << ".\n");
1447 return false; // Not coalescable.
1451 // Check that a physical dst register is compatible with source regclass
1453 unsigned DstSubReg = DstSubIdx ?
1454 tri_->getSubReg(DstReg, DstSubIdx) : DstReg;
1455 const TargetRegisterClass *SrcRC = mri_->getRegClass(SrcReg);
1456 const TargetRegisterClass *SrcSubRC = SrcRC;
1458 SrcSubRC = SrcRC->getSubRegisterRegClass(SrcSubIdx);
1459 assert(SrcSubRC && "Illegal subregister index");
1460 if (!SrcSubRC->contains(DstSubReg)) {
1461 DEBUG(dbgs() << "\tIncompatible source regclass: "
1462 << "none of the super-registers of "
1463 << tri_->getName(DstSubReg) << " are in "
1464 << SrcSubRC->getName() << ".\n");
1466 return false; // Not coalescable.
1470 // Should be non-null only when coalescing to a sub-register class.
1471 bool CrossRC = false;
1472 const TargetRegisterClass *SrcRC= SrcIsPhys ? 0 : mri_->getRegClass(SrcReg);
1473 const TargetRegisterClass *DstRC= DstIsPhys ? 0 : mri_->getRegClass(DstReg);
1474 const TargetRegisterClass *NewRC = NULL;
1475 unsigned RealDstReg = 0;
1476 unsigned RealSrcReg = 0;
1477 if (isExtSubReg || isInsSubReg || isSubRegToReg) {
1478 SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm();
1479 if (SrcIsPhys && isExtSubReg) {
1480 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
1481 // coalesced with AX.
1482 unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
1484 // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
1485 // coalesced to a larger register so the subreg indices cancel out.
1486 if (DstSubIdx != SubIdx) {
1487 DEBUG(dbgs() << "\t Sub-register indices mismatch.\n");
1488 return false; // Not coalescable.
1491 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
1493 } else if (DstIsPhys && (isInsSubReg || isSubRegToReg)) {
1494 // EAX = INSERT_SUBREG EAX, r1024, 0
1495 unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1497 // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
1498 // coalesced to a larger register so the subreg indices cancel out.
1499 if (SrcSubIdx != SubIdx) {
1500 DEBUG(dbgs() << "\t Sub-register indices mismatch.\n");
1501 return false; // Not coalescable.
1504 DstReg = tri_->getSubReg(DstReg, SubIdx);
1506 } else if ((DstIsPhys && isExtSubReg) ||
1507 (SrcIsPhys && (isInsSubReg || isSubRegToReg))) {
1508 if (!isSubRegToReg && CopyMI->getOperand(1).getSubReg()) {
1509 DEBUG(dbgs() << "\tSrc of extract_subreg already coalesced with reg"
1510 << " of a super-class.\n");
1511 return false; // Not coalescable.
1514 // FIXME: The following checks are somewhat conservative. Perhaps a better
1515 // way to implement this is to treat this as coalescing a vr with the
1516 // super physical register.
1518 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealDstReg))
1519 return false; // Not coalescable
1521 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1522 return false; // Not coalescable
1526 unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg()
1527 : CopyMI->getOperand(2).getSubReg();
1529 if (OldSubIdx == SubIdx && !differingRegisterClasses(SrcReg, DstReg))
1530 // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been
1531 // coalesced to a larger register so the subreg indices cancel out.
1532 // Also check if the other larger register is of the same register
1533 // class as the would be resulting register.
1536 DEBUG(dbgs() << "\t Sub-register indices mismatch.\n");
1537 return false; // Not coalescable.
1541 if (!DstIsPhys && !SrcIsPhys) {
1542 if (isInsSubReg || isSubRegToReg) {
1543 NewRC = tri_->getMatchingSuperRegClass(DstRC, SrcRC, SubIdx);
1544 } else // extract_subreg {
1545 NewRC = tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx);
1548 DEBUG(dbgs() << "\t Conflicting sub-register indices.\n");
1549 return false; // Not coalescable
1552 if (!isWinToJoinCrossClass(SrcReg, DstReg, SrcRC, DstRC, NewRC)) {
1553 DEBUG(dbgs() << "\tAvoid coalescing to constrained register class: "
1554 << SrcRC->getName() << "/"
1555 << DstRC->getName() << " -> "
1556 << NewRC->getName() << ".\n");
1557 Again = true; // May be possible to coalesce later.
1562 } else if (differingRegisterClasses(SrcReg, DstReg)) {
1563 if (DisableCrossClassJoin)
1567 // FIXME: What if the result of a EXTRACT_SUBREG is then coalesced
1568 // with another? If it's the resulting destination register, then
1569 // the subidx must be propagated to uses (but only those defined
1570 // by the EXTRACT_SUBREG). If it's being coalesced into another
1571 // register, it should be safe because register is assumed to have
1572 // the register class of the super-register.
1574 // Process moves where one of the registers have a sub-register index.
1575 MachineOperand *DstMO = CopyMI->findRegisterDefOperand(DstReg);
1576 MachineOperand *SrcMO = CopyMI->findRegisterUseOperand(SrcReg);
1577 SubIdx = DstMO->getSubReg();
1579 if (SrcMO->getSubReg())
1580 // FIXME: can we handle this?
1582 // This is not an insert_subreg but it looks like one.
1583 // e.g. %reg1024:4 = MOV32rr %EAX
1586 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1587 return false; // Not coalescable
1591 SubIdx = SrcMO->getSubReg();
1593 // This is not a extract_subreg but it looks like one.
1594 // e.g. %cl = MOV16rr %reg1024:1
1597 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx,RealDstReg))
1598 return false; // Not coalescable
1604 // Now determine the register class of the joined register.
1605 if (!SrcIsPhys && !DstIsPhys) {
1608 SubIdx ? tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx) : SrcRC;
1609 } else if (isInsSubReg) {
1611 SubIdx ? tri_->getMatchingSuperRegClass(DstRC, SrcRC, SubIdx) : DstRC;
1613 NewRC = getCommonSubClass(SrcRC, DstRC);
1617 DEBUG(dbgs() << "\tDisjoint regclasses: "
1618 << SrcRC->getName() << ", "
1619 << DstRC->getName() << ".\n");
1620 return false; // Not coalescable.
1623 // If we are joining two virtual registers and the resulting register
1624 // class is more restrictive (fewer register, smaller size). Check if it's
1625 // worth doing the merge.
1626 if (!isWinToJoinCrossClass(SrcReg, DstReg, SrcRC, DstRC, NewRC)) {
1627 DEBUG(dbgs() << "\tAvoid coalescing to constrained register class: "
1628 << SrcRC->getName() << "/"
1629 << DstRC->getName() << " -> "
1630 << NewRC->getName() << ".\n");
1631 // Allow the coalescer to try again in case either side gets coalesced to
1632 // a physical register that's compatible with the other side. e.g.
1633 // r1024 = MOV32to32_ r1025
1634 // But later r1024 is assigned EAX then r1025 may be coalesced with EAX.
1635 Again = true; // May be possible to coalesce later.
1641 // Will it create illegal extract_subreg / insert_subreg?
1642 if (SrcIsPhys && HasIncompatibleSubRegDefUse(CopyMI, DstReg, SrcReg))
1644 if (DstIsPhys && HasIncompatibleSubRegDefUse(CopyMI, SrcReg, DstReg))
1647 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1648 LiveInterval &DstInt = li_->getInterval(DstReg);
1649 assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
1650 "Register mapping is horribly broken!");
1653 dbgs() << "\t\tInspecting ";
1654 if (SrcRC) dbgs() << SrcRC->getName() << ": ";
1655 SrcInt.print(dbgs(), tri_);
1656 dbgs() << "\n\t\t and ";
1657 if (DstRC) dbgs() << DstRC->getName() << ": ";
1658 DstInt.print(dbgs(), tri_);
1662 // Save a copy of the virtual register live interval. We'll manually
1663 // merge this into the "real" physical register live interval this is
1665 OwningPtr<LiveInterval> SavedLI;
1667 SavedLI.reset(li_->dupInterval(&SrcInt));
1668 else if (RealSrcReg)
1669 SavedLI.reset(li_->dupInterval(&DstInt));
1671 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg) {
1672 // Check if it is necessary to propagate "isDead" property.
1673 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
1674 bool isDead = mopd->isDead();
1676 // We need to be careful about coalescing a source physical register with a
1677 // virtual register. Once the coalescing is done, it cannot be broken and
1678 // these are not spillable! If the destination interval uses are far away,
1679 // think twice about coalescing them!
1680 if (!isDead && (SrcIsPhys || DstIsPhys)) {
1681 // If the virtual register live interval is long but it has low use
1682 // density, do not join them, instead mark the physical register as its
1683 // allocation preference.
1684 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
1685 LiveInterval &JoinPInt = SrcIsPhys ? SrcInt : DstInt;
1686 unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
1687 unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
1689 // Don't join with physregs that have a ridiculous number of live
1690 // ranges. The data structure performance is really bad when that
1692 if (JoinPInt.ranges.size() > 1000) {
1693 mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
1696 << "\tPhysical register live interval too complicated, abort!\n");
1700 const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
1701 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1702 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
1703 if (Length > Threshold &&
1704 std::distance(mri_->use_nodbg_begin(JoinVReg),
1705 mri_->use_nodbg_end()) * Threshold < Length) {
1706 // Before giving up coalescing, if definition of source is defined by
1707 // trivial computation, try rematerializing it.
1708 if (ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI))
1711 mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
1713 DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
1714 Again = true; // May be possible to coalesce later.
1720 // Okay, attempt to join these two intervals. On failure, this returns false.
1721 // Otherwise, if one of the intervals being joined is a physreg, this method
1722 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1723 // been modified, so we can use this information below to update aliases.
1724 bool Swapped = false;
1725 // If SrcInt is implicitly defined, it's safe to coalesce.
1726 if (SrcInt.empty()) {
1727 if (!CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
1728 // Only coalesce an empty interval (defined by implicit_def) with
1729 // another interval which has a valno defined by the CopyMI and the CopyMI
1730 // is a kill of the implicit def.
1731 DEBUG(dbgs() << "\tNot profitable!\n");
1734 } else if (!JoinIntervals(DstInt, SrcInt, Swapped)) {
1735 // Coalescing failed.
1737 // If definition of source is defined by trivial computation, try
1738 // rematerializing it.
1739 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1740 ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI))
1743 // If we can eliminate the copy without merging the live ranges, do so now.
1744 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1745 (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
1746 RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
1747 JoinedCopies.insert(CopyMI);
1748 DEBUG(dbgs() << "\tTrivial!\n");
1752 // Otherwise, we are unable to join the intervals.
1753 DEBUG(dbgs() << "\tInterference!\n");
1754 Again = true; // May be possible to coalesce later.
1758 LiveInterval *ResSrcInt = &SrcInt;
1759 LiveInterval *ResDstInt = &DstInt;
1761 std::swap(SrcReg, DstReg);
1762 std::swap(ResSrcInt, ResDstInt);
1764 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1765 "LiveInterval::join didn't work right!");
1767 // If we're about to merge live ranges into a physical register live interval,
1768 // we have to update any aliased register's live ranges to indicate that they
1769 // have clobbered values for this range.
1770 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1771 // If this is a extract_subreg where dst is a physical register, e.g.
1772 // cl = EXTRACT_SUBREG reg1024, 1
1773 // then create and update the actual physical register allocated to RHS.
1774 if (RealDstReg || RealSrcReg) {
1775 LiveInterval &RealInt =
1776 li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg);
1777 for (LiveInterval::const_vni_iterator I = SavedLI->vni_begin(),
1778 E = SavedLI->vni_end(); I != E; ++I) {
1779 const VNInfo *ValNo = *I;
1780 VNInfo *NewValNo = RealInt.getNextValue(ValNo->def, ValNo->getCopy(),
1781 false, // updated at *
1782 li_->getVNInfoAllocator());
1783 NewValNo->setFlags(ValNo->getFlags()); // * updated here.
1784 RealInt.addKills(NewValNo, ValNo->kills);
1785 RealInt.MergeValueInAsValue(*SavedLI, ValNo, NewValNo);
1787 RealInt.weight += SavedLI->weight;
1788 DstReg = RealDstReg ? RealDstReg : RealSrcReg;
1791 // Update the liveintervals of sub-registers.
1792 for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
1793 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*li_, *ResSrcInt,
1794 li_->getVNInfoAllocator());
1797 // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
1798 // larger super-register.
1799 if ((isExtSubReg || isInsSubReg || isSubRegToReg) &&
1800 !SrcIsPhys && !DstIsPhys) {
1801 if ((isExtSubReg && !Swapped) ||
1802 ((isInsSubReg || isSubRegToReg) && Swapped)) {
1803 ResSrcInt->Copy(*ResDstInt, mri_, li_->getVNInfoAllocator());
1804 std::swap(SrcReg, DstReg);
1805 std::swap(ResSrcInt, ResDstInt);
1809 // Coalescing to a virtual register that is of a sub-register class of the
1810 // other. Make sure the resulting register is set to the right register class.
1814 // This may happen even if it's cross-rc coalescing. e.g.
1815 // %reg1026<def> = SUBREG_TO_REG 0, %reg1037<kill>, 4
1816 // reg1026 -> GR64, reg1037 -> GR32_ABCD. The resulting register will have to
1817 // be allocate a register from GR64_ABCD.
1819 mri_->setRegClass(DstReg, NewRC);
1821 // Remember to delete the copy instruction.
1822 JoinedCopies.insert(CopyMI);
1824 UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
1826 // If we have extended the live range of a physical register, make sure we
1827 // update live-in lists as well.
1828 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1829 const LiveInterval &VRegInterval = li_->getInterval(SrcReg);
1830 SmallVector<MachineBasicBlock*, 16> BlockSeq;
1831 for (LiveInterval::const_iterator I = VRegInterval.begin(),
1832 E = VRegInterval.end(); I != E; ++I ) {
1833 li_->findLiveInMBBs(I->start, I->end, BlockSeq);
1834 for (unsigned idx = 0, size = BlockSeq.size(); idx != size; ++idx) {
1835 MachineBasicBlock &block = *BlockSeq[idx];
1836 if (!block.isLiveIn(DstReg))
1837 block.addLiveIn(DstReg);
1843 // SrcReg is guarateed to be the register whose live interval that is
1845 li_->removeInterval(SrcReg);
1847 // Update regalloc hint.
1848 tri_->UpdateRegAllocHint(SrcReg, DstReg, *mf_);
1850 // Manually deleted the live interval copy.
1856 // If resulting interval has a preference that no longer fits because of subreg
1857 // coalescing, just clear the preference.
1858 unsigned Preference = getRegAllocPreference(ResDstInt->reg, *mf_, mri_, tri_);
1859 if (Preference && (isExtSubReg || isInsSubReg || isSubRegToReg) &&
1860 TargetRegisterInfo::isVirtualRegister(ResDstInt->reg)) {
1861 const TargetRegisterClass *RC = mri_->getRegClass(ResDstInt->reg);
1862 if (!RC->contains(Preference))
1863 mri_->setRegAllocationHint(ResDstInt->reg, 0, 0);
1867 dbgs() << "\t\tJoined. Result = ";
1868 ResDstInt->print(dbgs(), tri_);
1876 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1877 /// compute what the resultant value numbers for each value in the input two
1878 /// ranges will be. This is complicated by copies between the two which can
1879 /// and will commonly cause multiple value numbers to be merged into one.
1881 /// VN is the value number that we're trying to resolve. InstDefiningValue
1882 /// keeps track of the new InstDefiningValue assignment for the result
1883 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1884 /// whether a value in this or other is a copy from the opposite set.
1885 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1886 /// already been assigned.
1888 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1889 /// contains the value number the copy is from.
1891 static unsigned ComputeUltimateVN(VNInfo *VNI,
1892 SmallVector<VNInfo*, 16> &NewVNInfo,
1893 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1894 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1895 SmallVector<int, 16> &ThisValNoAssignments,
1896 SmallVector<int, 16> &OtherValNoAssignments) {
1897 unsigned VN = VNI->id;
1899 // If the VN has already been computed, just return it.
1900 if (ThisValNoAssignments[VN] >= 0)
1901 return ThisValNoAssignments[VN];
1902 assert(ThisValNoAssignments[VN] != -2 && "Cyclic value numbers");
1904 // If this val is not a copy from the other val, then it must be a new value
1905 // number in the destination.
1906 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1907 if (I == ThisFromOther.end()) {
1908 NewVNInfo.push_back(VNI);
1909 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1911 VNInfo *OtherValNo = I->second;
1913 // Otherwise, this *is* a copy from the RHS. If the other side has already
1914 // been computed, return it.
1915 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1916 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1918 // Mark this value number as currently being computed, then ask what the
1919 // ultimate value # of the other value is.
1920 ThisValNoAssignments[VN] = -2;
1921 unsigned UltimateVN =
1922 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1923 OtherValNoAssignments, ThisValNoAssignments);
1924 return ThisValNoAssignments[VN] = UltimateVN;
1927 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
1928 return std::find(V.begin(), V.end(), Val) != V.end();
1931 static bool isValNoDefMove(const MachineInstr *MI, unsigned DR, unsigned SR,
1932 const TargetInstrInfo *TII,
1933 const TargetRegisterInfo *TRI) {
1934 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1935 if (TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
1937 else if (MI->isExtractSubreg()) {
1938 DstReg = MI->getOperand(0).getReg();
1939 SrcReg = MI->getOperand(1).getReg();
1940 } else if (MI->isSubregToReg() ||
1941 MI->isInsertSubreg()) {
1942 DstReg = MI->getOperand(0).getReg();
1943 SrcReg = MI->getOperand(2).getReg();
1946 return (SrcReg == SR || TRI->isSuperRegister(SR, SrcReg)) &&
1947 (DstReg == DR || TRI->isSuperRegister(DR, DstReg));
1950 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
1951 /// the specified live interval is defined by a copy from the specified
1953 bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li,
1956 unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno);
1959 // FIXME: Do isPHIDef and isDefAccurate both need to be tested?
1960 if ((LR->valno->isPHIDef() || !LR->valno->isDefAccurate()) &&
1961 TargetRegisterInfo::isPhysicalRegister(li.reg) &&
1962 *tri_->getSuperRegisters(li.reg)) {
1963 // It's a sub-register live interval, we may not have precise information.
1965 MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start);
1966 if (DefMI && isValNoDefMove(DefMI, li.reg, Reg, tii_, tri_)) {
1967 // Cache computed info.
1968 LR->valno->def = LR->start;
1969 LR->valno->setCopy(DefMI);
1977 /// ValueLiveAt - Return true if the LiveRange pointed to by the given
1978 /// iterator, or any subsequent range with the same value number,
1979 /// is live at the given point.
1980 bool SimpleRegisterCoalescing::ValueLiveAt(LiveInterval::iterator LRItr,
1981 LiveInterval::iterator LREnd,
1982 SlotIndex defPoint) const {
1983 for (const VNInfo *valno = LRItr->valno;
1984 (LRItr != LREnd) && (LRItr->valno == valno); ++LRItr) {
1985 if (LRItr->contains(defPoint))
1993 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1994 /// caller of this method must guarantee that the RHS only contains a single
1995 /// value number and that the RHS is not defined by a copy from this
1996 /// interval. This returns false if the intervals are not joinable, or it
1997 /// joins them and returns true.
1998 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
1999 assert(RHS.containsOneValue());
2001 // Some number (potentially more than one) value numbers in the current
2002 // interval may be defined as copies from the RHS. Scan the overlapping
2003 // portions of the LHS and RHS, keeping track of this and looking for
2004 // overlapping live ranges that are NOT defined as copies. If these exist, we
2007 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
2008 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
2010 if (LHSIt->start < RHSIt->start) {
2011 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
2012 if (LHSIt != LHS.begin()) --LHSIt;
2013 } else if (RHSIt->start < LHSIt->start) {
2014 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
2015 if (RHSIt != RHS.begin()) --RHSIt;
2018 SmallVector<VNInfo*, 8> EliminatedLHSVals;
2021 // Determine if these live intervals overlap.
2022 bool Overlaps = false;
2023 if (LHSIt->start <= RHSIt->start)
2024 Overlaps = LHSIt->end > RHSIt->start;
2026 Overlaps = RHSIt->end > LHSIt->start;
2028 // If the live intervals overlap, there are two interesting cases: if the
2029 // LHS interval is defined by a copy from the RHS, it's ok and we record
2030 // that the LHS value # is the same as the RHS. If it's not, then we cannot
2031 // coalesce these live ranges and we bail out.
2033 // If we haven't already recorded that this value # is safe, check it.
2034 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
2035 // If it's re-defined by an early clobber somewhere in the live range,
2036 // then conservatively abort coalescing.
2037 if (LHSIt->valno->hasRedefByEC())
2039 // Copy from the RHS?
2040 if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg))
2041 return false; // Nope, bail out.
2043 if (ValueLiveAt(LHSIt, LHS.end(), RHSIt->valno->def))
2044 // Here is an interesting situation:
2046 // vr1025 = copy vr1024
2051 // Even though vr1025 is copied from vr1024, it's not safe to
2052 // coalesce them since the live range of vr1025 intersects the
2053 // def of vr1024. This happens because vr1025 is assigned the
2054 // value of the previous iteration of vr1024.
2056 EliminatedLHSVals.push_back(LHSIt->valno);
2059 // We know this entire LHS live range is okay, so skip it now.
2060 if (++LHSIt == LHSEnd) break;
2064 if (LHSIt->end < RHSIt->end) {
2065 if (++LHSIt == LHSEnd) break;
2067 // One interesting case to check here. It's possible that we have
2068 // something like "X3 = Y" which defines a new value number in the LHS,
2069 // and is the last use of this liverange of the RHS. In this case, we
2070 // want to notice this copy (so that it gets coalesced away) even though
2071 // the live ranges don't actually overlap.
2072 if (LHSIt->start == RHSIt->end) {
2073 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
2074 // We already know that this value number is going to be merged in
2075 // if coalescing succeeds. Just skip the liverange.
2076 if (++LHSIt == LHSEnd) break;
2078 // If it's re-defined by an early clobber somewhere in the live range,
2079 // then conservatively abort coalescing.
2080 if (LHSIt->valno->hasRedefByEC())
2082 // Otherwise, if this is a copy from the RHS, mark it as being merged
2084 if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) {
2085 if (ValueLiveAt(LHSIt, LHS.end(), RHSIt->valno->def))
2086 // Here is an interesting situation:
2088 // vr1025 = copy vr1024
2093 // Even though vr1025 is copied from vr1024, it's not safe to
2094 // coalesced them since live range of vr1025 intersects the
2095 // def of vr1024. This happens because vr1025 is assigned the
2096 // value of the previous iteration of vr1024.
2098 EliminatedLHSVals.push_back(LHSIt->valno);
2100 // We know this entire LHS live range is okay, so skip it now.
2101 if (++LHSIt == LHSEnd) break;
2106 if (++RHSIt == RHSEnd) break;
2110 // If we got here, we know that the coalescing will be successful and that
2111 // the value numbers in EliminatedLHSVals will all be merged together. Since
2112 // the most common case is that EliminatedLHSVals has a single number, we
2113 // optimize for it: if there is more than one value, we merge them all into
2114 // the lowest numbered one, then handle the interval as if we were merging
2115 // with one value number.
2116 VNInfo *LHSValNo = NULL;
2117 if (EliminatedLHSVals.size() > 1) {
2118 // Loop through all the equal value numbers merging them into the smallest
2120 VNInfo *Smallest = EliminatedLHSVals[0];
2121 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
2122 if (EliminatedLHSVals[i]->id < Smallest->id) {
2123 // Merge the current notion of the smallest into the smaller one.
2124 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
2125 Smallest = EliminatedLHSVals[i];
2127 // Merge into the smallest.
2128 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
2131 LHSValNo = Smallest;
2132 } else if (EliminatedLHSVals.empty()) {
2133 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
2134 *tri_->getSuperRegisters(LHS.reg))
2135 // Imprecise sub-register information. Can't handle it.
2137 llvm_unreachable("No copies from the RHS?");
2139 LHSValNo = EliminatedLHSVals[0];
2142 // Okay, now that there is a single LHS value number that we're merging the
2143 // RHS into, update the value number info for the LHS to indicate that the
2144 // value number is defined where the RHS value number was.
2145 const VNInfo *VNI = RHS.getValNumInfo(0);
2146 LHSValNo->def = VNI->def;
2147 LHSValNo->setCopy(VNI->getCopy());
2149 // Okay, the final step is to loop over the RHS live intervals, adding them to
2151 if (VNI->hasPHIKill())
2152 LHSValNo->setHasPHIKill(true);
2153 LHS.addKills(LHSValNo, VNI->kills);
2154 LHS.MergeRangesInAsValue(RHS, LHSValNo);
2156 LHS.ComputeJoinedWeight(RHS);
2158 // Update regalloc hint if both are virtual registers.
2159 if (TargetRegisterInfo::isVirtualRegister(LHS.reg) &&
2160 TargetRegisterInfo::isVirtualRegister(RHS.reg)) {
2161 std::pair<unsigned, unsigned> RHSPref = mri_->getRegAllocationHint(RHS.reg);
2162 std::pair<unsigned, unsigned> LHSPref = mri_->getRegAllocationHint(LHS.reg);
2163 if (RHSPref != LHSPref)
2164 mri_->setRegAllocationHint(LHS.reg, RHSPref.first, RHSPref.second);
2167 // Update the liveintervals of sub-registers.
2168 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg))
2169 for (const unsigned *AS = tri_->getSubRegisters(LHS.reg); *AS; ++AS)
2170 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*li_, LHS,
2171 li_->getVNInfoAllocator());
2176 /// JoinIntervals - Attempt to join these two intervals. On failure, this
2177 /// returns false. Otherwise, if one of the intervals being joined is a
2178 /// physreg, this method always canonicalizes LHS to be it. The output
2179 /// "RHS" will not have been modified, so we can use this information
2180 /// below to update aliases.
2182 SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
2184 // Compute the final value assignment, assuming that the live ranges can be
2186 SmallVector<int, 16> LHSValNoAssignments;
2187 SmallVector<int, 16> RHSValNoAssignments;
2188 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
2189 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
2190 SmallVector<VNInfo*, 16> NewVNInfo;
2192 // If a live interval is a physical register, conservatively check if any
2193 // of its sub-registers is overlapping the live interval of the virtual
2194 // register. If so, do not coalesce.
2195 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
2196 *tri_->getSubRegisters(LHS.reg)) {
2197 // If it's coalescing a virtual register to a physical register, estimate
2198 // its live interval length. This is the *cost* of scanning an entire live
2199 // interval. If the cost is low, we'll do an exhaustive check instead.
2201 // If this is something like this:
2209 // That is, the live interval of v1024 crosses a bb. Then we can't rely on
2210 // less conservative check. It's possible a sub-register is defined before
2211 // v1024 (or live in) and live out of BB1.
2212 if (RHS.containsOneValue() &&
2213 li_->intervalIsInOneMBB(RHS) &&
2214 li_->getApproximateInstructionCount(RHS) <= 10) {
2215 // Perform a more exhaustive check for some common cases.
2216 if (li_->conflictsWithSubPhysRegRef(RHS, LHS.reg, true, JoinedCopies))
2219 for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
2220 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
2222 dbgs() << "\tInterfere with sub-register ";
2223 li_->getInterval(*SR).print(dbgs(), tri_);
2228 } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
2229 *tri_->getSubRegisters(RHS.reg)) {
2230 if (LHS.containsOneValue() &&
2231 li_->getApproximateInstructionCount(LHS) <= 10) {
2232 // Perform a more exhaustive check for some common cases.
2233 if (li_->conflictsWithSubPhysRegRef(LHS, RHS.reg, false, JoinedCopies))
2236 for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
2237 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
2239 dbgs() << "\tInterfere with sub-register ";
2240 li_->getInterval(*SR).print(dbgs(), tri_);
2247 // Compute ultimate value numbers for the LHS and RHS values.
2248 if (RHS.containsOneValue()) {
2249 // Copies from a liveinterval with a single value are simple to handle and
2250 // very common, handle the special case here. This is important, because
2251 // often RHS is small and LHS is large (e.g. a physreg).
2253 // Find out if the RHS is defined as a copy from some value in the LHS.
2254 int RHSVal0DefinedFromLHS = -1;
2256 VNInfo *RHSValNoInfo = NULL;
2257 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
2258 unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0);
2259 if (RHSSrcReg == 0 || RHSSrcReg != LHS.reg) {
2260 // If RHS is not defined as a copy from the LHS, we can use simpler and
2261 // faster checks to see if the live ranges are coalescable. This joiner
2262 // can't swap the LHS/RHS intervals though.
2263 if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
2264 return SimpleJoin(LHS, RHS);
2266 RHSValNoInfo = RHSValNoInfo0;
2269 // It was defined as a copy from the LHS, find out what value # it is.
2271 LHS.getLiveRangeContaining(RHSValNoInfo0->def.getPrevSlot())->valno;
2272 RHSValID = RHSValNoInfo->id;
2273 RHSVal0DefinedFromLHS = RHSValID;
2276 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
2277 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
2278 NewVNInfo.resize(LHS.getNumValNums(), NULL);
2280 // Okay, *all* of the values in LHS that are defined as a copy from RHS
2281 // should now get updated.
2282 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2285 unsigned VN = VNI->id;
2286 if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) {
2287 if (LHSSrcReg != RHS.reg) {
2288 // If this is not a copy from the RHS, its value number will be
2289 // unmodified by the coalescing.
2290 NewVNInfo[VN] = VNI;
2291 LHSValNoAssignments[VN] = VN;
2292 } else if (RHSValID == -1) {
2293 // Otherwise, it is a copy from the RHS, and we don't already have a
2294 // value# for it. Keep the current value number, but remember it.
2295 LHSValNoAssignments[VN] = RHSValID = VN;
2296 NewVNInfo[VN] = RHSValNoInfo;
2297 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
2299 // Otherwise, use the specified value #.
2300 LHSValNoAssignments[VN] = RHSValID;
2301 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
2302 NewVNInfo[VN] = RHSValNoInfo;
2303 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
2307 NewVNInfo[VN] = VNI;
2308 LHSValNoAssignments[VN] = VN;
2312 assert(RHSValID != -1 && "Didn't find value #?");
2313 RHSValNoAssignments[0] = RHSValID;
2314 if (RHSVal0DefinedFromLHS != -1) {
2315 // This path doesn't go through ComputeUltimateVN so just set
2317 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
2320 // Loop over the value numbers of the LHS, seeing if any are defined from
2322 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2325 if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
2328 // DstReg is known to be a register in the LHS interval. If the src is
2329 // from the RHS interval, we can use its value #.
2330 if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
2333 // Figure out the value # from the RHS.
2334 LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
2335 assert(lr && "Cannot find live range");
2336 LHSValsDefinedFromRHS[VNI] = lr->valno;
2339 // Loop over the value numbers of the RHS, seeing if any are defined from
2341 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
2344 if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
2347 // DstReg is known to be a register in the RHS interval. If the src is
2348 // from the LHS interval, we can use its value #.
2349 if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
2352 // Figure out the value # from the LHS.
2353 LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
2354 assert(lr && "Cannot find live range");
2355 RHSValsDefinedFromLHS[VNI] = lr->valno;
2358 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
2359 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
2360 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
2362 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2365 unsigned VN = VNI->id;
2366 if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
2368 ComputeUltimateVN(VNI, NewVNInfo,
2369 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
2370 LHSValNoAssignments, RHSValNoAssignments);
2372 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
2375 unsigned VN = VNI->id;
2376 if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused())
2378 // If this value number isn't a copy from the LHS, it's a new number.
2379 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
2380 NewVNInfo.push_back(VNI);
2381 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
2385 ComputeUltimateVN(VNI, NewVNInfo,
2386 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
2387 RHSValNoAssignments, LHSValNoAssignments);
2391 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
2392 // interval lists to see if these intervals are coalescable.
2393 LiveInterval::const_iterator I = LHS.begin();
2394 LiveInterval::const_iterator IE = LHS.end();
2395 LiveInterval::const_iterator J = RHS.begin();
2396 LiveInterval::const_iterator JE = RHS.end();
2398 // Skip ahead until the first place of potential sharing.
2399 if (I->start < J->start) {
2400 I = std::upper_bound(I, IE, J->start);
2401 if (I != LHS.begin()) --I;
2402 } else if (J->start < I->start) {
2403 J = std::upper_bound(J, JE, I->start);
2404 if (J != RHS.begin()) --J;
2408 // Determine if these two live ranges overlap.
2410 if (I->start < J->start) {
2411 Overlaps = I->end > J->start;
2413 Overlaps = J->end > I->start;
2416 // If so, check value # info to determine if they are really different.
2418 // If the live range overlap will map to the same value number in the
2419 // result liverange, we can still coalesce them. If not, we can't.
2420 if (LHSValNoAssignments[I->valno->id] !=
2421 RHSValNoAssignments[J->valno->id])
2423 // If it's re-defined by an early clobber somewhere in the live range,
2424 // then conservatively abort coalescing.
2425 if (NewVNInfo[LHSValNoAssignments[I->valno->id]]->hasRedefByEC())
2429 if (I->end < J->end) {
2438 // Update kill info. Some live ranges are extended due to copy coalescing.
2439 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
2440 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
2441 VNInfo *VNI = I->first;
2442 unsigned LHSValID = LHSValNoAssignments[VNI->id];
2443 NewVNInfo[LHSValID]->removeKill(VNI->def);
2444 if (VNI->hasPHIKill())
2445 NewVNInfo[LHSValID]->setHasPHIKill(true);
2446 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
2449 // Update kill info. Some live ranges are extended due to copy coalescing.
2450 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
2451 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
2452 VNInfo *VNI = I->first;
2453 unsigned RHSValID = RHSValNoAssignments[VNI->id];
2454 NewVNInfo[RHSValID]->removeKill(VNI->def);
2455 if (VNI->hasPHIKill())
2456 NewVNInfo[RHSValID]->setHasPHIKill(true);
2457 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
2460 // If we get here, we know that we can coalesce the live ranges. Ask the
2461 // intervals to coalesce themselves now.
2462 if ((RHS.ranges.size() > LHS.ranges.size() &&
2463 TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
2464 TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
2465 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo,
2469 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
2477 // DepthMBBCompare - Comparison predicate that sort first based on the loop
2478 // depth of the basic block (the unsigned), and then on the MBB number.
2479 struct DepthMBBCompare {
2480 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
2481 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
2482 // Deeper loops first
2483 if (LHS.first != RHS.first)
2484 return LHS.first > RHS.first;
2486 // Prefer blocks that are more connected in the CFG. This takes care of
2487 // the most difficult copies first while intervals are short.
2488 unsigned cl = LHS.second->pred_size() + LHS.second->succ_size();
2489 unsigned cr = RHS.second->pred_size() + RHS.second->succ_size();
2493 // As a last resort, sort by block number.
2494 return LHS.second->getNumber() < RHS.second->getNumber();
2499 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
2500 std::vector<CopyRec> &TryAgain) {
2501 DEBUG(dbgs() << MBB->getName() << ":\n");
2503 std::vector<CopyRec> VirtCopies;
2504 std::vector<CopyRec> PhysCopies;
2505 std::vector<CopyRec> ImpDefCopies;
2506 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
2508 MachineInstr *Inst = MII++;
2510 // If this isn't a copy nor a extract_subreg, we can't join intervals.
2511 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2512 bool isInsUndef = false;
2513 if (Inst->isExtractSubreg()) {
2514 DstReg = Inst->getOperand(0).getReg();
2515 SrcReg = Inst->getOperand(1).getReg();
2516 } else if (Inst->isInsertSubreg()) {
2517 DstReg = Inst->getOperand(0).getReg();
2518 SrcReg = Inst->getOperand(2).getReg();
2519 if (Inst->getOperand(1).isUndef())
2521 } else if (Inst->isInsertSubreg() || Inst->isSubregToReg()) {
2522 DstReg = Inst->getOperand(0).getReg();
2523 SrcReg = Inst->getOperand(2).getReg();
2524 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
2527 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
2528 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
2530 (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty()))
2531 ImpDefCopies.push_back(CopyRec(Inst, 0));
2532 else if (SrcIsPhys || DstIsPhys)
2533 PhysCopies.push_back(CopyRec(Inst, 0));
2535 VirtCopies.push_back(CopyRec(Inst, 0));
2538 // Try coalescing implicit copies and insert_subreg <undef> first,
2539 // followed by copies to / from physical registers, then finally copies
2540 // from virtual registers to virtual registers.
2541 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
2542 CopyRec &TheCopy = ImpDefCopies[i];
2544 if (!JoinCopy(TheCopy, Again))
2546 TryAgain.push_back(TheCopy);
2548 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
2549 CopyRec &TheCopy = PhysCopies[i];
2551 if (!JoinCopy(TheCopy, Again))
2553 TryAgain.push_back(TheCopy);
2555 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
2556 CopyRec &TheCopy = VirtCopies[i];
2558 if (!JoinCopy(TheCopy, Again))
2560 TryAgain.push_back(TheCopy);
2564 void SimpleRegisterCoalescing::joinIntervals() {
2565 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
2567 std::vector<CopyRec> TryAgainList;
2568 if (loopInfo->empty()) {
2569 // If there are no loops in the function, join intervals in function order.
2570 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
2572 CopyCoalesceInMBB(I, TryAgainList);
2574 // Otherwise, join intervals in inner loops before other intervals.
2575 // Unfortunately we can't just iterate over loop hierarchy here because
2576 // there may be more MBB's than BB's. Collect MBB's for sorting.
2578 // Join intervals in the function prolog first. We want to join physical
2579 // registers with virtual registers before the intervals got too long.
2580 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
2581 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
2582 MachineBasicBlock *MBB = I;
2583 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
2586 // Sort by loop depth.
2587 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
2589 // Finally, join intervals in loop nest order.
2590 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
2591 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
2594 // Joining intervals can allow other intervals to be joined. Iteratively join
2595 // until we make no progress.
2596 bool ProgressMade = true;
2597 while (ProgressMade) {
2598 ProgressMade = false;
2600 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
2601 CopyRec &TheCopy = TryAgainList[i];
2606 bool Success = JoinCopy(TheCopy, Again);
2607 if (Success || !Again) {
2608 TheCopy.MI = 0; // Mark this one as done.
2609 ProgressMade = true;
2615 /// Return true if the two specified registers belong to different register
2616 /// classes. The registers may be either phys or virt regs.
2618 SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
2619 unsigned RegB) const {
2620 // Get the register classes for the first reg.
2621 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
2622 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
2623 "Shouldn't consider two physregs!");
2624 return !mri_->getRegClass(RegB)->contains(RegA);
2627 // Compare against the regclass for the second reg.
2628 const TargetRegisterClass *RegClassA = mri_->getRegClass(RegA);
2629 if (TargetRegisterInfo::isVirtualRegister(RegB)) {
2630 const TargetRegisterClass *RegClassB = mri_->getRegClass(RegB);
2631 return RegClassA != RegClassB;
2633 return !RegClassA->contains(RegB);
2636 /// lastRegisterUse - Returns the last (non-debug) use of the specific register
2637 /// between cycles Start and End or NULL if there are no uses.
2639 SimpleRegisterCoalescing::lastRegisterUse(SlotIndex Start,
2642 SlotIndex &UseIdx) const{
2643 UseIdx = SlotIndex();
2644 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2645 MachineOperand *LastUse = NULL;
2646 for (MachineRegisterInfo::use_nodbg_iterator I = mri_->use_nodbg_begin(Reg),
2647 E = mri_->use_nodbg_end(); I != E; ++I) {
2648 MachineOperand &Use = I.getOperand();
2649 MachineInstr *UseMI = Use.getParent();
2650 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2651 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2652 SrcReg == DstReg && SrcSubIdx == DstSubIdx)
2653 // Ignore identity copies.
2655 SlotIndex Idx = li_->getInstructionIndex(UseMI);
2656 // FIXME: Should this be Idx != UseIdx? SlotIndex() will return something
2657 // that compares higher than any other interval.
2658 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
2660 UseIdx = Idx.getUseIndex();
2666 SlotIndex s = Start;
2667 SlotIndex e = End.getPrevSlot().getBaseIndex();
2669 // Skip deleted instructions
2670 MachineInstr *MI = li_->getInstructionFromIndex(e);
2671 while (e != SlotIndex() && e.getPrevIndex() >= s && !MI) {
2672 e = e.getPrevIndex();
2673 MI = li_->getInstructionFromIndex(e);
2675 if (e < s || MI == NULL)
2678 // Ignore identity copies.
2679 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2680 if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2681 SrcReg == DstReg && SrcSubIdx == DstSubIdx))
2682 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
2683 MachineOperand &Use = MI->getOperand(i);
2684 if (Use.isReg() && Use.isUse() && Use.getReg() &&
2685 tri_->regsOverlap(Use.getReg(), Reg)) {
2686 UseIdx = e.getUseIndex();
2691 e = e.getPrevIndex();
2697 void SimpleRegisterCoalescing::releaseMemory() {
2698 JoinedCopies.clear();
2699 ReMatCopies.clear();
2703 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
2705 mri_ = &fn.getRegInfo();
2706 tm_ = &fn.getTarget();
2707 tri_ = tm_->getRegisterInfo();
2708 tii_ = tm_->getInstrInfo();
2709 li_ = &getAnalysis<LiveIntervals>();
2710 AA = &getAnalysis<AliasAnalysis>();
2711 loopInfo = &getAnalysis<MachineLoopInfo>();
2713 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
2714 << "********** Function: "
2715 << ((Value*)mf_->getFunction())->getName() << '\n');
2717 allocatableRegs_ = tri_->getAllocatableSet(fn);
2718 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
2719 E = tri_->regclass_end(); I != E; ++I)
2720 allocatableRCRegs_.insert(std::make_pair(*I,
2721 tri_->getAllocatableSet(fn, *I)));
2723 // Join (coalesce) intervals if requested.
2724 if (EnableJoining) {
2727 dbgs() << "********** INTERVALS POST JOINING **********\n";
2728 for (LiveIntervals::iterator I = li_->begin(), E = li_->end();
2730 I->second->print(dbgs(), tri_);
2736 // Perform a final pass over the instructions and compute spill weights
2737 // and remove identity moves.
2738 SmallVector<unsigned, 4> DeadDefs;
2739 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
2740 mbbi != mbbe; ++mbbi) {
2741 MachineBasicBlock* mbb = mbbi;
2742 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
2744 MachineInstr *MI = mii;
2745 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2746 if (JoinedCopies.count(MI)) {
2747 // Delete all coalesced copies.
2748 bool DoDelete = true;
2749 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
2750 assert((MI->isExtractSubreg() || MI->isInsertSubreg() ||
2751 MI->isSubregToReg()) && "Unrecognized copy instruction");
2752 DstReg = MI->getOperand(0).getReg();
2753 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2754 // Do not delete extract_subreg, insert_subreg of physical
2755 // registers unless the definition is dead. e.g.
2756 // %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
2757 // or else the scavenger may complain. LowerSubregs will
2758 // delete them later.
2761 if (MI->allDefsAreDead()) {
2762 LiveInterval &li = li_->getInterval(DstReg);
2763 if (!ShortenDeadCopySrcLiveRange(li, MI))
2764 ShortenDeadCopyLiveRange(li, MI);
2768 mii = llvm::next(mii);
2770 li_->RemoveMachineInstrFromMaps(MI);
2771 mii = mbbi->erase(mii);
2777 // Now check if this is a remat'ed def instruction which is now dead.
2778 if (ReMatDefs.count(MI)) {
2780 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2781 const MachineOperand &MO = MI->getOperand(i);
2784 unsigned Reg = MO.getReg();
2787 if (TargetRegisterInfo::isVirtualRegister(Reg))
2788 DeadDefs.push_back(Reg);
2791 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
2792 !mri_->use_nodbg_empty(Reg)) {
2798 while (!DeadDefs.empty()) {
2799 unsigned DeadDef = DeadDefs.back();
2800 DeadDefs.pop_back();
2801 RemoveDeadDef(li_->getInterval(DeadDef), MI);
2803 li_->RemoveMachineInstrFromMaps(mii);
2804 mii = mbbi->erase(mii);
2810 // If the move will be an identity move delete it
2811 bool isMove= tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
2812 if (isMove && SrcReg == DstReg && SrcSubIdx == DstSubIdx) {
2813 if (li_->hasInterval(SrcReg)) {
2814 LiveInterval &RegInt = li_->getInterval(SrcReg);
2815 // If def of this move instruction is dead, remove its live range
2816 // from the dstination register's live interval.
2817 if (MI->registerDefIsDead(DstReg)) {
2818 if (!ShortenDeadCopySrcLiveRange(RegInt, MI))
2819 ShortenDeadCopyLiveRange(RegInt, MI);
2822 li_->RemoveMachineInstrFromMaps(MI);
2823 mii = mbbi->erase(mii);
2830 // Check for now unnecessary kill flags.
2831 if (li_->isNotInMIMap(MI)) continue;
2832 SlotIndex UseIdx = li_->getInstructionIndex(MI).getUseIndex();
2833 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2834 MachineOperand &MO = MI->getOperand(i);
2835 if (!MO.isReg() || !MO.isKill()) continue;
2836 unsigned reg = MO.getReg();
2837 if (!reg || !li_->hasInterval(reg)) continue;
2838 LiveInterval &LI = li_->getInterval(reg);
2839 const LiveRange *LR = LI.getLiveRangeContaining(UseIdx);
2841 (!LR->valno->isKill(UseIdx.getDefIndex()) &&
2842 LR->valno->def != UseIdx.getDefIndex()))
2843 MO.setIsKill(false);
2852 /// print - Implement the dump method.
2853 void SimpleRegisterCoalescing::print(raw_ostream &O, const Module* m) const {
2857 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
2858 return new SimpleRegisterCoalescing();
2861 // Make sure that anything that uses RegisterCoalescer pulls in this file...
2862 DEFINING_FILE_FOR(SimpleRegisterCoalescing)