1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegisterCoalescer.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/ADT/OwningPtr.h"
35 #include "llvm/ADT/SmallSet.h"
36 #include "llvm/ADT/Statistic.h"
37 #include "llvm/ADT/STLExtras.h"
42 STATISTIC(numJoins , "Number of interval joins performed");
43 STATISTIC(numCrossRCs , "Number of cross class joins performed");
44 STATISTIC(numCommutes , "Number of instruction commuting performed");
45 STATISTIC(numExtends , "Number of copies extended");
46 STATISTIC(NumReMats , "Number of instructions re-materialized");
47 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
48 STATISTIC(numAborts , "Number of times interval joining aborted");
49 STATISTIC(numDeadValNo, "Number of valno def marked dead");
51 char SimpleRegisterCoalescing::ID = 0;
53 EnableJoining("join-liveintervals",
54 cl::desc("Coalesce copies (default=true)"),
58 DisableCrossClassJoin("disable-cross-class-join",
59 cl::desc("Avoid coalescing cross register class copies"),
60 cl::init(false), cl::Hidden);
62 static RegisterPass<SimpleRegisterCoalescing>
63 X("simple-register-coalescing", "Simple Register Coalescing");
65 // Declare that we implement the RegisterCoalescer interface
66 static RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
68 const PassInfo *const llvm::SimpleRegisterCoalescingID = &X;
70 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
72 AU.addRequired<AliasAnalysis>();
73 AU.addRequired<LiveIntervals>();
74 AU.addPreserved<LiveIntervals>();
75 AU.addPreserved<SlotIndexes>();
76 AU.addRequired<MachineLoopInfo>();
77 AU.addPreserved<MachineLoopInfo>();
78 AU.addPreservedID(MachineDominatorsID);
80 AU.addPreservedID(StrongPHIEliminationID);
82 AU.addPreservedID(PHIEliminationID);
83 AU.addPreservedID(TwoAddressInstructionPassID);
84 MachineFunctionPass::getAnalysisUsage(AU);
87 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
88 /// being the source and IntB being the dest, thus this defines a value number
89 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
90 /// see if we can merge these two pieces of B into a single value number,
91 /// eliminating a copy. For example:
95 /// B1 = A3 <- this copy
97 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
98 /// value number to be replaced with B0 (which simplifies the B liveinterval).
100 /// This returns true if an interval was modified.
102 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
104 MachineInstr *CopyMI) {
105 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getDefIndex();
107 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
108 // the example above.
109 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
110 assert(BLR != IntB.end() && "Live range not found!");
111 VNInfo *BValNo = BLR->valno;
113 // Get the location that B is defined at. Two options: either this value has
114 // an unknown definition point or it is defined at CopyIdx. If unknown, we
116 if (!BValNo->getCopy()) return false;
117 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
119 // AValNo is the value number in A that defines the copy, A3 in the example.
120 SlotIndex CopyUseIdx = CopyIdx.getUseIndex();
121 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyUseIdx);
122 assert(ALR != IntA.end() && "Live range not found!");
123 VNInfo *AValNo = ALR->valno;
124 // If it's re-defined by an early clobber somewhere in the live range, then
125 // it's not safe to eliminate the copy. FIXME: This is a temporary workaround.
127 // 172 %ECX<def> = MOV32rr %reg1039<kill>
128 // 180 INLINEASM <es:subl $5,$1
129 // sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9,
131 // 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0
132 // 188 %EAX<def> = MOV32rr %EAX<kill>
133 // 196 %ECX<def> = MOV32rr %ECX<kill>
134 // 204 %ECX<def> = MOV32rr %ECX<kill>
135 // 212 %EAX<def> = MOV32rr %EAX<kill>
136 // 220 %EAX<def> = MOV32rr %EAX
137 // 228 %reg1039<def> = MOV32rr %ECX<kill>
138 // The early clobber operand ties ECX input to the ECX def.
140 // The live interval of ECX is represented as this:
141 // %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47)
142 // The coalescer has no idea there was a def in the middle of [174,230].
143 if (AValNo->hasRedefByEC())
146 // If AValNo is defined as a copy from IntB, we can potentially process this.
147 // Get the instruction that defines this value number.
148 unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
149 if (!SrcReg) return false; // Not defined by a copy.
151 // If the value number is not defined by a copy instruction, ignore it.
153 // If the source register comes from an interval other than IntB, we can't
155 if (SrcReg != IntB.reg) return false;
157 // Get the LiveRange in IntB that this value number starts with.
158 LiveInterval::iterator ValLR =
159 IntB.FindLiveRangeContaining(AValNo->def.getPrevSlot());
160 assert(ValLR != IntB.end() && "Live range not found!");
162 // Make sure that the end of the live range is inside the same block as
164 MachineInstr *ValLREndInst =
165 li_->getInstructionFromIndex(ValLR->end.getPrevSlot());
167 ValLREndInst->getParent() != CopyMI->getParent()) return false;
169 // Okay, we now know that ValLR ends in the same block that the CopyMI
170 // live-range starts. If there are no intervening live ranges between them in
171 // IntB, we can merge them.
172 if (ValLR+1 != BLR) return false;
174 // If a live interval is a physical register, conservatively check if any
175 // of its sub-registers is overlapping the live interval of the virtual
176 // register. If so, do not coalesce.
177 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
178 *tri_->getSubRegisters(IntB.reg)) {
179 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
180 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
182 dbgs() << "\t\tInterfere with sub-register ";
183 li_->getInterval(*SR).print(dbgs(), tri_);
190 dbgs() << "Extending: ";
191 IntB.print(dbgs(), tri_);
194 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
195 // We are about to delete CopyMI, so need to remove it as the 'instruction
196 // that defines this value #'. Update the valnum with the new defining
198 BValNo->def = FillerStart;
201 // Okay, we can merge them. We need to insert a new liverange:
202 // [ValLR.end, BLR.begin) of either value number, then we merge the
203 // two value numbers.
204 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
206 // If the IntB live range is assigned to a physical register, and if that
207 // physreg has sub-registers, update their live intervals as well.
208 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
209 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
210 LiveInterval &SRLI = li_->getInterval(*SR);
211 SRLI.addRange(LiveRange(FillerStart, FillerEnd,
212 SRLI.getNextValue(FillerStart, 0, true,
213 li_->getVNInfoAllocator())));
217 // Okay, merge "B1" into the same value number as "B0".
218 if (BValNo != ValLR->valno) {
219 IntB.addKills(ValLR->valno, BValNo->kills);
220 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
223 dbgs() << " result = ";
224 IntB.print(dbgs(), tri_);
228 // If the source instruction was killing the source register before the
229 // merge, unset the isKill marker given the live range has been extended.
230 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
232 ValLREndInst->getOperand(UIdx).setIsKill(false);
233 ValLR->valno->removeKill(FillerStart);
236 // If the copy instruction was killing the destination register before the
237 // merge, find the last use and trim the live range. That will also add the
239 if (ALR->valno->isKill(CopyIdx))
240 TrimLiveIntervalToLastUse(CopyUseIdx, CopyMI->getParent(), IntA, ALR);
246 /// HasOtherReachingDefs - Return true if there are definitions of IntB
247 /// other than BValNo val# that can reach uses of AValno val# of IntA.
248 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
252 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
254 if (AI->valno != AValNo) continue;
255 LiveInterval::Ranges::iterator BI =
256 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
257 if (BI != IntB.ranges.begin())
259 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
260 if (BI->valno == BValNo)
262 // When BValNo is null, we're looking for a dummy clobber-value for a subreg.
263 if (!BValNo && !BI->valno->isDefAccurate() && !BI->valno->getCopy())
265 if (BI->start <= AI->start && BI->end > AI->start)
267 if (BI->start > AI->start && BI->start < AI->end)
275 TransferImplicitOps(MachineInstr *MI, MachineInstr *NewMI) {
276 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
278 MachineOperand &MO = MI->getOperand(i);
279 if (MO.isReg() && MO.isImplicit())
280 NewMI->addOperand(MO);
284 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with
285 /// IntA being the source and IntB being the dest, thus this defines a value
286 /// number in IntB. If the source value number (in IntA) is defined by a
287 /// commutable instruction and its other operand is coalesced to the copy dest
288 /// register, see if we can transform the copy into a noop by commuting the
289 /// definition. For example,
291 /// A3 = op A2 B0<kill>
293 /// B1 = A3 <- this copy
295 /// = op A3 <- more uses
299 /// B2 = op B0 A2<kill>
301 /// B1 = B2 <- now an identify copy
303 /// = op B2 <- more uses
305 /// This returns true if an interval was modified.
307 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
309 MachineInstr *CopyMI) {
311 li_->getInstructionIndex(CopyMI).getDefIndex();
313 // FIXME: For now, only eliminate the copy by commuting its def when the
314 // source register is a virtual register. We want to guard against cases
315 // where the copy is a back edge copy and commuting the def lengthen the
316 // live interval of the source register to the entire loop.
317 if (TargetRegisterInfo::isPhysicalRegister(IntA.reg))
320 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
321 // the example above.
322 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
323 assert(BLR != IntB.end() && "Live range not found!");
324 VNInfo *BValNo = BLR->valno;
326 // Get the location that B is defined at. Two options: either this value has
327 // an unknown definition point or it is defined at CopyIdx. If unknown, we
329 if (!BValNo->getCopy()) return false;
330 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
332 // AValNo is the value number in A that defines the copy, A3 in the example.
333 LiveInterval::iterator ALR =
334 IntA.FindLiveRangeContaining(CopyIdx.getUseIndex()); //
336 assert(ALR != IntA.end() && "Live range not found!");
337 VNInfo *AValNo = ALR->valno;
338 // If other defs can reach uses of this def, then it's not safe to perform
339 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
341 if (AValNo->isPHIDef() || !AValNo->isDefAccurate() ||
342 AValNo->isUnused() || AValNo->hasPHIKill())
344 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
345 const TargetInstrDesc &TID = DefMI->getDesc();
346 if (!TID.isCommutable())
348 // If DefMI is a two-address instruction then commuting it will change the
349 // destination register.
350 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg);
351 assert(DefIdx != -1);
353 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx))
355 unsigned Op1, Op2, NewDstIdx;
356 if (!tii_->findCommutedOpIndices(DefMI, Op1, Op2))
360 else if (Op2 == UseOpIdx)
365 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
366 unsigned NewReg = NewDstMO.getReg();
367 if (NewReg != IntB.reg || !NewDstMO.isKill())
370 // Make sure there are no other definitions of IntB that would reach the
371 // uses which the new definition can reach.
372 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
375 bool BHasSubRegs = false;
376 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg))
377 BHasSubRegs = *tri_->getSubRegisters(IntB.reg);
379 // Abort if the subregisters of IntB.reg have values that are not simply the
380 // clobbers from the superreg.
382 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
383 if (HasOtherReachingDefs(IntA, li_->getInterval(*SR), AValNo, 0))
386 // If some of the uses of IntA.reg is already coalesced away, return false.
387 // It's not possible to determine whether it's safe to perform the coalescing.
388 for (MachineRegisterInfo::use_nodbg_iterator UI =
389 mri_->use_nodbg_begin(IntA.reg),
390 UE = mri_->use_nodbg_end(); UI != UE; ++UI) {
391 MachineInstr *UseMI = &*UI;
392 SlotIndex UseIdx = li_->getInstructionIndex(UseMI);
393 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
394 if (ULR == IntA.end())
396 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
400 // At this point we have decided that it is legal to do this
401 // transformation. Start by commuting the instruction.
402 MachineBasicBlock *MBB = DefMI->getParent();
403 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
406 if (NewMI != DefMI) {
407 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
408 MBB->insert(DefMI, NewMI);
411 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
412 NewMI->getOperand(OpIdx).setIsKill();
414 bool BHasPHIKill = BValNo->hasPHIKill();
415 SmallVector<VNInfo*, 4> BDeadValNos;
416 VNInfo::KillSet BKills;
417 std::map<SlotIndex, SlotIndex> BExtend;
419 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
428 // then do not add kills of A to the newly created B interval.
429 bool Extended = BLR->end > ALR->end && ALR->end != ALR->start;
431 BExtend[ALR->end] = BLR->end;
433 // Update uses of IntA of the specific Val# with IntB.
434 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
435 UE = mri_->use_end(); UI != UE;) {
436 MachineOperand &UseMO = UI.getOperand();
437 MachineInstr *UseMI = &*UI;
439 if (JoinedCopies.count(UseMI))
441 if (UseMI->isDebugValue()) {
442 // FIXME These don't have an instruction index. Not clear we have enough
443 // info to decide whether to do this replacement or not. For now do it.
444 UseMO.setReg(NewReg);
447 SlotIndex UseIdx = li_->getInstructionIndex(UseMI).getUseIndex();
448 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
449 if (ULR == IntA.end() || ULR->valno != AValNo)
451 UseMO.setReg(NewReg);
454 if (UseMO.isKill()) {
456 UseMO.setIsKill(false);
458 BKills.push_back(UseIdx.getDefIndex());
460 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
461 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
463 if (DstReg == IntB.reg) {
464 // This copy will become a noop. If it's defining a new val#,
465 // remove that val# as well. However this live range is being
466 // extended to the end of the existing live range defined by the copy.
467 SlotIndex DefIdx = UseIdx.getDefIndex();
468 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
469 BHasPHIKill |= DLR->valno->hasPHIKill();
470 assert(DLR->valno->def == DefIdx);
471 BDeadValNos.push_back(DLR->valno);
472 BExtend[DLR->start] = DLR->end;
473 JoinedCopies.insert(UseMI);
474 // If this is a kill but it's going to be removed, the last use
475 // of the same val# is the new kill.
481 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
482 // simply extend BLR if CopyMI doesn't end the range.
484 dbgs() << "Extending: ";
485 IntB.print(dbgs(), tri_);
488 // Remove val#'s defined by copies that will be coalesced away.
489 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i) {
490 VNInfo *DeadVNI = BDeadValNos[i];
492 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
493 LiveInterval &SRLI = li_->getInterval(*SR);
494 const LiveRange *SRLR = SRLI.getLiveRangeContaining(DeadVNI->def);
495 SRLI.removeValNo(SRLR->valno);
498 IntB.removeValNo(BDeadValNos[i]);
501 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
502 // is updated. Kills are also updated.
503 VNInfo *ValNo = BValNo;
504 ValNo->def = AValNo->def;
506 for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) {
507 if (ValNo->kills[j] != BLR->end)
508 BKills.push_back(ValNo->kills[j]);
510 ValNo->kills.clear();
511 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
513 if (AI->valno != AValNo) continue;
514 SlotIndex End = AI->end;
515 std::map<SlotIndex, SlotIndex>::iterator
516 EI = BExtend.find(End);
517 if (EI != BExtend.end())
519 IntB.addRange(LiveRange(AI->start, End, ValNo));
521 // If the IntB live range is assigned to a physical register, and if that
522 // physreg has sub-registers, update their live intervals as well.
524 for (const unsigned *SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR) {
525 LiveInterval &SRLI = li_->getInterval(*SR);
526 SRLI.MergeInClobberRange(*li_, AI->start, End,
527 li_->getVNInfoAllocator());
531 IntB.addKills(ValNo, BKills);
532 ValNo->setHasPHIKill(BHasPHIKill);
535 dbgs() << " result = ";
536 IntB.print(dbgs(), tri_);
537 dbgs() << "\nShortening: ";
538 IntA.print(dbgs(), tri_);
541 IntA.removeValNo(AValNo);
544 dbgs() << " result = ";
545 IntA.print(dbgs(), tri_);
553 /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply
554 /// fallthoughs to SuccMBB.
555 static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
556 MachineBasicBlock *SuccMBB,
557 const TargetInstrInfo *tii_) {
560 MachineBasicBlock *TBB = 0, *FBB = 0;
561 SmallVector<MachineOperand, 4> Cond;
562 return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
563 MBB->isSuccessor(SuccMBB);
566 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
567 /// from a physical register live interval as well as from the live intervals
568 /// of its sub-registers.
569 static void removeRange(LiveInterval &li,
570 SlotIndex Start, SlotIndex End,
571 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
572 li.removeRange(Start, End, true);
573 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
574 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
575 if (!li_->hasInterval(*SR))
577 LiveInterval &sli = li_->getInterval(*SR);
578 SlotIndex RemoveStart = Start;
579 SlotIndex RemoveEnd = Start;
581 while (RemoveEnd != End) {
582 LiveInterval::iterator LR = sli.FindLiveRangeContaining(RemoveStart);
585 RemoveEnd = (LR->end < End) ? LR->end : End;
586 sli.removeRange(RemoveStart, RemoveEnd, true);
587 RemoveStart = RemoveEnd;
593 /// TrimLiveIntervalToLastUse - If there is a last use in the same basic block
594 /// as the copy instruction, trim the live interval to the last use and return
597 SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(SlotIndex CopyIdx,
598 MachineBasicBlock *CopyMBB,
600 const LiveRange *LR) {
601 SlotIndex MBBStart = li_->getMBBStartIdx(CopyMBB);
602 SlotIndex LastUseIdx;
603 MachineOperand *LastUse =
604 lastRegisterUse(LR->start, CopyIdx.getPrevSlot(), li.reg, LastUseIdx);
606 MachineInstr *LastUseMI = LastUse->getParent();
607 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
614 // r1025<dead> = r1024<kill>
615 if (MBBStart < LR->end)
616 removeRange(li, MBBStart, LR->end, li_, tri_);
620 // There are uses before the copy, just shorten the live range to the end
622 LastUse->setIsKill();
623 removeRange(li, LastUseIdx.getDefIndex(), LR->end, li_, tri_);
624 LR->valno->addKill(LastUseIdx.getDefIndex());
625 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
626 if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
628 // Last use is itself an identity code.
629 int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_);
630 LastUseMI->getOperand(DeadIdx).setIsDead();
636 if (LR->start <= MBBStart && LR->end > MBBStart) {
637 if (LR->start == li_->getZeroIndex()) {
638 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
639 // Live-in to the function but dead. Remove it from entry live-in set.
640 mf_->begin()->removeLiveIn(li.reg);
642 // FIXME: Shorten intervals in BBs that reaches this BB.
648 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
649 /// computation, replace the copy by rematerialize the definition.
650 bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
653 MachineInstr *CopyMI) {
654 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI).getUseIndex();
655 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
656 assert(SrcLR != SrcInt.end() && "Live range not found!");
657 VNInfo *ValNo = SrcLR->valno;
658 // If other defs can reach uses of this def, then it's not safe to perform
659 // the optimization. FIXME: Do isPHIDef and isDefAccurate both need to be
661 if (ValNo->isPHIDef() || !ValNo->isDefAccurate() ||
662 ValNo->isUnused() || ValNo->hasPHIKill())
664 MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
665 const TargetInstrDesc &TID = DefMI->getDesc();
666 if (!TID.isAsCheapAsAMove())
668 if (!tii_->isTriviallyReMaterializable(DefMI, AA))
670 bool SawStore = false;
671 if (!DefMI->isSafeToMove(tii_, AA, SawStore))
673 if (TID.getNumDefs() != 1)
675 if (!DefMI->isImplicitDef()) {
676 // Make sure the copy destination register class fits the instruction
677 // definition register class. The mismatch can happen as a result of earlier
678 // extract_subreg, insert_subreg, subreg_to_reg coalescing.
679 const TargetRegisterClass *RC = TID.OpInfo[0].getRegClass(tri_);
680 if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
681 if (mri_->getRegClass(DstReg) != RC)
683 } else if (!RC->contains(DstReg))
687 // If destination register has a sub-register index on it, make sure it mtches
688 // the instruction register class.
690 const TargetInstrDesc &TID = DefMI->getDesc();
691 if (TID.getNumDefs() != 1)
693 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
694 const TargetRegisterClass *DstSubRC =
695 DstRC->getSubRegisterRegClass(DstSubIdx);
696 const TargetRegisterClass *DefRC = TID.OpInfo[0].getRegClass(tri_);
699 else if (DefRC != DstSubRC)
703 SlotIndex DefIdx = CopyIdx.getDefIndex();
704 const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
705 DLR->valno->setCopy(0);
706 // Don't forget to update sub-register intervals.
707 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
708 for (const unsigned* SR = tri_->getSubRegisters(DstReg); *SR; ++SR) {
709 if (!li_->hasInterval(*SR))
711 const LiveRange *DLR =
712 li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
713 if (DLR && DLR->valno->getCopy() == CopyMI)
714 DLR->valno->setCopy(0);
718 // If copy kills the source register, find the last use and propagate
720 bool checkForDeadDef = false;
721 MachineBasicBlock *MBB = CopyMI->getParent();
722 if (SrcLR->valno->isKill(DefIdx))
723 if (!TrimLiveIntervalToLastUse(CopyIdx, MBB, SrcInt, SrcLR)) {
724 checkForDeadDef = true;
727 MachineBasicBlock::iterator MII =
728 llvm::next(MachineBasicBlock::iterator(CopyMI));
729 tii_->reMaterialize(*MBB, MII, DstReg, DstSubIdx, DefMI, tri_);
730 MachineInstr *NewMI = prior(MII);
732 if (checkForDeadDef) {
733 // PR4090 fix: Trim interval failed because there was no use of the
734 // source interval in this MBB. If the def is in this MBB too then we
735 // should mark it dead:
736 if (DefMI->getParent() == MBB) {
737 DefMI->addRegisterDead(SrcInt.reg, tri_);
738 SrcLR->end = SrcLR->start.getNextSlot();
742 // CopyMI may have implicit operands, transfer them over to the newly
743 // rematerialized instruction. And update implicit def interval valnos.
744 for (unsigned i = CopyMI->getDesc().getNumOperands(),
745 e = CopyMI->getNumOperands(); i != e; ++i) {
746 MachineOperand &MO = CopyMI->getOperand(i);
747 if (MO.isReg() && MO.isImplicit())
748 NewMI->addOperand(MO);
749 if (MO.isDef() && li_->hasInterval(MO.getReg())) {
750 unsigned Reg = MO.getReg();
751 const LiveRange *DLR =
752 li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
753 if (DLR && DLR->valno->getCopy() == CopyMI)
754 DLR->valno->setCopy(0);
755 // Handle subregs as well
756 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
757 for (const unsigned* SR = tri_->getSubRegisters(Reg); *SR; ++SR) {
758 if (!li_->hasInterval(*SR))
760 const LiveRange *DLR =
761 li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
762 if (DLR && DLR->valno->getCopy() == CopyMI)
763 DLR->valno->setCopy(0);
769 TransferImplicitOps(CopyMI, NewMI);
770 li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
771 CopyMI->eraseFromParent();
772 ReMatCopies.insert(CopyMI);
773 ReMatDefs.insert(DefMI);
774 DEBUG(dbgs() << "Remat: " << *NewMI);
779 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
780 /// update the subregister number if it is not zero. If DstReg is a
781 /// physical register and the existing subregister number of the def / use
782 /// being updated is not zero, make sure to set it to the correct physical
785 SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
787 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
788 if (DstIsPhys && SubIdx) {
789 // Figure out the real physical register we are updating with.
790 DstReg = tri_->getSubReg(DstReg, SubIdx);
794 // Copy the register use-list before traversing it. We may be adding operands
795 // and invalidating pointers.
796 SmallVector<std::pair<MachineInstr*, unsigned>, 32> reglist;
797 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
798 E = mri_->reg_end(); I != E; ++I)
799 reglist.push_back(std::make_pair(&*I, I.getOperandNo()));
801 for (unsigned N=0; N != reglist.size(); ++N) {
802 MachineInstr *UseMI = reglist[N].first;
803 MachineOperand &O = UseMI->getOperand(reglist[N].second);
804 unsigned OldSubIdx = O.getSubReg();
806 unsigned UseDstReg = DstReg;
808 UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
810 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
811 if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
812 CopySrcSubIdx, CopyDstSubIdx) &&
813 CopySrcReg != CopyDstReg &&
814 CopySrcReg == SrcReg && CopyDstReg != UseDstReg) {
815 // If the use is a copy and it won't be coalesced away, and its source
816 // is defined by a trivial computation, try to rematerialize it instead.
817 if (!JoinedCopies.count(UseMI) &&
818 ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg,
819 CopyDstSubIdx, UseMI))
826 // Def and kill of subregister of a virtual register actually defs and
827 // kills the whole register. Add imp-defs and imp-kills as needed.
830 UseMI->addRegisterDead(DstReg, tri_, true);
832 UseMI->addRegisterDefined(DstReg, tri_);
833 } else if (!O.isUndef() &&
835 UseMI->isRegTiedToDefOperand(&O-&UseMI->getOperand(0))))
836 UseMI->addRegisterKilled(DstReg, tri_, true);
838 DEBUG(dbgs() << "\t\tupdated: " << li_->getInstructionIndex(UseMI)
843 // Sub-register indexes goes from small to large. e.g.
844 // RAX: 1 -> AL, 2 -> AX, 3 -> EAX
845 // EAX: 1 -> AL, 2 -> AX
846 // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose
847 // sub-register 2 is also AX.
848 if (SubIdx && OldSubIdx && SubIdx != OldSubIdx)
849 assert(OldSubIdx < SubIdx && "Conflicting sub-register index!");
854 DEBUG(dbgs() << "\t\tupdated: " << li_->getInstructionIndex(UseMI)
857 // After updating the operand, check if the machine instruction has
858 // become a copy. If so, update its val# information.
859 if (JoinedCopies.count(UseMI))
862 const TargetInstrDesc &TID = UseMI->getDesc();
863 unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
864 if (TID.getNumDefs() == 1 && TID.getNumOperands() > 2 &&
865 tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
866 CopySrcSubIdx, CopyDstSubIdx) &&
867 CopySrcReg != CopyDstReg &&
868 (TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
869 allocatableRegs_[CopyDstReg])) {
870 LiveInterval &LI = li_->getInterval(CopyDstReg);
872 li_->getInstructionIndex(UseMI).getDefIndex();
873 if (const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx)) {
874 if (DLR->valno->def == DefIdx)
875 DLR->valno->setCopy(UseMI);
881 /// removeIntervalIfEmpty - Check if the live interval of a physical register
882 /// is empty, if so remove it and also remove the empty intervals of its
883 /// sub-registers. Return true if live interval is removed.
884 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
885 const TargetRegisterInfo *tri_) {
887 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
888 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
889 if (!li_->hasInterval(*SR))
891 LiveInterval &sli = li_->getInterval(*SR);
893 li_->removeInterval(*SR);
895 li_->removeInterval(li.reg);
901 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
902 /// Return true if live interval is removed.
903 bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
904 MachineInstr *CopyMI) {
905 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI);
906 LiveInterval::iterator MLR =
907 li.FindLiveRangeContaining(CopyIdx.getDefIndex());
909 return false; // Already removed by ShortenDeadCopySrcLiveRange.
910 SlotIndex RemoveStart = MLR->start;
911 SlotIndex RemoveEnd = MLR->end;
912 SlotIndex DefIdx = CopyIdx.getDefIndex();
913 // Remove the liverange that's defined by this.
914 if (RemoveStart == DefIdx && RemoveEnd == DefIdx.getStoreIndex()) {
915 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
916 return removeIntervalIfEmpty(li, li_, tri_);
921 /// RemoveDeadDef - If a def of a live interval is now determined dead, remove
922 /// the val# it defines. If the live interval becomes empty, remove it as well.
923 bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li,
924 MachineInstr *DefMI) {
925 SlotIndex DefIdx = li_->getInstructionIndex(DefMI).getDefIndex();
926 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
927 if (DefIdx != MLR->valno->def)
929 li.removeValNo(MLR->valno);
930 return removeIntervalIfEmpty(li, li_, tri_);
933 /// PropagateDeadness - Propagate the dead marker to the instruction which
934 /// defines the val#.
935 static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
936 SlotIndex &LRStart, LiveIntervals *li_,
937 const TargetRegisterInfo* tri_) {
938 MachineInstr *DefMI =
939 li_->getInstructionFromIndex(LRStart.getDefIndex());
940 if (DefMI && DefMI != CopyMI) {
941 int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false);
943 DefMI->getOperand(DeadIdx).setIsDead();
945 DefMI->addOperand(MachineOperand::CreateReg(li.reg,
946 /*def*/true, /*implicit*/true, /*kill*/false, /*dead*/true));
947 LRStart = LRStart.getNextSlot();
951 /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially
952 /// extended by a dead copy. Mark the last use (if any) of the val# as kill as
953 /// ends the live range there. If there isn't another use, then this live range
954 /// is dead. Return true if live interval is removed.
956 SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
957 MachineInstr *CopyMI) {
958 SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI);
959 if (CopyIdx == SlotIndex()) {
960 // FIXME: special case: function live in. It can be a general case if the
961 // first instruction index starts at > 0 value.
962 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
963 // Live-in to the function but dead. Remove it from entry live-in set.
964 if (mf_->begin()->isLiveIn(li.reg))
965 mf_->begin()->removeLiveIn(li.reg);
966 const LiveRange *LR = li.getLiveRangeContaining(CopyIdx);
967 removeRange(li, LR->start, LR->end, li_, tri_);
968 return removeIntervalIfEmpty(li, li_, tri_);
971 LiveInterval::iterator LR =
972 li.FindLiveRangeContaining(CopyIdx.getPrevIndex().getStoreIndex());
974 // Livein but defined by a phi.
977 SlotIndex RemoveStart = LR->start;
978 SlotIndex RemoveEnd = CopyIdx.getStoreIndex();
979 if (LR->end > RemoveEnd)
980 // More uses past this copy? Nothing to do.
983 // If there is a last use in the same bb, we can't remove the live range.
984 // Shorten the live interval and return.
985 MachineBasicBlock *CopyMBB = CopyMI->getParent();
986 if (TrimLiveIntervalToLastUse(CopyIdx, CopyMBB, li, LR))
989 // There are other kills of the val#. Nothing to do.
990 if (!li.isOnlyLROfValNo(LR))
993 MachineBasicBlock *StartMBB = li_->getMBBFromIndex(RemoveStart);
994 if (!isSameOrFallThroughBB(StartMBB, CopyMBB, tii_))
995 // If the live range starts in another mbb and the copy mbb is not a fall
996 // through mbb, then we can only cut the range from the beginning of the
998 RemoveStart = li_->getMBBStartIdx(CopyMBB).getNextIndex().getBaseIndex();
1000 if (LR->valno->def == RemoveStart) {
1001 // If the def MI defines the val# and this copy is the only kill of the
1002 // val#, then propagate the dead marker.
1003 PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
1006 if (LR->valno->isKill(RemoveEnd))
1007 LR->valno->removeKill(RemoveEnd);
1010 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
1011 return removeIntervalIfEmpty(li, li_, tri_);
1014 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
1015 /// from an implicit def to another register can be coalesced away.
1016 bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI,
1018 LiveInterval &ImpLi) const{
1019 if (!CopyMI->killsRegister(ImpLi.reg))
1021 // Make sure this is the only use.
1022 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(ImpLi.reg),
1023 UE = mri_->use_end(); UI != UE;) {
1024 MachineInstr *UseMI = &*UI;
1026 if (CopyMI == UseMI || JoinedCopies.count(UseMI))
1034 /// isWinToJoinVRWithSrcPhysReg - Return true if it's worth while to join a
1035 /// a virtual destination register with physical source register.
1037 SimpleRegisterCoalescing::isWinToJoinVRWithSrcPhysReg(MachineInstr *CopyMI,
1038 MachineBasicBlock *CopyMBB,
1039 LiveInterval &DstInt,
1040 LiveInterval &SrcInt) {
1041 // If the virtual register live interval is long but it has low use desity,
1042 // do not join them, instead mark the physical register as its allocation
1044 const TargetRegisterClass *RC = mri_->getRegClass(DstInt.reg);
1045 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1046 unsigned Length = li_->getApproximateInstructionCount(DstInt);
1047 if (Length > Threshold &&
1048 std::distance(mri_->use_nodbg_begin(DstInt.reg),
1049 mri_->use_nodbg_end()) * Threshold < Length)
1052 // If the virtual register live interval extends into a loop, turn down
1055 li_->getInstructionIndex(CopyMI).getDefIndex();
1056 const MachineLoop *L = loopInfo->getLoopFor(CopyMBB);
1058 // Let's see if the virtual register live interval extends into the loop.
1059 LiveInterval::iterator DLR = DstInt.FindLiveRangeContaining(CopyIdx);
1060 assert(DLR != DstInt.end() && "Live range not found!");
1061 DLR = DstInt.FindLiveRangeContaining(DLR->end.getNextSlot());
1062 if (DLR != DstInt.end()) {
1063 CopyMBB = li_->getMBBFromIndex(DLR->start);
1064 L = loopInfo->getLoopFor(CopyMBB);
1068 if (!L || Length <= Threshold)
1071 SlotIndex UseIdx = CopyIdx.getUseIndex();
1072 LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
1073 MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
1074 if (loopInfo->getLoopFor(SMBB) != L) {
1075 if (!loopInfo->isLoopHeader(CopyMBB))
1077 // If vr's live interval extends pass the loop header, do not join.
1078 for (MachineBasicBlock::succ_iterator SI = CopyMBB->succ_begin(),
1079 SE = CopyMBB->succ_end(); SI != SE; ++SI) {
1080 MachineBasicBlock *SuccMBB = *SI;
1081 if (SuccMBB == CopyMBB)
1083 if (DstInt.overlaps(li_->getMBBStartIdx(SuccMBB),
1084 li_->getMBBEndIdx(SuccMBB)))
1091 /// isWinToJoinVRWithDstPhysReg - Return true if it's worth while to join a
1092 /// copy from a virtual source register to a physical destination register.
1094 SimpleRegisterCoalescing::isWinToJoinVRWithDstPhysReg(MachineInstr *CopyMI,
1095 MachineBasicBlock *CopyMBB,
1096 LiveInterval &DstInt,
1097 LiveInterval &SrcInt) {
1098 // If the virtual register live interval is long but it has low use density,
1099 // do not join them, instead mark the physical register as its allocation
1101 const TargetRegisterClass *RC = mri_->getRegClass(SrcInt.reg);
1102 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1103 unsigned Length = li_->getApproximateInstructionCount(SrcInt);
1104 if (Length > Threshold &&
1105 std::distance(mri_->use_nodbg_begin(SrcInt.reg),
1106 mri_->use_nodbg_end()) * Threshold < Length)
1110 // Must be implicit_def.
1113 // If the virtual register live interval is defined or cross a loop, turn
1114 // down aggressiveness.
1116 li_->getInstructionIndex(CopyMI).getDefIndex();
1117 SlotIndex UseIdx = CopyIdx.getUseIndex();
1118 LiveInterval::iterator SLR = SrcInt.FindLiveRangeContaining(UseIdx);
1119 assert(SLR != SrcInt.end() && "Live range not found!");
1120 SLR = SrcInt.FindLiveRangeContaining(SLR->start.getPrevSlot());
1121 if (SLR == SrcInt.end())
1123 MachineBasicBlock *SMBB = li_->getMBBFromIndex(SLR->start);
1124 const MachineLoop *L = loopInfo->getLoopFor(SMBB);
1126 if (!L || Length <= Threshold)
1129 if (loopInfo->getLoopFor(CopyMBB) != L) {
1130 if (SMBB != L->getLoopLatch())
1132 // If vr's live interval is extended from before the loop latch, do not
1134 for (MachineBasicBlock::pred_iterator PI = SMBB->pred_begin(),
1135 PE = SMBB->pred_end(); PI != PE; ++PI) {
1136 MachineBasicBlock *PredMBB = *PI;
1137 if (PredMBB == SMBB)
1139 if (SrcInt.overlaps(li_->getMBBStartIdx(PredMBB),
1140 li_->getMBBEndIdx(PredMBB)))
1147 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
1148 /// two virtual registers from different register classes.
1150 SimpleRegisterCoalescing::isWinToJoinCrossClass(unsigned SrcReg,
1152 const TargetRegisterClass *SrcRC,
1153 const TargetRegisterClass *DstRC,
1154 const TargetRegisterClass *NewRC) {
1155 unsigned NewRCCount = allocatableRCRegs_[NewRC].count();
1156 // This heuristics is good enough in practice, but it's obviously not *right*.
1157 // 4 is a magic number that works well enough for x86, ARM, etc. It filter
1158 // out all but the most restrictive register classes.
1159 if (NewRCCount > 4 ||
1160 // Early exit if the function is fairly small, coalesce aggressively if
1161 // that's the case. For really special register classes with 3 or
1162 // fewer registers, be a bit more careful.
1163 (li_->getFuncInstructionCount() / NewRCCount) < 8)
1165 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1166 LiveInterval &DstInt = li_->getInterval(DstReg);
1167 unsigned SrcSize = li_->getApproximateInstructionCount(SrcInt);
1168 unsigned DstSize = li_->getApproximateInstructionCount(DstInt);
1169 if (SrcSize <= NewRCCount && DstSize <= NewRCCount)
1171 // Estimate *register use density*. If it doubles or more, abort.
1172 unsigned SrcUses = std::distance(mri_->use_nodbg_begin(SrcReg),
1173 mri_->use_nodbg_end());
1174 unsigned DstUses = std::distance(mri_->use_nodbg_begin(DstReg),
1175 mri_->use_nodbg_end());
1176 unsigned NewUses = SrcUses + DstUses;
1177 unsigned NewSize = SrcSize + DstSize;
1178 if (SrcRC != NewRC && SrcSize > NewRCCount) {
1179 unsigned SrcRCCount = allocatableRCRegs_[SrcRC].count();
1180 if (NewUses*SrcSize*SrcRCCount > 2*SrcUses*NewSize*NewRCCount)
1183 if (DstRC != NewRC && DstSize > NewRCCount) {
1184 unsigned DstRCCount = allocatableRCRegs_[DstRC].count();
1185 if (NewUses*DstSize*DstRCCount > 2*DstUses*NewSize*NewRCCount)
1191 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
1192 /// register with a physical register, check if any of the virtual register
1193 /// operand is a sub-register use or def. If so, make sure it won't result
1194 /// in an illegal extract_subreg or insert_subreg instruction. e.g.
1195 /// vr1024 = extract_subreg vr1025, 1
1197 /// vr1024 = mov8rr AH
1198 /// If vr1024 is coalesced with AH, the extract_subreg is now illegal since
1199 /// AH does not have a super-reg whose sub-register 1 is AH.
1201 SimpleRegisterCoalescing::HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
1204 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(VirtReg),
1205 E = mri_->reg_end(); I != E; ++I) {
1206 MachineOperand &O = I.getOperand();
1209 MachineInstr *MI = &*I;
1210 if (MI == CopyMI || JoinedCopies.count(MI))
1212 unsigned SubIdx = O.getSubReg();
1213 if (SubIdx && !tri_->getSubReg(PhysReg, SubIdx))
1215 if (MI->isExtractSubreg()) {
1216 SubIdx = MI->getOperand(2).getImm();
1217 if (O.isUse() && !tri_->getSubReg(PhysReg, SubIdx))
1220 unsigned SrcReg = MI->getOperand(1).getReg();
1221 const TargetRegisterClass *RC =
1222 TargetRegisterInfo::isPhysicalRegister(SrcReg)
1223 ? tri_->getPhysicalRegisterRegClass(SrcReg)
1224 : mri_->getRegClass(SrcReg);
1225 if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
1229 if (MI->isInsertSubreg() || MI->isSubregToReg()) {
1230 SubIdx = MI->getOperand(3).getImm();
1231 if (VirtReg == MI->getOperand(0).getReg()) {
1232 if (!tri_->getSubReg(PhysReg, SubIdx))
1235 unsigned DstReg = MI->getOperand(0).getReg();
1236 const TargetRegisterClass *RC =
1237 TargetRegisterInfo::isPhysicalRegister(DstReg)
1238 ? tri_->getPhysicalRegisterRegClass(DstReg)
1239 : mri_->getRegClass(DstReg);
1240 if (!tri_->getMatchingSuperReg(PhysReg, SubIdx, RC))
1249 /// CanJoinExtractSubRegToPhysReg - Return true if it's possible to coalesce
1250 /// an extract_subreg where dst is a physical register, e.g.
1251 /// cl = EXTRACT_SUBREG reg1024, 1
1253 SimpleRegisterCoalescing::CanJoinExtractSubRegToPhysReg(unsigned DstReg,
1254 unsigned SrcReg, unsigned SubIdx,
1255 unsigned &RealDstReg) {
1256 const TargetRegisterClass *RC = mri_->getRegClass(SrcReg);
1257 RealDstReg = tri_->getMatchingSuperReg(DstReg, SubIdx, RC);
1259 DEBUG(dbgs() << "\tIncompatible source regclass: "
1260 << "none of the super-registers of " << tri_->getName(DstReg)
1261 << " are in " << RC->getName() << ".\n");
1265 LiveInterval &RHS = li_->getInterval(SrcReg);
1266 // For this type of EXTRACT_SUBREG, conservatively
1267 // check if the live interval of the source register interfere with the
1268 // actual super physical register we are trying to coalesce with.
1269 if (li_->hasInterval(RealDstReg) &&
1270 RHS.overlaps(li_->getInterval(RealDstReg))) {
1272 dbgs() << "\t\tInterfere with register ";
1273 li_->getInterval(RealDstReg).print(dbgs(), tri_);
1275 return false; // Not coalescable
1277 for (const unsigned* SR = tri_->getSubRegisters(RealDstReg); *SR; ++SR)
1278 // Do not check DstReg or its sub-register. JoinIntervals() will take care
1280 if (*SR != DstReg &&
1281 !tri_->isSubRegister(DstReg, *SR) &&
1282 li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1284 dbgs() << "\t\tInterfere with sub-register ";
1285 li_->getInterval(*SR).print(dbgs(), tri_);
1287 return false; // Not coalescable
1292 /// CanJoinInsertSubRegToPhysReg - Return true if it's possible to coalesce
1293 /// an insert_subreg where src is a physical register, e.g.
1294 /// reg1024 = INSERT_SUBREG reg1024, c1, 0
1296 SimpleRegisterCoalescing::CanJoinInsertSubRegToPhysReg(unsigned DstReg,
1297 unsigned SrcReg, unsigned SubIdx,
1298 unsigned &RealSrcReg) {
1299 const TargetRegisterClass *RC = mri_->getRegClass(DstReg);
1300 RealSrcReg = tri_->getMatchingSuperReg(SrcReg, SubIdx, RC);
1302 DEBUG(dbgs() << "\tIncompatible destination regclass: "
1303 << "none of the super-registers of " << tri_->getName(SrcReg)
1304 << " are in " << RC->getName() << ".\n");
1308 LiveInterval &LHS = li_->getInterval(DstReg);
1309 if (li_->hasInterval(RealSrcReg) &&
1310 LHS.overlaps(li_->getInterval(RealSrcReg))) {
1312 dbgs() << "\t\tInterfere with register ";
1313 li_->getInterval(RealSrcReg).print(dbgs(), tri_);
1315 return false; // Not coalescable
1317 for (const unsigned* SR = tri_->getSubRegisters(RealSrcReg); *SR; ++SR)
1318 // Do not check SrcReg or its sub-register. JoinIntervals() will take care
1320 if (*SR != SrcReg &&
1321 !tri_->isSubRegister(SrcReg, *SR) &&
1322 li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
1324 dbgs() << "\t\tInterfere with sub-register ";
1325 li_->getInterval(*SR).print(dbgs(), tri_);
1327 return false; // Not coalescable
1332 /// getRegAllocPreference - Return register allocation preference register.
1334 static unsigned getRegAllocPreference(unsigned Reg, MachineFunction &MF,
1335 MachineRegisterInfo *MRI,
1336 const TargetRegisterInfo *TRI) {
1337 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1339 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
1340 return TRI->ResolveRegAllocHint(Hint.first, Hint.second, MF);
1343 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1344 /// which are the src/dst of the copy instruction CopyMI. This returns true
1345 /// if the copy was successfully coalesced away. If it is not currently
1346 /// possible to coalesce this interval, but it may be possible if other
1347 /// things get coalesced, then it returns true by reference in 'Again'.
1348 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
1349 MachineInstr *CopyMI = TheCopy.MI;
1352 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1353 return false; // Already done.
1355 DEBUG(dbgs() << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI);
1357 unsigned SrcReg, DstReg, SrcSubIdx = 0, DstSubIdx = 0;
1358 bool isExtSubReg = CopyMI->isExtractSubreg();
1359 bool isInsSubReg = CopyMI->isInsertSubreg();
1360 bool isSubRegToReg = CopyMI->isSubregToReg();
1361 unsigned SubIdx = 0;
1363 DstReg = CopyMI->getOperand(0).getReg();
1364 DstSubIdx = CopyMI->getOperand(0).getSubReg();
1365 SrcReg = CopyMI->getOperand(1).getReg();
1366 SrcSubIdx = CopyMI->getOperand(2).getImm();
1367 } else if (isInsSubReg || isSubRegToReg) {
1368 DstReg = CopyMI->getOperand(0).getReg();
1369 DstSubIdx = CopyMI->getOperand(3).getImm();
1370 SrcReg = CopyMI->getOperand(2).getReg();
1371 SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1372 if (SrcSubIdx && SrcSubIdx != DstSubIdx) {
1373 // r1025 = INSERT_SUBREG r1025, r1024<2>, 2 Then r1024 has already been
1374 // coalesced to a larger register so the subreg indices cancel out.
1375 DEBUG(dbgs() << "\tSource of insert_subreg or subreg_to_reg is already "
1376 "coalesced to another register.\n");
1377 return false; // Not coalescable.
1379 } else if (tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
1380 if (SrcSubIdx && DstSubIdx && SrcSubIdx != DstSubIdx) {
1381 // e.g. %reg16404:1<def> = MOV8rr %reg16412:2<kill>
1383 return false; // Not coalescable.
1386 llvm_unreachable("Unrecognized copy instruction!");
1389 // If they are already joined we continue.
1390 if (SrcReg == DstReg) {
1391 DEBUG(dbgs() << "\tCopy already coalesced.\n");
1392 return false; // Not coalescable.
1395 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1396 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1398 // If they are both physical registers, we cannot join them.
1399 if (SrcIsPhys && DstIsPhys) {
1400 DEBUG(dbgs() << "\tCan not coalesce physregs.\n");
1401 return false; // Not coalescable.
1404 // We only join virtual registers with allocatable physical registers.
1405 if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
1406 DEBUG(dbgs() << "\tSrc reg is unallocatable physreg.\n");
1407 return false; // Not coalescable.
1409 if (DstIsPhys && !allocatableRegs_[DstReg]) {
1410 DEBUG(dbgs() << "\tDst reg is unallocatable physreg.\n");
1411 return false; // Not coalescable.
1414 // We cannot handle dual subreg indices and mismatched classes at the same
1416 if (SrcSubIdx && DstSubIdx && differingRegisterClasses(SrcReg, DstReg)) {
1417 DEBUG(dbgs() << "\tCannot handle subreg indices and mismatched classes.\n");
1421 // Check that a physical source register is compatible with dst regclass
1423 unsigned SrcSubReg = SrcSubIdx ?
1424 tri_->getSubReg(SrcReg, SrcSubIdx) : SrcReg;
1425 const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg);
1426 const TargetRegisterClass *DstSubRC = DstRC;
1428 DstSubRC = DstRC->getSubRegisterRegClass(DstSubIdx);
1429 assert(DstSubRC && "Illegal subregister index");
1430 if (!DstSubRC->contains(SrcSubReg)) {
1431 DEBUG(dbgs() << "\tIncompatible destination regclass: "
1432 << "none of the super-registers of "
1433 << tri_->getName(SrcSubReg) << " are in "
1434 << DstSubRC->getName() << ".\n");
1435 return false; // Not coalescable.
1439 // Check that a physical dst register is compatible with source regclass
1441 unsigned DstSubReg = DstSubIdx ?
1442 tri_->getSubReg(DstReg, DstSubIdx) : DstReg;
1443 const TargetRegisterClass *SrcRC = mri_->getRegClass(SrcReg);
1444 const TargetRegisterClass *SrcSubRC = SrcRC;
1446 SrcSubRC = SrcRC->getSubRegisterRegClass(SrcSubIdx);
1447 assert(SrcSubRC && "Illegal subregister index");
1448 if (!SrcSubRC->contains(DstSubReg)) {
1449 DEBUG(dbgs() << "\tIncompatible source regclass: "
1450 << "none of the super-registers of "
1451 << tri_->getName(DstSubReg) << " are in "
1452 << SrcSubRC->getName() << ".\n");
1454 return false; // Not coalescable.
1458 // Should be non-null only when coalescing to a sub-register class.
1459 bool CrossRC = false;
1460 const TargetRegisterClass *SrcRC= SrcIsPhys ? 0 : mri_->getRegClass(SrcReg);
1461 const TargetRegisterClass *DstRC= DstIsPhys ? 0 : mri_->getRegClass(DstReg);
1462 const TargetRegisterClass *NewRC = NULL;
1463 unsigned RealDstReg = 0;
1464 unsigned RealSrcReg = 0;
1465 if (isExtSubReg || isInsSubReg || isSubRegToReg) {
1466 SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm();
1467 if (SrcIsPhys && isExtSubReg) {
1468 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
1469 // coalesced with AX.
1470 unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
1472 // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
1473 // coalesced to a larger register so the subreg indices cancel out.
1474 if (DstSubIdx != SubIdx) {
1475 DEBUG(dbgs() << "\t Sub-register indices mismatch.\n");
1476 return false; // Not coalescable.
1479 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
1481 } else if (DstIsPhys && (isInsSubReg || isSubRegToReg)) {
1482 // EAX = INSERT_SUBREG EAX, r1024, 0
1483 unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1485 // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
1486 // coalesced to a larger register so the subreg indices cancel out.
1487 if (SrcSubIdx != SubIdx) {
1488 DEBUG(dbgs() << "\t Sub-register indices mismatch.\n");
1489 return false; // Not coalescable.
1492 DstReg = tri_->getSubReg(DstReg, SubIdx);
1494 } else if ((DstIsPhys && isExtSubReg) ||
1495 (SrcIsPhys && (isInsSubReg || isSubRegToReg))) {
1496 if (!isSubRegToReg && CopyMI->getOperand(1).getSubReg()) {
1497 DEBUG(dbgs() << "\tSrc of extract_subreg already coalesced with reg"
1498 << " of a super-class.\n");
1499 return false; // Not coalescable.
1502 // FIXME: The following checks are somewhat conservative. Perhaps a better
1503 // way to implement this is to treat this as coalescing a vr with the
1504 // super physical register.
1506 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealDstReg))
1507 return false; // Not coalescable
1509 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1510 return false; // Not coalescable
1514 unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg()
1515 : CopyMI->getOperand(2).getSubReg();
1517 if (OldSubIdx == SubIdx && !differingRegisterClasses(SrcReg, DstReg))
1518 // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been
1519 // coalesced to a larger register so the subreg indices cancel out.
1520 // Also check if the other larger register is of the same register
1521 // class as the would be resulting register.
1524 DEBUG(dbgs() << "\t Sub-register indices mismatch.\n");
1525 return false; // Not coalescable.
1529 if (!DstIsPhys && !SrcIsPhys) {
1530 if (isInsSubReg || isSubRegToReg) {
1531 NewRC = tri_->getMatchingSuperRegClass(DstRC, SrcRC, SubIdx);
1532 } else // extract_subreg {
1533 NewRC = tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx);
1536 DEBUG(dbgs() << "\t Conflicting sub-register indices.\n");
1537 return false; // Not coalescable
1540 if (!isWinToJoinCrossClass(SrcReg, DstReg, SrcRC, DstRC, NewRC)) {
1541 DEBUG(dbgs() << "\tAvoid coalescing to constrained register class: "
1542 << SrcRC->getName() << "/"
1543 << DstRC->getName() << " -> "
1544 << NewRC->getName() << ".\n");
1545 Again = true; // May be possible to coalesce later.
1550 } else if (differingRegisterClasses(SrcReg, DstReg)) {
1551 if (DisableCrossClassJoin)
1555 // FIXME: What if the result of a EXTRACT_SUBREG is then coalesced
1556 // with another? If it's the resulting destination register, then
1557 // the subidx must be propagated to uses (but only those defined
1558 // by the EXTRACT_SUBREG). If it's being coalesced into another
1559 // register, it should be safe because register is assumed to have
1560 // the register class of the super-register.
1562 // Process moves where one of the registers have a sub-register index.
1563 MachineOperand *DstMO = CopyMI->findRegisterDefOperand(DstReg);
1564 MachineOperand *SrcMO = CopyMI->findRegisterUseOperand(SrcReg);
1565 SubIdx = DstMO->getSubReg();
1567 if (SrcMO->getSubReg())
1568 // FIXME: can we handle this?
1570 // This is not an insert_subreg but it looks like one.
1571 // e.g. %reg1024:4 = MOV32rr %EAX
1574 if (!CanJoinInsertSubRegToPhysReg(DstReg, SrcReg, SubIdx, RealSrcReg))
1575 return false; // Not coalescable
1579 SubIdx = SrcMO->getSubReg();
1581 // This is not a extract_subreg but it looks like one.
1582 // e.g. %cl = MOV16rr %reg1024:1
1585 if (!CanJoinExtractSubRegToPhysReg(DstReg, SrcReg, SubIdx,RealDstReg))
1586 return false; // Not coalescable
1592 // Now determine the register class of the joined register.
1593 if (!SrcIsPhys && !DstIsPhys) {
1596 SubIdx ? tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx) : SrcRC;
1597 } else if (isInsSubReg) {
1599 SubIdx ? tri_->getMatchingSuperRegClass(DstRC, SrcRC, SubIdx) : DstRC;
1601 NewRC = getCommonSubClass(SrcRC, DstRC);
1605 DEBUG(dbgs() << "\tDisjoint regclasses: "
1606 << SrcRC->getName() << ", "
1607 << DstRC->getName() << ".\n");
1608 return false; // Not coalescable.
1611 // If we are joining two virtual registers and the resulting register
1612 // class is more restrictive (fewer register, smaller size). Check if it's
1613 // worth doing the merge.
1614 if (!isWinToJoinCrossClass(SrcReg, DstReg, SrcRC, DstRC, NewRC)) {
1615 DEBUG(dbgs() << "\tAvoid coalescing to constrained register class: "
1616 << SrcRC->getName() << "/"
1617 << DstRC->getName() << " -> "
1618 << NewRC->getName() << ".\n");
1619 // Allow the coalescer to try again in case either side gets coalesced to
1620 // a physical register that's compatible with the other side. e.g.
1621 // r1024 = MOV32to32_ r1025
1622 // But later r1024 is assigned EAX then r1025 may be coalesced with EAX.
1623 Again = true; // May be possible to coalesce later.
1629 // Will it create illegal extract_subreg / insert_subreg?
1630 if (SrcIsPhys && HasIncompatibleSubRegDefUse(CopyMI, DstReg, SrcReg))
1632 if (DstIsPhys && HasIncompatibleSubRegDefUse(CopyMI, SrcReg, DstReg))
1635 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1636 LiveInterval &DstInt = li_->getInterval(DstReg);
1637 assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
1638 "Register mapping is horribly broken!");
1641 dbgs() << "\t\tInspecting ";
1642 if (SrcRC) dbgs() << SrcRC->getName() << ": ";
1643 SrcInt.print(dbgs(), tri_);
1644 dbgs() << "\n\t\t and ";
1645 if (DstRC) dbgs() << DstRC->getName() << ": ";
1646 DstInt.print(dbgs(), tri_);
1650 // Save a copy of the virtual register live interval. We'll manually
1651 // merge this into the "real" physical register live interval this is
1653 OwningPtr<LiveInterval> SavedLI;
1655 SavedLI.reset(li_->dupInterval(&SrcInt));
1656 else if (RealSrcReg)
1657 SavedLI.reset(li_->dupInterval(&DstInt));
1659 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg) {
1660 // Check if it is necessary to propagate "isDead" property.
1661 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
1662 bool isDead = mopd->isDead();
1664 // We need to be careful about coalescing a source physical register with a
1665 // virtual register. Once the coalescing is done, it cannot be broken and
1666 // these are not spillable! If the destination interval uses are far away,
1667 // think twice about coalescing them!
1668 if (!isDead && (SrcIsPhys || DstIsPhys)) {
1669 // If the virtual register live interval is long but it has low use
1670 // density, do not join them, instead mark the physical register as its
1671 // allocation preference.
1672 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
1673 LiveInterval &JoinPInt = SrcIsPhys ? SrcInt : DstInt;
1674 unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
1675 unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
1677 // Don't join with physregs that have a ridiculous number of live
1678 // ranges. The data structure performance is really bad when that
1680 if (JoinPInt.ranges.size() > 1000) {
1681 mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
1684 << "\tPhysical register live interval too complicated, abort!\n");
1688 const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
1689 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1690 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
1691 if (Length > Threshold &&
1692 std::distance(mri_->use_nodbg_begin(JoinVReg),
1693 mri_->use_nodbg_end()) * Threshold < Length) {
1694 // Before giving up coalescing, if definition of source is defined by
1695 // trivial computation, try rematerializing it.
1696 if (ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI))
1699 mri_->setRegAllocationHint(JoinVInt.reg, 0, JoinPReg);
1701 DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
1702 Again = true; // May be possible to coalesce later.
1708 // Okay, attempt to join these two intervals. On failure, this returns false.
1709 // Otherwise, if one of the intervals being joined is a physreg, this method
1710 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1711 // been modified, so we can use this information below to update aliases.
1712 bool Swapped = false;
1713 // If SrcInt is implicitly defined, it's safe to coalesce.
1714 if (SrcInt.empty()) {
1715 if (!CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
1716 // Only coalesce an empty interval (defined by implicit_def) with
1717 // another interval which has a valno defined by the CopyMI and the CopyMI
1718 // is a kill of the implicit def.
1719 DEBUG(dbgs() << "\tNot profitable!\n");
1722 } else if (!JoinIntervals(DstInt, SrcInt, Swapped)) {
1723 // Coalescing failed.
1725 // If definition of source is defined by trivial computation, try
1726 // rematerializing it.
1727 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1728 ReMaterializeTrivialDef(SrcInt, DstReg, DstSubIdx, CopyMI))
1731 // If we can eliminate the copy without merging the live ranges, do so now.
1732 if (!isExtSubReg && !isInsSubReg && !isSubRegToReg &&
1733 (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
1734 RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
1735 JoinedCopies.insert(CopyMI);
1736 DEBUG(dbgs() << "\tTrivial!\n");
1740 // Otherwise, we are unable to join the intervals.
1741 DEBUG(dbgs() << "\tInterference!\n");
1742 Again = true; // May be possible to coalesce later.
1746 LiveInterval *ResSrcInt = &SrcInt;
1747 LiveInterval *ResDstInt = &DstInt;
1749 std::swap(SrcReg, DstReg);
1750 std::swap(ResSrcInt, ResDstInt);
1752 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1753 "LiveInterval::join didn't work right!");
1755 // If we're about to merge live ranges into a physical register live interval,
1756 // we have to update any aliased register's live ranges to indicate that they
1757 // have clobbered values for this range.
1758 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1759 // If this is a extract_subreg where dst is a physical register, e.g.
1760 // cl = EXTRACT_SUBREG reg1024, 1
1761 // then create and update the actual physical register allocated to RHS.
1762 if (RealDstReg || RealSrcReg) {
1763 LiveInterval &RealInt =
1764 li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg);
1765 for (LiveInterval::const_vni_iterator I = SavedLI->vni_begin(),
1766 E = SavedLI->vni_end(); I != E; ++I) {
1767 const VNInfo *ValNo = *I;
1768 VNInfo *NewValNo = RealInt.getNextValue(ValNo->def, ValNo->getCopy(),
1769 false, // updated at *
1770 li_->getVNInfoAllocator());
1771 NewValNo->setFlags(ValNo->getFlags()); // * updated here.
1772 RealInt.addKills(NewValNo, ValNo->kills);
1773 RealInt.MergeValueInAsValue(*SavedLI, ValNo, NewValNo);
1775 RealInt.weight += SavedLI->weight;
1776 DstReg = RealDstReg ? RealDstReg : RealSrcReg;
1779 // Update the liveintervals of sub-registers.
1780 for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
1781 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*li_, *ResSrcInt,
1782 li_->getVNInfoAllocator());
1785 // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
1786 // larger super-register.
1787 if ((isExtSubReg || isInsSubReg || isSubRegToReg) &&
1788 !SrcIsPhys && !DstIsPhys) {
1789 if ((isExtSubReg && !Swapped) ||
1790 ((isInsSubReg || isSubRegToReg) && Swapped)) {
1791 ResSrcInt->Copy(*ResDstInt, mri_, li_->getVNInfoAllocator());
1792 std::swap(SrcReg, DstReg);
1793 std::swap(ResSrcInt, ResDstInt);
1797 // Coalescing to a virtual register that is of a sub-register class of the
1798 // other. Make sure the resulting register is set to the right register class.
1802 // This may happen even if it's cross-rc coalescing. e.g.
1803 // %reg1026<def> = SUBREG_TO_REG 0, %reg1037<kill>, 4
1804 // reg1026 -> GR64, reg1037 -> GR32_ABCD. The resulting register will have to
1805 // be allocate a register from GR64_ABCD.
1807 mri_->setRegClass(DstReg, NewRC);
1809 // Remember to delete the copy instruction.
1810 JoinedCopies.insert(CopyMI);
1812 UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
1814 // If we have extended the live range of a physical register, make sure we
1815 // update live-in lists as well.
1816 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1817 const LiveInterval &VRegInterval = li_->getInterval(SrcReg);
1818 SmallVector<MachineBasicBlock*, 16> BlockSeq;
1819 for (LiveInterval::const_iterator I = VRegInterval.begin(),
1820 E = VRegInterval.end(); I != E; ++I ) {
1821 li_->findLiveInMBBs(I->start, I->end, BlockSeq);
1822 for (unsigned idx = 0, size = BlockSeq.size(); idx != size; ++idx) {
1823 MachineBasicBlock &block = *BlockSeq[idx];
1824 if (!block.isLiveIn(DstReg))
1825 block.addLiveIn(DstReg);
1831 // SrcReg is guarateed to be the register whose live interval that is
1833 li_->removeInterval(SrcReg);
1835 // Update regalloc hint.
1836 tri_->UpdateRegAllocHint(SrcReg, DstReg, *mf_);
1838 // Manually deleted the live interval copy.
1844 // If resulting interval has a preference that no longer fits because of subreg
1845 // coalescing, just clear the preference.
1846 unsigned Preference = getRegAllocPreference(ResDstInt->reg, *mf_, mri_, tri_);
1847 if (Preference && (isExtSubReg || isInsSubReg || isSubRegToReg) &&
1848 TargetRegisterInfo::isVirtualRegister(ResDstInt->reg)) {
1849 const TargetRegisterClass *RC = mri_->getRegClass(ResDstInt->reg);
1850 if (!RC->contains(Preference))
1851 mri_->setRegAllocationHint(ResDstInt->reg, 0, 0);
1855 dbgs() << "\t\tJoined. Result = ";
1856 ResDstInt->print(dbgs(), tri_);
1864 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1865 /// compute what the resultant value numbers for each value in the input two
1866 /// ranges will be. This is complicated by copies between the two which can
1867 /// and will commonly cause multiple value numbers to be merged into one.
1869 /// VN is the value number that we're trying to resolve. InstDefiningValue
1870 /// keeps track of the new InstDefiningValue assignment for the result
1871 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1872 /// whether a value in this or other is a copy from the opposite set.
1873 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1874 /// already been assigned.
1876 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1877 /// contains the value number the copy is from.
1879 static unsigned ComputeUltimateVN(VNInfo *VNI,
1880 SmallVector<VNInfo*, 16> &NewVNInfo,
1881 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1882 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1883 SmallVector<int, 16> &ThisValNoAssignments,
1884 SmallVector<int, 16> &OtherValNoAssignments) {
1885 unsigned VN = VNI->id;
1887 // If the VN has already been computed, just return it.
1888 if (ThisValNoAssignments[VN] >= 0)
1889 return ThisValNoAssignments[VN];
1890 assert(ThisValNoAssignments[VN] != -2 && "Cyclic value numbers");
1892 // If this val is not a copy from the other val, then it must be a new value
1893 // number in the destination.
1894 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1895 if (I == ThisFromOther.end()) {
1896 NewVNInfo.push_back(VNI);
1897 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1899 VNInfo *OtherValNo = I->second;
1901 // Otherwise, this *is* a copy from the RHS. If the other side has already
1902 // been computed, return it.
1903 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1904 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1906 // Mark this value number as currently being computed, then ask what the
1907 // ultimate value # of the other value is.
1908 ThisValNoAssignments[VN] = -2;
1909 unsigned UltimateVN =
1910 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1911 OtherValNoAssignments, ThisValNoAssignments);
1912 return ThisValNoAssignments[VN] = UltimateVN;
1915 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
1916 return std::find(V.begin(), V.end(), Val) != V.end();
1919 static bool isValNoDefMove(const MachineInstr *MI, unsigned DR, unsigned SR,
1920 const TargetInstrInfo *TII,
1921 const TargetRegisterInfo *TRI) {
1922 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
1923 if (TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
1925 else if (MI->isExtractSubreg()) {
1926 DstReg = MI->getOperand(0).getReg();
1927 SrcReg = MI->getOperand(1).getReg();
1928 } else if (MI->isSubregToReg() ||
1929 MI->isInsertSubreg()) {
1930 DstReg = MI->getOperand(0).getReg();
1931 SrcReg = MI->getOperand(2).getReg();
1934 return (SrcReg == SR || TRI->isSuperRegister(SR, SrcReg)) &&
1935 (DstReg == DR || TRI->isSuperRegister(DR, DstReg));
1938 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
1939 /// the specified live interval is defined by a copy from the specified
1941 bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li,
1944 unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno);
1947 // FIXME: Do isPHIDef and isDefAccurate both need to be tested?
1948 if ((LR->valno->isPHIDef() || !LR->valno->isDefAccurate()) &&
1949 TargetRegisterInfo::isPhysicalRegister(li.reg) &&
1950 *tri_->getSuperRegisters(li.reg)) {
1951 // It's a sub-register live interval, we may not have precise information.
1953 MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start);
1954 if (DefMI && isValNoDefMove(DefMI, li.reg, Reg, tii_, tri_)) {
1955 // Cache computed info.
1956 LR->valno->def = LR->start;
1957 LR->valno->setCopy(DefMI);
1965 /// ValueLiveAt - Return true if the LiveRange pointed to by the given
1966 /// iterator, or any subsequent range with the same value number,
1967 /// is live at the given point.
1968 bool SimpleRegisterCoalescing::ValueLiveAt(LiveInterval::iterator LRItr,
1969 LiveInterval::iterator LREnd,
1970 SlotIndex defPoint) const {
1971 for (const VNInfo *valno = LRItr->valno;
1972 (LRItr != LREnd) && (LRItr->valno == valno); ++LRItr) {
1973 if (LRItr->contains(defPoint))
1981 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1982 /// caller of this method must guarantee that the RHS only contains a single
1983 /// value number and that the RHS is not defined by a copy from this
1984 /// interval. This returns false if the intervals are not joinable, or it
1985 /// joins them and returns true.
1986 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
1987 assert(RHS.containsOneValue());
1989 // Some number (potentially more than one) value numbers in the current
1990 // interval may be defined as copies from the RHS. Scan the overlapping
1991 // portions of the LHS and RHS, keeping track of this and looking for
1992 // overlapping live ranges that are NOT defined as copies. If these exist, we
1995 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
1996 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
1998 if (LHSIt->start < RHSIt->start) {
1999 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
2000 if (LHSIt != LHS.begin()) --LHSIt;
2001 } else if (RHSIt->start < LHSIt->start) {
2002 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
2003 if (RHSIt != RHS.begin()) --RHSIt;
2006 SmallVector<VNInfo*, 8> EliminatedLHSVals;
2009 // Determine if these live intervals overlap.
2010 bool Overlaps = false;
2011 if (LHSIt->start <= RHSIt->start)
2012 Overlaps = LHSIt->end > RHSIt->start;
2014 Overlaps = RHSIt->end > LHSIt->start;
2016 // If the live intervals overlap, there are two interesting cases: if the
2017 // LHS interval is defined by a copy from the RHS, it's ok and we record
2018 // that the LHS value # is the same as the RHS. If it's not, then we cannot
2019 // coalesce these live ranges and we bail out.
2021 // If we haven't already recorded that this value # is safe, check it.
2022 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
2023 // If it's re-defined by an early clobber somewhere in the live range,
2024 // then conservatively abort coalescing.
2025 if (LHSIt->valno->hasRedefByEC())
2027 // Copy from the RHS?
2028 if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg))
2029 return false; // Nope, bail out.
2031 if (ValueLiveAt(LHSIt, LHS.end(), RHSIt->valno->def))
2032 // Here is an interesting situation:
2034 // vr1025 = copy vr1024
2039 // Even though vr1025 is copied from vr1024, it's not safe to
2040 // coalesce them since the live range of vr1025 intersects the
2041 // def of vr1024. This happens because vr1025 is assigned the
2042 // value of the previous iteration of vr1024.
2044 EliminatedLHSVals.push_back(LHSIt->valno);
2047 // We know this entire LHS live range is okay, so skip it now.
2048 if (++LHSIt == LHSEnd) break;
2052 if (LHSIt->end < RHSIt->end) {
2053 if (++LHSIt == LHSEnd) break;
2055 // One interesting case to check here. It's possible that we have
2056 // something like "X3 = Y" which defines a new value number in the LHS,
2057 // and is the last use of this liverange of the RHS. In this case, we
2058 // want to notice this copy (so that it gets coalesced away) even though
2059 // the live ranges don't actually overlap.
2060 if (LHSIt->start == RHSIt->end) {
2061 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
2062 // We already know that this value number is going to be merged in
2063 // if coalescing succeeds. Just skip the liverange.
2064 if (++LHSIt == LHSEnd) break;
2066 // If it's re-defined by an early clobber somewhere in the live range,
2067 // then conservatively abort coalescing.
2068 if (LHSIt->valno->hasRedefByEC())
2070 // Otherwise, if this is a copy from the RHS, mark it as being merged
2072 if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) {
2073 if (ValueLiveAt(LHSIt, LHS.end(), RHSIt->valno->def))
2074 // Here is an interesting situation:
2076 // vr1025 = copy vr1024
2081 // Even though vr1025 is copied from vr1024, it's not safe to
2082 // coalesced them since live range of vr1025 intersects the
2083 // def of vr1024. This happens because vr1025 is assigned the
2084 // value of the previous iteration of vr1024.
2086 EliminatedLHSVals.push_back(LHSIt->valno);
2088 // We know this entire LHS live range is okay, so skip it now.
2089 if (++LHSIt == LHSEnd) break;
2094 if (++RHSIt == RHSEnd) break;
2098 // If we got here, we know that the coalescing will be successful and that
2099 // the value numbers in EliminatedLHSVals will all be merged together. Since
2100 // the most common case is that EliminatedLHSVals has a single number, we
2101 // optimize for it: if there is more than one value, we merge them all into
2102 // the lowest numbered one, then handle the interval as if we were merging
2103 // with one value number.
2104 VNInfo *LHSValNo = NULL;
2105 if (EliminatedLHSVals.size() > 1) {
2106 // Loop through all the equal value numbers merging them into the smallest
2108 VNInfo *Smallest = EliminatedLHSVals[0];
2109 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
2110 if (EliminatedLHSVals[i]->id < Smallest->id) {
2111 // Merge the current notion of the smallest into the smaller one.
2112 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
2113 Smallest = EliminatedLHSVals[i];
2115 // Merge into the smallest.
2116 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
2119 LHSValNo = Smallest;
2120 } else if (EliminatedLHSVals.empty()) {
2121 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
2122 *tri_->getSuperRegisters(LHS.reg))
2123 // Imprecise sub-register information. Can't handle it.
2125 llvm_unreachable("No copies from the RHS?");
2127 LHSValNo = EliminatedLHSVals[0];
2130 // Okay, now that there is a single LHS value number that we're merging the
2131 // RHS into, update the value number info for the LHS to indicate that the
2132 // value number is defined where the RHS value number was.
2133 const VNInfo *VNI = RHS.getValNumInfo(0);
2134 LHSValNo->def = VNI->def;
2135 LHSValNo->setCopy(VNI->getCopy());
2137 // Okay, the final step is to loop over the RHS live intervals, adding them to
2139 if (VNI->hasPHIKill())
2140 LHSValNo->setHasPHIKill(true);
2141 LHS.addKills(LHSValNo, VNI->kills);
2142 LHS.MergeRangesInAsValue(RHS, LHSValNo);
2144 LHS.ComputeJoinedWeight(RHS);
2146 // Update regalloc hint if both are virtual registers.
2147 if (TargetRegisterInfo::isVirtualRegister(LHS.reg) &&
2148 TargetRegisterInfo::isVirtualRegister(RHS.reg)) {
2149 std::pair<unsigned, unsigned> RHSPref = mri_->getRegAllocationHint(RHS.reg);
2150 std::pair<unsigned, unsigned> LHSPref = mri_->getRegAllocationHint(LHS.reg);
2151 if (RHSPref != LHSPref)
2152 mri_->setRegAllocationHint(LHS.reg, RHSPref.first, RHSPref.second);
2155 // Update the liveintervals of sub-registers.
2156 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg))
2157 for (const unsigned *AS = tri_->getSubRegisters(LHS.reg); *AS; ++AS)
2158 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*li_, LHS,
2159 li_->getVNInfoAllocator());
2164 /// JoinIntervals - Attempt to join these two intervals. On failure, this
2165 /// returns false. Otherwise, if one of the intervals being joined is a
2166 /// physreg, this method always canonicalizes LHS to be it. The output
2167 /// "RHS" will not have been modified, so we can use this information
2168 /// below to update aliases.
2170 SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
2172 // Compute the final value assignment, assuming that the live ranges can be
2174 SmallVector<int, 16> LHSValNoAssignments;
2175 SmallVector<int, 16> RHSValNoAssignments;
2176 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
2177 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
2178 SmallVector<VNInfo*, 16> NewVNInfo;
2180 // If a live interval is a physical register, conservatively check if any
2181 // of its sub-registers is overlapping the live interval of the virtual
2182 // register. If so, do not coalesce.
2183 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
2184 *tri_->getSubRegisters(LHS.reg)) {
2185 // If it's coalescing a virtual register to a physical register, estimate
2186 // its live interval length. This is the *cost* of scanning an entire live
2187 // interval. If the cost is low, we'll do an exhaustive check instead.
2189 // If this is something like this:
2197 // That is, the live interval of v1024 crosses a bb. Then we can't rely on
2198 // less conservative check. It's possible a sub-register is defined before
2199 // v1024 (or live in) and live out of BB1.
2200 if (RHS.containsOneValue() &&
2201 li_->intervalIsInOneMBB(RHS) &&
2202 li_->getApproximateInstructionCount(RHS) <= 10) {
2203 // Perform a more exhaustive check for some common cases.
2204 if (li_->conflictsWithSubPhysRegRef(RHS, LHS.reg, true, JoinedCopies))
2207 for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
2208 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
2210 dbgs() << "\tInterfere with sub-register ";
2211 li_->getInterval(*SR).print(dbgs(), tri_);
2216 } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
2217 *tri_->getSubRegisters(RHS.reg)) {
2218 if (LHS.containsOneValue() &&
2219 li_->getApproximateInstructionCount(LHS) <= 10) {
2220 // Perform a more exhaustive check for some common cases.
2221 if (li_->conflictsWithSubPhysRegRef(LHS, RHS.reg, false, JoinedCopies))
2224 for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
2225 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
2227 dbgs() << "\tInterfere with sub-register ";
2228 li_->getInterval(*SR).print(dbgs(), tri_);
2235 // Compute ultimate value numbers for the LHS and RHS values.
2236 if (RHS.containsOneValue()) {
2237 // Copies from a liveinterval with a single value are simple to handle and
2238 // very common, handle the special case here. This is important, because
2239 // often RHS is small and LHS is large (e.g. a physreg).
2241 // Find out if the RHS is defined as a copy from some value in the LHS.
2242 int RHSVal0DefinedFromLHS = -1;
2244 VNInfo *RHSValNoInfo = NULL;
2245 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
2246 unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0);
2247 if (RHSSrcReg == 0 || RHSSrcReg != LHS.reg) {
2248 // If RHS is not defined as a copy from the LHS, we can use simpler and
2249 // faster checks to see if the live ranges are coalescable. This joiner
2250 // can't swap the LHS/RHS intervals though.
2251 if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
2252 return SimpleJoin(LHS, RHS);
2254 RHSValNoInfo = RHSValNoInfo0;
2257 // It was defined as a copy from the LHS, find out what value # it is.
2259 LHS.getLiveRangeContaining(RHSValNoInfo0->def.getPrevSlot())->valno;
2260 RHSValID = RHSValNoInfo->id;
2261 RHSVal0DefinedFromLHS = RHSValID;
2264 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
2265 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
2266 NewVNInfo.resize(LHS.getNumValNums(), NULL);
2268 // Okay, *all* of the values in LHS that are defined as a copy from RHS
2269 // should now get updated.
2270 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2273 unsigned VN = VNI->id;
2274 if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) {
2275 if (LHSSrcReg != RHS.reg) {
2276 // If this is not a copy from the RHS, its value number will be
2277 // unmodified by the coalescing.
2278 NewVNInfo[VN] = VNI;
2279 LHSValNoAssignments[VN] = VN;
2280 } else if (RHSValID == -1) {
2281 // Otherwise, it is a copy from the RHS, and we don't already have a
2282 // value# for it. Keep the current value number, but remember it.
2283 LHSValNoAssignments[VN] = RHSValID = VN;
2284 NewVNInfo[VN] = RHSValNoInfo;
2285 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
2287 // Otherwise, use the specified value #.
2288 LHSValNoAssignments[VN] = RHSValID;
2289 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
2290 NewVNInfo[VN] = RHSValNoInfo;
2291 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
2295 NewVNInfo[VN] = VNI;
2296 LHSValNoAssignments[VN] = VN;
2300 assert(RHSValID != -1 && "Didn't find value #?");
2301 RHSValNoAssignments[0] = RHSValID;
2302 if (RHSVal0DefinedFromLHS != -1) {
2303 // This path doesn't go through ComputeUltimateVN so just set
2305 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
2308 // Loop over the value numbers of the LHS, seeing if any are defined from
2310 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2313 if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
2316 // DstReg is known to be a register in the LHS interval. If the src is
2317 // from the RHS interval, we can use its value #.
2318 if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
2321 // Figure out the value # from the RHS.
2322 LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
2323 assert(lr && "Cannot find live range");
2324 LHSValsDefinedFromRHS[VNI] = lr->valno;
2327 // Loop over the value numbers of the RHS, seeing if any are defined from
2329 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
2332 if (VNI->isUnused() || VNI->getCopy() == 0) // Src not defined by a copy?
2335 // DstReg is known to be a register in the RHS interval. If the src is
2336 // from the LHS interval, we can use its value #.
2337 if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
2340 // Figure out the value # from the LHS.
2341 LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
2342 assert(lr && "Cannot find live range");
2343 RHSValsDefinedFromLHS[VNI] = lr->valno;
2346 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
2347 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
2348 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
2350 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
2353 unsigned VN = VNI->id;
2354 if (LHSValNoAssignments[VN] >= 0 || VNI->isUnused())
2356 ComputeUltimateVN(VNI, NewVNInfo,
2357 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
2358 LHSValNoAssignments, RHSValNoAssignments);
2360 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
2363 unsigned VN = VNI->id;
2364 if (RHSValNoAssignments[VN] >= 0 || VNI->isUnused())
2366 // If this value number isn't a copy from the LHS, it's a new number.
2367 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
2368 NewVNInfo.push_back(VNI);
2369 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
2373 ComputeUltimateVN(VNI, NewVNInfo,
2374 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
2375 RHSValNoAssignments, LHSValNoAssignments);
2379 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
2380 // interval lists to see if these intervals are coalescable.
2381 LiveInterval::const_iterator I = LHS.begin();
2382 LiveInterval::const_iterator IE = LHS.end();
2383 LiveInterval::const_iterator J = RHS.begin();
2384 LiveInterval::const_iterator JE = RHS.end();
2386 // Skip ahead until the first place of potential sharing.
2387 if (I->start < J->start) {
2388 I = std::upper_bound(I, IE, J->start);
2389 if (I != LHS.begin()) --I;
2390 } else if (J->start < I->start) {
2391 J = std::upper_bound(J, JE, I->start);
2392 if (J != RHS.begin()) --J;
2396 // Determine if these two live ranges overlap.
2398 if (I->start < J->start) {
2399 Overlaps = I->end > J->start;
2401 Overlaps = J->end > I->start;
2404 // If so, check value # info to determine if they are really different.
2406 // If the live range overlap will map to the same value number in the
2407 // result liverange, we can still coalesce them. If not, we can't.
2408 if (LHSValNoAssignments[I->valno->id] !=
2409 RHSValNoAssignments[J->valno->id])
2411 // If it's re-defined by an early clobber somewhere in the live range,
2412 // then conservatively abort coalescing.
2413 if (NewVNInfo[LHSValNoAssignments[I->valno->id]]->hasRedefByEC())
2417 if (I->end < J->end) {
2426 // Update kill info. Some live ranges are extended due to copy coalescing.
2427 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
2428 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
2429 VNInfo *VNI = I->first;
2430 unsigned LHSValID = LHSValNoAssignments[VNI->id];
2431 NewVNInfo[LHSValID]->removeKill(VNI->def);
2432 if (VNI->hasPHIKill())
2433 NewVNInfo[LHSValID]->setHasPHIKill(true);
2434 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
2437 // Update kill info. Some live ranges are extended due to copy coalescing.
2438 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
2439 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
2440 VNInfo *VNI = I->first;
2441 unsigned RHSValID = RHSValNoAssignments[VNI->id];
2442 NewVNInfo[RHSValID]->removeKill(VNI->def);
2443 if (VNI->hasPHIKill())
2444 NewVNInfo[RHSValID]->setHasPHIKill(true);
2445 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
2448 // If we get here, we know that we can coalesce the live ranges. Ask the
2449 // intervals to coalesce themselves now.
2450 if ((RHS.ranges.size() > LHS.ranges.size() &&
2451 TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
2452 TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
2453 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo,
2457 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,
2465 // DepthMBBCompare - Comparison predicate that sort first based on the loop
2466 // depth of the basic block (the unsigned), and then on the MBB number.
2467 struct DepthMBBCompare {
2468 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
2469 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
2470 // Deeper loops first
2471 if (LHS.first != RHS.first)
2472 return LHS.first > RHS.first;
2474 // Prefer blocks that are more connected in the CFG. This takes care of
2475 // the most difficult copies first while intervals are short.
2476 unsigned cl = LHS.second->pred_size() + LHS.second->succ_size();
2477 unsigned cr = RHS.second->pred_size() + RHS.second->succ_size();
2481 // As a last resort, sort by block number.
2482 return LHS.second->getNumber() < RHS.second->getNumber();
2487 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
2488 std::vector<CopyRec> &TryAgain) {
2489 DEBUG(dbgs() << MBB->getName() << ":\n");
2491 std::vector<CopyRec> VirtCopies;
2492 std::vector<CopyRec> PhysCopies;
2493 std::vector<CopyRec> ImpDefCopies;
2494 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
2496 MachineInstr *Inst = MII++;
2498 // If this isn't a copy nor a extract_subreg, we can't join intervals.
2499 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2500 bool isInsUndef = false;
2501 if (Inst->isExtractSubreg()) {
2502 DstReg = Inst->getOperand(0).getReg();
2503 SrcReg = Inst->getOperand(1).getReg();
2504 } else if (Inst->isInsertSubreg()) {
2505 DstReg = Inst->getOperand(0).getReg();
2506 SrcReg = Inst->getOperand(2).getReg();
2507 if (Inst->getOperand(1).isUndef())
2509 } else if (Inst->isInsertSubreg() || Inst->isSubregToReg()) {
2510 DstReg = Inst->getOperand(0).getReg();
2511 SrcReg = Inst->getOperand(2).getReg();
2512 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
2515 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
2516 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
2518 (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty()))
2519 ImpDefCopies.push_back(CopyRec(Inst, 0));
2520 else if (SrcIsPhys || DstIsPhys)
2521 PhysCopies.push_back(CopyRec(Inst, 0));
2523 VirtCopies.push_back(CopyRec(Inst, 0));
2526 // Try coalescing implicit copies and insert_subreg <undef> first,
2527 // followed by copies to / from physical registers, then finally copies
2528 // from virtual registers to virtual registers.
2529 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
2530 CopyRec &TheCopy = ImpDefCopies[i];
2532 if (!JoinCopy(TheCopy, Again))
2534 TryAgain.push_back(TheCopy);
2536 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
2537 CopyRec &TheCopy = PhysCopies[i];
2539 if (!JoinCopy(TheCopy, Again))
2541 TryAgain.push_back(TheCopy);
2543 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
2544 CopyRec &TheCopy = VirtCopies[i];
2546 if (!JoinCopy(TheCopy, Again))
2548 TryAgain.push_back(TheCopy);
2552 void SimpleRegisterCoalescing::joinIntervals() {
2553 DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
2555 std::vector<CopyRec> TryAgainList;
2556 if (loopInfo->empty()) {
2557 // If there are no loops in the function, join intervals in function order.
2558 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
2560 CopyCoalesceInMBB(I, TryAgainList);
2562 // Otherwise, join intervals in inner loops before other intervals.
2563 // Unfortunately we can't just iterate over loop hierarchy here because
2564 // there may be more MBB's than BB's. Collect MBB's for sorting.
2566 // Join intervals in the function prolog first. We want to join physical
2567 // registers with virtual registers before the intervals got too long.
2568 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
2569 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
2570 MachineBasicBlock *MBB = I;
2571 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
2574 // Sort by loop depth.
2575 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
2577 // Finally, join intervals in loop nest order.
2578 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
2579 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
2582 // Joining intervals can allow other intervals to be joined. Iteratively join
2583 // until we make no progress.
2584 bool ProgressMade = true;
2585 while (ProgressMade) {
2586 ProgressMade = false;
2588 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
2589 CopyRec &TheCopy = TryAgainList[i];
2594 bool Success = JoinCopy(TheCopy, Again);
2595 if (Success || !Again) {
2596 TheCopy.MI = 0; // Mark this one as done.
2597 ProgressMade = true;
2603 /// Return true if the two specified registers belong to different register
2604 /// classes. The registers may be either phys or virt regs.
2606 SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
2607 unsigned RegB) const {
2608 // Get the register classes for the first reg.
2609 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
2610 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
2611 "Shouldn't consider two physregs!");
2612 return !mri_->getRegClass(RegB)->contains(RegA);
2615 // Compare against the regclass for the second reg.
2616 const TargetRegisterClass *RegClassA = mri_->getRegClass(RegA);
2617 if (TargetRegisterInfo::isVirtualRegister(RegB)) {
2618 const TargetRegisterClass *RegClassB = mri_->getRegClass(RegB);
2619 return RegClassA != RegClassB;
2621 return !RegClassA->contains(RegB);
2624 /// lastRegisterUse - Returns the last (non-debug) use of the specific register
2625 /// between cycles Start and End or NULL if there are no uses.
2627 SimpleRegisterCoalescing::lastRegisterUse(SlotIndex Start,
2630 SlotIndex &UseIdx) const{
2631 UseIdx = SlotIndex();
2632 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2633 MachineOperand *LastUse = NULL;
2634 for (MachineRegisterInfo::use_nodbg_iterator I = mri_->use_nodbg_begin(Reg),
2635 E = mri_->use_nodbg_end(); I != E; ++I) {
2636 MachineOperand &Use = I.getOperand();
2637 MachineInstr *UseMI = Use.getParent();
2638 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2639 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2641 // Ignore identity copies.
2643 SlotIndex Idx = li_->getInstructionIndex(UseMI);
2644 // FIXME: Should this be Idx != UseIdx? SlotIndex() will return something
2645 // that compares higher than any other interval.
2646 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
2648 UseIdx = Idx.getUseIndex();
2654 SlotIndex s = Start;
2655 SlotIndex e = End.getPrevSlot().getBaseIndex();
2657 // Skip deleted instructions
2658 MachineInstr *MI = li_->getInstructionFromIndex(e);
2659 while (e != SlotIndex() && e.getPrevIndex() >= s && !MI) {
2660 e = e.getPrevIndex();
2661 MI = li_->getInstructionFromIndex(e);
2663 if (e < s || MI == NULL)
2666 // Ignore identity copies.
2667 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2668 if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
2670 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
2671 MachineOperand &Use = MI->getOperand(i);
2672 if (Use.isReg() && Use.isUse() && Use.getReg() &&
2673 tri_->regsOverlap(Use.getReg(), Reg)) {
2674 UseIdx = e.getUseIndex();
2679 e = e.getPrevIndex();
2685 void SimpleRegisterCoalescing::releaseMemory() {
2686 JoinedCopies.clear();
2687 ReMatCopies.clear();
2691 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
2693 mri_ = &fn.getRegInfo();
2694 tm_ = &fn.getTarget();
2695 tri_ = tm_->getRegisterInfo();
2696 tii_ = tm_->getInstrInfo();
2697 li_ = &getAnalysis<LiveIntervals>();
2698 AA = &getAnalysis<AliasAnalysis>();
2699 loopInfo = &getAnalysis<MachineLoopInfo>();
2701 DEBUG(dbgs() << "********** SIMPLE REGISTER COALESCING **********\n"
2702 << "********** Function: "
2703 << ((Value*)mf_->getFunction())->getName() << '\n');
2705 allocatableRegs_ = tri_->getAllocatableSet(fn);
2706 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
2707 E = tri_->regclass_end(); I != E; ++I)
2708 allocatableRCRegs_.insert(std::make_pair(*I,
2709 tri_->getAllocatableSet(fn, *I)));
2711 // Join (coalesce) intervals if requested.
2712 if (EnableJoining) {
2715 dbgs() << "********** INTERVALS POST JOINING **********\n";
2716 for (LiveIntervals::iterator I = li_->begin(), E = li_->end();
2718 I->second->print(dbgs(), tri_);
2724 // Perform a final pass over the instructions and compute spill weights
2725 // and remove identity moves.
2726 SmallVector<unsigned, 4> DeadDefs;
2727 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
2728 mbbi != mbbe; ++mbbi) {
2729 MachineBasicBlock* mbb = mbbi;
2730 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
2732 MachineInstr *MI = mii;
2733 unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
2734 if (JoinedCopies.count(MI)) {
2735 // Delete all coalesced copies.
2736 bool DoDelete = true;
2737 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
2738 assert((MI->isExtractSubreg() || MI->isInsertSubreg() ||
2739 MI->isSubregToReg()) && "Unrecognized copy instruction");
2740 DstReg = MI->getOperand(0).getReg();
2741 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2742 // Do not delete extract_subreg, insert_subreg of physical
2743 // registers unless the definition is dead. e.g.
2744 // %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
2745 // or else the scavenger may complain. LowerSubregs will
2746 // delete them later.
2749 if (MI->allDefsAreDead()) {
2750 LiveInterval &li = li_->getInterval(DstReg);
2751 if (!ShortenDeadCopySrcLiveRange(li, MI))
2752 ShortenDeadCopyLiveRange(li, MI);
2756 mii = llvm::next(mii);
2758 li_->RemoveMachineInstrFromMaps(MI);
2759 mii = mbbi->erase(mii);
2765 // Now check if this is a remat'ed def instruction which is now dead.
2766 if (ReMatDefs.count(MI)) {
2768 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2769 const MachineOperand &MO = MI->getOperand(i);
2772 unsigned Reg = MO.getReg();
2775 if (TargetRegisterInfo::isVirtualRegister(Reg))
2776 DeadDefs.push_back(Reg);
2779 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
2780 !mri_->use_nodbg_empty(Reg)) {
2786 while (!DeadDefs.empty()) {
2787 unsigned DeadDef = DeadDefs.back();
2788 DeadDefs.pop_back();
2789 RemoveDeadDef(li_->getInterval(DeadDef), MI);
2791 li_->RemoveMachineInstrFromMaps(mii);
2792 mii = mbbi->erase(mii);
2798 // If the move will be an identity move delete it
2799 bool isMove= tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
2800 if (isMove && SrcReg == DstReg) {
2801 if (li_->hasInterval(SrcReg)) {
2802 LiveInterval &RegInt = li_->getInterval(SrcReg);
2803 // If def of this move instruction is dead, remove its live range
2804 // from the dstination register's live interval.
2805 if (MI->registerDefIsDead(DstReg)) {
2806 if (!ShortenDeadCopySrcLiveRange(RegInt, MI))
2807 ShortenDeadCopyLiveRange(RegInt, MI);
2810 li_->RemoveMachineInstrFromMaps(MI);
2811 mii = mbbi->erase(mii);
2818 // Check for now unnecessary kill flags.
2819 if (li_->isNotInMIMap(MI)) continue;
2820 SlotIndex UseIdx = li_->getInstructionIndex(MI).getUseIndex();
2821 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2822 MachineOperand &MO = MI->getOperand(i);
2823 if (!MO.isReg() || !MO.isKill()) continue;
2824 unsigned reg = MO.getReg();
2825 if (!reg || !li_->hasInterval(reg)) continue;
2826 LiveInterval &LI = li_->getInterval(reg);
2827 const LiveRange *LR = LI.getLiveRangeContaining(UseIdx);
2829 (!LR->valno->isKill(UseIdx.getDefIndex()) &&
2830 LR->valno->def != UseIdx.getDefIndex()))
2831 MO.setIsKill(false);
2840 /// print - Implement the dump method.
2841 void SimpleRegisterCoalescing::print(raw_ostream &O, const Module* m) const {
2845 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
2846 return new SimpleRegisterCoalescing();
2849 // Make sure that anything that uses RegisterCoalescer pulls in this file...
2850 DEFINING_FILE_FOR(SimpleRegisterCoalescing)