1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/CodeGen/LiveVariables.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineLoopInfo.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/RegisterCoalescer.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/ADT/STLExtras.h"
38 STATISTIC(numJoins , "Number of interval joins performed");
39 STATISTIC(numCommutes , "Number of instruction commuting performed");
40 STATISTIC(numExtends , "Number of copies extended");
41 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
42 STATISTIC(numAborts , "Number of times interval joining aborted");
44 char SimpleRegisterCoalescing::ID = 0;
47 EnableJoining("join-liveintervals",
48 cl::desc("Coalesce copies (default=true)"),
52 NewHeuristic("new-coalescer-heuristic",
53 cl::desc("Use new coalescer heuristic"),
56 RegisterPass<SimpleRegisterCoalescing>
57 X("simple-register-coalescing", "Simple Register Coalescing");
59 // Declare that we implement the RegisterCoalescer interface
60 RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
63 const PassInfo *llvm::SimpleRegisterCoalescingID = X.getPassInfo();
65 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
66 AU.addPreserved<LiveIntervals>();
67 AU.addPreserved<MachineLoopInfo>();
68 AU.addPreservedID(MachineDominatorsID);
69 AU.addPreservedID(PHIEliminationID);
70 AU.addPreservedID(TwoAddressInstructionPassID);
71 AU.addRequired<LiveVariables>();
72 AU.addRequired<LiveIntervals>();
73 AU.addRequired<MachineLoopInfo>();
74 MachineFunctionPass::getAnalysisUsage(AU);
77 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
78 /// being the source and IntB being the dest, thus this defines a value number
79 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
80 /// see if we can merge these two pieces of B into a single value number,
81 /// eliminating a copy. For example:
85 /// B1 = A3 <- this copy
87 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
88 /// value number to be replaced with B0 (which simplifies the B liveinterval).
90 /// This returns true if an interval was modified.
92 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
94 MachineInstr *CopyMI) {
95 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
97 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
99 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
100 if (BLR == IntB.end()) // Should never happen!
102 VNInfo *BValNo = BLR->valno;
104 // Get the location that B is defined at. Two options: either this value has
105 // an unknown definition point or it is defined at CopyIdx. If unknown, we
107 if (!BValNo->copy) return false;
108 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
110 // AValNo is the value number in A that defines the copy, A3 in the example.
111 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
112 if (ALR == IntA.end()) // Should never happen!
114 VNInfo *AValNo = ALR->valno;
116 // If AValNo is defined as a copy from IntB, we can potentially process this.
117 // Get the instruction that defines this value number.
118 unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
119 if (!SrcReg) return false; // Not defined by a copy.
121 // If the value number is not defined by a copy instruction, ignore it.
123 // If the source register comes from an interval other than IntB, we can't
125 if (SrcReg != IntB.reg) return false;
127 // Get the LiveRange in IntB that this value number starts with.
128 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
129 if (ValLR == IntB.end()) // Should never happen!
132 // Make sure that the end of the live range is inside the same block as
134 MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
136 ValLREndInst->getParent() != CopyMI->getParent()) return false;
138 // Okay, we now know that ValLR ends in the same block that the CopyMI
139 // live-range starts. If there are no intervening live ranges between them in
140 // IntB, we can merge them.
141 if (ValLR+1 != BLR) return false;
143 // If a live interval is a physical register, conservatively check if any
144 // of its sub-registers is overlapping the live interval of the virtual
145 // register. If so, do not coalesce.
146 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
147 *tri_->getSubRegisters(IntB.reg)) {
148 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
149 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
150 DOUT << "Interfere with sub-register ";
151 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
156 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
158 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
159 // We are about to delete CopyMI, so need to remove it as the 'instruction
160 // that defines this value #'. Update the the valnum with the new defining
162 BValNo->def = FillerStart;
165 // Okay, we can merge them. We need to insert a new liverange:
166 // [ValLR.end, BLR.begin) of either value number, then we merge the
167 // two value numbers.
168 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
170 // If the IntB live range is assigned to a physical register, and if that
171 // physreg has aliases,
172 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
173 // Update the liveintervals of sub-registers.
174 for (const unsigned *AS = tri_->getSubRegisters(IntB.reg); *AS; ++AS) {
175 LiveInterval &AliasLI = li_->getInterval(*AS);
176 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
177 AliasLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator())));
181 // Okay, merge "B1" into the same value number as "B0".
182 if (BValNo != ValLR->valno)
183 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
184 DOUT << " result = "; IntB.print(DOUT, tri_);
187 // If the source instruction was killing the source register before the
188 // merge, unset the isKill marker given the live range has been extended.
189 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
191 ValLREndInst->getOperand(UIdx).setIsKill(false);
197 /// HasOtherReachingDefs - Return true if there are definitions of IntB
198 /// other than BValNo val# that can reach uses of AValno val# of IntA.
199 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
203 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
205 if (AI->valno != AValNo) continue;
206 LiveInterval::Ranges::iterator BI =
207 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
208 if (BI != IntB.ranges.begin())
210 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
211 if (BI->valno == BValNo)
213 if (BI->start <= AI->start && BI->end > AI->start)
215 if (BI->start > AI->start && BI->start < AI->end)
222 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA
223 /// being the source and IntB being the dest, thus this defines a value number
224 /// in IntB. If the source value number (in IntA) is defined by a commutable
225 /// instruction and its other operand is coalesced to the copy dest register,
226 /// see if we can transform the copy into a noop by commuting the definition. For
229 /// A3 = op A2 B0<kill>
231 /// B1 = A3 <- this copy
233 /// = op A3 <- more uses
237 /// B2 = op B0 A2<kill>
239 /// B1 = B2 <- now an identify copy
241 /// = op B2 <- more uses
243 /// This returns true if an interval was modified.
245 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
247 MachineInstr *CopyMI) {
248 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
250 // FIXME: For now, only eliminate the copy by commuting its def when the
251 // source register is a virtual register. We want to guard against cases
252 // where the copy is a back edge copy and commuting the def lengthen the
253 // live interval of the source register to the entire loop.
254 if (TargetRegisterInfo::isPhysicalRegister(IntA.reg))
257 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
258 // the example above.
259 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
260 if (BLR == IntB.end()) // Should never happen!
262 VNInfo *BValNo = BLR->valno;
264 // Get the location that B is defined at. Two options: either this value has
265 // an unknown definition point or it is defined at CopyIdx. If unknown, we
267 if (!BValNo->copy) return false;
268 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
270 // AValNo is the value number in A that defines the copy, A3 in the example.
271 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
272 if (ALR == IntA.end()) // Should never happen!
274 VNInfo *AValNo = ALR->valno;
275 // If other defs can reach uses of this def, then it's not safe to perform
277 if (AValNo->def == ~0U || AValNo->def == ~1U || AValNo->hasPHIKill)
279 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
280 const TargetInstrDesc &TID = DefMI->getDesc();
282 if (!TID.isCommutable() ||
283 !tii_->CommuteChangesDestination(DefMI, NewDstIdx))
286 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
287 unsigned NewReg = NewDstMO.getReg();
288 if (NewReg != IntB.reg || !NewDstMO.isKill())
291 // Make sure there are no other definitions of IntB that would reach the
292 // uses which the new definition can reach.
293 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
296 // If some of the uses of IntA.reg is already coalesced away, return false.
297 // It's not possible to determine whether it's safe to perform the coalescing.
298 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
299 UE = mri_->use_end(); UI != UE; ++UI) {
300 MachineInstr *UseMI = &*UI;
301 unsigned UseIdx = li_->getInstructionIndex(UseMI);
302 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
303 if (ULR == IntA.end())
305 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
309 // At this point we have decided that it is legal to do this
310 // transformation. Start by commuting the instruction.
311 MachineBasicBlock *MBB = DefMI->getParent();
312 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
315 if (NewMI != DefMI) {
316 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
317 MBB->insert(DefMI, NewMI);
320 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
321 NewMI->getOperand(OpIdx).setIsKill();
323 bool BHasPHIKill = BValNo->hasPHIKill;
324 SmallVector<VNInfo*, 4> BDeadValNos;
325 SmallVector<unsigned, 4> BKills;
326 std::map<unsigned, unsigned> BExtend;
328 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
337 // then do not add kills of A to the newly created B interval.
338 bool Extended = BLR->end > ALR->end && ALR->end != ALR->start;
340 BExtend[ALR->end] = BLR->end;
342 // Update uses of IntA of the specific Val# with IntB.
343 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
344 UE = mri_->use_end(); UI != UE;) {
345 MachineOperand &UseMO = UI.getOperand();
346 MachineInstr *UseMI = &*UI;
348 if (JoinedCopies.count(UseMI))
350 unsigned UseIdx = li_->getInstructionIndex(UseMI);
351 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
352 if (ULR == IntA.end() || ULR->valno != AValNo)
354 UseMO.setReg(NewReg);
357 if (UseMO.isKill()) {
359 UseMO.setIsKill(false);
361 BKills.push_back(li_->getUseIndex(UseIdx)+1);
363 unsigned SrcReg, DstReg;
364 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg))
366 if (DstReg == IntB.reg) {
367 // This copy will become a noop. If it's defining a new val#,
368 // remove that val# as well. However this live range is being
369 // extended to the end of the existing live range defined by the copy.
370 unsigned DefIdx = li_->getDefIndex(UseIdx);
371 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
372 BHasPHIKill |= DLR->valno->hasPHIKill;
373 assert(DLR->valno->def == DefIdx);
374 BDeadValNos.push_back(DLR->valno);
375 BExtend[DLR->start] = DLR->end;
376 JoinedCopies.insert(UseMI);
377 // If this is a kill but it's going to be removed, the last use
378 // of the same val# is the new kill.
384 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
385 // simply extend BLR if CopyMI doesn't end the range.
386 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
388 IntB.removeValNo(BValNo);
389 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i)
390 IntB.removeValNo(BDeadValNos[i]);
391 VNInfo *ValNo = IntB.getNextValue(AValNo->def, 0, li_->getVNInfoAllocator());
392 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
394 if (AI->valno != AValNo) continue;
395 unsigned End = AI->end;
396 std::map<unsigned, unsigned>::iterator EI = BExtend.find(End);
397 if (EI != BExtend.end())
399 IntB.addRange(LiveRange(AI->start, End, ValNo));
401 IntB.addKills(ValNo, BKills);
402 ValNo->hasPHIKill = BHasPHIKill;
404 DOUT << " result = "; IntB.print(DOUT, tri_);
407 DOUT << "\nShortening: "; IntA.print(DOUT, tri_);
408 IntA.removeValNo(AValNo);
409 DOUT << " result = "; IntA.print(DOUT, tri_);
416 /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
418 bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
419 unsigned DstReg) const {
420 MachineBasicBlock *MBB = CopyMI->getParent();
421 const MachineLoop *L = loopInfo->getLoopFor(MBB);
424 if (MBB != L->getLoopLatch())
427 LiveInterval &LI = li_->getInterval(DstReg);
428 unsigned DefIdx = li_->getInstructionIndex(CopyMI);
429 LiveInterval::const_iterator DstLR =
430 LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx));
431 if (DstLR == LI.end())
433 unsigned KillIdx = li_->getInstructionIndex(&MBB->back()) + InstrSlots::NUM;
434 if (DstLR->valno->kills.size() == 1 &&
435 DstLR->valno->kills[0] == KillIdx && DstLR->valno->hasPHIKill)
440 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
441 /// update the subregister number if it is not zero. If DstReg is a
442 /// physical register and the existing subregister number of the def / use
443 /// being updated is not zero, make sure to set it to the correct physical
446 SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
448 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
449 if (DstIsPhys && SubIdx) {
450 // Figure out the real physical register we are updating with.
451 DstReg = tri_->getSubReg(DstReg, SubIdx);
455 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
456 E = mri_->reg_end(); I != E; ) {
457 MachineOperand &O = I.getOperand();
458 MachineInstr *UseMI = &*I;
460 unsigned OldSubIdx = O.getSubReg();
462 unsigned UseDstReg = DstReg;
464 UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
468 // Sub-register indexes goes from small to large. e.g.
469 // RAX: 1 -> AL, 2 -> AX, 3 -> EAX
470 // EAX: 1 -> AL, 2 -> AX
471 // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose
472 // sub-register 2 is also AX.
473 if (SubIdx && OldSubIdx && SubIdx != OldSubIdx)
474 assert(OldSubIdx < SubIdx && "Conflicting sub-register index!");
477 // Remove would-be duplicated kill marker.
478 if (O.isKill() && UseMI->killsRegister(DstReg))
485 /// RemoveDeadImpDef - Remove implicit_def instructions which are "re-defining"
486 /// registers due to insert_subreg coalescing. e.g.
488 /// r1025 = implicit_def
489 /// r1025 = insert_subreg r1025, r1024
493 /// r1025 = implicit_def
494 /// r1025 = insert_subreg r1025, r1025
497 SimpleRegisterCoalescing::RemoveDeadImpDef(unsigned Reg, LiveInterval &LI) {
498 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
499 E = mri_->reg_end(); I != E; ) {
500 MachineOperand &O = I.getOperand();
501 MachineInstr *DefMI = &*I;
505 if (DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
507 if (!LI.liveBeforeAndAt(li_->getInstructionIndex(DefMI)))
509 li_->RemoveMachineInstrFromMaps(DefMI);
510 DefMI->eraseFromParent();
514 /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
515 /// due to live range lengthening as the result of coalescing.
516 void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg,
518 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
519 UE = mri_->use_end(); UI != UE; ++UI) {
520 MachineOperand &UseMO = UI.getOperand();
521 if (UseMO.isKill()) {
522 MachineInstr *UseMI = UseMO.getParent();
524 if (!tii_->isMoveInstr(*UseMI, SReg, DReg))
526 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
527 if (JoinedCopies.count(UseMI))
529 const LiveRange *UI = LI.getLiveRangeContaining(UseIdx);
530 if (!LI.isKill(UI->valno, UseIdx+1))
531 UseMO.setIsKill(false);
536 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
537 /// from a physical register live interval as well as from the live intervals
538 /// of its sub-registers.
539 static void removeRange(LiveInterval &li, unsigned Start, unsigned End,
540 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
541 li.removeRange(Start, End, true);
542 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
543 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
544 if (!li_->hasInterval(*SR))
546 LiveInterval &sli = li_->getInterval(*SR);
547 unsigned RemoveEnd = Start;
548 while (RemoveEnd != End) {
549 LiveInterval::iterator LR = sli.FindLiveRangeContaining(Start);
552 RemoveEnd = (LR->end < End) ? LR->end : End;
553 sli.removeRange(Start, RemoveEnd, true);
560 /// removeIntervalIfEmpty - Check if the live interval of a physical register
561 /// is empty, if so remove it and also remove the empty intervals of its
562 /// sub-registers. Return true if live interval is removed.
563 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
564 const TargetRegisterInfo *tri_) {
566 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
567 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
568 if (!li_->hasInterval(*SR))
570 LiveInterval &sli = li_->getInterval(*SR);
572 li_->removeInterval(*SR);
574 li_->removeInterval(li.reg);
580 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
581 /// Return true if live interval is removed.
582 bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
583 MachineInstr *CopyMI) {
584 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
585 LiveInterval::iterator MLR =
586 li.FindLiveRangeContaining(li_->getDefIndex(CopyIdx));
588 return false; // Already removed by ShortenDeadCopySrcLiveRange.
589 unsigned RemoveStart = MLR->start;
590 unsigned RemoveEnd = MLR->end;
591 // Remove the liverange that's defined by this.
592 if (RemoveEnd == li_->getDefIndex(CopyIdx)+1) {
593 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
594 return removeIntervalIfEmpty(li, li_, tri_);
599 /// PropagateDeadness - Propagate the dead marker to the instruction which
600 /// defines the val#.
601 static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
602 unsigned &LRStart, LiveIntervals *li_,
603 const TargetRegisterInfo* tri_) {
604 MachineInstr *DefMI =
605 li_->getInstructionFromIndex(li_->getDefIndex(LRStart));
606 if (DefMI && DefMI != CopyMI) {
607 int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false, tri_);
609 DefMI->getOperand(DeadIdx).setIsDead();
610 // A dead def should have a single cycle interval.
616 /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply
617 /// fallthoughs to SuccMBB.
618 static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
619 MachineBasicBlock *SuccMBB,
620 const TargetInstrInfo *tii_) {
623 MachineBasicBlock *TBB = 0, *FBB = 0;
624 std::vector<MachineOperand> Cond;
625 return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
626 MBB->isSuccessor(SuccMBB);
629 /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially
630 /// extended by a dead copy. Mark the last use (if any) of the val# as kill as
631 /// ends the live range there. If there isn't another use, then this live range
632 /// is dead. Return true if live interval is removed.
634 SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
635 MachineInstr *CopyMI) {
636 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
638 // FIXME: special case: function live in. It can be a general case if the
639 // first instruction index starts at > 0 value.
640 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
641 // Live-in to the function but dead. Remove it from entry live-in set.
642 mf_->begin()->removeLiveIn(li.reg);
643 const LiveRange *LR = li.getLiveRangeContaining(CopyIdx);
644 removeRange(li, LR->start, LR->end, li_, tri_);
645 return removeIntervalIfEmpty(li, li_, tri_);
648 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx-1);
650 // Livein but defined by a phi.
653 unsigned RemoveStart = LR->start;
654 unsigned RemoveEnd = li_->getDefIndex(CopyIdx)+1;
655 if (LR->end > RemoveEnd)
656 // More uses past this copy? Nothing to do.
659 MachineBasicBlock *CopyMBB = CopyMI->getParent();
660 unsigned MBBStart = li_->getMBBStartIdx(CopyMBB);
662 MachineOperand *LastUse = lastRegisterUse(LR->start, CopyIdx-1, li.reg,
665 MachineInstr *LastUseMI = LastUse->getParent();
666 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
673 // r1025<dead> = r1024<kill>
674 if (MBBStart < LR->end)
675 removeRange(li, MBBStart, LR->end, li_, tri_);
679 // There are uses before the copy, just shorten the live range to the end
681 LastUse->setIsKill();
682 removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_);
683 unsigned SrcReg, DstReg;
684 if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg) &&
686 // Last use is itself an identity code.
687 int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_);
688 LastUseMI->getOperand(DeadIdx).setIsDead();
694 if (LR->start <= MBBStart && LR->end > MBBStart) {
695 if (LR->start == 0) {
696 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
697 // Live-in to the function but dead. Remove it from entry live-in set.
698 mf_->begin()->removeLiveIn(li.reg);
700 // FIXME: Shorten intervals in BBs that reaches this BB.
703 if (LR->valno->def == RemoveStart)
704 // If the def MI defines the val#, propagate the dead marker.
705 PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
707 removeRange(li, RemoveStart, LR->end, li_, tri_);
708 return removeIntervalIfEmpty(li, li_, tri_);
711 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
712 /// from an implicit def to another register can be coalesced away.
713 bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI,
715 LiveInterval &ImpLi) const{
716 if (!CopyMI->killsRegister(ImpLi.reg))
718 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
719 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx);
722 if (LR->valno->hasPHIKill)
724 if (LR->valno->def != CopyIdx)
726 // Make sure all of val# uses are copies.
727 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(li.reg),
728 UE = mri_->use_end(); UI != UE;) {
729 MachineInstr *UseMI = &*UI;
731 if (JoinedCopies.count(UseMI))
733 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
734 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
735 if (ULR == li.end() || ULR->valno != LR->valno)
737 // If the use is not a use, then it's not safe to coalesce the move.
738 unsigned SrcReg, DstReg;
739 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg)) {
740 if (UseMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG &&
741 UseMI->getOperand(1).getReg() == li.reg)
750 /// RemoveCopiesFromValNo - The specified value# is defined by an implicit
751 /// def and it is being removed. Turn all copies from this value# into
752 /// identity copies so they will be removed.
753 void SimpleRegisterCoalescing::RemoveCopiesFromValNo(LiveInterval &li,
755 MachineInstr *ImpDef = NULL;
756 MachineOperand *LastUse = NULL;
757 unsigned LastUseIdx = li_->getUseIndex(VNI->def);
758 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg),
759 RE = mri_->reg_end(); RI != RE;) {
760 MachineOperand *MO = &RI.getOperand();
761 MachineInstr *MI = &*RI;
764 if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
765 assert(!ImpDef && "Multiple implicit_def defining same register?");
770 if (JoinedCopies.count(MI))
772 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(MI));
773 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
774 if (ULR == li.end() || ULR->valno != VNI)
776 // If the use is a copy, turn it into an identity copy.
777 unsigned SrcReg, DstReg;
778 if (tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == li.reg) {
779 // Each use MI may have multiple uses of this register. Change them all.
780 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
781 MachineOperand &MO = MI->getOperand(i);
782 if (MO.isReg() && MO.getReg() == li.reg)
785 JoinedCopies.insert(MI);
786 } else if (UseIdx > LastUseIdx) {
792 LastUse->setIsKill();
794 // Remove dead implicit_def.
795 li_->RemoveMachineInstrFromMaps(ImpDef);
796 ImpDef->eraseFromParent();
800 static unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
801 const TargetRegisterClass *RC,
802 const TargetRegisterInfo* TRI) {
803 for (const unsigned *SRs = TRI->getSuperRegisters(Reg);
804 unsigned SR = *SRs; ++SRs)
805 if (Reg == TRI->getSubReg(SR, SubIdx) && RC->contains(SR))
810 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
811 /// which are the src/dst of the copy instruction CopyMI. This returns true
812 /// if the copy was successfully coalesced away. If it is not currently
813 /// possible to coalesce this interval, but it may be possible if other
814 /// things get coalesced, then it returns true by reference in 'Again'.
815 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
816 MachineInstr *CopyMI = TheCopy.MI;
819 if (JoinedCopies.count(CopyMI))
820 return false; // Already done.
822 DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
826 bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
827 bool isInsSubReg = CopyMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG;
830 DstReg = CopyMI->getOperand(0).getReg();
831 SrcReg = CopyMI->getOperand(1).getReg();
832 } else if (isInsSubReg) {
833 if (CopyMI->getOperand(2).getSubReg()) {
834 DOUT << "\tSource of insert_subreg is already coalesced "
835 << "to another register.\n";
836 return false; // Not coalescable.
838 DstReg = CopyMI->getOperand(0).getReg();
839 SrcReg = CopyMI->getOperand(2).getReg();
840 } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
841 assert(0 && "Unrecognized copy instruction!");
845 // If they are already joined we continue.
846 if (SrcReg == DstReg) {
847 DOUT << "\tCopy already coalesced.\n";
848 return false; // Not coalescable.
851 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
852 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
854 // If they are both physical registers, we cannot join them.
855 if (SrcIsPhys && DstIsPhys) {
856 DOUT << "\tCan not coalesce physregs.\n";
857 return false; // Not coalescable.
860 // We only join virtual registers with allocatable physical registers.
861 if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
862 DOUT << "\tSrc reg is unallocatable physreg.\n";
863 return false; // Not coalescable.
865 if (DstIsPhys && !allocatableRegs_[DstReg]) {
866 DOUT << "\tDst reg is unallocatable physreg.\n";
867 return false; // Not coalescable.
870 unsigned RealDstReg = 0;
871 unsigned RealSrcReg = 0;
872 if (isExtSubReg || isInsSubReg) {
873 SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm();
874 if (SrcIsPhys && isExtSubReg) {
875 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
876 // coalesced with AX.
877 unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
879 // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
880 // coalesced to a larger register so the subreg indices cancel out.
881 if (DstSubIdx != SubIdx) {
882 DOUT << "\t Sub-register indices mismatch.\n";
883 return false; // Not coalescable.
886 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
888 } else if (DstIsPhys && isInsSubReg) {
889 // EAX = INSERT_SUBREG EAX, r1024, 0
890 unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
892 // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
893 // coalesced to a larger register so the subreg indices cancel out.
894 if (SrcSubIdx != SubIdx) {
895 DOUT << "\t Sub-register indices mismatch.\n";
896 return false; // Not coalescable.
899 DstReg = tri_->getSubReg(DstReg, SubIdx);
901 } else if ((DstIsPhys && isExtSubReg) || (SrcIsPhys && isInsSubReg)) {
902 // If this is a extract_subreg where dst is a physical register, e.g.
903 // cl = EXTRACT_SUBREG reg1024, 1
904 // then create and update the actual physical register allocated to RHS.
906 // reg1024 = INSERT_SUBREG r1024, cl, 1
907 if (CopyMI->getOperand(1).getSubReg()) {
908 DOUT << "\tSrc of extract_ / insert_subreg already coalesced with reg"
909 << " of a super-class.\n";
910 return false; // Not coalescable.
912 const TargetRegisterClass *RC =
913 mri_->getRegClass(isExtSubReg ? SrcReg : DstReg);
915 RealDstReg = getMatchingSuperReg(DstReg, SubIdx, RC, tri_);
916 assert(RealDstReg && "Invalid extra_subreg instruction!");
918 RealSrcReg = getMatchingSuperReg(SrcReg, SubIdx, RC, tri_);
919 assert(RealSrcReg && "Invalid extra_subreg instruction!");
922 // For this type of EXTRACT_SUBREG, conservatively
923 // check if the live interval of the source register interfere with the
924 // actual super physical register we are trying to coalesce with.
925 unsigned PhysReg = isExtSubReg ? RealDstReg : RealSrcReg;
926 LiveInterval &RHS = li_->getInterval(isExtSubReg ? SrcReg : DstReg);
927 if (li_->hasInterval(PhysReg) &&
928 RHS.overlaps(li_->getInterval(PhysReg))) {
929 DOUT << "Interfere with register ";
930 DEBUG(li_->getInterval(PhysReg).print(DOUT, tri_));
931 return false; // Not coalescable
933 for (const unsigned* SR = tri_->getSubRegisters(PhysReg); *SR; ++SR)
934 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
935 DOUT << "Interfere with sub-register ";
936 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
937 return false; // Not coalescable
941 unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg()
942 : CopyMI->getOperand(2).getSubReg();
944 if (OldSubIdx == SubIdx)
945 // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been
946 // coalesced to a larger register so the subreg indices cancel out.
949 DOUT << "\t Sub-register indices mismatch.\n";
950 return false; // Not coalescable.
954 unsigned LargeReg = isExtSubReg ? SrcReg : DstReg;
955 unsigned SmallReg = isExtSubReg ? DstReg : SrcReg;
956 unsigned LargeRegSize =
957 li_->getInterval(LargeReg).getSize() / InstrSlots::NUM;
958 unsigned SmallRegSize =
959 li_->getInterval(SmallReg).getSize() / InstrSlots::NUM;
960 const TargetRegisterClass *RC = mri_->getRegClass(SmallReg);
961 unsigned Threshold = allocatableRCRegs_[RC].count();
962 // Be conservative. If both sides are virtual registers, do not coalesce
963 // if this will cause a high use density interval to target a smaller
965 if (SmallRegSize > Threshold || LargeRegSize > Threshold) {
966 LiveVariables::VarInfo &svi = lv_->getVarInfo(LargeReg);
967 LiveVariables::VarInfo &dvi = lv_->getVarInfo(SmallReg);
968 if ((float)dvi.NumUses / SmallRegSize <
969 (float)svi.NumUses / LargeRegSize) {
970 Again = true; // May be possible to coalesce later.
976 } else if (differingRegisterClasses(SrcReg, DstReg)) {
977 // FIXME: What if the resul of a EXTRACT_SUBREG is then coalesced
978 // with another? If it's the resulting destination register, then
979 // the subidx must be propagated to uses (but only those defined
980 // by the EXTRACT_SUBREG). If it's being coalesced into another
981 // register, it should be safe because register is assumed to have
982 // the register class of the super-register.
984 // If they are not of the same register class, we cannot join them.
985 DOUT << "\tSrc/Dest are different register classes.\n";
986 // Allow the coalescer to try again in case either side gets coalesced to
987 // a physical register that's compatible with the other side. e.g.
988 // r1024 = MOV32to32_ r1025
989 // but later r1024 is assigned EAX then r1025 may be coalesced with EAX.
990 Again = true; // May be possible to coalesce later.
994 LiveInterval &SrcInt = li_->getInterval(SrcReg);
995 LiveInterval &DstInt = li_->getInterval(DstReg);
996 assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
997 "Register mapping is horribly broken!");
999 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_);
1000 DOUT << " and "; DstInt.print(DOUT, tri_);
1003 // Check if it is necessary to propagate "isDead" property.
1004 if (!isExtSubReg && !isInsSubReg) {
1005 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
1006 bool isDead = mopd->isDead();
1008 // We need to be careful about coalescing a source physical register with a
1009 // virtual register. Once the coalescing is done, it cannot be broken and
1010 // these are not spillable! If the destination interval uses are far away,
1011 // think twice about coalescing them!
1012 if (!isDead && (SrcIsPhys || DstIsPhys)) {
1013 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
1014 unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
1015 unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
1016 const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
1017 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1018 if (TheCopy.isBackEdge)
1019 Threshold *= 2; // Favors back edge copies.
1021 // If the virtual register live interval is long but it has low use desity,
1022 // do not join them, instead mark the physical register as its allocation
1024 unsigned Length = JoinVInt.getSize() / InstrSlots::NUM;
1025 LiveVariables::VarInfo &vi = lv_->getVarInfo(JoinVReg);
1026 if (Length > Threshold &&
1027 (((float)vi.NumUses / Length) < (1.0 / Threshold))) {
1028 JoinVInt.preference = JoinPReg;
1030 DOUT << "\tMay tie down a physical register, abort!\n";
1031 Again = true; // May be possible to coalesce later.
1037 // Okay, attempt to join these two intervals. On failure, this returns false.
1038 // Otherwise, if one of the intervals being joined is a physreg, this method
1039 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1040 // been modified, so we can use this information below to update aliases.
1041 bool Swapped = false;
1042 // If SrcInt is implicitly defined, it's safe to coalesce.
1043 bool isEmpty = SrcInt.empty();
1044 if (isEmpty && !CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
1045 // Only coalesce an empty interval (defined by implicit_def) with
1046 // another interval which has a valno defined by the CopyMI and the CopyMI
1047 // is a kill of the implicit def.
1048 DOUT << "Not profitable!\n";
1052 if (!isEmpty && !JoinIntervals(DstInt, SrcInt, Swapped)) {
1053 // Coalescing failed.
1055 // If we can eliminate the copy without merging the live ranges, do so now.
1056 if (!isExtSubReg && !isInsSubReg &&
1057 (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
1058 RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
1059 JoinedCopies.insert(CopyMI);
1063 // Otherwise, we are unable to join the intervals.
1064 DOUT << "Interference!\n";
1065 Again = true; // May be possible to coalesce later.
1069 LiveInterval *ResSrcInt = &SrcInt;
1070 LiveInterval *ResDstInt = &DstInt;
1072 std::swap(SrcReg, DstReg);
1073 std::swap(ResSrcInt, ResDstInt);
1075 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1076 "LiveInterval::join didn't work right!");
1078 // If we're about to merge live ranges into a physical register live range,
1079 // we have to update any aliased register's live ranges to indicate that they
1080 // have clobbered values for this range.
1081 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1082 // If this is a extract_subreg where dst is a physical register, e.g.
1083 // cl = EXTRACT_SUBREG reg1024, 1
1084 // then create and update the actual physical register allocated to RHS.
1085 if (RealDstReg || RealSrcReg) {
1086 LiveInterval &RealInt =
1087 li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg);
1088 SmallSet<const VNInfo*, 4> CopiedValNos;
1089 for (LiveInterval::Ranges::const_iterator I = ResSrcInt->ranges.begin(),
1090 E = ResSrcInt->ranges.end(); I != E; ++I) {
1091 const LiveRange *DstLR = ResDstInt->getLiveRangeContaining(I->start);
1092 assert(DstLR && "Invalid joined interval!");
1093 const VNInfo *DstValNo = DstLR->valno;
1094 if (CopiedValNos.insert(DstValNo)) {
1095 VNInfo *ValNo = RealInt.getNextValue(DstValNo->def, DstValNo->copy,
1096 li_->getVNInfoAllocator());
1097 ValNo->hasPHIKill = DstValNo->hasPHIKill;
1098 RealInt.addKills(ValNo, DstValNo->kills);
1099 RealInt.MergeValueInAsValue(*ResDstInt, DstValNo, ValNo);
1103 DstReg = RealDstReg ? RealDstReg : RealSrcReg;
1106 // Update the liveintervals of sub-registers.
1107 for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
1108 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt,
1109 li_->getVNInfoAllocator());
1111 // Merge use info if the destination is a virtual register.
1112 LiveVariables::VarInfo& dVI = lv_->getVarInfo(DstReg);
1113 LiveVariables::VarInfo& sVI = lv_->getVarInfo(SrcReg);
1114 dVI.NumUses += sVI.NumUses;
1117 // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
1118 // larger super-register.
1119 if ((isExtSubReg || isInsSubReg) && !SrcIsPhys && !DstIsPhys) {
1120 if ((isExtSubReg && !Swapped) || (isInsSubReg && Swapped)) {
1121 ResSrcInt->Copy(*ResDstInt, li_->getVNInfoAllocator());
1122 std::swap(SrcReg, DstReg);
1123 std::swap(ResSrcInt, ResDstInt);
1128 // Add all copies that define val# in the source interval into the queue.
1129 for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(),
1130 e = ResSrcInt->vni_end(); i != e; ++i) {
1131 const VNInfo *vni = *i;
1132 if (!vni->def || vni->def == ~1U || vni->def == ~0U)
1134 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
1135 unsigned NewSrcReg, NewDstReg;
1137 JoinedCopies.count(CopyMI) == 0 &&
1138 tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg)) {
1139 unsigned LoopDepth = loopInfo->getLoopDepth(CopyMI->getParent());
1140 JoinQueue->push(CopyRec(CopyMI, LoopDepth,
1141 isBackEdgeCopy(CopyMI, DstReg)));
1146 // Remember to delete the copy instruction.
1147 JoinedCopies.insert(CopyMI);
1149 // Some live range has been lengthened due to colaescing, eliminate the
1150 // unnecessary kills.
1151 RemoveUnnecessaryKills(SrcReg, *ResDstInt);
1152 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1153 RemoveUnnecessaryKills(DstReg, *ResDstInt);
1155 // SrcReg is guarateed to be the register whose live interval that is
1157 li_->removeInterval(SrcReg);
1161 // r1024 = implicit_def
1164 RemoveDeadImpDef(DstReg, *ResDstInt);
1165 UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
1168 // Now the copy is being coalesced away, the val# previously defined
1169 // by the copy is being defined by an IMPLICIT_DEF which defines a zero
1170 // length interval. Remove the val#.
1171 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1172 const LiveRange *LR = ResDstInt->getLiveRangeContaining(CopyIdx);
1173 VNInfo *ImpVal = LR->valno;
1174 assert(ImpVal->def == CopyIdx);
1175 unsigned NextDef = LR->end;
1176 RemoveCopiesFromValNo(*ResDstInt, ImpVal);
1177 ResDstInt->removeValNo(ImpVal);
1178 LR = ResDstInt->FindLiveRangeContaining(NextDef);
1179 if (LR != ResDstInt->end() && LR->valno->def == NextDef) {
1180 // Special case: vr1024 = implicit_def
1181 // vr1024 = insert_subreg vr1024, vr1025, c
1182 // The insert_subreg becomes a "copy" that defines a val# which can itself
1183 // be coalesced away.
1184 MachineInstr *DefMI = li_->getInstructionFromIndex(NextDef);
1185 if (DefMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG)
1186 LR->valno->copy = DefMI;
1190 DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_);
1197 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1198 /// compute what the resultant value numbers for each value in the input two
1199 /// ranges will be. This is complicated by copies between the two which can
1200 /// and will commonly cause multiple value numbers to be merged into one.
1202 /// VN is the value number that we're trying to resolve. InstDefiningValue
1203 /// keeps track of the new InstDefiningValue assignment for the result
1204 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1205 /// whether a value in this or other is a copy from the opposite set.
1206 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1207 /// already been assigned.
1209 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1210 /// contains the value number the copy is from.
1212 static unsigned ComputeUltimateVN(VNInfo *VNI,
1213 SmallVector<VNInfo*, 16> &NewVNInfo,
1214 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1215 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1216 SmallVector<int, 16> &ThisValNoAssignments,
1217 SmallVector<int, 16> &OtherValNoAssignments) {
1218 unsigned VN = VNI->id;
1220 // If the VN has already been computed, just return it.
1221 if (ThisValNoAssignments[VN] >= 0)
1222 return ThisValNoAssignments[VN];
1223 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
1225 // If this val is not a copy from the other val, then it must be a new value
1226 // number in the destination.
1227 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1228 if (I == ThisFromOther.end()) {
1229 NewVNInfo.push_back(VNI);
1230 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1232 VNInfo *OtherValNo = I->second;
1234 // Otherwise, this *is* a copy from the RHS. If the other side has already
1235 // been computed, return it.
1236 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1237 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1239 // Mark this value number as currently being computed, then ask what the
1240 // ultimate value # of the other value is.
1241 ThisValNoAssignments[VN] = -2;
1242 unsigned UltimateVN =
1243 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1244 OtherValNoAssignments, ThisValNoAssignments);
1245 return ThisValNoAssignments[VN] = UltimateVN;
1248 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
1249 return std::find(V.begin(), V.end(), Val) != V.end();
1252 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
1253 /// the specified live interval is defined by a copy from the specified
1255 bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li,
1258 unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno);
1261 if (LR->valno->def == ~0U &&
1262 TargetRegisterInfo::isPhysicalRegister(li.reg) &&
1263 *tri_->getSuperRegisters(li.reg)) {
1264 // It's a sub-register live interval, we may not have precise information.
1266 MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start);
1267 unsigned SrcReg, DstReg;
1268 if (tii_->isMoveInstr(*DefMI, SrcReg, DstReg) &&
1269 DstReg == li.reg && SrcReg == Reg) {
1270 // Cache computed info.
1271 LR->valno->def = LR->start;
1272 LR->valno->copy = DefMI;
1279 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1280 /// caller of this method must guarantee that the RHS only contains a single
1281 /// value number and that the RHS is not defined by a copy from this
1282 /// interval. This returns false if the intervals are not joinable, or it
1283 /// joins them and returns true.
1284 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
1285 assert(RHS.containsOneValue());
1287 // Some number (potentially more than one) value numbers in the current
1288 // interval may be defined as copies from the RHS. Scan the overlapping
1289 // portions of the LHS and RHS, keeping track of this and looking for
1290 // overlapping live ranges that are NOT defined as copies. If these exist, we
1293 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
1294 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
1296 if (LHSIt->start < RHSIt->start) {
1297 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
1298 if (LHSIt != LHS.begin()) --LHSIt;
1299 } else if (RHSIt->start < LHSIt->start) {
1300 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
1301 if (RHSIt != RHS.begin()) --RHSIt;
1304 SmallVector<VNInfo*, 8> EliminatedLHSVals;
1307 // Determine if these live intervals overlap.
1308 bool Overlaps = false;
1309 if (LHSIt->start <= RHSIt->start)
1310 Overlaps = LHSIt->end > RHSIt->start;
1312 Overlaps = RHSIt->end > LHSIt->start;
1314 // If the live intervals overlap, there are two interesting cases: if the
1315 // LHS interval is defined by a copy from the RHS, it's ok and we record
1316 // that the LHS value # is the same as the RHS. If it's not, then we cannot
1317 // coalesce these live ranges and we bail out.
1319 // If we haven't already recorded that this value # is safe, check it.
1320 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
1321 // Copy from the RHS?
1322 if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg))
1323 return false; // Nope, bail out.
1325 EliminatedLHSVals.push_back(LHSIt->valno);
1328 // We know this entire LHS live range is okay, so skip it now.
1329 if (++LHSIt == LHSEnd) break;
1333 if (LHSIt->end < RHSIt->end) {
1334 if (++LHSIt == LHSEnd) break;
1336 // One interesting case to check here. It's possible that we have
1337 // something like "X3 = Y" which defines a new value number in the LHS,
1338 // and is the last use of this liverange of the RHS. In this case, we
1339 // want to notice this copy (so that it gets coalesced away) even though
1340 // the live ranges don't actually overlap.
1341 if (LHSIt->start == RHSIt->end) {
1342 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
1343 // We already know that this value number is going to be merged in
1344 // if coalescing succeeds. Just skip the liverange.
1345 if (++LHSIt == LHSEnd) break;
1347 // Otherwise, if this is a copy from the RHS, mark it as being merged
1349 if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) {
1350 EliminatedLHSVals.push_back(LHSIt->valno);
1352 // We know this entire LHS live range is okay, so skip it now.
1353 if (++LHSIt == LHSEnd) break;
1358 if (++RHSIt == RHSEnd) break;
1362 // If we got here, we know that the coalescing will be successful and that
1363 // the value numbers in EliminatedLHSVals will all be merged together. Since
1364 // the most common case is that EliminatedLHSVals has a single number, we
1365 // optimize for it: if there is more than one value, we merge them all into
1366 // the lowest numbered one, then handle the interval as if we were merging
1367 // with one value number.
1369 if (EliminatedLHSVals.size() > 1) {
1370 // Loop through all the equal value numbers merging them into the smallest
1372 VNInfo *Smallest = EliminatedLHSVals[0];
1373 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
1374 if (EliminatedLHSVals[i]->id < Smallest->id) {
1375 // Merge the current notion of the smallest into the smaller one.
1376 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
1377 Smallest = EliminatedLHSVals[i];
1379 // Merge into the smallest.
1380 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
1383 LHSValNo = Smallest;
1384 } else if (EliminatedLHSVals.empty()) {
1385 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
1386 *tri_->getSuperRegisters(LHS.reg))
1387 // Imprecise sub-register information. Can't handle it.
1389 assert(0 && "No copies from the RHS?");
1391 LHSValNo = EliminatedLHSVals[0];
1394 // Okay, now that there is a single LHS value number that we're merging the
1395 // RHS into, update the value number info for the LHS to indicate that the
1396 // value number is defined where the RHS value number was.
1397 const VNInfo *VNI = RHS.getValNumInfo(0);
1398 LHSValNo->def = VNI->def;
1399 LHSValNo->copy = VNI->copy;
1401 // Okay, the final step is to loop over the RHS live intervals, adding them to
1403 LHSValNo->hasPHIKill |= VNI->hasPHIKill;
1404 LHS.addKills(LHSValNo, VNI->kills);
1405 LHS.MergeRangesInAsValue(RHS, LHSValNo);
1406 LHS.weight += RHS.weight;
1407 if (RHS.preference && !LHS.preference)
1408 LHS.preference = RHS.preference;
1413 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1414 /// returns false. Otherwise, if one of the intervals being joined is a
1415 /// physreg, this method always canonicalizes LHS to be it. The output
1416 /// "RHS" will not have been modified, so we can use this information
1417 /// below to update aliases.
1418 bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS,
1419 LiveInterval &RHS, bool &Swapped) {
1420 // Compute the final value assignment, assuming that the live ranges can be
1422 SmallVector<int, 16> LHSValNoAssignments;
1423 SmallVector<int, 16> RHSValNoAssignments;
1424 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
1425 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
1426 SmallVector<VNInfo*, 16> NewVNInfo;
1428 // If a live interval is a physical register, conservatively check if any
1429 // of its sub-registers is overlapping the live interval of the virtual
1430 // register. If so, do not coalesce.
1431 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
1432 *tri_->getSubRegisters(LHS.reg)) {
1433 for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
1434 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1435 DOUT << "Interfere with sub-register ";
1436 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1439 } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
1440 *tri_->getSubRegisters(RHS.reg)) {
1441 for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
1442 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
1443 DOUT << "Interfere with sub-register ";
1444 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1449 // Compute ultimate value numbers for the LHS and RHS values.
1450 if (RHS.containsOneValue()) {
1451 // Copies from a liveinterval with a single value are simple to handle and
1452 // very common, handle the special case here. This is important, because
1453 // often RHS is small and LHS is large (e.g. a physreg).
1455 // Find out if the RHS is defined as a copy from some value in the LHS.
1456 int RHSVal0DefinedFromLHS = -1;
1458 VNInfo *RHSValNoInfo = NULL;
1459 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
1460 unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0);
1461 if ((RHSSrcReg == 0 || RHSSrcReg != LHS.reg)) {
1462 // If RHS is not defined as a copy from the LHS, we can use simpler and
1463 // faster checks to see if the live ranges are coalescable. This joiner
1464 // can't swap the LHS/RHS intervals though.
1465 if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
1466 return SimpleJoin(LHS, RHS);
1468 RHSValNoInfo = RHSValNoInfo0;
1471 // It was defined as a copy from the LHS, find out what value # it is.
1472 RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno;
1473 RHSValID = RHSValNoInfo->id;
1474 RHSVal0DefinedFromLHS = RHSValID;
1477 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1478 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1479 NewVNInfo.resize(LHS.getNumValNums(), NULL);
1481 // Okay, *all* of the values in LHS that are defined as a copy from RHS
1482 // should now get updated.
1483 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1486 unsigned VN = VNI->id;
1487 if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) {
1488 if (LHSSrcReg != RHS.reg) {
1489 // If this is not a copy from the RHS, its value number will be
1490 // unmodified by the coalescing.
1491 NewVNInfo[VN] = VNI;
1492 LHSValNoAssignments[VN] = VN;
1493 } else if (RHSValID == -1) {
1494 // Otherwise, it is a copy from the RHS, and we don't already have a
1495 // value# for it. Keep the current value number, but remember it.
1496 LHSValNoAssignments[VN] = RHSValID = VN;
1497 NewVNInfo[VN] = RHSValNoInfo;
1498 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
1500 // Otherwise, use the specified value #.
1501 LHSValNoAssignments[VN] = RHSValID;
1502 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
1503 NewVNInfo[VN] = RHSValNoInfo;
1504 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
1508 NewVNInfo[VN] = VNI;
1509 LHSValNoAssignments[VN] = VN;
1513 assert(RHSValID != -1 && "Didn't find value #?");
1514 RHSValNoAssignments[0] = RHSValID;
1515 if (RHSVal0DefinedFromLHS != -1) {
1516 // This path doesn't go through ComputeUltimateVN so just set
1518 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
1521 // Loop over the value numbers of the LHS, seeing if any are defined from
1523 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1526 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
1529 // DstReg is known to be a register in the LHS interval. If the src is
1530 // from the RHS interval, we can use its value #.
1531 if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
1534 // Figure out the value # from the RHS.
1535 LHSValsDefinedFromRHS[VNI]=RHS.getLiveRangeContaining(VNI->def-1)->valno;
1538 // Loop over the value numbers of the RHS, seeing if any are defined from
1540 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1543 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
1546 // DstReg is known to be a register in the RHS interval. If the src is
1547 // from the LHS interval, we can use its value #.
1548 if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
1551 // Figure out the value # from the LHS.
1552 RHSValsDefinedFromLHS[VNI]=LHS.getLiveRangeContaining(VNI->def-1)->valno;
1555 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1556 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1557 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1559 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1562 unsigned VN = VNI->id;
1563 if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
1565 ComputeUltimateVN(VNI, NewVNInfo,
1566 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1567 LHSValNoAssignments, RHSValNoAssignments);
1569 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1572 unsigned VN = VNI->id;
1573 if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
1575 // If this value number isn't a copy from the LHS, it's a new number.
1576 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
1577 NewVNInfo.push_back(VNI);
1578 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
1582 ComputeUltimateVN(VNI, NewVNInfo,
1583 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1584 RHSValNoAssignments, LHSValNoAssignments);
1588 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1589 // interval lists to see if these intervals are coalescable.
1590 LiveInterval::const_iterator I = LHS.begin();
1591 LiveInterval::const_iterator IE = LHS.end();
1592 LiveInterval::const_iterator J = RHS.begin();
1593 LiveInterval::const_iterator JE = RHS.end();
1595 // Skip ahead until the first place of potential sharing.
1596 if (I->start < J->start) {
1597 I = std::upper_bound(I, IE, J->start);
1598 if (I != LHS.begin()) --I;
1599 } else if (J->start < I->start) {
1600 J = std::upper_bound(J, JE, I->start);
1601 if (J != RHS.begin()) --J;
1605 // Determine if these two live ranges overlap.
1607 if (I->start < J->start) {
1608 Overlaps = I->end > J->start;
1610 Overlaps = J->end > I->start;
1613 // If so, check value # info to determine if they are really different.
1615 // If the live range overlap will map to the same value number in the
1616 // result liverange, we can still coalesce them. If not, we can't.
1617 if (LHSValNoAssignments[I->valno->id] !=
1618 RHSValNoAssignments[J->valno->id])
1622 if (I->end < J->end) {
1631 // Update kill info. Some live ranges are extended due to copy coalescing.
1632 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
1633 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
1634 VNInfo *VNI = I->first;
1635 unsigned LHSValID = LHSValNoAssignments[VNI->id];
1636 LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def);
1637 NewVNInfo[LHSValID]->hasPHIKill |= VNI->hasPHIKill;
1638 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
1641 // Update kill info. Some live ranges are extended due to copy coalescing.
1642 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
1643 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
1644 VNInfo *VNI = I->first;
1645 unsigned RHSValID = RHSValNoAssignments[VNI->id];
1646 LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def);
1647 NewVNInfo[RHSValID]->hasPHIKill |= VNI->hasPHIKill;
1648 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
1651 // If we get here, we know that we can coalesce the live ranges. Ask the
1652 // intervals to coalesce themselves now.
1653 if ((RHS.ranges.size() > LHS.ranges.size() &&
1654 TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
1655 TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
1656 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo);
1659 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo);
1666 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1667 // depth of the basic block (the unsigned), and then on the MBB number.
1668 struct DepthMBBCompare {
1669 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1670 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1671 if (LHS.first > RHS.first) return true; // Deeper loops first
1672 return LHS.first == RHS.first &&
1673 LHS.second->getNumber() < RHS.second->getNumber();
1678 /// getRepIntervalSize - Returns the size of the interval that represents the
1679 /// specified register.
1681 unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) {
1682 return Rc->getRepIntervalSize(Reg);
1685 /// CopyRecSort::operator - Join priority queue sorting function.
1687 bool CopyRecSort::operator()(CopyRec left, CopyRec right) const {
1688 // Inner loops first.
1689 if (left.LoopDepth > right.LoopDepth)
1691 else if (left.LoopDepth == right.LoopDepth)
1692 if (left.isBackEdge && !right.isBackEdge)
1697 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
1698 std::vector<CopyRec> &TryAgain) {
1699 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
1701 std::vector<CopyRec> VirtCopies;
1702 std::vector<CopyRec> PhysCopies;
1703 std::vector<CopyRec> ImpDefCopies;
1704 unsigned LoopDepth = loopInfo->getLoopDepth(MBB);
1705 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
1707 MachineInstr *Inst = MII++;
1709 // If this isn't a copy nor a extract_subreg, we can't join intervals.
1710 unsigned SrcReg, DstReg;
1711 if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
1712 DstReg = Inst->getOperand(0).getReg();
1713 SrcReg = Inst->getOperand(1).getReg();
1714 } else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
1715 DstReg = Inst->getOperand(0).getReg();
1716 SrcReg = Inst->getOperand(2).getReg();
1717 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg))
1720 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1721 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1723 JoinQueue->push(CopyRec(Inst, LoopDepth, isBackEdgeCopy(Inst, DstReg)));
1725 if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
1726 ImpDefCopies.push_back(CopyRec(Inst, 0, false));
1727 else if (SrcIsPhys || DstIsPhys)
1728 PhysCopies.push_back(CopyRec(Inst, 0, false));
1730 VirtCopies.push_back(CopyRec(Inst, 0, false));
1737 // Try coalescing implicit copies first, followed by copies to / from
1738 // physical registers, then finally copies from virtual registers to
1739 // virtual registers.
1740 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
1741 CopyRec &TheCopy = ImpDefCopies[i];
1743 if (!JoinCopy(TheCopy, Again))
1745 TryAgain.push_back(TheCopy);
1747 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
1748 CopyRec &TheCopy = PhysCopies[i];
1750 if (!JoinCopy(TheCopy, Again))
1752 TryAgain.push_back(TheCopy);
1754 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
1755 CopyRec &TheCopy = VirtCopies[i];
1757 if (!JoinCopy(TheCopy, Again))
1759 TryAgain.push_back(TheCopy);
1763 void SimpleRegisterCoalescing::joinIntervals() {
1764 DOUT << "********** JOINING INTERVALS ***********\n";
1767 JoinQueue = new JoinPriorityQueue<CopyRecSort>(this);
1769 std::vector<CopyRec> TryAgainList;
1770 if (loopInfo->begin() == loopInfo->end()) {
1771 // If there are no loops in the function, join intervals in function order.
1772 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
1774 CopyCoalesceInMBB(I, TryAgainList);
1776 // Otherwise, join intervals in inner loops before other intervals.
1777 // Unfortunately we can't just iterate over loop hierarchy here because
1778 // there may be more MBB's than BB's. Collect MBB's for sorting.
1780 // Join intervals in the function prolog first. We want to join physical
1781 // registers with virtual registers before the intervals got too long.
1782 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
1783 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
1784 MachineBasicBlock *MBB = I;
1785 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
1788 // Sort by loop depth.
1789 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
1791 // Finally, join intervals in loop nest order.
1792 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
1793 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
1796 // Joining intervals can allow other intervals to be joined. Iteratively join
1797 // until we make no progress.
1799 SmallVector<CopyRec, 16> TryAgain;
1800 bool ProgressMade = true;
1801 while (ProgressMade) {
1802 ProgressMade = false;
1803 while (!JoinQueue->empty()) {
1804 CopyRec R = JoinQueue->pop();
1806 bool Success = JoinCopy(R, Again);
1808 ProgressMade = true;
1810 TryAgain.push_back(R);
1814 while (!TryAgain.empty()) {
1815 JoinQueue->push(TryAgain.back());
1816 TryAgain.pop_back();
1821 bool ProgressMade = true;
1822 while (ProgressMade) {
1823 ProgressMade = false;
1825 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
1826 CopyRec &TheCopy = TryAgainList[i];
1829 bool Success = JoinCopy(TheCopy, Again);
1830 if (Success || !Again) {
1831 TheCopy.MI = 0; // Mark this one as done.
1832 ProgressMade = true;
1843 /// Return true if the two specified registers belong to different register
1844 /// classes. The registers may be either phys or virt regs.
1845 bool SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
1846 unsigned RegB) const {
1848 // Get the register classes for the first reg.
1849 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
1850 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
1851 "Shouldn't consider two physregs!");
1852 return !mri_->getRegClass(RegB)->contains(RegA);
1855 // Compare against the regclass for the second reg.
1856 const TargetRegisterClass *RegClass = mri_->getRegClass(RegA);
1857 if (TargetRegisterInfo::isVirtualRegister(RegB))
1858 return RegClass != mri_->getRegClass(RegB);
1860 return !RegClass->contains(RegB);
1863 /// lastRegisterUse - Returns the last use of the specific register between
1864 /// cycles Start and End or NULL if there are no uses.
1866 SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End,
1867 unsigned Reg, unsigned &UseIdx) const{
1869 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
1870 MachineOperand *LastUse = NULL;
1871 for (MachineRegisterInfo::use_iterator I = mri_->use_begin(Reg),
1872 E = mri_->use_end(); I != E; ++I) {
1873 MachineOperand &Use = I.getOperand();
1874 MachineInstr *UseMI = Use.getParent();
1875 unsigned SrcReg, DstReg;
1876 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg) && SrcReg == DstReg)
1877 // Ignore identity copies.
1879 unsigned Idx = li_->getInstructionIndex(UseMI);
1880 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
1888 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
1891 // Skip deleted instructions
1892 MachineInstr *MI = li_->getInstructionFromIndex(e);
1893 while ((e - InstrSlots::NUM) >= s && !MI) {
1894 e -= InstrSlots::NUM;
1895 MI = li_->getInstructionFromIndex(e);
1897 if (e < s || MI == NULL)
1900 // Ignore identity copies.
1901 unsigned SrcReg, DstReg;
1902 if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg))
1903 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
1904 MachineOperand &Use = MI->getOperand(i);
1905 if (Use.isRegister() && Use.isUse() && Use.getReg() &&
1906 tri_->regsOverlap(Use.getReg(), Reg)) {
1912 e -= InstrSlots::NUM;
1919 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
1920 if (TargetRegisterInfo::isPhysicalRegister(reg))
1921 cerr << tri_->getName(reg);
1923 cerr << "%reg" << reg;
1926 void SimpleRegisterCoalescing::releaseMemory() {
1927 JoinedCopies.clear();
1930 static bool isZeroLengthInterval(LiveInterval *li) {
1931 for (LiveInterval::Ranges::const_iterator
1932 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
1933 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
1938 /// TurnCopyIntoImpDef - If source of the specified copy is an implicit def,
1939 /// turn the copy into an implicit def.
1941 SimpleRegisterCoalescing::TurnCopyIntoImpDef(MachineBasicBlock::iterator &I,
1942 MachineBasicBlock *MBB,
1943 unsigned DstReg, unsigned SrcReg) {
1944 MachineInstr *CopyMI = &*I;
1945 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1946 if (!li_->hasInterval(SrcReg))
1948 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1949 if (!SrcInt.empty())
1951 if (!li_->hasInterval(DstReg))
1953 LiveInterval &DstInt = li_->getInterval(DstReg);
1954 const LiveRange *DstLR = DstInt.getLiveRangeContaining(CopyIdx);
1955 DstInt.removeValNo(DstLR->valno);
1956 CopyMI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
1957 for (int i = CopyMI->getNumOperands() - 1, e = 0; i > e; --i)
1958 CopyMI->RemoveOperand(i);
1959 bool NoUse = mri_->use_begin(SrcReg) == mri_->use_end();
1961 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
1962 E = mri_->reg_end(); I != E; ) {
1963 assert(I.getOperand().isDef());
1964 MachineInstr *DefMI = &*I;
1966 // The implicit_def source has no other uses, delete it.
1967 assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF);
1968 li_->RemoveMachineInstrFromMaps(DefMI);
1969 DefMI->eraseFromParent();
1977 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
1979 mri_ = &fn.getRegInfo();
1980 tm_ = &fn.getTarget();
1981 tri_ = tm_->getRegisterInfo();
1982 tii_ = tm_->getInstrInfo();
1983 li_ = &getAnalysis<LiveIntervals>();
1984 lv_ = &getAnalysis<LiveVariables>();
1985 loopInfo = &getAnalysis<MachineLoopInfo>();
1987 DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
1988 << "********** Function: "
1989 << ((Value*)mf_->getFunction())->getName() << '\n';
1991 allocatableRegs_ = tri_->getAllocatableSet(fn);
1992 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
1993 E = tri_->regclass_end(); I != E; ++I)
1994 allocatableRCRegs_.insert(std::make_pair(*I,
1995 tri_->getAllocatableSet(fn, *I)));
1997 // Join (coalesce) intervals if requested.
1998 if (EnableJoining) {
2000 DOUT << "********** INTERVALS POST JOINING **********\n";
2001 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){
2002 I->second.print(DOUT, tri_);
2006 // Delete all coalesced copies.
2007 for (SmallPtrSet<MachineInstr*,32>::iterator I = JoinedCopies.begin(),
2008 E = JoinedCopies.end(); I != E; ++I) {
2009 MachineInstr *CopyMI = *I;
2010 unsigned SrcReg, DstReg;
2011 if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
2012 assert((CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
2013 CopyMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) &&
2014 "Unrecognized copy instruction");
2015 DstReg = CopyMI->getOperand(0).getReg();
2017 if (CopyMI->registerDefIsDead(DstReg)) {
2018 LiveInterval &li = li_->getInterval(DstReg);
2019 if (!ShortenDeadCopySrcLiveRange(li, CopyMI))
2020 ShortenDeadCopyLiveRange(li, CopyMI);
2022 li_->RemoveMachineInstrFromMaps(*I);
2023 (*I)->eraseFromParent();
2028 // Perform a final pass over the instructions and compute spill weights
2029 // and remove identity moves.
2030 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
2031 mbbi != mbbe; ++mbbi) {
2032 MachineBasicBlock* mbb = mbbi;
2033 unsigned loopDepth = loopInfo->getLoopDepth(mbb);
2035 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
2037 // if the move will be an identity move delete it
2038 unsigned srcReg, dstReg;
2039 bool isMove = tii_->isMoveInstr(*mii, srcReg, dstReg);
2040 if (isMove && srcReg == dstReg) {
2041 if (li_->hasInterval(srcReg)) {
2042 LiveInterval &RegInt = li_->getInterval(srcReg);
2043 // If def of this move instruction is dead, remove its live range
2044 // from the dstination register's live interval.
2045 if (mii->registerDefIsDead(dstReg)) {
2046 if (!ShortenDeadCopySrcLiveRange(RegInt, mii))
2047 ShortenDeadCopyLiveRange(RegInt, mii);
2050 li_->RemoveMachineInstrFromMaps(mii);
2051 mii = mbbi->erase(mii);
2053 } else if (!isMove || !TurnCopyIntoImpDef(mii, mbb, dstReg, srcReg)) {
2054 SmallSet<unsigned, 4> UniqueUses;
2055 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
2056 const MachineOperand &mop = mii->getOperand(i);
2057 if (mop.isRegister() && mop.getReg() &&
2058 TargetRegisterInfo::isVirtualRegister(mop.getReg())) {
2059 unsigned reg = mop.getReg();
2060 // Multiple uses of reg by the same instruction. It should not
2061 // contribute to spill weight again.
2062 if (UniqueUses.count(reg) != 0)
2064 LiveInterval &RegInt = li_->getInterval(reg);
2066 li_->getSpillWeight(mop.isDef(), mop.isUse(), loopDepth);
2067 UniqueUses.insert(reg);
2075 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
2076 LiveInterval &LI = I->second;
2077 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
2078 // If the live interval length is essentially zero, i.e. in every live
2079 // range the use follows def immediately, it doesn't make sense to spill
2080 // it and hope it will be easier to allocate for this li.
2081 if (isZeroLengthInterval(&LI))
2082 LI.weight = HUGE_VALF;
2084 bool isLoad = false;
2085 if (li_->isReMaterializable(LI, isLoad)) {
2086 // If all of the definitions of the interval are re-materializable,
2087 // it is a preferred candidate for spilling. If non of the defs are
2088 // loads, then it's potentially very cheap to re-materialize.
2089 // FIXME: this gets much more complicated once we support non-trivial
2090 // re-materialization.
2098 // Slightly prefer live interval that has been assigned a preferred reg.
2102 // Divide the weight of the interval by its size. This encourages
2103 // spilling of intervals that are large and have few uses, and
2104 // discourages spilling of small intervals with many uses.
2105 LI.weight /= LI.getSize();
2113 /// print - Implement the dump method.
2114 void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const {
2118 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
2119 return new SimpleRegisterCoalescing();
2122 // Make sure that anything that uses RegisterCoalescer pulls in this file...
2123 DEFINING_FILE_FOR(SimpleRegisterCoalescing)