1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "SimpleRegisterCoalescing.h"
17 #include "VirtRegMap.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/Value.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/RegisterCoalescer.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/ADT/STLExtras.h"
38 STATISTIC(numJoins , "Number of interval joins performed");
39 STATISTIC(numSubJoins , "Number of subclass joins performed");
40 STATISTIC(numCommutes , "Number of instruction commuting performed");
41 STATISTIC(numExtends , "Number of copies extended");
42 STATISTIC(NumReMats , "Number of instructions re-materialized");
43 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
44 STATISTIC(numAborts , "Number of times interval joining aborted");
46 char SimpleRegisterCoalescing::ID = 0;
48 EnableJoining("join-liveintervals",
49 cl::desc("Coalesce copies (default=true)"),
53 NewHeuristic("new-coalescer-heuristic",
54 cl::desc("Use new coalescer heuristic"),
55 cl::init(false), cl::Hidden);
58 CrossClassJoin("join-subclass-copies",
59 cl::desc("Coalesce copies to sub- register class"),
60 cl::init(false), cl::Hidden);
62 static RegisterPass<SimpleRegisterCoalescing>
63 X("simple-register-coalescing", "Simple Register Coalescing");
65 // Declare that we implement the RegisterCoalescer interface
66 static RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
68 const PassInfo *const llvm::SimpleRegisterCoalescingID = &X;
70 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
71 AU.addRequired<LiveIntervals>();
72 AU.addPreserved<LiveIntervals>();
73 AU.addRequired<MachineLoopInfo>();
74 AU.addPreserved<MachineLoopInfo>();
75 AU.addPreservedID(MachineDominatorsID);
77 AU.addPreservedID(StrongPHIEliminationID);
79 AU.addPreservedID(PHIEliminationID);
80 AU.addPreservedID(TwoAddressInstructionPassID);
81 MachineFunctionPass::getAnalysisUsage(AU);
84 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
85 /// being the source and IntB being the dest, thus this defines a value number
86 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
87 /// see if we can merge these two pieces of B into a single value number,
88 /// eliminating a copy. For example:
92 /// B1 = A3 <- this copy
94 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
95 /// value number to be replaced with B0 (which simplifies the B liveinterval).
97 /// This returns true if an interval was modified.
99 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA,
101 MachineInstr *CopyMI) {
102 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
104 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
105 // the example above.
106 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
107 assert(BLR != IntB.end() && "Live range not found!");
108 VNInfo *BValNo = BLR->valno;
110 // Get the location that B is defined at. Two options: either this value has
111 // an unknown definition point or it is defined at CopyIdx. If unknown, we
113 if (!BValNo->copy) return false;
114 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
116 // AValNo is the value number in A that defines the copy, A3 in the example.
117 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
118 assert(ALR != IntA.end() && "Live range not found!");
119 VNInfo *AValNo = ALR->valno;
120 // If it's re-defined by an early clobber somewhere in the live range, then
121 // it's not safe to eliminate the copy. FIXME: This is a temporary workaround.
123 // 172 %ECX<def> = MOV32rr %reg1039<kill>
124 // 180 INLINEASM <es:subl $5,$1
125 // sbbl $3,$0>, 10, %EAX<def>, 14, %ECX<earlyclobber,def>, 9, %EAX<kill>,
126 // 36, <fi#0>, 1, %reg0, 0, 9, %ECX<kill>, 36, <fi#1>, 1, %reg0, 0
127 // 188 %EAX<def> = MOV32rr %EAX<kill>
128 // 196 %ECX<def> = MOV32rr %ECX<kill>
129 // 204 %ECX<def> = MOV32rr %ECX<kill>
130 // 212 %EAX<def> = MOV32rr %EAX<kill>
131 // 220 %EAX<def> = MOV32rr %EAX
132 // 228 %reg1039<def> = MOV32rr %ECX<kill>
133 // The early clobber operand ties ECX input to the ECX def.
135 // The live interval of ECX is represented as this:
136 // %reg20,inf = [46,47:1)[174,230:0) 0@174-(230) 1@46-(47)
137 // The coalescer has no idea there was a def in the middle of [174,230].
138 if (AValNo->redefByEC)
141 // If AValNo is defined as a copy from IntB, we can potentially process this.
142 // Get the instruction that defines this value number.
143 unsigned SrcReg = li_->getVNInfoSourceReg(AValNo);
144 if (!SrcReg) return false; // Not defined by a copy.
146 // If the value number is not defined by a copy instruction, ignore it.
148 // If the source register comes from an interval other than IntB, we can't
150 if (SrcReg != IntB.reg) return false;
152 // Get the LiveRange in IntB that this value number starts with.
153 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
154 assert(ValLR != IntB.end() && "Live range not found!");
156 // Make sure that the end of the live range is inside the same block as
158 MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
160 ValLREndInst->getParent() != CopyMI->getParent()) return false;
162 // Okay, we now know that ValLR ends in the same block that the CopyMI
163 // live-range starts. If there are no intervening live ranges between them in
164 // IntB, we can merge them.
165 if (ValLR+1 != BLR) return false;
167 // If a live interval is a physical register, conservatively check if any
168 // of its sub-registers is overlapping the live interval of the virtual
169 // register. If so, do not coalesce.
170 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg) &&
171 *tri_->getSubRegisters(IntB.reg)) {
172 for (const unsigned* SR = tri_->getSubRegisters(IntB.reg); *SR; ++SR)
173 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
174 DOUT << "Interfere with sub-register ";
175 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
180 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
182 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
183 // We are about to delete CopyMI, so need to remove it as the 'instruction
184 // that defines this value #'. Update the the valnum with the new defining
186 BValNo->def = FillerStart;
189 // Okay, we can merge them. We need to insert a new liverange:
190 // [ValLR.end, BLR.begin) of either value number, then we merge the
191 // two value numbers.
192 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
194 // If the IntB live range is assigned to a physical register, and if that
195 // physreg has aliases,
196 if (TargetRegisterInfo::isPhysicalRegister(IntB.reg)) {
197 // Update the liveintervals of sub-registers.
198 for (const unsigned *AS = tri_->getSubRegisters(IntB.reg); *AS; ++AS) {
199 LiveInterval &AliasLI = li_->getInterval(*AS);
200 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
201 AliasLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator())));
205 // Okay, merge "B1" into the same value number as "B0".
206 if (BValNo != ValLR->valno) {
207 IntB.addKills(ValLR->valno, BValNo->kills);
208 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
210 DOUT << " result = "; IntB.print(DOUT, tri_);
213 // If the source instruction was killing the source register before the
214 // merge, unset the isKill marker given the live range has been extended.
215 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
217 ValLREndInst->getOperand(UIdx).setIsKill(false);
218 IntB.removeKill(ValLR->valno, FillerStart);
225 /// HasOtherReachingDefs - Return true if there are definitions of IntB
226 /// other than BValNo val# that can reach uses of AValno val# of IntA.
227 bool SimpleRegisterCoalescing::HasOtherReachingDefs(LiveInterval &IntA,
231 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
233 if (AI->valno != AValNo) continue;
234 LiveInterval::Ranges::iterator BI =
235 std::upper_bound(IntB.ranges.begin(), IntB.ranges.end(), AI->start);
236 if (BI != IntB.ranges.begin())
238 for (; BI != IntB.ranges.end() && AI->end >= BI->start; ++BI) {
239 if (BI->valno == BValNo)
241 if (BI->start <= AI->start && BI->end > AI->start)
243 if (BI->start > AI->start && BI->start < AI->end)
250 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy with IntA
251 /// being the source and IntB being the dest, thus this defines a value number
252 /// in IntB. If the source value number (in IntA) is defined by a commutable
253 /// instruction and its other operand is coalesced to the copy dest register,
254 /// see if we can transform the copy into a noop by commuting the definition. For
257 /// A3 = op A2 B0<kill>
259 /// B1 = A3 <- this copy
261 /// = op A3 <- more uses
265 /// B2 = op B0 A2<kill>
267 /// B1 = B2 <- now an identify copy
269 /// = op B2 <- more uses
271 /// This returns true if an interval was modified.
273 bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA,
275 MachineInstr *CopyMI) {
276 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
278 // FIXME: For now, only eliminate the copy by commuting its def when the
279 // source register is a virtual register. We want to guard against cases
280 // where the copy is a back edge copy and commuting the def lengthen the
281 // live interval of the source register to the entire loop.
282 if (TargetRegisterInfo::isPhysicalRegister(IntA.reg))
285 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
286 // the example above.
287 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
288 assert(BLR != IntB.end() && "Live range not found!");
289 VNInfo *BValNo = BLR->valno;
291 // Get the location that B is defined at. Two options: either this value has
292 // an unknown definition point or it is defined at CopyIdx. If unknown, we
294 if (!BValNo->copy) return false;
295 assert(BValNo->def == CopyIdx && "Copy doesn't define the value?");
297 // AValNo is the value number in A that defines the copy, A3 in the example.
298 LiveInterval::iterator ALR = IntA.FindLiveRangeContaining(CopyIdx-1);
299 assert(ALR != IntA.end() && "Live range not found!");
300 VNInfo *AValNo = ALR->valno;
301 // If other defs can reach uses of this def, then it's not safe to perform
303 if (AValNo->def == ~0U || AValNo->def == ~1U || AValNo->hasPHIKill)
305 MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def);
306 const TargetInstrDesc &TID = DefMI->getDesc();
308 if (!TID.isCommutable() ||
309 !tii_->CommuteChangesDestination(DefMI, NewDstIdx))
312 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx);
313 unsigned NewReg = NewDstMO.getReg();
314 if (NewReg != IntB.reg || !NewDstMO.isKill())
317 // Make sure there are no other definitions of IntB that would reach the
318 // uses which the new definition can reach.
319 if (HasOtherReachingDefs(IntA, IntB, AValNo, BValNo))
322 // If some of the uses of IntA.reg is already coalesced away, return false.
323 // It's not possible to determine whether it's safe to perform the coalescing.
324 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
325 UE = mri_->use_end(); UI != UE; ++UI) {
326 MachineInstr *UseMI = &*UI;
327 unsigned UseIdx = li_->getInstructionIndex(UseMI);
328 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
329 if (ULR == IntA.end())
331 if (ULR->valno == AValNo && JoinedCopies.count(UseMI))
335 // At this point we have decided that it is legal to do this
336 // transformation. Start by commuting the instruction.
337 MachineBasicBlock *MBB = DefMI->getParent();
338 MachineInstr *NewMI = tii_->commuteInstruction(DefMI);
341 if (NewMI != DefMI) {
342 li_->ReplaceMachineInstrInMaps(DefMI, NewMI);
343 MBB->insert(DefMI, NewMI);
346 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
347 NewMI->getOperand(OpIdx).setIsKill();
349 bool BHasPHIKill = BValNo->hasPHIKill;
350 SmallVector<VNInfo*, 4> BDeadValNos;
351 SmallVector<unsigned, 4> BKills;
352 std::map<unsigned, unsigned> BExtend;
354 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
363 // then do not add kills of A to the newly created B interval.
364 bool Extended = BLR->end > ALR->end && ALR->end != ALR->start;
366 BExtend[ALR->end] = BLR->end;
368 // Update uses of IntA of the specific Val# with IntB.
369 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(IntA.reg),
370 UE = mri_->use_end(); UI != UE;) {
371 MachineOperand &UseMO = UI.getOperand();
372 MachineInstr *UseMI = &*UI;
374 if (JoinedCopies.count(UseMI))
376 unsigned UseIdx = li_->getInstructionIndex(UseMI);
377 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
378 if (ULR == IntA.end() || ULR->valno != AValNo)
380 UseMO.setReg(NewReg);
383 if (UseMO.isKill()) {
385 UseMO.setIsKill(false);
387 BKills.push_back(li_->getUseIndex(UseIdx)+1);
389 unsigned SrcReg, DstReg;
390 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg))
392 if (DstReg == IntB.reg) {
393 // This copy will become a noop. If it's defining a new val#,
394 // remove that val# as well. However this live range is being
395 // extended to the end of the existing live range defined by the copy.
396 unsigned DefIdx = li_->getDefIndex(UseIdx);
397 const LiveRange *DLR = IntB.getLiveRangeContaining(DefIdx);
398 BHasPHIKill |= DLR->valno->hasPHIKill;
399 assert(DLR->valno->def == DefIdx);
400 BDeadValNos.push_back(DLR->valno);
401 BExtend[DLR->start] = DLR->end;
402 JoinedCopies.insert(UseMI);
403 // If this is a kill but it's going to be removed, the last use
404 // of the same val# is the new kill.
410 // We need to insert a new liverange: [ALR.start, LastUse). It may be we can
411 // simply extend BLR if CopyMI doesn't end the range.
412 DOUT << "\nExtending: "; IntB.print(DOUT, tri_);
414 // Remove val#'s defined by copies that will be coalesced away.
415 for (unsigned i = 0, e = BDeadValNos.size(); i != e; ++i)
416 IntB.removeValNo(BDeadValNos[i]);
418 // Extend BValNo by merging in IntA live ranges of AValNo. Val# definition
419 // is updated. Kills are also updated.
420 VNInfo *ValNo = BValNo;
421 ValNo->def = AValNo->def;
423 for (unsigned j = 0, ee = ValNo->kills.size(); j != ee; ++j) {
424 unsigned Kill = ValNo->kills[j];
425 if (Kill != BLR->end)
426 BKills.push_back(Kill);
428 ValNo->kills.clear();
429 for (LiveInterval::iterator AI = IntA.begin(), AE = IntA.end();
431 if (AI->valno != AValNo) continue;
432 unsigned End = AI->end;
433 std::map<unsigned, unsigned>::iterator EI = BExtend.find(End);
434 if (EI != BExtend.end())
436 IntB.addRange(LiveRange(AI->start, End, ValNo));
438 IntB.addKills(ValNo, BKills);
439 ValNo->hasPHIKill = BHasPHIKill;
441 DOUT << " result = "; IntB.print(DOUT, tri_);
444 DOUT << "\nShortening: "; IntA.print(DOUT, tri_);
445 IntA.removeValNo(AValNo);
446 DOUT << " result = "; IntA.print(DOUT, tri_);
453 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
454 /// computation, replace the copy by rematerialize the definition.
455 bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
457 MachineInstr *CopyMI) {
458 unsigned CopyIdx = li_->getUseIndex(li_->getInstructionIndex(CopyMI));
459 LiveInterval::iterator SrcLR = SrcInt.FindLiveRangeContaining(CopyIdx);
460 assert(SrcLR != SrcInt.end() && "Live range not found!");
461 VNInfo *ValNo = SrcLR->valno;
462 // If other defs can reach uses of this def, then it's not safe to perform
464 if (ValNo->def == ~0U || ValNo->def == ~1U || ValNo->hasPHIKill)
466 MachineInstr *DefMI = li_->getInstructionFromIndex(ValNo->def);
467 const TargetInstrDesc &TID = DefMI->getDesc();
468 if (!TID.isAsCheapAsAMove())
470 bool SawStore = false;
471 if (!DefMI->isSafeToMove(tii_, SawStore))
474 unsigned DefIdx = li_->getDefIndex(CopyIdx);
475 const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
476 DLR->valno->copy = NULL;
477 // Don't forget to update sub-register intervals.
478 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
479 for (const unsigned* SR = tri_->getSubRegisters(DstReg); *SR; ++SR) {
480 if (!li_->hasInterval(*SR))
482 DLR = li_->getInterval(*SR).getLiveRangeContaining(DefIdx);
483 if (DLR && DLR->valno->copy == CopyMI)
484 DLR->valno->copy = NULL;
488 MachineBasicBlock *MBB = CopyMI->getParent();
489 MachineBasicBlock::iterator MII = next(MachineBasicBlock::iterator(CopyMI));
490 CopyMI->removeFromParent();
491 tii_->reMaterialize(*MBB, MII, DstReg, DefMI);
492 MachineInstr *NewMI = prior(MII);
493 // CopyMI may have implicit operands, transfer them over to the newly
494 // rematerialized instruction. And update implicit def interval valnos.
495 for (unsigned i = CopyMI->getDesc().getNumOperands(),
496 e = CopyMI->getNumOperands(); i != e; ++i) {
497 MachineOperand &MO = CopyMI->getOperand(i);
498 if (MO.isReg() && MO.isImplicit())
499 NewMI->addOperand(MO);
500 if (MO.isDef() && li_->hasInterval(MO.getReg())) {
501 unsigned Reg = MO.getReg();
502 DLR = li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
503 if (DLR && DLR->valno->copy == CopyMI)
504 DLR->valno->copy = NULL;
508 li_->ReplaceMachineInstrInMaps(CopyMI, NewMI);
509 MBB->getParent()->DeleteMachineInstr(CopyMI);
510 ReMatCopies.insert(CopyMI);
511 ReMatDefs.insert(DefMI);
516 /// isBackEdgeCopy - Returns true if CopyMI is a back edge copy.
518 bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
519 unsigned DstReg) const {
520 MachineBasicBlock *MBB = CopyMI->getParent();
521 const MachineLoop *L = loopInfo->getLoopFor(MBB);
524 if (MBB != L->getLoopLatch())
527 LiveInterval &LI = li_->getInterval(DstReg);
528 unsigned DefIdx = li_->getInstructionIndex(CopyMI);
529 LiveInterval::const_iterator DstLR =
530 LI.FindLiveRangeContaining(li_->getDefIndex(DefIdx));
531 if (DstLR == LI.end())
533 unsigned KillIdx = li_->getMBBEndIdx(MBB) + 1;
534 if (DstLR->valno->kills.size() == 1 &&
535 DstLR->valno->kills[0] == KillIdx && DstLR->valno->hasPHIKill)
540 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
541 /// update the subregister number if it is not zero. If DstReg is a
542 /// physical register and the existing subregister number of the def / use
543 /// being updated is not zero, make sure to set it to the correct physical
546 SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
548 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
549 if (DstIsPhys && SubIdx) {
550 // Figure out the real physical register we are updating with.
551 DstReg = tri_->getSubReg(DstReg, SubIdx);
555 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
556 E = mri_->reg_end(); I != E; ) {
557 MachineOperand &O = I.getOperand();
558 MachineInstr *UseMI = &*I;
560 unsigned OldSubIdx = O.getSubReg();
562 unsigned UseDstReg = DstReg;
564 UseDstReg = tri_->getSubReg(DstReg, OldSubIdx);
566 unsigned CopySrcReg, CopyDstReg;
567 if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg) &&
568 CopySrcReg != CopyDstReg &&
569 CopySrcReg == SrcReg && CopyDstReg != UseDstReg) {
570 // If the use is a copy and it won't be coalesced away, and its source
571 // is defined by a trivial computation, try to rematerialize it instead.
572 if (ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg,UseMI))
581 // Sub-register indexes goes from small to large. e.g.
582 // RAX: 1 -> AL, 2 -> AX, 3 -> EAX
583 // EAX: 1 -> AL, 2 -> AX
584 // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose
585 // sub-register 2 is also AX.
586 if (SubIdx && OldSubIdx && SubIdx != OldSubIdx)
587 assert(OldSubIdx < SubIdx && "Conflicting sub-register index!");
590 // Remove would-be duplicated kill marker.
591 if (O.isKill() && UseMI->killsRegister(DstReg))
595 // After updating the operand, check if the machine instruction has
596 // become a copy. If so, update its val# information.
597 const TargetInstrDesc &TID = UseMI->getDesc();
598 unsigned CopySrcReg, CopyDstReg;
599 if (TID.getNumDefs() == 1 && TID.getNumOperands() > 2 &&
600 tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg) &&
601 CopySrcReg != CopyDstReg &&
602 (TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
603 allocatableRegs_[CopyDstReg])) {
604 LiveInterval &LI = li_->getInterval(CopyDstReg);
605 unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(UseMI));
606 const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx);
607 if (DLR->valno->def == DefIdx)
608 DLR->valno->copy = UseMI;
613 /// RemoveDeadImpDef - Remove implicit_def instructions which are "re-defining"
614 /// registers due to insert_subreg coalescing. e.g.
616 /// r1025 = implicit_def
617 /// r1025 = insert_subreg r1025, r1024
621 /// r1025 = implicit_def
622 /// r1025 = insert_subreg r1025, r1025
625 SimpleRegisterCoalescing::RemoveDeadImpDef(unsigned Reg, LiveInterval &LI) {
626 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
627 E = mri_->reg_end(); I != E; ) {
628 MachineOperand &O = I.getOperand();
629 MachineInstr *DefMI = &*I;
633 if (DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
635 if (!LI.liveBeforeAndAt(li_->getInstructionIndex(DefMI)))
637 li_->RemoveMachineInstrFromMaps(DefMI);
638 DefMI->eraseFromParent();
642 /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
643 /// due to live range lengthening as the result of coalescing.
644 void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg,
646 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
647 UE = mri_->use_end(); UI != UE; ++UI) {
648 MachineOperand &UseMO = UI.getOperand();
649 if (UseMO.isKill()) {
650 MachineInstr *UseMI = UseMO.getParent();
651 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
652 if (JoinedCopies.count(UseMI))
654 const LiveRange *UI = LI.getLiveRangeContaining(UseIdx);
655 if (!UI || !LI.isKill(UI->valno, UseIdx+1))
656 UseMO.setIsKill(false);
661 /// removeRange - Wrapper for LiveInterval::removeRange. This removes a range
662 /// from a physical register live interval as well as from the live intervals
663 /// of its sub-registers.
664 static void removeRange(LiveInterval &li, unsigned Start, unsigned End,
665 LiveIntervals *li_, const TargetRegisterInfo *tri_) {
666 li.removeRange(Start, End, true);
667 if (TargetRegisterInfo::isPhysicalRegister(li.reg)) {
668 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
669 if (!li_->hasInterval(*SR))
671 LiveInterval &sli = li_->getInterval(*SR);
672 unsigned RemoveEnd = Start;
673 while (RemoveEnd != End) {
674 LiveInterval::iterator LR = sli.FindLiveRangeContaining(Start);
677 RemoveEnd = (LR->end < End) ? LR->end : End;
678 sli.removeRange(Start, RemoveEnd, true);
685 /// removeIntervalIfEmpty - Check if the live interval of a physical register
686 /// is empty, if so remove it and also remove the empty intervals of its
687 /// sub-registers. Return true if live interval is removed.
688 static bool removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *li_,
689 const TargetRegisterInfo *tri_) {
691 if (TargetRegisterInfo::isPhysicalRegister(li.reg))
692 for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) {
693 if (!li_->hasInterval(*SR))
695 LiveInterval &sli = li_->getInterval(*SR);
697 li_->removeInterval(*SR);
699 li_->removeInterval(li.reg);
705 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
706 /// Return true if live interval is removed.
707 bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li,
708 MachineInstr *CopyMI) {
709 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
710 LiveInterval::iterator MLR =
711 li.FindLiveRangeContaining(li_->getDefIndex(CopyIdx));
713 return false; // Already removed by ShortenDeadCopySrcLiveRange.
714 unsigned RemoveStart = MLR->start;
715 unsigned RemoveEnd = MLR->end;
716 // Remove the liverange that's defined by this.
717 if (RemoveEnd == li_->getDefIndex(CopyIdx)+1) {
718 removeRange(li, RemoveStart, RemoveEnd, li_, tri_);
719 return removeIntervalIfEmpty(li, li_, tri_);
724 /// RemoveDeadDef - If a def of a live interval is now determined dead, remove
725 /// the val# it defines. If the live interval becomes empty, remove it as well.
726 bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li,
727 MachineInstr *DefMI) {
728 unsigned DefIdx = li_->getDefIndex(li_->getInstructionIndex(DefMI));
729 LiveInterval::iterator MLR = li.FindLiveRangeContaining(DefIdx);
730 if (DefIdx != MLR->valno->def)
732 li.removeValNo(MLR->valno);
733 return removeIntervalIfEmpty(li, li_, tri_);
736 /// PropagateDeadness - Propagate the dead marker to the instruction which
737 /// defines the val#.
738 static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI,
739 unsigned &LRStart, LiveIntervals *li_,
740 const TargetRegisterInfo* tri_) {
741 MachineInstr *DefMI =
742 li_->getInstructionFromIndex(li_->getDefIndex(LRStart));
743 if (DefMI && DefMI != CopyMI) {
744 int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg, false, tri_);
746 DefMI->getOperand(DeadIdx).setIsDead();
747 // A dead def should have a single cycle interval.
753 /// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply
754 /// fallthoughs to SuccMBB.
755 static bool isSameOrFallThroughBB(MachineBasicBlock *MBB,
756 MachineBasicBlock *SuccMBB,
757 const TargetInstrInfo *tii_) {
760 MachineBasicBlock *TBB = 0, *FBB = 0;
761 SmallVector<MachineOperand, 4> Cond;
762 return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB &&
763 MBB->isSuccessor(SuccMBB);
766 /// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially
767 /// extended by a dead copy. Mark the last use (if any) of the val# as kill as
768 /// ends the live range there. If there isn't another use, then this live range
769 /// is dead. Return true if live interval is removed.
771 SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li,
772 MachineInstr *CopyMI) {
773 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
775 // FIXME: special case: function live in. It can be a general case if the
776 // first instruction index starts at > 0 value.
777 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
778 // Live-in to the function but dead. Remove it from entry live-in set.
779 if (mf_->begin()->isLiveIn(li.reg))
780 mf_->begin()->removeLiveIn(li.reg);
781 const LiveRange *LR = li.getLiveRangeContaining(CopyIdx);
782 removeRange(li, LR->start, LR->end, li_, tri_);
783 return removeIntervalIfEmpty(li, li_, tri_);
786 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx-1);
788 // Livein but defined by a phi.
791 unsigned RemoveStart = LR->start;
792 unsigned RemoveEnd = li_->getDefIndex(CopyIdx)+1;
793 if (LR->end > RemoveEnd)
794 // More uses past this copy? Nothing to do.
797 MachineBasicBlock *CopyMBB = CopyMI->getParent();
798 unsigned MBBStart = li_->getMBBStartIdx(CopyMBB);
800 MachineOperand *LastUse = lastRegisterUse(LR->start, CopyIdx-1, li.reg,
803 MachineInstr *LastUseMI = LastUse->getParent();
804 if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) {
811 // r1025<dead> = r1024<kill>
812 if (MBBStart < LR->end)
813 removeRange(li, MBBStart, LR->end, li_, tri_);
817 // There are uses before the copy, just shorten the live range to the end
819 LastUse->setIsKill();
820 removeRange(li, li_->getDefIndex(LastUseIdx), LR->end, li_, tri_);
821 unsigned SrcReg, DstReg;
822 if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg) &&
824 // Last use is itself an identity code.
825 int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg, false, tri_);
826 LastUseMI->getOperand(DeadIdx).setIsDead();
832 if (LR->start <= MBBStart && LR->end > MBBStart) {
833 if (LR->start == 0) {
834 assert(TargetRegisterInfo::isPhysicalRegister(li.reg));
835 // Live-in to the function but dead. Remove it from entry live-in set.
836 mf_->begin()->removeLiveIn(li.reg);
838 // FIXME: Shorten intervals in BBs that reaches this BB.
841 if (LR->valno->def == RemoveStart)
842 // If the def MI defines the val#, propagate the dead marker.
843 PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_);
845 removeRange(li, RemoveStart, LR->end, li_, tri_);
846 return removeIntervalIfEmpty(li, li_, tri_);
849 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
850 /// from an implicit def to another register can be coalesced away.
851 bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI,
853 LiveInterval &ImpLi) const{
854 if (!CopyMI->killsRegister(ImpLi.reg))
856 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
857 LiveInterval::iterator LR = li.FindLiveRangeContaining(CopyIdx);
860 if (LR->valno->hasPHIKill)
862 if (LR->valno->def != CopyIdx)
864 // Make sure all of val# uses are copies.
865 for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(li.reg),
866 UE = mri_->use_end(); UI != UE;) {
867 MachineInstr *UseMI = &*UI;
869 if (JoinedCopies.count(UseMI))
871 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(UseMI));
872 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
873 if (ULR == li.end() || ULR->valno != LR->valno)
875 // If the use is not a use, then it's not safe to coalesce the move.
876 unsigned SrcReg, DstReg;
877 if (!tii_->isMoveInstr(*UseMI, SrcReg, DstReg)) {
878 if (UseMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG &&
879 UseMI->getOperand(1).getReg() == li.reg)
888 /// RemoveCopiesFromValNo - The specified value# is defined by an implicit
889 /// def and it is being removed. Turn all copies from this value# into
890 /// identity copies so they will be removed.
891 void SimpleRegisterCoalescing::RemoveCopiesFromValNo(LiveInterval &li,
893 SmallVector<MachineInstr*, 4> ImpDefs;
894 MachineOperand *LastUse = NULL;
895 unsigned LastUseIdx = li_->getUseIndex(VNI->def);
896 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg),
897 RE = mri_->reg_end(); RI != RE;) {
898 MachineOperand *MO = &RI.getOperand();
899 MachineInstr *MI = &*RI;
902 if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
903 ImpDefs.push_back(MI);
907 if (JoinedCopies.count(MI))
909 unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(MI));
910 LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
911 if (ULR == li.end() || ULR->valno != VNI)
913 // If the use is a copy, turn it into an identity copy.
914 unsigned SrcReg, DstReg;
915 if (tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == li.reg) {
916 // Each use MI may have multiple uses of this register. Change them all.
917 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
918 MachineOperand &MO = MI->getOperand(i);
919 if (MO.isReg() && MO.getReg() == li.reg)
922 JoinedCopies.insert(MI);
923 } else if (UseIdx > LastUseIdx) {
929 LastUse->setIsKill();
931 // Remove dead implicit_def's.
932 while (!ImpDefs.empty()) {
933 MachineInstr *ImpDef = ImpDefs.back();
935 li_->RemoveMachineInstrFromMaps(ImpDef);
936 ImpDef->eraseFromParent();
941 /// getMatchingSuperReg - Return a super-register of the specified register
942 /// Reg so its sub-register of index SubIdx is Reg.
943 static unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
944 const TargetRegisterClass *RC,
945 const TargetRegisterInfo* TRI) {
946 for (const unsigned *SRs = TRI->getSuperRegisters(Reg);
947 unsigned SR = *SRs; ++SRs)
948 if (Reg == TRI->getSubReg(SR, SubIdx) && RC->contains(SR))
953 /// isProfitableToCoalesceToSubRC - Given that register class of DstReg is
954 /// a subset of the register class of SrcReg, return true if it's profitable
955 /// to coalesce the two registers.
957 SimpleRegisterCoalescing::isProfitableToCoalesceToSubRC(unsigned SrcReg,
959 MachineBasicBlock *MBB){
963 // First let's make sure all uses are in the same MBB.
964 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(SrcReg),
965 RE = mri_->reg_end(); RI != RE; ++RI) {
966 MachineInstr &MI = *RI;
967 if (MI.getParent() != MBB)
970 for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(DstReg),
971 RE = mri_->reg_end(); RI != RE; ++RI) {
972 MachineInstr &MI = *RI;
973 if (MI.getParent() != MBB)
977 // Then make sure the intervals are *short*.
978 LiveInterval &SrcInt = li_->getInterval(SrcReg);
979 LiveInterval &DstInt = li_->getInterval(DstReg);
980 unsigned SrcSize = li_->getApproximateInstructionCount(SrcInt);
981 unsigned DstSize = li_->getApproximateInstructionCount(DstInt);
982 const TargetRegisterClass *RC = mri_->getRegClass(DstReg);
983 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
984 return (SrcSize + DstSize) <= Threshold;
987 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
988 /// register with a physical register, check if any of the virtual register
989 /// operand is a sub-register use or def. If so, make sure it won't result
990 /// in an illegal extract_subreg or insert_subreg instruction. e.g.
991 /// vr1024 = extract_subreg vr1025, 1
993 /// vr1024 = mov8rr AH
994 /// If vr1024 is coalesced with AH, the extract_subreg is now illegal since
995 /// AH does not have a super-reg whose sub-register 1 is AH.
997 SimpleRegisterCoalescing::HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
1000 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(VirtReg),
1001 E = mri_->reg_end(); I != E; ++I) {
1002 MachineOperand &O = I.getOperand();
1003 MachineInstr *MI = &*I;
1004 if (MI == CopyMI || JoinedCopies.count(MI))
1006 unsigned SubIdx = O.getSubReg();
1007 if (SubIdx && !tri_->getSubReg(PhysReg, SubIdx))
1009 if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
1010 SubIdx = MI->getOperand(2).getImm();
1011 if (O.isUse() && !tri_->getSubReg(PhysReg, SubIdx))
1014 unsigned SrcReg = MI->getOperand(1).getReg();
1015 const TargetRegisterClass *RC =
1016 TargetRegisterInfo::isPhysicalRegister(SrcReg)
1017 ? tri_->getPhysicalRegisterRegClass(SrcReg)
1018 : mri_->getRegClass(SrcReg);
1019 if (!getMatchingSuperReg(PhysReg, SubIdx, RC, tri_))
1023 if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
1024 SubIdx = MI->getOperand(3).getImm();
1025 if (VirtReg == MI->getOperand(0).getReg()) {
1026 if (!tri_->getSubReg(PhysReg, SubIdx))
1029 unsigned DstReg = MI->getOperand(0).getReg();
1030 const TargetRegisterClass *RC =
1031 TargetRegisterInfo::isPhysicalRegister(DstReg)
1032 ? tri_->getPhysicalRegisterRegClass(DstReg)
1033 : mri_->getRegClass(DstReg);
1034 if (!getMatchingSuperReg(PhysReg, SubIdx, RC, tri_))
1043 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
1044 /// which are the src/dst of the copy instruction CopyMI. This returns true
1045 /// if the copy was successfully coalesced away. If it is not currently
1046 /// possible to coalesce this interval, but it may be possible if other
1047 /// things get coalesced, then it returns true by reference in 'Again'.
1048 bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
1049 MachineInstr *CopyMI = TheCopy.MI;
1052 if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
1053 return false; // Already done.
1055 DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
1059 bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
1060 bool isInsSubReg = CopyMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG;
1061 unsigned SubIdx = 0;
1063 DstReg = CopyMI->getOperand(0).getReg();
1064 SrcReg = CopyMI->getOperand(1).getReg();
1065 } else if (isInsSubReg) {
1066 if (CopyMI->getOperand(2).getSubReg()) {
1067 DOUT << "\tSource of insert_subreg is already coalesced "
1068 << "to another register.\n";
1069 return false; // Not coalescable.
1071 DstReg = CopyMI->getOperand(0).getReg();
1072 SrcReg = CopyMI->getOperand(2).getReg();
1073 } else if (!tii_->isMoveInstr(*CopyMI, SrcReg, DstReg)) {
1074 assert(0 && "Unrecognized copy instruction!");
1078 // If they are already joined we continue.
1079 if (SrcReg == DstReg) {
1080 DOUT << "\tCopy already coalesced.\n";
1081 return false; // Not coalescable.
1084 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
1085 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
1087 // If they are both physical registers, we cannot join them.
1088 if (SrcIsPhys && DstIsPhys) {
1089 DOUT << "\tCan not coalesce physregs.\n";
1090 return false; // Not coalescable.
1093 // We only join virtual registers with allocatable physical registers.
1094 if (SrcIsPhys && !allocatableRegs_[SrcReg]) {
1095 DOUT << "\tSrc reg is unallocatable physreg.\n";
1096 return false; // Not coalescable.
1098 if (DstIsPhys && !allocatableRegs_[DstReg]) {
1099 DOUT << "\tDst reg is unallocatable physreg.\n";
1100 return false; // Not coalescable.
1103 // Should be non-null only when coalescing to a sub-register class.
1104 const TargetRegisterClass *SubRC = NULL;
1105 MachineBasicBlock *CopyMBB = CopyMI->getParent();
1106 unsigned RealDstReg = 0;
1107 unsigned RealSrcReg = 0;
1108 if (isExtSubReg || isInsSubReg) {
1109 SubIdx = CopyMI->getOperand(isExtSubReg ? 2 : 3).getImm();
1110 if (SrcIsPhys && isExtSubReg) {
1111 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
1112 // coalesced with AX.
1113 unsigned DstSubIdx = CopyMI->getOperand(0).getSubReg();
1115 // r1024<2> = EXTRACT_SUBREG EAX, 2. Then r1024 has already been
1116 // coalesced to a larger register so the subreg indices cancel out.
1117 if (DstSubIdx != SubIdx) {
1118 DOUT << "\t Sub-register indices mismatch.\n";
1119 return false; // Not coalescable.
1122 SrcReg = tri_->getSubReg(SrcReg, SubIdx);
1124 } else if (DstIsPhys && isInsSubReg) {
1125 // EAX = INSERT_SUBREG EAX, r1024, 0
1126 unsigned SrcSubIdx = CopyMI->getOperand(2).getSubReg();
1128 // EAX = INSERT_SUBREG EAX, r1024<2>, 2 Then r1024 has already been
1129 // coalesced to a larger register so the subreg indices cancel out.
1130 if (SrcSubIdx != SubIdx) {
1131 DOUT << "\t Sub-register indices mismatch.\n";
1132 return false; // Not coalescable.
1135 DstReg = tri_->getSubReg(DstReg, SubIdx);
1137 } else if ((DstIsPhys && isExtSubReg) || (SrcIsPhys && isInsSubReg)) {
1138 // If this is a extract_subreg where dst is a physical register, e.g.
1139 // cl = EXTRACT_SUBREG reg1024, 1
1140 // then create and update the actual physical register allocated to RHS.
1142 // reg1024 = INSERT_SUBREG r1024, cl, 1
1143 if (CopyMI->getOperand(1).getSubReg()) {
1144 DOUT << "\tSrc of extract_ / insert_subreg already coalesced with reg"
1145 << " of a super-class.\n";
1146 return false; // Not coalescable.
1148 const TargetRegisterClass *RC =
1149 mri_->getRegClass(isExtSubReg ? SrcReg : DstReg);
1151 RealDstReg = getMatchingSuperReg(DstReg, SubIdx, RC, tri_);
1152 assert(RealDstReg && "Invalid extract_subreg instruction!");
1154 RealSrcReg = getMatchingSuperReg(SrcReg, SubIdx, RC, tri_);
1155 assert(RealSrcReg && "Invalid extract_subreg instruction!");
1158 // For this type of EXTRACT_SUBREG, conservatively
1159 // check if the live interval of the source register interfere with the
1160 // actual super physical register we are trying to coalesce with.
1161 unsigned PhysReg = isExtSubReg ? RealDstReg : RealSrcReg;
1162 LiveInterval &RHS = li_->getInterval(isExtSubReg ? SrcReg : DstReg);
1163 if (li_->hasInterval(PhysReg) &&
1164 RHS.overlaps(li_->getInterval(PhysReg))) {
1165 DOUT << "Interfere with register ";
1166 DEBUG(li_->getInterval(PhysReg).print(DOUT, tri_));
1167 return false; // Not coalescable
1169 for (const unsigned* SR = tri_->getSubRegisters(PhysReg); *SR; ++SR)
1170 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1171 DOUT << "Interfere with sub-register ";
1172 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1173 return false; // Not coalescable
1177 unsigned OldSubIdx = isExtSubReg ? CopyMI->getOperand(0).getSubReg()
1178 : CopyMI->getOperand(2).getSubReg();
1180 if (OldSubIdx == SubIdx &&
1181 !differingRegisterClasses(SrcReg, DstReg, SubRC))
1182 // r1024<2> = EXTRACT_SUBREG r1025, 2. Then r1024 has already been
1183 // coalesced to a larger register so the subreg indices cancel out.
1184 // Also check if the other larger register is of the same register
1185 // class as the would be resulting register.
1188 DOUT << "\t Sub-register indices mismatch.\n";
1189 return false; // Not coalescable.
1193 unsigned LargeReg = isExtSubReg ? SrcReg : DstReg;
1194 unsigned SmallReg = isExtSubReg ? DstReg : SrcReg;
1195 unsigned LargeRegSize =
1196 li_->getApproximateInstructionCount(li_->getInterval(LargeReg));
1197 unsigned SmallRegSize =
1198 li_->getApproximateInstructionCount(li_->getInterval(SmallReg));
1199 const TargetRegisterClass *RC = mri_->getRegClass(SmallReg);
1200 unsigned Threshold = allocatableRCRegs_[RC].count();
1201 // Be conservative. If both sides are virtual registers, do not coalesce
1202 // if this will cause a high use density interval to target a smaller
1203 // set of registers.
1204 if (SmallRegSize > Threshold || LargeRegSize > Threshold) {
1205 if ((float)std::distance(mri_->use_begin(SmallReg),
1206 mri_->use_end()) / SmallRegSize <
1207 (float)std::distance(mri_->use_begin(LargeReg),
1208 mri_->use_end()) / LargeRegSize) {
1209 Again = true; // May be possible to coalesce later.
1215 } else if (differingRegisterClasses(SrcReg, DstReg, SubRC)) {
1216 // FIXME: What if the resul of a EXTRACT_SUBREG is then coalesced
1217 // with another? If it's the resulting destination register, then
1218 // the subidx must be propagated to uses (but only those defined
1219 // by the EXTRACT_SUBREG). If it's being coalesced into another
1220 // register, it should be safe because register is assumed to have
1221 // the register class of the super-register.
1223 if (!SubRC || !isProfitableToCoalesceToSubRC(SrcReg, DstReg, CopyMBB)) {
1224 // If they are not of the same register class, we cannot join them.
1225 DOUT << "\tSrc/Dest are different register classes.\n";
1226 // Allow the coalescer to try again in case either side gets coalesced to
1227 // a physical register that's compatible with the other side. e.g.
1228 // r1024 = MOV32to32_ r1025
1229 // but later r1024 is assigned EAX then r1025 may be coalesced with EAX.
1230 Again = true; // May be possible to coalesce later.
1235 // Will it create illegal extract_subreg / insert_subreg?
1236 if (SrcIsPhys && HasIncompatibleSubRegDefUse(CopyMI, DstReg, SrcReg))
1238 if (DstIsPhys && HasIncompatibleSubRegDefUse(CopyMI, SrcReg, DstReg))
1241 LiveInterval &SrcInt = li_->getInterval(SrcReg);
1242 LiveInterval &DstInt = li_->getInterval(DstReg);
1243 assert(SrcInt.reg == SrcReg && DstInt.reg == DstReg &&
1244 "Register mapping is horribly broken!");
1246 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, tri_);
1247 DOUT << " and "; DstInt.print(DOUT, tri_);
1250 // Check if it is necessary to propagate "isDead" property.
1251 if (!isExtSubReg && !isInsSubReg) {
1252 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg, false);
1253 bool isDead = mopd->isDead();
1255 // We need to be careful about coalescing a source physical register with a
1256 // virtual register. Once the coalescing is done, it cannot be broken and
1257 // these are not spillable! If the destination interval uses are far away,
1258 // think twice about coalescing them!
1259 if (!isDead && (SrcIsPhys || DstIsPhys)) {
1260 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
1261 unsigned JoinVReg = SrcIsPhys ? DstReg : SrcReg;
1262 unsigned JoinPReg = SrcIsPhys ? SrcReg : DstReg;
1263 const TargetRegisterClass *RC = mri_->getRegClass(JoinVReg);
1264 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
1265 if (TheCopy.isBackEdge)
1266 Threshold *= 2; // Favors back edge copies.
1268 // If the virtual register live interval is long but it has low use desity,
1269 // do not join them, instead mark the physical register as its allocation
1271 unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
1272 if (Length > Threshold &&
1273 (((float)std::distance(mri_->use_begin(JoinVReg), mri_->use_end())
1274 / Length) < (1.0 / Threshold))) {
1275 JoinVInt.preference = JoinPReg;
1277 DOUT << "\tMay tie down a physical register, abort!\n";
1278 Again = true; // May be possible to coalesce later.
1284 // Okay, attempt to join these two intervals. On failure, this returns false.
1285 // Otherwise, if one of the intervals being joined is a physreg, this method
1286 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
1287 // been modified, so we can use this information below to update aliases.
1288 bool Swapped = false;
1289 // If SrcInt is implicitly defined, it's safe to coalesce.
1290 bool isEmpty = SrcInt.empty();
1291 if (isEmpty && !CanCoalesceWithImpDef(CopyMI, DstInt, SrcInt)) {
1292 // Only coalesce an empty interval (defined by implicit_def) with
1293 // another interval which has a valno defined by the CopyMI and the CopyMI
1294 // is a kill of the implicit def.
1295 DOUT << "Not profitable!\n";
1299 if (!isEmpty && !JoinIntervals(DstInt, SrcInt, Swapped)) {
1300 // Coalescing failed.
1302 // If definition of source is defined by trivial computation, try
1303 // rematerializing it.
1304 if (!isExtSubReg && !isInsSubReg &&
1305 ReMaterializeTrivialDef(SrcInt, DstInt.reg, CopyMI))
1308 // If we can eliminate the copy without merging the live ranges, do so now.
1309 if (!isExtSubReg && !isInsSubReg &&
1310 (AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI) ||
1311 RemoveCopyByCommutingDef(SrcInt, DstInt, CopyMI))) {
1312 JoinedCopies.insert(CopyMI);
1316 // Otherwise, we are unable to join the intervals.
1317 DOUT << "Interference!\n";
1318 Again = true; // May be possible to coalesce later.
1322 LiveInterval *ResSrcInt = &SrcInt;
1323 LiveInterval *ResDstInt = &DstInt;
1325 std::swap(SrcReg, DstReg);
1326 std::swap(ResSrcInt, ResDstInt);
1328 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) &&
1329 "LiveInterval::join didn't work right!");
1331 // If we're about to merge live ranges into a physical register live interval,
1332 // we have to update any aliased register's live ranges to indicate that they
1333 // have clobbered values for this range.
1334 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) {
1335 // If this is a extract_subreg where dst is a physical register, e.g.
1336 // cl = EXTRACT_SUBREG reg1024, 1
1337 // then create and update the actual physical register allocated to RHS.
1338 if (RealDstReg || RealSrcReg) {
1339 LiveInterval &RealInt =
1340 li_->getOrCreateInterval(RealDstReg ? RealDstReg : RealSrcReg);
1341 SmallSet<const VNInfo*, 4> CopiedValNos;
1342 for (LiveInterval::Ranges::const_iterator I = ResSrcInt->ranges.begin(),
1343 E = ResSrcInt->ranges.end(); I != E; ++I) {
1344 const LiveRange *DstLR = ResDstInt->getLiveRangeContaining(I->start);
1345 assert(DstLR && "Invalid joined interval!");
1346 const VNInfo *DstValNo = DstLR->valno;
1347 if (CopiedValNos.insert(DstValNo)) {
1348 VNInfo *ValNo = RealInt.getNextValue(DstValNo->def, DstValNo->copy,
1349 li_->getVNInfoAllocator());
1350 ValNo->hasPHIKill = DstValNo->hasPHIKill;
1351 RealInt.addKills(ValNo, DstValNo->kills);
1352 RealInt.MergeValueInAsValue(*ResDstInt, DstValNo, ValNo);
1356 DstReg = RealDstReg ? RealDstReg : RealSrcReg;
1359 // Update the liveintervals of sub-registers.
1360 for (const unsigned *AS = tri_->getSubRegisters(DstReg); *AS; ++AS)
1361 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt,
1362 li_->getVNInfoAllocator());
1365 // If this is a EXTRACT_SUBREG, make sure the result of coalescing is the
1366 // larger super-register.
1367 if ((isExtSubReg || isInsSubReg) && !SrcIsPhys && !DstIsPhys) {
1368 if ((isExtSubReg && !Swapped) || (isInsSubReg && Swapped)) {
1369 ResSrcInt->Copy(*ResDstInt, li_->getVNInfoAllocator());
1370 std::swap(SrcReg, DstReg);
1371 std::swap(ResSrcInt, ResDstInt);
1375 // Coalescing to a virtual register that is of a sub-register class of the
1376 // other. Make sure the resulting register is set to the right register class.
1378 mri_->setRegClass(DstReg, SubRC);
1383 // Add all copies that define val# in the source interval into the queue.
1384 for (LiveInterval::const_vni_iterator i = ResSrcInt->vni_begin(),
1385 e = ResSrcInt->vni_end(); i != e; ++i) {
1386 const VNInfo *vni = *i;
1387 if (!vni->def || vni->def == ~1U || vni->def == ~0U)
1389 MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
1390 unsigned NewSrcReg, NewDstReg;
1392 JoinedCopies.count(CopyMI) == 0 &&
1393 tii_->isMoveInstr(*CopyMI, NewSrcReg, NewDstReg)) {
1394 unsigned LoopDepth = loopInfo->getLoopDepth(CopyMBB);
1395 JoinQueue->push(CopyRec(CopyMI, LoopDepth,
1396 isBackEdgeCopy(CopyMI, DstReg)));
1401 // Remember to delete the copy instruction.
1402 JoinedCopies.insert(CopyMI);
1404 // Some live range has been lengthened due to colaescing, eliminate the
1405 // unnecessary kills.
1406 RemoveUnnecessaryKills(SrcReg, *ResDstInt);
1407 if (TargetRegisterInfo::isVirtualRegister(DstReg))
1408 RemoveUnnecessaryKills(DstReg, *ResDstInt);
1413 // r1024 = implicit_def
1416 RemoveDeadImpDef(DstReg, *ResDstInt);
1417 UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
1419 // SrcReg is guarateed to be the register whose live interval that is
1421 li_->removeInterval(SrcReg);
1424 // Now the copy is being coalesced away, the val# previously defined
1425 // by the copy is being defined by an IMPLICIT_DEF which defines a zero
1426 // length interval. Remove the val#.
1427 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
1428 const LiveRange *LR = ResDstInt->getLiveRangeContaining(CopyIdx);
1429 VNInfo *ImpVal = LR->valno;
1430 assert(ImpVal->def == CopyIdx);
1431 unsigned NextDef = LR->end;
1432 RemoveCopiesFromValNo(*ResDstInt, ImpVal);
1433 ResDstInt->removeValNo(ImpVal);
1434 LR = ResDstInt->FindLiveRangeContaining(NextDef);
1435 if (LR != ResDstInt->end() && LR->valno->def == NextDef) {
1436 // Special case: vr1024 = implicit_def
1437 // vr1024 = insert_subreg vr1024, vr1025, c
1438 // The insert_subreg becomes a "copy" that defines a val# which can itself
1439 // be coalesced away.
1440 MachineInstr *DefMI = li_->getInstructionFromIndex(NextDef);
1441 if (DefMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG)
1442 LR->valno->copy = DefMI;
1446 // If resulting interval has a preference that no longer fits because of subreg
1447 // coalescing, just clear the preference.
1448 if (ResDstInt->preference && (isExtSubReg || isInsSubReg) &&
1449 TargetRegisterInfo::isVirtualRegister(ResDstInt->reg)) {
1450 const TargetRegisterClass *RC = mri_->getRegClass(ResDstInt->reg);
1451 if (!RC->contains(ResDstInt->preference))
1452 ResDstInt->preference = 0;
1455 DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, tri_);
1462 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
1463 /// compute what the resultant value numbers for each value in the input two
1464 /// ranges will be. This is complicated by copies between the two which can
1465 /// and will commonly cause multiple value numbers to be merged into one.
1467 /// VN is the value number that we're trying to resolve. InstDefiningValue
1468 /// keeps track of the new InstDefiningValue assignment for the result
1469 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
1470 /// whether a value in this or other is a copy from the opposite set.
1471 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
1472 /// already been assigned.
1474 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
1475 /// contains the value number the copy is from.
1477 static unsigned ComputeUltimateVN(VNInfo *VNI,
1478 SmallVector<VNInfo*, 16> &NewVNInfo,
1479 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
1480 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
1481 SmallVector<int, 16> &ThisValNoAssignments,
1482 SmallVector<int, 16> &OtherValNoAssignments) {
1483 unsigned VN = VNI->id;
1485 // If the VN has already been computed, just return it.
1486 if (ThisValNoAssignments[VN] >= 0)
1487 return ThisValNoAssignments[VN];
1488 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
1490 // If this val is not a copy from the other val, then it must be a new value
1491 // number in the destination.
1492 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
1493 if (I == ThisFromOther.end()) {
1494 NewVNInfo.push_back(VNI);
1495 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
1497 VNInfo *OtherValNo = I->second;
1499 // Otherwise, this *is* a copy from the RHS. If the other side has already
1500 // been computed, return it.
1501 if (OtherValNoAssignments[OtherValNo->id] >= 0)
1502 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
1504 // Mark this value number as currently being computed, then ask what the
1505 // ultimate value # of the other value is.
1506 ThisValNoAssignments[VN] = -2;
1507 unsigned UltimateVN =
1508 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
1509 OtherValNoAssignments, ThisValNoAssignments);
1510 return ThisValNoAssignments[VN] = UltimateVN;
1513 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
1514 return std::find(V.begin(), V.end(), Val) != V.end();
1517 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
1518 /// the specified live interval is defined by a copy from the specified
1520 bool SimpleRegisterCoalescing::RangeIsDefinedByCopyFromReg(LiveInterval &li,
1523 unsigned SrcReg = li_->getVNInfoSourceReg(LR->valno);
1526 if (LR->valno->def == ~0U &&
1527 TargetRegisterInfo::isPhysicalRegister(li.reg) &&
1528 *tri_->getSuperRegisters(li.reg)) {
1529 // It's a sub-register live interval, we may not have precise information.
1531 MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start);
1532 unsigned SrcReg, DstReg;
1533 if (DefMI && tii_->isMoveInstr(*DefMI, SrcReg, DstReg) &&
1534 DstReg == li.reg && SrcReg == Reg) {
1535 // Cache computed info.
1536 LR->valno->def = LR->start;
1537 LR->valno->copy = DefMI;
1544 /// SimpleJoin - Attempt to joint the specified interval into this one. The
1545 /// caller of this method must guarantee that the RHS only contains a single
1546 /// value number and that the RHS is not defined by a copy from this
1547 /// interval. This returns false if the intervals are not joinable, or it
1548 /// joins them and returns true.
1549 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS){
1550 assert(RHS.containsOneValue());
1552 // Some number (potentially more than one) value numbers in the current
1553 // interval may be defined as copies from the RHS. Scan the overlapping
1554 // portions of the LHS and RHS, keeping track of this and looking for
1555 // overlapping live ranges that are NOT defined as copies. If these exist, we
1558 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
1559 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
1561 if (LHSIt->start < RHSIt->start) {
1562 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
1563 if (LHSIt != LHS.begin()) --LHSIt;
1564 } else if (RHSIt->start < LHSIt->start) {
1565 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
1566 if (RHSIt != RHS.begin()) --RHSIt;
1569 SmallVector<VNInfo*, 8> EliminatedLHSVals;
1572 // Determine if these live intervals overlap.
1573 bool Overlaps = false;
1574 if (LHSIt->start <= RHSIt->start)
1575 Overlaps = LHSIt->end > RHSIt->start;
1577 Overlaps = RHSIt->end > LHSIt->start;
1579 // If the live intervals overlap, there are two interesting cases: if the
1580 // LHS interval is defined by a copy from the RHS, it's ok and we record
1581 // that the LHS value # is the same as the RHS. If it's not, then we cannot
1582 // coalesce these live ranges and we bail out.
1584 // If we haven't already recorded that this value # is safe, check it.
1585 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
1586 // Copy from the RHS?
1587 if (!RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg))
1588 return false; // Nope, bail out.
1590 if (LHSIt->contains(RHSIt->valno->def))
1591 // Here is an interesting situation:
1593 // vr1025 = copy vr1024
1598 // Even though vr1025 is copied from vr1024, it's not safe to
1599 // coalesced them since live range of vr1025 intersects the
1600 // def of vr1024. This happens because vr1025 is assigned the
1601 // value of the previous iteration of vr1024.
1603 EliminatedLHSVals.push_back(LHSIt->valno);
1606 // We know this entire LHS live range is okay, so skip it now.
1607 if (++LHSIt == LHSEnd) break;
1611 if (LHSIt->end < RHSIt->end) {
1612 if (++LHSIt == LHSEnd) break;
1614 // One interesting case to check here. It's possible that we have
1615 // something like "X3 = Y" which defines a new value number in the LHS,
1616 // and is the last use of this liverange of the RHS. In this case, we
1617 // want to notice this copy (so that it gets coalesced away) even though
1618 // the live ranges don't actually overlap.
1619 if (LHSIt->start == RHSIt->end) {
1620 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
1621 // We already know that this value number is going to be merged in
1622 // if coalescing succeeds. Just skip the liverange.
1623 if (++LHSIt == LHSEnd) break;
1625 // Otherwise, if this is a copy from the RHS, mark it as being merged
1627 if (RangeIsDefinedByCopyFromReg(LHS, LHSIt, RHS.reg)) {
1628 if (LHSIt->contains(RHSIt->valno->def))
1629 // Here is an interesting situation:
1631 // vr1025 = copy vr1024
1636 // Even though vr1025 is copied from vr1024, it's not safe to
1637 // coalesced them since live range of vr1025 intersects the
1638 // def of vr1024. This happens because vr1025 is assigned the
1639 // value of the previous iteration of vr1024.
1641 EliminatedLHSVals.push_back(LHSIt->valno);
1643 // We know this entire LHS live range is okay, so skip it now.
1644 if (++LHSIt == LHSEnd) break;
1649 if (++RHSIt == RHSEnd) break;
1653 // If we got here, we know that the coalescing will be successful and that
1654 // the value numbers in EliminatedLHSVals will all be merged together. Since
1655 // the most common case is that EliminatedLHSVals has a single number, we
1656 // optimize for it: if there is more than one value, we merge them all into
1657 // the lowest numbered one, then handle the interval as if we were merging
1658 // with one value number.
1659 VNInfo *LHSValNo = NULL;
1660 if (EliminatedLHSVals.size() > 1) {
1661 // Loop through all the equal value numbers merging them into the smallest
1663 VNInfo *Smallest = EliminatedLHSVals[0];
1664 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
1665 if (EliminatedLHSVals[i]->id < Smallest->id) {
1666 // Merge the current notion of the smallest into the smaller one.
1667 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
1668 Smallest = EliminatedLHSVals[i];
1670 // Merge into the smallest.
1671 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
1674 LHSValNo = Smallest;
1675 } else if (EliminatedLHSVals.empty()) {
1676 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
1677 *tri_->getSuperRegisters(LHS.reg))
1678 // Imprecise sub-register information. Can't handle it.
1680 assert(0 && "No copies from the RHS?");
1682 LHSValNo = EliminatedLHSVals[0];
1685 // Okay, now that there is a single LHS value number that we're merging the
1686 // RHS into, update the value number info for the LHS to indicate that the
1687 // value number is defined where the RHS value number was.
1688 const VNInfo *VNI = RHS.getValNumInfo(0);
1689 LHSValNo->def = VNI->def;
1690 LHSValNo->copy = VNI->copy;
1692 // Okay, the final step is to loop over the RHS live intervals, adding them to
1694 LHSValNo->hasPHIKill |= VNI->hasPHIKill;
1695 LHS.addKills(LHSValNo, VNI->kills);
1696 LHS.MergeRangesInAsValue(RHS, LHSValNo);
1697 LHS.weight += RHS.weight;
1698 if (RHS.preference && !LHS.preference)
1699 LHS.preference = RHS.preference;
1704 /// JoinIntervals - Attempt to join these two intervals. On failure, this
1705 /// returns false. Otherwise, if one of the intervals being joined is a
1706 /// physreg, this method always canonicalizes LHS to be it. The output
1707 /// "RHS" will not have been modified, so we can use this information
1708 /// below to update aliases.
1710 SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS, LiveInterval &RHS,
1712 // Compute the final value assignment, assuming that the live ranges can be
1714 SmallVector<int, 16> LHSValNoAssignments;
1715 SmallVector<int, 16> RHSValNoAssignments;
1716 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
1717 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
1718 SmallVector<VNInfo*, 16> NewVNInfo;
1720 // If a live interval is a physical register, conservatively check if any
1721 // of its sub-registers is overlapping the live interval of the virtual
1722 // register. If so, do not coalesce.
1723 if (TargetRegisterInfo::isPhysicalRegister(LHS.reg) &&
1724 *tri_->getSubRegisters(LHS.reg)) {
1725 // If it's coalescing a virtual register to a physical register, estimate
1726 // its live interval length. This is the *cost* of scanning an entire live
1727 // interval. If the cost is low, we'll do an exhaustive check instead.
1729 // If this is something like this:
1737 // That is, the live interval of v1024 crosses a bb. Then we can't rely on
1738 // less conservative check. It's possible a sub-register is defined before
1739 // v1024 (or live in) and live out of BB1.
1740 if (RHS.containsOneValue() &&
1741 li_->intervalIsInOneMBB(RHS) &&
1742 li_->getApproximateInstructionCount(RHS) <= 10) {
1743 // Perform a more exhaustive check for some common cases.
1744 if (li_->conflictsWithPhysRegRef(RHS, LHS.reg, true, JoinedCopies))
1747 for (const unsigned* SR = tri_->getSubRegisters(LHS.reg); *SR; ++SR)
1748 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
1749 DOUT << "Interfere with sub-register ";
1750 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1754 } else if (TargetRegisterInfo::isPhysicalRegister(RHS.reg) &&
1755 *tri_->getSubRegisters(RHS.reg)) {
1756 if (LHS.containsOneValue() &&
1757 li_->getApproximateInstructionCount(LHS) <= 10) {
1758 // Perform a more exhaustive check for some common cases.
1759 if (li_->conflictsWithPhysRegRef(LHS, RHS.reg, false, JoinedCopies))
1762 for (const unsigned* SR = tri_->getSubRegisters(RHS.reg); *SR; ++SR)
1763 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
1764 DOUT << "Interfere with sub-register ";
1765 DEBUG(li_->getInterval(*SR).print(DOUT, tri_));
1771 // Compute ultimate value numbers for the LHS and RHS values.
1772 if (RHS.containsOneValue()) {
1773 // Copies from a liveinterval with a single value are simple to handle and
1774 // very common, handle the special case here. This is important, because
1775 // often RHS is small and LHS is large (e.g. a physreg).
1777 // Find out if the RHS is defined as a copy from some value in the LHS.
1778 int RHSVal0DefinedFromLHS = -1;
1780 VNInfo *RHSValNoInfo = NULL;
1781 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
1782 unsigned RHSSrcReg = li_->getVNInfoSourceReg(RHSValNoInfo0);
1783 if (RHSSrcReg == 0 || RHSSrcReg != LHS.reg) {
1784 // If RHS is not defined as a copy from the LHS, we can use simpler and
1785 // faster checks to see if the live ranges are coalescable. This joiner
1786 // can't swap the LHS/RHS intervals though.
1787 if (!TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
1788 return SimpleJoin(LHS, RHS);
1790 RHSValNoInfo = RHSValNoInfo0;
1793 // It was defined as a copy from the LHS, find out what value # it is.
1794 RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno;
1795 RHSValID = RHSValNoInfo->id;
1796 RHSVal0DefinedFromLHS = RHSValID;
1799 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1800 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1801 NewVNInfo.resize(LHS.getNumValNums(), NULL);
1803 // Okay, *all* of the values in LHS that are defined as a copy from RHS
1804 // should now get updated.
1805 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1808 unsigned VN = VNI->id;
1809 if (unsigned LHSSrcReg = li_->getVNInfoSourceReg(VNI)) {
1810 if (LHSSrcReg != RHS.reg) {
1811 // If this is not a copy from the RHS, its value number will be
1812 // unmodified by the coalescing.
1813 NewVNInfo[VN] = VNI;
1814 LHSValNoAssignments[VN] = VN;
1815 } else if (RHSValID == -1) {
1816 // Otherwise, it is a copy from the RHS, and we don't already have a
1817 // value# for it. Keep the current value number, but remember it.
1818 LHSValNoAssignments[VN] = RHSValID = VN;
1819 NewVNInfo[VN] = RHSValNoInfo;
1820 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
1822 // Otherwise, use the specified value #.
1823 LHSValNoAssignments[VN] = RHSValID;
1824 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
1825 NewVNInfo[VN] = RHSValNoInfo;
1826 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
1830 NewVNInfo[VN] = VNI;
1831 LHSValNoAssignments[VN] = VN;
1835 assert(RHSValID != -1 && "Didn't find value #?");
1836 RHSValNoAssignments[0] = RHSValID;
1837 if (RHSVal0DefinedFromLHS != -1) {
1838 // This path doesn't go through ComputeUltimateVN so just set
1840 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
1843 // Loop over the value numbers of the LHS, seeing if any are defined from
1845 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1848 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
1851 // DstReg is known to be a register in the LHS interval. If the src is
1852 // from the RHS interval, we can use its value #.
1853 if (li_->getVNInfoSourceReg(VNI) != RHS.reg)
1856 // Figure out the value # from the RHS.
1857 LHSValsDefinedFromRHS[VNI]=RHS.getLiveRangeContaining(VNI->def-1)->valno;
1860 // Loop over the value numbers of the RHS, seeing if any are defined from
1862 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1865 if (VNI->def == ~1U || VNI->copy == 0) // Src not defined by a copy?
1868 // DstReg is known to be a register in the RHS interval. If the src is
1869 // from the LHS interval, we can use its value #.
1870 if (li_->getVNInfoSourceReg(VNI) != LHS.reg)
1873 // Figure out the value # from the LHS.
1874 RHSValsDefinedFromLHS[VNI]=LHS.getLiveRangeContaining(VNI->def-1)->valno;
1877 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
1878 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
1879 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
1881 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
1884 unsigned VN = VNI->id;
1885 if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
1887 ComputeUltimateVN(VNI, NewVNInfo,
1888 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
1889 LHSValNoAssignments, RHSValNoAssignments);
1891 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
1894 unsigned VN = VNI->id;
1895 if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
1897 // If this value number isn't a copy from the LHS, it's a new number.
1898 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
1899 NewVNInfo.push_back(VNI);
1900 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
1904 ComputeUltimateVN(VNI, NewVNInfo,
1905 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
1906 RHSValNoAssignments, LHSValNoAssignments);
1910 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
1911 // interval lists to see if these intervals are coalescable.
1912 LiveInterval::const_iterator I = LHS.begin();
1913 LiveInterval::const_iterator IE = LHS.end();
1914 LiveInterval::const_iterator J = RHS.begin();
1915 LiveInterval::const_iterator JE = RHS.end();
1917 // Skip ahead until the first place of potential sharing.
1918 if (I->start < J->start) {
1919 I = std::upper_bound(I, IE, J->start);
1920 if (I != LHS.begin()) --I;
1921 } else if (J->start < I->start) {
1922 J = std::upper_bound(J, JE, I->start);
1923 if (J != RHS.begin()) --J;
1927 // Determine if these two live ranges overlap.
1929 if (I->start < J->start) {
1930 Overlaps = I->end > J->start;
1932 Overlaps = J->end > I->start;
1935 // If so, check value # info to determine if they are really different.
1937 // If the live range overlap will map to the same value number in the
1938 // result liverange, we can still coalesce them. If not, we can't.
1939 if (LHSValNoAssignments[I->valno->id] !=
1940 RHSValNoAssignments[J->valno->id])
1944 if (I->end < J->end) {
1953 // Update kill info. Some live ranges are extended due to copy coalescing.
1954 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
1955 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
1956 VNInfo *VNI = I->first;
1957 unsigned LHSValID = LHSValNoAssignments[VNI->id];
1958 LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def);
1959 NewVNInfo[LHSValID]->hasPHIKill |= VNI->hasPHIKill;
1960 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
1963 // Update kill info. Some live ranges are extended due to copy coalescing.
1964 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
1965 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
1966 VNInfo *VNI = I->first;
1967 unsigned RHSValID = RHSValNoAssignments[VNI->id];
1968 LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def);
1969 NewVNInfo[RHSValID]->hasPHIKill |= VNI->hasPHIKill;
1970 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
1973 // If we get here, we know that we can coalesce the live ranges. Ask the
1974 // intervals to coalesce themselves now.
1975 if ((RHS.ranges.size() > LHS.ranges.size() &&
1976 TargetRegisterInfo::isVirtualRegister(LHS.reg)) ||
1977 TargetRegisterInfo::isPhysicalRegister(RHS.reg)) {
1978 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo);
1981 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo);
1988 // DepthMBBCompare - Comparison predicate that sort first based on the loop
1989 // depth of the basic block (the unsigned), and then on the MBB number.
1990 struct DepthMBBCompare {
1991 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
1992 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
1993 if (LHS.first > RHS.first) return true; // Deeper loops first
1994 return LHS.first == RHS.first &&
1995 LHS.second->getNumber() < RHS.second->getNumber();
2000 /// getRepIntervalSize - Returns the size of the interval that represents the
2001 /// specified register.
2003 unsigned JoinPriorityQueue<SF>::getRepIntervalSize(unsigned Reg) {
2004 return Rc->getRepIntervalSize(Reg);
2007 /// CopyRecSort::operator - Join priority queue sorting function.
2009 bool CopyRecSort::operator()(CopyRec left, CopyRec right) const {
2010 // Inner loops first.
2011 if (left.LoopDepth > right.LoopDepth)
2013 else if (left.LoopDepth == right.LoopDepth)
2014 if (left.isBackEdge && !right.isBackEdge)
2019 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
2020 std::vector<CopyRec> &TryAgain) {
2021 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
2023 std::vector<CopyRec> VirtCopies;
2024 std::vector<CopyRec> PhysCopies;
2025 std::vector<CopyRec> ImpDefCopies;
2026 unsigned LoopDepth = loopInfo->getLoopDepth(MBB);
2027 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
2029 MachineInstr *Inst = MII++;
2031 // If this isn't a copy nor a extract_subreg, we can't join intervals.
2032 unsigned SrcReg, DstReg;
2033 if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
2034 DstReg = Inst->getOperand(0).getReg();
2035 SrcReg = Inst->getOperand(1).getReg();
2036 } else if (Inst->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
2037 DstReg = Inst->getOperand(0).getReg();
2038 SrcReg = Inst->getOperand(2).getReg();
2039 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg))
2042 bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
2043 bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
2045 JoinQueue->push(CopyRec(Inst, LoopDepth, isBackEdgeCopy(Inst, DstReg)));
2047 if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
2048 ImpDefCopies.push_back(CopyRec(Inst, 0, false));
2049 else if (SrcIsPhys || DstIsPhys)
2050 PhysCopies.push_back(CopyRec(Inst, 0, false));
2052 VirtCopies.push_back(CopyRec(Inst, 0, false));
2059 // Try coalescing implicit copies first, followed by copies to / from
2060 // physical registers, then finally copies from virtual registers to
2061 // virtual registers.
2062 for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
2063 CopyRec &TheCopy = ImpDefCopies[i];
2065 if (!JoinCopy(TheCopy, Again))
2067 TryAgain.push_back(TheCopy);
2069 for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
2070 CopyRec &TheCopy = PhysCopies[i];
2072 if (!JoinCopy(TheCopy, Again))
2074 TryAgain.push_back(TheCopy);
2076 for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
2077 CopyRec &TheCopy = VirtCopies[i];
2079 if (!JoinCopy(TheCopy, Again))
2081 TryAgain.push_back(TheCopy);
2085 void SimpleRegisterCoalescing::joinIntervals() {
2086 DOUT << "********** JOINING INTERVALS ***********\n";
2089 JoinQueue = new JoinPriorityQueue<CopyRecSort>(this);
2091 std::vector<CopyRec> TryAgainList;
2092 if (loopInfo->empty()) {
2093 // If there are no loops in the function, join intervals in function order.
2094 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
2096 CopyCoalesceInMBB(I, TryAgainList);
2098 // Otherwise, join intervals in inner loops before other intervals.
2099 // Unfortunately we can't just iterate over loop hierarchy here because
2100 // there may be more MBB's than BB's. Collect MBB's for sorting.
2102 // Join intervals in the function prolog first. We want to join physical
2103 // registers with virtual registers before the intervals got too long.
2104 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
2105 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
2106 MachineBasicBlock *MBB = I;
2107 MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
2110 // Sort by loop depth.
2111 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
2113 // Finally, join intervals in loop nest order.
2114 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
2115 CopyCoalesceInMBB(MBBs[i].second, TryAgainList);
2118 // Joining intervals can allow other intervals to be joined. Iteratively join
2119 // until we make no progress.
2121 SmallVector<CopyRec, 16> TryAgain;
2122 bool ProgressMade = true;
2123 while (ProgressMade) {
2124 ProgressMade = false;
2125 while (!JoinQueue->empty()) {
2126 CopyRec R = JoinQueue->pop();
2128 bool Success = JoinCopy(R, Again);
2130 ProgressMade = true;
2132 TryAgain.push_back(R);
2136 while (!TryAgain.empty()) {
2137 JoinQueue->push(TryAgain.back());
2138 TryAgain.pop_back();
2143 bool ProgressMade = true;
2144 while (ProgressMade) {
2145 ProgressMade = false;
2147 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
2148 CopyRec &TheCopy = TryAgainList[i];
2151 bool Success = JoinCopy(TheCopy, Again);
2152 if (Success || !Again) {
2153 TheCopy.MI = 0; // Mark this one as done.
2154 ProgressMade = true;
2165 /// Return true if the two specified registers belong to different register
2166 /// classes. The registers may be either phys or virt regs. In the
2167 /// case where both registers are virtual registers, it would also returns
2168 /// true by reference the RegB register class in SubRC if it is a subset of
2169 /// RegA's register class.
2171 SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA, unsigned RegB,
2172 const TargetRegisterClass *&SubRC) const {
2174 // Get the register classes for the first reg.
2175 if (TargetRegisterInfo::isPhysicalRegister(RegA)) {
2176 assert(TargetRegisterInfo::isVirtualRegister(RegB) &&
2177 "Shouldn't consider two physregs!");
2178 return !mri_->getRegClass(RegB)->contains(RegA);
2181 // Compare against the regclass for the second reg.
2182 const TargetRegisterClass *RegClassA = mri_->getRegClass(RegA);
2183 if (TargetRegisterInfo::isVirtualRegister(RegB)) {
2184 const TargetRegisterClass *RegClassB = mri_->getRegClass(RegB);
2185 if (RegClassA == RegClassB)
2187 SubRC = (RegClassA->hasSubClass(RegClassB)) ? RegClassB : NULL;
2190 return !RegClassA->contains(RegB);
2193 /// lastRegisterUse - Returns the last use of the specific register between
2194 /// cycles Start and End or NULL if there are no uses.
2196 SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End,
2197 unsigned Reg, unsigned &UseIdx) const{
2199 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
2200 MachineOperand *LastUse = NULL;
2201 for (MachineRegisterInfo::use_iterator I = mri_->use_begin(Reg),
2202 E = mri_->use_end(); I != E; ++I) {
2203 MachineOperand &Use = I.getOperand();
2204 MachineInstr *UseMI = Use.getParent();
2205 unsigned SrcReg, DstReg;
2206 if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg) && SrcReg == DstReg)
2207 // Ignore identity copies.
2209 unsigned Idx = li_->getInstructionIndex(UseMI);
2210 if (Idx >= Start && Idx < End && Idx >= UseIdx) {
2218 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
2221 // Skip deleted instructions
2222 MachineInstr *MI = li_->getInstructionFromIndex(e);
2223 while ((e - InstrSlots::NUM) >= s && !MI) {
2224 e -= InstrSlots::NUM;
2225 MI = li_->getInstructionFromIndex(e);
2227 if (e < s || MI == NULL)
2230 // Ignore identity copies.
2231 unsigned SrcReg, DstReg;
2232 if (!(tii_->isMoveInstr(*MI, SrcReg, DstReg) && SrcReg == DstReg))
2233 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
2234 MachineOperand &Use = MI->getOperand(i);
2235 if (Use.isReg() && Use.isUse() && Use.getReg() &&
2236 tri_->regsOverlap(Use.getReg(), Reg)) {
2242 e -= InstrSlots::NUM;
2249 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
2250 if (TargetRegisterInfo::isPhysicalRegister(reg))
2251 cerr << tri_->getName(reg);
2253 cerr << "%reg" << reg;
2256 void SimpleRegisterCoalescing::releaseMemory() {
2257 JoinedCopies.clear();
2258 ReMatCopies.clear();
2262 static bool isZeroLengthInterval(LiveInterval *li) {
2263 for (LiveInterval::Ranges::const_iterator
2264 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
2265 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
2270 /// TurnCopyIntoImpDef - If source of the specified copy is an implicit def,
2271 /// turn the copy into an implicit def.
2273 SimpleRegisterCoalescing::TurnCopyIntoImpDef(MachineBasicBlock::iterator &I,
2274 MachineBasicBlock *MBB,
2275 unsigned DstReg, unsigned SrcReg) {
2276 MachineInstr *CopyMI = &*I;
2277 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
2278 if (!li_->hasInterval(SrcReg))
2280 LiveInterval &SrcInt = li_->getInterval(SrcReg);
2281 if (!SrcInt.empty())
2283 if (!li_->hasInterval(DstReg))
2285 LiveInterval &DstInt = li_->getInterval(DstReg);
2286 const LiveRange *DstLR = DstInt.getLiveRangeContaining(CopyIdx);
2287 DstInt.removeValNo(DstLR->valno);
2288 CopyMI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
2289 for (int i = CopyMI->getNumOperands() - 1, e = 0; i > e; --i)
2290 CopyMI->RemoveOperand(i);
2291 bool NoUse = mri_->use_empty(SrcReg);
2293 for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(SrcReg),
2294 E = mri_->reg_end(); I != E; ) {
2295 assert(I.getOperand().isDef());
2296 MachineInstr *DefMI = &*I;
2298 // The implicit_def source has no other uses, delete it.
2299 assert(DefMI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF);
2300 li_->RemoveMachineInstrFromMaps(DefMI);
2301 DefMI->eraseFromParent();
2309 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
2311 mri_ = &fn.getRegInfo();
2312 tm_ = &fn.getTarget();
2313 tri_ = tm_->getRegisterInfo();
2314 tii_ = tm_->getInstrInfo();
2315 li_ = &getAnalysis<LiveIntervals>();
2316 loopInfo = &getAnalysis<MachineLoopInfo>();
2318 DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
2319 << "********** Function: "
2320 << ((Value*)mf_->getFunction())->getName() << '\n';
2322 allocatableRegs_ = tri_->getAllocatableSet(fn);
2323 for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(),
2324 E = tri_->regclass_end(); I != E; ++I)
2325 allocatableRCRegs_.insert(std::make_pair(*I,
2326 tri_->getAllocatableSet(fn, *I)));
2328 // Join (coalesce) intervals if requested.
2329 if (EnableJoining) {
2332 DOUT << "********** INTERVALS POST JOINING **********\n";
2333 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I){
2334 I->second->print(DOUT, tri_);
2340 // Perform a final pass over the instructions and compute spill weights
2341 // and remove identity moves.
2342 SmallVector<unsigned, 4> DeadDefs;
2343 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
2344 mbbi != mbbe; ++mbbi) {
2345 MachineBasicBlock* mbb = mbbi;
2346 unsigned loopDepth = loopInfo->getLoopDepth(mbb);
2348 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
2350 MachineInstr *MI = mii;
2351 unsigned SrcReg, DstReg;
2352 if (JoinedCopies.count(MI)) {
2353 // Delete all coalesced copies.
2354 if (!tii_->isMoveInstr(*MI, SrcReg, DstReg)) {
2355 assert((MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG ||
2356 MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) &&
2357 "Unrecognized copy instruction");
2358 DstReg = MI->getOperand(0).getReg();
2360 if (MI->registerDefIsDead(DstReg)) {
2361 LiveInterval &li = li_->getInterval(DstReg);
2362 if (!ShortenDeadCopySrcLiveRange(li, MI))
2363 ShortenDeadCopyLiveRange(li, MI);
2365 li_->RemoveMachineInstrFromMaps(MI);
2366 mii = mbbi->erase(mii);
2371 // Now check if this is a remat'ed def instruction which is now dead.
2372 if (ReMatDefs.count(MI)) {
2374 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2375 const MachineOperand &MO = MI->getOperand(i);
2378 unsigned Reg = MO.getReg();
2379 if (TargetRegisterInfo::isVirtualRegister(Reg))
2380 DeadDefs.push_back(Reg);
2383 if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
2384 !mri_->use_empty(Reg)) {
2390 while (!DeadDefs.empty()) {
2391 unsigned DeadDef = DeadDefs.back();
2392 DeadDefs.pop_back();
2393 RemoveDeadDef(li_->getInterval(DeadDef), MI);
2395 li_->RemoveMachineInstrFromMaps(mii);
2396 mii = mbbi->erase(mii);
2402 // If the move will be an identity move delete it
2403 bool isMove = tii_->isMoveInstr(*MI, SrcReg, DstReg);
2404 if (isMove && SrcReg == DstReg) {
2405 if (li_->hasInterval(SrcReg)) {
2406 LiveInterval &RegInt = li_->getInterval(SrcReg);
2407 // If def of this move instruction is dead, remove its live range
2408 // from the dstination register's live interval.
2409 if (MI->registerDefIsDead(DstReg)) {
2410 if (!ShortenDeadCopySrcLiveRange(RegInt, MI))
2411 ShortenDeadCopyLiveRange(RegInt, MI);
2414 li_->RemoveMachineInstrFromMaps(MI);
2415 mii = mbbi->erase(mii);
2417 } else if (!isMove || !TurnCopyIntoImpDef(mii, mbb, DstReg, SrcReg)) {
2418 SmallSet<unsigned, 4> UniqueUses;
2419 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2420 const MachineOperand &mop = MI->getOperand(i);
2421 if (mop.isReg() && mop.getReg() &&
2422 TargetRegisterInfo::isVirtualRegister(mop.getReg())) {
2423 unsigned reg = mop.getReg();
2424 // Multiple uses of reg by the same instruction. It should not
2425 // contribute to spill weight again.
2426 if (UniqueUses.count(reg) != 0)
2428 LiveInterval &RegInt = li_->getInterval(reg);
2430 li_->getSpillWeight(mop.isDef(), mop.isUse(), loopDepth);
2431 UniqueUses.insert(reg);
2439 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
2440 LiveInterval &LI = *I->second;
2441 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
2442 // If the live interval length is essentially zero, i.e. in every live
2443 // range the use follows def immediately, it doesn't make sense to spill
2444 // it and hope it will be easier to allocate for this li.
2445 if (isZeroLengthInterval(&LI))
2446 LI.weight = HUGE_VALF;
2448 bool isLoad = false;
2449 SmallVector<LiveInterval*, 4> SpillIs;
2450 if (li_->isReMaterializable(LI, SpillIs, isLoad)) {
2451 // If all of the definitions of the interval are re-materializable,
2452 // it is a preferred candidate for spilling. If non of the defs are
2453 // loads, then it's potentially very cheap to re-materialize.
2454 // FIXME: this gets much more complicated once we support non-trivial
2455 // re-materialization.
2463 // Slightly prefer live interval that has been assigned a preferred reg.
2467 // Divide the weight of the interval by its size. This encourages
2468 // spilling of intervals that are large and have few uses, and
2469 // discourages spilling of small intervals with many uses.
2470 LI.weight /= li_->getApproximateInstructionCount(LI) * InstrSlots::NUM;
2478 /// print - Implement the dump method.
2479 void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const {
2483 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
2484 return new SimpleRegisterCoalescing();
2487 // Make sure that anything that uses RegisterCoalescer pulls in this file...
2488 DEFINING_FILE_FOR(SimpleRegisterCoalescing)