1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/Target/TargetData.h"
16 #include "llvm/Target/TargetMachine.h"
17 #include "llvm/Target/MRegisterInfo.h"
18 #include "llvm/DerivedTypes.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Target/TargetAsmInfo.h"
26 /// InitLibcallNames - Set default libcall names.
28 static void InitLibcallNames(const char **Names) {
29 Names[RTLIB::SHL_I32] = "__ashlsi3";
30 Names[RTLIB::SHL_I64] = "__ashldi3";
31 Names[RTLIB::SRL_I32] = "__lshrsi3";
32 Names[RTLIB::SRL_I64] = "__lshrdi3";
33 Names[RTLIB::SRA_I32] = "__ashrsi3";
34 Names[RTLIB::SRA_I64] = "__ashrdi3";
35 Names[RTLIB::MUL_I32] = "__mulsi3";
36 Names[RTLIB::MUL_I64] = "__muldi3";
37 Names[RTLIB::SDIV_I32] = "__divsi3";
38 Names[RTLIB::SDIV_I64] = "__divdi3";
39 Names[RTLIB::UDIV_I32] = "__udivsi3";
40 Names[RTLIB::UDIV_I64] = "__udivdi3";
41 Names[RTLIB::SREM_I32] = "__modsi3";
42 Names[RTLIB::SREM_I64] = "__moddi3";
43 Names[RTLIB::UREM_I32] = "__umodsi3";
44 Names[RTLIB::UREM_I64] = "__umoddi3";
45 Names[RTLIB::NEG_I32] = "__negsi2";
46 Names[RTLIB::NEG_I64] = "__negdi2";
47 Names[RTLIB::ADD_F32] = "__addsf3";
48 Names[RTLIB::ADD_F64] = "__adddf3";
49 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
50 Names[RTLIB::SUB_F32] = "__subsf3";
51 Names[RTLIB::SUB_F64] = "__subdf3";
52 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
53 Names[RTLIB::MUL_F32] = "__mulsf3";
54 Names[RTLIB::MUL_F64] = "__muldf3";
55 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
56 Names[RTLIB::DIV_F32] = "__divsf3";
57 Names[RTLIB::DIV_F64] = "__divdf3";
58 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
59 Names[RTLIB::REM_F32] = "fmodf";
60 Names[RTLIB::REM_F64] = "fmod";
61 Names[RTLIB::REM_PPCF128] = "fmodl";
62 Names[RTLIB::NEG_F32] = "__negsf2";
63 Names[RTLIB::NEG_F64] = "__negdf2";
64 Names[RTLIB::POWI_F32] = "__powisf2";
65 Names[RTLIB::POWI_F64] = "__powidf2";
66 Names[RTLIB::POWI_F80] = "__powixf2";
67 Names[RTLIB::POWI_PPCF128] = "__powitf2";
68 Names[RTLIB::SQRT_F32] = "sqrtf";
69 Names[RTLIB::SQRT_F64] = "sqrt";
70 Names[RTLIB::SQRT_F80] = "sqrtl";
71 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
72 Names[RTLIB::SIN_F32] = "sinf";
73 Names[RTLIB::SIN_F64] = "sin";
74 Names[RTLIB::COS_F32] = "cosf";
75 Names[RTLIB::COS_F64] = "cos";
76 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
77 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
78 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
79 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
80 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
81 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
82 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
83 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
84 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
85 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
86 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
87 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
88 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
89 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
90 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
91 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
92 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
93 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
94 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
95 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
96 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
97 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
98 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
99 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
100 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
101 Names[RTLIB::OEQ_F32] = "__eqsf2";
102 Names[RTLIB::OEQ_F64] = "__eqdf2";
103 Names[RTLIB::UNE_F32] = "__nesf2";
104 Names[RTLIB::UNE_F64] = "__nedf2";
105 Names[RTLIB::OGE_F32] = "__gesf2";
106 Names[RTLIB::OGE_F64] = "__gedf2";
107 Names[RTLIB::OLT_F32] = "__ltsf2";
108 Names[RTLIB::OLT_F64] = "__ltdf2";
109 Names[RTLIB::OLE_F32] = "__lesf2";
110 Names[RTLIB::OLE_F64] = "__ledf2";
111 Names[RTLIB::OGT_F32] = "__gtsf2";
112 Names[RTLIB::OGT_F64] = "__gtdf2";
113 Names[RTLIB::UO_F32] = "__unordsf2";
114 Names[RTLIB::UO_F64] = "__unorddf2";
115 Names[RTLIB::O_F32] = "__unordsf2";
116 Names[RTLIB::O_F64] = "__unorddf2";
119 /// InitCmpLibcallCCs - Set default comparison libcall CC.
121 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
122 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
123 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
124 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
125 CCs[RTLIB::UNE_F32] = ISD::SETNE;
126 CCs[RTLIB::UNE_F64] = ISD::SETNE;
127 CCs[RTLIB::OGE_F32] = ISD::SETGE;
128 CCs[RTLIB::OGE_F64] = ISD::SETGE;
129 CCs[RTLIB::OLT_F32] = ISD::SETLT;
130 CCs[RTLIB::OLT_F64] = ISD::SETLT;
131 CCs[RTLIB::OLE_F32] = ISD::SETLE;
132 CCs[RTLIB::OLE_F64] = ISD::SETLE;
133 CCs[RTLIB::OGT_F32] = ISD::SETGT;
134 CCs[RTLIB::OGT_F64] = ISD::SETGT;
135 CCs[RTLIB::UO_F32] = ISD::SETNE;
136 CCs[RTLIB::UO_F64] = ISD::SETNE;
137 CCs[RTLIB::O_F32] = ISD::SETEQ;
138 CCs[RTLIB::O_F64] = ISD::SETEQ;
141 TargetLowering::TargetLowering(TargetMachine &tm)
142 : TM(tm), TD(TM.getTargetData()) {
143 assert(ISD::BUILTIN_OP_END <= 156 &&
144 "Fixed size array in TargetLowering is not large enough!");
145 // All operations default to being supported.
146 memset(OpActions, 0, sizeof(OpActions));
147 memset(LoadXActions, 0, sizeof(LoadXActions));
148 memset(&StoreXActions, 0, sizeof(StoreXActions));
149 memset(&IndexedModeActions, 0, sizeof(IndexedModeActions));
150 memset(&ConvertActions, 0, sizeof(ConvertActions));
152 // Set all indexed load / store to expand.
153 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
154 for (unsigned IM = (unsigned)ISD::PRE_INC;
155 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
156 setIndexedLoadAction(IM, (MVT::ValueType)VT, Expand);
157 setIndexedStoreAction(IM, (MVT::ValueType)VT, Expand);
161 IsLittleEndian = TD->isLittleEndian();
162 UsesGlobalOffsetTable = false;
163 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD->getIntPtrType());
164 ShiftAmtHandling = Undefined;
165 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
166 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
167 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
168 allowUnalignedMemoryAccesses = false;
169 UseUnderscoreSetJmp = false;
170 UseUnderscoreLongJmp = false;
171 SelectIsExpensive = false;
172 IntDivIsCheap = false;
173 Pow2DivIsCheap = false;
174 StackPointerRegisterToSaveRestore = 0;
175 ExceptionPointerRegister = 0;
176 ExceptionSelectorRegister = 0;
177 SetCCResultContents = UndefinedSetCCResult;
178 SchedPreferenceInfo = SchedulingForLatency;
180 JumpBufAlignment = 0;
181 IfCvtBlockSizeLimit = 2;
183 InitLibcallNames(LibcallRoutineNames);
184 InitCmpLibcallCCs(CmpLibcallCCs);
186 // Tell Legalize whether the assembler supports DEBUG_LOC.
187 if (!TM.getTargetAsmInfo()->hasDotLocAndDotFile())
188 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
191 TargetLowering::~TargetLowering() {}
193 /// computeRegisterProperties - Once all of the register classes are added,
194 /// this allows us to compute derived properties we expose.
195 void TargetLowering::computeRegisterProperties() {
196 assert(MVT::LAST_VALUETYPE <= 32 &&
197 "Too many value types for ValueTypeActions to hold!");
199 // Everything defaults to needing one register.
200 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
201 NumRegistersForVT[i] = 1;
202 RegisterTypeForVT[i] = TransformToType[i] = i;
204 // ...except isVoid, which doesn't need any registers.
205 NumRegistersForVT[MVT::isVoid] = 0;
207 // Find the largest integer register class.
208 unsigned LargestIntReg = MVT::i128;
209 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
210 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
212 // Every integer value type larger than this largest register takes twice as
213 // many registers to represent as the previous ValueType.
214 for (MVT::ValueType ExpandedReg = LargestIntReg + 1;
215 MVT::isInteger(ExpandedReg); ++ExpandedReg) {
216 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
217 RegisterTypeForVT[ExpandedReg] = LargestIntReg;
218 TransformToType[ExpandedReg] = ExpandedReg - 1;
219 ValueTypeActions.setTypeAction(ExpandedReg, Expand);
222 // Inspect all of the ValueType's smaller than the largest integer
223 // register to see which ones need promotion.
224 MVT::ValueType LegalIntReg = LargestIntReg;
225 for (MVT::ValueType IntReg = LargestIntReg - 1;
226 IntReg >= MVT::i1; --IntReg) {
227 if (isTypeLegal(IntReg)) {
228 LegalIntReg = IntReg;
230 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = LegalIntReg;
231 ValueTypeActions.setTypeAction(IntReg, Promote);
235 // ppcf128 type is really two f64's.
236 if (!isTypeLegal(MVT::ppcf128)) {
237 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
238 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
239 TransformToType[MVT::ppcf128] = MVT::f64;
240 ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
243 // Decide how to handle f64. If the target does not have native f64 support,
244 // expand it to i64 and we will be generating soft float library calls.
245 if (!isTypeLegal(MVT::f64)) {
246 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
247 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
248 TransformToType[MVT::f64] = MVT::i64;
249 ValueTypeActions.setTypeAction(MVT::f64, Expand);
252 // Decide how to handle f32. If the target does not have native support for
253 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
254 if (!isTypeLegal(MVT::f32)) {
255 if (isTypeLegal(MVT::f64)) {
256 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
257 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
258 TransformToType[MVT::f32] = MVT::f64;
259 ValueTypeActions.setTypeAction(MVT::f32, Promote);
261 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
262 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
263 TransformToType[MVT::f32] = MVT::i32;
264 ValueTypeActions.setTypeAction(MVT::f32, Expand);
268 // Loop over all of the vector value types to see which need transformations.
269 for (MVT::ValueType i = MVT::FIRST_VECTOR_VALUETYPE;
270 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
271 if (!isTypeLegal(i)) {
272 MVT::ValueType IntermediateVT, RegisterVT;
273 unsigned NumIntermediates;
274 NumRegistersForVT[i] =
275 getVectorTypeBreakdown(i,
276 IntermediateVT, NumIntermediates,
278 RegisterTypeForVT[i] = RegisterVT;
279 TransformToType[i] = MVT::Other; // this isn't actually used
280 ValueTypeActions.setTypeAction(i, Expand);
285 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
289 /// getVectorTypeBreakdown - Vector types are broken down into some number of
290 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
291 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
292 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
294 /// This method returns the number of registers needed, and the VT for each
295 /// register. It also returns the VT and quantity of the intermediate values
296 /// before they are promoted/expanded.
298 unsigned TargetLowering::getVectorTypeBreakdown(MVT::ValueType VT,
299 MVT::ValueType &IntermediateVT,
300 unsigned &NumIntermediates,
301 MVT::ValueType &RegisterVT) const {
302 // Figure out the right, legal destination reg to copy into.
303 unsigned NumElts = MVT::getVectorNumElements(VT);
304 MVT::ValueType EltTy = MVT::getVectorElementType(VT);
306 unsigned NumVectorRegs = 1;
308 // Divide the input until we get to a supported size. This will always
309 // end with a scalar if the target doesn't support vectors.
310 while (NumElts > 1 &&
311 !isTypeLegal(MVT::getVectorType(EltTy, NumElts))) {
316 NumIntermediates = NumVectorRegs;
318 MVT::ValueType NewVT = MVT::getVectorType(EltTy, NumElts);
319 if (!isTypeLegal(NewVT))
321 IntermediateVT = NewVT;
323 MVT::ValueType DestVT = getTypeToTransformTo(NewVT);
325 if (DestVT < NewVT) {
326 // Value is expanded, e.g. i64 -> i16.
327 return NumVectorRegs*(MVT::getSizeInBits(NewVT)/MVT::getSizeInBits(DestVT));
329 // Otherwise, promotion or legal types use the same number of registers as
330 // the vector decimated to the appropriate level.
331 return NumVectorRegs;
337 //===----------------------------------------------------------------------===//
338 // Optimization Methods
339 //===----------------------------------------------------------------------===//
341 /// ShrinkDemandedConstant - Check to see if the specified operand of the
342 /// specified instruction is a constant integer. If so, check to see if there
343 /// are any bits set in the constant that are not demanded. If so, shrink the
344 /// constant and return true.
345 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
347 // FIXME: ISD::SELECT, ISD::SELECT_CC
348 switch(Op.getOpcode()) {
353 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
354 if ((~Demanded & C->getValue()) != 0) {
355 MVT::ValueType VT = Op.getValueType();
356 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
357 DAG.getConstant(Demanded & C->getValue(),
359 return CombineTo(Op, New);
366 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
367 /// DemandedMask bits of the result of Op are ever used downstream. If we can
368 /// use this information to simplify Op, create a new simplified DAG node and
369 /// return true, returning the original and new nodes in Old and New. Otherwise,
370 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
371 /// the expression (used to simplify the caller). The KnownZero/One bits may
372 /// only be accurate for those bits in the DemandedMask.
373 bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
376 TargetLoweringOpt &TLO,
377 unsigned Depth) const {
378 KnownZero = KnownOne = 0; // Don't know anything.
380 // The masks are not wide enough to represent this type! Should use APInt.
381 if (Op.getValueType() == MVT::i128)
384 // Other users may use these bits.
385 if (!Op.Val->hasOneUse()) {
387 // If not at the root, Just compute the KnownZero/KnownOne bits to
388 // simplify things downstream.
389 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
392 // If this is the root being simplified, allow it to have multiple uses,
393 // just set the DemandedMask to all bits.
394 DemandedMask = MVT::getIntVTBitMask(Op.getValueType());
395 } else if (DemandedMask == 0) {
396 // Not demanding any bits from Op.
397 if (Op.getOpcode() != ISD::UNDEF)
398 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType()));
400 } else if (Depth == 6) { // Limit search depth.
404 uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
405 switch (Op.getOpcode()) {
407 // We know all of the bits for a constant!
408 KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask;
409 KnownZero = ~KnownOne & DemandedMask;
410 return false; // Don't fall through, will infinitely loop.
412 // If the RHS is a constant, check to see if the LHS would be zero without
413 // using the bits from the RHS. Below, we use knowledge about the RHS to
414 // simplify the LHS, here we're using information from the LHS to simplify
416 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
417 uint64_t LHSZero, LHSOne;
418 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), DemandedMask,
419 LHSZero, LHSOne, Depth+1);
420 // If the LHS already has zeros where RHSC does, this and is dead.
421 if ((LHSZero & DemandedMask) == (~RHSC->getValue() & DemandedMask))
422 return TLO.CombineTo(Op, Op.getOperand(0));
423 // If any of the set bits in the RHS are known zero on the LHS, shrink
425 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & DemandedMask))
429 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
430 KnownOne, TLO, Depth+1))
432 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
433 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero,
434 KnownZero2, KnownOne2, TLO, Depth+1))
436 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
438 // If all of the demanded bits are known one on one side, return the other.
439 // These bits cannot contribute to the result of the 'and'.
440 if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2))
441 return TLO.CombineTo(Op, Op.getOperand(0));
442 if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero))
443 return TLO.CombineTo(Op, Op.getOperand(1));
444 // If all of the demanded bits in the inputs are known zeros, return zero.
445 if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask)
446 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
447 // If the RHS is a constant, see if we can simplify it.
448 if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2))
451 // Output known-1 bits are only known if set in both the LHS & RHS.
452 KnownOne &= KnownOne2;
453 // Output known-0 are known to be clear if zero in either the LHS | RHS.
454 KnownZero |= KnownZero2;
457 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
458 KnownOne, TLO, Depth+1))
460 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
461 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne,
462 KnownZero2, KnownOne2, TLO, Depth+1))
464 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
466 // If all of the demanded bits are known zero on one side, return the other.
467 // These bits cannot contribute to the result of the 'or'.
468 if ((DemandedMask & ~KnownOne2 & KnownZero) == (DemandedMask & ~KnownOne2))
469 return TLO.CombineTo(Op, Op.getOperand(0));
470 if ((DemandedMask & ~KnownOne & KnownZero2) == (DemandedMask & ~KnownOne))
471 return TLO.CombineTo(Op, Op.getOperand(1));
472 // If all of the potentially set bits on one side are known to be set on
473 // the other side, just use the 'other' side.
474 if ((DemandedMask & (~KnownZero) & KnownOne2) ==
475 (DemandedMask & (~KnownZero)))
476 return TLO.CombineTo(Op, Op.getOperand(0));
477 if ((DemandedMask & (~KnownZero2) & KnownOne) ==
478 (DemandedMask & (~KnownZero2)))
479 return TLO.CombineTo(Op, Op.getOperand(1));
480 // If the RHS is a constant, see if we can simplify it.
481 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
484 // Output known-0 bits are only known if clear in both the LHS & RHS.
485 KnownZero &= KnownZero2;
486 // Output known-1 are known to be set if set in either the LHS | RHS.
487 KnownOne |= KnownOne2;
490 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
491 KnownOne, TLO, Depth+1))
493 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
494 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2,
495 KnownOne2, TLO, Depth+1))
497 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
499 // If all of the demanded bits are known zero on one side, return the other.
500 // These bits cannot contribute to the result of the 'xor'.
501 if ((DemandedMask & KnownZero) == DemandedMask)
502 return TLO.CombineTo(Op, Op.getOperand(0));
503 if ((DemandedMask & KnownZero2) == DemandedMask)
504 return TLO.CombineTo(Op, Op.getOperand(1));
506 // If all of the unknown bits are known to be zero on one side or the other
507 // (but not both) turn this into an *inclusive* or.
508 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
509 if ((DemandedMask & ~KnownZero & ~KnownZero2) == 0)
510 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(),
514 // Output known-0 bits are known if clear or set in both the LHS & RHS.
515 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
516 // Output known-1 are known to be set if set in only one of the LHS, RHS.
517 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
519 // If all of the demanded bits on one side are known, and all of the set
520 // bits on that side are also known to be set on the other side, turn this
521 // into an AND, as we know the bits will be cleared.
522 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
523 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known
524 if ((KnownOne & KnownOne2) == KnownOne) {
525 MVT::ValueType VT = Op.getValueType();
526 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT);
527 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0),
532 // If the RHS is a constant, see if we can simplify it.
533 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1.
534 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
537 KnownZero = KnownZeroOut;
538 KnownOne = KnownOneOut;
541 // If we know the result of a setcc has the top bits zero, use this info.
542 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult)
543 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
546 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero,
547 KnownOne, TLO, Depth+1))
549 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2,
550 KnownOne2, TLO, Depth+1))
552 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
553 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
555 // If the operands are constants, see if we can simplify them.
556 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
559 // Only known if known in both the LHS and RHS.
560 KnownOne &= KnownOne2;
561 KnownZero &= KnownZero2;
564 if (SimplifyDemandedBits(Op.getOperand(3), DemandedMask, KnownZero,
565 KnownOne, TLO, Depth+1))
567 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero2,
568 KnownOne2, TLO, Depth+1))
570 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
571 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
573 // If the operands are constants, see if we can simplify them.
574 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
577 // Only known if known in both the LHS and RHS.
578 KnownOne &= KnownOne2;
579 KnownZero &= KnownZero2;
582 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
583 unsigned ShAmt = SA->getValue();
584 SDOperand InOp = Op.getOperand(0);
586 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
587 // single shift. We can do this if the bottom bits (which are shifted
588 // out) are never demanded.
589 if (InOp.getOpcode() == ISD::SRL &&
590 isa<ConstantSDNode>(InOp.getOperand(1))) {
591 if (ShAmt && (DemandedMask & ((1ULL << ShAmt)-1)) == 0) {
592 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
593 unsigned Opc = ISD::SHL;
601 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
602 MVT::ValueType VT = Op.getValueType();
603 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
604 InOp.getOperand(0), NewSA));
608 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> ShAmt,
609 KnownZero, KnownOne, TLO, Depth+1))
611 KnownZero <<= SA->getValue();
612 KnownOne <<= SA->getValue();
613 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
617 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
618 MVT::ValueType VT = Op.getValueType();
619 unsigned ShAmt = SA->getValue();
620 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
621 unsigned VTSize = MVT::getSizeInBits(VT);
622 SDOperand InOp = Op.getOperand(0);
624 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
625 // single shift. We can do this if the top bits (which are shifted out)
626 // are never demanded.
627 if (InOp.getOpcode() == ISD::SHL &&
628 isa<ConstantSDNode>(InOp.getOperand(1))) {
629 if (ShAmt && (DemandedMask & (~0ULL << (VTSize-ShAmt))) == 0) {
630 unsigned C1 = cast<ConstantSDNode>(InOp.getOperand(1))->getValue();
631 unsigned Opc = ISD::SRL;
639 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
640 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, VT,
641 InOp.getOperand(0), NewSA));
645 // Compute the new bits that are at the top now.
646 if (SimplifyDemandedBits(InOp, (DemandedMask << ShAmt) & TypeMask,
647 KnownZero, KnownOne, TLO, Depth+1))
649 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
650 KnownZero &= TypeMask;
651 KnownOne &= TypeMask;
655 uint64_t HighBits = (1ULL << ShAmt)-1;
656 HighBits <<= VTSize - ShAmt;
657 KnownZero |= HighBits; // High bits known zero.
661 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
662 MVT::ValueType VT = Op.getValueType();
663 unsigned ShAmt = SA->getValue();
665 // Compute the new bits that are at the top now.
666 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
668 uint64_t InDemandedMask = (DemandedMask << ShAmt) & TypeMask;
670 // If any of the demanded bits are produced by the sign extension, we also
671 // demand the input sign bit.
672 uint64_t HighBits = (1ULL << ShAmt)-1;
673 HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
674 if (HighBits & DemandedMask)
675 InDemandedMask |= MVT::getIntVTSignBit(VT);
677 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
678 KnownZero, KnownOne, TLO, Depth+1))
680 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
681 KnownZero &= TypeMask;
682 KnownOne &= TypeMask;
686 // Handle the sign bits.
687 uint64_t SignBit = MVT::getIntVTSignBit(VT);
688 SignBit >>= ShAmt; // Adjust to where it is now in the mask.
690 // If the input sign bit is known to be zero, or if none of the top bits
691 // are demanded, turn this into an unsigned shift right.
692 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) {
693 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0),
695 } else if (KnownOne & SignBit) { // New bits are known one.
696 KnownOne |= HighBits;
700 case ISD::SIGN_EXTEND_INREG: {
701 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
703 // Sign extension. Compute the demanded bits in the result that are not
704 // present in the input.
705 uint64_t NewBits = ~MVT::getIntVTBitMask(EVT) & DemandedMask;
707 // If none of the extended bits are demanded, eliminate the sextinreg.
709 return TLO.CombineTo(Op, Op.getOperand(0));
711 uint64_t InSignBit = MVT::getIntVTSignBit(EVT);
712 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT);
714 // Since the sign extended bits are demanded, we know that the sign
716 InputDemandedBits |= InSignBit;
718 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
719 KnownZero, KnownOne, TLO, Depth+1))
721 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
723 // If the sign bit of the input is known set or clear, then we know the
724 // top bits of the result.
726 // If the input sign bit is known zero, convert this into a zero extension.
727 if (KnownZero & InSignBit)
728 return TLO.CombineTo(Op,
729 TLO.DAG.getZeroExtendInReg(Op.getOperand(0), EVT));
731 if (KnownOne & InSignBit) { // Input sign bit known set
733 KnownZero &= ~NewBits;
734 } else { // Input sign bit unknown
735 KnownZero &= ~NewBits;
736 KnownOne &= ~NewBits;
743 MVT::ValueType VT = Op.getValueType();
744 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1;
745 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT);
750 if (ISD::isZEXTLoad(Op.Val)) {
751 LoadSDNode *LD = cast<LoadSDNode>(Op);
752 MVT::ValueType VT = LD->getLoadedVT();
753 KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask;
757 case ISD::ZERO_EXTEND: {
758 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
760 // If none of the top bits are demanded, convert this into an any_extend.
761 uint64_t NewBits = (~InMask) & DemandedMask;
763 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND,
767 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
768 KnownZero, KnownOne, TLO, Depth+1))
770 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
771 KnownZero |= NewBits;
774 case ISD::SIGN_EXTEND: {
775 MVT::ValueType InVT = Op.getOperand(0).getValueType();
776 uint64_t InMask = MVT::getIntVTBitMask(InVT);
777 uint64_t InSignBit = MVT::getIntVTSignBit(InVT);
778 uint64_t NewBits = (~InMask) & DemandedMask;
780 // If none of the top bits are demanded, convert this into an any_extend.
782 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND,Op.getValueType(),
785 // Since some of the sign extended bits are demanded, we know that the sign
787 uint64_t InDemandedBits = DemandedMask & InMask;
788 InDemandedBits |= InSignBit;
790 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
791 KnownOne, TLO, Depth+1))
794 // If the sign bit is known zero, convert this to a zero extend.
795 if (KnownZero & InSignBit)
796 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND,
800 // If the sign bit is known one, the top bits match.
801 if (KnownOne & InSignBit) {
803 KnownZero &= ~NewBits;
804 } else { // Otherwise, top bits aren't known.
805 KnownOne &= ~NewBits;
806 KnownZero &= ~NewBits;
810 case ISD::ANY_EXTEND: {
811 uint64_t InMask = MVT::getIntVTBitMask(Op.getOperand(0).getValueType());
812 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
813 KnownZero, KnownOne, TLO, Depth+1))
815 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
818 case ISD::TRUNCATE: {
819 // Simplify the input, using demanded bit information, and compute the known
820 // zero/one bits live out.
821 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask,
822 KnownZero, KnownOne, TLO, Depth+1))
825 // If the input is only used by this truncate, see if we can shrink it based
826 // on the known demanded bits.
827 if (Op.getOperand(0).Val->hasOneUse()) {
828 SDOperand In = Op.getOperand(0);
829 switch (In.getOpcode()) {
832 // Shrink SRL by a constant if none of the high bits shifted in are
834 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1))){
835 uint64_t HighBits = MVT::getIntVTBitMask(In.getValueType());
836 HighBits &= ~MVT::getIntVTBitMask(Op.getValueType());
837 HighBits >>= ShAmt->getValue();
839 if (ShAmt->getValue() < MVT::getSizeInBits(Op.getValueType()) &&
840 (DemandedMask & HighBits) == 0) {
841 // None of the shifted in bits are needed. Add a truncate of the
842 // shift input, then shift it.
843 SDOperand NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE,
846 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL,Op.getValueType(),
847 NewTrunc, In.getOperand(1)));
854 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
855 uint64_t OutMask = MVT::getIntVTBitMask(Op.getValueType());
856 KnownZero &= OutMask;
860 case ISD::AssertZext: {
861 MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
862 uint64_t InMask = MVT::getIntVTBitMask(VT);
863 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & InMask,
864 KnownZero, KnownOne, TLO, Depth+1))
866 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
867 KnownZero |= ~InMask & DemandedMask;
872 case ISD::INTRINSIC_WO_CHAIN:
873 case ISD::INTRINSIC_W_CHAIN:
874 case ISD::INTRINSIC_VOID:
875 // Just use ComputeMaskedBits to compute output bits.
876 TLO.DAG.ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
880 // If we know the value of all of the demanded bits, return this as a
882 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask)
883 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
888 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
889 /// in Mask are known to be either zero or one and return them in the
890 /// KnownZero/KnownOne bitsets.
891 void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
895 const SelectionDAG &DAG,
896 unsigned Depth) const {
897 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
898 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
899 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
900 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
901 "Should use MaskedValueIsZero if you don't know whether Op"
902 " is a target node!");
907 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
908 /// targets that want to expose additional information about sign bits to the
910 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDOperand Op,
911 unsigned Depth) const {
912 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
913 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
914 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
915 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
916 "Should use ComputeNumSignBits if you don't know whether Op"
917 " is a target node!");
922 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
923 /// and cc. If it is unable to simplify it, return a null SDOperand.
925 TargetLowering::SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
926 ISD::CondCode Cond, bool foldBooleans,
927 DAGCombinerInfo &DCI) const {
928 SelectionDAG &DAG = DCI.DAG;
930 // These setcc operations always fold.
934 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
936 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
939 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
940 uint64_t C1 = N1C->getValue();
941 if (isa<ConstantSDNode>(N0.Val)) {
942 return DAG.FoldSetCC(VT, N0, N1, Cond);
944 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
945 // equality comparison, then we're just comparing whether X itself is
947 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
948 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
949 N0.getOperand(1).getOpcode() == ISD::Constant) {
950 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
951 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
952 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
953 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
954 // (srl (ctlz x), 5) == 0 -> X != 0
955 // (srl (ctlz x), 5) != 1 -> X != 0
958 // (srl (ctlz x), 5) != 0 -> X == 0
959 // (srl (ctlz x), 5) == 1 -> X == 0
962 SDOperand Zero = DAG.getConstant(0, N0.getValueType());
963 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
968 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
969 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
970 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
972 // If the comparison constant has bits in the upper part, the
973 // zero-extended value could never match.
974 if (C1 & (~0ULL << InSize)) {
975 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
979 case ISD::SETEQ: return DAG.getConstant(0, VT);
982 case ISD::SETNE: return DAG.getConstant(1, VT);
985 // True if the sign bit of C1 is set.
986 return DAG.getConstant((C1 & (1ULL << (VSize-1))) != 0, VT);
989 // True if the sign bit of C1 isn't set.
990 return DAG.getConstant((C1 & (1ULL << (VSize-1))) == 0, VT);
996 // Otherwise, we can perform the comparison with the low bits.
1004 return DAG.getSetCC(VT, N0.getOperand(0),
1005 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
1008 break; // todo, be more careful with signed comparisons
1010 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1011 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1012 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1013 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
1014 MVT::ValueType ExtDstTy = N0.getValueType();
1015 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
1017 // If the extended part has any inconsistent bits, it cannot ever
1018 // compare equal. In other words, they have to be all ones or all
1021 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
1022 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1023 return DAG.getConstant(Cond == ISD::SETNE, VT);
1026 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
1027 if (Op0Ty == ExtSrcTy) {
1028 ZextOp = N0.getOperand(0);
1030 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
1031 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
1032 DAG.getConstant(Imm, Op0Ty));
1034 if (!DCI.isCalledByLegalizer())
1035 DCI.AddToWorklist(ZextOp.Val);
1036 // Otherwise, make this a use of a zext.
1037 return DAG.getSetCC(VT, ZextOp,
1038 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
1041 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
1042 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1044 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1045 if (N0.getOpcode() == ISD::SETCC) {
1046 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1);
1050 // Invert the condition.
1051 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1052 CC = ISD::getSetCCInverse(CC,
1053 MVT::isInteger(N0.getOperand(0).getValueType()));
1054 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC);
1057 if ((N0.getOpcode() == ISD::XOR ||
1058 (N0.getOpcode() == ISD::AND &&
1059 N0.getOperand(0).getOpcode() == ISD::XOR &&
1060 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1061 isa<ConstantSDNode>(N0.getOperand(1)) &&
1062 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
1063 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1064 // can only do this if the top bits are known zero.
1065 if (DAG.MaskedValueIsZero(N0,
1066 MVT::getIntVTBitMask(N0.getValueType())-1)){
1067 // Okay, get the un-inverted input value.
1069 if (N0.getOpcode() == ISD::XOR)
1070 Val = N0.getOperand(0);
1072 assert(N0.getOpcode() == ISD::AND &&
1073 N0.getOperand(0).getOpcode() == ISD::XOR);
1074 // ((X^1)&1)^1 -> X & 1
1075 Val = DAG.getNode(ISD::AND, N0.getValueType(),
1076 N0.getOperand(0).getOperand(0),
1079 return DAG.getSetCC(VT, Val, N1,
1080 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1085 uint64_t MinVal, MaxVal;
1086 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
1087 if (ISD::isSignedIntSetCC(Cond)) {
1088 MinVal = 1ULL << (OperandBitSize-1);
1089 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
1090 MaxVal = ~0ULL >> (65-OperandBitSize);
1095 MaxVal = ~0ULL >> (64-OperandBitSize);
1098 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1099 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1100 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1101 --C1; // X >= C0 --> X > (C0-1)
1102 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
1103 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
1106 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1107 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1108 ++C1; // X <= C0 --> X < (C0+1)
1109 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
1110 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
1113 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1114 return DAG.getConstant(0, VT); // X < MIN --> false
1115 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1116 return DAG.getConstant(1, VT); // X >= MIN --> true
1117 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1118 return DAG.getConstant(0, VT); // X > MAX --> false
1119 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1120 return DAG.getConstant(1, VT); // X <= MAX --> true
1122 // Canonicalize setgt X, Min --> setne X, Min
1123 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1124 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
1125 // Canonicalize setlt X, Max --> setne X, Max
1126 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1127 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
1129 // If we have setult X, 1, turn it into seteq X, 0
1130 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1131 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
1133 // If we have setugt X, Max-1, turn it into seteq X, Max
1134 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1135 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
1138 // If we have "setcc X, C0", check to see if we can shrink the immediate
1141 // SETUGT X, SINTMAX -> SETLT X, 0
1142 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
1143 C1 == (~0ULL >> (65-OperandBitSize)))
1144 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
1147 // FIXME: Implement the rest of these.
1149 // Fold bit comparisons when we can.
1150 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1151 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
1152 if (ConstantSDNode *AndRHS =
1153 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1154 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1155 // Perform the xform if the AND RHS is a single bit.
1156 if (isPowerOf2_64(AndRHS->getValue())) {
1157 return DAG.getNode(ISD::SRL, VT, N0,
1158 DAG.getConstant(Log2_64(AndRHS->getValue()),
1159 getShiftAmountTy()));
1161 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
1162 // (X & 8) == 8 --> (X & 8) >> 3
1163 // Perform the xform if C1 is a single bit.
1164 if (isPowerOf2_64(C1)) {
1165 return DAG.getNode(ISD::SRL, VT, N0,
1166 DAG.getConstant(Log2_64(C1), getShiftAmountTy()));
1171 } else if (isa<ConstantSDNode>(N0.Val)) {
1172 // Ensure that the constant occurs on the RHS.
1173 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1176 if (isa<ConstantFPSDNode>(N0.Val)) {
1177 // Constant fold or commute setcc.
1178 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond);
1179 if (O.Val) return O;
1183 // We can always fold X == X for integer setcc's.
1184 if (MVT::isInteger(N0.getValueType()))
1185 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1186 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1187 if (UOF == 2) // FP operators that are undefined on NaNs.
1188 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
1189 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1190 return DAG.getConstant(UOF, VT);
1191 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1192 // if it is not already.
1193 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1194 if (NewCond != Cond)
1195 return DAG.getSetCC(VT, N0, N1, NewCond);
1198 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1199 MVT::isInteger(N0.getValueType())) {
1200 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1201 N0.getOpcode() == ISD::XOR) {
1202 // Simplify (X+Y) == (X+Z) --> Y == Z
1203 if (N0.getOpcode() == N1.getOpcode()) {
1204 if (N0.getOperand(0) == N1.getOperand(0))
1205 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
1206 if (N0.getOperand(1) == N1.getOperand(1))
1207 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
1208 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1209 // If X op Y == Y op X, try other combinations.
1210 if (N0.getOperand(0) == N1.getOperand(1))
1211 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
1212 if (N0.getOperand(1) == N1.getOperand(0))
1213 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
1217 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1218 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1219 // Turn (X+C1) == C2 --> X == C2-C1
1220 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
1221 return DAG.getSetCC(VT, N0.getOperand(0),
1222 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
1223 N0.getValueType()), Cond);
1226 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1227 if (N0.getOpcode() == ISD::XOR)
1228 // If we know that all of the inverted bits are zero, don't bother
1229 // performing the inversion.
1230 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
1231 return DAG.getSetCC(VT, N0.getOperand(0),
1232 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
1233 N0.getValueType()), Cond);
1236 // Turn (C1-X) == C2 --> X == C1-C2
1237 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1238 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
1239 return DAG.getSetCC(VT, N0.getOperand(1),
1240 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
1241 N0.getValueType()), Cond);
1246 // Simplify (X+Z) == X --> Z == 0
1247 if (N0.getOperand(0) == N1)
1248 return DAG.getSetCC(VT, N0.getOperand(1),
1249 DAG.getConstant(0, N0.getValueType()), Cond);
1250 if (N0.getOperand(1) == N1) {
1251 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1252 return DAG.getSetCC(VT, N0.getOperand(0),
1253 DAG.getConstant(0, N0.getValueType()), Cond);
1254 else if (N0.Val->hasOneUse()) {
1255 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1256 // (Z-X) == X --> Z == X<<1
1257 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
1259 DAG.getConstant(1, getShiftAmountTy()));
1260 if (!DCI.isCalledByLegalizer())
1261 DCI.AddToWorklist(SH.Val);
1262 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
1267 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1268 N1.getOpcode() == ISD::XOR) {
1269 // Simplify X == (X+Z) --> Z == 0
1270 if (N1.getOperand(0) == N0) {
1271 return DAG.getSetCC(VT, N1.getOperand(1),
1272 DAG.getConstant(0, N1.getValueType()), Cond);
1273 } else if (N1.getOperand(1) == N0) {
1274 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
1275 return DAG.getSetCC(VT, N1.getOperand(0),
1276 DAG.getConstant(0, N1.getValueType()), Cond);
1277 } else if (N1.Val->hasOneUse()) {
1278 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1279 // X == (Z-X) --> X<<1 == Z
1280 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
1281 DAG.getConstant(1, getShiftAmountTy()));
1282 if (!DCI.isCalledByLegalizer())
1283 DCI.AddToWorklist(SH.Val);
1284 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
1290 // Fold away ALL boolean setcc's.
1292 if (N0.getValueType() == MVT::i1 && foldBooleans) {
1294 default: assert(0 && "Unknown integer setcc!");
1295 case ISD::SETEQ: // X == Y -> (X^Y)^1
1296 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1297 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
1298 if (!DCI.isCalledByLegalizer())
1299 DCI.AddToWorklist(Temp.Val);
1301 case ISD::SETNE: // X != Y --> (X^Y)
1302 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
1304 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
1305 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
1306 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1307 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
1308 if (!DCI.isCalledByLegalizer())
1309 DCI.AddToWorklist(Temp.Val);
1311 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
1312 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
1313 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1314 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
1315 if (!DCI.isCalledByLegalizer())
1316 DCI.AddToWorklist(Temp.Val);
1318 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
1319 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
1320 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
1321 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
1322 if (!DCI.isCalledByLegalizer())
1323 DCI.AddToWorklist(Temp.Val);
1325 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
1326 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
1327 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
1328 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
1331 if (VT != MVT::i1) {
1332 if (!DCI.isCalledByLegalizer())
1333 DCI.AddToWorklist(N0.Val);
1334 // FIXME: If running after legalize, we probably can't do this.
1335 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1340 // Could not fold it.
1344 SDOperand TargetLowering::
1345 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1346 // Default implementation: no optimization.
1350 //===----------------------------------------------------------------------===//
1351 // Inline Assembler Implementation Methods
1352 //===----------------------------------------------------------------------===//
1354 TargetLowering::ConstraintType
1355 TargetLowering::getConstraintType(const std::string &Constraint) const {
1356 // FIXME: lots more standard ones to handle.
1357 if (Constraint.size() == 1) {
1358 switch (Constraint[0]) {
1360 case 'r': return C_RegisterClass;
1362 case 'o': // offsetable
1363 case 'V': // not offsetable
1365 case 'i': // Simple Integer or Relocatable Constant
1366 case 'n': // Simple Integer
1367 case 's': // Relocatable Constant
1368 case 'X': // Allow ANY value.
1369 case 'I': // Target registers.
1381 if (Constraint.size() > 1 && Constraint[0] == '{' &&
1382 Constraint[Constraint.size()-1] == '}')
1387 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1388 /// vector. If it is invalid, don't add anything to Ops.
1389 void TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
1390 char ConstraintLetter,
1391 std::vector<SDOperand> &Ops,
1392 SelectionDAG &DAG) {
1393 switch (ConstraintLetter) {
1395 case 'i': // Simple Integer or Relocatable Constant
1396 case 'n': // Simple Integer
1397 case 's': // Relocatable Constant
1398 case 'X': { // Allows any operand.
1399 // These operands are interested in values of the form (GV+C), where C may
1400 // be folded in as an offset of GV, or it may be explicitly added. Also, it
1401 // is possible and fine if either GV or C are missing.
1402 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1403 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
1405 // If we have "(add GV, C)", pull out GV/C
1406 if (Op.getOpcode() == ISD::ADD) {
1407 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1408 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
1409 if (C == 0 || GA == 0) {
1410 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
1411 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
1413 if (C == 0 || GA == 0)
1417 // If we find a valid operand, map to the TargetXXX version so that the
1418 // value itself doesn't get selected.
1419 if (GA) { // Either &GV or &GV+C
1420 if (ConstraintLetter != 'n') {
1421 int64_t Offs = GA->getOffset();
1422 if (C) Offs += C->getValue();
1423 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
1424 Op.getValueType(), Offs));
1428 if (C) { // just C, no GV.
1429 // Simple constants are not allowed for 's'.
1430 if (ConstraintLetter != 's') {
1431 Ops.push_back(DAG.getTargetConstant(C->getValue(), Op.getValueType()));
1440 std::vector<unsigned> TargetLowering::
1441 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1442 MVT::ValueType VT) const {
1443 return std::vector<unsigned>();
1447 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
1448 getRegForInlineAsmConstraint(const std::string &Constraint,
1449 MVT::ValueType VT) const {
1450 if (Constraint[0] != '{')
1451 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1452 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
1454 // Remove the braces from around the name.
1455 std::string RegName(Constraint.begin()+1, Constraint.end()-1);
1457 // Figure out which register class contains this reg.
1458 const MRegisterInfo *RI = TM.getRegisterInfo();
1459 for (MRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
1460 E = RI->regclass_end(); RCI != E; ++RCI) {
1461 const TargetRegisterClass *RC = *RCI;
1463 // If none of the the value types for this register class are valid, we
1464 // can't use it. For example, 64-bit reg classes on 32-bit targets.
1465 bool isLegal = false;
1466 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1468 if (isTypeLegal(*I)) {
1474 if (!isLegal) continue;
1476 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
1478 if (StringsEqualNoCase(RegName, RI->get(*I).Name))
1479 return std::make_pair(*I, RC);
1483 return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
1486 //===----------------------------------------------------------------------===//
1487 // Loop Strength Reduction hooks
1488 //===----------------------------------------------------------------------===//
1490 /// isLegalAddressingMode - Return true if the addressing mode represented
1491 /// by AM is legal for this target, for a load/store of the specified type.
1492 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
1493 const Type *Ty) const {
1494 // The default implementation of this implements a conservative RISCy, r+r and
1497 // Allows a sign-extended 16-bit immediate field.
1498 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1501 // No global is ever allowed as a base.
1505 // Only support r+r,
1507 case 0: // "r+i" or just "i", depending on HasBaseReg.
1510 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1512 // Otherwise we have r+r or r+i.
1515 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1517 // Allow 2*r as r+r.
1524 // Magic for divide replacement
1527 int64_t m; // magic number
1528 int64_t s; // shift amount
1532 uint64_t m; // magic number
1533 int64_t a; // add indicator
1534 int64_t s; // shift amount
1537 /// magic - calculate the magic numbers required to codegen an integer sdiv as
1538 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
1540 static ms magic32(int32_t d) {
1542 uint32_t ad, anc, delta, q1, r1, q2, r2, t;
1543 const uint32_t two31 = 0x80000000U;
1547 t = two31 + ((uint32_t)d >> 31);
1548 anc = t - 1 - t%ad; // absolute value of nc
1549 p = 31; // initialize p
1550 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
1551 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
1552 q2 = two31/ad; // initialize q2 = 2p/abs(d)
1553 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
1556 q1 = 2*q1; // update q1 = 2p/abs(nc)
1557 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
1558 if (r1 >= anc) { // must be unsigned comparison
1562 q2 = 2*q2; // update q2 = 2p/abs(d)
1563 r2 = 2*r2; // update r2 = rem(2p/abs(d))
1564 if (r2 >= ad) { // must be unsigned comparison
1569 } while (q1 < delta || (q1 == delta && r1 == 0));
1571 mag.m = (int32_t)(q2 + 1); // make sure to sign extend
1572 if (d < 0) mag.m = -mag.m; // resulting magic number
1573 mag.s = p - 32; // resulting shift
1577 /// magicu - calculate the magic numbers required to codegen an integer udiv as
1578 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
1579 static mu magicu32(uint32_t d) {
1581 uint32_t nc, delta, q1, r1, q2, r2;
1583 magu.a = 0; // initialize "add" indicator
1585 p = 31; // initialize p
1586 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
1587 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
1588 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
1589 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
1592 if (r1 >= nc - r1 ) {
1593 q1 = 2*q1 + 1; // update q1
1594 r1 = 2*r1 - nc; // update r1
1597 q1 = 2*q1; // update q1
1598 r1 = 2*r1; // update r1
1600 if (r2 + 1 >= d - r2) {
1601 if (q2 >= 0x7FFFFFFF) magu.a = 1;
1602 q2 = 2*q2 + 1; // update q2
1603 r2 = 2*r2 + 1 - d; // update r2
1606 if (q2 >= 0x80000000) magu.a = 1;
1607 q2 = 2*q2; // update q2
1608 r2 = 2*r2 + 1; // update r2
1611 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
1612 magu.m = q2 + 1; // resulting magic number
1613 magu.s = p - 32; // resulting shift
1617 /// magic - calculate the magic numbers required to codegen an integer sdiv as
1618 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
1620 static ms magic64(int64_t d) {
1622 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
1623 const uint64_t two63 = 9223372036854775808ULL; // 2^63
1626 ad = d >= 0 ? d : -d;
1627 t = two63 + ((uint64_t)d >> 63);
1628 anc = t - 1 - t%ad; // absolute value of nc
1629 p = 63; // initialize p
1630 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
1631 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
1632 q2 = two63/ad; // initialize q2 = 2p/abs(d)
1633 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
1636 q1 = 2*q1; // update q1 = 2p/abs(nc)
1637 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
1638 if (r1 >= anc) { // must be unsigned comparison
1642 q2 = 2*q2; // update q2 = 2p/abs(d)
1643 r2 = 2*r2; // update r2 = rem(2p/abs(d))
1644 if (r2 >= ad) { // must be unsigned comparison
1649 } while (q1 < delta || (q1 == delta && r1 == 0));
1652 if (d < 0) mag.m = -mag.m; // resulting magic number
1653 mag.s = p - 64; // resulting shift
1657 /// magicu - calculate the magic numbers required to codegen an integer udiv as
1658 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
1659 static mu magicu64(uint64_t d)
1662 uint64_t nc, delta, q1, r1, q2, r2;
1664 magu.a = 0; // initialize "add" indicator
1666 p = 63; // initialize p
1667 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
1668 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
1669 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
1670 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
1673 if (r1 >= nc - r1 ) {
1674 q1 = 2*q1 + 1; // update q1
1675 r1 = 2*r1 - nc; // update r1
1678 q1 = 2*q1; // update q1
1679 r1 = 2*r1; // update r1
1681 if (r2 + 1 >= d - r2) {
1682 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
1683 q2 = 2*q2 + 1; // update q2
1684 r2 = 2*r2 + 1 - d; // update r2
1687 if (q2 >= 0x8000000000000000ull) magu.a = 1;
1688 q2 = 2*q2; // update q2
1689 r2 = 2*r2 + 1; // update r2
1692 } while (p < 128 && (q1 < delta || (q1 == delta && r1 == 0)));
1693 magu.m = q2 + 1; // resulting magic number
1694 magu.s = p - 64; // resulting shift
1698 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
1699 /// return a DAG expression to select that will generate the same value by
1700 /// multiplying by a magic number. See:
1701 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
1702 SDOperand TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
1703 std::vector<SDNode*>* Created) const {
1704 MVT::ValueType VT = N->getValueType(0);
1706 // Check to see if we can do this.
1707 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
1708 return SDOperand(); // BuildSDIV only operates on i32 or i64
1709 if (!isOperationLegal(ISD::MULHS, VT))
1710 return SDOperand(); // Make sure the target supports MULHS.
1712 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
1713 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
1715 // Multiply the numerator (operand 0) by the magic value
1716 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
1717 DAG.getConstant(magics.m, VT));
1718 // If d > 0 and m < 0, add the numerator
1719 if (d > 0 && magics.m < 0) {
1720 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
1722 Created->push_back(Q.Val);
1724 // If d < 0 and m > 0, subtract the numerator.
1725 if (d < 0 && magics.m > 0) {
1726 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
1728 Created->push_back(Q.Val);
1730 // Shift right algebraic if shift value is nonzero
1732 Q = DAG.getNode(ISD::SRA, VT, Q,
1733 DAG.getConstant(magics.s, getShiftAmountTy()));
1735 Created->push_back(Q.Val);
1737 // Extract the sign bit and add it to the quotient
1739 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
1740 getShiftAmountTy()));
1742 Created->push_back(T.Val);
1743 return DAG.getNode(ISD::ADD, VT, Q, T);
1746 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
1747 /// return a DAG expression to select that will generate the same value by
1748 /// multiplying by a magic number. See:
1749 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
1750 SDOperand TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
1751 std::vector<SDNode*>* Created) const {
1752 MVT::ValueType VT = N->getValueType(0);
1754 // Check to see if we can do this.
1755 if (!isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
1756 return SDOperand(); // BuildUDIV only operates on i32 or i64
1757 if (!isOperationLegal(ISD::MULHU, VT))
1758 return SDOperand(); // Make sure the target supports MULHU.
1760 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
1761 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
1763 // Multiply the numerator (operand 0) by the magic value
1764 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
1765 DAG.getConstant(magics.m, VT));
1767 Created->push_back(Q.Val);
1769 if (magics.a == 0) {
1770 return DAG.getNode(ISD::SRL, VT, Q,
1771 DAG.getConstant(magics.s, getShiftAmountTy()));
1773 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
1775 Created->push_back(NPQ.Val);
1776 NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
1777 DAG.getConstant(1, getShiftAmountTy()));
1779 Created->push_back(NPQ.Val);
1780 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
1782 Created->push_back(NPQ.Val);
1783 return DAG.getNode(ISD::SRL, VT, NPQ,
1784 DAG.getConstant(magics.s-1, getShiftAmountTy()));