1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/ADT/BitVector.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/Analysis.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/IR/DerivedTypes.h"
24 #include "llvm/IR/GlobalVariable.h"
25 #include "llvm/IR/LLVMContext.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCExpr.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Target/TargetLoweringObjectFile.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
34 #include "llvm/Target/TargetSubtargetInfo.h"
38 /// NOTE: The TargetMachine owns TLOF.
39 TargetLowering::TargetLowering(const TargetMachine &tm)
40 : TargetLoweringBase(tm) {}
42 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
46 /// Check whether a given call node is in tail position within its function. If
47 /// so, it sets Chain to the input chain of the tail call.
48 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
49 SDValue &Chain) const {
50 const Function *F = DAG.getMachineFunction().getFunction();
52 // Conservatively require the attributes of the call to match those of
53 // the return. Ignore noalias because it doesn't affect the call sequence.
54 AttributeSet CallerAttrs = F->getAttributes();
55 if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex)
56 .removeAttribute(Attribute::NoAlias).hasAttributes())
59 // It's not safe to eliminate the sign / zero extension of the return value.
60 if (CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt) ||
61 CallerAttrs.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
64 // Check if the only use is a function return node.
65 return isUsedByReturnOnly(Node, Chain);
68 /// \brief Set CallLoweringInfo attribute flags based on a call instruction
69 /// and called function attributes.
70 void TargetLowering::ArgListEntry::setAttributes(ImmutableCallSite *CS,
72 isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt);
73 isZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt);
74 isInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg);
75 isSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet);
76 isNest = CS->paramHasAttr(AttrIdx, Attribute::Nest);
77 isByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal);
78 isInAlloca = CS->paramHasAttr(AttrIdx, Attribute::InAlloca);
79 isReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned);
80 Alignment = CS->getParamAlignment(AttrIdx);
83 /// Generate a libcall taking the given operands as arguments and returning a
84 /// result of type RetVT.
85 std::pair<SDValue, SDValue>
86 TargetLowering::makeLibCall(SelectionDAG &DAG,
87 RTLIB::Libcall LC, EVT RetVT,
88 const SDValue *Ops, unsigned NumOps,
89 bool isSigned, SDLoc dl,
91 bool isReturnValueUsed) const {
92 TargetLowering::ArgListTy Args;
95 TargetLowering::ArgListEntry Entry;
96 for (unsigned i = 0; i != NumOps; ++i) {
98 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
99 Entry.isSExt = shouldSignExtendTypeInLibCall(Ops[i].getValueType(), isSigned);
100 Entry.isZExt = !shouldSignExtendTypeInLibCall(Ops[i].getValueType(), isSigned);
101 Args.push_back(Entry);
103 if (LC == RTLIB::UNKNOWN_LIBCALL)
104 report_fatal_error("Unsupported library call operation!");
105 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), getPointerTy());
107 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
108 TargetLowering::CallLoweringInfo CLI(DAG);
109 bool signExtend = shouldSignExtendTypeInLibCall(RetVT, isSigned);
110 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
111 .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
112 .setNoReturn(doesNotReturn).setDiscardResult(!isReturnValueUsed)
113 .setSExtResult(signExtend).setZExtResult(!signExtend);
114 return LowerCallTo(CLI);
118 /// SoftenSetCCOperands - Soften the operands of a comparison. This code is
119 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
120 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
121 SDValue &NewLHS, SDValue &NewRHS,
122 ISD::CondCode &CCCode,
124 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
125 && "Unsupported setcc type!");
127 // Expand into one or more soft-fp libcall(s).
128 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
132 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
133 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
137 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
138 (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128;
142 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
143 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
147 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
148 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
152 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
153 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
157 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
158 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
161 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
162 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
165 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
166 (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128;
169 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
170 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
173 // SETONE = SETOLT | SETOGT
174 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
175 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
178 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
179 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
182 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
183 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
186 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
187 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
190 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
191 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
194 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
195 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
197 default: llvm_unreachable("Do not know how to soften this setcc!");
201 // Use the target specific return value for comparions lib calls.
202 EVT RetVT = getCmpLibcallReturnType();
203 SDValue Ops[2] = { NewLHS, NewRHS };
204 NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, 2, false/*sign irrelevant*/,
206 NewRHS = DAG.getConstant(0, dl, RetVT);
207 CCCode = getCmpLibcallCC(LC1);
208 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
209 SDValue Tmp = DAG.getNode(ISD::SETCC, dl,
210 getSetCCResultType(*DAG.getContext(), RetVT),
211 NewLHS, NewRHS, DAG.getCondCode(CCCode));
212 NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, 2, false/*sign irrelevant*/,
214 NewLHS = DAG.getNode(ISD::SETCC, dl,
215 getSetCCResultType(*DAG.getContext(), RetVT), NewLHS,
216 NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2)));
217 NewLHS = DAG.getNode(ISD::OR, dl, Tmp.getValueType(), Tmp, NewLHS);
222 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
223 /// current function. The returned value is a member of the
224 /// MachineJumpTableInfo::JTEntryKind enum.
225 unsigned TargetLowering::getJumpTableEncoding() const {
226 // In non-pic modes, just use the address of a block.
227 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
228 return MachineJumpTableInfo::EK_BlockAddress;
230 // In PIC mode, if the target supports a GPRel32 directive, use it.
231 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != nullptr)
232 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
234 // Otherwise, use a label difference.
235 return MachineJumpTableInfo::EK_LabelDifference32;
238 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
239 SelectionDAG &DAG) const {
240 // If our PIC model is GP relative, use the global offset table as the base.
241 unsigned JTEncoding = getJumpTableEncoding();
243 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
244 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
245 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy(0));
250 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
251 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
254 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
255 unsigned JTI,MCContext &Ctx) const{
256 // The normal PIC reloc base is the label at the start of the jump table.
257 return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx);
261 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
262 // Assume that everything is safe in static mode.
263 if (getTargetMachine().getRelocationModel() == Reloc::Static)
266 // In dynamic-no-pic mode, assume that known defined values are safe.
267 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
268 GA && GA->getGlobal()->isStrongDefinitionForLinker())
271 // Otherwise assume nothing is safe.
275 //===----------------------------------------------------------------------===//
276 // Optimization Methods
277 //===----------------------------------------------------------------------===//
279 /// ShrinkDemandedConstant - Check to see if the specified operand of the
280 /// specified instruction is a constant integer. If so, check to see if there
281 /// are any bits set in the constant that are not demanded. If so, shrink the
282 /// constant and return true.
283 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
284 const APInt &Demanded) {
287 // FIXME: ISD::SELECT, ISD::SELECT_CC
288 switch (Op.getOpcode()) {
293 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
294 if (!C) return false;
296 if (Op.getOpcode() == ISD::XOR &&
297 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
300 // if we can expand it to have all bits set, do it
301 if (C->getAPIntValue().intersects(~Demanded)) {
302 EVT VT = Op.getValueType();
303 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
304 DAG.getConstant(Demanded &
307 return CombineTo(Op, New);
317 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
318 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
319 /// cast, but it could be generalized for targets with other types of
320 /// implicit widening casts.
322 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
324 const APInt &Demanded,
326 assert(Op.getNumOperands() == 2 &&
327 "ShrinkDemandedOp only supports binary operators!");
328 assert(Op.getNode()->getNumValues() == 1 &&
329 "ShrinkDemandedOp only supports nodes with one result!");
331 // Early return, as this function cannot handle vector types.
332 if (Op.getValueType().isVector())
335 // Don't do this if the node has another user, which may require the
337 if (!Op.getNode()->hasOneUse())
340 // Search for the smallest integer type with free casts to and from
341 // Op's type. For expedience, just check power-of-2 integer types.
342 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
343 unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros();
344 unsigned SmallVTBits = DemandedSize;
345 if (!isPowerOf2_32(SmallVTBits))
346 SmallVTBits = NextPowerOf2(SmallVTBits);
347 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
348 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
349 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
350 TLI.isZExtFree(SmallVT, Op.getValueType())) {
351 // We found a type with free casts.
352 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
353 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
354 Op.getNode()->getOperand(0)),
355 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
356 Op.getNode()->getOperand(1)));
357 bool NeedZext = DemandedSize > SmallVTBits;
358 SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND,
359 dl, Op.getValueType(), X);
360 return CombineTo(Op, Z);
366 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
367 /// DemandedMask bits of the result of Op are ever used downstream. If we can
368 /// use this information to simplify Op, create a new simplified DAG node and
369 /// return true, returning the original and new nodes in Old and New. Otherwise,
370 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
371 /// the expression (used to simplify the caller). The KnownZero/One bits may
372 /// only be accurate for those bits in the DemandedMask.
373 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
374 const APInt &DemandedMask,
377 TargetLoweringOpt &TLO,
378 unsigned Depth) const {
379 unsigned BitWidth = DemandedMask.getBitWidth();
380 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
381 "Mask size mismatches value type size!");
382 APInt NewMask = DemandedMask;
385 // Don't know anything.
386 KnownZero = KnownOne = APInt(BitWidth, 0);
388 // Other users may use these bits.
389 if (!Op.getNode()->hasOneUse()) {
391 // If not at the root, Just compute the KnownZero/KnownOne bits to
392 // simplify things downstream.
393 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
396 // If this is the root being simplified, allow it to have multiple uses,
397 // just set the NewMask to all bits.
398 NewMask = APInt::getAllOnesValue(BitWidth);
399 } else if (DemandedMask == 0) {
400 // Not demanding any bits from Op.
401 if (Op.getOpcode() != ISD::UNDEF)
402 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
404 } else if (Depth == 6) { // Limit search depth.
408 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
409 switch (Op.getOpcode()) {
411 // We know all of the bits for a constant!
412 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
413 KnownZero = ~KnownOne;
414 return false; // Don't fall through, will infinitely loop.
416 // If the RHS is a constant, check to see if the LHS would be zero without
417 // using the bits from the RHS. Below, we use knowledge about the RHS to
418 // simplify the LHS, here we're using information from the LHS to simplify
420 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
421 APInt LHSZero, LHSOne;
422 // Do not increment Depth here; that can cause an infinite loop.
423 TLO.DAG.computeKnownBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
424 // If the LHS already has zeros where RHSC does, this and is dead.
425 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
426 return TLO.CombineTo(Op, Op.getOperand(0));
427 // If any of the set bits in the RHS are known zero on the LHS, shrink
429 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
433 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
434 KnownOne, TLO, Depth+1))
436 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
437 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
438 KnownZero2, KnownOne2, TLO, Depth+1))
440 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
442 // If all of the demanded bits are known one on one side, return the other.
443 // These bits cannot contribute to the result of the 'and'.
444 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
445 return TLO.CombineTo(Op, Op.getOperand(0));
446 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
447 return TLO.CombineTo(Op, Op.getOperand(1));
448 // If all of the demanded bits in the inputs are known zeros, return zero.
449 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
450 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, Op.getValueType()));
451 // If the RHS is a constant, see if we can simplify it.
452 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
454 // If the operation can be done in a smaller type, do so.
455 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
458 // Output known-1 bits are only known if set in both the LHS & RHS.
459 KnownOne &= KnownOne2;
460 // Output known-0 are known to be clear if zero in either the LHS | RHS.
461 KnownZero |= KnownZero2;
464 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
465 KnownOne, TLO, Depth+1))
467 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
468 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
469 KnownZero2, KnownOne2, TLO, Depth+1))
471 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
473 // If all of the demanded bits are known zero on one side, return the other.
474 // These bits cannot contribute to the result of the 'or'.
475 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
476 return TLO.CombineTo(Op, Op.getOperand(0));
477 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
478 return TLO.CombineTo(Op, Op.getOperand(1));
479 // If all of the potentially set bits on one side are known to be set on
480 // the other side, just use the 'other' side.
481 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
482 return TLO.CombineTo(Op, Op.getOperand(0));
483 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
484 return TLO.CombineTo(Op, Op.getOperand(1));
485 // If the RHS is a constant, see if we can simplify it.
486 if (TLO.ShrinkDemandedConstant(Op, NewMask))
488 // If the operation can be done in a smaller type, do so.
489 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
492 // Output known-0 bits are only known if clear in both the LHS & RHS.
493 KnownZero &= KnownZero2;
494 // Output known-1 are known to be set if set in either the LHS | RHS.
495 KnownOne |= KnownOne2;
498 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
499 KnownOne, TLO, Depth+1))
501 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
502 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
503 KnownOne2, TLO, Depth+1))
505 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
507 // If all of the demanded bits are known zero on one side, return the other.
508 // These bits cannot contribute to the result of the 'xor'.
509 if ((KnownZero & NewMask) == NewMask)
510 return TLO.CombineTo(Op, Op.getOperand(0));
511 if ((KnownZero2 & NewMask) == NewMask)
512 return TLO.CombineTo(Op, Op.getOperand(1));
513 // If the operation can be done in a smaller type, do so.
514 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
517 // If all of the unknown bits are known to be zero on one side or the other
518 // (but not both) turn this into an *inclusive* or.
519 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
520 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
521 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
525 // Output known-0 bits are known if clear or set in both the LHS & RHS.
526 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
527 // Output known-1 are known to be set if set in only one of the LHS, RHS.
528 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
530 // If all of the demanded bits on one side are known, and all of the set
531 // bits on that side are also known to be set on the other side, turn this
532 // into an AND, as we know the bits will be cleared.
533 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
534 // NB: it is okay if more bits are known than are requested
535 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
536 if (KnownOne == KnownOne2) { // set bits are the same on both sides
537 EVT VT = Op.getValueType();
538 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, dl, VT);
539 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
540 Op.getOperand(0), ANDC));
544 // If the RHS is a constant, see if we can simplify it.
545 // for XOR, we prefer to force bits to 1 if they will make a -1.
546 // if we can't force bits, try to shrink constant
547 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
548 APInt Expanded = C->getAPIntValue() | (~NewMask);
549 // if we can expand it to have all bits set, do it
550 if (Expanded.isAllOnesValue()) {
551 if (Expanded != C->getAPIntValue()) {
552 EVT VT = Op.getValueType();
553 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
554 TLO.DAG.getConstant(Expanded, dl, VT));
555 return TLO.CombineTo(Op, New);
557 // if it already has all the bits set, nothing to change
558 // but don't shrink either!
559 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
564 KnownZero = KnownZeroOut;
565 KnownOne = KnownOneOut;
568 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
569 KnownOne, TLO, Depth+1))
571 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
572 KnownOne2, TLO, Depth+1))
574 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
575 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
577 // If the operands are constants, see if we can simplify them.
578 if (TLO.ShrinkDemandedConstant(Op, NewMask))
581 // Only known if known in both the LHS and RHS.
582 KnownOne &= KnownOne2;
583 KnownZero &= KnownZero2;
586 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
587 KnownOne, TLO, Depth+1))
589 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
590 KnownOne2, TLO, Depth+1))
592 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
593 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
595 // If the operands are constants, see if we can simplify them.
596 if (TLO.ShrinkDemandedConstant(Op, NewMask))
599 // Only known if known in both the LHS and RHS.
600 KnownOne &= KnownOne2;
601 KnownZero &= KnownZero2;
604 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
605 unsigned ShAmt = SA->getZExtValue();
606 SDValue InOp = Op.getOperand(0);
608 // If the shift count is an invalid immediate, don't do anything.
609 if (ShAmt >= BitWidth)
612 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
613 // single shift. We can do this if the bottom bits (which are shifted
614 // out) are never demanded.
615 if (InOp.getOpcode() == ISD::SRL &&
616 isa<ConstantSDNode>(InOp.getOperand(1))) {
617 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
618 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
619 unsigned Opc = ISD::SHL;
627 TLO.DAG.getConstant(Diff, dl, Op.getOperand(1).getValueType());
628 EVT VT = Op.getValueType();
629 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
630 InOp.getOperand(0), NewSA));
634 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
635 KnownZero, KnownOne, TLO, Depth+1))
638 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
639 // are not demanded. This will likely allow the anyext to be folded away.
640 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
641 SDValue InnerOp = InOp.getNode()->getOperand(0);
642 EVT InnerVT = InnerOp.getValueType();
643 unsigned InnerBits = InnerVT.getSizeInBits();
644 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
645 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
646 EVT ShTy = getShiftAmountTy(InnerVT);
647 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
650 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
651 TLO.DAG.getConstant(ShAmt, dl, ShTy));
654 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
657 // Repeat the SHL optimization above in cases where an extension
658 // intervenes: (shl (anyext (shr x, c1)), c2) to
659 // (shl (anyext x), c2-c1). This requires that the bottom c1 bits
660 // aren't demanded (as above) and that the shifted upper c1 bits of
661 // x aren't demanded.
662 if (InOp.hasOneUse() &&
663 InnerOp.getOpcode() == ISD::SRL &&
664 InnerOp.hasOneUse() &&
665 isa<ConstantSDNode>(InnerOp.getOperand(1))) {
666 uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1))
668 if (InnerShAmt < ShAmt &&
669 InnerShAmt < InnerBits &&
670 NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
671 NewMask.trunc(ShAmt) == 0) {
673 TLO.DAG.getConstant(ShAmt - InnerShAmt, dl,
674 Op.getOperand(1).getValueType());
675 EVT VT = Op.getValueType();
676 SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT,
677 InnerOp.getOperand(0));
678 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT,
684 KnownZero <<= SA->getZExtValue();
685 KnownOne <<= SA->getZExtValue();
686 // low bits known zero.
687 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
691 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
692 EVT VT = Op.getValueType();
693 unsigned ShAmt = SA->getZExtValue();
694 unsigned VTSize = VT.getSizeInBits();
695 SDValue InOp = Op.getOperand(0);
697 // If the shift count is an invalid immediate, don't do anything.
698 if (ShAmt >= BitWidth)
701 APInt InDemandedMask = (NewMask << ShAmt);
703 // If the shift is exact, then it does demand the low bits (and knows that
705 if (cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact())
706 InDemandedMask |= APInt::getLowBitsSet(BitWidth, ShAmt);
708 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
709 // single shift. We can do this if the top bits (which are shifted out)
710 // are never demanded.
711 if (InOp.getOpcode() == ISD::SHL &&
712 isa<ConstantSDNode>(InOp.getOperand(1))) {
713 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
714 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
715 unsigned Opc = ISD::SRL;
723 TLO.DAG.getConstant(Diff, dl, Op.getOperand(1).getValueType());
724 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
725 InOp.getOperand(0), NewSA));
729 // Compute the new bits that are at the top now.
730 if (SimplifyDemandedBits(InOp, InDemandedMask,
731 KnownZero, KnownOne, TLO, Depth+1))
733 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
734 KnownZero = KnownZero.lshr(ShAmt);
735 KnownOne = KnownOne.lshr(ShAmt);
737 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
738 KnownZero |= HighBits; // High bits known zero.
742 // If this is an arithmetic shift right and only the low-bit is set, we can
743 // always convert this into a logical shr, even if the shift amount is
744 // variable. The low bit of the shift cannot be an input sign bit unless
745 // the shift amount is >= the size of the datatype, which is undefined.
747 return TLO.CombineTo(Op,
748 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
749 Op.getOperand(0), Op.getOperand(1)));
751 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
752 EVT VT = Op.getValueType();
753 unsigned ShAmt = SA->getZExtValue();
755 // If the shift count is an invalid immediate, don't do anything.
756 if (ShAmt >= BitWidth)
759 APInt InDemandedMask = (NewMask << ShAmt);
761 // If the shift is exact, then it does demand the low bits (and knows that
763 if (cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact())
764 InDemandedMask |= APInt::getLowBitsSet(BitWidth, ShAmt);
766 // If any of the demanded bits are produced by the sign extension, we also
767 // demand the input sign bit.
768 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
769 if (HighBits.intersects(NewMask))
770 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
772 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
773 KnownZero, KnownOne, TLO, Depth+1))
775 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
776 KnownZero = KnownZero.lshr(ShAmt);
777 KnownOne = KnownOne.lshr(ShAmt);
779 // Handle the sign bit, adjusted to where it is now in the mask.
780 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
782 // If the input sign bit is known to be zero, or if none of the top bits
783 // are demanded, turn this into an unsigned shift right.
784 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
786 Flags.setExact(cast<BinaryWithFlagsSDNode>(Op)->Flags.hasExact());
787 return TLO.CombineTo(Op,
788 TLO.DAG.getNode(ISD::SRL, dl, VT, Op.getOperand(0),
789 Op.getOperand(1), &Flags));
792 int Log2 = NewMask.exactLogBase2();
794 // The bit must come from the sign.
796 TLO.DAG.getConstant(BitWidth - 1 - Log2, dl,
797 Op.getOperand(1).getValueType());
798 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
799 Op.getOperand(0), NewSA));
802 if (KnownOne.intersects(SignBit))
803 // New bits are known one.
804 KnownOne |= HighBits;
807 case ISD::SIGN_EXTEND_INREG: {
808 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
810 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
811 // If we only care about the highest bit, don't bother shifting right.
812 if (MsbMask == NewMask) {
813 unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
814 SDValue InOp = Op.getOperand(0);
815 unsigned VTBits = Op->getValueType(0).getScalarType().getSizeInBits();
816 bool AlreadySignExtended =
817 TLO.DAG.ComputeNumSignBits(InOp) >= VTBits-ShAmt+1;
818 // However if the input is already sign extended we expect the sign
819 // extension to be dropped altogether later and do not simplify.
820 if (!AlreadySignExtended) {
821 // Compute the correct shift amount type, which must be getShiftAmountTy
822 // for scalar types after legalization.
823 EVT ShiftAmtTy = Op.getValueType();
824 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
825 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
827 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, dl,
829 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
830 Op.getValueType(), InOp,
835 // Sign extension. Compute the demanded bits in the result that are not
836 // present in the input.
838 APInt::getHighBitsSet(BitWidth,
839 BitWidth - ExVT.getScalarType().getSizeInBits());
841 // If none of the extended bits are demanded, eliminate the sextinreg.
842 if ((NewBits & NewMask) == 0)
843 return TLO.CombineTo(Op, Op.getOperand(0));
846 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
847 APInt InputDemandedBits =
848 APInt::getLowBitsSet(BitWidth,
849 ExVT.getScalarType().getSizeInBits()) &
852 // Since the sign extended bits are demanded, we know that the sign
854 InputDemandedBits |= InSignBit;
856 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
857 KnownZero, KnownOne, TLO, Depth+1))
859 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
861 // If the sign bit of the input is known set or clear, then we know the
862 // top bits of the result.
864 // If the input sign bit is known zero, convert this into a zero extension.
865 if (KnownZero.intersects(InSignBit))
866 return TLO.CombineTo(Op,
867 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
869 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
871 KnownZero &= ~NewBits;
872 } else { // Input sign bit unknown
873 KnownZero &= ~NewBits;
874 KnownOne &= ~NewBits;
878 case ISD::BUILD_PAIR: {
879 EVT HalfVT = Op.getOperand(0).getValueType();
880 unsigned HalfBitWidth = HalfVT.getScalarSizeInBits();
882 APInt MaskLo = NewMask.getLoBits(HalfBitWidth).trunc(HalfBitWidth);
883 APInt MaskHi = NewMask.getHiBits(HalfBitWidth).trunc(HalfBitWidth);
885 APInt KnownZeroLo, KnownOneLo;
886 APInt KnownZeroHi, KnownOneHi;
888 if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownZeroLo,
889 KnownOneLo, TLO, Depth + 1))
892 if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownZeroHi,
893 KnownOneHi, TLO, Depth + 1))
896 KnownZero = KnownZeroLo.zext(BitWidth) |
897 KnownZeroHi.zext(BitWidth).shl(HalfBitWidth);
899 KnownOne = KnownOneLo.zext(BitWidth) |
900 KnownOneHi.zext(BitWidth).shl(HalfBitWidth);
903 case ISD::ZERO_EXTEND: {
904 unsigned OperandBitWidth =
905 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
906 APInt InMask = NewMask.trunc(OperandBitWidth);
908 // If none of the top bits are demanded, convert this into an any_extend.
910 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
911 if (!NewBits.intersects(NewMask))
912 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
916 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
917 KnownZero, KnownOne, TLO, Depth+1))
919 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
920 KnownZero = KnownZero.zext(BitWidth);
921 KnownOne = KnownOne.zext(BitWidth);
922 KnownZero |= NewBits;
925 case ISD::SIGN_EXTEND: {
926 EVT InVT = Op.getOperand(0).getValueType();
927 unsigned InBits = InVT.getScalarType().getSizeInBits();
928 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
929 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
930 APInt NewBits = ~InMask & NewMask;
932 // If none of the top bits are demanded, convert this into an any_extend.
934 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
938 // Since some of the sign extended bits are demanded, we know that the sign
940 APInt InDemandedBits = InMask & NewMask;
941 InDemandedBits |= InSignBit;
942 InDemandedBits = InDemandedBits.trunc(InBits);
944 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
945 KnownOne, TLO, Depth+1))
947 KnownZero = KnownZero.zext(BitWidth);
948 KnownOne = KnownOne.zext(BitWidth);
950 // If the sign bit is known zero, convert this to a zero extend.
951 if (KnownZero.intersects(InSignBit))
952 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
956 // If the sign bit is known one, the top bits match.
957 if (KnownOne.intersects(InSignBit)) {
959 assert((KnownZero & NewBits) == 0);
960 } else { // Otherwise, top bits aren't known.
961 assert((KnownOne & NewBits) == 0);
962 assert((KnownZero & NewBits) == 0);
966 case ISD::ANY_EXTEND: {
967 unsigned OperandBitWidth =
968 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
969 APInt InMask = NewMask.trunc(OperandBitWidth);
970 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
971 KnownZero, KnownOne, TLO, Depth+1))
973 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
974 KnownZero = KnownZero.zext(BitWidth);
975 KnownOne = KnownOne.zext(BitWidth);
978 case ISD::TRUNCATE: {
979 // Simplify the input, using demanded bit information, and compute the known
980 // zero/one bits live out.
981 unsigned OperandBitWidth =
982 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
983 APInt TruncMask = NewMask.zext(OperandBitWidth);
984 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
985 KnownZero, KnownOne, TLO, Depth+1))
987 KnownZero = KnownZero.trunc(BitWidth);
988 KnownOne = KnownOne.trunc(BitWidth);
990 // If the input is only used by this truncate, see if we can shrink it based
991 // on the known demanded bits.
992 if (Op.getOperand(0).getNode()->hasOneUse()) {
993 SDValue In = Op.getOperand(0);
994 switch (In.getOpcode()) {
997 // Shrink SRL by a constant if none of the high bits shifted in are
999 if (TLO.LegalTypes() &&
1000 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1001 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1004 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1007 SDValue Shift = In.getOperand(1);
1008 if (TLO.LegalTypes()) {
1009 uint64_t ShVal = ShAmt->getZExtValue();
1011 TLO.DAG.getConstant(ShVal, dl, getShiftAmountTy(Op.getValueType()));
1014 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1015 OperandBitWidth - BitWidth);
1016 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
1018 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1019 // None of the shifted in bits are needed. Add a truncate of the
1020 // shift input, then shift it.
1021 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1024 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1033 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1036 case ISD::AssertZext: {
1037 // AssertZext demands all of the high bits, plus any of the low bits
1038 // demanded by its users.
1039 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1040 APInt InMask = APInt::getLowBitsSet(BitWidth,
1041 VT.getSizeInBits());
1042 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1043 KnownZero, KnownOne, TLO, Depth+1))
1045 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1047 KnownZero |= ~InMask & NewMask;
1051 // If this is an FP->Int bitcast and if the sign bit is the only
1052 // thing demanded, turn this into a FGETSIGN.
1053 if (!TLO.LegalOperations() &&
1054 !Op.getValueType().isVector() &&
1055 !Op.getOperand(0).getValueType().isVector() &&
1056 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1057 Op.getOperand(0).getValueType().isFloatingPoint()) {
1058 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1059 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1060 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1061 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1062 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1063 // place. We expect the SHL to be eliminated by other optimizations.
1064 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1065 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1066 if (!OpVTLegal && OpVTSizeInBits > 32)
1067 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1068 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1069 SDValue ShAmt = TLO.DAG.getConstant(ShVal, dl, Op.getValueType());
1070 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1079 // Add, Sub, and Mul don't demand any bits in positions beyond that
1080 // of the highest bit demanded of them.
1081 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1082 BitWidth - NewMask.countLeadingZeros());
1083 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1084 KnownOne2, TLO, Depth+1))
1086 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1087 KnownOne2, TLO, Depth+1))
1089 // See if the operation should be performed at a smaller bit width.
1090 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1095 // Just use computeKnownBits to compute output bits.
1096 TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
1100 // If we know the value of all of the demanded bits, return this as a
1102 if ((NewMask & (KnownZero|KnownOne)) == NewMask) {
1103 // Avoid folding to a constant if any OpaqueConstant is involved.
1104 const SDNode *N = Op.getNode();
1105 for (SDNodeIterator I = SDNodeIterator::begin(N),
1106 E = SDNodeIterator::end(N); I != E; ++I) {
1108 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
1112 return TLO.CombineTo(Op,
1113 TLO.DAG.getConstant(KnownOne, dl, Op.getValueType()));
1119 /// computeKnownBitsForTargetNode - Determine which of the bits specified
1120 /// in Mask are known to be either zero or one and return them in the
1121 /// KnownZero/KnownOne bitsets.
1122 void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
1125 const SelectionDAG &DAG,
1126 unsigned Depth) const {
1127 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1128 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1129 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1130 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1131 "Should use MaskedValueIsZero if you don't know whether Op"
1132 " is a target node!");
1133 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
1136 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1137 /// targets that want to expose additional information about sign bits to the
1139 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1140 const SelectionDAG &,
1141 unsigned Depth) const {
1142 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1143 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1144 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1145 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1146 "Should use ComputeNumSignBits if you don't know whether Op"
1147 " is a target node!");
1151 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1152 /// one bit set. This differs from computeKnownBits in that it doesn't need to
1153 /// determine which bit is set.
1155 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1156 // A left-shift of a constant one will have exactly one bit set, because
1157 // shifting the bit off the end is undefined.
1158 if (Val.getOpcode() == ISD::SHL)
1159 if (ConstantSDNode *C =
1160 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1161 if (C->getAPIntValue() == 1)
1164 // Similarly, a right-shift of a constant sign-bit will have exactly
1166 if (Val.getOpcode() == ISD::SRL)
1167 if (ConstantSDNode *C =
1168 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1169 if (C->getAPIntValue().isSignBit())
1172 // More could be done here, though the above checks are enough
1173 // to handle some common cases.
1175 // Fall back to computeKnownBits to catch other known cases.
1176 EVT OpVT = Val.getValueType();
1177 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1178 APInt KnownZero, KnownOne;
1179 DAG.computeKnownBits(Val, KnownZero, KnownOne);
1180 return (KnownZero.countPopulation() == BitWidth - 1) &&
1181 (KnownOne.countPopulation() == 1);
1184 bool TargetLowering::isConstTrueVal(const SDNode *N) const {
1188 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1190 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1194 BitVector UndefElements;
1195 CN = BV->getConstantSplatNode(&UndefElements);
1196 // Only interested in constant splats, and we don't try to handle undef
1197 // elements in identifying boolean constants.
1198 if (!CN || UndefElements.none())
1202 switch (getBooleanContents(N->getValueType(0))) {
1203 case UndefinedBooleanContent:
1204 return CN->getAPIntValue()[0];
1205 case ZeroOrOneBooleanContent:
1207 case ZeroOrNegativeOneBooleanContent:
1208 return CN->isAllOnesValue();
1211 llvm_unreachable("Invalid boolean contents");
1214 bool TargetLowering::isConstFalseVal(const SDNode *N) const {
1218 const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
1220 const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
1224 BitVector UndefElements;
1225 CN = BV->getConstantSplatNode(&UndefElements);
1226 // Only interested in constant splats, and we don't try to handle undef
1227 // elements in identifying boolean constants.
1228 if (!CN || UndefElements.none())
1232 if (getBooleanContents(N->getValueType(0)) == UndefinedBooleanContent)
1233 return !CN->getAPIntValue()[0];
1235 return CN->isNullValue();
1238 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1239 /// and cc. If it is unable to simplify it, return a null SDValue.
1241 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1242 ISD::CondCode Cond, bool foldBooleans,
1243 DAGCombinerInfo &DCI, SDLoc dl) const {
1244 SelectionDAG &DAG = DCI.DAG;
1246 // These setcc operations always fold.
1250 case ISD::SETFALSE2: return DAG.getConstant(0, dl, VT);
1252 case ISD::SETTRUE2: {
1253 TargetLowering::BooleanContent Cnt =
1254 getBooleanContents(N0->getValueType(0));
1255 return DAG.getConstant(
1256 Cnt == TargetLowering::ZeroOrNegativeOneBooleanContent ? -1ULL : 1, dl,
1261 // Ensure that the constant occurs on the RHS, and fold constant
1263 ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
1264 if (isa<ConstantSDNode>(N0.getNode()) &&
1265 (DCI.isBeforeLegalizeOps() ||
1266 isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
1267 return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
1269 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1270 const APInt &C1 = N1C->getAPIntValue();
1272 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1273 // equality comparison, then we're just comparing whether X itself is
1275 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1276 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1277 N0.getOperand(1).getOpcode() == ISD::Constant) {
1279 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1280 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1281 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1282 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1283 // (srl (ctlz x), 5) == 0 -> X != 0
1284 // (srl (ctlz x), 5) != 1 -> X != 0
1287 // (srl (ctlz x), 5) != 0 -> X == 0
1288 // (srl (ctlz x), 5) == 1 -> X == 0
1291 SDValue Zero = DAG.getConstant(0, dl, N0.getValueType());
1292 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1298 // Look through truncs that don't change the value of a ctpop.
1299 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1300 CTPOP = N0.getOperand(0);
1302 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1303 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1304 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1305 EVT CTVT = CTPOP.getValueType();
1306 SDValue CTOp = CTPOP.getOperand(0);
1308 // (ctpop x) u< 2 -> (x & x-1) == 0
1309 // (ctpop x) u> 1 -> (x & x-1) != 0
1310 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1311 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1312 DAG.getConstant(1, dl, CTVT));
1313 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1314 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1315 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, dl, CTVT), CC);
1318 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1321 // (zext x) == C --> x == (trunc C)
1322 // (sext x) == C --> x == (trunc C)
1323 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1324 DCI.isBeforeLegalize() && N0->hasOneUse()) {
1325 unsigned MinBits = N0.getValueSizeInBits();
1327 bool Signed = false;
1328 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1330 MinBits = N0->getOperand(0).getValueSizeInBits();
1331 PreExt = N0->getOperand(0);
1332 } else if (N0->getOpcode() == ISD::AND) {
1333 // DAGCombine turns costly ZExts into ANDs
1334 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1335 if ((C->getAPIntValue()+1).isPowerOf2()) {
1336 MinBits = C->getAPIntValue().countTrailingOnes();
1337 PreExt = N0->getOperand(0);
1339 } else if (N0->getOpcode() == ISD::SIGN_EXTEND) {
1341 MinBits = N0->getOperand(0).getValueSizeInBits();
1342 PreExt = N0->getOperand(0);
1344 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1345 // ZEXTLOAD / SEXTLOAD
1346 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1347 MinBits = LN0->getMemoryVT().getSizeInBits();
1349 } else if (LN0->getExtensionType() == ISD::SEXTLOAD) {
1351 MinBits = LN0->getMemoryVT().getSizeInBits();
1356 // Figure out how many bits we need to preserve this constant.
1357 unsigned ReqdBits = Signed ?
1358 C1.getBitWidth() - C1.getNumSignBits() + 1 :
1361 // Make sure we're not losing bits from the constant.
1363 MinBits < C1.getBitWidth() &&
1364 MinBits >= ReqdBits) {
1365 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
1366 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
1367 // Will get folded away.
1368 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreExt);
1369 SDValue C = DAG.getConstant(C1.trunc(MinBits), dl, MinVT);
1370 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
1375 // If the LHS is '(and load, const)', the RHS is 0,
1376 // the test is for equality or unsigned, and all 1 bits of the const are
1377 // in the same partial word, see if we can shorten the load.
1378 if (DCI.isBeforeLegalize() &&
1379 !ISD::isSignedIntSetCC(Cond) &&
1380 N0.getOpcode() == ISD::AND && C1 == 0 &&
1381 N0.getNode()->hasOneUse() &&
1382 isa<LoadSDNode>(N0.getOperand(0)) &&
1383 N0.getOperand(0).getNode()->hasOneUse() &&
1384 isa<ConstantSDNode>(N0.getOperand(1))) {
1385 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
1387 unsigned bestWidth = 0, bestOffset = 0;
1388 if (!Lod->isVolatile() && Lod->isUnindexed()) {
1389 unsigned origWidth = N0.getValueType().getSizeInBits();
1390 unsigned maskWidth = origWidth;
1391 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
1392 // 8 bits, but have to be careful...
1393 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
1394 origWidth = Lod->getMemoryVT().getSizeInBits();
1396 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1397 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
1398 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
1399 for (unsigned offset=0; offset<origWidth/width; offset++) {
1400 if ((newMask & Mask) == Mask) {
1401 if (!getDataLayout()->isLittleEndian())
1402 bestOffset = (origWidth/width - offset - 1) * (width/8);
1404 bestOffset = (uint64_t)offset * (width/8);
1405 bestMask = Mask.lshr(offset * (width/8) * 8);
1409 newMask = newMask << width;
1414 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
1415 if (newVT.isRound()) {
1416 EVT PtrType = Lod->getOperand(1).getValueType();
1417 SDValue Ptr = Lod->getBasePtr();
1418 if (bestOffset != 0)
1419 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
1420 DAG.getConstant(bestOffset, dl, PtrType));
1421 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
1422 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
1423 Lod->getPointerInfo().getWithOffset(bestOffset),
1424 false, false, false, NewAlign);
1425 return DAG.getSetCC(dl, VT,
1426 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
1427 DAG.getConstant(bestMask.trunc(bestWidth),
1429 DAG.getConstant(0LL, dl, newVT), Cond);
1434 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1435 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1436 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
1438 // If the comparison constant has bits in the upper part, the
1439 // zero-extended value could never match.
1440 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
1441 C1.getBitWidth() - InSize))) {
1445 case ISD::SETEQ: return DAG.getConstant(0, dl, VT);
1448 case ISD::SETNE: return DAG.getConstant(1, dl, VT);
1451 // True if the sign bit of C1 is set.
1452 return DAG.getConstant(C1.isNegative(), dl, VT);
1455 // True if the sign bit of C1 isn't set.
1456 return DAG.getConstant(C1.isNonNegative(), dl, VT);
1462 // Otherwise, we can perform the comparison with the low bits.
1470 EVT newVT = N0.getOperand(0).getValueType();
1471 if (DCI.isBeforeLegalizeOps() ||
1472 (isOperationLegal(ISD::SETCC, newVT) &&
1473 getCondCodeAction(Cond, newVT.getSimpleVT()) == Legal)) {
1474 EVT NewSetCCVT = getSetCCResultType(*DAG.getContext(), newVT);
1475 SDValue NewConst = DAG.getConstant(C1.trunc(InSize), dl, newVT);
1477 SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0),
1479 return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType());
1484 break; // todo, be more careful with signed comparisons
1486 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1487 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1488 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1489 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
1490 EVT ExtDstTy = N0.getValueType();
1491 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
1493 // If the constant doesn't fit into the number of bits for the source of
1494 // the sign extension, it is impossible for both sides to be equal.
1495 if (C1.getMinSignedBits() > ExtSrcTyBits)
1496 return DAG.getConstant(Cond == ISD::SETNE, dl, VT);
1499 EVT Op0Ty = N0.getOperand(0).getValueType();
1500 if (Op0Ty == ExtSrcTy) {
1501 ZextOp = N0.getOperand(0);
1503 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
1504 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
1505 DAG.getConstant(Imm, dl, Op0Ty));
1507 if (!DCI.isCalledByLegalizer())
1508 DCI.AddToWorklist(ZextOp.getNode());
1509 // Otherwise, make this a use of a zext.
1510 return DAG.getSetCC(dl, VT, ZextOp,
1511 DAG.getConstant(C1 & APInt::getLowBitsSet(
1516 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
1517 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1518 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
1519 if (N0.getOpcode() == ISD::SETCC &&
1520 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1521 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
1523 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1524 // Invert the condition.
1525 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
1526 CC = ISD::getSetCCInverse(CC,
1527 N0.getOperand(0).getValueType().isInteger());
1528 if (DCI.isBeforeLegalizeOps() ||
1529 isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType()))
1530 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1533 if ((N0.getOpcode() == ISD::XOR ||
1534 (N0.getOpcode() == ISD::AND &&
1535 N0.getOperand(0).getOpcode() == ISD::XOR &&
1536 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
1537 isa<ConstantSDNode>(N0.getOperand(1)) &&
1538 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
1539 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
1540 // can only do this if the top bits are known zero.
1541 unsigned BitWidth = N0.getValueSizeInBits();
1542 if (DAG.MaskedValueIsZero(N0,
1543 APInt::getHighBitsSet(BitWidth,
1545 // Okay, get the un-inverted input value.
1547 if (N0.getOpcode() == ISD::XOR)
1548 Val = N0.getOperand(0);
1550 assert(N0.getOpcode() == ISD::AND &&
1551 N0.getOperand(0).getOpcode() == ISD::XOR);
1552 // ((X^1)&1)^1 -> X & 1
1553 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
1554 N0.getOperand(0).getOperand(0),
1558 return DAG.getSetCC(dl, VT, Val, N1,
1559 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1561 } else if (N1C->getAPIntValue() == 1 &&
1563 getBooleanContents(N0->getValueType(0)) ==
1564 ZeroOrOneBooleanContent)) {
1566 if (Op0.getOpcode() == ISD::TRUNCATE)
1567 Op0 = Op0.getOperand(0);
1569 if ((Op0.getOpcode() == ISD::XOR) &&
1570 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
1571 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
1572 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
1573 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
1574 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1577 if (Op0.getOpcode() == ISD::AND &&
1578 isa<ConstantSDNode>(Op0.getOperand(1)) &&
1579 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
1580 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
1581 if (Op0.getValueType().bitsGT(VT))
1582 Op0 = DAG.getNode(ISD::AND, dl, VT,
1583 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1584 DAG.getConstant(1, dl, VT));
1585 else if (Op0.getValueType().bitsLT(VT))
1586 Op0 = DAG.getNode(ISD::AND, dl, VT,
1587 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1588 DAG.getConstant(1, dl, VT));
1590 return DAG.getSetCC(dl, VT, Op0,
1591 DAG.getConstant(0, dl, Op0.getValueType()),
1592 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1594 if (Op0.getOpcode() == ISD::AssertZext &&
1595 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
1596 return DAG.getSetCC(dl, VT, Op0,
1597 DAG.getConstant(0, dl, Op0.getValueType()),
1598 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
1602 APInt MinVal, MaxVal;
1603 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
1604 if (ISD::isSignedIntSetCC(Cond)) {
1605 MinVal = APInt::getSignedMinValue(OperandBitSize);
1606 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
1608 MinVal = APInt::getMinValue(OperandBitSize);
1609 MaxVal = APInt::getMaxValue(OperandBitSize);
1612 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
1613 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
1614 if (C1 == MinVal) return DAG.getConstant(1, dl, VT); // X >= MIN --> true
1615 // X >= C0 --> X > (C0 - 1)
1617 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT;
1618 if ((DCI.isBeforeLegalizeOps() ||
1619 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1620 (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1621 isLegalICmpImmediate(C.getSExtValue())))) {
1622 return DAG.getSetCC(dl, VT, N0,
1623 DAG.getConstant(C, dl, N1.getValueType()),
1628 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
1629 if (C1 == MaxVal) return DAG.getConstant(1, dl, VT); // X <= MAX --> true
1630 // X <= C0 --> X < (C0 + 1)
1632 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT;
1633 if ((DCI.isBeforeLegalizeOps() ||
1634 isCondCodeLegal(NewCC, VT.getSimpleVT())) &&
1635 (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 &&
1636 isLegalICmpImmediate(C.getSExtValue())))) {
1637 return DAG.getSetCC(dl, VT, N0,
1638 DAG.getConstant(C, dl, N1.getValueType()),
1643 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
1644 return DAG.getConstant(0, dl, VT); // X < MIN --> false
1645 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
1646 return DAG.getConstant(1, dl, VT); // X >= MIN --> true
1647 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
1648 return DAG.getConstant(0, dl, VT); // X > MAX --> false
1649 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
1650 return DAG.getConstant(1, dl, VT); // X <= MAX --> true
1652 // Canonicalize setgt X, Min --> setne X, Min
1653 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
1654 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1655 // Canonicalize setlt X, Max --> setne X, Max
1656 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
1657 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1659 // If we have setult X, 1, turn it into seteq X, 0
1660 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
1661 return DAG.getSetCC(dl, VT, N0,
1662 DAG.getConstant(MinVal, dl, N0.getValueType()),
1664 // If we have setugt X, Max-1, turn it into seteq X, Max
1665 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
1666 return DAG.getSetCC(dl, VT, N0,
1667 DAG.getConstant(MaxVal, dl, N0.getValueType()),
1670 // If we have "setcc X, C0", check to see if we can shrink the immediate
1673 // SETUGT X, SINTMAX -> SETLT X, 0
1674 if (Cond == ISD::SETUGT &&
1675 C1 == APInt::getSignedMaxValue(OperandBitSize))
1676 return DAG.getSetCC(dl, VT, N0,
1677 DAG.getConstant(0, dl, N1.getValueType()),
1680 // SETULT X, SINTMIN -> SETGT X, -1
1681 if (Cond == ISD::SETULT &&
1682 C1 == APInt::getSignedMinValue(OperandBitSize)) {
1683 SDValue ConstMinusOne =
1684 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), dl,
1686 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1689 // Fold bit comparisons when we can.
1690 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1691 (VT == N0.getValueType() ||
1692 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1693 N0.getOpcode() == ISD::AND)
1694 if (ConstantSDNode *AndRHS =
1695 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1696 EVT ShiftTy = DCI.isBeforeLegalize() ?
1697 getPointerTy() : getShiftAmountTy(N0.getValueType());
1698 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
1699 // Perform the xform if the AND RHS is a single bit.
1700 if (AndRHS->getAPIntValue().isPowerOf2()) {
1701 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1702 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1703 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), dl,
1706 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
1707 // (X & 8) == 8 --> (X & 8) >> 3
1708 // Perform the xform if C1 is a single bit.
1709 if (C1.isPowerOf2()) {
1710 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1711 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
1712 DAG.getConstant(C1.logBase2(), dl,
1718 if (C1.getMinSignedBits() <= 64 &&
1719 !isLegalICmpImmediate(C1.getSExtValue())) {
1720 // (X & -256) == 256 -> (X >> 8) == 1
1721 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1722 N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
1723 if (ConstantSDNode *AndRHS =
1724 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1725 const APInt &AndRHSC = AndRHS->getAPIntValue();
1726 if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
1727 unsigned ShiftBits = AndRHSC.countTrailingZeros();
1728 EVT ShiftTy = DCI.isBeforeLegalize() ?
1729 getPointerTy() : getShiftAmountTy(N0.getValueType());
1730 EVT CmpTy = N0.getValueType();
1731 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0),
1732 DAG.getConstant(ShiftBits, dl,
1734 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, CmpTy);
1735 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
1738 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
1739 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
1740 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
1741 // X < 0x100000000 -> (X >> 32) < 1
1742 // X >= 0x100000000 -> (X >> 32) >= 1
1743 // X <= 0x0ffffffff -> (X >> 32) < 1
1744 // X > 0x0ffffffff -> (X >> 32) >= 1
1747 ISD::CondCode NewCond = Cond;
1749 ShiftBits = C1.countTrailingOnes();
1751 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1753 ShiftBits = C1.countTrailingZeros();
1755 NewC = NewC.lshr(ShiftBits);
1756 if (ShiftBits && NewC.getMinSignedBits() <= 64 &&
1757 isLegalICmpImmediate(NewC.getSExtValue())) {
1758 EVT ShiftTy = DCI.isBeforeLegalize() ?
1759 getPointerTy() : getShiftAmountTy(N0.getValueType());
1760 EVT CmpTy = N0.getValueType();
1761 SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
1762 DAG.getConstant(ShiftBits, dl, ShiftTy));
1763 SDValue CmpRHS = DAG.getConstant(NewC, dl, CmpTy);
1764 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
1770 if (isa<ConstantFPSDNode>(N0.getNode())) {
1771 // Constant fold or commute setcc.
1772 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1773 if (O.getNode()) return O;
1774 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
1775 // If the RHS of an FP comparison is a constant, simplify it away in
1777 if (CFP->getValueAPF().isNaN()) {
1778 // If an operand is known to be a nan, we can fold it.
1779 switch (ISD::getUnorderedFlavor(Cond)) {
1780 default: llvm_unreachable("Unknown flavor!");
1781 case 0: // Known false.
1782 return DAG.getConstant(0, dl, VT);
1783 case 1: // Known true.
1784 return DAG.getConstant(1, dl, VT);
1785 case 2: // Undefined.
1786 return DAG.getUNDEF(VT);
1790 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
1791 // constant if knowing that the operand is non-nan is enough. We prefer to
1792 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
1794 if (Cond == ISD::SETO || Cond == ISD::SETUO)
1795 return DAG.getSetCC(dl, VT, N0, N0, Cond);
1797 // If the condition is not legal, see if we can find an equivalent one
1799 if (!isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1800 // If the comparison was an awkward floating-point == or != and one of
1801 // the comparison operands is infinity or negative infinity, convert the
1802 // condition to a less-awkward <= or >=.
1803 if (CFP->getValueAPF().isInfinity()) {
1804 if (CFP->getValueAPF().isNegative()) {
1805 if (Cond == ISD::SETOEQ &&
1806 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1807 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1808 if (Cond == ISD::SETUEQ &&
1809 isCondCodeLegal(ISD::SETOLE, N0.getSimpleValueType()))
1810 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1811 if (Cond == ISD::SETUNE &&
1812 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1813 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1814 if (Cond == ISD::SETONE &&
1815 isCondCodeLegal(ISD::SETUGT, N0.getSimpleValueType()))
1816 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1818 if (Cond == ISD::SETOEQ &&
1819 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1820 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1821 if (Cond == ISD::SETUEQ &&
1822 isCondCodeLegal(ISD::SETOGE, N0.getSimpleValueType()))
1823 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1824 if (Cond == ISD::SETUNE &&
1825 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1826 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1827 if (Cond == ISD::SETONE &&
1828 isCondCodeLegal(ISD::SETULT, N0.getSimpleValueType()))
1829 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1836 // The sext(setcc()) => setcc() optimization relies on the appropriate
1837 // constant being emitted.
1839 switch (getBooleanContents(N0.getValueType())) {
1840 case UndefinedBooleanContent:
1841 case ZeroOrOneBooleanContent:
1842 EqVal = ISD::isTrueWhenEqual(Cond);
1844 case ZeroOrNegativeOneBooleanContent:
1845 EqVal = ISD::isTrueWhenEqual(Cond) ? -1 : 0;
1849 // We can always fold X == X for integer setcc's.
1850 if (N0.getValueType().isInteger()) {
1851 return DAG.getConstant(EqVal, dl, VT);
1853 unsigned UOF = ISD::getUnorderedFlavor(Cond);
1854 if (UOF == 2) // FP operators that are undefined on NaNs.
1855 return DAG.getConstant(EqVal, dl, VT);
1856 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
1857 return DAG.getConstant(EqVal, dl, VT);
1858 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
1859 // if it is not already.
1860 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
1861 if (NewCond != Cond && (DCI.isBeforeLegalizeOps() ||
1862 getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal))
1863 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1866 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1867 N0.getValueType().isInteger()) {
1868 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
1869 N0.getOpcode() == ISD::XOR) {
1870 // Simplify (X+Y) == (X+Z) --> Y == Z
1871 if (N0.getOpcode() == N1.getOpcode()) {
1872 if (N0.getOperand(0) == N1.getOperand(0))
1873 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1874 if (N0.getOperand(1) == N1.getOperand(1))
1875 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1876 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
1877 // If X op Y == Y op X, try other combinations.
1878 if (N0.getOperand(0) == N1.getOperand(1))
1879 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1881 if (N0.getOperand(1) == N1.getOperand(0))
1882 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1887 // If RHS is a legal immediate value for a compare instruction, we need
1888 // to be careful about increasing register pressure needlessly.
1889 bool LegalRHSImm = false;
1891 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
1892 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1893 // Turn (X+C1) == C2 --> X == C2-C1
1894 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
1895 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1896 DAG.getConstant(RHSC->getAPIntValue()-
1897 LHSR->getAPIntValue(),
1898 dl, N0.getValueType()), Cond);
1901 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
1902 if (N0.getOpcode() == ISD::XOR)
1903 // If we know that all of the inverted bits are zero, don't bother
1904 // performing the inversion.
1905 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
1907 DAG.getSetCC(dl, VT, N0.getOperand(0),
1908 DAG.getConstant(LHSR->getAPIntValue() ^
1909 RHSC->getAPIntValue(),
1910 dl, N0.getValueType()),
1914 // Turn (C1-X) == C2 --> X == C1-C2
1915 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
1916 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
1918 DAG.getSetCC(dl, VT, N0.getOperand(1),
1919 DAG.getConstant(SUBC->getAPIntValue() -
1920 RHSC->getAPIntValue(),
1921 dl, N0.getValueType()),
1926 // Could RHSC fold directly into a compare?
1927 if (RHSC->getValueType(0).getSizeInBits() <= 64)
1928 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
1931 // Simplify (X+Z) == X --> Z == 0
1932 // Don't do this if X is an immediate that can fold into a cmp
1933 // instruction and X+Z has other uses. It could be an induction variable
1934 // chain, and the transform would increase register pressure.
1935 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
1936 if (N0.getOperand(0) == N1)
1937 return DAG.getSetCC(dl, VT, N0.getOperand(1),
1938 DAG.getConstant(0, dl, N0.getValueType()), Cond);
1939 if (N0.getOperand(1) == N1) {
1940 if (DAG.isCommutativeBinOp(N0.getOpcode()))
1941 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1942 DAG.getConstant(0, dl, N0.getValueType()),
1944 if (N0.getNode()->hasOneUse()) {
1945 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
1946 // (Z-X) == X --> Z == X<<1
1947 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
1948 DAG.getConstant(1, dl,
1949 getShiftAmountTy(N1.getValueType())));
1950 if (!DCI.isCalledByLegalizer())
1951 DCI.AddToWorklist(SH.getNode());
1952 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1958 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
1959 N1.getOpcode() == ISD::XOR) {
1960 // Simplify X == (X+Z) --> Z == 0
1961 if (N1.getOperand(0) == N0)
1962 return DAG.getSetCC(dl, VT, N1.getOperand(1),
1963 DAG.getConstant(0, dl, N1.getValueType()), Cond);
1964 if (N1.getOperand(1) == N0) {
1965 if (DAG.isCommutativeBinOp(N1.getOpcode()))
1966 return DAG.getSetCC(dl, VT, N1.getOperand(0),
1967 DAG.getConstant(0, dl, N1.getValueType()), Cond);
1968 if (N1.getNode()->hasOneUse()) {
1969 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
1970 // X == (Z-X) --> X<<1 == Z
1971 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
1972 DAG.getConstant(1, dl,
1973 getShiftAmountTy(N0.getValueType())));
1974 if (!DCI.isCalledByLegalizer())
1975 DCI.AddToWorklist(SH.getNode());
1976 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
1981 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
1982 // Note that where y is variable and is known to have at most
1983 // one bit set (for example, if it is z&1) we cannot do this;
1984 // the expressions are not equivalent when y==0.
1985 if (N0.getOpcode() == ISD::AND)
1986 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
1987 if (ValueHasExactlyOneBitSet(N1, DAG)) {
1988 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
1989 if (DCI.isBeforeLegalizeOps() ||
1990 isCondCodeLegal(Cond, N0.getSimpleValueType())) {
1991 SDValue Zero = DAG.getConstant(0, dl, N1.getValueType());
1992 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
1996 if (N1.getOpcode() == ISD::AND)
1997 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
1998 if (ValueHasExactlyOneBitSet(N0, DAG)) {
1999 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2000 if (DCI.isBeforeLegalizeOps() ||
2001 isCondCodeLegal(Cond, N1.getSimpleValueType())) {
2002 SDValue Zero = DAG.getConstant(0, dl, N0.getValueType());
2003 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2009 // Fold away ALL boolean setcc's.
2011 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2013 default: llvm_unreachable("Unknown integer setcc!");
2014 case ISD::SETEQ: // X == Y -> ~(X^Y)
2015 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2016 N0 = DAG.getNOT(dl, Temp, MVT::i1);
2017 if (!DCI.isCalledByLegalizer())
2018 DCI.AddToWorklist(Temp.getNode());
2020 case ISD::SETNE: // X != Y --> (X^Y)
2021 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2023 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2024 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2025 Temp = DAG.getNOT(dl, N0, MVT::i1);
2026 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2027 if (!DCI.isCalledByLegalizer())
2028 DCI.AddToWorklist(Temp.getNode());
2030 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2031 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2032 Temp = DAG.getNOT(dl, N1, MVT::i1);
2033 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2034 if (!DCI.isCalledByLegalizer())
2035 DCI.AddToWorklist(Temp.getNode());
2037 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2038 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2039 Temp = DAG.getNOT(dl, N0, MVT::i1);
2040 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2041 if (!DCI.isCalledByLegalizer())
2042 DCI.AddToWorklist(Temp.getNode());
2044 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2045 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2046 Temp = DAG.getNOT(dl, N1, MVT::i1);
2047 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2050 if (VT != MVT::i1) {
2051 if (!DCI.isCalledByLegalizer())
2052 DCI.AddToWorklist(N0.getNode());
2053 // FIXME: If running after legalize, we probably can't do this.
2054 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2059 // Could not fold it.
2063 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2064 /// node is a GlobalAddress + offset.
2065 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
2066 int64_t &Offset) const {
2067 if (isa<GlobalAddressSDNode>(N)) {
2068 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2069 GA = GASD->getGlobal();
2070 Offset += GASD->getOffset();
2074 if (N->getOpcode() == ISD::ADD) {
2075 SDValue N1 = N->getOperand(0);
2076 SDValue N2 = N->getOperand(1);
2077 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2078 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2080 Offset += V->getSExtValue();
2083 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2084 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2086 Offset += V->getSExtValue();
2096 SDValue TargetLowering::
2097 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2098 // Default implementation: no optimization.
2102 //===----------------------------------------------------------------------===//
2103 // Inline Assembler Implementation Methods
2104 //===----------------------------------------------------------------------===//
2106 TargetLowering::ConstraintType
2107 TargetLowering::getConstraintType(StringRef Constraint) const {
2108 unsigned S = Constraint.size();
2111 switch (Constraint[0]) {
2113 case 'r': return C_RegisterClass;
2115 case 'o': // offsetable
2116 case 'V': // not offsetable
2118 case 'i': // Simple Integer or Relocatable Constant
2119 case 'n': // Simple Integer
2120 case 'E': // Floating Point Constant
2121 case 'F': // Floating Point Constant
2122 case 's': // Relocatable Constant
2123 case 'p': // Address.
2124 case 'X': // Allow ANY value.
2125 case 'I': // Target registers.
2139 if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') {
2140 if (S == 8 && Constraint.substr(1, 6) == "memory") // "{memory}"
2147 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2148 /// with another that has more specific requirements based on the type of the
2149 /// corresponding operand.
2150 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2151 if (ConstraintVT.isInteger())
2153 if (ConstraintVT.isFloatingPoint())
2154 return "f"; // works for many targets
2158 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2159 /// vector. If it is invalid, don't add anything to Ops.
2160 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2161 std::string &Constraint,
2162 std::vector<SDValue> &Ops,
2163 SelectionDAG &DAG) const {
2165 if (Constraint.length() > 1) return;
2167 char ConstraintLetter = Constraint[0];
2168 switch (ConstraintLetter) {
2170 case 'X': // Allows any operand; labels (basic block) use this.
2171 if (Op.getOpcode() == ISD::BasicBlock) {
2176 case 'i': // Simple Integer or Relocatable Constant
2177 case 'n': // Simple Integer
2178 case 's': { // Relocatable Constant
2179 // These operands are interested in values of the form (GV+C), where C may
2180 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2181 // is possible and fine if either GV or C are missing.
2182 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2183 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2185 // If we have "(add GV, C)", pull out GV/C
2186 if (Op.getOpcode() == ISD::ADD) {
2187 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2188 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2190 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2191 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2194 C = nullptr, GA = nullptr;
2197 // If we find a valid operand, map to the TargetXXX version so that the
2198 // value itself doesn't get selected.
2199 if (GA) { // Either &GV or &GV+C
2200 if (ConstraintLetter != 'n') {
2201 int64_t Offs = GA->getOffset();
2202 if (C) Offs += C->getZExtValue();
2203 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2204 C ? SDLoc(C) : SDLoc(),
2205 Op.getValueType(), Offs));
2209 if (C) { // just C, no GV.
2210 // Simple constants are not allowed for 's'.
2211 if (ConstraintLetter != 's') {
2212 // gcc prints these as sign extended. Sign extend value to 64 bits
2213 // now; without this it would get ZExt'd later in
2214 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2215 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2216 SDLoc(C), MVT::i64));
2225 std::pair<unsigned, const TargetRegisterClass *>
2226 TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI,
2227 StringRef Constraint,
2229 if (Constraint.empty() || Constraint[0] != '{')
2230 return std::make_pair(0u, static_cast<TargetRegisterClass*>(nullptr));
2231 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2233 // Remove the braces from around the name.
2234 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2236 std::pair<unsigned, const TargetRegisterClass*> R =
2237 std::make_pair(0u, static_cast<const TargetRegisterClass*>(nullptr));
2239 // Figure out which register class contains this reg.
2240 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2241 E = RI->regclass_end(); RCI != E; ++RCI) {
2242 const TargetRegisterClass *RC = *RCI;
2244 // If none of the value types for this register class are valid, we
2245 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2249 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2251 if (RegName.equals_lower(RI->getName(*I))) {
2252 std::pair<unsigned, const TargetRegisterClass*> S =
2253 std::make_pair(*I, RC);
2255 // If this register class has the requested value type, return it,
2256 // otherwise keep searching and return the first class found
2257 // if no other is found which explicitly has the requested type.
2258 if (RC->hasType(VT))
2269 //===----------------------------------------------------------------------===//
2270 // Constraint Selection.
2272 /// isMatchingInputConstraint - Return true of this is an input operand that is
2273 /// a matching constraint like "4".
2274 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2275 assert(!ConstraintCode.empty() && "No known constraint!");
2276 return isdigit(static_cast<unsigned char>(ConstraintCode[0]));
2279 /// getMatchedOperand - If this is an input matching constraint, this method
2280 /// returns the output operand it matches.
2281 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2282 assert(!ConstraintCode.empty() && "No known constraint!");
2283 return atoi(ConstraintCode.c_str());
2287 /// ParseConstraints - Split up the constraint string from the inline
2288 /// assembly value into the specific constraints and their prefixes,
2289 /// and also tie in the associated operand values.
2290 /// If this returns an empty vector, and if the constraint string itself
2291 /// isn't empty, there was an error parsing.
2292 TargetLowering::AsmOperandInfoVector
2293 TargetLowering::ParseConstraints(const TargetRegisterInfo *TRI,
2294 ImmutableCallSite CS) const {
2295 /// ConstraintOperands - Information about all of the constraints.
2296 AsmOperandInfoVector ConstraintOperands;
2297 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2298 unsigned maCount = 0; // Largest number of multiple alternative constraints.
2300 // Do a prepass over the constraints, canonicalizing them, and building up the
2301 // ConstraintOperands list.
2302 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2303 unsigned ResNo = 0; // ResNo - The result number of the next output.
2305 for (InlineAsm::ConstraintInfo &CI : IA->ParseConstraints()) {
2306 ConstraintOperands.emplace_back(std::move(CI));
2307 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2309 // Update multiple alternative constraint count.
2310 if (OpInfo.multipleAlternatives.size() > maCount)
2311 maCount = OpInfo.multipleAlternatives.size();
2313 OpInfo.ConstraintVT = MVT::Other;
2315 // Compute the value type for each operand.
2316 switch (OpInfo.Type) {
2317 case InlineAsm::isOutput:
2318 // Indirect outputs just consume an argument.
2319 if (OpInfo.isIndirect) {
2320 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2324 // The return value of the call is this value. As such, there is no
2325 // corresponding argument.
2326 assert(!CS.getType()->isVoidTy() &&
2328 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2329 OpInfo.ConstraintVT = getSimpleValueType(STy->getElementType(ResNo));
2331 assert(ResNo == 0 && "Asm only has one result!");
2332 OpInfo.ConstraintVT = getSimpleValueType(CS.getType());
2336 case InlineAsm::isInput:
2337 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2339 case InlineAsm::isClobber:
2344 if (OpInfo.CallOperandVal) {
2345 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2346 if (OpInfo.isIndirect) {
2347 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2349 report_fatal_error("Indirect operand for inline asm not a pointer!");
2350 OpTy = PtrTy->getElementType();
2353 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2354 if (StructType *STy = dyn_cast<StructType>(OpTy))
2355 if (STy->getNumElements() == 1)
2356 OpTy = STy->getElementType(0);
2358 // If OpTy is not a single value, it may be a struct/union that we
2359 // can tile with integers.
2360 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2361 unsigned BitSize = getDataLayout()->getTypeSizeInBits(OpTy);
2370 OpInfo.ConstraintVT =
2371 MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2374 } else if (PointerType *PT = dyn_cast<PointerType>(OpTy)) {
2376 = getDataLayout()->getPointerSizeInBits(PT->getAddressSpace());
2377 OpInfo.ConstraintVT = MVT::getIntegerVT(PtrSize);
2379 OpInfo.ConstraintVT = MVT::getVT(OpTy, true);
2384 // If we have multiple alternative constraints, select the best alternative.
2385 if (!ConstraintOperands.empty()) {
2387 unsigned bestMAIndex = 0;
2388 int bestWeight = -1;
2389 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2392 // Compute the sums of the weights for each alternative, keeping track
2393 // of the best (highest weight) one so far.
2394 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2396 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2397 cIndex != eIndex; ++cIndex) {
2398 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2399 if (OpInfo.Type == InlineAsm::isClobber)
2402 // If this is an output operand with a matching input operand,
2403 // look up the matching input. If their types mismatch, e.g. one
2404 // is an integer, the other is floating point, or their sizes are
2405 // different, flag it as an maCantMatch.
2406 if (OpInfo.hasMatchingInput()) {
2407 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2408 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2409 if ((OpInfo.ConstraintVT.isInteger() !=
2410 Input.ConstraintVT.isInteger()) ||
2411 (OpInfo.ConstraintVT.getSizeInBits() !=
2412 Input.ConstraintVT.getSizeInBits())) {
2413 weightSum = -1; // Can't match.
2418 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2423 weightSum += weight;
2426 if (weightSum > bestWeight) {
2427 bestWeight = weightSum;
2428 bestMAIndex = maIndex;
2432 // Now select chosen alternative in each constraint.
2433 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2434 cIndex != eIndex; ++cIndex) {
2435 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2436 if (cInfo.Type == InlineAsm::isClobber)
2438 cInfo.selectAlternative(bestMAIndex);
2443 // Check and hook up tied operands, choose constraint code to use.
2444 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2445 cIndex != eIndex; ++cIndex) {
2446 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2448 // If this is an output operand with a matching input operand, look up the
2449 // matching input. If their types mismatch, e.g. one is an integer, the
2450 // other is floating point, or their sizes are different, flag it as an
2452 if (OpInfo.hasMatchingInput()) {
2453 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2455 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2456 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
2457 getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
2458 OpInfo.ConstraintVT);
2459 std::pair<unsigned, const TargetRegisterClass *> InputRC =
2460 getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
2461 Input.ConstraintVT);
2462 if ((OpInfo.ConstraintVT.isInteger() !=
2463 Input.ConstraintVT.isInteger()) ||
2464 (MatchRC.second != InputRC.second)) {
2465 report_fatal_error("Unsupported asm: input constraint"
2466 " with a matching output constraint of"
2467 " incompatible type!");
2474 return ConstraintOperands;
2478 /// getConstraintGenerality - Return an integer indicating how general CT
2480 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
2482 case TargetLowering::C_Other:
2483 case TargetLowering::C_Unknown:
2485 case TargetLowering::C_Register:
2487 case TargetLowering::C_RegisterClass:
2489 case TargetLowering::C_Memory:
2492 llvm_unreachable("Invalid constraint type");
2495 /// Examine constraint type and operand type and determine a weight value.
2496 /// This object must already have been set up with the operand type
2497 /// and the current alternative constraint selected.
2498 TargetLowering::ConstraintWeight
2499 TargetLowering::getMultipleConstraintMatchWeight(
2500 AsmOperandInfo &info, int maIndex) const {
2501 InlineAsm::ConstraintCodeVector *rCodes;
2502 if (maIndex >= (int)info.multipleAlternatives.size())
2503 rCodes = &info.Codes;
2505 rCodes = &info.multipleAlternatives[maIndex].Codes;
2506 ConstraintWeight BestWeight = CW_Invalid;
2508 // Loop over the options, keeping track of the most general one.
2509 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
2510 ConstraintWeight weight =
2511 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
2512 if (weight > BestWeight)
2513 BestWeight = weight;
2519 /// Examine constraint type and operand type and determine a weight value.
2520 /// This object must already have been set up with the operand type
2521 /// and the current alternative constraint selected.
2522 TargetLowering::ConstraintWeight
2523 TargetLowering::getSingleConstraintMatchWeight(
2524 AsmOperandInfo &info, const char *constraint) const {
2525 ConstraintWeight weight = CW_Invalid;
2526 Value *CallOperandVal = info.CallOperandVal;
2527 // If we don't have a value, we can't do a match,
2528 // but allow it at the lowest weight.
2529 if (!CallOperandVal)
2531 // Look at the constraint type.
2532 switch (*constraint) {
2533 case 'i': // immediate integer.
2534 case 'n': // immediate integer with a known value.
2535 if (isa<ConstantInt>(CallOperandVal))
2536 weight = CW_Constant;
2538 case 's': // non-explicit intregal immediate.
2539 if (isa<GlobalValue>(CallOperandVal))
2540 weight = CW_Constant;
2542 case 'E': // immediate float if host format.
2543 case 'F': // immediate float.
2544 if (isa<ConstantFP>(CallOperandVal))
2545 weight = CW_Constant;
2547 case '<': // memory operand with autodecrement.
2548 case '>': // memory operand with autoincrement.
2549 case 'm': // memory operand.
2550 case 'o': // offsettable memory operand
2551 case 'V': // non-offsettable memory operand
2554 case 'r': // general register.
2555 case 'g': // general register, memory operand or immediate integer.
2556 // note: Clang converts "g" to "imr".
2557 if (CallOperandVal->getType()->isIntegerTy())
2558 weight = CW_Register;
2560 case 'X': // any operand.
2562 weight = CW_Default;
2568 /// ChooseConstraint - If there are multiple different constraints that we
2569 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
2570 /// This is somewhat tricky: constraints fall into four classes:
2571 /// Other -> immediates and magic values
2572 /// Register -> one specific register
2573 /// RegisterClass -> a group of regs
2574 /// Memory -> memory
2575 /// Ideally, we would pick the most specific constraint possible: if we have
2576 /// something that fits into a register, we would pick it. The problem here
2577 /// is that if we have something that could either be in a register or in
2578 /// memory that use of the register could cause selection of *other*
2579 /// operands to fail: they might only succeed if we pick memory. Because of
2580 /// this the heuristic we use is:
2582 /// 1) If there is an 'other' constraint, and if the operand is valid for
2583 /// that constraint, use it. This makes us take advantage of 'i'
2584 /// constraints when available.
2585 /// 2) Otherwise, pick the most general constraint present. This prefers
2586 /// 'm' over 'r', for example.
2588 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
2589 const TargetLowering &TLI,
2590 SDValue Op, SelectionDAG *DAG) {
2591 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
2592 unsigned BestIdx = 0;
2593 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
2594 int BestGenerality = -1;
2596 // Loop over the options, keeping track of the most general one.
2597 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
2598 TargetLowering::ConstraintType CType =
2599 TLI.getConstraintType(OpInfo.Codes[i]);
2601 // If this is an 'other' constraint, see if the operand is valid for it.
2602 // For example, on X86 we might have an 'rI' constraint. If the operand
2603 // is an integer in the range [0..31] we want to use I (saving a load
2604 // of a register), otherwise we must use 'r'.
2605 if (CType == TargetLowering::C_Other && Op.getNode()) {
2606 assert(OpInfo.Codes[i].size() == 1 &&
2607 "Unhandled multi-letter 'other' constraint");
2608 std::vector<SDValue> ResultOps;
2609 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
2611 if (!ResultOps.empty()) {
2618 // Things with matching constraints can only be registers, per gcc
2619 // documentation. This mainly affects "g" constraints.
2620 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
2623 // This constraint letter is more general than the previous one, use it.
2624 int Generality = getConstraintGenerality(CType);
2625 if (Generality > BestGenerality) {
2628 BestGenerality = Generality;
2632 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
2633 OpInfo.ConstraintType = BestType;
2636 /// ComputeConstraintToUse - Determines the constraint code and constraint
2637 /// type to use for the specific AsmOperandInfo, setting
2638 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
2639 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2641 SelectionDAG *DAG) const {
2642 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
2644 // Single-letter constraints ('r') are very common.
2645 if (OpInfo.Codes.size() == 1) {
2646 OpInfo.ConstraintCode = OpInfo.Codes[0];
2647 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2649 ChooseConstraint(OpInfo, *this, Op, DAG);
2652 // 'X' matches anything.
2653 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
2654 // Labels and constants are handled elsewhere ('X' is the only thing
2655 // that matches labels). For Functions, the type here is the type of
2656 // the result, which is not what we want to look at; leave them alone.
2657 Value *v = OpInfo.CallOperandVal;
2658 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
2659 OpInfo.CallOperandVal = v;
2663 // Otherwise, try to resolve it to something we know about by looking at
2664 // the actual operand type.
2665 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
2666 OpInfo.ConstraintCode = Repl;
2667 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
2672 /// \brief Given an exact SDIV by a constant, create a multiplication
2673 /// with the multiplicative inverse of the constant.
2674 static SDValue BuildExactSDIV(const TargetLowering &TLI, SDValue Op1, APInt d,
2675 SDLoc dl, SelectionDAG &DAG,
2676 std::vector<SDNode *> &Created) {
2677 assert(d != 0 && "Division by zero!");
2679 // Shift the value upfront if it is even, so the LSB is one.
2680 unsigned ShAmt = d.countTrailingZeros();
2682 // TODO: For UDIV use SRL instead of SRA.
2684 DAG.getConstant(ShAmt, dl, TLI.getShiftAmountTy(Op1.getValueType()));
2686 Flags.setExact(true);
2687 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, &Flags);
2688 Created.push_back(Op1.getNode());
2692 // Calculate the multiplicative inverse, using Newton's method.
2694 while ((t = d*xn) != 1)
2695 xn *= APInt(d.getBitWidth(), 2) - t;
2697 SDValue Op2 = DAG.getConstant(xn, dl, Op1.getValueType());
2698 SDValue Mul = DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
2699 Created.push_back(Mul.getNode());
2703 /// \brief Given an ISD::SDIV node expressing a divide by constant,
2704 /// return a DAG expression to select that will generate the same value by
2705 /// multiplying by a magic number.
2706 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
2707 SDValue TargetLowering::BuildSDIV(SDNode *N, const APInt &Divisor,
2708 SelectionDAG &DAG, bool IsAfterLegalization,
2709 std::vector<SDNode *> *Created) const {
2710 assert(Created && "No vector to hold sdiv ops.");
2712 EVT VT = N->getValueType(0);
2715 // Check to see if we can do this.
2716 // FIXME: We should be more aggressive here.
2717 if (!isTypeLegal(VT))
2720 // If the sdiv has an 'exact' bit we can use a simpler lowering.
2721 if (cast<BinaryWithFlagsSDNode>(N)->Flags.hasExact())
2722 return BuildExactSDIV(*this, N->getOperand(0), Divisor, dl, DAG, *Created);
2724 APInt::ms magics = Divisor.magic();
2726 // Multiply the numerator (operand 0) by the magic value
2727 // FIXME: We should support doing a MUL in a wider type
2729 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
2730 isOperationLegalOrCustom(ISD::MULHS, VT))
2731 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2732 DAG.getConstant(magics.m, dl, VT));
2733 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2734 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2735 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2737 DAG.getConstant(magics.m, dl, VT)).getNode(), 1);
2739 return SDValue(); // No mulhs or equvialent
2740 // If d > 0 and m < 0, add the numerator
2741 if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
2742 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2743 Created->push_back(Q.getNode());
2745 // If d < 0 and m > 0, subtract the numerator.
2746 if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
2747 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2748 Created->push_back(Q.getNode());
2750 // Shift right algebraic if shift value is nonzero
2752 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2753 DAG.getConstant(magics.s, dl,
2754 getShiftAmountTy(Q.getValueType())));
2755 Created->push_back(Q.getNode());
2757 // Extract the sign bit and add it to the quotient
2758 SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q,
2759 DAG.getConstant(VT.getScalarSizeInBits() - 1, dl,
2760 getShiftAmountTy(Q.getValueType())));
2761 Created->push_back(T.getNode());
2762 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2765 /// \brief Given an ISD::UDIV node expressing a divide by constant,
2766 /// return a DAG expression to select that will generate the same value by
2767 /// multiplying by a magic number.
2768 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
2769 SDValue TargetLowering::BuildUDIV(SDNode *N, const APInt &Divisor,
2770 SelectionDAG &DAG, bool IsAfterLegalization,
2771 std::vector<SDNode *> *Created) const {
2772 assert(Created && "No vector to hold udiv ops.");
2774 EVT VT = N->getValueType(0);
2777 // Check to see if we can do this.
2778 // FIXME: We should be more aggressive here.
2779 if (!isTypeLegal(VT))
2782 // FIXME: We should use a narrower constant when the upper
2783 // bits are known to be zero.
2784 APInt::mu magics = Divisor.magicu();
2786 SDValue Q = N->getOperand(0);
2788 // If the divisor is even, we can avoid using the expensive fixup by shifting
2789 // the divided value upfront.
2790 if (magics.a != 0 && !Divisor[0]) {
2791 unsigned Shift = Divisor.countTrailingZeros();
2792 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
2793 DAG.getConstant(Shift, dl,
2794 getShiftAmountTy(Q.getValueType())));
2795 Created->push_back(Q.getNode());
2797 // Get magic number for the shifted divisor.
2798 magics = Divisor.lshr(Shift).magicu(Shift);
2799 assert(magics.a == 0 && "Should use cheap fixup now");
2802 // Multiply the numerator (operand 0) by the magic value
2803 // FIXME: We should support doing a MUL in a wider type
2804 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
2805 isOperationLegalOrCustom(ISD::MULHU, VT))
2806 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, dl, VT));
2807 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
2808 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2809 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
2810 DAG.getConstant(magics.m, dl, VT)).getNode(), 1);
2812 return SDValue(); // No mulhu or equvialent
2814 Created->push_back(Q.getNode());
2816 if (magics.a == 0) {
2817 assert(magics.s < Divisor.getBitWidth() &&
2818 "We shouldn't generate an undefined shift!");
2819 return DAG.getNode(ISD::SRL, dl, VT, Q,
2820 DAG.getConstant(magics.s, dl,
2821 getShiftAmountTy(Q.getValueType())));
2823 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2824 Created->push_back(NPQ.getNode());
2825 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2826 DAG.getConstant(1, dl,
2827 getShiftAmountTy(NPQ.getValueType())));
2828 Created->push_back(NPQ.getNode());
2829 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2830 Created->push_back(NPQ.getNode());
2831 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
2832 DAG.getConstant(magics.s - 1, dl,
2833 getShiftAmountTy(NPQ.getValueType())));
2837 bool TargetLowering::
2838 verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const {
2839 if (!isa<ConstantSDNode>(Op.getOperand(0))) {
2840 DAG.getContext()->emitError("argument to '__builtin_return_address' must "
2841 "be a constant integer");
2848 //===----------------------------------------------------------------------===//
2849 // Legalization Utilities
2850 //===----------------------------------------------------------------------===//
2852 bool TargetLowering::expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2853 SelectionDAG &DAG, SDValue LL, SDValue LH,
2854 SDValue RL, SDValue RH) const {
2855 EVT VT = N->getValueType(0);
2858 bool HasMULHS = isOperationLegalOrCustom(ISD::MULHS, HiLoVT);
2859 bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT);
2860 bool HasSMUL_LOHI = isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);
2861 bool HasUMUL_LOHI = isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);
2862 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
2863 unsigned OuterBitSize = VT.getSizeInBits();
2864 unsigned InnerBitSize = HiLoVT.getSizeInBits();
2865 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
2866 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
2868 // LL, LH, RL, and RH must be either all NULL or all set to a value.
2869 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
2870 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode()));
2872 if (!LL.getNode() && !RL.getNode() &&
2873 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2874 LL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(0));
2875 RL = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, N->getOperand(1));
2881 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
2882 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
2883 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
2884 // The inputs are both zero-extended.
2886 // We can emit a umul_lohi.
2887 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL,
2889 Hi = SDValue(Lo.getNode(), 1);
2893 // We can emit a mulhu+mul.
2894 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2895 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2899 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
2900 // The input values are both sign-extended.
2902 // We can emit a smul_lohi.
2903 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(HiLoVT, HiLoVT), LL,
2905 Hi = SDValue(Lo.getNode(), 1);
2909 // We can emit a mulhs+mul.
2910 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2911 Hi = DAG.getNode(ISD::MULHS, dl, HiLoVT, LL, RL);
2916 if (!LH.getNode() && !RH.getNode() &&
2917 isOperationLegalOrCustom(ISD::SRL, VT) &&
2918 isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {
2919 unsigned ShiftAmt = VT.getSizeInBits() - HiLoVT.getSizeInBits();
2920 SDValue Shift = DAG.getConstant(ShiftAmt, dl, getShiftAmountTy(VT));
2921 LH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(0), Shift);
2922 LH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, LH);
2923 RH = DAG.getNode(ISD::SRL, dl, VT, N->getOperand(1), Shift);
2924 RH = DAG.getNode(ISD::TRUNCATE, dl, HiLoVT, RH);
2931 // Lo,Hi = umul LHS, RHS.
2932 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
2933 DAG.getVTList(HiLoVT, HiLoVT), LL, RL);
2935 Hi = UMulLOHI.getValue(1);
2936 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2937 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2938 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2939 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2943 Lo = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RL);
2944 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL);
2945 RH = DAG.getNode(ISD::MUL, dl, HiLoVT, LL, RH);
2946 LH = DAG.getNode(ISD::MUL, dl, HiLoVT, LH, RL);
2947 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, RH);
2948 Hi = DAG.getNode(ISD::ADD, dl, HiLoVT, Hi, LH);
2955 bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result,
2956 SelectionDAG &DAG) const {
2957 EVT VT = Node->getOperand(0).getValueType();
2958 EVT NVT = Node->getValueType(0);
2959 SDLoc dl(SDValue(Node, 0));
2961 // FIXME: Only f32 to i64 conversions are supported.
2962 if (VT != MVT::f32 || NVT != MVT::i64)
2965 // Expand f32 -> i64 conversion
2966 // This algorithm comes from compiler-rt's implementation of fixsfdi:
2967 // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c
2968 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(),
2969 VT.getSizeInBits());
2970 SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT);
2971 SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT);
2972 SDValue Bias = DAG.getConstant(127, dl, IntVT);
2973 SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()), dl,
2975 SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, dl, IntVT);
2976 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT);
2978 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0));
2980 SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT,
2981 DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask),
2982 DAG.getZExtOrTrunc(ExponentLoBit, dl, getShiftAmountTy(IntVT)));
2983 SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
2985 SDValue Sign = DAG.getNode(ISD::SRA, dl, IntVT,
2986 DAG.getNode(ISD::AND, dl, IntVT, Bits, SignMask),
2987 DAG.getZExtOrTrunc(SignLowBit, dl, getShiftAmountTy(IntVT)));
2988 Sign = DAG.getSExtOrTrunc(Sign, dl, NVT);
2990 SDValue R = DAG.getNode(ISD::OR, dl, IntVT,
2991 DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask),
2992 DAG.getConstant(0x00800000, dl, IntVT));
2994 R = DAG.getZExtOrTrunc(R, dl, NVT);
2997 R = DAG.getSelectCC(dl, Exponent, ExponentLoBit,
2998 DAG.getNode(ISD::SHL, dl, NVT, R,
3000 DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
3001 dl, getShiftAmountTy(IntVT))),
3002 DAG.getNode(ISD::SRL, dl, NVT, R,
3004 DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
3005 dl, getShiftAmountTy(IntVT))),
3008 SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT,
3009 DAG.getNode(ISD::XOR, dl, NVT, R, Sign),
3012 Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, dl, IntVT),
3013 DAG.getConstant(0, dl, NVT), Ret, ISD::SETLT);