1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/Target/TargetMachine.h"
16 #include "llvm/Target/MRegisterInfo.h"
17 #include "llvm/CodeGen/SelectionDAG.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/Support/MathExtras.h"
22 TargetLowering::TargetLowering(TargetMachine &tm)
23 : TM(tm), TD(TM.getTargetData()) {
24 assert(ISD::BUILTIN_OP_END <= 128 &&
25 "Fixed size array in TargetLowering is not large enough!");
26 // All operations default to being supported.
27 memset(OpActions, 0, sizeof(OpActions));
29 IsLittleEndian = TD.isLittleEndian();
30 ShiftAmountTy = SetCCResultTy = PointerTy = getValueType(TD.getIntPtrType());
31 ShiftAmtHandling = Undefined;
32 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
33 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
34 allowUnalignedMemoryAccesses = false;
35 UseUnderscoreSetJmpLongJmp = false;
36 IntDivIsCheap = false;
37 Pow2DivIsCheap = false;
38 StackPointerRegisterToSaveRestore = 0;
39 SchedPreferenceInfo = SchedulingForLatency;
42 TargetLowering::~TargetLowering() {}
44 /// setValueTypeAction - Set the action for a particular value type. This
45 /// assumes an action has not already been set for this value type.
46 static void SetValueTypeAction(MVT::ValueType VT,
47 TargetLowering::LegalizeAction Action,
49 MVT::ValueType *TransformToType,
50 TargetLowering::ValueTypeActionImpl &ValueTypeActions) {
51 ValueTypeActions.setTypeAction(VT, Action);
52 if (Action == TargetLowering::Promote) {
53 MVT::ValueType PromoteTo;
57 unsigned LargerReg = VT+1;
58 while (!TLI.isTypeLegal((MVT::ValueType)LargerReg)) {
60 assert(MVT::isInteger((MVT::ValueType)LargerReg) &&
61 "Nothing to promote to??");
63 PromoteTo = (MVT::ValueType)LargerReg;
66 assert(MVT::isInteger(VT) == MVT::isInteger(PromoteTo) &&
67 MVT::isFloatingPoint(VT) == MVT::isFloatingPoint(PromoteTo) &&
68 "Can only promote from int->int or fp->fp!");
69 assert(VT < PromoteTo && "Must promote to a larger type!");
70 TransformToType[VT] = PromoteTo;
71 } else if (Action == TargetLowering::Expand) {
72 assert((VT == MVT::Vector || MVT::isInteger(VT)) && VT > MVT::i8 &&
73 "Cannot expand this type: target must support SOME integer reg!");
74 // Expand to the next smaller integer type!
75 TransformToType[VT] = (MVT::ValueType)(VT-1);
80 /// computeRegisterProperties - Once all of the register classes are added,
81 /// this allows us to compute derived properties we expose.
82 void TargetLowering::computeRegisterProperties() {
83 assert(MVT::LAST_VALUETYPE <= 32 &&
84 "Too many value types for ValueTypeActions to hold!");
86 // Everything defaults to one.
87 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i)
88 NumElementsForVT[i] = 1;
90 // Find the largest integer register class.
91 unsigned LargestIntReg = MVT::i128;
92 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
93 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
95 // Every integer value type larger than this largest register takes twice as
96 // many registers to represent as the previous ValueType.
97 unsigned ExpandedReg = LargestIntReg; ++LargestIntReg;
98 for (++ExpandedReg; MVT::isInteger((MVT::ValueType)ExpandedReg);++ExpandedReg)
99 NumElementsForVT[ExpandedReg] = 2*NumElementsForVT[ExpandedReg-1];
101 // Inspect all of the ValueType's possible, deciding how to process them.
102 for (unsigned IntReg = MVT::i1; IntReg <= MVT::i128; ++IntReg)
103 // If we are expanding this type, expand it!
104 if (getNumElements((MVT::ValueType)IntReg) != 1)
105 SetValueTypeAction((MVT::ValueType)IntReg, Expand, *this, TransformToType,
107 else if (!isTypeLegal((MVT::ValueType)IntReg))
108 // Otherwise, if we don't have native support, we must promote to a
110 SetValueTypeAction((MVT::ValueType)IntReg, Promote, *this,
111 TransformToType, ValueTypeActions);
113 TransformToType[(MVT::ValueType)IntReg] = (MVT::ValueType)IntReg;
115 // If the target does not have native support for F32, promote it to F64.
116 if (!isTypeLegal(MVT::f32))
117 SetValueTypeAction(MVT::f32, Promote, *this,
118 TransformToType, ValueTypeActions);
120 TransformToType[MVT::f32] = MVT::f32;
122 // Set MVT::Vector to always be Expanded
123 SetValueTypeAction(MVT::Vector, Expand, *this, TransformToType,
126 assert(isTypeLegal(MVT::f64) && "Target does not support FP?");
127 TransformToType[MVT::f64] = MVT::f64;
130 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
134 //===----------------------------------------------------------------------===//
135 // Optimization Methods
136 //===----------------------------------------------------------------------===//
138 /// ShrinkDemandedConstant - Check to see if the specified operand of the
139 /// specified instruction is a constant integer. If so, check to see if there
140 /// are any bits set in the constant that are not demanded. If so, shrink the
141 /// constant and return true.
142 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDOperand Op,
144 // FIXME: ISD::SELECT
145 switch(Op.getOpcode()) {
150 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
151 if ((~Demanded & C->getValue()) != 0) {
152 MVT::ValueType VT = Op.getValueType();
153 SDOperand New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
154 DAG.getConstant(Demanded & C->getValue(),
156 return CombineTo(Op, New);
163 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
164 /// DemandedMask bits of the result of Op are ever used downstream. If we can
165 /// use this information to simplify Op, create a new simplified DAG node and
166 /// return true, returning the original and new nodes in Old and New. Otherwise,
167 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
168 /// the expression (used to simplify the caller). The KnownZero/One bits may
169 /// only be accurate for those bits in the DemandedMask.
170 bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
173 TargetLoweringOpt &TLO,
174 unsigned Depth) const {
175 KnownZero = KnownOne = 0; // Don't know anything.
176 // Other users may use these bits.
177 if (!Op.Val->hasOneUse()) {
179 // If not at the root, Just compute the KnownZero/KnownOne bits to
180 // simplify things downstream.
181 ComputeMaskedBits(Op, DemandedMask, KnownZero, KnownOne, Depth);
184 // If this is the root being simplified, allow it to have multiple uses,
185 // just set the DemandedMask to all bits.
186 DemandedMask = MVT::getIntVTBitMask(Op.getValueType());
187 } else if (DemandedMask == 0) {
188 // Not demanding any bits from Op.
189 if (Op.getOpcode() != ISD::UNDEF)
190 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::UNDEF, Op.getValueType()));
192 } else if (Depth == 6) { // Limit search depth.
196 uint64_t KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
197 switch (Op.getOpcode()) {
199 // We know all of the bits for a constant!
200 KnownOne = cast<ConstantSDNode>(Op)->getValue() & DemandedMask;
201 KnownZero = ~KnownOne & DemandedMask;
204 // If either the LHS or the RHS are Zero, the result is zero.
205 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
206 KnownOne, TLO, Depth+1))
208 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
209 // If something is known zero on the RHS, the bits aren't demanded on the
211 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownZero,
212 KnownZero2, KnownOne2, TLO, Depth+1))
214 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
216 // If all of the demanded bits are known one on one side, return the other.
217 // These bits cannot contribute to the result of the 'and'.
218 if ((DemandedMask & ~KnownZero2 & KnownOne)==(DemandedMask & ~KnownZero2))
219 return TLO.CombineTo(Op, Op.getOperand(0));
220 if ((DemandedMask & ~KnownZero & KnownOne2)==(DemandedMask & ~KnownZero))
221 return TLO.CombineTo(Op, Op.getOperand(1));
222 // If all of the demanded bits in the inputs are known zeros, return zero.
223 if ((DemandedMask & (KnownZero|KnownZero2)) == DemandedMask)
224 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
225 // If the RHS is a constant, see if we can simplify it.
226 if (TLO.ShrinkDemandedConstant(Op, DemandedMask & ~KnownZero2))
229 // Output known-1 bits are only known if set in both the LHS & RHS.
230 KnownOne &= KnownOne2;
231 // Output known-0 are known to be clear if zero in either the LHS | RHS.
232 KnownZero |= KnownZero2;
235 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
236 KnownOne, TLO, Depth+1))
238 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
239 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask & ~KnownOne,
240 KnownZero2, KnownOne2, TLO, Depth+1))
242 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
244 // If all of the demanded bits are known zero on one side, return the other.
245 // These bits cannot contribute to the result of the 'or'.
246 if ((DemandedMask & ~KnownOne2 & KnownZero) == DemandedMask & ~KnownOne2)
247 return TLO.CombineTo(Op, Op.getOperand(0));
248 if ((DemandedMask & ~KnownOne & KnownZero2) == DemandedMask & ~KnownOne)
249 return TLO.CombineTo(Op, Op.getOperand(1));
250 // If all of the potentially set bits on one side are known to be set on
251 // the other side, just use the 'other' side.
252 if ((DemandedMask & (~KnownZero) & KnownOne2) ==
253 (DemandedMask & (~KnownZero)))
254 return TLO.CombineTo(Op, Op.getOperand(0));
255 if ((DemandedMask & (~KnownZero2) & KnownOne) ==
256 (DemandedMask & (~KnownZero2)))
257 return TLO.CombineTo(Op, Op.getOperand(1));
258 // If the RHS is a constant, see if we can simplify it.
259 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
262 // Output known-0 bits are only known if clear in both the LHS & RHS.
263 KnownZero &= KnownZero2;
264 // Output known-1 are known to be set if set in either the LHS | RHS.
265 KnownOne |= KnownOne2;
268 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero,
269 KnownOne, TLO, Depth+1))
271 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
272 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero2,
273 KnownOne2, TLO, Depth+1))
275 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
277 // If all of the demanded bits are known zero on one side, return the other.
278 // These bits cannot contribute to the result of the 'xor'.
279 if ((DemandedMask & KnownZero) == DemandedMask)
280 return TLO.CombineTo(Op, Op.getOperand(0));
281 if ((DemandedMask & KnownZero2) == DemandedMask)
282 return TLO.CombineTo(Op, Op.getOperand(1));
284 // Output known-0 bits are known if clear or set in both the LHS & RHS.
285 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
286 // Output known-1 are known to be set if set in only one of the LHS, RHS.
287 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
289 // If all of the unknown bits are known to be zero on one side or the other
290 // (but not both) turn this into an *inclusive* or.
291 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
292 if (uint64_t UnknownBits = DemandedMask & ~(KnownZeroOut|KnownOneOut))
293 if ((UnknownBits & (KnownZero|KnownZero2)) == UnknownBits)
294 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(),
297 // If all of the demanded bits on one side are known, and all of the set
298 // bits on that side are also known to be set on the other side, turn this
299 // into an AND, as we know the bits will be cleared.
300 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
301 if ((DemandedMask & (KnownZero|KnownOne)) == DemandedMask) { // all known
302 if ((KnownOne & KnownOne2) == KnownOne) {
303 MVT::ValueType VT = Op.getValueType();
304 SDOperand ANDC = TLO.DAG.getConstant(~KnownOne & DemandedMask, VT);
305 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, VT, Op.getOperand(0),
310 // If the RHS is a constant, see if we can simplify it.
311 // FIXME: for XOR, we prefer to force bits to 1 if they will make a -1.
312 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
315 KnownZero = KnownZeroOut;
316 KnownOne = KnownOneOut;
319 // If we know the result of a setcc has the top bits zero, use this info.
320 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult)
321 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
324 if (SimplifyDemandedBits(Op.getOperand(2), DemandedMask, KnownZero,
325 KnownOne, TLO, Depth+1))
327 if (SimplifyDemandedBits(Op.getOperand(1), DemandedMask, KnownZero2,
328 KnownOne2, TLO, Depth+1))
330 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
331 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
333 // If the operands are constants, see if we can simplify them.
334 if (TLO.ShrinkDemandedConstant(Op, DemandedMask))
337 // Only known if known in both the LHS and RHS.
338 KnownOne &= KnownOne2;
339 KnownZero &= KnownZero2;
342 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
343 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask >> SA->getValue(),
344 KnownZero, KnownOne, TLO, Depth+1))
346 KnownZero <<= SA->getValue();
347 KnownOne <<= SA->getValue();
348 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
352 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
353 MVT::ValueType VT = Op.getValueType();
354 unsigned ShAmt = SA->getValue();
356 // Compute the new bits that are at the top now.
357 uint64_t HighBits = (1ULL << ShAmt)-1;
358 HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
359 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
361 if (SimplifyDemandedBits(Op.getOperand(0),
362 (DemandedMask << ShAmt) & TypeMask,
363 KnownZero, KnownOne, TLO, Depth+1))
365 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
366 KnownZero &= TypeMask;
367 KnownOne &= TypeMask;
370 KnownZero |= HighBits; // high bits known zero.
374 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
375 MVT::ValueType VT = Op.getValueType();
376 unsigned ShAmt = SA->getValue();
378 // Compute the new bits that are at the top now.
379 uint64_t HighBits = (1ULL << ShAmt)-1;
380 HighBits <<= MVT::getSizeInBits(VT) - ShAmt;
381 uint64_t TypeMask = MVT::getIntVTBitMask(VT);
383 if (SimplifyDemandedBits(Op.getOperand(0),
384 (DemandedMask << ShAmt) & TypeMask,
385 KnownZero, KnownOne, TLO, Depth+1))
387 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
388 KnownZero &= TypeMask;
389 KnownOne &= TypeMask;
390 KnownZero >>= SA->getValue();
391 KnownOne >>= SA->getValue();
393 // Handle the sign bits.
394 uint64_t SignBit = MVT::getIntVTSignBit(VT);
395 SignBit >>= SA->getValue(); // Adjust to where it is now in the mask.
397 // If the input sign bit is known to be zero, or if none of the top bits
398 // are demanded, turn this into an unsigned shift right.
399 if ((KnownZero & SignBit) || (HighBits & ~DemandedMask) == HighBits) {
400 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, VT, Op.getOperand(0),
402 } else if (KnownOne & SignBit) { // New bits are known one.
403 KnownOne |= HighBits;
407 case ISD::SIGN_EXTEND_INREG: {
408 MVT::ValueType VT = Op.getValueType();
409 MVT::ValueType EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
411 // Sign or Zero extension. Compute the bits in the result that are not
412 // present in the input.
413 uint64_t NotIn = ~MVT::getIntVTBitMask(EVT);
414 uint64_t NewBits = MVT::getIntVTBitMask(VT) & NotIn;
417 uint64_t InSignBit = MVT::getIntVTSignBit(EVT);
418 int64_t InputDemandedBits = DemandedMask & MVT::getIntVTBitMask(EVT);
420 // If any of the sign extended bits are demanded, we know that the sign
422 if (NewBits & DemandedMask)
423 InputDemandedBits |= InSignBit;
425 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
426 KnownZero, KnownOne, TLO, Depth+1))
428 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
430 // If the sign bit of the input is known set or clear, then we know the
431 // top bits of the result.
433 // If the input sign bit is known zero, or if the NewBits are not demanded
434 // convert this into a zero extension.
435 if ((KnownZero & InSignBit) || (NewBits & ~DemandedMask) == NewBits) {
436 return TLO.CombineTo(Op, Op.getOperand(0));
437 } else if (KnownOne & InSignBit) { // Input sign bit known set
439 KnownZero &= ~NewBits;
440 } else { // Input sign bit unknown
441 KnownZero &= ~NewBits;
442 KnownOne &= ~NewBits;
447 if (ConstantSDNode *AA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
448 if (SimplifyDemandedBits(Op.getOperand(0), DemandedMask, KnownZero,
449 KnownOne, TLO, Depth+1))
451 // Compute the KnownOne/KnownZero masks for the constant, so we can set
452 // KnownZero appropriately if we're adding a constant that has all low
454 ComputeMaskedBits(Op.getOperand(1),
455 MVT::getIntVTBitMask(Op.getValueType()),
456 KnownZero2, KnownOne2, Depth+1);
458 uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero),
459 CountTrailingZeros_64(~KnownZero2));
460 KnownZero = (1ULL << KnownZeroOut) - 1;
467 MVT::ValueType VT = Op.getValueType();
468 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1;
469 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT);
477 /// MaskedValueIsZero - Return true if 'V & Mask' is known to be zero. We use
478 /// this predicate to simplify operations downstream. Mask is known to be zero
479 /// for bits that V cannot have.
480 bool TargetLowering::MaskedValueIsZero(SDOperand Op, uint64_t Mask,
481 unsigned Depth) const {
482 uint64_t KnownZero, KnownOne;
483 ComputeMaskedBits(Op, Mask, KnownZero, KnownOne, Depth);
484 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
485 return (KnownZero & Mask) == Mask;
488 /// ComputeMaskedBits - Determine which of the bits specified in Mask are
489 /// known to be either zero or one and return them in the KnownZero/KnownOne
490 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit
492 void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
493 uint64_t &KnownZero, uint64_t &KnownOne,
494 unsigned Depth) const {
495 KnownZero = KnownOne = 0; // Don't know anything.
496 if (Depth == 6 || Mask == 0)
497 return; // Limit search depth.
499 uint64_t KnownZero2, KnownOne2;
501 switch (Op.getOpcode()) {
503 // We know all of the bits for a constant!
504 KnownOne = cast<ConstantSDNode>(Op)->getValue() & Mask;
505 KnownZero = ~KnownOne & Mask;
508 // If either the LHS or the RHS are Zero, the result is zero.
509 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
511 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
512 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
513 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
515 // Output known-1 bits are only known if set in both the LHS & RHS.
516 KnownOne &= KnownOne2;
517 // Output known-0 are known to be clear if zero in either the LHS | RHS.
518 KnownZero |= KnownZero2;
521 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
523 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
524 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
525 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
527 // Output known-0 bits are only known if clear in both the LHS & RHS.
528 KnownZero &= KnownZero2;
529 // Output known-1 are known to be set if set in either the LHS | RHS.
530 KnownOne |= KnownOne2;
533 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
534 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
535 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
536 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
538 // Output known-0 bits are known if clear or set in both the LHS & RHS.
539 uint64_t KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
540 // Output known-1 are known to be set if set in only one of the LHS, RHS.
541 KnownOne = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
542 KnownZero = KnownZeroOut;
546 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero, KnownOne, Depth+1);
547 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero2, KnownOne2, Depth+1);
548 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
549 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
551 // Only known if known in both the LHS and RHS.
552 KnownOne &= KnownOne2;
553 KnownZero &= KnownZero2;
556 ComputeMaskedBits(Op.getOperand(3), Mask, KnownZero, KnownOne, Depth+1);
557 ComputeMaskedBits(Op.getOperand(2), Mask, KnownZero2, KnownOne2, Depth+1);
558 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
559 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
561 // Only known if known in both the LHS and RHS.
562 KnownOne &= KnownOne2;
563 KnownZero &= KnownZero2;
566 // If we know the result of a setcc has the top bits zero, use this info.
567 if (getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult)
568 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
571 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0
572 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
573 Mask >>= SA->getValue();
574 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
575 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
576 KnownZero <<= SA->getValue();
577 KnownOne <<= SA->getValue();
578 KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
582 // (ushr X, C1) & C2 == 0 iff (-1 >> C1) & C2 == 0
583 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
584 uint64_t HighBits = (1ULL << SA->getValue())-1;
585 HighBits <<= MVT::getSizeInBits(Op.getValueType())-SA->getValue();
586 Mask <<= SA->getValue();
587 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
588 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
589 KnownZero >>= SA->getValue();
590 KnownOne >>= SA->getValue();
591 KnownZero |= HighBits; // high bits known zero.
595 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
596 uint64_t HighBits = (1ULL << SA->getValue())-1;
597 HighBits <<= MVT::getSizeInBits(Op.getValueType())-SA->getValue();
598 Mask <<= SA->getValue();
599 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
600 assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
601 KnownZero >>= SA->getValue();
602 KnownOne >>= SA->getValue();
604 // Handle the sign bits.
605 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(Op.getValueType())-1);
606 SignBit >>= SA->getValue(); // Adjust to where it is now in the mask.
608 if (KnownZero & SignBit) { // New bits are known zero.
609 KnownZero |= HighBits;
610 } else if (KnownOne & SignBit) { // New bits are known one.
611 KnownOne |= HighBits;
618 MVT::ValueType VT = Op.getValueType();
619 unsigned LowBits = Log2_32(MVT::getSizeInBits(VT))+1;
620 KnownZero = ~((1ULL << LowBits)-1) & MVT::getIntVTBitMask(VT);
624 case ISD::ZEXTLOAD: {
626 MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
627 KnownZero |= ~((1ULL << SrcBits)-1);
630 case ISD::ZERO_EXTEND: {
632 MVT::getSizeInBits(Op.getOperand(0).getValueType());
633 KnownZero |= ~((1ULL << SrcBits)-1);
636 case ISD::ANY_EXTEND: {
638 MVT::getSizeInBits(Op.getOperand(0).getValueType());
639 KnownZero &= ((1ULL << SrcBits)-1);
640 KnownOne &= ((1ULL << SrcBits)-1);
643 case ISD::AssertZext: {
645 MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
646 KnownZero |= ~((1ULL << SrcBits)-1);
650 // If either the LHS or the RHS are Zero, the result is zero.
651 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
652 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
653 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
654 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
656 // Output known-0 bits are known if clear or set in both the low clear bits
657 // common to both LHS & RHS;
658 uint64_t KnownZeroOut = std::min(CountTrailingZeros_64(~KnownZero),
659 CountTrailingZeros_64(~KnownZero2));
661 KnownZero = (1ULL << KnownZeroOut) - 1;
666 // We know that the top bits of C-X are clear if X contains less bits
667 // than C (i.e. no wrap-around can happen). For example, 20-X is
668 // positive if we can prove that X is >= 0 and < 16.
671 // Allow the target to implement this method for its nodes.
672 if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
673 computeMaskedBitsForTargetNode(Op, Mask, KnownZero, KnownOne);
678 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
679 /// in Mask are known to be either zero or one and return them in the
680 /// KnownZero/KnownOne bitsets.
681 void TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
685 unsigned Depth) const {
686 assert(Op.getOpcode() >= ISD::BUILTIN_OP_END &&
687 "Should use MaskedValueIsZero if you don't know whether Op"
688 " is a target node!");
693 //===----------------------------------------------------------------------===//
694 // Inline Assembler Implementation Methods
695 //===----------------------------------------------------------------------===//
697 TargetLowering::ConstraintType
698 TargetLowering::getConstraintType(char ConstraintLetter) const {
699 // FIXME: lots more standard ones to handle.
700 switch (ConstraintLetter) {
701 default: return C_Unknown;
702 case 'r': return C_RegisterClass;
703 case 'i': // Simple Integer or Relocatable Constant
704 case 'n': // Simple Integer
705 case 's': // Relocatable Constant
706 case 'I': // Target registers.
713 case 'P': return C_Other;
717 bool TargetLowering::isOperandValidForConstraint(SDOperand Op,
718 char ConstraintLetter) {
719 switch (ConstraintLetter) {
720 default: return false;
721 case 'i': // Simple Integer or Relocatable Constant
722 case 'n': // Simple Integer
723 case 's': // Relocatable Constant
724 return true; // FIXME: not right.
729 std::vector<unsigned> TargetLowering::
730 getRegForInlineAsmConstraint(const std::string &Constraint) const {
731 // Not a physreg, must not be a register reference or something.
732 if (Constraint[0] != '{') return std::vector<unsigned>();
733 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
735 // Remove the braces from around the name.
736 std::string RegName(Constraint.begin()+1, Constraint.end()-1);
738 // Scan to see if this constraint is a register name.
739 const MRegisterInfo *RI = TM.getRegisterInfo();
740 for (unsigned i = 1, e = RI->getNumRegs(); i != e; ++i) {
741 if (const char *Name = RI->get(i).Name)
742 if (StringsEqualNoCase(RegName, Name))
743 return std::vector<unsigned>(1, i);
747 return std::vector<unsigned>();