1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/Analysis/AliasAnalysis.h"
16 #include "llvm/CodeGen/SelectionDAGISel.h"
17 #include "llvm/CodeGen/ScheduleDAG.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/GlobalVariable.h"
23 #include "llvm/InlineAsm.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/IntrinsicInst.h"
27 #include "llvm/CodeGen/MachineDebugInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/SchedulerRegistry.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/CodeGen/SSARegMap.h"
35 #include "llvm/Target/MRegisterInfo.h"
36 #include "llvm/Target/TargetAsmInfo.h"
37 #include "llvm/Target/TargetData.h"
38 #include "llvm/Target/TargetFrameInfo.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetLowering.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/Compiler.h"
52 ViewISelDAGs("view-isel-dags", cl::Hidden,
53 cl::desc("Pop up a window to show isel dags as they are selected"));
55 ViewSchedDAGs("view-sched-dags", cl::Hidden,
56 cl::desc("Pop up a window to show sched dags as they are processed"));
58 static const bool ViewISelDAGs = 0, ViewSchedDAGs = 0;
62 //===---------------------------------------------------------------------===//
64 /// RegisterScheduler class - Track the registration of instruction schedulers.
66 //===---------------------------------------------------------------------===//
67 MachinePassRegistry RegisterScheduler::Registry;
69 //===---------------------------------------------------------------------===//
71 /// ISHeuristic command line option for instruction schedulers.
73 //===---------------------------------------------------------------------===//
75 cl::opt<RegisterScheduler::FunctionPassCtor, false,
76 RegisterPassParser<RegisterScheduler> >
78 cl::init(&createDefaultScheduler),
79 cl::desc("Instruction schedulers available:"));
81 static RegisterScheduler
82 defaultListDAGScheduler("default", " Best scheduler for the target",
83 createDefaultScheduler);
87 /// RegsForValue - This struct represents the physical registers that a
88 /// particular value is assigned and the type information about the value.
89 /// This is needed because values can be promoted into larger registers and
90 /// expanded into multiple smaller registers than the value.
91 struct VISIBILITY_HIDDEN RegsForValue {
92 /// Regs - This list hold the register (for legal and promoted values)
93 /// or register set (for expanded values) that the value should be assigned
95 std::vector<unsigned> Regs;
97 /// RegVT - The value type of each register.
101 /// ValueVT - The value type of the LLVM value, which may be promoted from
102 /// RegVT or made from merging the two expanded parts.
103 MVT::ValueType ValueVT;
105 RegsForValue() : RegVT(MVT::Other), ValueVT(MVT::Other) {}
107 RegsForValue(unsigned Reg, MVT::ValueType regvt, MVT::ValueType valuevt)
108 : RegVT(regvt), ValueVT(valuevt) {
111 RegsForValue(const std::vector<unsigned> ®s,
112 MVT::ValueType regvt, MVT::ValueType valuevt)
113 : Regs(regs), RegVT(regvt), ValueVT(valuevt) {
116 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
117 /// this value and returns the result as a ValueVT value. This uses
118 /// Chain/Flag as the input and updates them for the output Chain/Flag.
119 SDOperand getCopyFromRegs(SelectionDAG &DAG,
120 SDOperand &Chain, SDOperand &Flag) const;
122 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
123 /// specified value into the registers specified by this object. This uses
124 /// Chain/Flag as the input and updates them for the output Chain/Flag.
125 void getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
126 SDOperand &Chain, SDOperand &Flag,
127 MVT::ValueType PtrVT) const;
129 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
130 /// operand list. This adds the code marker and includes the number of
131 /// values added into it.
132 void AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
133 std::vector<SDOperand> &Ops) const;
138 //===--------------------------------------------------------------------===//
139 /// createDefaultScheduler - This creates an instruction scheduler appropriate
141 ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
143 MachineBasicBlock *BB) {
144 TargetLowering &TLI = IS->getTargetLowering();
146 if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
147 return createTDListDAGScheduler(IS, DAG, BB);
149 assert(TLI.getSchedulingPreference() ==
150 TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
151 return createBURRListDAGScheduler(IS, DAG, BB);
156 //===--------------------------------------------------------------------===//
157 /// FunctionLoweringInfo - This contains information that is global to a
158 /// function that is used when lowering a region of the function.
159 class FunctionLoweringInfo {
166 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
168 /// MBBMap - A mapping from LLVM basic blocks to their machine code entry.
169 std::map<const BasicBlock*, MachineBasicBlock *> MBBMap;
171 /// ValueMap - Since we emit code for the function a basic block at a time,
172 /// we must remember which virtual registers hold the values for
173 /// cross-basic-block values.
174 std::map<const Value*, unsigned> ValueMap;
176 /// StaticAllocaMap - Keep track of frame indices for fixed sized allocas in
177 /// the entry block. This allows the allocas to be efficiently referenced
178 /// anywhere in the function.
179 std::map<const AllocaInst*, int> StaticAllocaMap;
181 unsigned MakeReg(MVT::ValueType VT) {
182 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
185 /// isExportedInst - Return true if the specified value is an instruction
186 /// exported from its block.
187 bool isExportedInst(const Value *V) {
188 return ValueMap.count(V);
191 unsigned CreateRegForValue(const Value *V);
193 unsigned InitializeRegForValue(const Value *V) {
194 unsigned &R = ValueMap[V];
195 assert(R == 0 && "Already initialized this value register!");
196 return R = CreateRegForValue(V);
201 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
202 /// PHI nodes or outside of the basic block that defines it, or used by a
203 /// switch instruction, which may expand to multiple basic blocks.
204 static bool isUsedOutsideOfDefiningBlock(Instruction *I) {
205 if (isa<PHINode>(I)) return true;
206 BasicBlock *BB = I->getParent();
207 for (Value::use_iterator UI = I->use_begin(), E = I->use_end(); UI != E; ++UI)
208 if (cast<Instruction>(*UI)->getParent() != BB || isa<PHINode>(*UI) ||
209 // FIXME: Remove switchinst special case.
210 isa<SwitchInst>(*UI))
215 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
216 /// entry block, return true. This includes arguments used by switches, since
217 /// the switch may expand into multiple basic blocks.
218 static bool isOnlyUsedInEntryBlock(Argument *A) {
219 BasicBlock *Entry = A->getParent()->begin();
220 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
221 if (cast<Instruction>(*UI)->getParent() != Entry || isa<SwitchInst>(*UI))
222 return false; // Use not in entry block.
226 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
227 Function &fn, MachineFunction &mf)
228 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
230 // Create a vreg for each argument register that is not dead and is used
231 // outside of the entry block for the function.
232 for (Function::arg_iterator AI = Fn.arg_begin(), E = Fn.arg_end();
234 if (!isOnlyUsedInEntryBlock(AI))
235 InitializeRegForValue(AI);
237 // Initialize the mapping of values to registers. This is only set up for
238 // instruction values that are used outside of the block that defines
240 Function::iterator BB = Fn.begin(), EB = Fn.end();
241 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
242 if (AllocaInst *AI = dyn_cast<AllocaInst>(I))
243 if (ConstantInt *CUI = dyn_cast<ConstantInt>(AI->getArraySize())) {
244 const Type *Ty = AI->getAllocatedType();
245 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
247 std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
250 // If the alignment of the value is smaller than the size of the
251 // value, and if the size of the value is particularly small
252 // (<= 8 bytes), round up to the size of the value for potentially
253 // better performance.
255 // FIXME: This could be made better with a preferred alignment hook in
256 // TargetData. It serves primarily to 8-byte align doubles for X86.
257 if (Align < TySize && TySize <= 8) Align = TySize;
258 TySize *= CUI->getZExtValue(); // Get total allocated size.
259 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
260 StaticAllocaMap[AI] =
261 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
264 for (; BB != EB; ++BB)
265 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I)
266 if (!I->use_empty() && isUsedOutsideOfDefiningBlock(I))
267 if (!isa<AllocaInst>(I) ||
268 !StaticAllocaMap.count(cast<AllocaInst>(I)))
269 InitializeRegForValue(I);
271 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
272 // also creates the initial PHI MachineInstrs, though none of the input
273 // operands are populated.
274 for (BB = Fn.begin(), EB = Fn.end(); BB != EB; ++BB) {
275 MachineBasicBlock *MBB = new MachineBasicBlock(BB);
277 MF.getBasicBlockList().push_back(MBB);
279 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
282 for (BasicBlock::iterator I = BB->begin();(PN = dyn_cast<PHINode>(I)); ++I){
283 if (PN->use_empty()) continue;
285 MVT::ValueType VT = TLI.getValueType(PN->getType());
286 unsigned NumElements;
287 if (VT != MVT::Vector)
288 NumElements = TLI.getNumElements(VT);
290 MVT::ValueType VT1,VT2;
292 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
295 unsigned PHIReg = ValueMap[PN];
296 assert(PHIReg && "PHI node does not have an assigned virtual register!");
297 const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
298 for (unsigned i = 0; i != NumElements; ++i)
299 BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
304 /// CreateRegForValue - Allocate the appropriate number of virtual registers of
305 /// the correctly promoted or expanded types. Assign these registers
306 /// consecutive vreg numbers and return the first assigned number.
307 unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
308 MVT::ValueType VT = TLI.getValueType(V->getType());
310 // The number of multiples of registers that we need, to, e.g., split up
311 // a <2 x int64> -> 4 x i32 registers.
312 unsigned NumVectorRegs = 1;
314 // If this is a packed type, figure out what type it will decompose into
315 // and how many of the elements it will use.
316 if (VT == MVT::Vector) {
317 const PackedType *PTy = cast<PackedType>(V->getType());
318 unsigned NumElts = PTy->getNumElements();
319 MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
321 // Divide the input until we get to a supported size. This will always
322 // end with a scalar if the target doesn't support vectors.
323 while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
330 VT = getVectorType(EltTy, NumElts);
333 // The common case is that we will only create one register for this
334 // value. If we have that case, create and return the virtual register.
335 unsigned NV = TLI.getNumElements(VT);
337 // If we are promoting this value, pick the next largest supported type.
338 MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
339 unsigned Reg = MakeReg(PromotedType);
340 // If this is a vector of supported or promoted types (e.g. 4 x i16),
341 // create all of the registers.
342 for (unsigned i = 1; i != NumVectorRegs; ++i)
343 MakeReg(PromotedType);
347 // If this value is represented with multiple target registers, make sure
348 // to create enough consecutive registers of the right (smaller) type.
349 VT = TLI.getTypeToExpandTo(VT);
350 unsigned R = MakeReg(VT);
351 for (unsigned i = 1; i != NV*NumVectorRegs; ++i)
356 //===----------------------------------------------------------------------===//
357 /// SelectionDAGLowering - This is the common target-independent lowering
358 /// implementation that is parameterized by a TargetLowering object.
359 /// Also, targets can overload any lowering method.
362 class SelectionDAGLowering {
363 MachineBasicBlock *CurMBB;
365 std::map<const Value*, SDOperand> NodeMap;
367 /// PendingLoads - Loads are not emitted to the program immediately. We bunch
368 /// them up and then emit token factor nodes when possible. This allows us to
369 /// get simple disambiguation between loads without worrying about alias
371 std::vector<SDOperand> PendingLoads;
373 /// Case - A pair of values to record the Value for a switch case, and the
374 /// case's target basic block.
375 typedef std::pair<Constant*, MachineBasicBlock*> Case;
376 typedef std::vector<Case>::iterator CaseItr;
377 typedef std::pair<CaseItr, CaseItr> CaseRange;
379 /// CaseRec - A struct with ctor used in lowering switches to a binary tree
380 /// of conditional branches.
382 CaseRec(MachineBasicBlock *bb, Constant *lt, Constant *ge, CaseRange r) :
383 CaseBB(bb), LT(lt), GE(ge), Range(r) {}
385 /// CaseBB - The MBB in which to emit the compare and branch
386 MachineBasicBlock *CaseBB;
387 /// LT, GE - If nonzero, we know the current case value must be less-than or
388 /// greater-than-or-equal-to these Constants.
391 /// Range - A pair of iterators representing the range of case values to be
392 /// processed at this point in the binary search tree.
396 /// The comparison function for sorting Case values.
398 bool operator () (const Case& C1, const Case& C2) {
399 assert(isa<ConstantInt>(C1.first) && isa<ConstantInt>(C2.first));
400 return cast<const ConstantInt>(C1.first)->getSExtValue() <
401 cast<const ConstantInt>(C2.first)->getSExtValue();
406 // TLI - This is information that describes the available target features we
407 // need for lowering. This indicates when operations are unavailable,
408 // implemented with a libcall, etc.
411 const TargetData *TD;
413 /// SwitchCases - Vector of CaseBlock structures used to communicate
414 /// SwitchInst code generation information.
415 std::vector<SelectionDAGISel::CaseBlock> SwitchCases;
416 SelectionDAGISel::JumpTable JT;
418 /// FuncInfo - Information about the function as a whole.
420 FunctionLoweringInfo &FuncInfo;
422 SelectionDAGLowering(SelectionDAG &dag, TargetLowering &tli,
423 FunctionLoweringInfo &funcinfo)
424 : TLI(tli), DAG(dag), TD(DAG.getTarget().getTargetData()),
425 JT(0,0,0,0), FuncInfo(funcinfo) {
428 /// getRoot - Return the current virtual root of the Selection DAG.
430 SDOperand getRoot() {
431 if (PendingLoads.empty())
432 return DAG.getRoot();
434 if (PendingLoads.size() == 1) {
435 SDOperand Root = PendingLoads[0];
437 PendingLoads.clear();
441 // Otherwise, we have to make a token factor node.
442 SDOperand Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
443 &PendingLoads[0], PendingLoads.size());
444 PendingLoads.clear();
449 SDOperand CopyValueToVirtualRegister(Value *V, unsigned Reg);
451 void visit(Instruction &I) { visit(I.getOpcode(), I); }
453 void visit(unsigned Opcode, User &I) {
454 // Note: this doesn't use InstVisitor, because it has to work with
455 // ConstantExpr's in addition to instructions.
457 default: assert(0 && "Unknown instruction type encountered!");
459 // Build the switch statement using the Instruction.def file.
460 #define HANDLE_INST(NUM, OPCODE, CLASS) \
461 case Instruction::OPCODE:return visit##OPCODE((CLASS&)I);
462 #include "llvm/Instruction.def"
466 void setCurrentBasicBlock(MachineBasicBlock *MBB) { CurMBB = MBB; }
468 SDOperand getLoadFrom(const Type *Ty, SDOperand Ptr,
469 const Value *SV, SDOperand Root,
472 SDOperand getIntPtrConstant(uint64_t Val) {
473 return DAG.getConstant(Val, TLI.getPointerTy());
476 SDOperand getValue(const Value *V);
478 const SDOperand &setValue(const Value *V, SDOperand NewN) {
479 SDOperand &N = NodeMap[V];
480 assert(N.Val == 0 && "Already set a value for this node!");
484 RegsForValue GetRegistersForValue(const std::string &ConstrCode,
486 bool OutReg, bool InReg,
487 std::set<unsigned> &OutputRegs,
488 std::set<unsigned> &InputRegs);
490 void FindMergedConditions(Value *Cond, MachineBasicBlock *TBB,
491 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
493 bool isExportableFromCurrentBlock(Value *V, const BasicBlock *FromBB);
494 void ExportFromCurrentBlock(Value *V);
496 // Terminator instructions.
497 void visitRet(ReturnInst &I);
498 void visitBr(BranchInst &I);
499 void visitSwitch(SwitchInst &I);
500 void visitUnreachable(UnreachableInst &I) { /* noop */ }
502 // Helper for visitSwitch
503 void visitSwitchCase(SelectionDAGISel::CaseBlock &CB);
504 void visitJumpTable(SelectionDAGISel::JumpTable &JT);
506 // These all get lowered before this pass.
507 void visitInvoke(InvokeInst &I) { assert(0 && "TODO"); }
508 void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
510 void visitIntBinary(User &I, unsigned IntOp, unsigned VecOp);
511 void visitFPBinary(User &I, unsigned FPOp, unsigned VecOp);
512 void visitShift(User &I, unsigned Opcode);
513 void visitAdd(User &I) {
514 if (I.getType()->isFloatingPoint())
515 visitFPBinary(I, ISD::FADD, ISD::VADD);
517 visitIntBinary(I, ISD::ADD, ISD::VADD);
519 void visitSub(User &I);
520 void visitMul(User &I) {
521 if (I.getType()->isFloatingPoint())
522 visitFPBinary(I, ISD::FMUL, ISD::VMUL);
524 visitIntBinary(I, ISD::MUL, ISD::VMUL);
526 void visitURem(User &I) { visitIntBinary(I, ISD::UREM, 0); }
527 void visitSRem(User &I) { visitIntBinary(I, ISD::SREM, 0); }
528 void visitFRem(User &I) { visitFPBinary (I, ISD::FREM, 0); }
529 void visitUDiv(User &I) { visitIntBinary(I, ISD::UDIV, ISD::VUDIV); }
530 void visitSDiv(User &I) { visitIntBinary(I, ISD::SDIV, ISD::VSDIV); }
531 void visitFDiv(User &I) { visitFPBinary (I, ISD::FDIV, ISD::VSDIV); }
532 void visitAnd(User &I) { visitIntBinary(I, ISD::AND, ISD::VAND); }
533 void visitOr (User &I) { visitIntBinary(I, ISD::OR, ISD::VOR); }
534 void visitXor(User &I) { visitIntBinary(I, ISD::XOR, ISD::VXOR); }
535 void visitShl(User &I) { visitShift(I, ISD::SHL); }
536 void visitLShr(User &I) { visitShift(I, ISD::SRL); }
537 void visitAShr(User &I) { visitShift(I, ISD::SRA); }
538 void visitICmp(User &I);
539 void visitFCmp(User &I);
540 // Visit the conversion instructions
541 void visitTrunc(User &I);
542 void visitZExt(User &I);
543 void visitSExt(User &I);
544 void visitFPTrunc(User &I);
545 void visitFPExt(User &I);
546 void visitFPToUI(User &I);
547 void visitFPToSI(User &I);
548 void visitUIToFP(User &I);
549 void visitSIToFP(User &I);
550 void visitPtrToInt(User &I);
551 void visitIntToPtr(User &I);
552 void visitBitCast(User &I);
554 void visitExtractElement(User &I);
555 void visitInsertElement(User &I);
556 void visitShuffleVector(User &I);
558 void visitGetElementPtr(User &I);
559 void visitSelect(User &I);
561 void visitMalloc(MallocInst &I);
562 void visitFree(FreeInst &I);
563 void visitAlloca(AllocaInst &I);
564 void visitLoad(LoadInst &I);
565 void visitStore(StoreInst &I);
566 void visitPHI(PHINode &I) { } // PHI nodes are handled specially.
567 void visitCall(CallInst &I);
568 void visitInlineAsm(CallInst &I);
569 const char *visitIntrinsicCall(CallInst &I, unsigned Intrinsic);
570 void visitTargetIntrinsic(CallInst &I, unsigned Intrinsic);
572 void visitVAStart(CallInst &I);
573 void visitVAArg(VAArgInst &I);
574 void visitVAEnd(CallInst &I);
575 void visitVACopy(CallInst &I);
576 void visitFrameReturnAddress(CallInst &I, bool isFrameAddress);
578 void visitMemIntrinsic(CallInst &I, unsigned Op);
580 void visitUserOp1(Instruction &I) {
581 assert(0 && "UserOp1 should not exist at instruction selection time!");
584 void visitUserOp2(Instruction &I) {
585 assert(0 && "UserOp2 should not exist at instruction selection time!");
589 } // end namespace llvm
591 SDOperand SelectionDAGLowering::getValue(const Value *V) {
592 SDOperand &N = NodeMap[V];
595 const Type *VTy = V->getType();
596 MVT::ValueType VT = TLI.getValueType(VTy);
597 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
598 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
599 visit(CE->getOpcode(), *CE);
600 assert(N.Val && "visit didn't populate the ValueMap!");
602 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
603 return N = DAG.getGlobalAddress(GV, VT);
604 } else if (isa<ConstantPointerNull>(C)) {
605 return N = DAG.getConstant(0, TLI.getPointerTy());
606 } else if (isa<UndefValue>(C)) {
607 if (!isa<PackedType>(VTy))
608 return N = DAG.getNode(ISD::UNDEF, VT);
610 // Create a VBUILD_VECTOR of undef nodes.
611 const PackedType *PTy = cast<PackedType>(VTy);
612 unsigned NumElements = PTy->getNumElements();
613 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
615 SmallVector<SDOperand, 8> Ops;
616 Ops.assign(NumElements, DAG.getNode(ISD::UNDEF, PVT));
618 // Create a VConstant node with generic Vector type.
619 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
620 Ops.push_back(DAG.getValueType(PVT));
621 return N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
622 &Ops[0], Ops.size());
623 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
624 return N = DAG.getConstantFP(CFP->getValue(), VT);
625 } else if (const PackedType *PTy = dyn_cast<PackedType>(VTy)) {
626 unsigned NumElements = PTy->getNumElements();
627 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
629 // Now that we know the number and type of the elements, push a
630 // Constant or ConstantFP node onto the ops list for each element of
631 // the packed constant.
632 SmallVector<SDOperand, 8> Ops;
633 if (ConstantPacked *CP = dyn_cast<ConstantPacked>(C)) {
634 for (unsigned i = 0; i != NumElements; ++i)
635 Ops.push_back(getValue(CP->getOperand(i)));
637 assert(isa<ConstantAggregateZero>(C) && "Unknown packed constant!");
639 if (MVT::isFloatingPoint(PVT))
640 Op = DAG.getConstantFP(0, PVT);
642 Op = DAG.getConstant(0, PVT);
643 Ops.assign(NumElements, Op);
646 // Create a VBUILD_VECTOR node with generic Vector type.
647 Ops.push_back(DAG.getConstant(NumElements, MVT::i32));
648 Ops.push_back(DAG.getValueType(PVT));
649 return N = DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector,&Ops[0],Ops.size());
651 // Canonicalize all constant ints to be unsigned.
652 return N = DAG.getConstant(cast<ConstantIntegral>(C)->getZExtValue(),VT);
656 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
657 std::map<const AllocaInst*, int>::iterator SI =
658 FuncInfo.StaticAllocaMap.find(AI);
659 if (SI != FuncInfo.StaticAllocaMap.end())
660 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
663 std::map<const Value*, unsigned>::const_iterator VMI =
664 FuncInfo.ValueMap.find(V);
665 assert(VMI != FuncInfo.ValueMap.end() && "Value not in map!");
667 unsigned InReg = VMI->second;
669 // If this type is not legal, make it so now.
670 if (VT != MVT::Vector) {
671 if (TLI.getTypeAction(VT) == TargetLowering::Expand) {
672 // Source must be expanded. This input value is actually coming from the
673 // register pair VMI->second and VMI->second+1.
674 MVT::ValueType DestVT = TLI.getTypeToExpandTo(VT);
675 unsigned NumVals = TLI.getNumElements(VT);
676 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
678 N = DAG.getNode(ISD::BIT_CONVERT, VT, N);
680 assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!");
681 N = DAG.getNode(ISD::BUILD_PAIR, VT, N,
682 DAG.getCopyFromReg(DAG.getEntryNode(), InReg+1, DestVT));
685 MVT::ValueType DestVT = TLI.getTypeToTransformTo(VT);
686 N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
687 if (TLI.getTypeAction(VT) == TargetLowering::Promote) // Promotion case
688 N = MVT::isFloatingPoint(VT)
689 ? DAG.getNode(ISD::FP_ROUND, VT, N)
690 : DAG.getNode(ISD::TRUNCATE, VT, N);
693 // Otherwise, if this is a vector, make it available as a generic vector
695 MVT::ValueType PTyElementVT, PTyLegalElementVT;
696 const PackedType *PTy = cast<PackedType>(VTy);
697 unsigned NE = TLI.getPackedTypeBreakdown(PTy, PTyElementVT,
700 // Build a VBUILD_VECTOR with the input registers.
701 SmallVector<SDOperand, 8> Ops;
702 if (PTyElementVT == PTyLegalElementVT) {
703 // If the value types are legal, just VBUILD the CopyFromReg nodes.
704 for (unsigned i = 0; i != NE; ++i)
705 Ops.push_back(DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
707 } else if (PTyElementVT < PTyLegalElementVT) {
708 // If the register was promoted, use TRUNCATE of FP_ROUND as appropriate.
709 for (unsigned i = 0; i != NE; ++i) {
710 SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
712 if (MVT::isFloatingPoint(PTyElementVT))
713 Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op);
715 Op = DAG.getNode(ISD::TRUNCATE, PTyElementVT, Op);
719 // If the register was expanded, use BUILD_PAIR.
720 assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!");
721 for (unsigned i = 0; i != NE/2; ++i) {
722 SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
724 SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++,
726 Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1));
730 Ops.push_back(DAG.getConstant(NE, MVT::i32));
731 Ops.push_back(DAG.getValueType(PTyLegalElementVT));
732 N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
734 // Finally, use a VBIT_CONVERT to make this available as the appropriate
736 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
737 DAG.getConstant(PTy->getNumElements(),
739 DAG.getValueType(TLI.getValueType(PTy->getElementType())));
746 void SelectionDAGLowering::visitRet(ReturnInst &I) {
747 if (I.getNumOperands() == 0) {
748 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other, getRoot()));
751 SmallVector<SDOperand, 8> NewValues;
752 NewValues.push_back(getRoot());
753 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
754 SDOperand RetOp = getValue(I.getOperand(i));
756 // If this is an integer return value, we need to promote it ourselves to
757 // the full width of a register, since LegalizeOp will use ANY_EXTEND rather
759 // FIXME: C calling convention requires the return type to be promoted to
760 // at least 32-bit. But this is not necessary for non-C calling conventions.
761 if (MVT::isInteger(RetOp.getValueType()) &&
762 RetOp.getValueType() < MVT::i64) {
763 MVT::ValueType TmpVT;
764 if (TLI.getTypeAction(MVT::i32) == TargetLowering::Promote)
765 TmpVT = TLI.getTypeToTransformTo(MVT::i32);
768 const FunctionType *FTy = I.getParent()->getParent()->getFunctionType();
769 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
770 if (FTy->paramHasAttr(0, FunctionType::SExtAttribute))
771 ExtendKind = ISD::SIGN_EXTEND;
772 if (FTy->paramHasAttr(0, FunctionType::ZExtAttribute))
773 ExtendKind = ISD::ZERO_EXTEND;
774 RetOp = DAG.getNode(ExtendKind, TmpVT, RetOp);
776 NewValues.push_back(RetOp);
777 NewValues.push_back(DAG.getConstant(false, MVT::i32));
779 DAG.setRoot(DAG.getNode(ISD::RET, MVT::Other,
780 &NewValues[0], NewValues.size()));
783 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
784 /// the current basic block, add it to ValueMap now so that we'll get a
786 void SelectionDAGLowering::ExportFromCurrentBlock(Value *V) {
787 // No need to export constants.
788 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
791 if (FuncInfo.isExportedInst(V)) return;
793 unsigned Reg = FuncInfo.InitializeRegForValue(V);
794 PendingLoads.push_back(CopyValueToVirtualRegister(V, Reg));
797 bool SelectionDAGLowering::isExportableFromCurrentBlock(Value *V,
798 const BasicBlock *FromBB) {
799 // The operands of the setcc have to be in this block. We don't know
800 // how to export them from some other block.
801 if (Instruction *VI = dyn_cast<Instruction>(V)) {
802 // Can export from current BB.
803 if (VI->getParent() == FromBB)
806 // Is already exported, noop.
807 return FuncInfo.isExportedInst(V);
810 // If this is an argument, we can export it if the BB is the entry block or
811 // if it is already exported.
812 if (isa<Argument>(V)) {
813 if (FromBB == &FromBB->getParent()->getEntryBlock())
816 // Otherwise, can only export this if it is already exported.
817 return FuncInfo.isExportedInst(V);
820 // Otherwise, constants can always be exported.
824 static bool InBlock(const Value *V, const BasicBlock *BB) {
825 if (const Instruction *I = dyn_cast<Instruction>(V))
826 return I->getParent() == BB;
830 /// FindMergedConditions - If Cond is an expression like
831 void SelectionDAGLowering::FindMergedConditions(Value *Cond,
832 MachineBasicBlock *TBB,
833 MachineBasicBlock *FBB,
834 MachineBasicBlock *CurBB,
836 // If this node is not part of the or/and tree, emit it as a branch.
837 Instruction *BOp = dyn_cast<Instruction>(Cond);
839 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
840 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
841 BOp->getParent() != CurBB->getBasicBlock() ||
842 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
843 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
844 const BasicBlock *BB = CurBB->getBasicBlock();
846 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(Cond))
847 if ((II->getIntrinsicID() == Intrinsic::isunordered_f32 ||
848 II->getIntrinsicID() == Intrinsic::isunordered_f64) &&
849 // The operands of the setcc have to be in this block. We don't know
850 // how to export them from some other block. If this is the first
851 // block of the sequence, no exporting is needed.
853 (isExportableFromCurrentBlock(II->getOperand(1), BB) &&
854 isExportableFromCurrentBlock(II->getOperand(2), BB)))) {
855 SelectionDAGISel::CaseBlock CB(ISD::SETUO, II->getOperand(1),
856 II->getOperand(2), TBB, FBB, CurBB);
857 SwitchCases.push_back(CB);
862 // If the leaf of the tree is a comparison, merge the condition into
864 if ((isa<ICmpInst>(Cond) || isa<FCmpInst>(Cond)) &&
865 // The operands of the cmp have to be in this block. We don't know
866 // how to export them from some other block. If this is the first block
867 // of the sequence, no exporting is needed.
869 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
870 isExportableFromCurrentBlock(BOp->getOperand(1), BB)))) {
871 BOp = cast<Instruction>(Cond);
872 ISD::CondCode Condition;
873 if (ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
874 switch (IC->getPredicate()) {
875 default: assert(0 && "Unknown icmp predicate opcode!");
876 case ICmpInst::ICMP_EQ: Condition = ISD::SETEQ; break;
877 case ICmpInst::ICMP_NE: Condition = ISD::SETNE; break;
878 case ICmpInst::ICMP_SLE: Condition = ISD::SETLE; break;
879 case ICmpInst::ICMP_ULE: Condition = ISD::SETULE; break;
880 case ICmpInst::ICMP_SGE: Condition = ISD::SETGE; break;
881 case ICmpInst::ICMP_UGE: Condition = ISD::SETUGE; break;
882 case ICmpInst::ICMP_SLT: Condition = ISD::SETLT; break;
883 case ICmpInst::ICMP_ULT: Condition = ISD::SETULT; break;
884 case ICmpInst::ICMP_SGT: Condition = ISD::SETGT; break;
885 case ICmpInst::ICMP_UGT: Condition = ISD::SETUGT; break;
887 } else if (FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
888 ISD::CondCode FPC, FOC;
889 switch (FC->getPredicate()) {
890 default: assert(0 && "Unknown fcmp predicate opcode!");
891 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
892 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
893 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
894 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
895 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
896 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
897 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
898 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
899 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
900 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
901 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
902 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
903 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
904 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
905 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
906 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
908 if (FiniteOnlyFPMath())
913 assert(0 && "Unknown compare instruction");
916 SelectionDAGISel::CaseBlock CB(Condition, BOp->getOperand(0),
917 BOp->getOperand(1), TBB, FBB, CurBB);
918 SwitchCases.push_back(CB);
922 // Create a CaseBlock record representing this branch.
923 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, Cond, ConstantBool::getTrue(),
925 SwitchCases.push_back(CB);
930 // Create TmpBB after CurBB.
931 MachineFunction::iterator BBI = CurBB;
932 MachineBasicBlock *TmpBB = new MachineBasicBlock(CurBB->getBasicBlock());
933 CurBB->getParent()->getBasicBlockList().insert(++BBI, TmpBB);
935 if (Opc == Instruction::Or) {
944 // Emit the LHS condition.
945 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, Opc);
947 // Emit the RHS condition into TmpBB.
948 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
950 assert(Opc == Instruction::And && "Unknown merge op!");
958 // This requires creation of TmpBB after CurBB.
960 // Emit the LHS condition.
961 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, Opc);
963 // Emit the RHS condition into TmpBB.
964 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, Opc);
968 /// If the set of cases should be emitted as a series of branches, return true.
969 /// If we should emit this as a bunch of and/or'd together conditions, return
972 ShouldEmitAsBranches(const std::vector<SelectionDAGISel::CaseBlock> &Cases) {
973 if (Cases.size() != 2) return true;
975 // If this is two comparisons of the same values or'd or and'd together, they
976 // will get folded into a single comparison, so don't emit two blocks.
977 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
978 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
979 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
980 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
987 void SelectionDAGLowering::visitBr(BranchInst &I) {
988 // Update machine-CFG edges.
989 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
991 // Figure out which block is immediately after the current one.
992 MachineBasicBlock *NextBlock = 0;
993 MachineFunction::iterator BBI = CurMBB;
994 if (++BBI != CurMBB->getParent()->end())
997 if (I.isUnconditional()) {
998 // If this is not a fall-through branch, emit the branch.
999 if (Succ0MBB != NextBlock)
1000 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1001 DAG.getBasicBlock(Succ0MBB)));
1003 // Update machine-CFG edges.
1004 CurMBB->addSuccessor(Succ0MBB);
1009 // If this condition is one of the special cases we handle, do special stuff
1011 Value *CondVal = I.getCondition();
1012 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1014 // If this is a series of conditions that are or'd or and'd together, emit
1015 // this as a sequence of branches instead of setcc's with and/or operations.
1016 // For example, instead of something like:
1029 if (BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1030 if (BOp->hasOneUse() &&
1031 (BOp->getOpcode() == Instruction::And ||
1032 BOp->getOpcode() == Instruction::Or)) {
1033 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, CurMBB, BOp->getOpcode());
1034 // If the compares in later blocks need to use values not currently
1035 // exported from this block, export them now. This block should always
1036 // be the first entry.
1037 assert(SwitchCases[0].ThisBB == CurMBB && "Unexpected lowering!");
1039 // Allow some cases to be rejected.
1040 if (ShouldEmitAsBranches(SwitchCases)) {
1041 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1042 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1043 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1046 // Emit the branch for this block.
1047 visitSwitchCase(SwitchCases[0]);
1048 SwitchCases.erase(SwitchCases.begin());
1052 // Okay, we decided not to do this, remove any inserted MBB's and clear
1054 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1055 CurMBB->getParent()->getBasicBlockList().erase(SwitchCases[i].ThisBB);
1057 SwitchCases.clear();
1061 // Create a CaseBlock record representing this branch.
1062 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, CondVal, ConstantBool::getTrue(),
1063 Succ0MBB, Succ1MBB, CurMBB);
1064 // Use visitSwitchCase to actually insert the fast branch sequence for this
1066 visitSwitchCase(CB);
1069 /// visitSwitchCase - Emits the necessary code to represent a single node in
1070 /// the binary search tree resulting from lowering a switch instruction.
1071 void SelectionDAGLowering::visitSwitchCase(SelectionDAGISel::CaseBlock &CB) {
1073 SDOperand CondLHS = getValue(CB.CmpLHS);
1075 // Build the setcc now, fold "(X == true)" to X and "(X == false)" to !X to
1076 // handle common cases produced by branch lowering.
1077 if (CB.CmpRHS == ConstantBool::getTrue() && CB.CC == ISD::SETEQ)
1079 else if (CB.CmpRHS == ConstantBool::getFalse() && CB.CC == ISD::SETEQ) {
1080 SDOperand True = DAG.getConstant(1, CondLHS.getValueType());
1081 Cond = DAG.getNode(ISD::XOR, CondLHS.getValueType(), CondLHS, True);
1083 Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1085 // Set NextBlock to be the MBB immediately after the current one, if any.
1086 // This is used to avoid emitting unnecessary branches to the next block.
1087 MachineBasicBlock *NextBlock = 0;
1088 MachineFunction::iterator BBI = CurMBB;
1089 if (++BBI != CurMBB->getParent()->end())
1092 // If the lhs block is the next block, invert the condition so that we can
1093 // fall through to the lhs instead of the rhs block.
1094 if (CB.TrueBB == NextBlock) {
1095 std::swap(CB.TrueBB, CB.FalseBB);
1096 SDOperand True = DAG.getConstant(1, Cond.getValueType());
1097 Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
1099 SDOperand BrCond = DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(), Cond,
1100 DAG.getBasicBlock(CB.TrueBB));
1101 if (CB.FalseBB == NextBlock)
1102 DAG.setRoot(BrCond);
1104 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, BrCond,
1105 DAG.getBasicBlock(CB.FalseBB)));
1106 // Update successor info
1107 CurMBB->addSuccessor(CB.TrueBB);
1108 CurMBB->addSuccessor(CB.FalseBB);
1111 void SelectionDAGLowering::visitJumpTable(SelectionDAGISel::JumpTable &JT) {
1112 // Emit the code for the jump table
1113 MVT::ValueType PTy = TLI.getPointerTy();
1114 SDOperand Index = DAG.getCopyFromReg(getRoot(), JT.Reg, PTy);
1115 SDOperand Table = DAG.getJumpTable(JT.JTI, PTy);
1116 DAG.setRoot(DAG.getNode(ISD::BR_JT, MVT::Other, Index.getValue(1),
1121 void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
1122 // Figure out which block is immediately after the current one.
1123 MachineBasicBlock *NextBlock = 0;
1124 MachineFunction::iterator BBI = CurMBB;
1126 if (++BBI != CurMBB->getParent()->end())
1129 MachineBasicBlock *Default = FuncInfo.MBBMap[I.getDefaultDest()];
1131 // If there is only the default destination, branch to it if it is not the
1132 // next basic block. Otherwise, just fall through.
1133 if (I.getNumOperands() == 2) {
1134 // Update machine-CFG edges.
1136 // If this is not a fall-through branch, emit the branch.
1137 if (Default != NextBlock)
1138 DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
1139 DAG.getBasicBlock(Default)));
1141 CurMBB->addSuccessor(Default);
1145 // If there are any non-default case statements, create a vector of Cases
1146 // representing each one, and sort the vector so that we can efficiently
1147 // create a binary search tree from them.
1148 std::vector<Case> Cases;
1150 for (unsigned i = 1; i < I.getNumSuccessors(); ++i) {
1151 MachineBasicBlock *SMBB = FuncInfo.MBBMap[I.getSuccessor(i)];
1152 Cases.push_back(Case(I.getSuccessorValue(i), SMBB));
1155 std::sort(Cases.begin(), Cases.end(), CaseCmp());
1157 // Get the Value to be switched on and default basic blocks, which will be
1158 // inserted into CaseBlock records, representing basic blocks in the binary
1160 Value *SV = I.getOperand(0);
1162 // Get the MachineFunction which holds the current MBB. This is used during
1163 // emission of jump tables, and when inserting any additional MBBs necessary
1164 // to represent the switch.
1165 MachineFunction *CurMF = CurMBB->getParent();
1166 const BasicBlock *LLVMBB = CurMBB->getBasicBlock();
1168 // If the switch has few cases (two or less) emit a series of specific
1170 if (Cases.size() < 3) {
1171 // TODO: If any two of the cases has the same destination, and if one value
1172 // is the same as the other, but has one bit unset that the other has set,
1173 // use bit manipulation to do two compares at once. For example:
1174 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1176 // Rearrange the case blocks so that the last one falls through if possible.
1177 if (NextBlock && Default != NextBlock && Cases.back().second != NextBlock) {
1178 // The last case block won't fall through into 'NextBlock' if we emit the
1179 // branches in this order. See if rearranging a case value would help.
1180 for (unsigned i = 0, e = Cases.size()-1; i != e; ++i) {
1181 if (Cases[i].second == NextBlock) {
1182 std::swap(Cases[i], Cases.back());
1188 // Create a CaseBlock record representing a conditional branch to
1189 // the Case's target mbb if the value being switched on SV is equal
1191 MachineBasicBlock *CurBlock = CurMBB;
1192 for (unsigned i = 0, e = Cases.size(); i != e; ++i) {
1193 MachineBasicBlock *FallThrough;
1195 FallThrough = new MachineBasicBlock(CurMBB->getBasicBlock());
1196 CurMF->getBasicBlockList().insert(BBI, FallThrough);
1198 // If the last case doesn't match, go to the default block.
1199 FallThrough = Default;
1202 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, Cases[i].first,
1203 Cases[i].second, FallThrough, CurBlock);
1205 // If emitting the first comparison, just call visitSwitchCase to emit the
1206 // code into the current block. Otherwise, push the CaseBlock onto the
1207 // vector to be later processed by SDISel, and insert the node's MBB
1208 // before the next MBB.
1209 if (CurBlock == CurMBB)
1210 visitSwitchCase(CB);
1212 SwitchCases.push_back(CB);
1214 CurBlock = FallThrough;
1219 // If the switch has more than 5 blocks, and at least 31.25% dense, and the
1220 // target supports indirect branches, then emit a jump table rather than
1221 // lowering the switch to a binary tree of conditional branches.
1222 if ((TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
1223 TLI.isOperationLegal(ISD::BRIND, MVT::Other)) &&
1225 uint64_t First =cast<ConstantIntegral>(Cases.front().first)->getZExtValue();
1226 uint64_t Last = cast<ConstantIntegral>(Cases.back().first)->getZExtValue();
1227 double Density = (double)Cases.size() / (double)((Last - First) + 1ULL);
1229 if (Density >= 0.3125) {
1230 // Create a new basic block to hold the code for loading the address
1231 // of the jump table, and jumping to it. Update successor information;
1232 // we will either branch to the default case for the switch, or the jump
1234 MachineBasicBlock *JumpTableBB = new MachineBasicBlock(LLVMBB);
1235 CurMF->getBasicBlockList().insert(BBI, JumpTableBB);
1236 CurMBB->addSuccessor(Default);
1237 CurMBB->addSuccessor(JumpTableBB);
1239 // Subtract the lowest switch case value from the value being switched on
1240 // and conditional branch to default mbb if the result is greater than the
1241 // difference between smallest and largest cases.
1242 SDOperand SwitchOp = getValue(SV);
1243 MVT::ValueType VT = SwitchOp.getValueType();
1244 SDOperand SUB = DAG.getNode(ISD::SUB, VT, SwitchOp,
1245 DAG.getConstant(First, VT));
1247 // The SDNode we just created, which holds the value being switched on
1248 // minus the the smallest case value, needs to be copied to a virtual
1249 // register so it can be used as an index into the jump table in a
1250 // subsequent basic block. This value may be smaller or larger than the
1251 // target's pointer type, and therefore require extension or truncating.
1252 if (VT > TLI.getPointerTy())
1253 SwitchOp = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), SUB);
1255 SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), SUB);
1257 unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy());
1258 SDOperand CopyTo = DAG.getCopyToReg(getRoot(), JumpTableReg, SwitchOp);
1260 // Emit the range check for the jump table, and branch to the default
1261 // block for the switch statement if the value being switched on exceeds
1262 // the largest case in the switch.
1263 SDOperand CMP = DAG.getSetCC(TLI.getSetCCResultTy(), SUB,
1264 DAG.getConstant(Last-First,VT), ISD::SETUGT);
1265 DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, CopyTo, CMP,
1266 DAG.getBasicBlock(Default)));
1268 // Build a vector of destination BBs, corresponding to each target
1269 // of the jump table. If the value of the jump table slot corresponds to
1270 // a case statement, push the case's BB onto the vector, otherwise, push
1272 std::vector<MachineBasicBlock*> DestBBs;
1273 uint64_t TEI = First;
1274 for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI)
1275 if (cast<ConstantIntegral>(ii->first)->getZExtValue() == TEI) {
1276 DestBBs.push_back(ii->second);
1279 DestBBs.push_back(Default);
1282 // Update successor info. Add one edge to each unique successor.
1283 // Vector bool would be better, but vector<bool> is really slow.
1284 std::vector<unsigned char> SuccsHandled;
1285 SuccsHandled.resize(CurMBB->getParent()->getNumBlockIDs());
1287 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1288 E = DestBBs.end(); I != E; ++I) {
1289 if (!SuccsHandled[(*I)->getNumber()]) {
1290 SuccsHandled[(*I)->getNumber()] = true;
1291 JumpTableBB->addSuccessor(*I);
1295 // Create a jump table index for this jump table, or return an existing
1297 unsigned JTI = CurMF->getJumpTableInfo()->getJumpTableIndex(DestBBs);
1299 // Set the jump table information so that we can codegen it as a second
1300 // MachineBasicBlock
1301 JT.Reg = JumpTableReg;
1303 JT.MBB = JumpTableBB;
1304 JT.Default = Default;
1309 // Push the initial CaseRec onto the worklist
1310 std::vector<CaseRec> CaseVec;
1311 CaseVec.push_back(CaseRec(CurMBB,0,0,CaseRange(Cases.begin(),Cases.end())));
1313 while (!CaseVec.empty()) {
1314 // Grab a record representing a case range to process off the worklist
1315 CaseRec CR = CaseVec.back();
1318 // Size is the number of Cases represented by this range. If Size is 1,
1319 // then we are processing a leaf of the binary search tree. Otherwise,
1320 // we need to pick a pivot, and push left and right ranges onto the
1322 unsigned Size = CR.Range.second - CR.Range.first;
1325 // Create a CaseBlock record representing a conditional branch to
1326 // the Case's target mbb if the value being switched on SV is equal
1327 // to C. Otherwise, branch to default.
1328 Constant *C = CR.Range.first->first;
1329 MachineBasicBlock *Target = CR.Range.first->second;
1330 SelectionDAGISel::CaseBlock CB(ISD::SETEQ, SV, C, Target, Default,
1333 // If the MBB representing the leaf node is the current MBB, then just
1334 // call visitSwitchCase to emit the code into the current block.
1335 // Otherwise, push the CaseBlock onto the vector to be later processed
1336 // by SDISel, and insert the node's MBB before the next MBB.
1337 if (CR.CaseBB == CurMBB)
1338 visitSwitchCase(CB);
1340 SwitchCases.push_back(CB);
1342 // split case range at pivot
1343 CaseItr Pivot = CR.Range.first + (Size / 2);
1344 CaseRange LHSR(CR.Range.first, Pivot);
1345 CaseRange RHSR(Pivot, CR.Range.second);
1346 Constant *C = Pivot->first;
1347 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1349 // We know that we branch to the LHS if the Value being switched on is
1350 // less than the Pivot value, C. We use this to optimize our binary
1351 // tree a bit, by recognizing that if SV is greater than or equal to the
1352 // LHS's Case Value, and that Case Value is exactly one less than the
1353 // Pivot's Value, then we can branch directly to the LHS's Target,
1354 // rather than creating a leaf node for it.
1355 if ((LHSR.second - LHSR.first) == 1 &&
1356 LHSR.first->first == CR.GE &&
1357 cast<ConstantIntegral>(C)->getZExtValue() ==
1358 (cast<ConstantIntegral>(CR.GE)->getZExtValue() + 1ULL)) {
1359 TrueBB = LHSR.first->second;
1361 TrueBB = new MachineBasicBlock(LLVMBB);
1362 CurMF->getBasicBlockList().insert(BBI, TrueBB);
1363 CaseVec.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
1366 // Similar to the optimization above, if the Value being switched on is
1367 // known to be less than the Constant CR.LT, and the current Case Value
1368 // is CR.LT - 1, then we can branch directly to the target block for
1369 // the current Case Value, rather than emitting a RHS leaf node for it.
1370 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
1371 cast<ConstantIntegral>(RHSR.first->first)->getZExtValue() ==
1372 (cast<ConstantIntegral>(CR.LT)->getZExtValue() - 1ULL)) {
1373 FalseBB = RHSR.first->second;
1375 FalseBB = new MachineBasicBlock(LLVMBB);
1376 CurMF->getBasicBlockList().insert(BBI, FalseBB);
1377 CaseVec.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
1380 // Create a CaseBlock record representing a conditional branch to
1381 // the LHS node if the value being switched on SV is less than C.
1382 // Otherwise, branch to LHS.
1383 ISD::CondCode CC = ISD::SETLT;
1384 SelectionDAGISel::CaseBlock CB(CC, SV, C, TrueBB, FalseBB, CR.CaseBB);
1386 if (CR.CaseBB == CurMBB)
1387 visitSwitchCase(CB);
1389 SwitchCases.push_back(CB);
1394 void SelectionDAGLowering::visitSub(User &I) {
1395 // -0.0 - X --> fneg
1396 if (I.getType()->isFloatingPoint()) {
1397 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
1398 if (CFP->isExactlyValue(-0.0)) {
1399 SDOperand Op2 = getValue(I.getOperand(1));
1400 setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
1403 visitFPBinary(I, ISD::FSUB, ISD::VSUB);
1405 visitIntBinary(I, ISD::SUB, ISD::VSUB);
1409 SelectionDAGLowering::visitIntBinary(User &I, unsigned IntOp, unsigned VecOp) {
1410 const Type *Ty = I.getType();
1411 SDOperand Op1 = getValue(I.getOperand(0));
1412 SDOperand Op2 = getValue(I.getOperand(1));
1414 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
1415 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
1416 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
1417 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
1419 setValue(&I, DAG.getNode(IntOp, Op1.getValueType(), Op1, Op2));
1424 SelectionDAGLowering::visitFPBinary(User &I, unsigned FPOp, unsigned VecOp) {
1425 const Type *Ty = I.getType();
1426 SDOperand Op1 = getValue(I.getOperand(0));
1427 SDOperand Op2 = getValue(I.getOperand(1));
1429 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
1430 SDOperand Num = DAG.getConstant(PTy->getNumElements(), MVT::i32);
1431 SDOperand Typ = DAG.getValueType(TLI.getValueType(PTy->getElementType()));
1432 setValue(&I, DAG.getNode(VecOp, MVT::Vector, Op1, Op2, Num, Typ));
1434 setValue(&I, DAG.getNode(FPOp, Op1.getValueType(), Op1, Op2));
1438 void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) {
1439 SDOperand Op1 = getValue(I.getOperand(0));
1440 SDOperand Op2 = getValue(I.getOperand(1));
1442 Op2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Op2);
1444 setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));
1447 void SelectionDAGLowering::visitICmp(User &I) {
1448 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
1449 if (ICmpInst *IC = dyn_cast<ICmpInst>(&I))
1450 predicate = IC->getPredicate();
1451 else if (ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
1452 predicate = ICmpInst::Predicate(IC->getPredicate());
1453 SDOperand Op1 = getValue(I.getOperand(0));
1454 SDOperand Op2 = getValue(I.getOperand(1));
1455 ISD::CondCode Opcode;
1456 switch (predicate) {
1457 case ICmpInst::ICMP_EQ : Opcode = ISD::SETEQ; break;
1458 case ICmpInst::ICMP_NE : Opcode = ISD::SETNE; break;
1459 case ICmpInst::ICMP_UGT : Opcode = ISD::SETUGT; break;
1460 case ICmpInst::ICMP_UGE : Opcode = ISD::SETUGE; break;
1461 case ICmpInst::ICMP_ULT : Opcode = ISD::SETULT; break;
1462 case ICmpInst::ICMP_ULE : Opcode = ISD::SETULE; break;
1463 case ICmpInst::ICMP_SGT : Opcode = ISD::SETGT; break;
1464 case ICmpInst::ICMP_SGE : Opcode = ISD::SETGE; break;
1465 case ICmpInst::ICMP_SLT : Opcode = ISD::SETLT; break;
1466 case ICmpInst::ICMP_SLE : Opcode = ISD::SETLE; break;
1468 assert(!"Invalid ICmp predicate value");
1469 Opcode = ISD::SETEQ;
1472 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Opcode));
1475 void SelectionDAGLowering::visitFCmp(User &I) {
1476 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
1477 if (FCmpInst *FC = dyn_cast<FCmpInst>(&I))
1478 predicate = FC->getPredicate();
1479 else if (ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
1480 predicate = FCmpInst::Predicate(FC->getPredicate());
1481 SDOperand Op1 = getValue(I.getOperand(0));
1482 SDOperand Op2 = getValue(I.getOperand(1));
1483 ISD::CondCode Condition, FOC, FPC;
1484 switch (predicate) {
1485 case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
1486 case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
1487 case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
1488 case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
1489 case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
1490 case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
1491 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
1492 case FCmpInst::FCMP_ORD: FOC = ISD::SETEQ; FPC = ISD::SETO; break;
1493 case FCmpInst::FCMP_UNO: FOC = ISD::SETNE; FPC = ISD::SETUO; break;
1494 case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
1495 case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
1496 case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
1497 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
1498 case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
1499 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
1500 case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
1502 assert(!"Invalid FCmp predicate value");
1503 FOC = FPC = ISD::SETFALSE;
1506 if (FiniteOnlyFPMath())
1510 setValue(&I, DAG.getSetCC(MVT::i1, Op1, Op2, Condition));
1513 void SelectionDAGLowering::visitSelect(User &I) {
1514 SDOperand Cond = getValue(I.getOperand(0));
1515 SDOperand TrueVal = getValue(I.getOperand(1));
1516 SDOperand FalseVal = getValue(I.getOperand(2));
1517 if (!isa<PackedType>(I.getType())) {
1518 setValue(&I, DAG.getNode(ISD::SELECT, TrueVal.getValueType(), Cond,
1519 TrueVal, FalseVal));
1521 setValue(&I, DAG.getNode(ISD::VSELECT, MVT::Vector, Cond, TrueVal, FalseVal,
1522 *(TrueVal.Val->op_end()-2),
1523 *(TrueVal.Val->op_end()-1)));
1528 void SelectionDAGLowering::visitTrunc(User &I) {
1529 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
1530 SDOperand N = getValue(I.getOperand(0));
1531 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1532 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
1535 void SelectionDAGLowering::visitZExt(User &I) {
1536 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
1537 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
1538 SDOperand N = getValue(I.getOperand(0));
1539 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1540 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
1543 void SelectionDAGLowering::visitSExt(User &I) {
1544 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
1545 // SExt also can't be a cast to bool for same reason. So, nothing much to do
1546 SDOperand N = getValue(I.getOperand(0));
1547 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1548 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DestVT, N));
1551 void SelectionDAGLowering::visitFPTrunc(User &I) {
1552 // FPTrunc is never a no-op cast, no need to check
1553 SDOperand N = getValue(I.getOperand(0));
1554 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1555 setValue(&I, DAG.getNode(ISD::FP_ROUND, DestVT, N));
1558 void SelectionDAGLowering::visitFPExt(User &I){
1559 // FPTrunc is never a no-op cast, no need to check
1560 SDOperand N = getValue(I.getOperand(0));
1561 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1562 setValue(&I, DAG.getNode(ISD::FP_EXTEND, DestVT, N));
1565 void SelectionDAGLowering::visitFPToUI(User &I) {
1566 // FPToUI is never a no-op cast, no need to check
1567 SDOperand N = getValue(I.getOperand(0));
1568 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1569 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DestVT, N));
1572 void SelectionDAGLowering::visitFPToSI(User &I) {
1573 // FPToSI is never a no-op cast, no need to check
1574 SDOperand N = getValue(I.getOperand(0));
1575 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1576 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DestVT, N));
1579 void SelectionDAGLowering::visitUIToFP(User &I) {
1580 // UIToFP is never a no-op cast, no need to check
1581 SDOperand N = getValue(I.getOperand(0));
1582 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1583 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DestVT, N));
1586 void SelectionDAGLowering::visitSIToFP(User &I){
1587 // UIToFP is never a no-op cast, no need to check
1588 SDOperand N = getValue(I.getOperand(0));
1589 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1590 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DestVT, N));
1593 void SelectionDAGLowering::visitPtrToInt(User &I) {
1594 // What to do depends on the size of the integer and the size of the pointer.
1595 // We can either truncate, zero extend, or no-op, accordingly.
1596 SDOperand N = getValue(I.getOperand(0));
1597 MVT::ValueType SrcVT = N.getValueType();
1598 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1600 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
1601 Result = DAG.getNode(ISD::TRUNCATE, DestVT, N);
1603 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
1604 Result = DAG.getNode(ISD::ZERO_EXTEND, DestVT, N);
1605 setValue(&I, Result);
1608 void SelectionDAGLowering::visitIntToPtr(User &I) {
1609 // What to do depends on the size of the integer and the size of the pointer.
1610 // We can either truncate, zero extend, or no-op, accordingly.
1611 SDOperand N = getValue(I.getOperand(0));
1612 MVT::ValueType SrcVT = N.getValueType();
1613 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1614 if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(SrcVT))
1615 setValue(&I, DAG.getNode(ISD::TRUNCATE, DestVT, N));
1617 // Note: ZERO_EXTEND can handle cases where the sizes are equal too
1618 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DestVT, N));
1621 void SelectionDAGLowering::visitBitCast(User &I) {
1622 SDOperand N = getValue(I.getOperand(0));
1623 MVT::ValueType DestVT = TLI.getValueType(I.getType());
1624 if (DestVT == MVT::Vector) {
1625 // This is a cast to a vector from something else.
1626 // Get information about the output vector.
1627 const PackedType *DestTy = cast<PackedType>(I.getType());
1628 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1629 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N,
1630 DAG.getConstant(DestTy->getNumElements(),MVT::i32),
1631 DAG.getValueType(EltVT)));
1634 MVT::ValueType SrcVT = N.getValueType();
1635 if (SrcVT == MVT::Vector) {
1636 // This is a cast from a vctor to something else.
1637 // Get information about the input vector.
1638 setValue(&I, DAG.getNode(ISD::VBIT_CONVERT, DestVT, N));
1642 // BitCast assures us that source and destination are the same size so this
1643 // is either a BIT_CONVERT or a no-op.
1644 if (DestVT != N.getValueType())
1645 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DestVT, N)); // convert types
1647 setValue(&I, N); // noop cast.
1650 void SelectionDAGLowering::visitInsertElement(User &I) {
1651 SDOperand InVec = getValue(I.getOperand(0));
1652 SDOperand InVal = getValue(I.getOperand(1));
1653 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1654 getValue(I.getOperand(2)));
1656 SDOperand Num = *(InVec.Val->op_end()-2);
1657 SDOperand Typ = *(InVec.Val->op_end()-1);
1658 setValue(&I, DAG.getNode(ISD::VINSERT_VECTOR_ELT, MVT::Vector,
1659 InVec, InVal, InIdx, Num, Typ));
1662 void SelectionDAGLowering::visitExtractElement(User &I) {
1663 SDOperand InVec = getValue(I.getOperand(0));
1664 SDOperand InIdx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(),
1665 getValue(I.getOperand(1)));
1666 SDOperand Typ = *(InVec.Val->op_end()-1);
1667 setValue(&I, DAG.getNode(ISD::VEXTRACT_VECTOR_ELT,
1668 TLI.getValueType(I.getType()), InVec, InIdx));
1671 void SelectionDAGLowering::visitShuffleVector(User &I) {
1672 SDOperand V1 = getValue(I.getOperand(0));
1673 SDOperand V2 = getValue(I.getOperand(1));
1674 SDOperand Mask = getValue(I.getOperand(2));
1676 SDOperand Num = *(V1.Val->op_end()-2);
1677 SDOperand Typ = *(V2.Val->op_end()-1);
1678 setValue(&I, DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
1679 V1, V2, Mask, Num, Typ));
1683 void SelectionDAGLowering::visitGetElementPtr(User &I) {
1684 SDOperand N = getValue(I.getOperand(0));
1685 const Type *Ty = I.getOperand(0)->getType();
1687 for (GetElementPtrInst::op_iterator OI = I.op_begin()+1, E = I.op_end();
1690 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
1691 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
1694 uint64_t Offset = TD->getStructLayout(StTy)->MemberOffsets[Field];
1695 N = DAG.getNode(ISD::ADD, N.getValueType(), N,
1696 getIntPtrConstant(Offset));
1698 Ty = StTy->getElementType(Field);
1700 Ty = cast<SequentialType>(Ty)->getElementType();
1702 // If this is a constant subscript, handle it quickly.
1703 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
1704 if (CI->getZExtValue() == 0) continue;
1706 TD->getTypeSize(Ty)*cast<ConstantInt>(CI)->getZExtValue();
1707 N = DAG.getNode(ISD::ADD, N.getValueType(), N, getIntPtrConstant(Offs));
1711 // N = N + Idx * ElementSize;
1712 uint64_t ElementSize = TD->getTypeSize(Ty);
1713 SDOperand IdxN = getValue(Idx);
1715 // If the index is smaller or larger than intptr_t, truncate or extend
1717 if (IdxN.getValueType() < N.getValueType()) {
1718 IdxN = DAG.getNode(ISD::SIGN_EXTEND, N.getValueType(), IdxN);
1719 } else if (IdxN.getValueType() > N.getValueType())
1720 IdxN = DAG.getNode(ISD::TRUNCATE, N.getValueType(), IdxN);
1722 // If this is a multiply by a power of two, turn it into a shl
1723 // immediately. This is a very common case.
1724 if (isPowerOf2_64(ElementSize)) {
1725 unsigned Amt = Log2_64(ElementSize);
1726 IdxN = DAG.getNode(ISD::SHL, N.getValueType(), IdxN,
1727 DAG.getConstant(Amt, TLI.getShiftAmountTy()));
1728 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1732 SDOperand Scale = getIntPtrConstant(ElementSize);
1733 IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
1734 N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
1740 void SelectionDAGLowering::visitAlloca(AllocaInst &I) {
1741 // If this is a fixed sized alloca in the entry block of the function,
1742 // allocate it statically on the stack.
1743 if (FuncInfo.StaticAllocaMap.count(&I))
1744 return; // getValue will auto-populate this.
1746 const Type *Ty = I.getAllocatedType();
1747 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
1748 unsigned Align = std::max((unsigned)TLI.getTargetData()->getTypeAlignment(Ty),
1751 SDOperand AllocSize = getValue(I.getArraySize());
1752 MVT::ValueType IntPtr = TLI.getPointerTy();
1753 if (IntPtr < AllocSize.getValueType())
1754 AllocSize = DAG.getNode(ISD::TRUNCATE, IntPtr, AllocSize);
1755 else if (IntPtr > AllocSize.getValueType())
1756 AllocSize = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, AllocSize);
1758 AllocSize = DAG.getNode(ISD::MUL, IntPtr, AllocSize,
1759 getIntPtrConstant(TySize));
1761 // Handle alignment. If the requested alignment is less than or equal to the
1762 // stack alignment, ignore it and round the size of the allocation up to the
1763 // stack alignment size. If the size is greater than the stack alignment, we
1764 // note this in the DYNAMIC_STACKALLOC node.
1765 unsigned StackAlign =
1766 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1767 if (Align <= StackAlign) {
1769 // Add SA-1 to the size.
1770 AllocSize = DAG.getNode(ISD::ADD, AllocSize.getValueType(), AllocSize,
1771 getIntPtrConstant(StackAlign-1));
1772 // Mask out the low bits for alignment purposes.
1773 AllocSize = DAG.getNode(ISD::AND, AllocSize.getValueType(), AllocSize,
1774 getIntPtrConstant(~(uint64_t)(StackAlign-1)));
1777 SDOperand Ops[] = { getRoot(), AllocSize, getIntPtrConstant(Align) };
1778 const MVT::ValueType *VTs = DAG.getNodeValueTypes(AllocSize.getValueType(),
1780 SDOperand DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, 2, Ops, 3);
1781 DAG.setRoot(setValue(&I, DSA).getValue(1));
1783 // Inform the Frame Information that we have just allocated a variable-sized
1785 CurMBB->getParent()->getFrameInfo()->CreateVariableSizedObject();
1788 void SelectionDAGLowering::visitLoad(LoadInst &I) {
1789 SDOperand Ptr = getValue(I.getOperand(0));
1795 // Do not serialize non-volatile loads against each other.
1796 Root = DAG.getRoot();
1799 setValue(&I, getLoadFrom(I.getType(), Ptr, I.getOperand(0),
1800 Root, I.isVolatile()));
1803 SDOperand SelectionDAGLowering::getLoadFrom(const Type *Ty, SDOperand Ptr,
1804 const Value *SV, SDOperand Root,
1807 if (const PackedType *PTy = dyn_cast<PackedType>(Ty)) {
1808 MVT::ValueType PVT = TLI.getValueType(PTy->getElementType());
1809 L = DAG.getVecLoad(PTy->getNumElements(), PVT, Root, Ptr,
1810 DAG.getSrcValue(SV));
1812 L = DAG.getLoad(TLI.getValueType(Ty), Root, Ptr, SV, 0, isVolatile);
1816 DAG.setRoot(L.getValue(1));
1818 PendingLoads.push_back(L.getValue(1));
1824 void SelectionDAGLowering::visitStore(StoreInst &I) {
1825 Value *SrcV = I.getOperand(0);
1826 SDOperand Src = getValue(SrcV);
1827 SDOperand Ptr = getValue(I.getOperand(1));
1828 DAG.setRoot(DAG.getStore(getRoot(), Src, Ptr, I.getOperand(1), 0,
1832 /// IntrinsicCannotAccessMemory - Return true if the specified intrinsic cannot
1833 /// access memory and has no other side effects at all.
1834 static bool IntrinsicCannotAccessMemory(unsigned IntrinsicID) {
1835 #define GET_NO_MEMORY_INTRINSICS
1836 #include "llvm/Intrinsics.gen"
1837 #undef GET_NO_MEMORY_INTRINSICS
1841 // IntrinsicOnlyReadsMemory - Return true if the specified intrinsic doesn't
1842 // have any side-effects or if it only reads memory.
1843 static bool IntrinsicOnlyReadsMemory(unsigned IntrinsicID) {
1844 #define GET_SIDE_EFFECT_INFO
1845 #include "llvm/Intrinsics.gen"
1846 #undef GET_SIDE_EFFECT_INFO
1850 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
1852 void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I,
1853 unsigned Intrinsic) {
1854 bool HasChain = !IntrinsicCannotAccessMemory(Intrinsic);
1855 bool OnlyLoad = HasChain && IntrinsicOnlyReadsMemory(Intrinsic);
1857 // Build the operand list.
1858 SmallVector<SDOperand, 8> Ops;
1859 if (HasChain) { // If this intrinsic has side-effects, chainify it.
1861 // We don't need to serialize loads against other loads.
1862 Ops.push_back(DAG.getRoot());
1864 Ops.push_back(getRoot());
1868 // Add the intrinsic ID as an integer operand.
1869 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
1871 // Add all operands of the call to the operand list.
1872 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
1873 SDOperand Op = getValue(I.getOperand(i));
1875 // If this is a vector type, force it to the right packed type.
1876 if (Op.getValueType() == MVT::Vector) {
1877 const PackedType *OpTy = cast<PackedType>(I.getOperand(i)->getType());
1878 MVT::ValueType EltVT = TLI.getValueType(OpTy->getElementType());
1880 MVT::ValueType VVT = MVT::getVectorType(EltVT, OpTy->getNumElements());
1881 assert(VVT != MVT::Other && "Intrinsic uses a non-legal type?");
1882 Op = DAG.getNode(ISD::VBIT_CONVERT, VVT, Op);
1885 assert(TLI.isTypeLegal(Op.getValueType()) &&
1886 "Intrinsic uses a non-legal type?");
1890 std::vector<MVT::ValueType> VTs;
1891 if (I.getType() != Type::VoidTy) {
1892 MVT::ValueType VT = TLI.getValueType(I.getType());
1893 if (VT == MVT::Vector) {
1894 const PackedType *DestTy = cast<PackedType>(I.getType());
1895 MVT::ValueType EltVT = TLI.getValueType(DestTy->getElementType());
1897 VT = MVT::getVectorType(EltVT, DestTy->getNumElements());
1898 assert(VT != MVT::Other && "Intrinsic uses a non-legal type?");
1901 assert(TLI.isTypeLegal(VT) && "Intrinsic uses a non-legal type?");
1905 VTs.push_back(MVT::Other);
1907 const MVT::ValueType *VTList = DAG.getNodeValueTypes(VTs);
1912 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VTList, VTs.size(),
1913 &Ops[0], Ops.size());
1914 else if (I.getType() != Type::VoidTy)
1915 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, VTList, VTs.size(),
1916 &Ops[0], Ops.size());
1918 Result = DAG.getNode(ISD::INTRINSIC_VOID, VTList, VTs.size(),
1919 &Ops[0], Ops.size());
1922 SDOperand Chain = Result.getValue(Result.Val->getNumValues()-1);
1924 PendingLoads.push_back(Chain);
1928 if (I.getType() != Type::VoidTy) {
1929 if (const PackedType *PTy = dyn_cast<PackedType>(I.getType())) {
1930 MVT::ValueType EVT = TLI.getValueType(PTy->getElementType());
1931 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
1932 DAG.getConstant(PTy->getNumElements(), MVT::i32),
1933 DAG.getValueType(EVT));
1935 setValue(&I, Result);
1939 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
1940 /// we want to emit this as a call to a named external function, return the name
1941 /// otherwise lower it and return null.
1943 SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
1944 switch (Intrinsic) {
1946 // By default, turn this into a target intrinsic node.
1947 visitTargetIntrinsic(I, Intrinsic);
1949 case Intrinsic::vastart: visitVAStart(I); return 0;
1950 case Intrinsic::vaend: visitVAEnd(I); return 0;
1951 case Intrinsic::vacopy: visitVACopy(I); return 0;
1952 case Intrinsic::returnaddress: visitFrameReturnAddress(I, false); return 0;
1953 case Intrinsic::frameaddress: visitFrameReturnAddress(I, true); return 0;
1954 case Intrinsic::setjmp:
1955 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
1957 case Intrinsic::longjmp:
1958 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
1960 case Intrinsic::memcpy_i32:
1961 case Intrinsic::memcpy_i64:
1962 visitMemIntrinsic(I, ISD::MEMCPY);
1964 case Intrinsic::memset_i32:
1965 case Intrinsic::memset_i64:
1966 visitMemIntrinsic(I, ISD::MEMSET);
1968 case Intrinsic::memmove_i32:
1969 case Intrinsic::memmove_i64:
1970 visitMemIntrinsic(I, ISD::MEMMOVE);
1973 case Intrinsic::dbg_stoppoint: {
1974 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1975 DbgStopPointInst &SPI = cast<DbgStopPointInst>(I);
1976 if (DebugInfo && SPI.getContext() && DebugInfo->Verify(SPI.getContext())) {
1980 Ops[1] = getValue(SPI.getLineValue());
1981 Ops[2] = getValue(SPI.getColumnValue());
1983 DebugInfoDesc *DD = DebugInfo->getDescFor(SPI.getContext());
1984 assert(DD && "Not a debug information descriptor");
1985 CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
1987 Ops[3] = DAG.getString(CompileUnit->getFileName());
1988 Ops[4] = DAG.getString(CompileUnit->getDirectory());
1990 DAG.setRoot(DAG.getNode(ISD::LOCATION, MVT::Other, Ops, 5));
1995 case Intrinsic::dbg_region_start: {
1996 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
1997 DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
1998 if (DebugInfo && RSI.getContext() && DebugInfo->Verify(RSI.getContext())) {
1999 unsigned LabelID = DebugInfo->RecordRegionStart(RSI.getContext());
2000 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, getRoot(),
2001 DAG.getConstant(LabelID, MVT::i32)));
2006 case Intrinsic::dbg_region_end: {
2007 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
2008 DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
2009 if (DebugInfo && REI.getContext() && DebugInfo->Verify(REI.getContext())) {
2010 unsigned LabelID = DebugInfo->RecordRegionEnd(REI.getContext());
2011 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
2012 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2017 case Intrinsic::dbg_func_start: {
2018 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
2019 DbgFuncStartInst &FSI = cast<DbgFuncStartInst>(I);
2020 if (DebugInfo && FSI.getSubprogram() &&
2021 DebugInfo->Verify(FSI.getSubprogram())) {
2022 unsigned LabelID = DebugInfo->RecordRegionStart(FSI.getSubprogram());
2023 DAG.setRoot(DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,
2024 getRoot(), DAG.getConstant(LabelID, MVT::i32)));
2029 case Intrinsic::dbg_declare: {
2030 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
2031 DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
2032 if (DebugInfo && DI.getVariable() && DebugInfo->Verify(DI.getVariable())) {
2033 SDOperand AddressOp = getValue(DI.getAddress());
2034 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(AddressOp))
2035 DebugInfo->RecordVariable(DI.getVariable(), FI->getIndex());
2041 case Intrinsic::isunordered_f32:
2042 case Intrinsic::isunordered_f64:
2043 setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
2044 getValue(I.getOperand(2)), ISD::SETUO));
2047 case Intrinsic::sqrt_f32:
2048 case Intrinsic::sqrt_f64:
2049 setValue(&I, DAG.getNode(ISD::FSQRT,
2050 getValue(I.getOperand(1)).getValueType(),
2051 getValue(I.getOperand(1))));
2053 case Intrinsic::powi_f32:
2054 case Intrinsic::powi_f64:
2055 setValue(&I, DAG.getNode(ISD::FPOWI,
2056 getValue(I.getOperand(1)).getValueType(),
2057 getValue(I.getOperand(1)),
2058 getValue(I.getOperand(2))));
2060 case Intrinsic::pcmarker: {
2061 SDOperand Tmp = getValue(I.getOperand(1));
2062 DAG.setRoot(DAG.getNode(ISD::PCMARKER, MVT::Other, getRoot(), Tmp));
2065 case Intrinsic::readcyclecounter: {
2066 SDOperand Op = getRoot();
2067 SDOperand Tmp = DAG.getNode(ISD::READCYCLECOUNTER,
2068 DAG.getNodeValueTypes(MVT::i64, MVT::Other), 2,
2071 DAG.setRoot(Tmp.getValue(1));
2074 case Intrinsic::bswap_i16:
2075 case Intrinsic::bswap_i32:
2076 case Intrinsic::bswap_i64:
2077 setValue(&I, DAG.getNode(ISD::BSWAP,
2078 getValue(I.getOperand(1)).getValueType(),
2079 getValue(I.getOperand(1))));
2081 case Intrinsic::cttz_i8:
2082 case Intrinsic::cttz_i16:
2083 case Intrinsic::cttz_i32:
2084 case Intrinsic::cttz_i64:
2085 setValue(&I, DAG.getNode(ISD::CTTZ,
2086 getValue(I.getOperand(1)).getValueType(),
2087 getValue(I.getOperand(1))));
2089 case Intrinsic::ctlz_i8:
2090 case Intrinsic::ctlz_i16:
2091 case Intrinsic::ctlz_i32:
2092 case Intrinsic::ctlz_i64:
2093 setValue(&I, DAG.getNode(ISD::CTLZ,
2094 getValue(I.getOperand(1)).getValueType(),
2095 getValue(I.getOperand(1))));
2097 case Intrinsic::ctpop_i8:
2098 case Intrinsic::ctpop_i16:
2099 case Intrinsic::ctpop_i32:
2100 case Intrinsic::ctpop_i64:
2101 setValue(&I, DAG.getNode(ISD::CTPOP,
2102 getValue(I.getOperand(1)).getValueType(),
2103 getValue(I.getOperand(1))));
2105 case Intrinsic::stacksave: {
2106 SDOperand Op = getRoot();
2107 SDOperand Tmp = DAG.getNode(ISD::STACKSAVE,
2108 DAG.getNodeValueTypes(TLI.getPointerTy(), MVT::Other), 2, &Op, 1);
2110 DAG.setRoot(Tmp.getValue(1));
2113 case Intrinsic::stackrestore: {
2114 SDOperand Tmp = getValue(I.getOperand(1));
2115 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, MVT::Other, getRoot(), Tmp));
2118 case Intrinsic::prefetch:
2119 // FIXME: Currently discarding prefetches.
2125 void SelectionDAGLowering::visitCall(CallInst &I) {
2126 const char *RenameFn = 0;
2127 if (Function *F = I.getCalledFunction()) {
2128 if (F->isExternal())
2129 if (unsigned IID = F->getIntrinsicID()) {
2130 RenameFn = visitIntrinsicCall(I, IID);
2133 } else { // Not an LLVM intrinsic.
2134 const std::string &Name = F->getName();
2135 if (Name[0] == 'c' && (Name == "copysign" || Name == "copysignf")) {
2136 if (I.getNumOperands() == 3 && // Basic sanity checks.
2137 I.getOperand(1)->getType()->isFloatingPoint() &&
2138 I.getType() == I.getOperand(1)->getType() &&
2139 I.getType() == I.getOperand(2)->getType()) {
2140 SDOperand LHS = getValue(I.getOperand(1));
2141 SDOperand RHS = getValue(I.getOperand(2));
2142 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, LHS.getValueType(),
2146 } else if (Name[0] == 'f' && (Name == "fabs" || Name == "fabsf")) {
2147 if (I.getNumOperands() == 2 && // Basic sanity checks.
2148 I.getOperand(1)->getType()->isFloatingPoint() &&
2149 I.getType() == I.getOperand(1)->getType()) {
2150 SDOperand Tmp = getValue(I.getOperand(1));
2151 setValue(&I, DAG.getNode(ISD::FABS, Tmp.getValueType(), Tmp));
2154 } else if (Name[0] == 's' && (Name == "sin" || Name == "sinf")) {
2155 if (I.getNumOperands() == 2 && // Basic sanity checks.
2156 I.getOperand(1)->getType()->isFloatingPoint() &&
2157 I.getType() == I.getOperand(1)->getType()) {
2158 SDOperand Tmp = getValue(I.getOperand(1));
2159 setValue(&I, DAG.getNode(ISD::FSIN, Tmp.getValueType(), Tmp));
2162 } else if (Name[0] == 'c' && (Name == "cos" || Name == "cosf")) {
2163 if (I.getNumOperands() == 2 && // Basic sanity checks.
2164 I.getOperand(1)->getType()->isFloatingPoint() &&
2165 I.getType() == I.getOperand(1)->getType()) {
2166 SDOperand Tmp = getValue(I.getOperand(1));
2167 setValue(&I, DAG.getNode(ISD::FCOS, Tmp.getValueType(), Tmp));
2172 } else if (isa<InlineAsm>(I.getOperand(0))) {
2177 const PointerType *PT = cast<PointerType>(I.getCalledValue()->getType());
2178 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2182 Callee = getValue(I.getOperand(0));
2184 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
2185 TargetLowering::ArgListTy Args;
2186 TargetLowering::ArgListEntry Entry;
2187 Args.reserve(I.getNumOperands());
2188 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i) {
2189 Value *Arg = I.getOperand(i);
2190 SDOperand ArgNode = getValue(Arg);
2191 Entry.Node = ArgNode; Entry.Ty = Arg->getType();
2192 Entry.isSigned = FTy->paramHasAttr(i, FunctionType::SExtAttribute);
2193 Args.push_back(Entry);
2196 std::pair<SDOperand,SDOperand> Result =
2197 TLI.LowerCallTo(getRoot(), I.getType(),
2198 FTy->paramHasAttr(0,FunctionType::SExtAttribute),
2199 FTy->isVarArg(), I.getCallingConv(), I.isTailCall(),
2201 if (I.getType() != Type::VoidTy)
2202 setValue(&I, Result.first);
2203 DAG.setRoot(Result.second);
2206 SDOperand RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
2207 SDOperand &Chain, SDOperand &Flag)const{
2208 SDOperand Val = DAG.getCopyFromReg(Chain, Regs[0], RegVT, Flag);
2209 Chain = Val.getValue(1);
2210 Flag = Val.getValue(2);
2212 // If the result was expanded, copy from the top part.
2213 if (Regs.size() > 1) {
2214 assert(Regs.size() == 2 &&
2215 "Cannot expand to more than 2 elts yet!");
2216 SDOperand Hi = DAG.getCopyFromReg(Chain, Regs[1], RegVT, Flag);
2217 Chain = Hi.getValue(1);
2218 Flag = Hi.getValue(2);
2219 if (DAG.getTargetLoweringInfo().isLittleEndian())
2220 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Val, Hi);
2222 return DAG.getNode(ISD::BUILD_PAIR, ValueVT, Hi, Val);
2225 // Otherwise, if the return value was promoted or extended, truncate it to the
2226 // appropriate type.
2227 if (RegVT == ValueVT)
2230 if (MVT::isInteger(RegVT)) {
2231 if (ValueVT < RegVT)
2232 return DAG.getNode(ISD::TRUNCATE, ValueVT, Val);
2234 return DAG.getNode(ISD::ANY_EXTEND, ValueVT, Val);
2236 return DAG.getNode(ISD::FP_ROUND, ValueVT, Val);
2240 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
2241 /// specified value into the registers specified by this object. This uses
2242 /// Chain/Flag as the input and updates them for the output Chain/Flag.
2243 void RegsForValue::getCopyToRegs(SDOperand Val, SelectionDAG &DAG,
2244 SDOperand &Chain, SDOperand &Flag,
2245 MVT::ValueType PtrVT) const {
2246 if (Regs.size() == 1) {
2247 // If there is a single register and the types differ, this must be
2249 if (RegVT != ValueVT) {
2250 if (MVT::isInteger(RegVT)) {
2251 if (RegVT < ValueVT)
2252 Val = DAG.getNode(ISD::TRUNCATE, RegVT, Val);
2254 Val = DAG.getNode(ISD::ANY_EXTEND, RegVT, Val);
2256 Val = DAG.getNode(ISD::FP_EXTEND, RegVT, Val);
2258 Chain = DAG.getCopyToReg(Chain, Regs[0], Val, Flag);
2259 Flag = Chain.getValue(1);
2261 std::vector<unsigned> R(Regs);
2262 if (!DAG.getTargetLoweringInfo().isLittleEndian())
2263 std::reverse(R.begin(), R.end());
2265 for (unsigned i = 0, e = R.size(); i != e; ++i) {
2266 SDOperand Part = DAG.getNode(ISD::EXTRACT_ELEMENT, RegVT, Val,
2267 DAG.getConstant(i, PtrVT));
2268 Chain = DAG.getCopyToReg(Chain, R[i], Part, Flag);
2269 Flag = Chain.getValue(1);
2274 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
2275 /// operand list. This adds the code marker and includes the number of
2276 /// values added into it.
2277 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
2278 std::vector<SDOperand> &Ops) const {
2279 Ops.push_back(DAG.getConstant(Code | (Regs.size() << 3), MVT::i32));
2280 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
2281 Ops.push_back(DAG.getRegister(Regs[i], RegVT));
2284 /// isAllocatableRegister - If the specified register is safe to allocate,
2285 /// i.e. it isn't a stack pointer or some other special register, return the
2286 /// register class for the register. Otherwise, return null.
2287 static const TargetRegisterClass *
2288 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
2289 const TargetLowering &TLI, const MRegisterInfo *MRI) {
2290 MVT::ValueType FoundVT = MVT::Other;
2291 const TargetRegisterClass *FoundRC = 0;
2292 for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(),
2293 E = MRI->regclass_end(); RCI != E; ++RCI) {
2294 MVT::ValueType ThisVT = MVT::Other;
2296 const TargetRegisterClass *RC = *RCI;
2297 // If none of the the value types for this register class are valid, we
2298 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2299 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
2301 if (TLI.isTypeLegal(*I)) {
2302 // If we have already found this register in a different register class,
2303 // choose the one with the largest VT specified. For example, on
2304 // PowerPC, we favor f64 register classes over f32.
2305 if (FoundVT == MVT::Other ||
2306 MVT::getSizeInBits(FoundVT) < MVT::getSizeInBits(*I)) {
2313 if (ThisVT == MVT::Other) continue;
2315 // NOTE: This isn't ideal. In particular, this might allocate the
2316 // frame pointer in functions that need it (due to them not being taken
2317 // out of allocation, because a variable sized allocation hasn't been seen
2318 // yet). This is a slight code pessimization, but should still work.
2319 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
2320 E = RC->allocation_order_end(MF); I != E; ++I)
2322 // We found a matching register class. Keep looking at others in case
2323 // we find one with larger registers that this physreg is also in.
2332 RegsForValue SelectionDAGLowering::
2333 GetRegistersForValue(const std::string &ConstrCode,
2334 MVT::ValueType VT, bool isOutReg, bool isInReg,
2335 std::set<unsigned> &OutputRegs,
2336 std::set<unsigned> &InputRegs) {
2337 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
2338 TLI.getRegForInlineAsmConstraint(ConstrCode, VT);
2339 std::vector<unsigned> Regs;
2341 unsigned NumRegs = VT != MVT::Other ? TLI.getNumElements(VT) : 1;
2342 MVT::ValueType RegVT;
2343 MVT::ValueType ValueVT = VT;
2345 // If this is a constraint for a specific physical register, like {r17},
2347 if (PhysReg.first) {
2348 if (VT == MVT::Other)
2349 ValueVT = *PhysReg.second->vt_begin();
2351 // Get the actual register value type. This is important, because the user
2352 // may have asked for (e.g.) the AX register in i32 type. We need to
2353 // remember that AX is actually i16 to get the right extension.
2354 RegVT = *PhysReg.second->vt_begin();
2356 // This is a explicit reference to a physical register.
2357 Regs.push_back(PhysReg.first);
2359 // If this is an expanded reference, add the rest of the regs to Regs.
2361 TargetRegisterClass::iterator I = PhysReg.second->begin();
2362 TargetRegisterClass::iterator E = PhysReg.second->end();
2363 for (; *I != PhysReg.first; ++I)
2364 assert(I != E && "Didn't find reg!");
2366 // Already added the first reg.
2368 for (; NumRegs; --NumRegs, ++I) {
2369 assert(I != E && "Ran out of registers to allocate!");
2373 return RegsForValue(Regs, RegVT, ValueVT);
2376 // Otherwise, if this was a reference to an LLVM register class, create vregs
2377 // for this reference.
2378 std::vector<unsigned> RegClassRegs;
2379 if (PhysReg.second) {
2380 // If this is an early clobber or tied register, our regalloc doesn't know
2381 // how to maintain the constraint. If it isn't, go ahead and create vreg
2382 // and let the regalloc do the right thing.
2383 if (!isOutReg || !isInReg) {
2384 if (VT == MVT::Other)
2385 ValueVT = *PhysReg.second->vt_begin();
2386 RegVT = *PhysReg.second->vt_begin();
2388 // Create the appropriate number of virtual registers.
2389 SSARegMap *RegMap = DAG.getMachineFunction().getSSARegMap();
2390 for (; NumRegs; --NumRegs)
2391 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second));
2393 return RegsForValue(Regs, RegVT, ValueVT);
2396 // Otherwise, we can't allocate it. Let the code below figure out how to
2397 // maintain these constraints.
2398 RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
2401 // This is a reference to a register class that doesn't directly correspond
2402 // to an LLVM register class. Allocate NumRegs consecutive, available,
2403 // registers from the class.
2404 RegClassRegs = TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
2407 const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
2408 MachineFunction &MF = *CurMBB->getParent();
2409 unsigned NumAllocated = 0;
2410 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
2411 unsigned Reg = RegClassRegs[i];
2412 // See if this register is available.
2413 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
2414 (isInReg && InputRegs.count(Reg))) { // Already used.
2415 // Make sure we find consecutive registers.
2420 // Check to see if this register is allocatable (i.e. don't give out the
2422 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
2424 // Make sure we find consecutive registers.
2429 // Okay, this register is good, we can use it.
2432 // If we allocated enough consecutive
2433 if (NumAllocated == NumRegs) {
2434 unsigned RegStart = (i-NumAllocated)+1;
2435 unsigned RegEnd = i+1;
2436 // Mark all of the allocated registers used.
2437 for (unsigned i = RegStart; i != RegEnd; ++i) {
2438 unsigned Reg = RegClassRegs[i];
2439 Regs.push_back(Reg);
2440 if (isOutReg) OutputRegs.insert(Reg); // Mark reg used.
2441 if (isInReg) InputRegs.insert(Reg); // Mark reg used.
2444 return RegsForValue(Regs, *RC->vt_begin(), VT);
2448 // Otherwise, we couldn't allocate enough registers for this.
2449 return RegsForValue();
2453 /// visitInlineAsm - Handle a call to an InlineAsm object.
2455 void SelectionDAGLowering::visitInlineAsm(CallInst &I) {
2456 InlineAsm *IA = cast<InlineAsm>(I.getOperand(0));
2458 SDOperand AsmStr = DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
2461 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
2462 std::vector<MVT::ValueType> ConstraintVTs;
2464 /// AsmNodeOperands - A list of pairs. The first element is a register, the
2465 /// second is a bitfield where bit #0 is set if it is a use and bit #1 is set
2466 /// if it is a def of that register.
2467 std::vector<SDOperand> AsmNodeOperands;
2468 AsmNodeOperands.push_back(SDOperand()); // reserve space for input chain
2469 AsmNodeOperands.push_back(AsmStr);
2471 SDOperand Chain = getRoot();
2474 // We fully assign registers here at isel time. This is not optimal, but
2475 // should work. For register classes that correspond to LLVM classes, we
2476 // could let the LLVM RA do its thing, but we currently don't. Do a prepass
2477 // over the constraints, collecting fixed registers that we know we can't use.
2478 std::set<unsigned> OutputRegs, InputRegs;
2480 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2481 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2482 std::string &ConstraintCode = Constraints[i].Codes[0];
2484 MVT::ValueType OpVT;
2486 // Compute the value type for each operand and add it to ConstraintVTs.
2487 switch (Constraints[i].Type) {
2488 case InlineAsm::isOutput:
2489 if (!Constraints[i].isIndirectOutput) {
2490 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2491 OpVT = TLI.getValueType(I.getType());
2493 const Type *OpTy = I.getOperand(OpNum)->getType();
2494 OpVT = TLI.getValueType(cast<PointerType>(OpTy)->getElementType());
2495 OpNum++; // Consumes a call operand.
2498 case InlineAsm::isInput:
2499 OpVT = TLI.getValueType(I.getOperand(OpNum)->getType());
2500 OpNum++; // Consumes a call operand.
2502 case InlineAsm::isClobber:
2507 ConstraintVTs.push_back(OpVT);
2509 if (TLI.getRegForInlineAsmConstraint(ConstraintCode, OpVT).first == 0)
2510 continue; // Not assigned a fixed reg.
2512 // Build a list of regs that this operand uses. This always has a single
2513 // element for promoted/expanded operands.
2514 RegsForValue Regs = GetRegistersForValue(ConstraintCode, OpVT,
2516 OutputRegs, InputRegs);
2518 switch (Constraints[i].Type) {
2519 case InlineAsm::isOutput:
2520 // We can't assign any other output to this register.
2521 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2522 // If this is an early-clobber output, it cannot be assigned to the same
2523 // value as the input reg.
2524 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2525 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2527 case InlineAsm::isInput:
2528 // We can't assign any other input to this register.
2529 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2531 case InlineAsm::isClobber:
2532 // Clobbered regs cannot be used as inputs or outputs.
2533 InputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2534 OutputRegs.insert(Regs.Regs.begin(), Regs.Regs.end());
2539 // Loop over all of the inputs, copying the operand values into the
2540 // appropriate registers and processing the output regs.
2541 RegsForValue RetValRegs;
2542 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
2545 for (unsigned i = 0, e = Constraints.size(); i != e; ++i) {
2546 assert(Constraints[i].Codes.size() == 1 && "Only handles one code so far!");
2547 std::string &ConstraintCode = Constraints[i].Codes[0];
2549 switch (Constraints[i].Type) {
2550 case InlineAsm::isOutput: {
2551 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2552 if (ConstraintCode.size() == 1) // not a physreg name.
2553 CTy = TLI.getConstraintType(ConstraintCode[0]);
2555 if (CTy == TargetLowering::C_Memory) {
2557 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2559 // Check that the operand (the address to store to) isn't a float.
2560 if (!MVT::isInteger(InOperandVal.getValueType()))
2561 assert(0 && "MATCH FAIL!");
2563 if (!Constraints[i].isIndirectOutput)
2564 assert(0 && "MATCH FAIL!");
2566 OpNum++; // Consumes a call operand.
2568 // Extend/truncate to the right pointer type if needed.
2569 MVT::ValueType PtrType = TLI.getPointerTy();
2570 if (InOperandVal.getValueType() < PtrType)
2571 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2572 else if (InOperandVal.getValueType() > PtrType)
2573 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2575 // Add information to the INLINEASM node to know about this output.
2576 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2577 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2578 AsmNodeOperands.push_back(InOperandVal);
2582 // Otherwise, this is a register output.
2583 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2585 // If this is an early-clobber output, or if there is an input
2586 // constraint that matches this, we need to reserve the input register
2587 // so no other inputs allocate to it.
2588 bool UsesInputRegister = false;
2589 if (Constraints[i].isEarlyClobber || Constraints[i].hasMatchingInput)
2590 UsesInputRegister = true;
2592 // Copy the output from the appropriate register. Find a register that
2595 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2596 true, UsesInputRegister,
2597 OutputRegs, InputRegs);
2598 if (Regs.Regs.empty()) {
2599 cerr << "Couldn't allocate output reg for contraint '"
2600 << ConstraintCode << "'!\n";
2604 if (!Constraints[i].isIndirectOutput) {
2605 assert(RetValRegs.Regs.empty() &&
2606 "Cannot have multiple output constraints yet!");
2607 assert(I.getType() != Type::VoidTy && "Bad inline asm!");
2610 IndirectStoresToEmit.push_back(std::make_pair(Regs,
2611 I.getOperand(OpNum)));
2612 OpNum++; // Consumes a call operand.
2615 // Add information to the INLINEASM node to know that this register is
2617 Regs.AddInlineAsmOperands(2 /*REGDEF*/, DAG, AsmNodeOperands);
2620 case InlineAsm::isInput: {
2621 SDOperand InOperandVal = getValue(I.getOperand(OpNum));
2622 OpNum++; // Consumes a call operand.
2624 if (isdigit(ConstraintCode[0])) { // Matching constraint?
2625 // If this is required to match an output register we have already set,
2626 // just use its register.
2627 unsigned OperandNo = atoi(ConstraintCode.c_str());
2629 // Scan until we find the definition we already emitted of this operand.
2630 // When we find it, create a RegsForValue operand.
2631 unsigned CurOp = 2; // The first operand.
2632 for (; OperandNo; --OperandNo) {
2633 // Advance to the next operand.
2635 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2636 assert(((NumOps & 7) == 2 /*REGDEF*/ ||
2637 (NumOps & 7) == 4 /*MEM*/) &&
2638 "Skipped past definitions?");
2639 CurOp += (NumOps>>3)+1;
2643 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getValue();
2644 assert((NumOps & 7) == 2 /*REGDEF*/ &&
2645 "Skipped past definitions?");
2647 // Add NumOps>>3 registers to MatchedRegs.
2648 RegsForValue MatchedRegs;
2649 MatchedRegs.ValueVT = InOperandVal.getValueType();
2650 MatchedRegs.RegVT = AsmNodeOperands[CurOp+1].getValueType();
2651 for (unsigned i = 0, e = NumOps>>3; i != e; ++i) {
2652 unsigned Reg=cast<RegisterSDNode>(AsmNodeOperands[++CurOp])->getReg();
2653 MatchedRegs.Regs.push_back(Reg);
2656 // Use the produced MatchedRegs object to
2657 MatchedRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag,
2658 TLI.getPointerTy());
2659 MatchedRegs.AddInlineAsmOperands(1 /*REGUSE*/, DAG, AsmNodeOperands);
2663 TargetLowering::ConstraintType CTy = TargetLowering::C_RegisterClass;
2664 if (ConstraintCode.size() == 1) // not a physreg name.
2665 CTy = TLI.getConstraintType(ConstraintCode[0]);
2667 if (CTy == TargetLowering::C_Other) {
2668 InOperandVal = TLI.isOperandValidForConstraint(InOperandVal,
2669 ConstraintCode[0], DAG);
2670 if (!InOperandVal.Val) {
2671 cerr << "Invalid operand for inline asm constraint '"
2672 << ConstraintCode << "'!\n";
2676 // Add information to the INLINEASM node to know about this input.
2677 unsigned ResOpType = 3 /*IMM*/ | (1 << 3);
2678 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2679 AsmNodeOperands.push_back(InOperandVal);
2681 } else if (CTy == TargetLowering::C_Memory) {
2684 // Check that the operand isn't a float.
2685 if (!MVT::isInteger(InOperandVal.getValueType()))
2686 assert(0 && "MATCH FAIL!");
2688 // Extend/truncate to the right pointer type if needed.
2689 MVT::ValueType PtrType = TLI.getPointerTy();
2690 if (InOperandVal.getValueType() < PtrType)
2691 InOperandVal = DAG.getNode(ISD::ZERO_EXTEND, PtrType, InOperandVal);
2692 else if (InOperandVal.getValueType() > PtrType)
2693 InOperandVal = DAG.getNode(ISD::TRUNCATE, PtrType, InOperandVal);
2695 // Add information to the INLINEASM node to know about this input.
2696 unsigned ResOpType = 4/*MEM*/ | (1 << 3);
2697 AsmNodeOperands.push_back(DAG.getConstant(ResOpType, MVT::i32));
2698 AsmNodeOperands.push_back(InOperandVal);
2702 assert(CTy == TargetLowering::C_RegisterClass && "Unknown op type!");
2704 // Copy the input into the appropriate registers.
2705 RegsForValue InRegs =
2706 GetRegistersForValue(ConstraintCode, ConstraintVTs[i],
2707 false, true, OutputRegs, InputRegs);
2708 // FIXME: should be match fail.
2709 assert(!InRegs.Regs.empty() && "Couldn't allocate input reg!");
2711 InRegs.getCopyToRegs(InOperandVal, DAG, Chain, Flag, TLI.getPointerTy());
2713 InRegs.AddInlineAsmOperands(1/*REGUSE*/, DAG, AsmNodeOperands);
2716 case InlineAsm::isClobber: {
2717 RegsForValue ClobberedRegs =
2718 GetRegistersForValue(ConstraintCode, MVT::Other, false, false,
2719 OutputRegs, InputRegs);
2720 // Add the clobbered value to the operand list, so that the register
2721 // allocator is aware that the physreg got clobbered.
2722 if (!ClobberedRegs.Regs.empty())
2723 ClobberedRegs.AddInlineAsmOperands(2/*REGDEF*/, DAG, AsmNodeOperands);
2729 // Finish up input operands.
2730 AsmNodeOperands[0] = Chain;
2731 if (Flag.Val) AsmNodeOperands.push_back(Flag);
2733 Chain = DAG.getNode(ISD::INLINEASM,
2734 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 2,
2735 &AsmNodeOperands[0], AsmNodeOperands.size());
2736 Flag = Chain.getValue(1);
2738 // If this asm returns a register value, copy the result from that register
2739 // and set it as the value of the call.
2740 if (!RetValRegs.Regs.empty())
2741 setValue(&I, RetValRegs.getCopyFromRegs(DAG, Chain, Flag));
2743 std::vector<std::pair<SDOperand, Value*> > StoresToEmit;
2745 // Process indirect outputs, first output all of the flagged copies out of
2747 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
2748 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
2749 Value *Ptr = IndirectStoresToEmit[i].second;
2750 SDOperand OutVal = OutRegs.getCopyFromRegs(DAG, Chain, Flag);
2751 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
2754 // Emit the non-flagged stores from the physregs.
2755 SmallVector<SDOperand, 8> OutChains;
2756 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i)
2757 OutChains.push_back(DAG.getStore(Chain, StoresToEmit[i].first,
2758 getValue(StoresToEmit[i].second),
2759 StoresToEmit[i].second, 0));
2760 if (!OutChains.empty())
2761 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2762 &OutChains[0], OutChains.size());
2767 void SelectionDAGLowering::visitMalloc(MallocInst &I) {
2768 SDOperand Src = getValue(I.getOperand(0));
2770 MVT::ValueType IntPtr = TLI.getPointerTy();
2772 if (IntPtr < Src.getValueType())
2773 Src = DAG.getNode(ISD::TRUNCATE, IntPtr, Src);
2774 else if (IntPtr > Src.getValueType())
2775 Src = DAG.getNode(ISD::ZERO_EXTEND, IntPtr, Src);
2777 // Scale the source by the type size.
2778 uint64_t ElementSize = TD->getTypeSize(I.getType()->getElementType());
2779 Src = DAG.getNode(ISD::MUL, Src.getValueType(),
2780 Src, getIntPtrConstant(ElementSize));
2782 TargetLowering::ArgListTy Args;
2783 TargetLowering::ArgListEntry Entry;
2785 Entry.Ty = TLI.getTargetData()->getIntPtrType();
2786 Entry.isSigned = false;
2787 Args.push_back(Entry);
2789 std::pair<SDOperand,SDOperand> Result =
2790 TLI.LowerCallTo(getRoot(), I.getType(), false, false, CallingConv::C, true,
2791 DAG.getExternalSymbol("malloc", IntPtr),
2793 setValue(&I, Result.first); // Pointers always fit in registers
2794 DAG.setRoot(Result.second);
2797 void SelectionDAGLowering::visitFree(FreeInst &I) {
2798 TargetLowering::ArgListTy Args;
2799 TargetLowering::ArgListEntry Entry;
2800 Entry.Node = getValue(I.getOperand(0));
2801 Entry.Ty = TLI.getTargetData()->getIntPtrType();
2802 Entry.isSigned = false;
2803 Args.push_back(Entry);
2804 MVT::ValueType IntPtr = TLI.getPointerTy();
2805 std::pair<SDOperand,SDOperand> Result =
2806 TLI.LowerCallTo(getRoot(), Type::VoidTy, false, false, CallingConv::C, true,
2807 DAG.getExternalSymbol("free", IntPtr), Args, DAG);
2808 DAG.setRoot(Result.second);
2811 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
2812 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
2813 // instructions are special in various ways, which require special support to
2814 // insert. The specified MachineInstr is created but not inserted into any
2815 // basic blocks, and the scheduler passes ownership of it to this method.
2816 MachineBasicBlock *TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2817 MachineBasicBlock *MBB) {
2818 cerr << "If a target marks an instruction with "
2819 << "'usesCustomDAGSchedInserter', it must implement "
2820 << "TargetLowering::InsertAtEndOfBasicBlock!\n";
2825 void SelectionDAGLowering::visitVAStart(CallInst &I) {
2826 DAG.setRoot(DAG.getNode(ISD::VASTART, MVT::Other, getRoot(),
2827 getValue(I.getOperand(1)),
2828 DAG.getSrcValue(I.getOperand(1))));
2831 void SelectionDAGLowering::visitVAArg(VAArgInst &I) {
2832 SDOperand V = DAG.getVAArg(TLI.getValueType(I.getType()), getRoot(),
2833 getValue(I.getOperand(0)),
2834 DAG.getSrcValue(I.getOperand(0)));
2836 DAG.setRoot(V.getValue(1));
2839 void SelectionDAGLowering::visitVAEnd(CallInst &I) {
2840 DAG.setRoot(DAG.getNode(ISD::VAEND, MVT::Other, getRoot(),
2841 getValue(I.getOperand(1)),
2842 DAG.getSrcValue(I.getOperand(1))));
2845 void SelectionDAGLowering::visitVACopy(CallInst &I) {
2846 DAG.setRoot(DAG.getNode(ISD::VACOPY, MVT::Other, getRoot(),
2847 getValue(I.getOperand(1)),
2848 getValue(I.getOperand(2)),
2849 DAG.getSrcValue(I.getOperand(1)),
2850 DAG.getSrcValue(I.getOperand(2))));
2853 /// ExpandScalarFormalArgs - Recursively expand the formal_argument node, either
2854 /// bit_convert it or join a pair of them with a BUILD_PAIR when appropriate.
2855 static SDOperand ExpandScalarFormalArgs(MVT::ValueType VT, SDNode *Arg,
2856 unsigned &i, SelectionDAG &DAG,
2857 TargetLowering &TLI) {
2858 if (TLI.getTypeAction(VT) != TargetLowering::Expand)
2859 return SDOperand(Arg, i++);
2861 MVT::ValueType EVT = TLI.getTypeToTransformTo(VT);
2862 unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT);
2864 return DAG.getNode(ISD::BIT_CONVERT, VT,
2865 ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI));
2866 } else if (NumVals == 2) {
2867 SDOperand Lo = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI);
2868 SDOperand Hi = ExpandScalarFormalArgs(EVT, Arg, i, DAG, TLI);
2869 if (!TLI.isLittleEndian())
2871 return DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
2873 // Value scalarized into many values. Unimp for now.
2874 assert(0 && "Cannot expand i64 -> i16 yet!");
2879 /// TargetLowering::LowerArguments - This is the default LowerArguments
2880 /// implementation, which just inserts a FORMAL_ARGUMENTS node. FIXME: When all
2881 /// targets are migrated to using FORMAL_ARGUMENTS, this hook should be
2882 /// integrated into SDISel.
2883 std::vector<SDOperand>
2884 TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
2885 // Add CC# and isVararg as operands to the FORMAL_ARGUMENTS node.
2886 std::vector<SDOperand> Ops;
2887 Ops.push_back(DAG.getRoot());
2888 Ops.push_back(DAG.getConstant(F.getCallingConv(), getPointerTy()));
2889 Ops.push_back(DAG.getConstant(F.isVarArg(), getPointerTy()));
2891 // Add one result value for each formal argument.
2892 std::vector<MVT::ValueType> RetVals;
2893 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
2894 MVT::ValueType VT = getValueType(I->getType());
2896 switch (getTypeAction(VT)) {
2897 default: assert(0 && "Unknown type action!");
2899 RetVals.push_back(VT);
2902 RetVals.push_back(getTypeToTransformTo(VT));
2905 if (VT != MVT::Vector) {
2906 // If this is a large integer, it needs to be broken up into small
2907 // integers. Figure out what the destination type is and how many small
2908 // integers it turns into.
2909 MVT::ValueType NVT = getTypeToExpandTo(VT);
2910 unsigned NumVals = getNumElements(VT);
2911 for (unsigned i = 0; i != NumVals; ++i)
2912 RetVals.push_back(NVT);
2914 // Otherwise, this is a vector type. We only support legal vectors
2916 unsigned NumElems = cast<PackedType>(I->getType())->getNumElements();
2917 const Type *EltTy = cast<PackedType>(I->getType())->getElementType();
2919 // Figure out if there is a Packed type corresponding to this Vector
2920 // type. If so, convert to the packed type.
2921 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2922 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2923 RetVals.push_back(TVT);
2925 assert(0 && "Don't support illegal by-val vector arguments yet!");
2932 RetVals.push_back(MVT::Other);
2935 SDNode *Result = DAG.getNode(ISD::FORMAL_ARGUMENTS,
2936 DAG.getNodeValueTypes(RetVals), RetVals.size(),
2937 &Ops[0], Ops.size()).Val;
2939 DAG.setRoot(SDOperand(Result, Result->getNumValues()-1));
2941 // Set up the return result vector.
2943 const FunctionType *FTy = F.getFunctionType();
2946 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
2948 MVT::ValueType VT = getValueType(I->getType());
2950 switch (getTypeAction(VT)) {
2951 default: assert(0 && "Unknown type action!");
2953 Ops.push_back(SDOperand(Result, i++));
2956 SDOperand Op(Result, i++);
2957 if (MVT::isInteger(VT)) {
2958 if (FTy->paramHasAttr(Idx, FunctionType::SExtAttribute))
2959 Op = DAG.getNode(ISD::AssertSext, Op.getValueType(), Op,
2960 DAG.getValueType(VT));
2961 else if (FTy->paramHasAttr(Idx, FunctionType::ZExtAttribute))
2962 Op = DAG.getNode(ISD::AssertZext, Op.getValueType(), Op,
2963 DAG.getValueType(VT));
2964 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2966 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
2967 Op = DAG.getNode(ISD::FP_ROUND, VT, Op);
2973 if (VT != MVT::Vector) {
2974 // If this is a large integer or a floating point node that needs to be
2975 // expanded, it needs to be reassembled from small integers. Figure out
2976 // what the source elt type is and how many small integers it is.
2977 Ops.push_back(ExpandScalarFormalArgs(VT, Result, i, DAG, *this));
2979 // Otherwise, this is a vector type. We only support legal vectors
2981 const PackedType *PTy = cast<PackedType>(I->getType());
2982 unsigned NumElems = PTy->getNumElements();
2983 const Type *EltTy = PTy->getElementType();
2985 // Figure out if there is a Packed type corresponding to this Vector
2986 // type. If so, convert to the packed type.
2987 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
2988 if (TVT != MVT::Other && isTypeLegal(TVT)) {
2989 SDOperand N = SDOperand(Result, i++);
2990 // Handle copies from generic vectors to registers.
2991 N = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, N,
2992 DAG.getConstant(NumElems, MVT::i32),
2993 DAG.getValueType(getValueType(EltTy)));
2996 assert(0 && "Don't support illegal by-val vector arguments yet!");
3007 /// ExpandScalarCallArgs - Recursively expand call argument node by
3008 /// bit_converting it or extract a pair of elements from the larger node.
3009 static void ExpandScalarCallArgs(MVT::ValueType VT, SDOperand Arg,
3011 SmallVector<SDOperand, 32> &Ops,
3013 TargetLowering &TLI) {
3014 if (TLI.getTypeAction(VT) != TargetLowering::Expand) {
3016 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
3020 MVT::ValueType EVT = TLI.getTypeToTransformTo(VT);
3021 unsigned NumVals = MVT::getSizeInBits(VT) / MVT::getSizeInBits(EVT);
3023 Arg = DAG.getNode(ISD::BIT_CONVERT, EVT, Arg);
3024 ExpandScalarCallArgs(EVT, Arg, isSigned, Ops, DAG, TLI);
3025 } else if (NumVals == 2) {
3026 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg,
3027 DAG.getConstant(0, TLI.getPointerTy()));
3028 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, EVT, Arg,
3029 DAG.getConstant(1, TLI.getPointerTy()));
3030 if (!TLI.isLittleEndian())
3032 ExpandScalarCallArgs(EVT, Lo, isSigned, Ops, DAG, TLI);
3033 ExpandScalarCallArgs(EVT, Hi, isSigned, Ops, DAG, TLI);
3035 // Value scalarized into many values. Unimp for now.
3036 assert(0 && "Cannot expand i64 -> i16 yet!");
3040 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
3041 /// implementation, which just inserts an ISD::CALL node, which is later custom
3042 /// lowered by the target to something concrete. FIXME: When all targets are
3043 /// migrated to using ISD::CALL, this hook should be integrated into SDISel.
3044 std::pair<SDOperand, SDOperand>
3045 TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
3046 bool RetTyIsSigned, bool isVarArg,
3047 unsigned CallingConv, bool isTailCall,
3049 ArgListTy &Args, SelectionDAG &DAG) {
3050 SmallVector<SDOperand, 32> Ops;
3051 Ops.push_back(Chain); // Op#0 - Chain
3052 Ops.push_back(DAG.getConstant(CallingConv, getPointerTy())); // Op#1 - CC
3053 Ops.push_back(DAG.getConstant(isVarArg, getPointerTy())); // Op#2 - VarArg
3054 Ops.push_back(DAG.getConstant(isTailCall, getPointerTy())); // Op#3 - Tail
3055 Ops.push_back(Callee);
3057 // Handle all of the outgoing arguments.
3058 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
3059 MVT::ValueType VT = getValueType(Args[i].Ty);
3060 SDOperand Op = Args[i].Node;
3061 bool isSigned = Args[i].isSigned;
3062 switch (getTypeAction(VT)) {
3063 default: assert(0 && "Unknown type action!");
3066 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
3069 if (MVT::isInteger(VT)) {
3070 unsigned ExtOp = isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3071 Op = DAG.getNode(ExtOp, getTypeToTransformTo(VT), Op);
3073 assert(MVT::isFloatingPoint(VT) && "Not int or FP?");
3074 Op = DAG.getNode(ISD::FP_EXTEND, getTypeToTransformTo(VT), Op);
3077 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
3080 if (VT != MVT::Vector) {
3081 // If this is a large integer, it needs to be broken down into small
3082 // integers. Figure out what the source elt type is and how many small
3084 ExpandScalarCallArgs(VT, Op, isSigned, Ops, DAG, *this);
3086 // Otherwise, this is a vector type. We only support legal vectors
3088 const PackedType *PTy = cast<PackedType>(Args[i].Ty);
3089 unsigned NumElems = PTy->getNumElements();
3090 const Type *EltTy = PTy->getElementType();
3092 // Figure out if there is a Packed type corresponding to this Vector
3093 // type. If so, convert to the packed type.
3094 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
3095 if (TVT != MVT::Other && isTypeLegal(TVT)) {
3096 // Insert a VBIT_CONVERT of the MVT::Vector type to the packed type.
3097 Op = DAG.getNode(ISD::VBIT_CONVERT, TVT, Op);
3099 Ops.push_back(DAG.getConstant(isSigned, MVT::i32));
3101 assert(0 && "Don't support illegal by-val vector call args yet!");
3109 // Figure out the result value types.
3110 SmallVector<MVT::ValueType, 4> RetTys;
3112 if (RetTy != Type::VoidTy) {
3113 MVT::ValueType VT = getValueType(RetTy);
3114 switch (getTypeAction(VT)) {
3115 default: assert(0 && "Unknown type action!");
3117 RetTys.push_back(VT);
3120 RetTys.push_back(getTypeToTransformTo(VT));
3123 if (VT != MVT::Vector) {
3124 // If this is a large integer, it needs to be reassembled from small
3125 // integers. Figure out what the source elt type is and how many small
3127 MVT::ValueType NVT = getTypeToExpandTo(VT);
3128 unsigned NumVals = getNumElements(VT);
3129 for (unsigned i = 0; i != NumVals; ++i)
3130 RetTys.push_back(NVT);
3132 // Otherwise, this is a vector type. We only support legal vectors
3134 const PackedType *PTy = cast<PackedType>(RetTy);
3135 unsigned NumElems = PTy->getNumElements();
3136 const Type *EltTy = PTy->getElementType();
3138 // Figure out if there is a Packed type corresponding to this Vector
3139 // type. If so, convert to the packed type.
3140 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
3141 if (TVT != MVT::Other && isTypeLegal(TVT)) {
3142 RetTys.push_back(TVT);
3144 assert(0 && "Don't support illegal by-val vector call results yet!");
3151 RetTys.push_back(MVT::Other); // Always has a chain.
3153 // Finally, create the CALL node.
3154 SDOperand Res = DAG.getNode(ISD::CALL,
3155 DAG.getVTList(&RetTys[0], RetTys.size()),
3156 &Ops[0], Ops.size());
3158 // This returns a pair of operands. The first element is the
3159 // return value for the function (if RetTy is not VoidTy). The second
3160 // element is the outgoing token chain.
3162 if (RetTys.size() != 1) {
3163 MVT::ValueType VT = getValueType(RetTy);
3164 if (RetTys.size() == 2) {
3167 // If this value was promoted, truncate it down.
3168 if (ResVal.getValueType() != VT) {
3169 if (VT == MVT::Vector) {
3170 // Insert a VBITCONVERT to convert from the packed result type to the
3171 // MVT::Vector type.
3172 unsigned NumElems = cast<PackedType>(RetTy)->getNumElements();
3173 const Type *EltTy = cast<PackedType>(RetTy)->getElementType();
3175 // Figure out if there is a Packed type corresponding to this Vector
3176 // type. If so, convert to the packed type.
3177 MVT::ValueType TVT = MVT::getVectorType(getValueType(EltTy), NumElems);
3178 if (TVT != MVT::Other && isTypeLegal(TVT)) {
3179 // Insert a VBIT_CONVERT of the FORMAL_ARGUMENTS to a
3180 // "N x PTyElementVT" MVT::Vector type.
3181 ResVal = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, ResVal,
3182 DAG.getConstant(NumElems, MVT::i32),
3183 DAG.getValueType(getValueType(EltTy)));
3187 } else if (MVT::isInteger(VT)) {
3188 unsigned AssertOp = ISD::AssertSext;
3190 AssertOp = ISD::AssertZext;
3191 ResVal = DAG.getNode(AssertOp, ResVal.getValueType(), ResVal,
3192 DAG.getValueType(VT));
3193 ResVal = DAG.getNode(ISD::TRUNCATE, VT, ResVal);
3195 assert(MVT::isFloatingPoint(VT));
3196 if (getTypeAction(VT) == Expand)
3197 ResVal = DAG.getNode(ISD::BIT_CONVERT, VT, ResVal);
3199 ResVal = DAG.getNode(ISD::FP_ROUND, VT, ResVal);
3202 } else if (RetTys.size() == 3) {
3203 ResVal = DAG.getNode(ISD::BUILD_PAIR, VT,
3204 Res.getValue(0), Res.getValue(1));
3207 assert(0 && "Case not handled yet!");
3211 return std::make_pair(ResVal, Res.getValue(Res.Val->getNumValues()-1));
3216 // It is always conservatively correct for llvm.returnaddress and
3217 // llvm.frameaddress to return 0.
3219 // FIXME: Change this to insert a FRAMEADDR/RETURNADDR node, and have that be
3220 // expanded to 0 if the target wants.
3221 std::pair<SDOperand, SDOperand>
3222 TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain,
3223 unsigned Depth, SelectionDAG &DAG) {
3224 return std::make_pair(DAG.getConstant(0, getPointerTy()), Chain);
3227 SDOperand TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
3228 assert(0 && "LowerOperation not implemented for this target!");
3233 SDOperand TargetLowering::CustomPromoteOperation(SDOperand Op,
3234 SelectionDAG &DAG) {
3235 assert(0 && "CustomPromoteOperation not implemented for this target!");
3240 void SelectionDAGLowering::visitFrameReturnAddress(CallInst &I, bool isFrame) {
3241 unsigned Depth = (unsigned)cast<ConstantInt>(I.getOperand(1))->getZExtValue();
3242 std::pair<SDOperand,SDOperand> Result =
3243 TLI.LowerFrameReturnAddress(isFrame, getRoot(), Depth, DAG);
3244 setValue(&I, Result.first);
3245 DAG.setRoot(Result.second);
3248 /// getMemsetValue - Vectorized representation of the memset value
3250 static SDOperand getMemsetValue(SDOperand Value, MVT::ValueType VT,
3251 SelectionDAG &DAG) {
3252 MVT::ValueType CurVT = VT;
3253 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
3254 uint64_t Val = C->getValue() & 255;
3256 while (CurVT != MVT::i8) {
3257 Val = (Val << Shift) | Val;
3259 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
3261 return DAG.getConstant(Val, VT);
3263 Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
3265 while (CurVT != MVT::i8) {
3267 DAG.getNode(ISD::OR, VT,
3268 DAG.getNode(ISD::SHL, VT, Value,
3269 DAG.getConstant(Shift, MVT::i8)), Value);
3271 CurVT = (MVT::ValueType)((unsigned)CurVT - 1);
3278 /// getMemsetStringVal - Similar to getMemsetValue. Except this is only
3279 /// used when a memcpy is turned into a memset when the source is a constant
3281 static SDOperand getMemsetStringVal(MVT::ValueType VT,
3282 SelectionDAG &DAG, TargetLowering &TLI,
3283 std::string &Str, unsigned Offset) {
3285 unsigned MSB = getSizeInBits(VT) / 8;
3286 if (TLI.isLittleEndian())
3287 Offset = Offset + MSB - 1;
3288 for (unsigned i = 0; i != MSB; ++i) {
3289 Val = (Val << 8) | (unsigned char)Str[Offset];
3290 Offset += TLI.isLittleEndian() ? -1 : 1;
3292 return DAG.getConstant(Val, VT);
3295 /// getMemBasePlusOffset - Returns base and offset node for the
3296 static SDOperand getMemBasePlusOffset(SDOperand Base, unsigned Offset,
3297 SelectionDAG &DAG, TargetLowering &TLI) {
3298 MVT::ValueType VT = Base.getValueType();
3299 return DAG.getNode(ISD::ADD, VT, Base, DAG.getConstant(Offset, VT));
3302 /// MeetsMaxMemopRequirement - Determines if the number of memory ops required
3303 /// to replace the memset / memcpy is below the threshold. It also returns the
3304 /// types of the sequence of memory ops to perform memset / memcpy.
3305 static bool MeetsMaxMemopRequirement(std::vector<MVT::ValueType> &MemOps,
3306 unsigned Limit, uint64_t Size,
3307 unsigned Align, TargetLowering &TLI) {
3310 if (TLI.allowsUnalignedMemoryAccesses()) {
3313 switch (Align & 7) {
3329 MVT::ValueType LVT = MVT::i64;
3330 while (!TLI.isTypeLegal(LVT))
3331 LVT = (MVT::ValueType)((unsigned)LVT - 1);
3332 assert(MVT::isInteger(LVT));
3337 unsigned NumMemOps = 0;
3339 unsigned VTSize = getSizeInBits(VT) / 8;
3340 while (VTSize > Size) {
3341 VT = (MVT::ValueType)((unsigned)VT - 1);
3344 assert(MVT::isInteger(VT));
3346 if (++NumMemOps > Limit)
3348 MemOps.push_back(VT);
3355 void SelectionDAGLowering::visitMemIntrinsic(CallInst &I, unsigned Op) {
3356 SDOperand Op1 = getValue(I.getOperand(1));
3357 SDOperand Op2 = getValue(I.getOperand(2));
3358 SDOperand Op3 = getValue(I.getOperand(3));
3359 SDOperand Op4 = getValue(I.getOperand(4));
3360 unsigned Align = (unsigned)cast<ConstantSDNode>(Op4)->getValue();
3361 if (Align == 0) Align = 1;
3363 if (ConstantSDNode *Size = dyn_cast<ConstantSDNode>(Op3)) {
3364 std::vector<MVT::ValueType> MemOps;
3366 // Expand memset / memcpy to a series of load / store ops
3367 // if the size operand falls below a certain threshold.
3368 SmallVector<SDOperand, 8> OutChains;
3370 default: break; // Do nothing for now.
3372 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemset(),
3373 Size->getValue(), Align, TLI)) {
3374 unsigned NumMemOps = MemOps.size();
3375 unsigned Offset = 0;
3376 for (unsigned i = 0; i < NumMemOps; i++) {
3377 MVT::ValueType VT = MemOps[i];
3378 unsigned VTSize = getSizeInBits(VT) / 8;
3379 SDOperand Value = getMemsetValue(Op2, VT, DAG);
3380 SDOperand Store = DAG.getStore(getRoot(), Value,
3381 getMemBasePlusOffset(Op1, Offset, DAG, TLI),
3382 I.getOperand(1), Offset);
3383 OutChains.push_back(Store);
3390 if (MeetsMaxMemopRequirement(MemOps, TLI.getMaxStoresPerMemcpy(),
3391 Size->getValue(), Align, TLI)) {
3392 unsigned NumMemOps = MemOps.size();
3393 unsigned SrcOff = 0, DstOff = 0, SrcDelta = 0;
3394 GlobalAddressSDNode *G = NULL;
3396 bool CopyFromStr = false;
3398 if (Op2.getOpcode() == ISD::GlobalAddress)
3399 G = cast<GlobalAddressSDNode>(Op2);
3400 else if (Op2.getOpcode() == ISD::ADD &&
3401 Op2.getOperand(0).getOpcode() == ISD::GlobalAddress &&
3402 Op2.getOperand(1).getOpcode() == ISD::Constant) {
3403 G = cast<GlobalAddressSDNode>(Op2.getOperand(0));
3404 SrcDelta = cast<ConstantSDNode>(Op2.getOperand(1))->getValue();
3407 GlobalVariable *GV = dyn_cast<GlobalVariable>(G->getGlobal());
3408 if (GV && GV->isConstant()) {
3409 Str = GV->getStringValue(false);
3417 for (unsigned i = 0; i < NumMemOps; i++) {
3418 MVT::ValueType VT = MemOps[i];
3419 unsigned VTSize = getSizeInBits(VT) / 8;
3420 SDOperand Value, Chain, Store;
3423 Value = getMemsetStringVal(VT, DAG, TLI, Str, SrcOff);
3426 DAG.getStore(Chain, Value,
3427 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
3428 I.getOperand(1), DstOff);
3430 Value = DAG.getLoad(VT, getRoot(),
3431 getMemBasePlusOffset(Op2, SrcOff, DAG, TLI),
3432 I.getOperand(2), SrcOff);
3433 Chain = Value.getValue(1);
3435 DAG.getStore(Chain, Value,
3436 getMemBasePlusOffset(Op1, DstOff, DAG, TLI),
3437 I.getOperand(1), DstOff);
3439 OutChains.push_back(Store);
3448 if (!OutChains.empty()) {
3449 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
3450 &OutChains[0], OutChains.size()));
3455 DAG.setRoot(DAG.getNode(Op, MVT::Other, getRoot(), Op1, Op2, Op3, Op4));
3458 //===----------------------------------------------------------------------===//
3459 // SelectionDAGISel code
3460 //===----------------------------------------------------------------------===//
3462 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
3463 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
3466 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
3467 // FIXME: we only modify the CFG to split critical edges. This
3468 // updates dom and loop info.
3469 AU.addRequired<AliasAnalysis>();
3473 /// OptimizeNoopCopyExpression - We have determined that the specified cast
3474 /// instruction is a noop copy (e.g. it's casting from one pointer type to
3475 /// another, int->uint, or int->sbyte on PPC.
3477 /// Return true if any changes are made.
3478 static bool OptimizeNoopCopyExpression(CastInst *CI) {
3479 BasicBlock *DefBB = CI->getParent();
3481 /// InsertedCasts - Only insert a cast in each block once.
3482 std::map<BasicBlock*, CastInst*> InsertedCasts;
3484 bool MadeChange = false;
3485 for (Value::use_iterator UI = CI->use_begin(), E = CI->use_end();
3487 Use &TheUse = UI.getUse();
3488 Instruction *User = cast<Instruction>(*UI);
3490 // Figure out which BB this cast is used in. For PHI's this is the
3491 // appropriate predecessor block.
3492 BasicBlock *UserBB = User->getParent();
3493 if (PHINode *PN = dyn_cast<PHINode>(User)) {
3494 unsigned OpVal = UI.getOperandNo()/2;
3495 UserBB = PN->getIncomingBlock(OpVal);
3498 // Preincrement use iterator so we don't invalidate it.
3501 // If this user is in the same block as the cast, don't change the cast.
3502 if (UserBB == DefBB) continue;
3504 // If we have already inserted a cast into this block, use it.
3505 CastInst *&InsertedCast = InsertedCasts[UserBB];
3507 if (!InsertedCast) {
3508 BasicBlock::iterator InsertPt = UserBB->begin();
3509 while (isa<PHINode>(InsertPt)) ++InsertPt;
3512 CastInst::create(CI->getOpcode(), CI->getOperand(0), CI->getType(), "",
3517 // Replace a use of the cast with a use of the new casat.
3518 TheUse = InsertedCast;
3521 // If we removed all uses, nuke the cast.
3522 if (CI->use_empty())
3523 CI->eraseFromParent();
3528 /// InsertGEPComputeCode - Insert code into BB to compute Ptr+PtrOffset,
3529 /// casting to the type of GEPI.
3530 static Instruction *InsertGEPComputeCode(Instruction *&V, BasicBlock *BB,
3531 Instruction *GEPI, Value *Ptr,
3533 if (V) return V; // Already computed.
3535 // Figure out the insertion point
3536 BasicBlock::iterator InsertPt;
3537 if (BB == GEPI->getParent()) {
3538 // If GEP is already inserted into BB, insert right after the GEP.
3542 // Otherwise, insert at the top of BB, after any PHI nodes
3543 InsertPt = BB->begin();
3544 while (isa<PHINode>(InsertPt)) ++InsertPt;
3547 // If Ptr is itself a cast, but in some other BB, emit a copy of the cast into
3548 // BB so that there is only one value live across basic blocks (the cast
3550 if (CastInst *CI = dyn_cast<CastInst>(Ptr))
3551 if (CI->getParent() != BB && isa<PointerType>(CI->getOperand(0)->getType()))
3552 Ptr = CastInst::create(CI->getOpcode(), CI->getOperand(0), CI->getType(),
3555 // Add the offset, cast it to the right type.
3556 Ptr = BinaryOperator::createAdd(Ptr, PtrOffset, "", InsertPt);
3557 // Ptr is an integer type, GEPI is pointer type ==> IntToPtr
3558 return V = CastInst::create(Instruction::IntToPtr, Ptr, GEPI->getType(),
3562 /// ReplaceUsesOfGEPInst - Replace all uses of RepPtr with inserted code to
3563 /// compute its value. The RepPtr value can be computed with Ptr+PtrOffset. One
3564 /// trivial way of doing this would be to evaluate Ptr+PtrOffset in RepPtr's
3565 /// block, then ReplaceAllUsesWith'ing everything. However, we would prefer to
3566 /// sink PtrOffset into user blocks where doing so will likely allow us to fold
3567 /// the constant add into a load or store instruction. Additionally, if a user
3568 /// is a pointer-pointer cast, we look through it to find its users.
3569 static void ReplaceUsesOfGEPInst(Instruction *RepPtr, Value *Ptr,
3570 Constant *PtrOffset, BasicBlock *DefBB,
3571 GetElementPtrInst *GEPI,
3572 std::map<BasicBlock*,Instruction*> &InsertedExprs) {
3573 while (!RepPtr->use_empty()) {
3574 Instruction *User = cast<Instruction>(RepPtr->use_back());
3576 // If the user is a Pointer-Pointer cast, recurse. Only BitCast can be
3577 // used for a Pointer-Pointer cast.
3578 if (isa<BitCastInst>(User)) {
3579 ReplaceUsesOfGEPInst(User, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3581 // Drop the use of RepPtr. The cast is dead. Don't delete it now, else we
3582 // could invalidate an iterator.
3583 User->setOperand(0, UndefValue::get(RepPtr->getType()));
3587 // If this is a load of the pointer, or a store through the pointer, emit
3588 // the increment into the load/store block.
3589 Instruction *NewVal;
3590 if (isa<LoadInst>(User) ||
3591 (isa<StoreInst>(User) && User->getOperand(0) != RepPtr)) {
3592 NewVal = InsertGEPComputeCode(InsertedExprs[User->getParent()],
3593 User->getParent(), GEPI,
3596 // If this use is not foldable into the addressing mode, use a version
3597 // emitted in the GEP block.
3598 NewVal = InsertGEPComputeCode(InsertedExprs[DefBB], DefBB, GEPI,
3602 if (GEPI->getType() != RepPtr->getType()) {
3603 BasicBlock::iterator IP = NewVal;
3605 // NewVal must be a GEP which must be pointer type, so BitCast
3606 NewVal = new BitCastInst(NewVal, RepPtr->getType(), "", IP);
3608 User->replaceUsesOfWith(RepPtr, NewVal);
3613 /// OptimizeGEPExpression - Since we are doing basic-block-at-a-time instruction
3614 /// selection, we want to be a bit careful about some things. In particular, if
3615 /// we have a GEP instruction that is used in a different block than it is
3616 /// defined, the addressing expression of the GEP cannot be folded into loads or
3617 /// stores that use it. In this case, decompose the GEP and move constant
3618 /// indices into blocks that use it.
3619 static bool OptimizeGEPExpression(GetElementPtrInst *GEPI,
3620 const TargetData *TD) {
3621 // If this GEP is only used inside the block it is defined in, there is no
3622 // need to rewrite it.
3623 bool isUsedOutsideDefBB = false;
3624 BasicBlock *DefBB = GEPI->getParent();
3625 for (Value::use_iterator UI = GEPI->use_begin(), E = GEPI->use_end();
3627 if (cast<Instruction>(*UI)->getParent() != DefBB) {
3628 isUsedOutsideDefBB = true;
3632 if (!isUsedOutsideDefBB) return false;
3634 // If this GEP has no non-zero constant indices, there is nothing we can do,
3636 bool hasConstantIndex = false;
3637 bool hasVariableIndex = false;
3638 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3639 E = GEPI->op_end(); OI != E; ++OI) {
3640 if (ConstantInt *CI = dyn_cast<ConstantInt>(*OI)) {
3641 if (CI->getZExtValue()) {
3642 hasConstantIndex = true;
3646 hasVariableIndex = true;
3650 // If this is a "GEP X, 0, 0, 0", turn this into a cast.
3651 if (!hasConstantIndex && !hasVariableIndex) {
3652 /// The GEP operand must be a pointer, so must its result -> BitCast
3653 Value *NC = new BitCastInst(GEPI->getOperand(0), GEPI->getType(),
3654 GEPI->getName(), GEPI);
3655 GEPI->replaceAllUsesWith(NC);
3656 GEPI->eraseFromParent();
3660 // If this is a GEP &Alloca, 0, 0, forward subst the frame index into uses.
3661 if (!hasConstantIndex && !isa<AllocaInst>(GEPI->getOperand(0)))
3664 // Otherwise, decompose the GEP instruction into multiplies and adds. Sum the
3665 // constant offset (which we now know is non-zero) and deal with it later.
3666 uint64_t ConstantOffset = 0;
3667 const Type *UIntPtrTy = TD->getIntPtrType();
3668 Value *Ptr = new PtrToIntInst(GEPI->getOperand(0), UIntPtrTy, "", GEPI);
3669 const Type *Ty = GEPI->getOperand(0)->getType();
3671 for (GetElementPtrInst::op_iterator OI = GEPI->op_begin()+1,
3672 E = GEPI->op_end(); OI != E; ++OI) {
3674 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
3675 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
3677 ConstantOffset += TD->getStructLayout(StTy)->MemberOffsets[Field];
3678 Ty = StTy->getElementType(Field);
3680 Ty = cast<SequentialType>(Ty)->getElementType();
3682 // Handle constant subscripts.
3683 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3684 if (CI->getZExtValue() == 0) continue;
3685 ConstantOffset += (int64_t)TD->getTypeSize(Ty)*CI->getSExtValue();
3689 // Ptr = Ptr + Idx * ElementSize;
3691 // Cast Idx to UIntPtrTy if needed.
3692 Idx = CastInst::createIntegerCast(Idx, UIntPtrTy, true/*SExt*/, "", GEPI);
3694 uint64_t ElementSize = TD->getTypeSize(Ty);
3695 // Mask off bits that should not be set.
3696 ElementSize &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3697 Constant *SizeCst = ConstantInt::get(UIntPtrTy, ElementSize);
3699 // Multiply by the element size and add to the base.
3700 Idx = BinaryOperator::createMul(Idx, SizeCst, "", GEPI);
3701 Ptr = BinaryOperator::createAdd(Ptr, Idx, "", GEPI);
3705 // Make sure that the offset fits in uintptr_t.
3706 ConstantOffset &= ~0ULL >> (64-UIntPtrTy->getPrimitiveSizeInBits());
3707 Constant *PtrOffset = ConstantInt::get(UIntPtrTy, ConstantOffset);
3709 // Okay, we have now emitted all of the variable index parts to the BB that
3710 // the GEP is defined in. Loop over all of the using instructions, inserting
3711 // an "add Ptr, ConstantOffset" into each block that uses it and update the
3712 // instruction to use the newly computed value, making GEPI dead. When the
3713 // user is a load or store instruction address, we emit the add into the user
3714 // block, otherwise we use a canonical version right next to the gep (these
3715 // won't be foldable as addresses, so we might as well share the computation).
3717 std::map<BasicBlock*,Instruction*> InsertedExprs;
3718 ReplaceUsesOfGEPInst(GEPI, Ptr, PtrOffset, DefBB, GEPI, InsertedExprs);
3720 // Finally, the GEP is dead, remove it.
3721 GEPI->eraseFromParent();
3727 /// SplitEdgeNicely - Split the critical edge from TI to it's specified
3728 /// successor if it will improve codegen. We only do this if the successor has
3729 /// phi nodes (otherwise critical edges are ok). If there is already another
3730 /// predecessor of the succ that is empty (and thus has no phi nodes), use it
3731 /// instead of introducing a new block.
3732 static void SplitEdgeNicely(TerminatorInst *TI, unsigned SuccNum, Pass *P) {
3733 BasicBlock *TIBB = TI->getParent();
3734 BasicBlock *Dest = TI->getSuccessor(SuccNum);
3735 assert(isa<PHINode>(Dest->begin()) &&
3736 "This should only be called if Dest has a PHI!");
3738 /// TIPHIValues - This array is lazily computed to determine the values of
3739 /// PHIs in Dest that TI would provide.
3740 std::vector<Value*> TIPHIValues;
3742 // Check to see if Dest has any blocks that can be used as a split edge for
3744 for (pred_iterator PI = pred_begin(Dest), E = pred_end(Dest); PI != E; ++PI) {
3745 BasicBlock *Pred = *PI;
3746 // To be usable, the pred has to end with an uncond branch to the dest.
3747 BranchInst *PredBr = dyn_cast<BranchInst>(Pred->getTerminator());
3748 if (!PredBr || !PredBr->isUnconditional() ||
3749 // Must be empty other than the branch.
3750 &Pred->front() != PredBr)
3753 // Finally, since we know that Dest has phi nodes in it, we have to make
3754 // sure that jumping to Pred will have the same affect as going to Dest in
3755 // terms of PHI values.
3758 bool FoundMatch = true;
3759 for (BasicBlock::iterator I = Dest->begin();
3760 (PN = dyn_cast<PHINode>(I)); ++I, ++PHINo) {
3761 if (PHINo == TIPHIValues.size())
3762 TIPHIValues.push_back(PN->getIncomingValueForBlock(TIBB));
3764 // If the PHI entry doesn't work, we can't use this pred.
3765 if (TIPHIValues[PHINo] != PN->getIncomingValueForBlock(Pred)) {
3771 // If we found a workable predecessor, change TI to branch to Succ.
3773 Dest->removePredecessor(TIBB);
3774 TI->setSuccessor(SuccNum, Pred);
3779 SplitCriticalEdge(TI, SuccNum, P, true);
3783 bool SelectionDAGISel::runOnFunction(Function &Fn) {
3784 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
3785 RegMap = MF.getSSARegMap();
3786 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
3788 // First, split all critical edges.
3790 // In this pass we also look for GEP and cast instructions that are used
3791 // across basic blocks and rewrite them to improve basic-block-at-a-time
3794 bool MadeChange = true;
3795 while (MadeChange) {
3797 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
3798 // Split all critical edges where the dest block has a PHI.
3799 TerminatorInst *BBTI = BB->getTerminator();
3800 if (BBTI->getNumSuccessors() > 1) {
3801 for (unsigned i = 0, e = BBTI->getNumSuccessors(); i != e; ++i)
3802 if (isa<PHINode>(BBTI->getSuccessor(i)->begin()) &&
3803 isCriticalEdge(BBTI, i, true))
3804 SplitEdgeNicely(BBTI, i, this);
3808 for (BasicBlock::iterator BBI = BB->begin(), E = BB->end(); BBI != E; ) {
3809 Instruction *I = BBI++;
3811 if (CallInst *CI = dyn_cast<CallInst>(I)) {
3812 // If we found an inline asm expession, and if the target knows how to
3813 // lower it to normal LLVM code, do so now.
3814 if (isa<InlineAsm>(CI->getCalledValue()))
3815 if (const TargetAsmInfo *TAI =
3816 TLI.getTargetMachine().getTargetAsmInfo()) {
3817 if (TAI->ExpandInlineAsm(CI))
3820 } else if (GetElementPtrInst *GEPI = dyn_cast<GetElementPtrInst>(I)) {
3821 MadeChange |= OptimizeGEPExpression(GEPI, TLI.getTargetData());
3822 } else if (CastInst *CI = dyn_cast<CastInst>(I)) {
3823 // If the source of the cast is a constant, then this should have
3824 // already been constant folded. The only reason NOT to constant fold
3825 // it is if something (e.g. LSR) was careful to place the constant
3826 // evaluation in a block other than then one that uses it (e.g. to hoist
3827 // the address of globals out of a loop). If this is the case, we don't
3828 // want to forward-subst the cast.
3829 if (isa<Constant>(CI->getOperand(0)))
3832 // If this is a noop copy, sink it into user blocks to reduce the number
3833 // of virtual registers that must be created and coallesced.
3834 MVT::ValueType SrcVT = TLI.getValueType(CI->getOperand(0)->getType());
3835 MVT::ValueType DstVT = TLI.getValueType(CI->getType());
3837 // This is an fp<->int conversion?
3838 if (MVT::isInteger(SrcVT) != MVT::isInteger(DstVT))
3841 // If this is an extension, it will be a zero or sign extension, which
3843 if (SrcVT < DstVT) continue;
3845 // If these values will be promoted, find out what they will be promoted
3846 // to. This helps us consider truncates on PPC as noop copies when they
3848 if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote)
3849 SrcVT = TLI.getTypeToTransformTo(SrcVT);
3850 if (TLI.getTypeAction(DstVT) == TargetLowering::Promote)
3851 DstVT = TLI.getTypeToTransformTo(DstVT);
3853 // If, after promotion, these are the same types, this is a noop copy.
3855 MadeChange |= OptimizeNoopCopyExpression(CI);
3861 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
3863 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
3864 SelectBasicBlock(I, MF, FuncInfo);
3869 SDOperand SelectionDAGLowering::CopyValueToVirtualRegister(Value *V,
3871 SDOperand Op = getValue(V);
3872 assert((Op.getOpcode() != ISD::CopyFromReg ||
3873 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
3874 "Copy from a reg to the same reg!");
3876 // If this type is not legal, we must make sure to not create an invalid
3878 MVT::ValueType SrcVT = Op.getValueType();
3879 MVT::ValueType DestVT = TLI.getTypeToTransformTo(SrcVT);
3880 if (SrcVT == DestVT) {
3881 return DAG.getCopyToReg(getRoot(), Reg, Op);
3882 } else if (SrcVT == MVT::Vector) {
3883 // Handle copies from generic vectors to registers.
3884 MVT::ValueType PTyElementVT, PTyLegalElementVT;
3885 unsigned NE = TLI.getPackedTypeBreakdown(cast<PackedType>(V->getType()),
3886 PTyElementVT, PTyLegalElementVT);
3888 // Insert a VBIT_CONVERT of the input vector to a "N x PTyElementVT"
3889 // MVT::Vector type.
3890 Op = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Op,
3891 DAG.getConstant(NE, MVT::i32),
3892 DAG.getValueType(PTyElementVT));
3894 // Loop over all of the elements of the resultant vector,
3895 // VEXTRACT_VECTOR_ELT'ing them, converting them to PTyLegalElementVT, then
3896 // copying them into output registers.
3897 SmallVector<SDOperand, 8> OutChains;
3898 SDOperand Root = getRoot();
3899 for (unsigned i = 0; i != NE; ++i) {
3900 SDOperand Elt = DAG.getNode(ISD::VEXTRACT_VECTOR_ELT, PTyElementVT,
3901 Op, DAG.getConstant(i, TLI.getPointerTy()));
3902 if (PTyElementVT == PTyLegalElementVT) {
3903 // Elements are legal.
3904 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3905 } else if (PTyLegalElementVT > PTyElementVT) {
3906 // Elements are promoted.
3907 if (MVT::isFloatingPoint(PTyLegalElementVT))
3908 Elt = DAG.getNode(ISD::FP_EXTEND, PTyLegalElementVT, Elt);
3910 Elt = DAG.getNode(ISD::ANY_EXTEND, PTyLegalElementVT, Elt);
3911 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Elt));
3913 // Elements are expanded.
3914 // The src value is expanded into multiple registers.
3915 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3916 Elt, DAG.getConstant(0, TLI.getPointerTy()));
3917 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, PTyLegalElementVT,
3918 Elt, DAG.getConstant(1, TLI.getPointerTy()));
3919 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Lo));
3920 OutChains.push_back(DAG.getCopyToReg(Root, Reg++, Hi));
3923 return DAG.getNode(ISD::TokenFactor, MVT::Other,
3924 &OutChains[0], OutChains.size());
3925 } else if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote) {
3926 // The src value is promoted to the register.
3927 if (MVT::isFloatingPoint(SrcVT))
3928 Op = DAG.getNode(ISD::FP_EXTEND, DestVT, Op);
3930 Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
3931 return DAG.getCopyToReg(getRoot(), Reg, Op);
3933 DestVT = TLI.getTypeToExpandTo(SrcVT);
3934 unsigned NumVals = TLI.getNumElements(SrcVT);
3936 return DAG.getCopyToReg(getRoot(), Reg,
3937 DAG.getNode(ISD::BIT_CONVERT, DestVT, Op));
3938 assert(NumVals == 2 && "1 to 4 (and more) expansion not implemented!");
3939 // The src value is expanded into multiple registers.
3940 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3941 Op, DAG.getConstant(0, TLI.getPointerTy()));
3942 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,
3943 Op, DAG.getConstant(1, TLI.getPointerTy()));
3944 Op = DAG.getCopyToReg(getRoot(), Reg, Lo);
3945 return DAG.getCopyToReg(Op, Reg+1, Hi);
3949 void SelectionDAGISel::
3950 LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL,
3951 std::vector<SDOperand> &UnorderedChains) {
3952 // If this is the entry block, emit arguments.
3953 Function &F = *BB->getParent();
3954 FunctionLoweringInfo &FuncInfo = SDL.FuncInfo;
3955 SDOperand OldRoot = SDL.DAG.getRoot();
3956 std::vector<SDOperand> Args = TLI.LowerArguments(F, SDL.DAG);
3959 for (Function::arg_iterator AI = F.arg_begin(), E = F.arg_end();
3961 if (!AI->use_empty()) {
3962 SDL.setValue(AI, Args[a]);
3964 // If this argument is live outside of the entry block, insert a copy from
3965 // whereever we got it to the vreg that other BB's will reference it as.
3966 if (FuncInfo.ValueMap.count(AI)) {
3968 SDL.CopyValueToVirtualRegister(AI, FuncInfo.ValueMap[AI]);
3969 UnorderedChains.push_back(Copy);
3973 // Finally, if the target has anything special to do, allow it to do so.
3974 // FIXME: this should insert code into the DAG!
3975 EmitFunctionEntryCode(F, SDL.DAG.getMachineFunction());
3978 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
3979 std::vector<std::pair<MachineInstr*, unsigned> > &PHINodesToUpdate,
3980 FunctionLoweringInfo &FuncInfo) {
3981 SelectionDAGLowering SDL(DAG, TLI, FuncInfo);
3983 std::vector<SDOperand> UnorderedChains;
3985 // Lower any arguments needed in this block if this is the entry block.
3986 if (LLVMBB == &LLVMBB->getParent()->front())
3987 LowerArguments(LLVMBB, SDL, UnorderedChains);
3989 BB = FuncInfo.MBBMap[LLVMBB];
3990 SDL.setCurrentBasicBlock(BB);
3992 // Lower all of the non-terminator instructions.
3993 for (BasicBlock::iterator I = LLVMBB->begin(), E = --LLVMBB->end();
3997 // Ensure that all instructions which are used outside of their defining
3998 // blocks are available as virtual registers.
3999 for (BasicBlock::iterator I = LLVMBB->begin(), E = LLVMBB->end(); I != E;++I)
4000 if (!I->use_empty() && !isa<PHINode>(I)) {
4001 std::map<const Value*, unsigned>::iterator VMI =FuncInfo.ValueMap.find(I);
4002 if (VMI != FuncInfo.ValueMap.end())
4003 UnorderedChains.push_back(
4004 SDL.CopyValueToVirtualRegister(I, VMI->second));
4007 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
4008 // ensure constants are generated when needed. Remember the virtual registers
4009 // that need to be added to the Machine PHI nodes as input. We cannot just
4010 // directly add them, because expansion might result in multiple MBB's for one
4011 // BB. As such, the start of the BB might correspond to a different MBB than
4014 TerminatorInst *TI = LLVMBB->getTerminator();
4016 // Emit constants only once even if used by multiple PHI nodes.
4017 std::map<Constant*, unsigned> ConstantsOut;
4019 // Vector bool would be better, but vector<bool> is really slow.
4020 std::vector<unsigned char> SuccsHandled;
4021 if (TI->getNumSuccessors())
4022 SuccsHandled.resize(BB->getParent()->getNumBlockIDs());
4024 // Check successor nodes PHI nodes that expect a constant to be available from
4026 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
4027 BasicBlock *SuccBB = TI->getSuccessor(succ);
4028 if (!isa<PHINode>(SuccBB->begin())) continue;
4029 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
4031 // If this terminator has multiple identical successors (common for
4032 // switches), only handle each succ once.
4033 unsigned SuccMBBNo = SuccMBB->getNumber();
4034 if (SuccsHandled[SuccMBBNo]) continue;
4035 SuccsHandled[SuccMBBNo] = true;
4037 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
4040 // At this point we know that there is a 1-1 correspondence between LLVM PHI
4041 // nodes and Machine PHI nodes, but the incoming operands have not been
4043 for (BasicBlock::iterator I = SuccBB->begin();
4044 (PN = dyn_cast<PHINode>(I)); ++I) {
4045 // Ignore dead phi's.
4046 if (PN->use_empty()) continue;
4049 Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
4051 if (Constant *C = dyn_cast<Constant>(PHIOp)) {
4052 unsigned &RegOut = ConstantsOut[C];
4054 RegOut = FuncInfo.CreateRegForValue(C);
4055 UnorderedChains.push_back(
4056 SDL.CopyValueToVirtualRegister(C, RegOut));
4060 Reg = FuncInfo.ValueMap[PHIOp];
4062 assert(isa<AllocaInst>(PHIOp) &&
4063 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
4064 "Didn't codegen value into a register!??");
4065 Reg = FuncInfo.CreateRegForValue(PHIOp);
4066 UnorderedChains.push_back(
4067 SDL.CopyValueToVirtualRegister(PHIOp, Reg));
4071 // Remember that this register needs to added to the machine PHI node as
4072 // the input for this MBB.
4073 MVT::ValueType VT = TLI.getValueType(PN->getType());
4074 unsigned NumElements;
4075 if (VT != MVT::Vector)
4076 NumElements = TLI.getNumElements(VT);
4078 MVT::ValueType VT1,VT2;
4080 TLI.getPackedTypeBreakdown(cast<PackedType>(PN->getType()),
4083 for (unsigned i = 0, e = NumElements; i != e; ++i)
4084 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
4087 ConstantsOut.clear();
4089 // Turn all of the unordered chains into one factored node.
4090 if (!UnorderedChains.empty()) {
4091 SDOperand Root = SDL.getRoot();
4092 if (Root.getOpcode() != ISD::EntryToken) {
4093 unsigned i = 0, e = UnorderedChains.size();
4094 for (; i != e; ++i) {
4095 assert(UnorderedChains[i].Val->getNumOperands() > 1);
4096 if (UnorderedChains[i].Val->getOperand(0) == Root)
4097 break; // Don't add the root if we already indirectly depend on it.
4101 UnorderedChains.push_back(Root);
4103 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
4104 &UnorderedChains[0], UnorderedChains.size()));
4107 // Lower the terminator after the copies are emitted.
4108 SDL.visit(*LLVMBB->getTerminator());
4110 // Copy over any CaseBlock records that may now exist due to SwitchInst
4111 // lowering, as well as any jump table information.
4112 SwitchCases.clear();
4113 SwitchCases = SDL.SwitchCases;
4116 // Make sure the root of the DAG is up-to-date.
4117 DAG.setRoot(SDL.getRoot());
4120 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
4121 // Get alias analysis for load/store combining.
4122 AliasAnalysis &AA = getAnalysis<AliasAnalysis>();
4124 // Run the DAG combiner in pre-legalize mode.
4125 DAG.Combine(false, AA);
4127 DOUT << "Lowered selection DAG:\n";
4130 // Second step, hack on the DAG until it only uses operations and types that
4131 // the target supports.
4134 DOUT << "Legalized selection DAG:\n";
4137 // Run the DAG combiner in post-legalize mode.
4138 DAG.Combine(true, AA);
4140 if (ViewISelDAGs) DAG.viewGraph();
4142 // Third, instruction select all of the operations to machine code, adding the
4143 // code to the MachineBasicBlock.
4144 InstructionSelectBasicBlock(DAG);
4146 DOUT << "Selected machine code:\n";
4150 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
4151 FunctionLoweringInfo &FuncInfo) {
4152 std::vector<std::pair<MachineInstr*, unsigned> > PHINodesToUpdate;
4154 SelectionDAG DAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
4157 // First step, lower LLVM code to some DAG. This DAG may use operations and
4158 // types that are not supported by the target.
4159 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
4161 // Second step, emit the lowered DAG as machine code.
4162 CodeGenAndEmitDAG(DAG);
4165 // Next, now that we know what the last MBB the LLVM BB expanded is, update
4166 // PHI nodes in successors.
4167 if (SwitchCases.empty() && JT.Reg == 0) {
4168 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4169 MachineInstr *PHI = PHINodesToUpdate[i].first;
4170 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4171 "This is not a machine PHI node that we are updating!");
4172 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
4173 PHI->addMachineBasicBlockOperand(BB);
4178 // If the JumpTable record is filled in, then we need to emit a jump table.
4179 // Updating the PHI nodes is tricky in this case, since we need to determine
4180 // whether the PHI is a successor of the range check MBB or the jump table MBB
4182 assert(SwitchCases.empty() && "Cannot have jump table and lowered switch");
4183 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
4185 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
4186 MachineBasicBlock *RangeBB = BB;
4187 // Set the current basic block to the mbb we wish to insert the code into
4189 SDL.setCurrentBasicBlock(BB);
4191 SDL.visitJumpTable(JT);
4192 SDAG.setRoot(SDL.getRoot());
4193 CodeGenAndEmitDAG(SDAG);
4195 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
4196 MachineInstr *PHI = PHINodesToUpdate[pi].first;
4197 MachineBasicBlock *PHIBB = PHI->getParent();
4198 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4199 "This is not a machine PHI node that we are updating!");
4200 if (PHIBB == JT.Default) {
4201 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4202 PHI->addMachineBasicBlockOperand(RangeBB);
4204 if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) {
4205 PHI->addRegOperand(PHINodesToUpdate[pi].second, false);
4206 PHI->addMachineBasicBlockOperand(BB);
4212 // If the switch block involved a branch to one of the actual successors, we
4213 // need to update PHI nodes in that block.
4214 for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i) {
4215 MachineInstr *PHI = PHINodesToUpdate[i].first;
4216 assert(PHI->getOpcode() == TargetInstrInfo::PHI &&
4217 "This is not a machine PHI node that we are updating!");
4218 if (BB->isSuccessor(PHI->getParent())) {
4219 PHI->addRegOperand(PHINodesToUpdate[i].second, false);
4220 PHI->addMachineBasicBlockOperand(BB);
4224 // If we generated any switch lowering information, build and codegen any
4225 // additional DAGs necessary.
4226 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
4227 SelectionDAG SDAG(TLI, MF, getAnalysisToUpdate<MachineDebugInfo>());
4229 SelectionDAGLowering SDL(SDAG, TLI, FuncInfo);
4231 // Set the current basic block to the mbb we wish to insert the code into
4232 BB = SwitchCases[i].ThisBB;
4233 SDL.setCurrentBasicBlock(BB);
4236 SDL.visitSwitchCase(SwitchCases[i]);
4237 SDAG.setRoot(SDL.getRoot());
4238 CodeGenAndEmitDAG(SDAG);
4240 // Handle any PHI nodes in successors of this chunk, as if we were coming
4241 // from the original BB before switch expansion. Note that PHI nodes can
4242 // occur multiple times in PHINodesToUpdate. We have to be very careful to
4243 // handle them the right number of times.
4244 while ((BB = SwitchCases[i].TrueBB)) { // Handle LHS and RHS.
4245 for (MachineBasicBlock::iterator Phi = BB->begin();
4246 Phi != BB->end() && Phi->getOpcode() == TargetInstrInfo::PHI; ++Phi){
4247 // This value for this PHI node is recorded in PHINodesToUpdate, get it.
4248 for (unsigned pn = 0; ; ++pn) {
4249 assert(pn != PHINodesToUpdate.size() && "Didn't find PHI entry!");
4250 if (PHINodesToUpdate[pn].first == Phi) {
4251 Phi->addRegOperand(PHINodesToUpdate[pn].second, false);
4252 Phi->addMachineBasicBlockOperand(SwitchCases[i].ThisBB);
4258 // Don't process RHS if same block as LHS.
4259 if (BB == SwitchCases[i].FalseBB)
4260 SwitchCases[i].FalseBB = 0;
4262 // If we haven't handled the RHS, do so now. Otherwise, we're done.
4263 SwitchCases[i].TrueBB = SwitchCases[i].FalseBB;
4264 SwitchCases[i].FalseBB = 0;
4266 assert(SwitchCases[i].TrueBB == 0 && SwitchCases[i].FalseBB == 0);
4271 //===----------------------------------------------------------------------===//
4272 /// ScheduleAndEmitDAG - Pick a safe ordering and emit instructions for each
4273 /// target node in the graph.
4274 void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
4275 if (ViewSchedDAGs) DAG.viewGraph();
4277 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
4281 RegisterScheduler::setDefault(Ctor);
4284 ScheduleDAG *SL = Ctor(this, &DAG, BB);
4290 HazardRecognizer *SelectionDAGISel::CreateTargetHazardRecognizer() {
4291 return new HazardRecognizer();
4294 //===----------------------------------------------------------------------===//
4295 // Helper functions used by the generated instruction selector.
4296 //===----------------------------------------------------------------------===//
4297 // Calls to these methods are generated by tblgen.
4299 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
4300 /// the dag combiner simplified the 255, we still want to match. RHS is the
4301 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
4302 /// specified in the .td file (e.g. 255).
4303 bool SelectionDAGISel::CheckAndMask(SDOperand LHS, ConstantSDNode *RHS,
4304 int64_t DesiredMaskS) {
4305 uint64_t ActualMask = RHS->getValue();
4306 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
4308 // If the actual mask exactly matches, success!
4309 if (ActualMask == DesiredMask)
4312 // If the actual AND mask is allowing unallowed bits, this doesn't match.
4313 if (ActualMask & ~DesiredMask)
4316 // Otherwise, the DAG Combiner may have proven that the value coming in is
4317 // either already zero or is not demanded. Check for known zero input bits.
4318 uint64_t NeededMask = DesiredMask & ~ActualMask;
4319 if (getTargetLowering().MaskedValueIsZero(LHS, NeededMask))
4322 // TODO: check to see if missing bits are just not demanded.
4324 // Otherwise, this pattern doesn't match.
4328 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
4329 /// the dag combiner simplified the 255, we still want to match. RHS is the
4330 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
4331 /// specified in the .td file (e.g. 255).
4332 bool SelectionDAGISel::CheckOrMask(SDOperand LHS, ConstantSDNode *RHS,
4333 int64_t DesiredMaskS) {
4334 uint64_t ActualMask = RHS->getValue();
4335 uint64_t DesiredMask =DesiredMaskS & MVT::getIntVTBitMask(LHS.getValueType());
4337 // If the actual mask exactly matches, success!
4338 if (ActualMask == DesiredMask)
4341 // If the actual AND mask is allowing unallowed bits, this doesn't match.
4342 if (ActualMask & ~DesiredMask)
4345 // Otherwise, the DAG Combiner may have proven that the value coming in is
4346 // either already zero or is not demanded. Check for known zero input bits.
4347 uint64_t NeededMask = DesiredMask & ~ActualMask;
4349 uint64_t KnownZero, KnownOne;
4350 getTargetLowering().ComputeMaskedBits(LHS, NeededMask, KnownZero, KnownOne);
4352 // If all the missing bits in the or are already known to be set, match!
4353 if ((NeededMask & KnownOne) == NeededMask)
4356 // TODO: check to see if missing bits are just not demanded.
4358 // Otherwise, this pattern doesn't match.
4363 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
4364 /// by tblgen. Others should not call it.
4365 void SelectionDAGISel::
4366 SelectInlineAsmMemoryOperands(std::vector<SDOperand> &Ops, SelectionDAG &DAG) {
4367 std::vector<SDOperand> InOps;
4368 std::swap(InOps, Ops);
4370 Ops.push_back(InOps[0]); // input chain.
4371 Ops.push_back(InOps[1]); // input asm string.
4373 unsigned i = 2, e = InOps.size();
4374 if (InOps[e-1].getValueType() == MVT::Flag)
4375 --e; // Don't process a flag operand if it is here.
4378 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getValue();
4379 if ((Flags & 7) != 4 /*MEM*/) {
4380 // Just skip over this operand, copying the operands verbatim.
4381 Ops.insert(Ops.end(), InOps.begin()+i, InOps.begin()+i+(Flags >> 3) + 1);
4382 i += (Flags >> 3) + 1;
4384 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
4385 // Otherwise, this is a memory operand. Ask the target to select it.
4386 std::vector<SDOperand> SelOps;
4387 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
4388 cerr << "Could not match memory address. Inline asm failure!\n";
4392 // Add this to the output node.
4393 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
4395 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
4400 // Add the flag input back if present.
4401 if (e != InOps.size())
4402 Ops.push_back(InOps.back());