1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "llvm/CodeGen/SelectionDAGISel.h"
16 #include "ScheduleDAGSDNodes.h"
17 #include "SelectionDAGBuilder.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/FastISel.h"
24 #include "llvm/CodeGen/FunctionLoweringInfo.h"
25 #include "llvm/CodeGen/GCMetadata.h"
26 #include "llvm/CodeGen/GCStrategy.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/DebugInfo.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/InlineAsm.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/IntrinsicInst.h"
41 #include "llvm/IR/Intrinsics.h"
42 #include "llvm/IR/LLVMContext.h"
43 #include "llvm/IR/Module.h"
44 #include "llvm/Support/Compiler.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/Timer.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLibraryInfo.h"
52 #include "llvm/Target/TargetLowering.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "llvm/Target/TargetRegisterInfo.h"
56 #include "llvm/Target/TargetSubtargetInfo.h"
57 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
61 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
62 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
63 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
64 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
65 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
69 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
70 cl::desc("Enable extra verbose messages in the \"fast\" "
71 "instruction selector"));
73 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
74 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
75 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
76 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
77 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
78 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
79 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
81 // Standard binary operators...
82 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
83 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
84 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
85 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
86 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
87 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
88 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
89 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
90 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
91 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
92 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
93 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
95 // Logical operators...
96 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
97 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
98 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
100 // Memory instructions...
101 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
102 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
103 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
104 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
105 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
106 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
107 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
109 // Convert instructions...
110 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
111 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
112 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
113 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
114 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
115 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
116 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
117 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
118 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
119 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
120 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
121 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
123 // Other instructions...
124 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
125 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
126 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
127 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
128 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
129 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
130 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
131 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
132 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
133 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
134 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
135 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
136 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
137 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
138 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
142 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
143 cl::desc("Enable verbose messages in the \"fast\" "
144 "instruction selector"));
146 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
147 cl::desc("Enable abort calls when \"fast\" instruction fails"));
151 cl::desc("use Machine Branch Probability Info"),
152 cl::init(true), cl::Hidden);
156 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
157 cl::desc("Pop up a window to show dags before the first "
158 "dag combine pass"));
160 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
161 cl::desc("Pop up a window to show dags before legalize types"));
163 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
164 cl::desc("Pop up a window to show dags before legalize"));
166 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
167 cl::desc("Pop up a window to show dags before the second "
168 "dag combine pass"));
170 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
171 cl::desc("Pop up a window to show dags before the post legalize types"
172 " dag combine pass"));
174 ViewISelDAGs("view-isel-dags", cl::Hidden,
175 cl::desc("Pop up a window to show isel dags as they are selected"));
177 ViewSchedDAGs("view-sched-dags", cl::Hidden,
178 cl::desc("Pop up a window to show sched dags as they are processed"));
180 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
181 cl::desc("Pop up a window to show SUnit dags after they are processed"));
183 static const bool ViewDAGCombine1 = false,
184 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
185 ViewDAGCombine2 = false,
186 ViewDAGCombineLT = false,
187 ViewISelDAGs = false, ViewSchedDAGs = false,
188 ViewSUnitDAGs = false;
191 //===---------------------------------------------------------------------===//
193 /// RegisterScheduler class - Track the registration of instruction schedulers.
195 //===---------------------------------------------------------------------===//
196 MachinePassRegistry RegisterScheduler::Registry;
198 //===---------------------------------------------------------------------===//
200 /// ISHeuristic command line option for instruction schedulers.
202 //===---------------------------------------------------------------------===//
203 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
204 RegisterPassParser<RegisterScheduler> >
205 ISHeuristic("pre-RA-sched",
206 cl::init(&createDefaultScheduler),
207 cl::desc("Instruction schedulers available (before register"
210 static RegisterScheduler
211 defaultListDAGScheduler("default", "Best scheduler for the target",
212 createDefaultScheduler);
215 //===--------------------------------------------------------------------===//
216 /// createDefaultScheduler - This creates an instruction scheduler appropriate
218 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
219 CodeGenOpt::Level OptLevel) {
220 const TargetLowering &TLI = IS->getTargetLowering();
221 const TargetSubtargetInfo &ST = IS->TM.getSubtarget<TargetSubtargetInfo>();
223 if (OptLevel == CodeGenOpt::None || ST.enableMachineScheduler() ||
224 TLI.getSchedulingPreference() == Sched::Source)
225 return createSourceListDAGScheduler(IS, OptLevel);
226 if (TLI.getSchedulingPreference() == Sched::RegPressure)
227 return createBURRListDAGScheduler(IS, OptLevel);
228 if (TLI.getSchedulingPreference() == Sched::Hybrid)
229 return createHybridListDAGScheduler(IS, OptLevel);
230 if (TLI.getSchedulingPreference() == Sched::VLIW)
231 return createVLIWDAGScheduler(IS, OptLevel);
232 assert(TLI.getSchedulingPreference() == Sched::ILP &&
233 "Unknown sched type!");
234 return createILPListDAGScheduler(IS, OptLevel);
238 // EmitInstrWithCustomInserter - This method should be implemented by targets
239 // that mark instructions with the 'usesCustomInserter' flag. These
240 // instructions are special in various ways, which require special support to
241 // insert. The specified MachineInstr is created but not inserted into any
242 // basic blocks, and this method is called to expand it into a sequence of
243 // instructions, potentially also creating new basic blocks and control flow.
244 // When new basic blocks are inserted and the edges from MBB to its successors
245 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
248 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
249 MachineBasicBlock *MBB) const {
251 dbgs() << "If a target marks an instruction with "
252 "'usesCustomInserter', it must implement "
253 "TargetLowering::EmitInstrWithCustomInserter!";
258 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
259 SDNode *Node) const {
260 assert(!MI->hasPostISelHook() &&
261 "If a target marks an instruction with 'hasPostISelHook', "
262 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
265 //===----------------------------------------------------------------------===//
266 // SelectionDAGISel code
267 //===----------------------------------------------------------------------===//
269 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm,
270 CodeGenOpt::Level OL) :
271 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()),
272 FuncInfo(new FunctionLoweringInfo(TLI)),
273 CurDAG(new SelectionDAG(tm, OL)),
274 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
278 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
279 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
280 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
281 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry());
284 SelectionDAGISel::~SelectionDAGISel() {
290 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
291 AU.addRequired<AliasAnalysis>();
292 AU.addPreserved<AliasAnalysis>();
293 AU.addRequired<GCModuleInfo>();
294 AU.addPreserved<GCModuleInfo>();
295 AU.addRequired<TargetLibraryInfo>();
296 if (UseMBPI && OptLevel != CodeGenOpt::None)
297 AU.addRequired<BranchProbabilityInfo>();
298 MachineFunctionPass::getAnalysisUsage(AU);
301 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
302 /// may trap on it. In this case we have to split the edge so that the path
303 /// through the predecessor block that doesn't go to the phi block doesn't
304 /// execute the possibly trapping instruction.
306 /// This is required for correctness, so it must be done at -O0.
308 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) {
309 // Loop for blocks with phi nodes.
310 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
311 PHINode *PN = dyn_cast<PHINode>(BB->begin());
312 if (PN == 0) continue;
315 // For each block with a PHI node, check to see if any of the input values
316 // are potentially trapping constant expressions. Constant expressions are
317 // the only potentially trapping value that can occur as the argument to a
319 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
320 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
321 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
322 if (CE == 0 || !CE->canTrap()) continue;
324 // The only case we have to worry about is when the edge is critical.
325 // Since this block has a PHI Node, we assume it has multiple input
326 // edges: check to see if the pred has multiple successors.
327 BasicBlock *Pred = PN->getIncomingBlock(i);
328 if (Pred->getTerminator()->getNumSuccessors() == 1)
331 // Okay, we have to split this edge.
332 SplitCriticalEdge(Pred->getTerminator(),
333 GetSuccessorNumber(Pred, BB), SDISel, true);
339 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
340 // Do some sanity-checking on the command-line options.
341 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
342 "-fast-isel-verbose requires -fast-isel");
343 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
344 "-fast-isel-abort requires -fast-isel");
346 const Function &Fn = *mf.getFunction();
347 const TargetInstrInfo &TII = *TM.getInstrInfo();
348 const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
351 RegInfo = &MF->getRegInfo();
352 AA = &getAnalysis<AliasAnalysis>();
353 LibInfo = &getAnalysis<TargetLibraryInfo>();
354 TTI = getAnalysisIfAvailable<TargetTransformInfo>();
355 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0;
357 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
359 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this);
361 CurDAG->init(*MF, TTI);
362 FuncInfo->set(Fn, *MF);
364 if (UseMBPI && OptLevel != CodeGenOpt::None)
365 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
369 SDB->init(GFI, *AA, LibInfo);
371 SelectAllBasicBlocks(Fn);
373 // If the first basic block in the function has live ins that need to be
374 // copied into vregs, emit the copies into the top of the block before
375 // emitting the code for the block.
376 MachineBasicBlock *EntryMBB = MF->begin();
377 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII);
379 DenseMap<unsigned, unsigned> LiveInMap;
380 if (!FuncInfo->ArgDbgValues.empty())
381 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
382 E = RegInfo->livein_end(); LI != E; ++LI)
384 LiveInMap.insert(std::make_pair(LI->first, LI->second));
386 // Insert DBG_VALUE instructions for function arguments to the entry block.
387 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
388 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
389 unsigned Reg = MI->getOperand(0).getReg();
390 if (TargetRegisterInfo::isPhysicalRegister(Reg))
391 EntryMBB->insert(EntryMBB->begin(), MI);
393 MachineInstr *Def = RegInfo->getVRegDef(Reg);
394 MachineBasicBlock::iterator InsertPos = Def;
395 // FIXME: VR def may not be in entry block.
396 Def->getParent()->insert(llvm::next(InsertPos), MI);
399 // If Reg is live-in then update debug info to track its copy in a vreg.
400 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
401 if (LDI != LiveInMap.end()) {
402 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
403 MachineBasicBlock::iterator InsertPos = Def;
404 const MDNode *Variable =
405 MI->getOperand(MI->getNumOperands()-1).getMetadata();
406 unsigned Offset = MI->getOperand(1).getImm();
407 // Def is never a terminator here, so it is ok to increment InsertPos.
408 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
409 TII.get(TargetOpcode::DBG_VALUE))
410 .addReg(LDI->second, RegState::Debug)
411 .addImm(Offset).addMetadata(Variable);
413 // If this vreg is directly copied into an exported register then
414 // that COPY instructions also need DBG_VALUE, if it is the only
415 // user of LDI->second.
416 MachineInstr *CopyUseMI = NULL;
417 for (MachineRegisterInfo::use_iterator
418 UI = RegInfo->use_begin(LDI->second);
419 MachineInstr *UseMI = UI.skipInstruction();) {
420 if (UseMI->isDebugValue()) continue;
421 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
422 CopyUseMI = UseMI; continue;
424 // Otherwise this is another use or second copy use.
425 CopyUseMI = NULL; break;
428 MachineInstr *NewMI =
429 BuildMI(*MF, CopyUseMI->getDebugLoc(),
430 TII.get(TargetOpcode::DBG_VALUE))
431 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug)
432 .addImm(Offset).addMetadata(Variable);
433 MachineBasicBlock::iterator Pos = CopyUseMI;
434 EntryMBB->insertAfter(Pos, NewMI);
439 // Determine if there are any calls in this machine function.
440 MachineFrameInfo *MFI = MF->getFrameInfo();
441 if (!MFI->hasCalls()) {
442 for (MachineFunction::const_iterator
443 I = MF->begin(), E = MF->end(); I != E; ++I) {
444 const MachineBasicBlock *MBB = I;
445 for (MachineBasicBlock::const_iterator
446 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) {
447 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode());
449 if ((MCID.isCall() && !MCID.isReturn()) ||
450 II->isStackAligningInlineAsm()) {
451 MFI->setHasCalls(true);
459 // Determine if there is a call to setjmp in the machine function.
460 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
462 // Replace forward-declared registers with the registers containing
463 // the desired value.
464 MachineRegisterInfo &MRI = MF->getRegInfo();
465 for (DenseMap<unsigned, unsigned>::iterator
466 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
468 unsigned From = I->first;
469 unsigned To = I->second;
470 // If To is also scheduled to be replaced, find what its ultimate
473 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
478 MRI.replaceRegWith(From, To);
481 // Freeze the set of reserved registers now that MachineFrameInfo has been
482 // set up. All the information required by getReservedRegs() should be
484 MRI.freezeReservedRegs(*MF);
486 // Release function-specific state. SDB and CurDAG are already cleared
493 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
494 BasicBlock::const_iterator End,
496 // Lower all of the non-terminator instructions. If a call is emitted
497 // as a tail call, cease emitting nodes for this block. Terminators
498 // are handled below.
499 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
502 // Make sure the root of the DAG is up-to-date.
503 CurDAG->setRoot(SDB->getControlRoot());
504 HadTailCall = SDB->HasTailCall;
507 // Final step, emit the lowered DAG as machine code.
511 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
512 SmallPtrSet<SDNode*, 128> VisitedNodes;
513 SmallVector<SDNode*, 128> Worklist;
515 Worklist.push_back(CurDAG->getRoot().getNode());
521 SDNode *N = Worklist.pop_back_val();
523 // If we've already seen this node, ignore it.
524 if (!VisitedNodes.insert(N))
527 // Otherwise, add all chain operands to the worklist.
528 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
529 if (N->getOperand(i).getValueType() == MVT::Other)
530 Worklist.push_back(N->getOperand(i).getNode());
532 // If this is a CopyToReg with a vreg dest, process it.
533 if (N->getOpcode() != ISD::CopyToReg)
536 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
537 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
540 // Ignore non-scalar or non-integer values.
541 SDValue Src = N->getOperand(2);
542 EVT SrcVT = Src.getValueType();
543 if (!SrcVT.isInteger() || SrcVT.isVector())
546 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
547 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne);
548 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
549 } while (!Worklist.empty());
552 void SelectionDAGISel::CodeGenAndEmitDAG() {
553 std::string GroupName;
554 if (TimePassesIsEnabled)
555 GroupName = "Instruction Selection and Scheduling";
556 std::string BlockName;
557 int BlockNumber = -1;
560 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
561 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
565 BlockNumber = FuncInfo->MBB->getNumber();
566 BlockName = MF->getName().str() + ":" +
567 FuncInfo->MBB->getBasicBlock()->getName().str();
569 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
570 << " '" << BlockName << "'\n"; CurDAG->dump());
572 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
574 // Run the DAG combiner in pre-legalize mode.
576 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
577 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
580 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
581 << " '" << BlockName << "'\n"; CurDAG->dump());
583 // Second step, hack on the DAG until it only uses operations and types that
584 // the target supports.
585 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
590 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
591 Changed = CurDAG->LegalizeTypes();
594 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
595 << " '" << BlockName << "'\n"; CurDAG->dump());
598 if (ViewDAGCombineLT)
599 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
601 // Run the DAG combiner in post-type-legalize mode.
603 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
604 TimePassesIsEnabled);
605 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
608 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
609 << " '" << BlockName << "'\n"; CurDAG->dump());
613 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
614 Changed = CurDAG->LegalizeVectors();
619 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
620 CurDAG->LegalizeTypes();
623 if (ViewDAGCombineLT)
624 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
626 // Run the DAG combiner in post-type-legalize mode.
628 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
629 TimePassesIsEnabled);
630 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
633 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
634 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
637 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
640 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
644 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
645 << " '" << BlockName << "'\n"; CurDAG->dump());
647 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
649 // Run the DAG combiner in post-legalize mode.
651 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
652 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
655 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
656 << " '" << BlockName << "'\n"; CurDAG->dump());
658 if (OptLevel != CodeGenOpt::None)
659 ComputeLiveOutVRegInfo();
661 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
663 // Third, instruction select all of the operations to machine code, adding the
664 // code to the MachineBasicBlock.
666 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
667 DoInstructionSelection();
670 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
671 << " '" << BlockName << "'\n"; CurDAG->dump());
673 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
675 // Schedule machine code.
676 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
678 NamedRegionTimer T("Instruction Scheduling", GroupName,
679 TimePassesIsEnabled);
680 Scheduler->Run(CurDAG, FuncInfo->MBB);
683 if (ViewSUnitDAGs) Scheduler->viewGraph();
685 // Emit machine code to BB. This can change 'BB' to the last block being
687 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
689 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
691 // FuncInfo->InsertPt is passed by reference and set to the end of the
692 // scheduled instructions.
693 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
696 // If the block was split, make sure we update any references that are used to
697 // update PHI nodes later on.
698 if (FirstMBB != LastMBB)
699 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
701 // Free the scheduler state.
703 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
704 TimePassesIsEnabled);
708 // Free the SelectionDAG state, now that we're finished with it.
713 /// ISelUpdater - helper class to handle updates of the instruction selection
715 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
716 SelectionDAG::allnodes_iterator &ISelPosition;
718 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
719 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
721 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
722 /// deleted is the current ISelPosition node, update ISelPosition.
724 virtual void NodeDeleted(SDNode *N, SDNode *E) {
725 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
729 } // end anonymous namespace
731 void SelectionDAGISel::DoInstructionSelection() {
732 DEBUG(errs() << "===== Instruction selection begins: BB#"
733 << FuncInfo->MBB->getNumber()
734 << " '" << FuncInfo->MBB->getName() << "'\n");
738 // Select target instructions for the DAG.
740 // Number all nodes with a topological order and set DAGSize.
741 DAGSize = CurDAG->AssignTopologicalOrder();
743 // Create a dummy node (which is not added to allnodes), that adds
744 // a reference to the root node, preventing it from being deleted,
745 // and tracking any changes of the root.
746 HandleSDNode Dummy(CurDAG->getRoot());
747 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
750 // Make sure that ISelPosition gets properly updated when nodes are deleted
751 // in calls made from this function.
752 ISelUpdater ISU(*CurDAG, ISelPosition);
754 // The AllNodes list is now topological-sorted. Visit the
755 // nodes by starting at the end of the list (the root of the
756 // graph) and preceding back toward the beginning (the entry
758 while (ISelPosition != CurDAG->allnodes_begin()) {
759 SDNode *Node = --ISelPosition;
760 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
761 // but there are currently some corner cases that it misses. Also, this
762 // makes it theoretically possible to disable the DAGCombiner.
763 if (Node->use_empty())
766 SDNode *ResNode = Select(Node);
768 // FIXME: This is pretty gross. 'Select' should be changed to not return
769 // anything at all and this code should be nuked with a tactical strike.
771 // If node should not be replaced, continue with the next one.
772 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
776 ReplaceUses(Node, ResNode);
778 // If after the replacement this node is not used any more,
779 // remove this dead node.
780 if (Node->use_empty()) // Don't delete EntryToken, etc.
781 CurDAG->RemoveDeadNode(Node);
784 CurDAG->setRoot(Dummy.getValue());
787 DEBUG(errs() << "===== Instruction selection ends:\n");
789 PostprocessISelDAG();
792 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
793 /// do other setup for EH landing-pad blocks.
794 void SelectionDAGISel::PrepareEHLandingPad() {
795 MachineBasicBlock *MBB = FuncInfo->MBB;
797 // Add a label to mark the beginning of the landing pad. Deletion of the
798 // landing pad can thus be detected via the MachineModuleInfo.
799 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
801 // Assign the call site to the landing pad's begin label.
802 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
804 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
805 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
808 // Mark exception register as live in.
809 unsigned Reg = TLI.getExceptionPointerRegister();
810 if (Reg) MBB->addLiveIn(Reg);
812 // Mark exception selector register as live in.
813 Reg = TLI.getExceptionSelectorRegister();
814 if (Reg) MBB->addLiveIn(Reg);
817 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified
818 /// load into the specified FoldInst. Note that we could have a sequence where
819 /// multiple LLVM IR instructions are folded into the same machineinstr. For
820 /// example we could have:
821 /// A: x = load i32 *P
822 /// B: y = icmp A, 42
825 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and
826 /// any other folded instructions) because it is between A and C.
828 /// If we succeed in folding the load into the operation, return true.
830 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI,
831 const Instruction *FoldInst,
833 // We know that the load has a single use, but don't know what it is. If it
834 // isn't one of the folded instructions, then we can't succeed here. Handle
835 // this by scanning the single-use users of the load until we get to FoldInst.
836 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
838 const Instruction *TheUser = LI->use_back();
839 while (TheUser != FoldInst && // Scan up until we find FoldInst.
840 // Stay in the right block.
841 TheUser->getParent() == FoldInst->getParent() &&
842 --MaxUsers) { // Don't scan too far.
843 // If there are multiple or no uses of this instruction, then bail out.
844 if (!TheUser->hasOneUse())
847 TheUser = TheUser->use_back();
850 // If we didn't find the fold instruction, then we failed to collapse the
852 if (TheUser != FoldInst)
855 // Don't try to fold volatile loads. Target has to deal with alignment
857 if (LI->isVolatile()) return false;
859 // Figure out which vreg this is going into. If there is no assigned vreg yet
860 // then there actually was no reference to it. Perhaps the load is referenced
861 // by a dead instruction.
862 unsigned LoadReg = FastIS->getRegForValue(LI);
866 // Check to see what the uses of this vreg are. If it has no uses, or more
867 // than one use (at the machine instr level) then we can't fold it.
868 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg);
869 if (RI == RegInfo->reg_end())
872 // See if there is exactly one use of the vreg. If there are multiple uses,
873 // then the instruction got lowered to multiple machine instructions or the
874 // use of the loaded value ended up being multiple operands of the result, in
875 // either case, we can't fold this.
876 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI;
877 if (PostRI != RegInfo->reg_end())
880 assert(RI.getOperand().isUse() &&
881 "The only use of the vreg must be a use, we haven't emitted the def!");
883 MachineInstr *User = &*RI;
885 // Set the insertion point properly. Folding the load can cause generation of
886 // other random instructions (like sign extends) for addressing modes, make
887 // sure they get inserted in a logical place before the new instruction.
888 FuncInfo->InsertPt = User;
889 FuncInfo->MBB = User->getParent();
891 // Ask the target to try folding the load.
892 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI);
895 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
896 /// side-effect free and is either dead or folded into a generated instruction.
897 /// Return false if it needs to be emitted.
898 static bool isFoldedOrDeadInstruction(const Instruction *I,
899 FunctionLoweringInfo *FuncInfo) {
900 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
901 !isa<TerminatorInst>(I) && // Terminators aren't folded.
902 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
903 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
904 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
908 // Collect per Instruction statistics for fast-isel misses. Only those
909 // instructions that cause the bail are accounted for. It does not account for
910 // instructions higher in the block. Thus, summing the per instructions stats
911 // will not add up to what is reported by NumFastIselFailures.
912 static void collectFailStats(const Instruction *I) {
913 switch (I->getOpcode()) {
914 default: assert (0 && "<Invalid operator> ");
917 case Instruction::Ret: NumFastIselFailRet++; return;
918 case Instruction::Br: NumFastIselFailBr++; return;
919 case Instruction::Switch: NumFastIselFailSwitch++; return;
920 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
921 case Instruction::Invoke: NumFastIselFailInvoke++; return;
922 case Instruction::Resume: NumFastIselFailResume++; return;
923 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
925 // Standard binary operators...
926 case Instruction::Add: NumFastIselFailAdd++; return;
927 case Instruction::FAdd: NumFastIselFailFAdd++; return;
928 case Instruction::Sub: NumFastIselFailSub++; return;
929 case Instruction::FSub: NumFastIselFailFSub++; return;
930 case Instruction::Mul: NumFastIselFailMul++; return;
931 case Instruction::FMul: NumFastIselFailFMul++; return;
932 case Instruction::UDiv: NumFastIselFailUDiv++; return;
933 case Instruction::SDiv: NumFastIselFailSDiv++; return;
934 case Instruction::FDiv: NumFastIselFailFDiv++; return;
935 case Instruction::URem: NumFastIselFailURem++; return;
936 case Instruction::SRem: NumFastIselFailSRem++; return;
937 case Instruction::FRem: NumFastIselFailFRem++; return;
939 // Logical operators...
940 case Instruction::And: NumFastIselFailAnd++; return;
941 case Instruction::Or: NumFastIselFailOr++; return;
942 case Instruction::Xor: NumFastIselFailXor++; return;
944 // Memory instructions...
945 case Instruction::Alloca: NumFastIselFailAlloca++; return;
946 case Instruction::Load: NumFastIselFailLoad++; return;
947 case Instruction::Store: NumFastIselFailStore++; return;
948 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
949 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
950 case Instruction::Fence: NumFastIselFailFence++; return;
951 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
953 // Convert instructions...
954 case Instruction::Trunc: NumFastIselFailTrunc++; return;
955 case Instruction::ZExt: NumFastIselFailZExt++; return;
956 case Instruction::SExt: NumFastIselFailSExt++; return;
957 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
958 case Instruction::FPExt: NumFastIselFailFPExt++; return;
959 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
960 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
961 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
962 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
963 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
964 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
965 case Instruction::BitCast: NumFastIselFailBitCast++; return;
967 // Other instructions...
968 case Instruction::ICmp: NumFastIselFailICmp++; return;
969 case Instruction::FCmp: NumFastIselFailFCmp++; return;
970 case Instruction::PHI: NumFastIselFailPHI++; return;
971 case Instruction::Select: NumFastIselFailSelect++; return;
972 case Instruction::Call: NumFastIselFailCall++; return;
973 case Instruction::Shl: NumFastIselFailShl++; return;
974 case Instruction::LShr: NumFastIselFailLShr++; return;
975 case Instruction::AShr: NumFastIselFailAShr++; return;
976 case Instruction::VAArg: NumFastIselFailVAArg++; return;
977 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
978 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
979 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
980 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
981 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
982 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
987 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
988 // Initialize the Fast-ISel state, if needed.
989 FastISel *FastIS = 0;
990 if (TM.Options.EnableFastISel)
991 FastIS = TLI.createFastISel(*FuncInfo, LibInfo);
993 // Iterate over all basic blocks in the function.
994 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
995 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
996 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
997 const BasicBlock *LLVMBB = *I;
999 if (OptLevel != CodeGenOpt::None) {
1000 bool AllPredsVisited = true;
1001 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1003 if (!FuncInfo->VisitedBBs.count(*PI)) {
1004 AllPredsVisited = false;
1009 if (AllPredsVisited) {
1010 for (BasicBlock::const_iterator I = LLVMBB->begin();
1011 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1012 FuncInfo->ComputePHILiveOutRegInfo(PN);
1014 for (BasicBlock::const_iterator I = LLVMBB->begin();
1015 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1016 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1019 FuncInfo->VisitedBBs.insert(LLVMBB);
1022 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1023 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1025 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1026 BasicBlock::const_iterator const End = LLVMBB->end();
1027 BasicBlock::const_iterator BI = End;
1029 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1031 // Setup an EH landing-pad block.
1032 if (FuncInfo->MBB->isLandingPad())
1033 PrepareEHLandingPad();
1035 // Lower any arguments needed in this block if this is the entry block.
1036 if (LLVMBB == &Fn.getEntryBlock())
1037 LowerArguments(LLVMBB);
1039 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1041 FastIS->startNewBlock();
1043 // Emit code for any incoming arguments. This must happen before
1044 // beginning FastISel on the entry block.
1045 if (LLVMBB == &Fn.getEntryBlock()) {
1046 CurDAG->setRoot(SDB->getControlRoot());
1048 CodeGenAndEmitDAG();
1050 // If we inserted any instructions at the beginning, make a note of
1051 // where they are, so we can be sure to emit subsequent instructions
1053 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1054 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
1056 FastIS->setLastLocalValue(0);
1059 unsigned NumFastIselRemaining = std::distance(Begin, End);
1060 // Do FastISel on as many instructions as possible.
1061 for (; BI != Begin; --BI) {
1062 const Instruction *Inst = llvm::prior(BI);
1064 // If we no longer require this instruction, skip it.
1065 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1066 --NumFastIselRemaining;
1070 // Bottom-up: reset the insert pos at the top, after any local-value
1072 FastIS->recomputeInsertPt();
1074 // Try to select the instruction with FastISel.
1075 if (FastIS->SelectInstruction(Inst)) {
1076 --NumFastIselRemaining;
1077 ++NumFastIselSuccess;
1078 // If fast isel succeeded, skip over all the folded instructions, and
1079 // then see if there is a load right before the selected instructions.
1080 // Try to fold the load if so.
1081 const Instruction *BeforeInst = Inst;
1082 while (BeforeInst != Begin) {
1083 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst));
1084 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1087 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1088 BeforeInst->hasOneUse() &&
1089 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) {
1090 // If we succeeded, don't re-select the load.
1091 BI = llvm::next(BasicBlock::const_iterator(BeforeInst));
1092 --NumFastIselRemaining;
1093 ++NumFastIselSuccess;
1099 if (EnableFastISelVerbose2)
1100 collectFailStats(Inst);
1103 // Then handle certain instructions as single-LLVM-Instruction blocks.
1104 if (isa<CallInst>(Inst)) {
1106 if (EnableFastISelVerbose || EnableFastISelAbort) {
1107 dbgs() << "FastISel missed call: ";
1111 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1112 unsigned &R = FuncInfo->ValueMap[Inst];
1114 R = FuncInfo->CreateRegs(Inst->getType());
1117 bool HadTailCall = false;
1118 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1119 SelectBasicBlock(Inst, BI, HadTailCall);
1121 // If the call was emitted as a tail call, we're done with the block.
1122 // We also need to delete any previously emitted instructions.
1124 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1129 // Recompute NumFastIselRemaining as Selection DAG instruction
1130 // selection may have handled the call, input args, etc.
1131 unsigned RemainingNow = std::distance(Begin, BI);
1132 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1133 NumFastIselRemaining = RemainingNow;
1137 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1138 // Don't abort, and use a different message for terminator misses.
1139 NumFastIselFailures += NumFastIselRemaining;
1140 if (EnableFastISelVerbose || EnableFastISelAbort) {
1141 dbgs() << "FastISel missed terminator: ";
1145 NumFastIselFailures += NumFastIselRemaining;
1146 if (EnableFastISelVerbose || EnableFastISelAbort) {
1147 dbgs() << "FastISel miss: ";
1150 if (EnableFastISelAbort)
1151 // The "fast" selector couldn't handle something and bailed.
1152 // For the purpose of debugging, just abort.
1153 llvm_unreachable("FastISel didn't select the entire block");
1158 FastIS->recomputeInsertPt();
1164 ++NumFastIselBlocks;
1167 // Run SelectionDAG instruction selection on the remainder of the block
1168 // not handled by FastISel. If FastISel is not run, this is the entire
1171 SelectBasicBlock(Begin, BI, HadTailCall);
1175 FuncInfo->PHINodesToUpdate.clear();
1179 SDB->clearDanglingDebugInfo();
1183 SelectionDAGISel::FinishBasicBlock() {
1185 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1186 << FuncInfo->PHINodesToUpdate.size() << "\n";
1187 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1188 dbgs() << "Node " << i << " : ("
1189 << FuncInfo->PHINodesToUpdate[i].first
1190 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1192 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1193 // PHI nodes in successors.
1194 if (SDB->SwitchCases.empty() &&
1195 SDB->JTCases.empty() &&
1196 SDB->BitTestCases.empty()) {
1197 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1198 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1199 assert(PHI->isPHI() &&
1200 "This is not a machine PHI node that we are updating!");
1201 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1203 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1208 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1209 // Lower header first, if it wasn't already lowered
1210 if (!SDB->BitTestCases[i].Emitted) {
1211 // Set the current basic block to the mbb we wish to insert the code into
1212 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1213 FuncInfo->InsertPt = FuncInfo->MBB->end();
1215 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1216 CurDAG->setRoot(SDB->getRoot());
1218 CodeGenAndEmitDAG();
1221 uint32_t UnhandledWeight = 0;
1222 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1223 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1225 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1226 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1227 // Set the current basic block to the mbb we wish to insert the code into
1228 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1229 FuncInfo->InsertPt = FuncInfo->MBB->end();
1232 SDB->visitBitTestCase(SDB->BitTestCases[i],
1233 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1235 SDB->BitTestCases[i].Reg,
1236 SDB->BitTestCases[i].Cases[j],
1239 SDB->visitBitTestCase(SDB->BitTestCases[i],
1240 SDB->BitTestCases[i].Default,
1242 SDB->BitTestCases[i].Reg,
1243 SDB->BitTestCases[i].Cases[j],
1247 CurDAG->setRoot(SDB->getRoot());
1249 CodeGenAndEmitDAG();
1253 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1255 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1256 MachineBasicBlock *PHIBB = PHI->getParent();
1257 assert(PHI->isPHI() &&
1258 "This is not a machine PHI node that we are updating!");
1259 // This is "default" BB. We have two jumps to it. From "header" BB and
1260 // from last "case" BB.
1261 if (PHIBB == SDB->BitTestCases[i].Default)
1262 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1263 .addMBB(SDB->BitTestCases[i].Parent)
1264 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1265 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1266 // One of "cases" BB.
1267 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1269 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1270 if (cBB->isSuccessor(PHIBB))
1271 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1275 SDB->BitTestCases.clear();
1277 // If the JumpTable record is filled in, then we need to emit a jump table.
1278 // Updating the PHI nodes is tricky in this case, since we need to determine
1279 // whether the PHI is a successor of the range check MBB or the jump table MBB
1280 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1281 // Lower header first, if it wasn't already lowered
1282 if (!SDB->JTCases[i].first.Emitted) {
1283 // Set the current basic block to the mbb we wish to insert the code into
1284 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1285 FuncInfo->InsertPt = FuncInfo->MBB->end();
1287 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1289 CurDAG->setRoot(SDB->getRoot());
1291 CodeGenAndEmitDAG();
1294 // Set the current basic block to the mbb we wish to insert the code into
1295 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1296 FuncInfo->InsertPt = FuncInfo->MBB->end();
1298 SDB->visitJumpTable(SDB->JTCases[i].second);
1299 CurDAG->setRoot(SDB->getRoot());
1301 CodeGenAndEmitDAG();
1304 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1306 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1307 MachineBasicBlock *PHIBB = PHI->getParent();
1308 assert(PHI->isPHI() &&
1309 "This is not a machine PHI node that we are updating!");
1310 // "default" BB. We can go there only from header BB.
1311 if (PHIBB == SDB->JTCases[i].second.Default)
1312 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1313 .addMBB(SDB->JTCases[i].first.HeaderBB);
1314 // JT BB. Just iterate over successors here
1315 if (FuncInfo->MBB->isSuccessor(PHIBB))
1316 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1319 SDB->JTCases.clear();
1321 // If the switch block involved a branch to one of the actual successors, we
1322 // need to update PHI nodes in that block.
1323 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1324 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1325 assert(PHI->isPHI() &&
1326 "This is not a machine PHI node that we are updating!");
1327 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1328 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1331 // If we generated any switch lowering information, build and codegen any
1332 // additional DAGs necessary.
1333 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1334 // Set the current basic block to the mbb we wish to insert the code into
1335 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1336 FuncInfo->InsertPt = FuncInfo->MBB->end();
1338 // Determine the unique successors.
1339 SmallVector<MachineBasicBlock *, 2> Succs;
1340 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1341 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1342 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1344 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1345 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1346 CurDAG->setRoot(SDB->getRoot());
1348 CodeGenAndEmitDAG();
1350 // Remember the last block, now that any splitting is done, for use in
1351 // populating PHI nodes in successors.
1352 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1354 // Handle any PHI nodes in successors of this chunk, as if we were coming
1355 // from the original BB before switch expansion. Note that PHI nodes can
1356 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1357 // handle them the right number of times.
1358 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1359 FuncInfo->MBB = Succs[i];
1360 FuncInfo->InsertPt = FuncInfo->MBB->end();
1361 // FuncInfo->MBB may have been removed from the CFG if a branch was
1363 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1364 for (MachineBasicBlock::iterator
1365 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1366 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1367 MachineInstrBuilder PHI(*MF, MBBI);
1368 // This value for this PHI node is recorded in PHINodesToUpdate.
1369 for (unsigned pn = 0; ; ++pn) {
1370 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1371 "Didn't find PHI entry!");
1372 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1373 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1381 SDB->SwitchCases.clear();
1385 /// Create the scheduler. If a specific scheduler was specified
1386 /// via the SchedulerRegistry, use it, otherwise select the
1387 /// one preferred by the target.
1389 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1390 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1394 RegisterScheduler::setDefault(Ctor);
1397 return Ctor(this, OptLevel);
1400 //===----------------------------------------------------------------------===//
1401 // Helper functions used by the generated instruction selector.
1402 //===----------------------------------------------------------------------===//
1403 // Calls to these methods are generated by tblgen.
1405 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1406 /// the dag combiner simplified the 255, we still want to match. RHS is the
1407 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1408 /// specified in the .td file (e.g. 255).
1409 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1410 int64_t DesiredMaskS) const {
1411 const APInt &ActualMask = RHS->getAPIntValue();
1412 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1414 // If the actual mask exactly matches, success!
1415 if (ActualMask == DesiredMask)
1418 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1419 if (ActualMask.intersects(~DesiredMask))
1422 // Otherwise, the DAG Combiner may have proven that the value coming in is
1423 // either already zero or is not demanded. Check for known zero input bits.
1424 APInt NeededMask = DesiredMask & ~ActualMask;
1425 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1428 // TODO: check to see if missing bits are just not demanded.
1430 // Otherwise, this pattern doesn't match.
1434 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1435 /// the dag combiner simplified the 255, we still want to match. RHS is the
1436 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1437 /// specified in the .td file (e.g. 255).
1438 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1439 int64_t DesiredMaskS) const {
1440 const APInt &ActualMask = RHS->getAPIntValue();
1441 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1443 // If the actual mask exactly matches, success!
1444 if (ActualMask == DesiredMask)
1447 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1448 if (ActualMask.intersects(~DesiredMask))
1451 // Otherwise, the DAG Combiner may have proven that the value coming in is
1452 // either already zero or is not demanded. Check for known zero input bits.
1453 APInt NeededMask = DesiredMask & ~ActualMask;
1455 APInt KnownZero, KnownOne;
1456 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne);
1458 // If all the missing bits in the or are already known to be set, match!
1459 if ((NeededMask & KnownOne) == NeededMask)
1462 // TODO: check to see if missing bits are just not demanded.
1464 // Otherwise, this pattern doesn't match.
1469 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1470 /// by tblgen. Others should not call it.
1471 void SelectionDAGISel::
1472 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1473 std::vector<SDValue> InOps;
1474 std::swap(InOps, Ops);
1476 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1477 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1478 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1479 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1481 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1482 if (InOps[e-1].getValueType() == MVT::Glue)
1483 --e; // Don't process a glue operand if it is here.
1486 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1487 if (!InlineAsm::isMemKind(Flags)) {
1488 // Just skip over this operand, copying the operands verbatim.
1489 Ops.insert(Ops.end(), InOps.begin()+i,
1490 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1491 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1493 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1494 "Memory operand with multiple values?");
1495 // Otherwise, this is a memory operand. Ask the target to select it.
1496 std::vector<SDValue> SelOps;
1497 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1498 report_fatal_error("Could not match memory address. Inline asm"
1501 // Add this to the output node.
1503 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1504 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1505 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1510 // Add the glue input back if present.
1511 if (e != InOps.size())
1512 Ops.push_back(InOps.back());
1515 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1518 static SDNode *findGlueUse(SDNode *N) {
1519 unsigned FlagResNo = N->getNumValues()-1;
1520 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1521 SDUse &Use = I.getUse();
1522 if (Use.getResNo() == FlagResNo)
1523 return Use.getUser();
1528 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1529 /// This function recursively traverses up the operand chain, ignoring
1531 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1532 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited,
1533 bool IgnoreChains) {
1534 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1535 // greater than all of its (recursive) operands. If we scan to a point where
1536 // 'use' is smaller than the node we're scanning for, then we know we will
1539 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1540 // happen because we scan down to newly selected nodes in the case of glue
1542 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1545 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1546 // won't fail if we scan it again.
1547 if (!Visited.insert(Use))
1550 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1551 // Ignore chain uses, they are validated by HandleMergeInputChains.
1552 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1555 SDNode *N = Use->getOperand(i).getNode();
1557 if (Use == ImmedUse || Use == Root)
1558 continue; // We are not looking for immediate use.
1563 // Traverse up the operand chain.
1564 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1570 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1571 /// operand node N of U during instruction selection that starts at Root.
1572 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1573 SDNode *Root) const {
1574 if (OptLevel == CodeGenOpt::None) return false;
1575 return N.hasOneUse();
1578 /// IsLegalToFold - Returns true if the specific operand node N of
1579 /// U can be folded during instruction selection that starts at Root.
1580 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1581 CodeGenOpt::Level OptLevel,
1582 bool IgnoreChains) {
1583 if (OptLevel == CodeGenOpt::None) return false;
1585 // If Root use can somehow reach N through a path that that doesn't contain
1586 // U then folding N would create a cycle. e.g. In the following
1587 // diagram, Root can reach N through X. If N is folded into into Root, then
1588 // X is both a predecessor and a successor of U.
1599 // * indicates nodes to be folded together.
1601 // If Root produces glue, then it gets (even more) interesting. Since it
1602 // will be "glued" together with its glue use in the scheduler, we need to
1603 // check if it might reach N.
1622 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1623 // (call it Fold), then X is a predecessor of GU and a successor of
1624 // Fold. But since Fold and GU are glued together, this will create
1625 // a cycle in the scheduling graph.
1627 // If the node has glue, walk down the graph to the "lowest" node in the
1629 EVT VT = Root->getValueType(Root->getNumValues()-1);
1630 while (VT == MVT::Glue) {
1631 SDNode *GU = findGlueUse(Root);
1635 VT = Root->getValueType(Root->getNumValues()-1);
1637 // If our query node has a glue result with a use, we've walked up it. If
1638 // the user (which has already been selected) has a chain or indirectly uses
1639 // the chain, our WalkChainUsers predicate will not consider it. Because of
1640 // this, we cannot ignore chains in this predicate.
1641 IgnoreChains = false;
1645 SmallPtrSet<SDNode*, 16> Visited;
1646 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1649 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1650 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1651 SelectInlineAsmMemoryOperands(Ops);
1653 std::vector<EVT> VTs;
1654 VTs.push_back(MVT::Other);
1655 VTs.push_back(MVT::Glue);
1656 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(),
1657 VTs, &Ops[0], Ops.size());
1659 return New.getNode();
1662 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1663 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1666 /// GetVBR - decode a vbr encoding whose top bit is set.
1667 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1668 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1669 assert(Val >= 128 && "Not a VBR");
1670 Val &= 127; // Remove first vbr bit.
1675 NextBits = MatcherTable[Idx++];
1676 Val |= (NextBits&127) << Shift;
1678 } while (NextBits & 128);
1684 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1685 /// interior glue and chain results to use the new glue and chain results.
1686 void SelectionDAGISel::
1687 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1688 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1690 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1691 bool isMorphNodeTo) {
1692 SmallVector<SDNode*, 4> NowDeadNodes;
1694 // Now that all the normal results are replaced, we replace the chain and
1695 // glue results if present.
1696 if (!ChainNodesMatched.empty()) {
1697 assert(InputChain.getNode() != 0 &&
1698 "Matched input chains but didn't produce a chain");
1699 // Loop over all of the nodes we matched that produced a chain result.
1700 // Replace all the chain results with the final chain we ended up with.
1701 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1702 SDNode *ChainNode = ChainNodesMatched[i];
1704 // If this node was already deleted, don't look at it.
1705 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
1708 // Don't replace the results of the root node if we're doing a
1710 if (ChainNode == NodeToMatch && isMorphNodeTo)
1713 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
1714 if (ChainVal.getValueType() == MVT::Glue)
1715 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
1716 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
1717 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
1719 // If the node became dead and we haven't already seen it, delete it.
1720 if (ChainNode->use_empty() &&
1721 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
1722 NowDeadNodes.push_back(ChainNode);
1726 // If the result produces glue, update any glue results in the matched
1727 // pattern with the glue result.
1728 if (InputGlue.getNode() != 0) {
1729 // Handle any interior nodes explicitly marked.
1730 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
1731 SDNode *FRN = GlueResultNodesMatched[i];
1733 // If this node was already deleted, don't look at it.
1734 if (FRN->getOpcode() == ISD::DELETED_NODE)
1737 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
1738 "Doesn't have a glue result");
1739 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
1742 // If the node became dead and we haven't already seen it, delete it.
1743 if (FRN->use_empty() &&
1744 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
1745 NowDeadNodes.push_back(FRN);
1749 if (!NowDeadNodes.empty())
1750 CurDAG->RemoveDeadNodes(NowDeadNodes);
1752 DEBUG(errs() << "ISEL: Match complete!\n");
1758 CR_LeadsToInteriorNode
1761 /// WalkChainUsers - Walk down the users of the specified chained node that is
1762 /// part of the pattern we're matching, looking at all of the users we find.
1763 /// This determines whether something is an interior node, whether we have a
1764 /// non-pattern node in between two pattern nodes (which prevent folding because
1765 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
1766 /// between pattern nodes (in which case the TF becomes part of the pattern).
1768 /// The walk we do here is guaranteed to be small because we quickly get down to
1769 /// already selected nodes "below" us.
1771 WalkChainUsers(const SDNode *ChainedNode,
1772 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
1773 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
1774 ChainResult Result = CR_Simple;
1776 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
1777 E = ChainedNode->use_end(); UI != E; ++UI) {
1778 // Make sure the use is of the chain, not some other value we produce.
1779 if (UI.getUse().getValueType() != MVT::Other) continue;
1783 // If we see an already-selected machine node, then we've gone beyond the
1784 // pattern that we're selecting down into the already selected chunk of the
1786 if (User->isMachineOpcode() ||
1787 User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
1790 unsigned UserOpcode = User->getOpcode();
1791 if (UserOpcode == ISD::CopyToReg ||
1792 UserOpcode == ISD::CopyFromReg ||
1793 UserOpcode == ISD::INLINEASM ||
1794 UserOpcode == ISD::EH_LABEL ||
1795 UserOpcode == ISD::LIFETIME_START ||
1796 UserOpcode == ISD::LIFETIME_END) {
1797 // If their node ID got reset to -1 then they've already been selected.
1798 // Treat them like a MachineOpcode.
1799 if (User->getNodeId() == -1)
1803 // If we have a TokenFactor, we handle it specially.
1804 if (User->getOpcode() != ISD::TokenFactor) {
1805 // If the node isn't a token factor and isn't part of our pattern, then it
1806 // must be a random chained node in between two nodes we're selecting.
1807 // This happens when we have something like:
1812 // Because we structurally match the load/store as a read/modify/write,
1813 // but the call is chained between them. We cannot fold in this case
1814 // because it would induce a cycle in the graph.
1815 if (!std::count(ChainedNodesInPattern.begin(),
1816 ChainedNodesInPattern.end(), User))
1817 return CR_InducesCycle;
1819 // Otherwise we found a node that is part of our pattern. For example in:
1823 // This would happen when we're scanning down from the load and see the
1824 // store as a user. Record that there is a use of ChainedNode that is
1825 // part of the pattern and keep scanning uses.
1826 Result = CR_LeadsToInteriorNode;
1827 InteriorChainedNodes.push_back(User);
1831 // If we found a TokenFactor, there are two cases to consider: first if the
1832 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
1833 // uses of the TF are in our pattern) we just want to ignore it. Second,
1834 // the TokenFactor can be sandwiched in between two chained nodes, like so:
1840 // | \ DAG's like cheese
1843 // [TokenFactor] [Op]
1850 // In this case, the TokenFactor becomes part of our match and we rewrite it
1851 // as a new TokenFactor.
1853 // To distinguish these two cases, do a recursive walk down the uses.
1854 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
1856 // If the uses of the TokenFactor are just already-selected nodes, ignore
1857 // it, it is "below" our pattern.
1859 case CR_InducesCycle:
1860 // If the uses of the TokenFactor lead to nodes that are not part of our
1861 // pattern that are not selected, folding would turn this into a cycle,
1863 return CR_InducesCycle;
1864 case CR_LeadsToInteriorNode:
1865 break; // Otherwise, keep processing.
1868 // Okay, we know we're in the interesting interior case. The TokenFactor
1869 // is now going to be considered part of the pattern so that we rewrite its
1870 // uses (it may have uses that are not part of the pattern) with the
1871 // ultimate chain result of the generated code. We will also add its chain
1872 // inputs as inputs to the ultimate TokenFactor we create.
1873 Result = CR_LeadsToInteriorNode;
1874 ChainedNodesInPattern.push_back(User);
1875 InteriorChainedNodes.push_back(User);
1882 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
1883 /// operation for when the pattern matched at least one node with a chains. The
1884 /// input vector contains a list of all of the chained nodes that we match. We
1885 /// must determine if this is a valid thing to cover (i.e. matching it won't
1886 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
1887 /// be used as the input node chain for the generated nodes.
1889 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
1890 SelectionDAG *CurDAG) {
1891 // Walk all of the chained nodes we've matched, recursively scanning down the
1892 // users of the chain result. This adds any TokenFactor nodes that are caught
1893 // in between chained nodes to the chained and interior nodes list.
1894 SmallVector<SDNode*, 3> InteriorChainedNodes;
1895 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1896 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
1897 InteriorChainedNodes) == CR_InducesCycle)
1898 return SDValue(); // Would induce a cycle.
1901 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
1902 // that we are interested in. Form our input TokenFactor node.
1903 SmallVector<SDValue, 3> InputChains;
1904 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
1905 // Add the input chain of this node to the InputChains list (which will be
1906 // the operands of the generated TokenFactor) if it's not an interior node.
1907 SDNode *N = ChainNodesMatched[i];
1908 if (N->getOpcode() != ISD::TokenFactor) {
1909 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
1912 // Otherwise, add the input chain.
1913 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
1914 assert(InChain.getValueType() == MVT::Other && "Not a chain");
1915 InputChains.push_back(InChain);
1919 // If we have a token factor, we want to add all inputs of the token factor
1920 // that are not part of the pattern we're matching.
1921 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1922 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
1923 N->getOperand(op).getNode()))
1924 InputChains.push_back(N->getOperand(op));
1929 if (InputChains.size() == 1)
1930 return InputChains[0];
1931 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(),
1932 MVT::Other, &InputChains[0], InputChains.size());
1935 /// MorphNode - Handle morphing a node in place for the selector.
1936 SDNode *SelectionDAGISel::
1937 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
1938 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) {
1939 // It is possible we're using MorphNodeTo to replace a node with no
1940 // normal results with one that has a normal result (or we could be
1941 // adding a chain) and the input could have glue and chains as well.
1942 // In this case we need to shift the operands down.
1943 // FIXME: This is a horrible hack and broken in obscure cases, no worse
1944 // than the old isel though.
1945 int OldGlueResultNo = -1, OldChainResultNo = -1;
1947 unsigned NTMNumResults = Node->getNumValues();
1948 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
1949 OldGlueResultNo = NTMNumResults-1;
1950 if (NTMNumResults != 1 &&
1951 Node->getValueType(NTMNumResults-2) == MVT::Other)
1952 OldChainResultNo = NTMNumResults-2;
1953 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
1954 OldChainResultNo = NTMNumResults-1;
1956 // Call the underlying SelectionDAG routine to do the transmogrification. Note
1957 // that this deletes operands of the old node that become dead.
1958 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps);
1960 // MorphNodeTo can operate in two ways: if an existing node with the
1961 // specified operands exists, it can just return it. Otherwise, it
1962 // updates the node in place to have the requested operands.
1964 // If we updated the node in place, reset the node ID. To the isel,
1965 // this should be just like a newly allocated machine node.
1969 unsigned ResNumResults = Res->getNumValues();
1970 // Move the glue if needed.
1971 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
1972 (unsigned)OldGlueResultNo != ResNumResults-1)
1973 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
1974 SDValue(Res, ResNumResults-1));
1976 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
1979 // Move the chain reference if needed.
1980 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
1981 (unsigned)OldChainResultNo != ResNumResults-1)
1982 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
1983 SDValue(Res, ResNumResults-1));
1985 // Otherwise, no replacement happened because the node already exists. Replace
1986 // Uses of the old node with the new one.
1988 CurDAG->ReplaceAllUsesWith(Node, Res);
1993 /// CheckSame - Implements OP_CheckSame.
1994 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
1995 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
1997 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
1998 // Accept if it is exactly the same as a previously recorded node.
1999 unsigned RecNo = MatcherTable[MatcherIndex++];
2000 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2001 return N == RecordedNodes[RecNo].first;
2004 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2005 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2006 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2007 const SelectionDAGISel &SDISel) {
2008 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2011 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2012 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2013 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2014 const SelectionDAGISel &SDISel, SDNode *N) {
2015 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2018 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2019 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2021 uint16_t Opc = MatcherTable[MatcherIndex++];
2022 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2023 return N->getOpcode() == Opc;
2026 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2027 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2028 SDValue N, const TargetLowering &TLI) {
2029 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2030 if (N.getValueType() == VT) return true;
2032 // Handle the case when VT is iPTR.
2033 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy();
2036 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2037 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2038 SDValue N, const TargetLowering &TLI,
2040 if (ChildNo >= N.getNumOperands())
2041 return false; // Match fails if out of range child #.
2042 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2046 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2047 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2049 return cast<CondCodeSDNode>(N)->get() ==
2050 (ISD::CondCode)MatcherTable[MatcherIndex++];
2053 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2054 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2055 SDValue N, const TargetLowering &TLI) {
2056 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2057 if (cast<VTSDNode>(N)->getVT() == VT)
2060 // Handle the case when VT is iPTR.
2061 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy();
2064 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2065 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2067 int64_t Val = MatcherTable[MatcherIndex++];
2069 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2071 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2072 return C != 0 && C->getSExtValue() == Val;
2075 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2076 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2077 SDValue N, const SelectionDAGISel &SDISel) {
2078 int64_t Val = MatcherTable[MatcherIndex++];
2080 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2082 if (N->getOpcode() != ISD::AND) return false;
2084 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2085 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2088 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2089 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2090 SDValue N, const SelectionDAGISel &SDISel) {
2091 int64_t Val = MatcherTable[MatcherIndex++];
2093 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2095 if (N->getOpcode() != ISD::OR) return false;
2097 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2098 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2101 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2102 /// scope, evaluate the current node. If the current predicate is known to
2103 /// fail, set Result=true and return anything. If the current predicate is
2104 /// known to pass, set Result=false and return the MatcherIndex to continue
2105 /// with. If the current predicate is unknown, set Result=false and return the
2106 /// MatcherIndex to continue with.
2107 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2108 unsigned Index, SDValue N,
2110 const SelectionDAGISel &SDISel,
2111 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2112 switch (Table[Index++]) {
2115 return Index-1; // Could not evaluate this predicate.
2116 case SelectionDAGISel::OPC_CheckSame:
2117 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2119 case SelectionDAGISel::OPC_CheckPatternPredicate:
2120 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2122 case SelectionDAGISel::OPC_CheckPredicate:
2123 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2125 case SelectionDAGISel::OPC_CheckOpcode:
2126 Result = !::CheckOpcode(Table, Index, N.getNode());
2128 case SelectionDAGISel::OPC_CheckType:
2129 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2131 case SelectionDAGISel::OPC_CheckChild0Type:
2132 case SelectionDAGISel::OPC_CheckChild1Type:
2133 case SelectionDAGISel::OPC_CheckChild2Type:
2134 case SelectionDAGISel::OPC_CheckChild3Type:
2135 case SelectionDAGISel::OPC_CheckChild4Type:
2136 case SelectionDAGISel::OPC_CheckChild5Type:
2137 case SelectionDAGISel::OPC_CheckChild6Type:
2138 case SelectionDAGISel::OPC_CheckChild7Type:
2139 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2140 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type);
2142 case SelectionDAGISel::OPC_CheckCondCode:
2143 Result = !::CheckCondCode(Table, Index, N);
2145 case SelectionDAGISel::OPC_CheckValueType:
2146 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2148 case SelectionDAGISel::OPC_CheckInteger:
2149 Result = !::CheckInteger(Table, Index, N);
2151 case SelectionDAGISel::OPC_CheckAndImm:
2152 Result = !::CheckAndImm(Table, Index, N, SDISel);
2154 case SelectionDAGISel::OPC_CheckOrImm:
2155 Result = !::CheckOrImm(Table, Index, N, SDISel);
2163 /// FailIndex - If this match fails, this is the index to continue with.
2166 /// NodeStack - The node stack when the scope was formed.
2167 SmallVector<SDValue, 4> NodeStack;
2169 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2170 unsigned NumRecordedNodes;
2172 /// NumMatchedMemRefs - The number of matched memref entries.
2173 unsigned NumMatchedMemRefs;
2175 /// InputChain/InputGlue - The current chain/glue
2176 SDValue InputChain, InputGlue;
2178 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2179 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2184 SDNode *SelectionDAGISel::
2185 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2186 unsigned TableSize) {
2187 // FIXME: Should these even be selected? Handle these cases in the caller?
2188 switch (NodeToMatch->getOpcode()) {
2191 case ISD::EntryToken: // These nodes remain the same.
2192 case ISD::BasicBlock:
2194 case ISD::RegisterMask:
2195 //case ISD::VALUETYPE:
2196 //case ISD::CONDCODE:
2197 case ISD::HANDLENODE:
2198 case ISD::MDNODE_SDNODE:
2199 case ISD::TargetConstant:
2200 case ISD::TargetConstantFP:
2201 case ISD::TargetConstantPool:
2202 case ISD::TargetFrameIndex:
2203 case ISD::TargetExternalSymbol:
2204 case ISD::TargetBlockAddress:
2205 case ISD::TargetJumpTable:
2206 case ISD::TargetGlobalTLSAddress:
2207 case ISD::TargetGlobalAddress:
2208 case ISD::TokenFactor:
2209 case ISD::CopyFromReg:
2210 case ISD::CopyToReg:
2212 case ISD::LIFETIME_START:
2213 case ISD::LIFETIME_END:
2214 NodeToMatch->setNodeId(-1); // Mark selected.
2216 case ISD::AssertSext:
2217 case ISD::AssertZext:
2218 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2219 NodeToMatch->getOperand(0));
2221 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2222 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2225 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2227 // Set up the node stack with NodeToMatch as the only node on the stack.
2228 SmallVector<SDValue, 8> NodeStack;
2229 SDValue N = SDValue(NodeToMatch, 0);
2230 NodeStack.push_back(N);
2232 // MatchScopes - Scopes used when matching, if a match failure happens, this
2233 // indicates where to continue checking.
2234 SmallVector<MatchScope, 8> MatchScopes;
2236 // RecordedNodes - This is the set of nodes that have been recorded by the
2237 // state machine. The second value is the parent of the node, or null if the
2238 // root is recorded.
2239 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2241 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2243 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2245 // These are the current input chain and glue for use when generating nodes.
2246 // Various Emit operations change these. For example, emitting a copytoreg
2247 // uses and updates these.
2248 SDValue InputChain, InputGlue;
2250 // ChainNodesMatched - If a pattern matches nodes that have input/output
2251 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2252 // which ones they are. The result is captured into this list so that we can
2253 // update the chain results when the pattern is complete.
2254 SmallVector<SDNode*, 3> ChainNodesMatched;
2255 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2257 DEBUG(errs() << "ISEL: Starting pattern match on root node: ";
2258 NodeToMatch->dump(CurDAG);
2261 // Determine where to start the interpreter. Normally we start at opcode #0,
2262 // but if the state machine starts with an OPC_SwitchOpcode, then we
2263 // accelerate the first lookup (which is guaranteed to be hot) with the
2264 // OpcodeOffset table.
2265 unsigned MatcherIndex = 0;
2267 if (!OpcodeOffset.empty()) {
2268 // Already computed the OpcodeOffset table, just index into it.
2269 if (N.getOpcode() < OpcodeOffset.size())
2270 MatcherIndex = OpcodeOffset[N.getOpcode()];
2271 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n");
2273 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2274 // Otherwise, the table isn't computed, but the state machine does start
2275 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2276 // is the first time we're selecting an instruction.
2279 // Get the size of this case.
2280 unsigned CaseSize = MatcherTable[Idx++];
2282 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2283 if (CaseSize == 0) break;
2285 // Get the opcode, add the index to the table.
2286 uint16_t Opc = MatcherTable[Idx++];
2287 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2288 if (Opc >= OpcodeOffset.size())
2289 OpcodeOffset.resize((Opc+1)*2);
2290 OpcodeOffset[Opc] = Idx;
2294 // Okay, do the lookup for the first opcode.
2295 if (N.getOpcode() < OpcodeOffset.size())
2296 MatcherIndex = OpcodeOffset[N.getOpcode()];
2300 assert(MatcherIndex < TableSize && "Invalid index");
2302 unsigned CurrentOpcodeIndex = MatcherIndex;
2304 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2307 // Okay, the semantics of this operation are that we should push a scope
2308 // then evaluate the first child. However, pushing a scope only to have
2309 // the first check fail (which then pops it) is inefficient. If we can
2310 // determine immediately that the first check (or first several) will
2311 // immediately fail, don't even bother pushing a scope for them.
2315 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2316 if (NumToSkip & 128)
2317 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2318 // Found the end of the scope with no match.
2319 if (NumToSkip == 0) {
2324 FailIndex = MatcherIndex+NumToSkip;
2326 unsigned MatcherIndexOfPredicate = MatcherIndex;
2327 (void)MatcherIndexOfPredicate; // silence warning.
2329 // If we can't evaluate this predicate without pushing a scope (e.g. if
2330 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2331 // push the scope and evaluate the full predicate chain.
2333 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2334 Result, *this, RecordedNodes);
2338 DEBUG(errs() << " Skipped scope entry (due to false predicate) at "
2339 << "index " << MatcherIndexOfPredicate
2340 << ", continuing at " << FailIndex << "\n");
2341 ++NumDAGIselRetries;
2343 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2344 // move to the next case.
2345 MatcherIndex = FailIndex;
2348 // If the whole scope failed to match, bail.
2349 if (FailIndex == 0) break;
2351 // Push a MatchScope which indicates where to go if the first child fails
2353 MatchScope NewEntry;
2354 NewEntry.FailIndex = FailIndex;
2355 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2356 NewEntry.NumRecordedNodes = RecordedNodes.size();
2357 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2358 NewEntry.InputChain = InputChain;
2359 NewEntry.InputGlue = InputGlue;
2360 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2361 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2362 MatchScopes.push_back(NewEntry);
2365 case OPC_RecordNode: {
2366 // Remember this node, it may end up being an operand in the pattern.
2368 if (NodeStack.size() > 1)
2369 Parent = NodeStack[NodeStack.size()-2].getNode();
2370 RecordedNodes.push_back(std::make_pair(N, Parent));
2374 case OPC_RecordChild0: case OPC_RecordChild1:
2375 case OPC_RecordChild2: case OPC_RecordChild3:
2376 case OPC_RecordChild4: case OPC_RecordChild5:
2377 case OPC_RecordChild6: case OPC_RecordChild7: {
2378 unsigned ChildNo = Opcode-OPC_RecordChild0;
2379 if (ChildNo >= N.getNumOperands())
2380 break; // Match fails if out of range child #.
2382 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2386 case OPC_RecordMemRef:
2387 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2390 case OPC_CaptureGlueInput:
2391 // If the current node has an input glue, capture it in InputGlue.
2392 if (N->getNumOperands() != 0 &&
2393 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2394 InputGlue = N->getOperand(N->getNumOperands()-1);
2397 case OPC_MoveChild: {
2398 unsigned ChildNo = MatcherTable[MatcherIndex++];
2399 if (ChildNo >= N.getNumOperands())
2400 break; // Match fails if out of range child #.
2401 N = N.getOperand(ChildNo);
2402 NodeStack.push_back(N);
2406 case OPC_MoveParent:
2407 // Pop the current node off the NodeStack.
2408 NodeStack.pop_back();
2409 assert(!NodeStack.empty() && "Node stack imbalance!");
2410 N = NodeStack.back();
2414 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2416 case OPC_CheckPatternPredicate:
2417 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2419 case OPC_CheckPredicate:
2420 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2424 case OPC_CheckComplexPat: {
2425 unsigned CPNum = MatcherTable[MatcherIndex++];
2426 unsigned RecNo = MatcherTable[MatcherIndex++];
2427 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2428 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2429 RecordedNodes[RecNo].first, CPNum,
2434 case OPC_CheckOpcode:
2435 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2439 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break;
2442 case OPC_SwitchOpcode: {
2443 unsigned CurNodeOpcode = N.getOpcode();
2444 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2447 // Get the size of this case.
2448 CaseSize = MatcherTable[MatcherIndex++];
2450 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2451 if (CaseSize == 0) break;
2453 uint16_t Opc = MatcherTable[MatcherIndex++];
2454 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2456 // If the opcode matches, then we will execute this case.
2457 if (CurNodeOpcode == Opc)
2460 // Otherwise, skip over this case.
2461 MatcherIndex += CaseSize;
2464 // If no cases matched, bail out.
2465 if (CaseSize == 0) break;
2467 // Otherwise, execute the case we found.
2468 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart
2469 << " to " << MatcherIndex << "\n");
2473 case OPC_SwitchType: {
2474 MVT CurNodeVT = N.getValueType().getSimpleVT();
2475 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2478 // Get the size of this case.
2479 CaseSize = MatcherTable[MatcherIndex++];
2481 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2482 if (CaseSize == 0) break;
2484 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2485 if (CaseVT == MVT::iPTR)
2486 CaseVT = TLI.getPointerTy();
2488 // If the VT matches, then we will execute this case.
2489 if (CurNodeVT == CaseVT)
2492 // Otherwise, skip over this case.
2493 MatcherIndex += CaseSize;
2496 // If no cases matched, bail out.
2497 if (CaseSize == 0) break;
2499 // Otherwise, execute the case we found.
2500 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2501 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2504 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2505 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2506 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2507 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2508 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2509 Opcode-OPC_CheckChild0Type))
2512 case OPC_CheckCondCode:
2513 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2515 case OPC_CheckValueType:
2516 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break;
2518 case OPC_CheckInteger:
2519 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2521 case OPC_CheckAndImm:
2522 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2524 case OPC_CheckOrImm:
2525 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2528 case OPC_CheckFoldableChainNode: {
2529 assert(NodeStack.size() != 1 && "No parent node");
2530 // Verify that all intermediate nodes between the root and this one have
2532 bool HasMultipleUses = false;
2533 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2534 if (!NodeStack[i].hasOneUse()) {
2535 HasMultipleUses = true;
2538 if (HasMultipleUses) break;
2540 // Check to see that the target thinks this is profitable to fold and that
2541 // we can fold it without inducing cycles in the graph.
2542 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2544 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2545 NodeToMatch, OptLevel,
2546 true/*We validate our own chains*/))
2551 case OPC_EmitInteger: {
2552 MVT::SimpleValueType VT =
2553 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2554 int64_t Val = MatcherTable[MatcherIndex++];
2556 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2557 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2558 CurDAG->getTargetConstant(Val, VT), (SDNode*)0));
2561 case OPC_EmitRegister: {
2562 MVT::SimpleValueType VT =
2563 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2564 unsigned RegNo = MatcherTable[MatcherIndex++];
2565 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2566 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2569 case OPC_EmitRegister2: {
2570 // For targets w/ more than 256 register names, the register enum
2571 // values are stored in two bytes in the matcher table (just like
2573 MVT::SimpleValueType VT =
2574 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2575 unsigned RegNo = MatcherTable[MatcherIndex++];
2576 RegNo |= MatcherTable[MatcherIndex++] << 8;
2577 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2578 CurDAG->getRegister(RegNo, VT), (SDNode*)0));
2582 case OPC_EmitConvertToTarget: {
2583 // Convert from IMM/FPIMM to target version.
2584 unsigned RecNo = MatcherTable[MatcherIndex++];
2585 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2586 SDValue Imm = RecordedNodes[RecNo].first;
2588 if (Imm->getOpcode() == ISD::Constant) {
2589 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue();
2590 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType());
2591 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2592 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2593 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType());
2596 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2600 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2601 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
2602 // These are space-optimized forms of OPC_EmitMergeInputChains.
2603 assert(InputChain.getNode() == 0 &&
2604 "EmitMergeInputChains should be the first chain producing node");
2605 assert(ChainNodesMatched.empty() &&
2606 "Should only have one EmitMergeInputChains per match");
2608 // Read all of the chained nodes.
2609 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
2610 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2611 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2613 // FIXME: What if other value results of the node have uses not matched
2615 if (ChainNodesMatched.back() != NodeToMatch &&
2616 !RecordedNodes[RecNo].first.hasOneUse()) {
2617 ChainNodesMatched.clear();
2621 // Merge the input chains if they are not intra-pattern references.
2622 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2624 if (InputChain.getNode() == 0)
2625 break; // Failed to merge.
2629 case OPC_EmitMergeInputChains: {
2630 assert(InputChain.getNode() == 0 &&
2631 "EmitMergeInputChains should be the first chain producing node");
2632 // This node gets a list of nodes we matched in the input that have
2633 // chains. We want to token factor all of the input chains to these nodes
2634 // together. However, if any of the input chains is actually one of the
2635 // nodes matched in this pattern, then we have an intra-match reference.
2636 // Ignore these because the newly token factored chain should not refer to
2638 unsigned NumChains = MatcherTable[MatcherIndex++];
2639 assert(NumChains != 0 && "Can't TF zero chains");
2641 assert(ChainNodesMatched.empty() &&
2642 "Should only have one EmitMergeInputChains per match");
2644 // Read all of the chained nodes.
2645 for (unsigned i = 0; i != NumChains; ++i) {
2646 unsigned RecNo = MatcherTable[MatcherIndex++];
2647 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2648 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2650 // FIXME: What if other value results of the node have uses not matched
2652 if (ChainNodesMatched.back() != NodeToMatch &&
2653 !RecordedNodes[RecNo].first.hasOneUse()) {
2654 ChainNodesMatched.clear();
2659 // If the inner loop broke out, the match fails.
2660 if (ChainNodesMatched.empty())
2663 // Merge the input chains if they are not intra-pattern references.
2664 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
2666 if (InputChain.getNode() == 0)
2667 break; // Failed to merge.
2672 case OPC_EmitCopyToReg: {
2673 unsigned RecNo = MatcherTable[MatcherIndex++];
2674 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2675 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
2677 if (InputChain.getNode() == 0)
2678 InputChain = CurDAG->getEntryNode();
2680 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(),
2681 DestPhysReg, RecordedNodes[RecNo].first,
2684 InputGlue = InputChain.getValue(1);
2688 case OPC_EmitNodeXForm: {
2689 unsigned XFormNo = MatcherTable[MatcherIndex++];
2690 unsigned RecNo = MatcherTable[MatcherIndex++];
2691 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2692 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
2693 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0));
2698 case OPC_MorphNodeTo: {
2699 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
2700 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2701 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
2702 // Get the result VT list.
2703 unsigned NumVTs = MatcherTable[MatcherIndex++];
2704 SmallVector<EVT, 4> VTs;
2705 for (unsigned i = 0; i != NumVTs; ++i) {
2706 MVT::SimpleValueType VT =
2707 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2708 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy;
2712 if (EmitNodeInfo & OPFL_Chain)
2713 VTs.push_back(MVT::Other);
2714 if (EmitNodeInfo & OPFL_GlueOutput)
2715 VTs.push_back(MVT::Glue);
2717 // This is hot code, so optimize the two most common cases of 1 and 2
2720 if (VTs.size() == 1)
2721 VTList = CurDAG->getVTList(VTs[0]);
2722 else if (VTs.size() == 2)
2723 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
2725 VTList = CurDAG->getVTList(VTs.data(), VTs.size());
2727 // Get the operand list.
2728 unsigned NumOps = MatcherTable[MatcherIndex++];
2729 SmallVector<SDValue, 8> Ops;
2730 for (unsigned i = 0; i != NumOps; ++i) {
2731 unsigned RecNo = MatcherTable[MatcherIndex++];
2733 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2735 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
2736 Ops.push_back(RecordedNodes[RecNo].first);
2739 // If there are variadic operands to add, handle them now.
2740 if (EmitNodeInfo & OPFL_VariadicInfo) {
2741 // Determine the start index to copy from.
2742 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
2743 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
2744 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
2745 "Invalid variadic node");
2746 // Copy all of the variadic operands, not including a potential glue
2748 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
2750 SDValue V = NodeToMatch->getOperand(i);
2751 if (V.getValueType() == MVT::Glue) break;
2756 // If this has chain/glue inputs, add them.
2757 if (EmitNodeInfo & OPFL_Chain)
2758 Ops.push_back(InputChain);
2759 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0)
2760 Ops.push_back(InputGlue);
2764 if (Opcode != OPC_MorphNodeTo) {
2765 // If this is a normal EmitNode command, just create the new node and
2766 // add the results to the RecordedNodes list.
2767 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(),
2768 VTList, Ops.data(), Ops.size());
2770 // Add all the non-glue/non-chain results to the RecordedNodes list.
2771 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
2772 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
2773 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
2777 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
2778 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(),
2781 // NodeToMatch was eliminated by CSE when the target changed the DAG.
2782 // We will visit the equivalent node later.
2783 DEBUG(dbgs() << "Node was eliminated by CSE\n");
2787 // If the node had chain/glue results, update our notion of the current
2789 if (EmitNodeInfo & OPFL_GlueOutput) {
2790 InputGlue = SDValue(Res, VTs.size()-1);
2791 if (EmitNodeInfo & OPFL_Chain)
2792 InputChain = SDValue(Res, VTs.size()-2);
2793 } else if (EmitNodeInfo & OPFL_Chain)
2794 InputChain = SDValue(Res, VTs.size()-1);
2796 // If the OPFL_MemRefs glue is set on this node, slap all of the
2797 // accumulated memrefs onto it.
2799 // FIXME: This is vastly incorrect for patterns with multiple outputs
2800 // instructions that access memory and for ComplexPatterns that match
2802 if (EmitNodeInfo & OPFL_MemRefs) {
2803 // Only attach load or store memory operands if the generated
2804 // instruction may load or store.
2805 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc);
2806 bool mayLoad = MCID.mayLoad();
2807 bool mayStore = MCID.mayStore();
2809 unsigned NumMemRefs = 0;
2810 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2811 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2812 if ((*I)->isLoad()) {
2815 } else if ((*I)->isStore()) {
2823 MachineSDNode::mmo_iterator MemRefs =
2824 MF->allocateMemRefsArray(NumMemRefs);
2826 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
2827 for (SmallVector<MachineMemOperand*, 2>::const_iterator I =
2828 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
2829 if ((*I)->isLoad()) {
2832 } else if ((*I)->isStore()) {
2840 cast<MachineSDNode>(Res)
2841 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
2845 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
2846 << " node: "; Res->dump(CurDAG); errs() << "\n");
2848 // If this was a MorphNodeTo then we're completely done!
2849 if (Opcode == OPC_MorphNodeTo) {
2850 // Update chain and glue uses.
2851 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2852 InputGlue, GlueResultNodesMatched, true);
2859 case OPC_MarkGlueResults: {
2860 unsigned NumNodes = MatcherTable[MatcherIndex++];
2862 // Read and remember all the glue-result nodes.
2863 for (unsigned i = 0; i != NumNodes; ++i) {
2864 unsigned RecNo = MatcherTable[MatcherIndex++];
2866 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
2868 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2869 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
2874 case OPC_CompleteMatch: {
2875 // The match has been completed, and any new nodes (if any) have been
2876 // created. Patch up references to the matched dag to use the newly
2878 unsigned NumResults = MatcherTable[MatcherIndex++];
2880 for (unsigned i = 0; i != NumResults; ++i) {
2881 unsigned ResSlot = MatcherTable[MatcherIndex++];
2883 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
2885 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame");
2886 SDValue Res = RecordedNodes[ResSlot].first;
2888 assert(i < NodeToMatch->getNumValues() &&
2889 NodeToMatch->getValueType(i) != MVT::Other &&
2890 NodeToMatch->getValueType(i) != MVT::Glue &&
2891 "Invalid number of results to complete!");
2892 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
2893 NodeToMatch->getValueType(i) == MVT::iPTR ||
2894 Res.getValueType() == MVT::iPTR ||
2895 NodeToMatch->getValueType(i).getSizeInBits() ==
2896 Res.getValueType().getSizeInBits()) &&
2897 "invalid replacement");
2898 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
2901 // If the root node defines glue, add it to the glue nodes to update list.
2902 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
2903 GlueResultNodesMatched.push_back(NodeToMatch);
2905 // Update chain and glue uses.
2906 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
2907 InputGlue, GlueResultNodesMatched, false);
2909 assert(NodeToMatch->use_empty() &&
2910 "Didn't replace all uses of the node?");
2912 // FIXME: We just return here, which interacts correctly with SelectRoot
2913 // above. We should fix this to not return an SDNode* anymore.
2918 // If the code reached this point, then the match failed. See if there is
2919 // another child to try in the current 'Scope', otherwise pop it until we
2920 // find a case to check.
2921 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
2922 ++NumDAGIselRetries;
2924 if (MatchScopes.empty()) {
2925 CannotYetSelect(NodeToMatch);
2929 // Restore the interpreter state back to the point where the scope was
2931 MatchScope &LastScope = MatchScopes.back();
2932 RecordedNodes.resize(LastScope.NumRecordedNodes);
2934 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
2935 N = NodeStack.back();
2937 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
2938 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
2939 MatcherIndex = LastScope.FailIndex;
2941 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n");
2943 InputChain = LastScope.InputChain;
2944 InputGlue = LastScope.InputGlue;
2945 if (!LastScope.HasChainNodesMatched)
2946 ChainNodesMatched.clear();
2947 if (!LastScope.HasGlueResultNodesMatched)
2948 GlueResultNodesMatched.clear();
2950 // Check to see what the offset is at the new MatcherIndex. If it is zero
2951 // we have reached the end of this scope, otherwise we have another child
2952 // in the current scope to try.
2953 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2954 if (NumToSkip & 128)
2955 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2957 // If we have another child in this scope to match, update FailIndex and
2959 if (NumToSkip != 0) {
2960 LastScope.FailIndex = MatcherIndex+NumToSkip;
2964 // End of this scope, pop it and try the next child in the containing
2966 MatchScopes.pop_back();
2973 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
2975 raw_string_ostream Msg(msg);
2976 Msg << "Cannot select: ";
2978 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
2979 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
2980 N->getOpcode() != ISD::INTRINSIC_VOID) {
2981 N->printrFull(Msg, CurDAG);
2982 Msg << "\nIn function: " << MF->getName();
2984 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
2986 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
2987 if (iid < Intrinsic::num_intrinsics)
2988 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
2989 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
2990 Msg << "target intrinsic %" << TII->getName(iid);
2992 Msg << "unknown intrinsic #" << iid;
2994 report_fatal_error(Msg.str());
2997 char SelectionDAGISel::ID = 0;