1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the SelectionDAGISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAGISel.h"
15 #include "ScheduleDAGSDNodes.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/PostOrderIterator.h"
18 #include "llvm/ADT/Statistic.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
22 #include "llvm/Analysis/TargetLibraryInfo.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineModuleInfo.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
33 #include "llvm/CodeGen/SchedulerRegistry.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/IR/Constants.h"
36 #include "llvm/IR/DebugInfo.h"
37 #include "llvm/IR/Function.h"
38 #include "llvm/IR/GCStrategy.h"
39 #include "llvm/IR/InlineAsm.h"
40 #include "llvm/IR/Instructions.h"
41 #include "llvm/IR/IntrinsicInst.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/IR/LLVMContext.h"
44 #include "llvm/IR/Module.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/Support/Compiler.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/Timer.h"
50 #include "llvm/Support/raw_ostream.h"
51 #include "llvm/Target/TargetInstrInfo.h"
52 #include "llvm/Target/TargetIntrinsicInfo.h"
53 #include "llvm/Target/TargetLowering.h"
54 #include "llvm/Target/TargetMachine.h"
55 #include "llvm/Target/TargetOptions.h"
56 #include "llvm/Target/TargetRegisterInfo.h"
57 #include "llvm/Target/TargetSubtargetInfo.h"
58 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
62 #define DEBUG_TYPE "isel"
64 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
65 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
66 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
67 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
68 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
69 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
70 STATISTIC(NumFastIselFailLowerArguments,
71 "Number of entry blocks where fast isel failed to lower arguments");
75 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden,
76 cl::desc("Enable extra verbose messages in the \"fast\" "
77 "instruction selector"));
80 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret");
81 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br");
82 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch");
83 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr");
84 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke");
85 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume");
86 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable");
88 // Standard binary operators...
89 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add");
90 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd");
91 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub");
92 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub");
93 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul");
94 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul");
95 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv");
96 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv");
97 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv");
98 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem");
99 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
100 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem");
102 // Logical operators...
103 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And");
104 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or");
105 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor");
107 // Memory instructions...
108 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca");
109 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load");
110 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store");
111 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg");
112 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM");
113 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence");
114 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr");
116 // Convert instructions...
117 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc");
118 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt");
119 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt");
120 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc");
121 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt");
122 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI");
123 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI");
124 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP");
125 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP");
126 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr");
127 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt");
128 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast");
130 // Other instructions...
131 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp");
132 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp");
133 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI");
134 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select");
135 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call");
136 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl");
137 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr");
138 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr");
139 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg");
140 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement");
141 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement");
142 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector");
143 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue");
144 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue");
145 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad");
147 // Intrinsic instructions...
148 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call");
149 STATISTIC(NumFastIselFailSAddWithOverflow,
150 "Fast isel fails on sadd.with.overflow");
151 STATISTIC(NumFastIselFailUAddWithOverflow,
152 "Fast isel fails on uadd.with.overflow");
153 STATISTIC(NumFastIselFailSSubWithOverflow,
154 "Fast isel fails on ssub.with.overflow");
155 STATISTIC(NumFastIselFailUSubWithOverflow,
156 "Fast isel fails on usub.with.overflow");
157 STATISTIC(NumFastIselFailSMulWithOverflow,
158 "Fast isel fails on smul.with.overflow");
159 STATISTIC(NumFastIselFailUMulWithOverflow,
160 "Fast isel fails on umul.with.overflow");
161 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress");
162 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call");
163 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call");
164 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call");
168 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden,
169 cl::desc("Enable verbose messages in the \"fast\" "
170 "instruction selector"));
172 EnableFastISelAbort("fast-isel-abort", cl::Hidden,
173 cl::desc("Enable abort calls when \"fast\" instruction selection "
174 "fails to lower an instruction"));
176 EnableFastISelAbortArgs("fast-isel-abort-args", cl::Hidden,
177 cl::desc("Enable abort calls when \"fast\" instruction selection "
178 "fails to lower a formal argument"));
182 cl::desc("use Machine Branch Probability Info"),
183 cl::init(true), cl::Hidden);
186 static cl::opt<std::string>
187 FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
188 cl::desc("Only display the basic block whose name "
189 "matches this for all view-*-dags options"));
191 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
192 cl::desc("Pop up a window to show dags before the first "
193 "dag combine pass"));
195 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
196 cl::desc("Pop up a window to show dags before legalize types"));
198 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
199 cl::desc("Pop up a window to show dags before legalize"));
201 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
202 cl::desc("Pop up a window to show dags before the second "
203 "dag combine pass"));
205 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
206 cl::desc("Pop up a window to show dags before the post legalize types"
207 " dag combine pass"));
209 ViewISelDAGs("view-isel-dags", cl::Hidden,
210 cl::desc("Pop up a window to show isel dags as they are selected"));
212 ViewSchedDAGs("view-sched-dags", cl::Hidden,
213 cl::desc("Pop up a window to show sched dags as they are processed"));
215 ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
216 cl::desc("Pop up a window to show SUnit dags after they are processed"));
218 static const bool ViewDAGCombine1 = false,
219 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false,
220 ViewDAGCombine2 = false,
221 ViewDAGCombineLT = false,
222 ViewISelDAGs = false, ViewSchedDAGs = false,
223 ViewSUnitDAGs = false;
226 //===---------------------------------------------------------------------===//
228 /// RegisterScheduler class - Track the registration of instruction schedulers.
230 //===---------------------------------------------------------------------===//
231 MachinePassRegistry RegisterScheduler::Registry;
233 //===---------------------------------------------------------------------===//
235 /// ISHeuristic command line option for instruction schedulers.
237 //===---------------------------------------------------------------------===//
238 static cl::opt<RegisterScheduler::FunctionPassCtor, false,
239 RegisterPassParser<RegisterScheduler> >
240 ISHeuristic("pre-RA-sched",
241 cl::init(&createDefaultScheduler), cl::Hidden,
242 cl::desc("Instruction schedulers available (before register"
245 static RegisterScheduler
246 defaultListDAGScheduler("default", "Best scheduler for the target",
247 createDefaultScheduler);
250 //===--------------------------------------------------------------------===//
251 /// \brief This class is used by SelectionDAGISel to temporarily override
252 /// the optimization level on a per-function basis.
253 class OptLevelChanger {
254 SelectionDAGISel &IS;
255 CodeGenOpt::Level SavedOptLevel;
259 OptLevelChanger(SelectionDAGISel &ISel,
260 CodeGenOpt::Level NewOptLevel) : IS(ISel) {
261 SavedOptLevel = IS.OptLevel;
262 if (NewOptLevel == SavedOptLevel)
264 IS.OptLevel = NewOptLevel;
265 IS.TM.setOptLevel(NewOptLevel);
266 SavedFastISel = IS.TM.Options.EnableFastISel;
267 if (NewOptLevel == CodeGenOpt::None)
268 IS.TM.setFastISel(true);
269 DEBUG(dbgs() << "\nChanging optimization level for Function "
270 << IS.MF->getFunction()->getName() << "\n");
271 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
272 << " ; After: -O" << NewOptLevel << "\n");
276 if (IS.OptLevel == SavedOptLevel)
278 DEBUG(dbgs() << "\nRestoring optimization level for Function "
279 << IS.MF->getFunction()->getName() << "\n");
280 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
281 << " ; After: -O" << SavedOptLevel << "\n");
282 IS.OptLevel = SavedOptLevel;
283 IS.TM.setOptLevel(SavedOptLevel);
284 IS.TM.setFastISel(SavedFastISel);
288 //===--------------------------------------------------------------------===//
289 /// createDefaultScheduler - This creates an instruction scheduler appropriate
291 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
292 CodeGenOpt::Level OptLevel) {
293 const TargetLowering *TLI = IS->TLI;
294 const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
296 if (OptLevel == CodeGenOpt::None || ST.useMachineScheduler() ||
297 TLI->getSchedulingPreference() == Sched::Source)
298 return createSourceListDAGScheduler(IS, OptLevel);
299 if (TLI->getSchedulingPreference() == Sched::RegPressure)
300 return createBURRListDAGScheduler(IS, OptLevel);
301 if (TLI->getSchedulingPreference() == Sched::Hybrid)
302 return createHybridListDAGScheduler(IS, OptLevel);
303 if (TLI->getSchedulingPreference() == Sched::VLIW)
304 return createVLIWDAGScheduler(IS, OptLevel);
305 assert(TLI->getSchedulingPreference() == Sched::ILP &&
306 "Unknown sched type!");
307 return createILPListDAGScheduler(IS, OptLevel);
311 // EmitInstrWithCustomInserter - This method should be implemented by targets
312 // that mark instructions with the 'usesCustomInserter' flag. These
313 // instructions are special in various ways, which require special support to
314 // insert. The specified MachineInstr is created but not inserted into any
315 // basic blocks, and this method is called to expand it into a sequence of
316 // instructions, potentially also creating new basic blocks and control flow.
317 // When new basic blocks are inserted and the edges from MBB to its successors
318 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
321 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
322 MachineBasicBlock *MBB) const {
324 dbgs() << "If a target marks an instruction with "
325 "'usesCustomInserter', it must implement "
326 "TargetLowering::EmitInstrWithCustomInserter!";
328 llvm_unreachable(nullptr);
331 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
332 SDNode *Node) const {
333 assert(!MI->hasPostISelHook() &&
334 "If a target marks an instruction with 'hasPostISelHook', "
335 "it must implement TargetLowering::AdjustInstrPostInstrSelection!");
338 //===----------------------------------------------------------------------===//
339 // SelectionDAGISel code
340 //===----------------------------------------------------------------------===//
342 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm,
343 CodeGenOpt::Level OL) :
344 MachineFunctionPass(ID), TM(tm),
345 FuncInfo(new FunctionLoweringInfo()),
346 CurDAG(new SelectionDAG(tm, OL)),
347 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
351 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry());
352 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry());
353 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry());
354 initializeTargetLibraryInfoWrapperPassPass(
355 *PassRegistry::getPassRegistry());
358 SelectionDAGISel::~SelectionDAGISel() {
364 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
365 AU.addRequired<AliasAnalysis>();
366 AU.addPreserved<AliasAnalysis>();
367 AU.addRequired<GCModuleInfo>();
368 AU.addPreserved<GCModuleInfo>();
369 AU.addRequired<TargetLibraryInfoWrapperPass>();
370 if (UseMBPI && OptLevel != CodeGenOpt::None)
371 AU.addRequired<BranchProbabilityInfo>();
372 MachineFunctionPass::getAnalysisUsage(AU);
375 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that
376 /// may trap on it. In this case we have to split the edge so that the path
377 /// through the predecessor block that doesn't go to the phi block doesn't
378 /// execute the possibly trapping instruction.
380 /// This is required for correctness, so it must be done at -O0.
382 static void SplitCriticalSideEffectEdges(Function &Fn, AliasAnalysis *AA) {
383 // Loop for blocks with phi nodes.
384 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
385 PHINode *PN = dyn_cast<PHINode>(BB->begin());
389 // For each block with a PHI node, check to see if any of the input values
390 // are potentially trapping constant expressions. Constant expressions are
391 // the only potentially trapping value that can occur as the argument to a
393 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I)
394 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
395 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i));
396 if (!CE || !CE->canTrap()) continue;
398 // The only case we have to worry about is when the edge is critical.
399 // Since this block has a PHI Node, we assume it has multiple input
400 // edges: check to see if the pred has multiple successors.
401 BasicBlock *Pred = PN->getIncomingBlock(i);
402 if (Pred->getTerminator()->getNumSuccessors() == 1)
405 // Okay, we have to split this edge.
407 Pred->getTerminator(), GetSuccessorNumber(Pred, BB),
408 CriticalEdgeSplittingOptions(AA).setMergeIdenticalEdges());
414 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
415 // Do some sanity-checking on the command-line options.
416 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) &&
417 "-fast-isel-verbose requires -fast-isel");
418 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
419 "-fast-isel-abort requires -fast-isel");
421 const Function &Fn = *mf.getFunction();
424 // Reset the target options before resetting the optimization
426 // FIXME: This is a horrible hack and should be processed via
427 // codegen looking at the optimization level explicitly when
428 // it wants to look at it.
429 TM.resetTargetOptions(Fn);
430 // Reset OptLevel to None for optnone functions.
431 CodeGenOpt::Level NewOptLevel = OptLevel;
432 if (Fn.hasFnAttribute(Attribute::OptimizeNone))
433 NewOptLevel = CodeGenOpt::None;
434 OptLevelChanger OLC(*this, NewOptLevel);
436 TII = MF->getSubtarget().getInstrInfo();
437 TLI = MF->getSubtarget().getTargetLowering();
438 RegInfo = &MF->getRegInfo();
439 AA = &getAnalysis<AliasAnalysis>();
440 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
441 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr;
443 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
445 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), AA);
448 FuncInfo->set(Fn, *MF, CurDAG);
450 if (UseMBPI && OptLevel != CodeGenOpt::None)
451 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>();
453 FuncInfo->BPI = nullptr;
455 SDB->init(GFI, *AA, LibInfo);
457 MF->setHasInlineAsm(false);
459 SelectAllBasicBlocks(Fn);
461 // If the first basic block in the function has live ins that need to be
462 // copied into vregs, emit the copies into the top of the block before
463 // emitting the code for the block.
464 MachineBasicBlock *EntryMBB = MF->begin();
465 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
466 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII);
468 DenseMap<unsigned, unsigned> LiveInMap;
469 if (!FuncInfo->ArgDbgValues.empty())
470 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(),
471 E = RegInfo->livein_end(); LI != E; ++LI)
473 LiveInMap.insert(std::make_pair(LI->first, LI->second));
475 // Insert DBG_VALUE instructions for function arguments to the entry block.
476 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) {
477 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1];
478 bool hasFI = MI->getOperand(0).isFI();
480 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
481 if (TargetRegisterInfo::isPhysicalRegister(Reg))
482 EntryMBB->insert(EntryMBB->begin(), MI);
484 MachineInstr *Def = RegInfo->getVRegDef(Reg);
486 MachineBasicBlock::iterator InsertPos = Def;
487 // FIXME: VR def may not be in entry block.
488 Def->getParent()->insert(std::next(InsertPos), MI);
490 DEBUG(dbgs() << "Dropping debug info for dead vreg"
491 << TargetRegisterInfo::virtReg2Index(Reg) << "\n");
494 // If Reg is live-in then update debug info to track its copy in a vreg.
495 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg);
496 if (LDI != LiveInMap.end()) {
497 assert(!hasFI && "There's no handling of frame pointer updating here yet "
499 MachineInstr *Def = RegInfo->getVRegDef(LDI->second);
500 MachineBasicBlock::iterator InsertPos = Def;
501 const MDNode *Variable = MI->getDebugVariable();
502 const MDNode *Expr = MI->getDebugExpression();
503 bool IsIndirect = MI->isIndirectDebugValue();
504 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0;
505 // Def is never a terminator here, so it is ok to increment InsertPos.
506 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(),
507 TII->get(TargetOpcode::DBG_VALUE), IsIndirect, LDI->second, Offset,
510 // If this vreg is directly copied into an exported register then
511 // that COPY instructions also need DBG_VALUE, if it is the only
512 // user of LDI->second.
513 MachineInstr *CopyUseMI = nullptr;
514 for (MachineRegisterInfo::use_instr_iterator
515 UI = RegInfo->use_instr_begin(LDI->second),
516 E = RegInfo->use_instr_end(); UI != E; ) {
517 MachineInstr *UseMI = &*(UI++);
518 if (UseMI->isDebugValue()) continue;
519 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
520 CopyUseMI = UseMI; continue;
522 // Otherwise this is another use or second copy use.
523 CopyUseMI = nullptr; break;
526 MachineInstr *NewMI =
527 BuildMI(*MF, CopyUseMI->getDebugLoc(),
528 TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
529 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr);
530 MachineBasicBlock::iterator Pos = CopyUseMI;
531 EntryMBB->insertAfter(Pos, NewMI);
536 // Determine if there are any calls in this machine function.
537 MachineFrameInfo *MFI = MF->getFrameInfo();
538 for (const auto &MBB : *MF) {
539 if (MFI->hasCalls() && MF->hasInlineAsm())
542 for (const auto &MI : MBB) {
543 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
544 if ((MCID.isCall() && !MCID.isReturn()) ||
545 MI.isStackAligningInlineAsm()) {
546 MFI->setHasCalls(true);
548 if (MI.isInlineAsm()) {
549 MF->setHasInlineAsm(true);
554 // Determine if there is a call to setjmp in the machine function.
555 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice());
557 // Replace forward-declared registers with the registers containing
558 // the desired value.
559 MachineRegisterInfo &MRI = MF->getRegInfo();
560 for (DenseMap<unsigned, unsigned>::iterator
561 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
563 unsigned From = I->first;
564 unsigned To = I->second;
565 // If To is also scheduled to be replaced, find what its ultimate
568 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To);
572 // Make sure the new register has a sufficiently constrained register class.
573 if (TargetRegisterInfo::isVirtualRegister(From) &&
574 TargetRegisterInfo::isVirtualRegister(To))
575 MRI.constrainRegClass(To, MRI.getRegClass(From));
577 MRI.replaceRegWith(From, To);
580 // Freeze the set of reserved registers now that MachineFrameInfo has been
581 // set up. All the information required by getReservedRegs() should be
583 MRI.freezeReservedRegs(*MF);
585 // Release function-specific state. SDB and CurDAG are already cleared
589 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n");
590 DEBUG(MF->print(dbgs()));
595 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
596 BasicBlock::const_iterator End,
598 // Lower all of the non-terminator instructions. If a call is emitted
599 // as a tail call, cease emitting nodes for this block. Terminators
600 // are handled below.
601 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I)
604 // Make sure the root of the DAG is up-to-date.
605 CurDAG->setRoot(SDB->getControlRoot());
606 HadTailCall = SDB->HasTailCall;
609 // Final step, emit the lowered DAG as machine code.
613 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
614 SmallPtrSet<SDNode*, 128> VisitedNodes;
615 SmallVector<SDNode*, 128> Worklist;
617 Worklist.push_back(CurDAG->getRoot().getNode());
623 SDNode *N = Worklist.pop_back_val();
625 // If we've already seen this node, ignore it.
626 if (!VisitedNodes.insert(N).second)
629 // Otherwise, add all chain operands to the worklist.
630 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
631 if (N->getOperand(i).getValueType() == MVT::Other)
632 Worklist.push_back(N->getOperand(i).getNode());
634 // If this is a CopyToReg with a vreg dest, process it.
635 if (N->getOpcode() != ISD::CopyToReg)
638 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
639 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
642 // Ignore non-scalar or non-integer values.
643 SDValue Src = N->getOperand(2);
644 EVT SrcVT = Src.getValueType();
645 if (!SrcVT.isInteger() || SrcVT.isVector())
648 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
649 CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
650 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
651 } while (!Worklist.empty());
654 void SelectionDAGISel::CodeGenAndEmitDAG() {
655 std::string GroupName;
656 if (TimePassesIsEnabled)
657 GroupName = "Instruction Selection and Scheduling";
658 std::string BlockName;
659 int BlockNumber = -1;
661 bool MatchFilterBB = false; (void)MatchFilterBB;
663 MatchFilterBB = (FilterDAGBasicBlockName.empty() ||
664 FilterDAGBasicBlockName ==
665 FuncInfo->MBB->getBasicBlock()->getName().str());
668 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
669 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
673 BlockNumber = FuncInfo->MBB->getNumber();
674 BlockName = MF->getName().str() + ":" +
675 FuncInfo->MBB->getBasicBlock()->getName().str();
677 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber
678 << " '" << BlockName << "'\n"; CurDAG->dump());
680 if (ViewDAGCombine1 && MatchFilterBB)
681 CurDAG->viewGraph("dag-combine1 input for " + BlockName);
683 // Run the DAG combiner in pre-legalize mode.
685 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled);
686 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel);
689 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber
690 << " '" << BlockName << "'\n"; CurDAG->dump());
692 // Second step, hack on the DAG until it only uses operations and types that
693 // the target supports.
694 if (ViewLegalizeTypesDAGs && MatchFilterBB)
695 CurDAG->viewGraph("legalize-types input for " + BlockName);
699 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled);
700 Changed = CurDAG->LegalizeTypes();
703 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber
704 << " '" << BlockName << "'\n"; CurDAG->dump());
706 CurDAG->NewNodesMustHaveLegalTypes = true;
709 if (ViewDAGCombineLT && MatchFilterBB)
710 CurDAG->viewGraph("dag-combine-lt input for " + BlockName);
712 // Run the DAG combiner in post-type-legalize mode.
714 NamedRegionTimer T("DAG Combining after legalize types", GroupName,
715 TimePassesIsEnabled);
716 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel);
719 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
720 << " '" << BlockName << "'\n"; CurDAG->dump());
725 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled);
726 Changed = CurDAG->LegalizeVectors();
731 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled);
732 CurDAG->LegalizeTypes();
735 if (ViewDAGCombineLT && MatchFilterBB)
736 CurDAG->viewGraph("dag-combine-lv input for " + BlockName);
738 // Run the DAG combiner in post-type-legalize mode.
740 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName,
741 TimePassesIsEnabled);
742 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel);
745 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#"
746 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump());
749 if (ViewLegalizeDAGs && MatchFilterBB)
750 CurDAG->viewGraph("legalize input for " + BlockName);
753 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled);
757 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber
758 << " '" << BlockName << "'\n"; CurDAG->dump());
760 if (ViewDAGCombine2 && MatchFilterBB)
761 CurDAG->viewGraph("dag-combine2 input for " + BlockName);
763 // Run the DAG combiner in post-legalize mode.
765 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled);
766 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel);
769 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber
770 << " '" << BlockName << "'\n"; CurDAG->dump());
772 if (OptLevel != CodeGenOpt::None)
773 ComputeLiveOutVRegInfo();
775 if (ViewISelDAGs && MatchFilterBB)
776 CurDAG->viewGraph("isel input for " + BlockName);
778 // Third, instruction select all of the operations to machine code, adding the
779 // code to the MachineBasicBlock.
781 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled);
782 DoInstructionSelection();
785 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber
786 << " '" << BlockName << "'\n"; CurDAG->dump());
788 if (ViewSchedDAGs && MatchFilterBB)
789 CurDAG->viewGraph("scheduler input for " + BlockName);
791 // Schedule machine code.
792 ScheduleDAGSDNodes *Scheduler = CreateScheduler();
794 NamedRegionTimer T("Instruction Scheduling", GroupName,
795 TimePassesIsEnabled);
796 Scheduler->Run(CurDAG, FuncInfo->MBB);
799 if (ViewSUnitDAGs && MatchFilterBB) Scheduler->viewGraph();
801 // Emit machine code to BB. This can change 'BB' to the last block being
803 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB;
805 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
807 // FuncInfo->InsertPt is passed by reference and set to the end of the
808 // scheduled instructions.
809 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt);
812 // If the block was split, make sure we update any references that are used to
813 // update PHI nodes later on.
814 if (FirstMBB != LastMBB)
815 SDB->UpdateSplitBlock(FirstMBB, LastMBB);
817 // Free the scheduler state.
819 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName,
820 TimePassesIsEnabled);
824 // Free the SelectionDAG state, now that we're finished with it.
829 /// ISelUpdater - helper class to handle updates of the instruction selection
831 class ISelUpdater : public SelectionDAG::DAGUpdateListener {
832 SelectionDAG::allnodes_iterator &ISelPosition;
834 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
835 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
837 /// NodeDeleted - Handle nodes deleted from the graph. If the node being
838 /// deleted is the current ISelPosition node, update ISelPosition.
840 void NodeDeleted(SDNode *N, SDNode *E) override {
841 if (ISelPosition == SelectionDAG::allnodes_iterator(N))
845 } // end anonymous namespace
847 void SelectionDAGISel::DoInstructionSelection() {
848 DEBUG(dbgs() << "===== Instruction selection begins: BB#"
849 << FuncInfo->MBB->getNumber()
850 << " '" << FuncInfo->MBB->getName() << "'\n");
854 // Select target instructions for the DAG.
856 // Number all nodes with a topological order and set DAGSize.
857 DAGSize = CurDAG->AssignTopologicalOrder();
859 // Create a dummy node (which is not added to allnodes), that adds
860 // a reference to the root node, preventing it from being deleted,
861 // and tracking any changes of the root.
862 HandleSDNode Dummy(CurDAG->getRoot());
863 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
866 // Make sure that ISelPosition gets properly updated when nodes are deleted
867 // in calls made from this function.
868 ISelUpdater ISU(*CurDAG, ISelPosition);
870 // The AllNodes list is now topological-sorted. Visit the
871 // nodes by starting at the end of the list (the root of the
872 // graph) and preceding back toward the beginning (the entry
874 while (ISelPosition != CurDAG->allnodes_begin()) {
875 SDNode *Node = --ISelPosition;
876 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes,
877 // but there are currently some corner cases that it misses. Also, this
878 // makes it theoretically possible to disable the DAGCombiner.
879 if (Node->use_empty())
882 SDNode *ResNode = Select(Node);
884 // FIXME: This is pretty gross. 'Select' should be changed to not return
885 // anything at all and this code should be nuked with a tactical strike.
887 // If node should not be replaced, continue with the next one.
888 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE)
892 ReplaceUses(Node, ResNode);
895 // If after the replacement this node is not used any more,
896 // remove this dead node.
897 if (Node->use_empty()) // Don't delete EntryToken, etc.
898 CurDAG->RemoveDeadNode(Node);
901 CurDAG->setRoot(Dummy.getValue());
904 DEBUG(dbgs() << "===== Instruction selection ends:\n");
906 PostprocessISelDAG();
909 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
910 /// do other setup for EH landing-pad blocks.
911 void SelectionDAGISel::PrepareEHLandingPad() {
912 MachineBasicBlock *MBB = FuncInfo->MBB;
914 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy());
916 // Add a label to mark the beginning of the landing pad. Deletion of the
917 // landing pad can thus be detected via the MachineModuleInfo.
918 MCSymbol *Label = MF->getMMI().addLandingPad(MBB);
920 // Assign the call site to the landing pad's begin label.
921 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]);
923 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
924 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
927 if (TM.getMCAsmInfo()->getExceptionHandlingType() ==
928 ExceptionHandling::MSVC) {
929 // Make virtual registers and a series of labels that fill in values for the
931 auto &RI = MF->getRegInfo();
932 FuncInfo->ExceptionSelectorVirtReg = RI.createVirtualRegister(PtrRC);
934 // Get all invoke BBs that will unwind into the clause BBs.
935 SmallVector<MachineBasicBlock *, 4> InvokeBBs(MBB->pred_begin(),
938 // Emit separate machine basic blocks with separate labels for each clause
939 // before the main landing pad block.
940 const BasicBlock *LLVMBB = MBB->getBasicBlock();
941 const LandingPadInst *LPadInst = LLVMBB->getLandingPadInst();
942 MachineInstrBuilder SelectorPHI = BuildMI(
943 *MBB, MBB->begin(), SDB->getCurDebugLoc(), TII->get(TargetOpcode::PHI),
944 FuncInfo->ExceptionSelectorVirtReg);
945 for (unsigned I = 0, E = LPadInst->getNumClauses(); I != E; ++I) {
946 // Skip filter clauses, we can't implement them yet.
947 if (LPadInst->isFilter(I))
950 MachineBasicBlock *ClauseBB = MF->CreateMachineBasicBlock(LLVMBB);
951 MF->insert(MBB, ClauseBB);
953 // Add the edge from the invoke to the clause.
954 for (MachineBasicBlock *InvokeBB : InvokeBBs)
955 InvokeBB->addSuccessor(ClauseBB);
957 // Mark the clause as a landing pad or MI passes will delete it.
958 ClauseBB->setIsLandingPad();
960 GlobalValue *ClauseGV = ExtractTypeInfo(LPadInst->getClause(I));
962 // Start the BB with a label.
963 MCSymbol *ClauseLabel = MF->getMMI().addClauseForLandingPad(MBB);
964 BuildMI(*ClauseBB, ClauseBB->begin(), SDB->getCurDebugLoc(), II)
965 .addSym(ClauseLabel);
967 // Construct a simple BB that defines a register with the typeid constant.
968 FuncInfo->MBB = ClauseBB;
969 FuncInfo->InsertPt = ClauseBB->end();
970 unsigned VReg = SDB->visitLandingPadClauseBB(ClauseGV, MBB);
971 CurDAG->setRoot(SDB->getRoot());
975 // Add the typeid virtual register to the phi in the main landing pad.
976 SelectorPHI.addReg(VReg).addMBB(ClauseBB);
979 // Remove the edge from the invoke to the lpad.
980 for (MachineBasicBlock *InvokeBB : InvokeBBs)
981 InvokeBB->removeSuccessor(MBB);
983 // Restore FuncInfo back to its previous state and select the main landing
986 FuncInfo->InsertPt = MBB->end();
990 // Mark exception register as live in.
991 if (unsigned Reg = TLI->getExceptionPointerRegister())
992 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC);
994 // Mark exception selector register as live in.
995 if (unsigned Reg = TLI->getExceptionSelectorRegister())
996 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC);
999 /// isFoldedOrDeadInstruction - Return true if the specified instruction is
1000 /// side-effect free and is either dead or folded into a generated instruction.
1001 /// Return false if it needs to be emitted.
1002 static bool isFoldedOrDeadInstruction(const Instruction *I,
1003 FunctionLoweringInfo *FuncInfo) {
1004 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded.
1005 !isa<TerminatorInst>(I) && // Terminators aren't folded.
1006 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded.
1007 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded.
1008 !FuncInfo->isExportedInst(I); // Exported instrs must be computed.
1012 // Collect per Instruction statistics for fast-isel misses. Only those
1013 // instructions that cause the bail are accounted for. It does not account for
1014 // instructions higher in the block. Thus, summing the per instructions stats
1015 // will not add up to what is reported by NumFastIselFailures.
1016 static void collectFailStats(const Instruction *I) {
1017 switch (I->getOpcode()) {
1018 default: assert (0 && "<Invalid operator> ");
1021 case Instruction::Ret: NumFastIselFailRet++; return;
1022 case Instruction::Br: NumFastIselFailBr++; return;
1023 case Instruction::Switch: NumFastIselFailSwitch++; return;
1024 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return;
1025 case Instruction::Invoke: NumFastIselFailInvoke++; return;
1026 case Instruction::Resume: NumFastIselFailResume++; return;
1027 case Instruction::Unreachable: NumFastIselFailUnreachable++; return;
1029 // Standard binary operators...
1030 case Instruction::Add: NumFastIselFailAdd++; return;
1031 case Instruction::FAdd: NumFastIselFailFAdd++; return;
1032 case Instruction::Sub: NumFastIselFailSub++; return;
1033 case Instruction::FSub: NumFastIselFailFSub++; return;
1034 case Instruction::Mul: NumFastIselFailMul++; return;
1035 case Instruction::FMul: NumFastIselFailFMul++; return;
1036 case Instruction::UDiv: NumFastIselFailUDiv++; return;
1037 case Instruction::SDiv: NumFastIselFailSDiv++; return;
1038 case Instruction::FDiv: NumFastIselFailFDiv++; return;
1039 case Instruction::URem: NumFastIselFailURem++; return;
1040 case Instruction::SRem: NumFastIselFailSRem++; return;
1041 case Instruction::FRem: NumFastIselFailFRem++; return;
1043 // Logical operators...
1044 case Instruction::And: NumFastIselFailAnd++; return;
1045 case Instruction::Or: NumFastIselFailOr++; return;
1046 case Instruction::Xor: NumFastIselFailXor++; return;
1048 // Memory instructions...
1049 case Instruction::Alloca: NumFastIselFailAlloca++; return;
1050 case Instruction::Load: NumFastIselFailLoad++; return;
1051 case Instruction::Store: NumFastIselFailStore++; return;
1052 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return;
1053 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return;
1054 case Instruction::Fence: NumFastIselFailFence++; return;
1055 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return;
1057 // Convert instructions...
1058 case Instruction::Trunc: NumFastIselFailTrunc++; return;
1059 case Instruction::ZExt: NumFastIselFailZExt++; return;
1060 case Instruction::SExt: NumFastIselFailSExt++; return;
1061 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return;
1062 case Instruction::FPExt: NumFastIselFailFPExt++; return;
1063 case Instruction::FPToUI: NumFastIselFailFPToUI++; return;
1064 case Instruction::FPToSI: NumFastIselFailFPToSI++; return;
1065 case Instruction::UIToFP: NumFastIselFailUIToFP++; return;
1066 case Instruction::SIToFP: NumFastIselFailSIToFP++; return;
1067 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return;
1068 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return;
1069 case Instruction::BitCast: NumFastIselFailBitCast++; return;
1071 // Other instructions...
1072 case Instruction::ICmp: NumFastIselFailICmp++; return;
1073 case Instruction::FCmp: NumFastIselFailFCmp++; return;
1074 case Instruction::PHI: NumFastIselFailPHI++; return;
1075 case Instruction::Select: NumFastIselFailSelect++; return;
1076 case Instruction::Call: {
1077 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
1078 switch (Intrinsic->getIntrinsicID()) {
1080 NumFastIselFailIntrinsicCall++; return;
1081 case Intrinsic::sadd_with_overflow:
1082 NumFastIselFailSAddWithOverflow++; return;
1083 case Intrinsic::uadd_with_overflow:
1084 NumFastIselFailUAddWithOverflow++; return;
1085 case Intrinsic::ssub_with_overflow:
1086 NumFastIselFailSSubWithOverflow++; return;
1087 case Intrinsic::usub_with_overflow:
1088 NumFastIselFailUSubWithOverflow++; return;
1089 case Intrinsic::smul_with_overflow:
1090 NumFastIselFailSMulWithOverflow++; return;
1091 case Intrinsic::umul_with_overflow:
1092 NumFastIselFailUMulWithOverflow++; return;
1093 case Intrinsic::frameaddress:
1094 NumFastIselFailFrameaddress++; return;
1095 case Intrinsic::sqrt:
1096 NumFastIselFailSqrt++; return;
1097 case Intrinsic::experimental_stackmap:
1098 NumFastIselFailStackMap++; return;
1099 case Intrinsic::experimental_patchpoint_void: // fall-through
1100 case Intrinsic::experimental_patchpoint_i64:
1101 NumFastIselFailPatchPoint++; return;
1104 NumFastIselFailCall++;
1107 case Instruction::Shl: NumFastIselFailShl++; return;
1108 case Instruction::LShr: NumFastIselFailLShr++; return;
1109 case Instruction::AShr: NumFastIselFailAShr++; return;
1110 case Instruction::VAArg: NumFastIselFailVAArg++; return;
1111 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return;
1112 case Instruction::InsertElement: NumFastIselFailInsertElement++; return;
1113 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return;
1114 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return;
1115 case Instruction::InsertValue: NumFastIselFailInsertValue++; return;
1116 case Instruction::LandingPad: NumFastIselFailLandingPad++; return;
1121 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
1122 // Initialize the Fast-ISel state, if needed.
1123 FastISel *FastIS = nullptr;
1124 if (TM.Options.EnableFastISel)
1125 FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
1127 // Iterate over all basic blocks in the function.
1128 ReversePostOrderTraversal<const Function*> RPOT(&Fn);
1129 for (ReversePostOrderTraversal<const Function*>::rpo_iterator
1130 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) {
1131 const BasicBlock *LLVMBB = *I;
1133 if (OptLevel != CodeGenOpt::None) {
1134 bool AllPredsVisited = true;
1135 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB);
1137 if (!FuncInfo->VisitedBBs.count(*PI)) {
1138 AllPredsVisited = false;
1143 if (AllPredsVisited) {
1144 for (BasicBlock::const_iterator I = LLVMBB->begin();
1145 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1146 FuncInfo->ComputePHILiveOutRegInfo(PN);
1148 for (BasicBlock::const_iterator I = LLVMBB->begin();
1149 const PHINode *PN = dyn_cast<PHINode>(I); ++I)
1150 FuncInfo->InvalidatePHILiveOutRegInfo(PN);
1153 FuncInfo->VisitedBBs.insert(LLVMBB);
1156 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
1157 BasicBlock::const_iterator const End = LLVMBB->end();
1158 BasicBlock::const_iterator BI = End;
1160 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
1161 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
1163 // Setup an EH landing-pad block.
1164 FuncInfo->ExceptionPointerVirtReg = 0;
1165 FuncInfo->ExceptionSelectorVirtReg = 0;
1166 if (FuncInfo->MBB->isLandingPad())
1167 PrepareEHLandingPad();
1169 // Before doing SelectionDAG ISel, see if FastISel has been requested.
1171 FastIS->startNewBlock();
1173 // Emit code for any incoming arguments. This must happen before
1174 // beginning FastISel on the entry block.
1175 if (LLVMBB == &Fn.getEntryBlock()) {
1178 // Lower any arguments needed in this block if this is the entry block.
1179 if (!FastIS->lowerArguments()) {
1180 // Fast isel failed to lower these arguments
1181 ++NumFastIselFailLowerArguments;
1182 if (EnableFastISelAbortArgs)
1183 llvm_unreachable("FastISel didn't lower all arguments");
1185 // Use SelectionDAG argument lowering
1187 CurDAG->setRoot(SDB->getControlRoot());
1189 CodeGenAndEmitDAG();
1192 // If we inserted any instructions at the beginning, make a note of
1193 // where they are, so we can be sure to emit subsequent instructions
1195 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
1196 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt));
1198 FastIS->setLastLocalValue(nullptr);
1201 unsigned NumFastIselRemaining = std::distance(Begin, End);
1202 // Do FastISel on as many instructions as possible.
1203 for (; BI != Begin; --BI) {
1204 const Instruction *Inst = std::prev(BI);
1206 // If we no longer require this instruction, skip it.
1207 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) {
1208 --NumFastIselRemaining;
1212 // Bottom-up: reset the insert pos at the top, after any local-value
1214 FastIS->recomputeInsertPt();
1216 // Try to select the instruction with FastISel.
1217 if (FastIS->selectInstruction(Inst)) {
1218 --NumFastIselRemaining;
1219 ++NumFastIselSuccess;
1220 // If fast isel succeeded, skip over all the folded instructions, and
1221 // then see if there is a load right before the selected instructions.
1222 // Try to fold the load if so.
1223 const Instruction *BeforeInst = Inst;
1224 while (BeforeInst != Begin) {
1225 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst));
1226 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo))
1229 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) &&
1230 BeforeInst->hasOneUse() &&
1231 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) {
1232 // If we succeeded, don't re-select the load.
1233 BI = std::next(BasicBlock::const_iterator(BeforeInst));
1234 --NumFastIselRemaining;
1235 ++NumFastIselSuccess;
1241 if (EnableFastISelVerbose2)
1242 collectFailStats(Inst);
1245 // Then handle certain instructions as single-LLVM-Instruction blocks.
1246 if (isa<CallInst>(Inst)) {
1248 if (EnableFastISelVerbose || EnableFastISelAbort) {
1249 dbgs() << "FastISel missed call: ";
1253 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
1254 unsigned &R = FuncInfo->ValueMap[Inst];
1256 R = FuncInfo->CreateRegs(Inst->getType());
1259 bool HadTailCall = false;
1260 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt;
1261 SelectBasicBlock(Inst, BI, HadTailCall);
1263 // If the call was emitted as a tail call, we're done with the block.
1264 // We also need to delete any previously emitted instructions.
1266 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end());
1271 // Recompute NumFastIselRemaining as Selection DAG instruction
1272 // selection may have handled the call, input args, etc.
1273 unsigned RemainingNow = std::distance(Begin, BI);
1274 NumFastIselFailures += NumFastIselRemaining - RemainingNow;
1275 NumFastIselRemaining = RemainingNow;
1279 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) {
1280 // Don't abort, and use a different message for terminator misses.
1281 NumFastIselFailures += NumFastIselRemaining;
1282 if (EnableFastISelVerbose || EnableFastISelAbort) {
1283 dbgs() << "FastISel missed terminator: ";
1287 NumFastIselFailures += NumFastIselRemaining;
1288 if (EnableFastISelVerbose || EnableFastISelAbort) {
1289 dbgs() << "FastISel miss: ";
1292 if (EnableFastISelAbort)
1293 // The "fast" selector couldn't handle something and bailed.
1294 // For the purpose of debugging, just abort.
1295 llvm_unreachable("FastISel didn't select the entire block");
1300 FastIS->recomputeInsertPt();
1302 // Lower any arguments needed in this block if this is the entry block.
1303 if (LLVMBB == &Fn.getEntryBlock()) {
1312 ++NumFastIselBlocks;
1315 // Run SelectionDAG instruction selection on the remainder of the block
1316 // not handled by FastISel. If FastISel is not run, this is the entire
1319 SelectBasicBlock(Begin, BI, HadTailCall);
1323 FuncInfo->PHINodesToUpdate.clear();
1327 SDB->clearDanglingDebugInfo();
1328 SDB->SPDescriptor.resetPerFunctionState();
1331 /// Given that the input MI is before a partial terminator sequence TSeq, return
1332 /// true if M + TSeq also a partial terminator sequence.
1334 /// A Terminator sequence is a sequence of MachineInstrs which at this point in
1335 /// lowering copy vregs into physical registers, which are then passed into
1336 /// terminator instructors so we can satisfy ABI constraints. A partial
1337 /// terminator sequence is an improper subset of a terminator sequence (i.e. it
1338 /// may be the whole terminator sequence).
1339 static bool MIIsInTerminatorSequence(const MachineInstr *MI) {
1340 // If we do not have a copy or an implicit def, we return true if and only if
1341 // MI is a debug value.
1342 if (!MI->isCopy() && !MI->isImplicitDef())
1343 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the
1344 // physical registers if there is debug info associated with the terminator
1345 // of our mbb. We want to include said debug info in our terminator
1346 // sequence, so we return true in that case.
1347 return MI->isDebugValue();
1349 // We have left the terminator sequence if we are not doing one of the
1352 // 1. Copying a vreg into a physical register.
1353 // 2. Copying a vreg into a vreg.
1354 // 3. Defining a register via an implicit def.
1356 // OPI should always be a register definition...
1357 MachineInstr::const_mop_iterator OPI = MI->operands_begin();
1358 if (!OPI->isReg() || !OPI->isDef())
1361 // Defining any register via an implicit def is always ok.
1362 if (MI->isImplicitDef())
1365 // Grab the copy source...
1366 MachineInstr::const_mop_iterator OPI2 = OPI;
1368 assert(OPI2 != MI->operands_end()
1369 && "Should have a copy implying we should have 2 arguments.");
1371 // Make sure that the copy dest is not a vreg when the copy source is a
1372 // physical register.
1373 if (!OPI2->isReg() ||
1374 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) &&
1375 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg())))
1381 /// Find the split point at which to splice the end of BB into its success stack
1382 /// protector check machine basic block.
1384 /// On many platforms, due to ABI constraints, terminators, even before register
1385 /// allocation, use physical registers. This creates an issue for us since
1386 /// physical registers at this point can not travel across basic
1387 /// blocks. Luckily, selectiondag always moves physical registers into vregs
1388 /// when they enter functions and moves them through a sequence of copies back
1389 /// into the physical registers right before the terminator creating a
1390 /// ``Terminator Sequence''. This function is searching for the beginning of the
1391 /// terminator sequence so that we can ensure that we splice off not just the
1392 /// terminator, but additionally the copies that move the vregs into the
1393 /// physical registers.
1394 static MachineBasicBlock::iterator
1395 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) {
1396 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator();
1398 if (SplitPoint == BB->begin())
1401 MachineBasicBlock::iterator Start = BB->begin();
1402 MachineBasicBlock::iterator Previous = SplitPoint;
1405 while (MIIsInTerminatorSequence(Previous)) {
1406 SplitPoint = Previous;
1407 if (Previous == Start)
1416 SelectionDAGISel::FinishBasicBlock() {
1418 DEBUG(dbgs() << "Total amount of phi nodes to update: "
1419 << FuncInfo->PHINodesToUpdate.size() << "\n";
1420 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i)
1421 dbgs() << "Node " << i << " : ("
1422 << FuncInfo->PHINodesToUpdate[i].first
1423 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n");
1425 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() &&
1426 SDB->JTCases.empty() &&
1427 SDB->BitTestCases.empty();
1429 // Next, now that we know what the last MBB the LLVM BB expanded is, update
1430 // PHI nodes in successors.
1431 if (MustUpdatePHINodes) {
1432 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1433 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1434 assert(PHI->isPHI() &&
1435 "This is not a machine PHI node that we are updating!");
1436 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
1438 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1442 // Handle stack protector.
1443 if (SDB->SPDescriptor.shouldEmitStackProtector()) {
1444 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB();
1445 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB();
1447 // Find the split point to split the parent mbb. At the same time copy all
1448 // physical registers used in the tail of parent mbb into virtual registers
1449 // before the split point and back into physical registers after the split
1450 // point. This prevents us needing to deal with Live-ins and many other
1451 // register allocation issues caused by us splitting the parent mbb. The
1452 // register allocator will clean up said virtual copies later on.
1453 MachineBasicBlock::iterator SplitPoint =
1454 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc());
1456 // Splice the terminator of ParentMBB into SuccessMBB.
1457 SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
1461 // Add compare/jump on neq/jump to the parent BB.
1462 FuncInfo->MBB = ParentMBB;
1463 FuncInfo->InsertPt = ParentMBB->end();
1464 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
1465 CurDAG->setRoot(SDB->getRoot());
1467 CodeGenAndEmitDAG();
1469 // CodeGen Failure MBB if we have not codegened it yet.
1470 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB();
1471 if (!FailureMBB->size()) {
1472 FuncInfo->MBB = FailureMBB;
1473 FuncInfo->InsertPt = FailureMBB->end();
1474 SDB->visitSPDescriptorFailure(SDB->SPDescriptor);
1475 CurDAG->setRoot(SDB->getRoot());
1477 CodeGenAndEmitDAG();
1480 // Clear the Per-BB State.
1481 SDB->SPDescriptor.resetPerBBState();
1484 // If we updated PHI Nodes, return early.
1485 if (MustUpdatePHINodes)
1488 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) {
1489 // Lower header first, if it wasn't already lowered
1490 if (!SDB->BitTestCases[i].Emitted) {
1491 // Set the current basic block to the mbb we wish to insert the code into
1492 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
1493 FuncInfo->InsertPt = FuncInfo->MBB->end();
1495 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
1496 CurDAG->setRoot(SDB->getRoot());
1498 CodeGenAndEmitDAG();
1501 uint32_t UnhandledWeight = 0;
1502 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j)
1503 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight;
1505 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
1506 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight;
1507 // Set the current basic block to the mbb we wish to insert the code into
1508 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1509 FuncInfo->InsertPt = FuncInfo->MBB->end();
1512 SDB->visitBitTestCase(SDB->BitTestCases[i],
1513 SDB->BitTestCases[i].Cases[j+1].ThisBB,
1515 SDB->BitTestCases[i].Reg,
1516 SDB->BitTestCases[i].Cases[j],
1519 SDB->visitBitTestCase(SDB->BitTestCases[i],
1520 SDB->BitTestCases[i].Default,
1522 SDB->BitTestCases[i].Reg,
1523 SDB->BitTestCases[i].Cases[j],
1527 CurDAG->setRoot(SDB->getRoot());
1529 CodeGenAndEmitDAG();
1533 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1535 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1536 MachineBasicBlock *PHIBB = PHI->getParent();
1537 assert(PHI->isPHI() &&
1538 "This is not a machine PHI node that we are updating!");
1539 // This is "default" BB. We have two jumps to it. From "header" BB and
1540 // from last "case" BB.
1541 if (PHIBB == SDB->BitTestCases[i].Default)
1542 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1543 .addMBB(SDB->BitTestCases[i].Parent)
1544 .addReg(FuncInfo->PHINodesToUpdate[pi].second)
1545 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB);
1546 // One of "cases" BB.
1547 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size();
1549 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB;
1550 if (cBB->isSuccessor(PHIBB))
1551 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1555 SDB->BitTestCases.clear();
1557 // If the JumpTable record is filled in, then we need to emit a jump table.
1558 // Updating the PHI nodes is tricky in this case, since we need to determine
1559 // whether the PHI is a successor of the range check MBB or the jump table MBB
1560 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) {
1561 // Lower header first, if it wasn't already lowered
1562 if (!SDB->JTCases[i].first.Emitted) {
1563 // Set the current basic block to the mbb we wish to insert the code into
1564 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
1565 FuncInfo->InsertPt = FuncInfo->MBB->end();
1567 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
1569 CurDAG->setRoot(SDB->getRoot());
1571 CodeGenAndEmitDAG();
1574 // Set the current basic block to the mbb we wish to insert the code into
1575 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
1576 FuncInfo->InsertPt = FuncInfo->MBB->end();
1578 SDB->visitJumpTable(SDB->JTCases[i].second);
1579 CurDAG->setRoot(SDB->getRoot());
1581 CodeGenAndEmitDAG();
1584 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
1586 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1587 MachineBasicBlock *PHIBB = PHI->getParent();
1588 assert(PHI->isPHI() &&
1589 "This is not a machine PHI node that we are updating!");
1590 // "default" BB. We can go there only from header BB.
1591 if (PHIBB == SDB->JTCases[i].second.Default)
1592 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1593 .addMBB(SDB->JTCases[i].first.HeaderBB);
1594 // JT BB. Just iterate over successors here
1595 if (FuncInfo->MBB->isSuccessor(PHIBB))
1596 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1599 SDB->JTCases.clear();
1601 // If the switch block involved a branch to one of the actual successors, we
1602 // need to update PHI nodes in that block.
1603 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) {
1604 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1605 assert(PHI->isPHI() &&
1606 "This is not a machine PHI node that we are updating!");
1607 if (FuncInfo->MBB->isSuccessor(PHI->getParent()))
1608 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1611 // If we generated any switch lowering information, build and codegen any
1612 // additional DAGs necessary.
1613 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
1614 // Set the current basic block to the mbb we wish to insert the code into
1615 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
1616 FuncInfo->InsertPt = FuncInfo->MBB->end();
1618 // Determine the unique successors.
1619 SmallVector<MachineBasicBlock *, 2> Succs;
1620 Succs.push_back(SDB->SwitchCases[i].TrueBB);
1621 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB)
1622 Succs.push_back(SDB->SwitchCases[i].FalseBB);
1624 // Emit the code. Note that this could result in FuncInfo->MBB being split.
1625 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
1626 CurDAG->setRoot(SDB->getRoot());
1628 CodeGenAndEmitDAG();
1630 // Remember the last block, now that any splitting is done, for use in
1631 // populating PHI nodes in successors.
1632 MachineBasicBlock *ThisBB = FuncInfo->MBB;
1634 // Handle any PHI nodes in successors of this chunk, as if we were coming
1635 // from the original BB before switch expansion. Note that PHI nodes can
1636 // occur multiple times in PHINodesToUpdate. We have to be very careful to
1637 // handle them the right number of times.
1638 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
1639 FuncInfo->MBB = Succs[i];
1640 FuncInfo->InsertPt = FuncInfo->MBB->end();
1641 // FuncInfo->MBB may have been removed from the CFG if a branch was
1643 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1644 for (MachineBasicBlock::iterator
1645 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
1646 MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
1647 MachineInstrBuilder PHI(*MF, MBBI);
1648 // This value for this PHI node is recorded in PHINodesToUpdate.
1649 for (unsigned pn = 0; ; ++pn) {
1650 assert(pn != FuncInfo->PHINodesToUpdate.size() &&
1651 "Didn't find PHI entry!");
1652 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
1653 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
1661 SDB->SwitchCases.clear();
1665 /// Create the scheduler. If a specific scheduler was specified
1666 /// via the SchedulerRegistry, use it, otherwise select the
1667 /// one preferred by the target.
1669 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
1670 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
1674 RegisterScheduler::setDefault(Ctor);
1677 return Ctor(this, OptLevel);
1680 //===----------------------------------------------------------------------===//
1681 // Helper functions used by the generated instruction selector.
1682 //===----------------------------------------------------------------------===//
1683 // Calls to these methods are generated by tblgen.
1685 /// CheckAndMask - The isel is trying to match something like (and X, 255). If
1686 /// the dag combiner simplified the 255, we still want to match. RHS is the
1687 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
1688 /// specified in the .td file (e.g. 255).
1689 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
1690 int64_t DesiredMaskS) const {
1691 const APInt &ActualMask = RHS->getAPIntValue();
1692 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1694 // If the actual mask exactly matches, success!
1695 if (ActualMask == DesiredMask)
1698 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1699 if (ActualMask.intersects(~DesiredMask))
1702 // Otherwise, the DAG Combiner may have proven that the value coming in is
1703 // either already zero or is not demanded. Check for known zero input bits.
1704 APInt NeededMask = DesiredMask & ~ActualMask;
1705 if (CurDAG->MaskedValueIsZero(LHS, NeededMask))
1708 // TODO: check to see if missing bits are just not demanded.
1710 // Otherwise, this pattern doesn't match.
1714 /// CheckOrMask - The isel is trying to match something like (or X, 255). If
1715 /// the dag combiner simplified the 255, we still want to match. RHS is the
1716 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
1717 /// specified in the .td file (e.g. 255).
1718 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
1719 int64_t DesiredMaskS) const {
1720 const APInt &ActualMask = RHS->getAPIntValue();
1721 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
1723 // If the actual mask exactly matches, success!
1724 if (ActualMask == DesiredMask)
1727 // If the actual AND mask is allowing unallowed bits, this doesn't match.
1728 if (ActualMask.intersects(~DesiredMask))
1731 // Otherwise, the DAG Combiner may have proven that the value coming in is
1732 // either already zero or is not demanded. Check for known zero input bits.
1733 APInt NeededMask = DesiredMask & ~ActualMask;
1735 APInt KnownZero, KnownOne;
1736 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
1738 // If all the missing bits in the or are already known to be set, match!
1739 if ((NeededMask & KnownOne) == NeededMask)
1742 // TODO: check to see if missing bits are just not demanded.
1744 // Otherwise, this pattern doesn't match.
1749 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
1750 /// by tblgen. Others should not call it.
1751 void SelectionDAGISel::
1752 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) {
1753 std::vector<SDValue> InOps;
1754 std::swap(InOps, Ops);
1756 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0
1757 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1
1758 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc
1759 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack)
1761 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size();
1762 if (InOps[e-1].getValueType() == MVT::Glue)
1763 --e; // Don't process a glue operand if it is here.
1766 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
1767 if (!InlineAsm::isMemKind(Flags)) {
1768 // Just skip over this operand, copying the operands verbatim.
1769 Ops.insert(Ops.end(), InOps.begin()+i,
1770 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1);
1771 i += InlineAsm::getNumOperandRegisters(Flags) + 1;
1773 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 &&
1774 "Memory operand with multiple values?");
1775 // Otherwise, this is a memory operand. Ask the target to select it.
1776 std::vector<SDValue> SelOps;
1777 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps))
1778 report_fatal_error("Could not match memory address. Inline asm"
1781 // Add this to the output node.
1783 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size());
1784 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32));
1785 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
1790 // Add the glue input back if present.
1791 if (e != InOps.size())
1792 Ops.push_back(InOps.back());
1795 /// findGlueUse - Return use of MVT::Glue value produced by the specified
1798 static SDNode *findGlueUse(SDNode *N) {
1799 unsigned FlagResNo = N->getNumValues()-1;
1800 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
1801 SDUse &Use = I.getUse();
1802 if (Use.getResNo() == FlagResNo)
1803 return Use.getUser();
1808 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
1809 /// This function recursively traverses up the operand chain, ignoring
1811 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
1812 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited,
1813 bool IgnoreChains) {
1814 // The NodeID's are given uniques ID's where a node ID is guaranteed to be
1815 // greater than all of its (recursive) operands. If we scan to a point where
1816 // 'use' is smaller than the node we're scanning for, then we know we will
1819 // The Use may be -1 (unassigned) if it is a newly allocated node. This can
1820 // happen because we scan down to newly selected nodes in the case of glue
1822 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1))
1825 // Don't revisit nodes if we already scanned it and didn't fail, we know we
1826 // won't fail if we scan it again.
1827 if (!Visited.insert(Use).second)
1830 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
1831 // Ignore chain uses, they are validated by HandleMergeInputChains.
1832 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains)
1835 SDNode *N = Use->getOperand(i).getNode();
1837 if (Use == ImmedUse || Use == Root)
1838 continue; // We are not looking for immediate use.
1843 // Traverse up the operand chain.
1844 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains))
1850 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
1851 /// operand node N of U during instruction selection that starts at Root.
1852 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
1853 SDNode *Root) const {
1854 if (OptLevel == CodeGenOpt::None) return false;
1855 return N.hasOneUse();
1858 /// IsLegalToFold - Returns true if the specific operand node N of
1859 /// U can be folded during instruction selection that starts at Root.
1860 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
1861 CodeGenOpt::Level OptLevel,
1862 bool IgnoreChains) {
1863 if (OptLevel == CodeGenOpt::None) return false;
1865 // If Root use can somehow reach N through a path that that doesn't contain
1866 // U then folding N would create a cycle. e.g. In the following
1867 // diagram, Root can reach N through X. If N is folded into into Root, then
1868 // X is both a predecessor and a successor of U.
1879 // * indicates nodes to be folded together.
1881 // If Root produces glue, then it gets (even more) interesting. Since it
1882 // will be "glued" together with its glue use in the scheduler, we need to
1883 // check if it might reach N.
1902 // If GU (glue use) indirectly reaches N (the load), and Root folds N
1903 // (call it Fold), then X is a predecessor of GU and a successor of
1904 // Fold. But since Fold and GU are glued together, this will create
1905 // a cycle in the scheduling graph.
1907 // If the node has glue, walk down the graph to the "lowest" node in the
1909 EVT VT = Root->getValueType(Root->getNumValues()-1);
1910 while (VT == MVT::Glue) {
1911 SDNode *GU = findGlueUse(Root);
1915 VT = Root->getValueType(Root->getNumValues()-1);
1917 // If our query node has a glue result with a use, we've walked up it. If
1918 // the user (which has already been selected) has a chain or indirectly uses
1919 // the chain, our WalkChainUsers predicate will not consider it. Because of
1920 // this, we cannot ignore chains in this predicate.
1921 IgnoreChains = false;
1925 SmallPtrSet<SDNode*, 16> Visited;
1926 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains);
1929 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) {
1930 std::vector<SDValue> Ops(N->op_begin(), N->op_end());
1931 SelectInlineAsmMemoryOperands(Ops);
1933 EVT VTs[] = { MVT::Other, MVT::Glue };
1934 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), VTs, Ops);
1936 return New.getNode();
1940 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
1942 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(0));
1943 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1945 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0));
1946 SDValue New = CurDAG->getCopyFromReg(
1947 CurDAG->getEntryNode(), dl, Reg, Op->getValueType(0));
1949 return New.getNode();
1953 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
1955 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1));
1956 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0));
1957 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(),
1958 Op->getOperand(2).getValueType());
1959 SDValue New = CurDAG->getCopyToReg(
1960 CurDAG->getEntryNode(), dl, Reg, Op->getOperand(2));
1962 return New.getNode();
1967 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) {
1968 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0));
1971 /// GetVBR - decode a vbr encoding whose top bit is set.
1972 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
1973 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
1974 assert(Val >= 128 && "Not a VBR");
1975 Val &= 127; // Remove first vbr bit.
1980 NextBits = MatcherTable[Idx++];
1981 Val |= (NextBits&127) << Shift;
1983 } while (NextBits & 128);
1989 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of
1990 /// interior glue and chain results to use the new glue and chain results.
1991 void SelectionDAGISel::
1992 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain,
1993 const SmallVectorImpl<SDNode*> &ChainNodesMatched,
1995 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched,
1996 bool isMorphNodeTo) {
1997 SmallVector<SDNode*, 4> NowDeadNodes;
1999 // Now that all the normal results are replaced, we replace the chain and
2000 // glue results if present.
2001 if (!ChainNodesMatched.empty()) {
2002 assert(InputChain.getNode() &&
2003 "Matched input chains but didn't produce a chain");
2004 // Loop over all of the nodes we matched that produced a chain result.
2005 // Replace all the chain results with the final chain we ended up with.
2006 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2007 SDNode *ChainNode = ChainNodesMatched[i];
2009 // If this node was already deleted, don't look at it.
2010 if (ChainNode->getOpcode() == ISD::DELETED_NODE)
2013 // Don't replace the results of the root node if we're doing a
2015 if (ChainNode == NodeToMatch && isMorphNodeTo)
2018 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
2019 if (ChainVal.getValueType() == MVT::Glue)
2020 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
2021 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
2022 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain);
2024 // If the node became dead and we haven't already seen it, delete it.
2025 if (ChainNode->use_empty() &&
2026 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode))
2027 NowDeadNodes.push_back(ChainNode);
2031 // If the result produces glue, update any glue results in the matched
2032 // pattern with the glue result.
2033 if (InputGlue.getNode()) {
2034 // Handle any interior nodes explicitly marked.
2035 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) {
2036 SDNode *FRN = GlueResultNodesMatched[i];
2038 // If this node was already deleted, don't look at it.
2039 if (FRN->getOpcode() == ISD::DELETED_NODE)
2042 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue &&
2043 "Doesn't have a glue result");
2044 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1),
2047 // If the node became dead and we haven't already seen it, delete it.
2048 if (FRN->use_empty() &&
2049 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN))
2050 NowDeadNodes.push_back(FRN);
2054 if (!NowDeadNodes.empty())
2055 CurDAG->RemoveDeadNodes(NowDeadNodes);
2057 DEBUG(dbgs() << "ISEL: Match complete!\n");
2063 CR_LeadsToInteriorNode
2066 /// WalkChainUsers - Walk down the users of the specified chained node that is
2067 /// part of the pattern we're matching, looking at all of the users we find.
2068 /// This determines whether something is an interior node, whether we have a
2069 /// non-pattern node in between two pattern nodes (which prevent folding because
2070 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched
2071 /// between pattern nodes (in which case the TF becomes part of the pattern).
2073 /// The walk we do here is guaranteed to be small because we quickly get down to
2074 /// already selected nodes "below" us.
2076 WalkChainUsers(const SDNode *ChainedNode,
2077 SmallVectorImpl<SDNode*> &ChainedNodesInPattern,
2078 SmallVectorImpl<SDNode*> &InteriorChainedNodes) {
2079 ChainResult Result = CR_Simple;
2081 for (SDNode::use_iterator UI = ChainedNode->use_begin(),
2082 E = ChainedNode->use_end(); UI != E; ++UI) {
2083 // Make sure the use is of the chain, not some other value we produce.
2084 if (UI.getUse().getValueType() != MVT::Other) continue;
2088 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph.
2091 // If we see an already-selected machine node, then we've gone beyond the
2092 // pattern that we're selecting down into the already selected chunk of the
2094 unsigned UserOpcode = User->getOpcode();
2095 if (User->isMachineOpcode() ||
2096 UserOpcode == ISD::CopyToReg ||
2097 UserOpcode == ISD::CopyFromReg ||
2098 UserOpcode == ISD::INLINEASM ||
2099 UserOpcode == ISD::EH_LABEL ||
2100 UserOpcode == ISD::LIFETIME_START ||
2101 UserOpcode == ISD::LIFETIME_END) {
2102 // If their node ID got reset to -1 then they've already been selected.
2103 // Treat them like a MachineOpcode.
2104 if (User->getNodeId() == -1)
2108 // If we have a TokenFactor, we handle it specially.
2109 if (User->getOpcode() != ISD::TokenFactor) {
2110 // If the node isn't a token factor and isn't part of our pattern, then it
2111 // must be a random chained node in between two nodes we're selecting.
2112 // This happens when we have something like:
2117 // Because we structurally match the load/store as a read/modify/write,
2118 // but the call is chained between them. We cannot fold in this case
2119 // because it would induce a cycle in the graph.
2120 if (!std::count(ChainedNodesInPattern.begin(),
2121 ChainedNodesInPattern.end(), User))
2122 return CR_InducesCycle;
2124 // Otherwise we found a node that is part of our pattern. For example in:
2128 // This would happen when we're scanning down from the load and see the
2129 // store as a user. Record that there is a use of ChainedNode that is
2130 // part of the pattern and keep scanning uses.
2131 Result = CR_LeadsToInteriorNode;
2132 InteriorChainedNodes.push_back(User);
2136 // If we found a TokenFactor, there are two cases to consider: first if the
2137 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no
2138 // uses of the TF are in our pattern) we just want to ignore it. Second,
2139 // the TokenFactor can be sandwiched in between two chained nodes, like so:
2145 // | \ DAG's like cheese
2148 // [TokenFactor] [Op]
2155 // In this case, the TokenFactor becomes part of our match and we rewrite it
2156 // as a new TokenFactor.
2158 // To distinguish these two cases, do a recursive walk down the uses.
2159 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) {
2161 // If the uses of the TokenFactor are just already-selected nodes, ignore
2162 // it, it is "below" our pattern.
2164 case CR_InducesCycle:
2165 // If the uses of the TokenFactor lead to nodes that are not part of our
2166 // pattern that are not selected, folding would turn this into a cycle,
2168 return CR_InducesCycle;
2169 case CR_LeadsToInteriorNode:
2170 break; // Otherwise, keep processing.
2173 // Okay, we know we're in the interesting interior case. The TokenFactor
2174 // is now going to be considered part of the pattern so that we rewrite its
2175 // uses (it may have uses that are not part of the pattern) with the
2176 // ultimate chain result of the generated code. We will also add its chain
2177 // inputs as inputs to the ultimate TokenFactor we create.
2178 Result = CR_LeadsToInteriorNode;
2179 ChainedNodesInPattern.push_back(User);
2180 InteriorChainedNodes.push_back(User);
2187 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains
2188 /// operation for when the pattern matched at least one node with a chains. The
2189 /// input vector contains a list of all of the chained nodes that we match. We
2190 /// must determine if this is a valid thing to cover (i.e. matching it won't
2191 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
2192 /// be used as the input node chain for the generated nodes.
2194 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
2195 SelectionDAG *CurDAG) {
2196 // Walk all of the chained nodes we've matched, recursively scanning down the
2197 // users of the chain result. This adds any TokenFactor nodes that are caught
2198 // in between chained nodes to the chained and interior nodes list.
2199 SmallVector<SDNode*, 3> InteriorChainedNodes;
2200 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2201 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched,
2202 InteriorChainedNodes) == CR_InducesCycle)
2203 return SDValue(); // Would induce a cycle.
2206 // Okay, we have walked all the matched nodes and collected TokenFactor nodes
2207 // that we are interested in. Form our input TokenFactor node.
2208 SmallVector<SDValue, 3> InputChains;
2209 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) {
2210 // Add the input chain of this node to the InputChains list (which will be
2211 // the operands of the generated TokenFactor) if it's not an interior node.
2212 SDNode *N = ChainNodesMatched[i];
2213 if (N->getOpcode() != ISD::TokenFactor) {
2214 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N))
2217 // Otherwise, add the input chain.
2218 SDValue InChain = ChainNodesMatched[i]->getOperand(0);
2219 assert(InChain.getValueType() == MVT::Other && "Not a chain");
2220 InputChains.push_back(InChain);
2224 // If we have a token factor, we want to add all inputs of the token factor
2225 // that are not part of the pattern we're matching.
2226 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
2227 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(),
2228 N->getOperand(op).getNode()))
2229 InputChains.push_back(N->getOperand(op));
2233 if (InputChains.size() == 1)
2234 return InputChains[0];
2235 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]),
2236 MVT::Other, InputChains);
2239 /// MorphNode - Handle morphing a node in place for the selector.
2240 SDNode *SelectionDAGISel::
2241 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
2242 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
2243 // It is possible we're using MorphNodeTo to replace a node with no
2244 // normal results with one that has a normal result (or we could be
2245 // adding a chain) and the input could have glue and chains as well.
2246 // In this case we need to shift the operands down.
2247 // FIXME: This is a horrible hack and broken in obscure cases, no worse
2248 // than the old isel though.
2249 int OldGlueResultNo = -1, OldChainResultNo = -1;
2251 unsigned NTMNumResults = Node->getNumValues();
2252 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
2253 OldGlueResultNo = NTMNumResults-1;
2254 if (NTMNumResults != 1 &&
2255 Node->getValueType(NTMNumResults-2) == MVT::Other)
2256 OldChainResultNo = NTMNumResults-2;
2257 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
2258 OldChainResultNo = NTMNumResults-1;
2260 // Call the underlying SelectionDAG routine to do the transmogrification. Note
2261 // that this deletes operands of the old node that become dead.
2262 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops);
2264 // MorphNodeTo can operate in two ways: if an existing node with the
2265 // specified operands exists, it can just return it. Otherwise, it
2266 // updates the node in place to have the requested operands.
2268 // If we updated the node in place, reset the node ID. To the isel,
2269 // this should be just like a newly allocated machine node.
2273 unsigned ResNumResults = Res->getNumValues();
2274 // Move the glue if needed.
2275 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 &&
2276 (unsigned)OldGlueResultNo != ResNumResults-1)
2277 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo),
2278 SDValue(Res, ResNumResults-1));
2280 if ((EmitNodeInfo & OPFL_GlueOutput) != 0)
2283 // Move the chain reference if needed.
2284 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 &&
2285 (unsigned)OldChainResultNo != ResNumResults-1)
2286 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo),
2287 SDValue(Res, ResNumResults-1));
2289 // Otherwise, no replacement happened because the node already exists. Replace
2290 // Uses of the old node with the new one.
2292 CurDAG->ReplaceAllUsesWith(Node, Res);
2297 /// CheckSame - Implements OP_CheckSame.
2298 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2299 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2301 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2302 // Accept if it is exactly the same as a previously recorded node.
2303 unsigned RecNo = MatcherTable[MatcherIndex++];
2304 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame");
2305 return N == RecordedNodes[RecNo].first;
2308 /// CheckChildSame - Implements OP_CheckChildXSame.
2309 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2310 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2312 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes,
2314 if (ChildNo >= N.getNumOperands())
2315 return false; // Match fails if out of range child #.
2316 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
2320 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate.
2321 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2322 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2323 const SelectionDAGISel &SDISel) {
2324 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]);
2327 /// CheckNodePredicate - Implements OP_CheckNodePredicate.
2328 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2329 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2330 const SelectionDAGISel &SDISel, SDNode *N) {
2331 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]);
2334 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2335 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2337 uint16_t Opc = MatcherTable[MatcherIndex++];
2338 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2339 return N->getOpcode() == Opc;
2342 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2343 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2344 SDValue N, const TargetLowering *TLI) {
2345 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2346 if (N.getValueType() == VT) return true;
2348 // Handle the case when VT is iPTR.
2349 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy();
2352 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2353 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2354 SDValue N, const TargetLowering *TLI, unsigned ChildNo) {
2355 if (ChildNo >= N.getNumOperands())
2356 return false; // Match fails if out of range child #.
2357 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI);
2360 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2361 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2363 return cast<CondCodeSDNode>(N)->get() ==
2364 (ISD::CondCode)MatcherTable[MatcherIndex++];
2367 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2368 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2369 SDValue N, const TargetLowering *TLI) {
2370 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2371 if (cast<VTSDNode>(N)->getVT() == VT)
2374 // Handle the case when VT is iPTR.
2375 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy();
2378 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2379 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2381 int64_t Val = MatcherTable[MatcherIndex++];
2383 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2385 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
2386 return C && C->getSExtValue() == Val;
2389 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2390 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2391 SDValue N, unsigned ChildNo) {
2392 if (ChildNo >= N.getNumOperands())
2393 return false; // Match fails if out of range child #.
2394 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
2397 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2398 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2399 SDValue N, const SelectionDAGISel &SDISel) {
2400 int64_t Val = MatcherTable[MatcherIndex++];
2402 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2404 if (N->getOpcode() != ISD::AND) return false;
2406 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2407 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
2410 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
2411 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
2412 SDValue N, const SelectionDAGISel &SDISel) {
2413 int64_t Val = MatcherTable[MatcherIndex++];
2415 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2417 if (N->getOpcode() != ISD::OR) return false;
2419 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
2420 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
2423 /// IsPredicateKnownToFail - If we know how and can do so without pushing a
2424 /// scope, evaluate the current node. If the current predicate is known to
2425 /// fail, set Result=true and return anything. If the current predicate is
2426 /// known to pass, set Result=false and return the MatcherIndex to continue
2427 /// with. If the current predicate is unknown, set Result=false and return the
2428 /// MatcherIndex to continue with.
2429 static unsigned IsPredicateKnownToFail(const unsigned char *Table,
2430 unsigned Index, SDValue N,
2432 const SelectionDAGISel &SDISel,
2433 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) {
2434 switch (Table[Index++]) {
2437 return Index-1; // Could not evaluate this predicate.
2438 case SelectionDAGISel::OPC_CheckSame:
2439 Result = !::CheckSame(Table, Index, N, RecordedNodes);
2441 case SelectionDAGISel::OPC_CheckChild0Same:
2442 case SelectionDAGISel::OPC_CheckChild1Same:
2443 case SelectionDAGISel::OPC_CheckChild2Same:
2444 case SelectionDAGISel::OPC_CheckChild3Same:
2445 Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
2446 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
2448 case SelectionDAGISel::OPC_CheckPatternPredicate:
2449 Result = !::CheckPatternPredicate(Table, Index, SDISel);
2451 case SelectionDAGISel::OPC_CheckPredicate:
2452 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode());
2454 case SelectionDAGISel::OPC_CheckOpcode:
2455 Result = !::CheckOpcode(Table, Index, N.getNode());
2457 case SelectionDAGISel::OPC_CheckType:
2458 Result = !::CheckType(Table, Index, N, SDISel.TLI);
2460 case SelectionDAGISel::OPC_CheckChild0Type:
2461 case SelectionDAGISel::OPC_CheckChild1Type:
2462 case SelectionDAGISel::OPC_CheckChild2Type:
2463 case SelectionDAGISel::OPC_CheckChild3Type:
2464 case SelectionDAGISel::OPC_CheckChild4Type:
2465 case SelectionDAGISel::OPC_CheckChild5Type:
2466 case SelectionDAGISel::OPC_CheckChild6Type:
2467 case SelectionDAGISel::OPC_CheckChild7Type:
2468 Result = !::CheckChildType(Table, Index, N, SDISel.TLI,
2470 SelectionDAGISel::OPC_CheckChild0Type);
2472 case SelectionDAGISel::OPC_CheckCondCode:
2473 Result = !::CheckCondCode(Table, Index, N);
2475 case SelectionDAGISel::OPC_CheckValueType:
2476 Result = !::CheckValueType(Table, Index, N, SDISel.TLI);
2478 case SelectionDAGISel::OPC_CheckInteger:
2479 Result = !::CheckInteger(Table, Index, N);
2481 case SelectionDAGISel::OPC_CheckChild0Integer:
2482 case SelectionDAGISel::OPC_CheckChild1Integer:
2483 case SelectionDAGISel::OPC_CheckChild2Integer:
2484 case SelectionDAGISel::OPC_CheckChild3Integer:
2485 case SelectionDAGISel::OPC_CheckChild4Integer:
2486 Result = !::CheckChildInteger(Table, Index, N,
2487 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
2489 case SelectionDAGISel::OPC_CheckAndImm:
2490 Result = !::CheckAndImm(Table, Index, N, SDISel);
2492 case SelectionDAGISel::OPC_CheckOrImm:
2493 Result = !::CheckOrImm(Table, Index, N, SDISel);
2501 /// FailIndex - If this match fails, this is the index to continue with.
2504 /// NodeStack - The node stack when the scope was formed.
2505 SmallVector<SDValue, 4> NodeStack;
2507 /// NumRecordedNodes - The number of recorded nodes when the scope was formed.
2508 unsigned NumRecordedNodes;
2510 /// NumMatchedMemRefs - The number of matched memref entries.
2511 unsigned NumMatchedMemRefs;
2513 /// InputChain/InputGlue - The current chain/glue
2514 SDValue InputChain, InputGlue;
2516 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty.
2517 bool HasChainNodesMatched, HasGlueResultNodesMatched;
2520 /// \\brief A DAG update listener to keep the matching state
2521 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
2522 /// change the DAG while matching. X86 addressing mode matcher is an example
2524 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
2526 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes;
2527 SmallVectorImpl<MatchScope> &MatchScopes;
2529 MatchStateUpdater(SelectionDAG &DAG,
2530 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN,
2531 SmallVectorImpl<MatchScope> &MS) :
2532 SelectionDAG::DAGUpdateListener(DAG),
2533 RecordedNodes(RN), MatchScopes(MS) { }
2535 void NodeDeleted(SDNode *N, SDNode *E) {
2536 // Some early-returns here to avoid the search if we deleted the node or
2537 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we
2538 // do, so it's unnecessary to update matching state at that point).
2539 // Neither of these can occur currently because we only install this
2540 // update listener during matching a complex patterns.
2541 if (!E || E->isMachineOpcode())
2543 // Performing linear search here does not matter because we almost never
2544 // run this code. You'd have to have a CSE during complex pattern
2546 for (auto &I : RecordedNodes)
2547 if (I.first.getNode() == N)
2550 for (auto &I : MatchScopes)
2551 for (auto &J : I.NodeStack)
2552 if (J.getNode() == N)
2558 SDNode *SelectionDAGISel::
2559 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
2560 unsigned TableSize) {
2561 // FIXME: Should these even be selected? Handle these cases in the caller?
2562 switch (NodeToMatch->getOpcode()) {
2565 case ISD::EntryToken: // These nodes remain the same.
2566 case ISD::BasicBlock:
2568 case ISD::RegisterMask:
2569 case ISD::HANDLENODE:
2570 case ISD::MDNODE_SDNODE:
2571 case ISD::TargetConstant:
2572 case ISD::TargetConstantFP:
2573 case ISD::TargetConstantPool:
2574 case ISD::TargetFrameIndex:
2575 case ISD::TargetExternalSymbol:
2576 case ISD::TargetBlockAddress:
2577 case ISD::TargetJumpTable:
2578 case ISD::TargetGlobalTLSAddress:
2579 case ISD::TargetGlobalAddress:
2580 case ISD::TokenFactor:
2581 case ISD::CopyFromReg:
2582 case ISD::CopyToReg:
2584 case ISD::LIFETIME_START:
2585 case ISD::LIFETIME_END:
2586 NodeToMatch->setNodeId(-1); // Mark selected.
2588 case ISD::AssertSext:
2589 case ISD::AssertZext:
2590 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
2591 NodeToMatch->getOperand(0));
2593 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
2594 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
2595 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);
2596 case ISD::UNDEF: return Select_UNDEF(NodeToMatch);
2599 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!");
2601 // Set up the node stack with NodeToMatch as the only node on the stack.
2602 SmallVector<SDValue, 8> NodeStack;
2603 SDValue N = SDValue(NodeToMatch, 0);
2604 NodeStack.push_back(N);
2606 // MatchScopes - Scopes used when matching, if a match failure happens, this
2607 // indicates where to continue checking.
2608 SmallVector<MatchScope, 8> MatchScopes;
2610 // RecordedNodes - This is the set of nodes that have been recorded by the
2611 // state machine. The second value is the parent of the node, or null if the
2612 // root is recorded.
2613 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
2615 // MatchedMemRefs - This is the set of MemRef's we've seen in the input
2617 SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
2619 // These are the current input chain and glue for use when generating nodes.
2620 // Various Emit operations change these. For example, emitting a copytoreg
2621 // uses and updates these.
2622 SDValue InputChain, InputGlue;
2624 // ChainNodesMatched - If a pattern matches nodes that have input/output
2625 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates
2626 // which ones they are. The result is captured into this list so that we can
2627 // update the chain results when the pattern is complete.
2628 SmallVector<SDNode*, 3> ChainNodesMatched;
2629 SmallVector<SDNode*, 3> GlueResultNodesMatched;
2631 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: ";
2632 NodeToMatch->dump(CurDAG);
2635 // Determine where to start the interpreter. Normally we start at opcode #0,
2636 // but if the state machine starts with an OPC_SwitchOpcode, then we
2637 // accelerate the first lookup (which is guaranteed to be hot) with the
2638 // OpcodeOffset table.
2639 unsigned MatcherIndex = 0;
2641 if (!OpcodeOffset.empty()) {
2642 // Already computed the OpcodeOffset table, just index into it.
2643 if (N.getOpcode() < OpcodeOffset.size())
2644 MatcherIndex = OpcodeOffset[N.getOpcode()];
2645 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n");
2647 } else if (MatcherTable[0] == OPC_SwitchOpcode) {
2648 // Otherwise, the table isn't computed, but the state machine does start
2649 // with an OPC_SwitchOpcode instruction. Populate the table now, since this
2650 // is the first time we're selecting an instruction.
2653 // Get the size of this case.
2654 unsigned CaseSize = MatcherTable[Idx++];
2656 CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
2657 if (CaseSize == 0) break;
2659 // Get the opcode, add the index to the table.
2660 uint16_t Opc = MatcherTable[Idx++];
2661 Opc |= (unsigned short)MatcherTable[Idx++] << 8;
2662 if (Opc >= OpcodeOffset.size())
2663 OpcodeOffset.resize((Opc+1)*2);
2664 OpcodeOffset[Opc] = Idx;
2668 // Okay, do the lookup for the first opcode.
2669 if (N.getOpcode() < OpcodeOffset.size())
2670 MatcherIndex = OpcodeOffset[N.getOpcode()];
2674 assert(MatcherIndex < TableSize && "Invalid index");
2676 unsigned CurrentOpcodeIndex = MatcherIndex;
2678 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++];
2681 // Okay, the semantics of this operation are that we should push a scope
2682 // then evaluate the first child. However, pushing a scope only to have
2683 // the first check fail (which then pops it) is inefficient. If we can
2684 // determine immediately that the first check (or first several) will
2685 // immediately fail, don't even bother pushing a scope for them.
2689 unsigned NumToSkip = MatcherTable[MatcherIndex++];
2690 if (NumToSkip & 128)
2691 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
2692 // Found the end of the scope with no match.
2693 if (NumToSkip == 0) {
2698 FailIndex = MatcherIndex+NumToSkip;
2700 unsigned MatcherIndexOfPredicate = MatcherIndex;
2701 (void)MatcherIndexOfPredicate; // silence warning.
2703 // If we can't evaluate this predicate without pushing a scope (e.g. if
2704 // it is a 'MoveParent') or if the predicate succeeds on this node, we
2705 // push the scope and evaluate the full predicate chain.
2707 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N,
2708 Result, *this, RecordedNodes);
2712 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at "
2713 << "index " << MatcherIndexOfPredicate
2714 << ", continuing at " << FailIndex << "\n");
2715 ++NumDAGIselRetries;
2717 // Otherwise, we know that this case of the Scope is guaranteed to fail,
2718 // move to the next case.
2719 MatcherIndex = FailIndex;
2722 // If the whole scope failed to match, bail.
2723 if (FailIndex == 0) break;
2725 // Push a MatchScope which indicates where to go if the first child fails
2727 MatchScope NewEntry;
2728 NewEntry.FailIndex = FailIndex;
2729 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end());
2730 NewEntry.NumRecordedNodes = RecordedNodes.size();
2731 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size();
2732 NewEntry.InputChain = InputChain;
2733 NewEntry.InputGlue = InputGlue;
2734 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty();
2735 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty();
2736 MatchScopes.push_back(NewEntry);
2739 case OPC_RecordNode: {
2740 // Remember this node, it may end up being an operand in the pattern.
2741 SDNode *Parent = nullptr;
2742 if (NodeStack.size() > 1)
2743 Parent = NodeStack[NodeStack.size()-2].getNode();
2744 RecordedNodes.push_back(std::make_pair(N, Parent));
2748 case OPC_RecordChild0: case OPC_RecordChild1:
2749 case OPC_RecordChild2: case OPC_RecordChild3:
2750 case OPC_RecordChild4: case OPC_RecordChild5:
2751 case OPC_RecordChild6: case OPC_RecordChild7: {
2752 unsigned ChildNo = Opcode-OPC_RecordChild0;
2753 if (ChildNo >= N.getNumOperands())
2754 break; // Match fails if out of range child #.
2756 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
2760 case OPC_RecordMemRef:
2761 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand());
2764 case OPC_CaptureGlueInput:
2765 // If the current node has an input glue, capture it in InputGlue.
2766 if (N->getNumOperands() != 0 &&
2767 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
2768 InputGlue = N->getOperand(N->getNumOperands()-1);
2771 case OPC_MoveChild: {
2772 unsigned ChildNo = MatcherTable[MatcherIndex++];
2773 if (ChildNo >= N.getNumOperands())
2774 break; // Match fails if out of range child #.
2775 N = N.getOperand(ChildNo);
2776 NodeStack.push_back(N);
2780 case OPC_MoveParent:
2781 // Pop the current node off the NodeStack.
2782 NodeStack.pop_back();
2783 assert(!NodeStack.empty() && "Node stack imbalance!");
2784 N = NodeStack.back();
2788 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
2791 case OPC_CheckChild0Same: case OPC_CheckChild1Same:
2792 case OPC_CheckChild2Same: case OPC_CheckChild3Same:
2793 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
2794 Opcode-OPC_CheckChild0Same))
2798 case OPC_CheckPatternPredicate:
2799 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break;
2801 case OPC_CheckPredicate:
2802 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this,
2806 case OPC_CheckComplexPat: {
2807 unsigned CPNum = MatcherTable[MatcherIndex++];
2808 unsigned RecNo = MatcherTable[MatcherIndex++];
2809 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat");
2811 // If target can modify DAG during matching, keep the matching state
2813 std::unique_ptr<MatchStateUpdater> MSU;
2814 if (ComplexPatternFuncMutatesDAG())
2815 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes,
2818 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second,
2819 RecordedNodes[RecNo].first, CPNum,
2824 case OPC_CheckOpcode:
2825 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
2829 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI))
2833 case OPC_SwitchOpcode: {
2834 unsigned CurNodeOpcode = N.getOpcode();
2835 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2838 // Get the size of this case.
2839 CaseSize = MatcherTable[MatcherIndex++];
2841 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2842 if (CaseSize == 0) break;
2844 uint16_t Opc = MatcherTable[MatcherIndex++];
2845 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
2847 // If the opcode matches, then we will execute this case.
2848 if (CurNodeOpcode == Opc)
2851 // Otherwise, skip over this case.
2852 MatcherIndex += CaseSize;
2855 // If no cases matched, bail out.
2856 if (CaseSize == 0) break;
2858 // Otherwise, execute the case we found.
2859 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart
2860 << " to " << MatcherIndex << "\n");
2864 case OPC_SwitchType: {
2865 MVT CurNodeVT = N.getSimpleValueType();
2866 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
2869 // Get the size of this case.
2870 CaseSize = MatcherTable[MatcherIndex++];
2872 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
2873 if (CaseSize == 0) break;
2875 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2876 if (CaseVT == MVT::iPTR)
2877 CaseVT = TLI->getPointerTy();
2879 // If the VT matches, then we will execute this case.
2880 if (CurNodeVT == CaseVT)
2883 // Otherwise, skip over this case.
2884 MatcherIndex += CaseSize;
2887 // If no cases matched, bail out.
2888 if (CaseSize == 0) break;
2890 // Otherwise, execute the case we found.
2891 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString()
2892 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n');
2895 case OPC_CheckChild0Type: case OPC_CheckChild1Type:
2896 case OPC_CheckChild2Type: case OPC_CheckChild3Type:
2897 case OPC_CheckChild4Type: case OPC_CheckChild5Type:
2898 case OPC_CheckChild6Type: case OPC_CheckChild7Type:
2899 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI,
2900 Opcode-OPC_CheckChild0Type))
2903 case OPC_CheckCondCode:
2904 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
2906 case OPC_CheckValueType:
2907 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI))
2910 case OPC_CheckInteger:
2911 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
2913 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
2914 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
2915 case OPC_CheckChild4Integer:
2916 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
2917 Opcode-OPC_CheckChild0Integer)) break;
2919 case OPC_CheckAndImm:
2920 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
2922 case OPC_CheckOrImm:
2923 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
2926 case OPC_CheckFoldableChainNode: {
2927 assert(NodeStack.size() != 1 && "No parent node");
2928 // Verify that all intermediate nodes between the root and this one have
2930 bool HasMultipleUses = false;
2931 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i)
2932 if (!NodeStack[i].hasOneUse()) {
2933 HasMultipleUses = true;
2936 if (HasMultipleUses) break;
2938 // Check to see that the target thinks this is profitable to fold and that
2939 // we can fold it without inducing cycles in the graph.
2940 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2942 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
2943 NodeToMatch, OptLevel,
2944 true/*We validate our own chains*/))
2949 case OPC_EmitInteger: {
2950 MVT::SimpleValueType VT =
2951 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2952 int64_t Val = MatcherTable[MatcherIndex++];
2954 Val = GetVBR(Val, MatcherTable, MatcherIndex);
2955 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2956 CurDAG->getTargetConstant(Val, VT), nullptr));
2959 case OPC_EmitRegister: {
2960 MVT::SimpleValueType VT =
2961 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2962 unsigned RegNo = MatcherTable[MatcherIndex++];
2963 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2964 CurDAG->getRegister(RegNo, VT), nullptr));
2967 case OPC_EmitRegister2: {
2968 // For targets w/ more than 256 register names, the register enum
2969 // values are stored in two bytes in the matcher table (just like
2971 MVT::SimpleValueType VT =
2972 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
2973 unsigned RegNo = MatcherTable[MatcherIndex++];
2974 RegNo |= MatcherTable[MatcherIndex++] << 8;
2975 RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
2976 CurDAG->getRegister(RegNo, VT), nullptr));
2980 case OPC_EmitConvertToTarget: {
2981 // Convert from IMM/FPIMM to target version.
2982 unsigned RecNo = MatcherTable[MatcherIndex++];
2983 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget");
2984 SDValue Imm = RecordedNodes[RecNo].first;
2986 if (Imm->getOpcode() == ISD::Constant) {
2987 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
2988 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true);
2989 } else if (Imm->getOpcode() == ISD::ConstantFP) {
2990 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
2991 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true);
2994 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second));
2998 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
2999 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1
3000 // These are space-optimized forms of OPC_EmitMergeInputChains.
3001 assert(!InputChain.getNode() &&
3002 "EmitMergeInputChains should be the first chain producing node");
3003 assert(ChainNodesMatched.empty() &&
3004 "Should only have one EmitMergeInputChains per match");
3006 // Read all of the chained nodes.
3007 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1;
3008 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3009 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3011 // FIXME: What if other value results of the node have uses not matched
3013 if (ChainNodesMatched.back() != NodeToMatch &&
3014 !RecordedNodes[RecNo].first.hasOneUse()) {
3015 ChainNodesMatched.clear();
3019 // Merge the input chains if they are not intra-pattern references.
3020 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3022 if (!InputChain.getNode())
3023 break; // Failed to merge.
3027 case OPC_EmitMergeInputChains: {
3028 assert(!InputChain.getNode() &&
3029 "EmitMergeInputChains should be the first chain producing node");
3030 // This node gets a list of nodes we matched in the input that have
3031 // chains. We want to token factor all of the input chains to these nodes
3032 // together. However, if any of the input chains is actually one of the
3033 // nodes matched in this pattern, then we have an intra-match reference.
3034 // Ignore these because the newly token factored chain should not refer to
3036 unsigned NumChains = MatcherTable[MatcherIndex++];
3037 assert(NumChains != 0 && "Can't TF zero chains");
3039 assert(ChainNodesMatched.empty() &&
3040 "Should only have one EmitMergeInputChains per match");
3042 // Read all of the chained nodes.
3043 for (unsigned i = 0; i != NumChains; ++i) {
3044 unsigned RecNo = MatcherTable[MatcherIndex++];
3045 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains");
3046 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3048 // FIXME: What if other value results of the node have uses not matched
3050 if (ChainNodesMatched.back() != NodeToMatch &&
3051 !RecordedNodes[RecNo].first.hasOneUse()) {
3052 ChainNodesMatched.clear();
3057 // If the inner loop broke out, the match fails.
3058 if (ChainNodesMatched.empty())
3061 // Merge the input chains if they are not intra-pattern references.
3062 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
3064 if (!InputChain.getNode())
3065 break; // Failed to merge.
3070 case OPC_EmitCopyToReg: {
3071 unsigned RecNo = MatcherTable[MatcherIndex++];
3072 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg");
3073 unsigned DestPhysReg = MatcherTable[MatcherIndex++];
3075 if (!InputChain.getNode())
3076 InputChain = CurDAG->getEntryNode();
3078 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
3079 DestPhysReg, RecordedNodes[RecNo].first,
3082 InputGlue = InputChain.getValue(1);
3086 case OPC_EmitNodeXForm: {
3087 unsigned XFormNo = MatcherTable[MatcherIndex++];
3088 unsigned RecNo = MatcherTable[MatcherIndex++];
3089 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
3090 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
3091 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
3096 case OPC_MorphNodeTo: {
3097 uint16_t TargetOpc = MatcherTable[MatcherIndex++];
3098 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8;
3099 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++];
3100 // Get the result VT list.
3101 unsigned NumVTs = MatcherTable[MatcherIndex++];
3102 SmallVector<EVT, 4> VTs;
3103 for (unsigned i = 0; i != NumVTs; ++i) {
3104 MVT::SimpleValueType VT =
3105 (MVT::SimpleValueType)MatcherTable[MatcherIndex++];
3106 if (VT == MVT::iPTR)
3107 VT = TLI->getPointerTy().SimpleTy;
3111 if (EmitNodeInfo & OPFL_Chain)
3112 VTs.push_back(MVT::Other);
3113 if (EmitNodeInfo & OPFL_GlueOutput)
3114 VTs.push_back(MVT::Glue);
3116 // This is hot code, so optimize the two most common cases of 1 and 2
3119 if (VTs.size() == 1)
3120 VTList = CurDAG->getVTList(VTs[0]);
3121 else if (VTs.size() == 2)
3122 VTList = CurDAG->getVTList(VTs[0], VTs[1]);
3124 VTList = CurDAG->getVTList(VTs);
3126 // Get the operand list.
3127 unsigned NumOps = MatcherTable[MatcherIndex++];
3128 SmallVector<SDValue, 8> Ops;
3129 for (unsigned i = 0; i != NumOps; ++i) {
3130 unsigned RecNo = MatcherTable[MatcherIndex++];
3132 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3134 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode");
3135 Ops.push_back(RecordedNodes[RecNo].first);
3138 // If there are variadic operands to add, handle them now.
3139 if (EmitNodeInfo & OPFL_VariadicInfo) {
3140 // Determine the start index to copy from.
3141 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo);
3142 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0;
3143 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy &&
3144 "Invalid variadic node");
3145 // Copy all of the variadic operands, not including a potential glue
3147 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
3149 SDValue V = NodeToMatch->getOperand(i);
3150 if (V.getValueType() == MVT::Glue) break;
3155 // If this has chain/glue inputs, add them.
3156 if (EmitNodeInfo & OPFL_Chain)
3157 Ops.push_back(InputChain);
3158 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr)
3159 Ops.push_back(InputGlue);
3162 SDNode *Res = nullptr;
3163 if (Opcode != OPC_MorphNodeTo) {
3164 // If this is a normal EmitNode command, just create the new node and
3165 // add the results to the RecordedNodes list.
3166 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
3169 // Add all the non-glue/non-chain results to the RecordedNodes list.
3170 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
3171 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
3172 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
3176 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) {
3177 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo);
3179 // NodeToMatch was eliminated by CSE when the target changed the DAG.
3180 // We will visit the equivalent node later.
3181 DEBUG(dbgs() << "Node was eliminated by CSE\n");
3185 // If the node had chain/glue results, update our notion of the current
3187 if (EmitNodeInfo & OPFL_GlueOutput) {
3188 InputGlue = SDValue(Res, VTs.size()-1);
3189 if (EmitNodeInfo & OPFL_Chain)
3190 InputChain = SDValue(Res, VTs.size()-2);
3191 } else if (EmitNodeInfo & OPFL_Chain)
3192 InputChain = SDValue(Res, VTs.size()-1);
3194 // If the OPFL_MemRefs glue is set on this node, slap all of the
3195 // accumulated memrefs onto it.
3197 // FIXME: This is vastly incorrect for patterns with multiple outputs
3198 // instructions that access memory and for ComplexPatterns that match
3200 if (EmitNodeInfo & OPFL_MemRefs) {
3201 // Only attach load or store memory operands if the generated
3202 // instruction may load or store.
3203 const MCInstrDesc &MCID = TII->get(TargetOpc);
3204 bool mayLoad = MCID.mayLoad();
3205 bool mayStore = MCID.mayStore();
3207 unsigned NumMemRefs = 0;
3208 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3209 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3210 if ((*I)->isLoad()) {
3213 } else if ((*I)->isStore()) {
3221 MachineSDNode::mmo_iterator MemRefs =
3222 MF->allocateMemRefsArray(NumMemRefs);
3224 MachineSDNode::mmo_iterator MemRefsPos = MemRefs;
3225 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I =
3226 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) {
3227 if ((*I)->isLoad()) {
3230 } else if ((*I)->isStore()) {
3238 cast<MachineSDNode>(Res)
3239 ->setMemRefs(MemRefs, MemRefs + NumMemRefs);
3243 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created")
3244 << " node: "; Res->dump(CurDAG); dbgs() << "\n");
3246 // If this was a MorphNodeTo then we're completely done!
3247 if (Opcode == OPC_MorphNodeTo) {
3248 // Update chain and glue uses.
3249 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3250 InputGlue, GlueResultNodesMatched, true);
3257 case OPC_MarkGlueResults: {
3258 unsigned NumNodes = MatcherTable[MatcherIndex++];
3260 // Read and remember all the glue-result nodes.
3261 for (unsigned i = 0; i != NumNodes; ++i) {
3262 unsigned RecNo = MatcherTable[MatcherIndex++];
3264 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex);
3266 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults");
3267 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode());
3272 case OPC_CompleteMatch: {
3273 // The match has been completed, and any new nodes (if any) have been
3274 // created. Patch up references to the matched dag to use the newly
3276 unsigned NumResults = MatcherTable[MatcherIndex++];
3278 for (unsigned i = 0; i != NumResults; ++i) {
3279 unsigned ResSlot = MatcherTable[MatcherIndex++];
3281 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex);
3283 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch");
3284 SDValue Res = RecordedNodes[ResSlot].first;
3286 assert(i < NodeToMatch->getNumValues() &&
3287 NodeToMatch->getValueType(i) != MVT::Other &&
3288 NodeToMatch->getValueType(i) != MVT::Glue &&
3289 "Invalid number of results to complete!");
3290 assert((NodeToMatch->getValueType(i) == Res.getValueType() ||
3291 NodeToMatch->getValueType(i) == MVT::iPTR ||
3292 Res.getValueType() == MVT::iPTR ||
3293 NodeToMatch->getValueType(i).getSizeInBits() ==
3294 Res.getValueType().getSizeInBits()) &&
3295 "invalid replacement");
3296 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res);
3299 // If the root node defines glue, add it to the glue nodes to update list.
3300 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue)
3301 GlueResultNodesMatched.push_back(NodeToMatch);
3303 // Update chain and glue uses.
3304 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched,
3305 InputGlue, GlueResultNodesMatched, false);
3307 assert(NodeToMatch->use_empty() &&
3308 "Didn't replace all uses of the node?");
3310 // FIXME: We just return here, which interacts correctly with SelectRoot
3311 // above. We should fix this to not return an SDNode* anymore.
3316 // If the code reached this point, then the match failed. See if there is
3317 // another child to try in the current 'Scope', otherwise pop it until we
3318 // find a case to check.
3319 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n");
3320 ++NumDAGIselRetries;
3322 if (MatchScopes.empty()) {
3323 CannotYetSelect(NodeToMatch);
3327 // Restore the interpreter state back to the point where the scope was
3329 MatchScope &LastScope = MatchScopes.back();
3330 RecordedNodes.resize(LastScope.NumRecordedNodes);
3332 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end());
3333 N = NodeStack.back();
3335 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size())
3336 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs);
3337 MatcherIndex = LastScope.FailIndex;
3339 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n");
3341 InputChain = LastScope.InputChain;
3342 InputGlue = LastScope.InputGlue;
3343 if (!LastScope.HasChainNodesMatched)
3344 ChainNodesMatched.clear();
3345 if (!LastScope.HasGlueResultNodesMatched)
3346 GlueResultNodesMatched.clear();
3348 // Check to see what the offset is at the new MatcherIndex. If it is zero
3349 // we have reached the end of this scope, otherwise we have another child
3350 // in the current scope to try.
3351 unsigned NumToSkip = MatcherTable[MatcherIndex++];
3352 if (NumToSkip & 128)
3353 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex);
3355 // If we have another child in this scope to match, update FailIndex and
3357 if (NumToSkip != 0) {
3358 LastScope.FailIndex = MatcherIndex+NumToSkip;
3362 // End of this scope, pop it and try the next child in the containing
3364 MatchScopes.pop_back();
3371 void SelectionDAGISel::CannotYetSelect(SDNode *N) {
3373 raw_string_ostream Msg(msg);
3374 Msg << "Cannot select: ";
3376 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN &&
3377 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN &&
3378 N->getOpcode() != ISD::INTRINSIC_VOID) {
3379 N->printrFull(Msg, CurDAG);
3380 Msg << "\nIn function: " << MF->getName();
3382 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
3384 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
3385 if (iid < Intrinsic::num_intrinsics)
3386 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid);
3387 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
3388 Msg << "target intrinsic %" << TII->getName(iid);
3390 Msg << "unknown intrinsic #" << iid;
3392 report_fatal_error(Msg.str());
3395 char SelectionDAGISel::ID = 0;